Functional safety test method, system and apparatus for integrated circuit, and storage medium

Abstract

A functional safety test method, system and apparatus for an integrated circuit, and a storage medium. The method comprises: determining each first unit to be tested in a first logic circuit and a second unit to be tested in a second logic circuit that corresponds to each first unit to be tested (501); performing a functional safety test on the first logic circuit and the second logic circuit, so as to obtain a consistency test result of first test data outputted by each first unit to be tested and second test data outputted by each corresponding second unit to be tested (502); on the basis of the consistency test result, determining the current test coverage rate of an integrated circuit (503); in response to the current test coverage rate and a target test coverage rate not meeting a preset numerical relationship, adjusting each first unit to be tested in the first logic circuit and each second unit to be tested in the second logic circuit, so as to obtain a first target logic circuit and a second target logic circuit (504); and on the basis of the obtained first target logic circuit and second target logic circuit, determining a target integrated circuit corresponding to the target test coverage rate (505). A target integrated circuit is obtained by means of adjusting each first test unit in a first logic circuit and each second test unit in a second logic circuit, so that the design is relatively simple, and thus the resource development costs can be effectively reduced.

Description

Functional safety testing methods, systems, devices, and storage media for integrated circuits

[0001] This disclosure claims priority to Chinese Patent Application No. 202410707778.X, filed on May 31, 2024, entitled “Functional Safety Testing Method, System, Apparatus and Storage Medium for Integrated Circuits”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of functional safety (FuSa) technology, and in particular to a method, system, apparatus and storage medium for functional safety testing of integrated circuits. Background Technology

[0003] Currently, in FuSa safety protection of automotive integrated circuits (such as automotive system-on-chip (SOC) or neural network processors), the dual-core lockstep scheme has become an essential protection scheme for FuSa safety protection because it is applicable to all logic circuits in integrated circuits.

[0004] However, the Dual Core approach requires replicating the entire logic circuit to be protected to achieve 100% functional safety coverage. This means the Dual Core approach incurs twice the circuit area cost for functional safety testing of a single circuit, resulting in significant area overhead. To reduce this overhead, when using the Dual Core approach for functional safety testing of integrated circuits with lower safety requirements (e.g., target functional safety coverage less than 100%), the integrated circuit can be redesigned. Multiple replicated logic units corresponding to the target test coverage can be added to each original logic circuit to be protected (in some examples, this can be achieved by replicating the units under test in the original logic circuit) to obtain the target integrated circuit with the target test coverage. However, this redesign process requires repeated design iterations and trade-offs to determine the multiple replicated logic units corresponding to the target test coverage, consuming significant human resources and resulting in high development costs. Summary of the Invention

[0005] Typically, when using the Dual Core approach to perform functional safety testing on integrated circuits with low safety requirements, it is necessary to repeatedly redesign each logic circuit to be protected in the integrated circuit, resulting in high human development costs.

[0006] To address the aforementioned technical problems, this disclosure provides a testing method for an integrated circuit, the integrated circuit including a first logic circuit and a second logic circuit for performing functional safety testing on the first logic circuit, the testing method including:

[0007] Determine at least one first unit under test in the first logic circuit and a second unit under test in the second logic circuit corresponding to each first unit under test;

[0008] Functional safety tests are performed on the first logic circuit and the second logic circuit to obtain the consistency test results of the first test data output by each first unit under test and the corresponding second test data output by each second unit under test.

[0009] Based on the conformance test results, determine the current test coverage of the integrated circuit;

[0010] In response to the fact that the current test coverage does not meet the preset numerical relationship with the target test coverage, the first unit under test in the first logic circuit and the second unit under test in the second logic circuit are adjusted to obtain the first target logic circuit and the second target logic circuit.

[0011] Based on the first target logic circuit and the second target logic circuit, the target integrated circuit corresponding to the target test coverage is determined.

[0012] A second aspect of this disclosure provides a functional safety test system for an integrated circuit, including an integrated circuit and test equipment for performing functional safety tests on the integrated circuit; the integrated circuit includes a first logic circuit, a second logic circuit, and a comparator;

[0013] A test device for identifying at least one first unit under test in a first logic circuit and a second unit under test in a second logic circuit corresponding to each first unit under test;

[0014] A first logic circuit, coupled to a comparator, is used to output first test data to the comparator based on at least one first unit under test in the first logic circuit;

[0015] The second logic circuit, coupled to the comparator, is used to output second test data to the comparator based on at least one second unit under test in the second logic circuit;

[0016] A comparator, coupled to the test equipment, is used to output a consistency test result to the test equipment based on the first test data and the second test data;

[0017] The testing equipment is used to determine the current test coverage of an integrated circuit based on the consistency test results; in response to the current test coverage not meeting the preset numerical relationship with the target test coverage, the first unit under test in the first logic circuit and the second unit under test in the second logic circuit are adjusted to obtain the first target logic circuit and the second target logic circuit; based on the first target logic circuit and the second target logic circuit, the target integrated circuit corresponding to the target test coverage is determined.

[0018] A third aspect of this disclosure provides a functional safety testing apparatus for an integrated circuit, the integrated circuit including a first logic circuit and a second logic circuit for performing functional safety testing on the first logic circuit, the functional safety testing apparatus comprising:

[0019] The first determining module is used to determine at least one first unit under test in the first logic circuit and a second unit under test in the second logic circuit corresponding to each first unit under test.

[0020] The functional safety test module is used to perform functional safety tests on the first logic circuit and the second logic circuit, and obtain the consistency test results of the first test data output by each first unit under test and the corresponding second test data output by each second unit under test.

[0021] The second determination module is used to determine the current test coverage of the integrated circuit based on the consistency test results;

[0022] The adjustment module is used to adjust the first unit under test in the first logic circuit and the second unit under test in the second logic circuit in response to the fact that the current test coverage and the target test coverage do not meet the preset numerical relationship, so as to obtain the first target logic circuit and the second target logic circuit.

[0023] The third determining module is used to determine the target integrated circuit corresponding to the target test coverage based on the first target logic circuit and the second target logic circuit.

[0024] A fourth aspect of this disclosure provides a computer-readable storage medium storing a computer program for performing a test method for an integrated circuit according to the first aspect described above.

[0025] In this embodiment, functional safety testing is performed on the first logic circuit and the second logic circuit to obtain consistency test results of the first test data output by each first unit under test in the first logic circuit and the second test data output by each second unit under test in the second logic circuit. Therefore, the consistency test results are related to each first unit under test in the first logic circuit and each second unit under test in the second logic circuit. The current test coverage of the integrated circuit determined based on the consistency test results is also related to each first unit under test in the first logic circuit and each second unit under test in the second logic circuit. Furthermore, when the current test coverage does not meet the preset numerical relationship with the target test coverage, adjusting the first test unit in the first logic circuit and the second test unit in the second logic circuit can accurately adjust the current test coverage to the target test coverage, thus obtaining the target integrated circuit corresponding to the target test coverage. Simultaneously, since adjusting the first test unit in the first logic circuit and the second test unit in the second logic circuit is relatively simple and does not require redesigning the integrated circuit, it can effectively save human development costs. Attached Figure Description

[0026] Figure 1 is a schematic diagram of the structure of an integrated circuit suitable for a dual-core scheme with high security requirements, provided by an exemplary embodiment of this disclosure.

[0027] Figure 2 is a schematic diagram of the structure of an integrated circuit suitable for a dual-core scheme with low security requirements, provided by an exemplary embodiment of this disclosure.

[0028] Figure 3 is a schematic diagram of the structure of a functional safety test system for an integrated circuit provided in an exemplary embodiment of this disclosure.

[0029] Figure 4 is a schematic diagram of the structure of another functional safety test system for integrated circuits provided in an exemplary embodiment of this disclosure.

[0030] Figure 5 is a flowchart illustrating a functional safety testing method for an integrated circuit provided in an exemplary embodiment of this disclosure.

[0031] Figure 6 is a flowchart illustrating another functional safety testing method for integrated circuits provided in an exemplary embodiment of this disclosure.

[0032] Figure 7 is a flowchart illustrating another functional safety testing method for an integrated circuit provided by an exemplary embodiment of this disclosure.

[0033] Figure 8 is a flowchart illustrating another functional safety testing method for an integrated circuit provided by an exemplary embodiment of this disclosure.

[0034] Figure 9 is a flowchart illustrating another functional safety testing method for an integrated circuit provided by an exemplary embodiment of this disclosure.

[0035] Figure 10 is a flowchart illustrating another functional safety testing method for an integrated circuit provided in an exemplary embodiment of this disclosure.

[0036] Figure 11 is a schematic diagram of the structure of another functional safety test system for integrated circuits provided in an exemplary embodiment of the present disclosure.

[0037] Figure 12 is a schematic diagram of the structure of another functional safety test system for integrated circuits provided in an exemplary embodiment of this disclosure.

[0038] Figure 13 is a schematic diagram of the structure of another functional safety test system for integrated circuits provided in an exemplary embodiment of the present disclosure.

[0039] Figure 14 is a schematic diagram of the structure of a functional safety testing device for an integrated circuit provided in an exemplary embodiment of the present disclosure.

[0040] Figure 15 is a schematic diagram of the structure of another functional safety testing device for an integrated circuit provided in an exemplary embodiment of the present disclosure.

[0041] Figure 16 is a schematic diagram of the structure of another functional safety testing device for an integrated circuit provided in an exemplary embodiment of the present disclosure.

[0042] Figure 17 is a schematic diagram of the structure of another functional safety testing device for an integrated circuit provided in an exemplary embodiment of the present disclosure.

[0043] Figure 18 is a schematic diagram of the structure of another functional safety testing device for an integrated circuit provided in an exemplary embodiment of the present disclosure.

[0044] Figure 19 is a structural schematic diagram of another functional safety testing device for an integrated circuit provided in an exemplary embodiment of the present disclosure.

[0045] Figure 20 is a schematic diagram of the structure of another functional safety testing device for an integrated circuit provided in an exemplary embodiment of the present disclosure.

[0046] Figure 21 is a schematic diagram of the structure of an electronic device provided by an exemplary embodiment of the present disclosure. Detailed Implementation

[0047] To explain this disclosure, exemplary embodiments of the disclosure will now be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the disclosure, and not all of them. It should be understood that the disclosure is not limited to exemplary embodiments.

[0048] It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of this disclosure.

[0049] Application Overview

[0050] Currently, FuSa (Full Satiety) is a key capability in the automotive-grade field and has been widely used in automotive integrated circuits. Typically, FuSa protection schemes for automotive integrated circuits include a dual-core scheme applicable to all logic circuits within the integrated circuit. The dual-core scheme requires replicating the entire logic circuit to be protected, enabling testing of the entire protected logic circuit, i.e., achieving 100% functional safety testing coverage.

[0051] Since all the logic circuits to be protected in the integrated circuit are in normal working condition when using the Dual-core scheme for functional safety testing, the coupling relationship of each original logic circuit (the logic circuit to be protected) in the integrated circuit is fixed (for example, the output of each original logic circuit is coupled to other corresponding logic circuits, that is, each original logic circuit can drive the next stage load circuit). To perform functional safety testing on the integrated circuit, only a test circuit for functional safety testing needs to be added according to the safety level requirements, and the corresponding coupling needs to be established. In this embodiment, the test circuit may include a replicated original logic circuit (replicated logic circuit), a replicated logic unit (replicated logic unit), and a comparator.

[0052] Since the coupling relationships of the original logic circuits in an integrated circuit do not change with the functional safety testing of the safety level, the following embodiments neither illustrate nor describe the coupling relationships of the original logic circuits. This disclosure does not limit the coupling relationships of the original logic circuits in an integrated circuit; the coupling relationships of the original logic circuits in an integrated circuit can be determined according to the actual function of the integrated circuit.

[0053] Figure 1 is a schematic diagram of the structure of an integrated circuit suitable for a dual-core scheme with high security requirements, provided by an exemplary embodiment of the present disclosure. As shown in Figure 1, the integrated circuit 10 may include a logic circuit 11 (the logic circuit to be protected), a copied logic circuit 12 obtained by copying the logic circuit 11, and a comparator 13 coupled to both the logic circuit 11 and the copied logic circuit 12.

[0054] The logic circuit 11 may include a first logic unit 111 to a fourth logic unit 114; the replication logic circuit 12 may include a first replication logic unit 121 to a fourth replication logic unit 124 corresponding to each logic unit in the first logic unit 111 to the fourth logic unit 114.

[0055] The first input terminal of comparator 13 is coupled to the output terminals of the first logic unit 111 to the fourth logic unit 114, and the second input terminal of comparator 13 is coupled to the output terminals of the first copy logic unit 121 to the fourth copy logic unit 124. Comparator 13 is used to receive the first logic data to the fourth logic data output by the first logic unit 111 to the fourth logic unit 114 respectively, and the first copy logic data to the fourth copy logic data output by the first copy logic unit 121 to the fourth copy logic unit 124 respectively, compare each logic data in the first logic data to the fourth logic data with the corresponding copy logic data in the first copy logic data to the fourth copy logic data, obtain the comparison result, and send the comparison result to the operating system through the output terminal.

[0056] In this embodiment of the disclosure, the coupling relationship of each logic unit (in some examples, it may include the coupling relationship between each logic unit and between each logic unit and other logic units outside of the logic circuit 11) is exactly the same as the coupling relationship of each replicated logic unit in the replicated logic circuit 12.

[0057] In the technical solution of this disclosure embodiment, when performing functional safety testing on the integrated circuit 10 with high safety requirements using the Dual core scheme, the entire logic circuit 11 is copied. Therefore, the area is doubled compared to the original area, resulting in a large area overhead.

[0058] To reduce area overhead, when using the Dual Core approach for functional safety testing of integrated circuits with low safety requirements (safety levels below 100% test coverage), multiple replicated logic units corresponding to the target test coverage can be added to each original logic circuit to be protected. In other words, the target integrated circuit with the target test coverage can be obtained by redesigning the integrated circuit.

[0059] Figure 2 is a schematic diagram of an integrated circuit structure suitable for a dual-core scheme with low security requirements, provided by an exemplary embodiment of this disclosure. As shown in Figure 2, the integrated circuit 20 may include a new logic circuit 21 and a comparator 22 coupled to the new logic circuit 21. The new logic circuit 21 may include the logic circuit 11 shown in Figure 1 and at least one replicated logic unit 23 (a replicated unit under test). This embodiment of the disclosure exemplifies the use of at least one replicated logic unit 23 including a first replicated logic unit 121 corresponding to a first logic unit 111 and a second replicated logic unit 122 corresponding to a second logic unit 112.

[0060] The outputs of the first logic unit 111 and the second logic unit 112 are both coupled to the first input of the comparator 22; the outputs of the first copy logic unit 121 and the second copy logic unit 122 are both coupled to the second input of the comparator 22; the output of the comparator 22 is used to send the comparison result to the operating system.

[0061] In this embodiment of the present disclosure, each copy logic unit in at least one copy logic unit 23 has the same input coupling relationship with the corresponding logic unit, that is, each copy logic unit has the same input data as the corresponding logic unit in the original logic circuit, but the output of each copy logic unit is not coupled to other logic units, that is, the output of each copy logic unit does not drive the load circuit.

[0062] The implementation process of the Dual core solution with low security requirements will be explained below with reference to Figure 2.

[0063] First, the first logic unit 111 and the second logic unit 112 output the first logic test data and the second logic test data to the comparator 22, respectively; the first copy logic unit 121 and the second copy logic unit 122 output the first copy logic test data and the second copy logic test data to the comparator 22, respectively.

[0064] Next, comparator 22 compares the first logical test data with the first copy logical test data and the second logical test data with the second copy logical test data to obtain the comparison result, and sends the comparison result to the operating system.

[0065] Next, the operating system calculates the current test coverage of integrated circuit 20 based on the comparison results.

[0066] Finally, when the designers determine that the current test coverage is not equal to the target test coverage corresponding to the target security level, they redesign the integrated circuit 20 based on the coverage difference between the current test coverage and the target test coverage. That is, based on the logic circuit 11, they repeatedly redesign and iterate, and select at least one copy logic unit in the copy logic unit 23 to obtain multiple copy logic units corresponding to the target coverage, which is the target integrated circuit corresponding to the target test coverage.

[0067] In the technical solution of this disclosure, when performing functional safety testing on a logic circuit with low safety requirements using the Dual Core approach, only a portion of the logic units (test units) in the original logic circuit to be protected are copied, thus reducing area overhead. However, this process of redesigning the integrated circuit requires repeated design iterations and trade-offs to determine the multiple copied logic units corresponding to the target test coverage, resulting in a significant consumption of human resources.

[0068] Based on the above-mentioned technical problems, this disclosure provides a functional safety testing method for integrated circuits. The method includes: determining the current test coverage of the integrated circuit based on the consistency test results of the first test data output by each first unit under test in the first logic circuit and the second test data output by each corresponding second unit under test in the second logic circuit; adjusting the first unit under test in the first logic circuit and the second unit under test in the second logic circuit based on the difference between the current test coverage and the target test coverage; and finally determining the target integrated circuit corresponding to the target test coverage based on the obtained first target logic circuit and second target logic circuit.

[0069] Since the current test coverage of the integrated circuit is related to each first unit under test in the first logic circuit and each second unit under test in the second logic circuit, when the current test coverage and the target test coverage do not meet the preset numerical relationship, adjusting the first test unit in the first logic circuit and the second test unit in the second logic circuit can accurately adjust the current test coverage to the target test coverage, thereby obtaining the target integrated circuit. Furthermore, since adjusting the first test unit in the first logic circuit and the second test unit in the second logic circuit is relatively simple and does not require redesigning the integrated circuit, it can effectively save on human development costs.

[0070] Exemplary System

[0071] Figure 3 is a schematic diagram of the structure of a functional safety test system for an integrated circuit provided in an exemplary embodiment of this disclosure. As shown in Figure 3, the functional safety test system 30 includes an integrated circuit 31 and a test device 32 for performing functional safety tests. The integrated circuit 31 may include a logic circuit 11, an adjustable proportional logic circuit 31, and a comparator 33 as shown in Figure 1. The adjustable proportional logic circuit 31 may include a first replication logic unit 121 to a fourth replication logic unit 124 as shown in Figure 1.

[0072] In this embodiment, the output of at least one logic unit in logic circuit 11 is coupled to the first input of comparator 33, and the output of at least one corresponding copy logic unit in adjustable proportional logic circuit 31 is coupled to the second input of comparator 33. The output of comparator 33 is used to output the comparison result. This embodiment uses the example where the outputs of the first logic unit 111 and the second logic unit 112 in logic circuit 11 are both coupled to the first input of comparator 33, and the outputs of the first copy logic unit 121 and the second copy logic unit 122 are both coupled to the second input of comparator 33 for illustrative purposes.

[0073] In this embodiment of the disclosure, the input coupling relationship between each copy logic unit and the corresponding logic unit in the adjustable proportional logic circuit 31 is the same, that is, the input data of each copy logic unit is the same as that of the corresponding logic unit in the original logic circuit, but the output of each copy logic unit is not coupled to other logic units, that is, the output of each copy logic unit does not drive the load circuit.

[0074] In this embodiment of the disclosure, the test device 32 can be a personal computer or industrial control computer with electronic design automation (EDA) software test tools installed.

[0075] Based on the embodiment shown in Figure 3 above, this disclosure provides another functional safety test system for integrated circuits. As shown in Figure 4, the integrated circuit 31 in this functional safety test system 30 further includes a hash generator 34. The hash generator 34 may include a first hash generator 341 and a second hash generator 342.

[0076] The outputs of the first logic unit 111 and the second logic unit 112 are both coupled to the input of the first hash generator 341; the output of the first hash generator 341 is coupled to the first input of the comparator 33. The outputs of the first replication logic unit 121 and the second replication logic unit 122 are both coupled to the input of the second hash generator 342; the output of the second hash generator 342 is coupled to the second input of the comparator 33.

[0077] In some embodiments of this disclosure, both the first hash generator 341 and the second hash generator 342 may include at least one hash generation module. The number of hash generation modules in the first hash generator 341 and / or the second hash generator 342 can be determined based on the bit width of the hash generation module, the number and bit width of the first and second test units included in the logic circuit 11 and / or the adjustable proportional logic circuit 31. This disclosure does not limit the number of hash generation modules included in the first hash generator 341 and the second hash generator 342. This disclosure provides an illustrative example using the example of each hash generator 341 and the second hash generator 342 including one hash generation module.

[0078] Exemplary methods

[0079] Figure 5 is a flowchart illustrating a functional safety testing method for an integrated circuit according to an exemplary embodiment of this disclosure. This functional safety testing method for an integrated circuit can be applied to the functional safety testing system 30 shown in Figures 3 and / or 4. As shown in Figure 5, the functional safety testing method for an integrated circuit may include the following steps 501 to 505.

[0080] Step 501: Determine at least one first unit under test in the first logic circuit and a second unit under test in the second logic circuit corresponding to each first unit under test.

[0081] For example, the first logic circuit may be a raw logic circuit in an integrated circuit, and the output terminals of each logic unit included in the first logic circuit are all coupled to the corresponding logic unit. The first unit under test may be a raw logic unit in the raw logic circuit that needs to be functionally tested. In some examples, referring to FIG3 or FIG4, the first logic circuit may be logic circuit 11, and the first logic unit 111 to the second logic unit 114 in logic circuit 11 are all coupled to the corresponding logic unit (not shown in FIG3 or FIG4). At least one unit under test may include the first logic unit 111 and the second logic unit 112 coupled to comparator 33.

[0082] For example, the second logic circuit can be obtained by copying each logic unit in the first logic circuit, and the output terminals of each logic unit included in the second logic circuit are not coupled to any logic unit. In some examples, referring to FIG3 or FIG4, the second logic circuit can be an adjustable proportional logic circuit 31 obtained by copying the first logic unit 111 to the second logic unit 114, and the outputs of the first copied logic unit 121 to the fourth copied logic unit 124 in the adjustable proportional logic circuit 31 are not coupled to any logic unit.

[0083] For example, the second unit under test may be a logic unit among multiple replicated logic units that requires functional safety testing. In some examples, referring to FIG3 or FIG4, at least one second unit under test may include a first replicated logic unit 121 and a second replicated logic unit 122.

[0084] For example, determining at least one first unit under test (UTD) in a first logic circuit may include, without any basis, arbitrarily determining at least one logic unit from a plurality of logic units in the first logic circuit that requires functional safety testing, and defining that logic unit requiring functional safety testing as the first UTD; or it may include determining at least one logic unit from a plurality of logic units in the first logic circuit that requires functional safety testing based on a target test coverage rate for functional safety testing, and defining that logic unit requiring functional safety testing as the first UTD. This disclosure does not limit the specific implementation method of determining at least one UTD from the first logic circuit. This disclosure uses the example of determining at least one UTD from a plurality of logic units in the first logic circuit based on a target test coverage rate for illustrative purposes.

[0085] For example, referring to FIG3, step 501 may include: the test equipment 32 determines the target test coverage for functional safety testing of the integrated circuit according to the safety level of the integrated circuit, and then determines the first logic unit 111 and the second logic unit 112 from the first logic unit 111 to the fourth logic unit 114 of the logic circuit 11 that need to be functionally tested, and determines the first logic unit 111 and the second logic unit 112 as at least one first unit under test; and determines the first copy logic unit 121 corresponding to the first logic unit 111 and the second copy logic unit 112 corresponding to the second logic unit 112 from the first copy logic unit 121 to the fourth copy logic unit 124 of the adjustable proportional logic circuit 31, and determines the first copy logic unit 121 and the second copy logic unit 122 as at least one second unit under test.

[0086] In some examples, test device 32 can determine at least one first unit under test and at least one second unit under test by means of a script program and the method described above.

[0087] For example, referring to FIG3, taking at least one first unit under test including a first logic unit 111 and a second logic unit 112, and at least one second unit under test including a first replication logic unit 121 and a second replication logic unit 122 as an example, after the test device 32 determines at least one first unit under test and at least one second unit under test through a script program, it further includes: coupling the output terminal of the first logic unit 111 and the output terminal of the second logic unit 112 to the first input terminal of the comparator 33 through EDA software test operations to perform functional safety testing on the first logic unit 111 and the second logic unit 112; and coupling the output terminal of the first replication logic unit 121 and the output terminal of the second replication logic unit 122 to the second input terminal of the comparator 33 to perform functional safety testing on the first replication logic unit 121 and the second replication logic unit 122.

[0088] Step 502: Perform functional safety testing on the first logic circuit and the second logic circuit to obtain the consistency test results of the first test data output by each first unit under test and the corresponding second test data output by each second unit under test.

[0089] For example, the first test data can be the first processed data obtained by each first unit under test in the first logic circuit after processing the input first data to be processed. The second test data can be the second processed data obtained by each second unit under test in the second logic circuit after processing the input second data to be processed. In some examples, the first data to be processed and the second data to be processed can be the same data, and when the first test unit and the second test unit are normal, the first processed data and the second processed data are also the same data, that is, the first test data and the second test data are consistent.

[0090] For example, the consistency test result can be a comparison result of the first test data and the second test data, and can include whether the first test data and the second test data are consistent or inconsistent. In some examples, a logic high level "1" can be used to indicate that the first test data and the second test data are consistent, and a logic low level "0" can be used to indicate that the first test data and the second test data are inconsistent. In other examples, a logic low level "0" can be used to indicate that the first test data and the second test data are consistent, and a logic high level "1" can be used to indicate that the first test data and the second test data are inconsistent. This disclosure does not limit the specific implementation form of the consistency test result. This disclosure uses the example of a logic high level "1" indicating that the first test data and the second test data are consistent, and a logic low level "0" indicating that the first test data and the second test data are inconsistent, for illustrative purposes.

[0091] For example, performing functional safety testing on the first logic circuit and the second logic circuit may include: inputting corresponding first data to be processed to each logic unit in the first logic circuit, and inputting corresponding second data to be processed to each copy logic unit in the second logic circuit, so as to perform functional safety testing on the first logic circuit and the second logic circuit.

[0092] In some examples, referring to Figure 3, the first logic circuit is logic circuit 11 and the second logic circuit is adjustable proportional logic circuit 31. Functional safety testing of the first and second logic circuits may include: using EDA software testing tools in the testing device 32, inputting corresponding first data to be processed to the first logic units 111 to the fourth logic units 114 in logic circuit 11 in a simulated manner, and inputting corresponding second data to be processed to the first copy logic units 121 to the fourth copy logic units 124 in adjustable proportional logic circuit 31, to perform functional safety testing on logic circuit 11 and adjustable proportional logic circuit 31.

[0093] For example, when performing functional safety testing on the first logic circuit and the second logic circuit, first test data and second test data can be obtained first, and then the first test data and second test data can be compared to obtain the consistency test result of the first test data and the second test data.

[0094] In some examples, at least one first unit under test includes a first logic unit 111 and a second logic unit 112, and at least one second unit under test includes a first replica logic unit 121 and a second replica logic unit 122. After inputting corresponding first data to be processed to the first logic units 111 to the fourth logic units 114 in the logic circuit 11, and inputting corresponding second data to be processed to the first replica logic units 121 to the fourth replica logic units 124 in the adjustable proportional logic circuit 31, the first logic units 111 and 112 will output first test data to the comparator 33; the first replica logic units 121 and 122 will output second test data to the comparator 33. Then, the comparator 33 can compare the first test data and the second test data to obtain a consistency test result of the first test data and the second test data.

[0095] Step 503: Based on the conformance test results, determine the current test coverage of the integrated circuit.

[0096] For example, step 503 may include: determining the structure and coupling relationship of each original logic circuit in the integrated circuit, and determining the current test coverage of the integrated circuit based on the structure and coupling relationship and the consistency test results.

[0097] In some examples, referring to Figure 3, the EDA software testing tool in the test device 32 can acquire the consistency test results of the first test data and the second test data in real time, and calculate the current test coverage corresponding to the consistency test results based on the structure and coupling relationship of each original logic circuit in the pre-stored integrated circuit.

[0098] Step 504: In response to the fact that the current test coverage and the target test coverage do not meet the preset numerical relationship, adjust the first unit under test in the first logic circuit and the second unit under test in the second logic circuit to obtain the first target logic circuit and the second target logic circuit.

[0099] For example, the preset numerical relationship can be that the numerical values ​​are equal or close. In some examples, if the difference between the current test coverage and the target test coverage is less than a difference threshold, then the current test coverage is determined to be equal to or close to the target test coverage.

[0100] For example, referring to Figure 3, the test device 32 can determine the coverage difference between the current test coverage and the target test coverage through a script program. When the coverage difference is greater than or equal to the difference threshold, it is determined that the current test coverage and the target test coverage do not meet the preset numerical relationship. When the coverage difference is less than the difference threshold, it is determined that the current test coverage and the target test coverage meet the preset numerical relationship.

[0101] For example, the first target logic circuit can be a first logic circuit adjusted from the first test unit. The second target logic circuit can be a second logic circuit adjusted from the second test unit.

[0102] For example, adjusting the first unit under test in the first logic circuit and the second unit under test in the second logic circuit to obtain the first target logic circuit and the second target logic circuit may include: adding, reducing or replacing the first unit under test in the first logic circuit and the second unit under test in the second logic circuit, and determining the first target logic circuit based on the added, reduced or replaced first unit under test, and determining the second target logic circuit based on the added, reduced or replaced second unit under test.

[0103] In some examples, referring to Figure 3, the first unit under test includes a first logic unit 111 and a second logic unit 112, and the second unit under test includes a first copy logic unit 121 and a second copy logic unit 122. Adding, reducing, or replacing the first unit under test in the first logic circuit and the second unit under test in the second logic circuit may include: the test device 32 adding the third logic unit 113 or the fourth logic unit 114 as the first unit under test through a script program, and correspondingly adding the third copy logic unit 123 or the fourth copy logic unit 124 as the second unit under test; or, removing the test on the first logic unit 111 or the second logic unit 112, and correspondingly removing the test on the first copy logic unit 121 or the second copy logic unit 122; or, replacing the test on the first logic unit 111 or the second logic unit 112 with the test on the third logic unit 113 or the fourth logic unit 114, and correspondingly replacing the test on the first copy logic unit 121 or the second copy logic unit 122 with the test on the third copy logic unit 123 or the fourth copy logic unit 124.

[0104] Step 505: Based on the first target logic circuit and the second target logic circuit, determine the target integrated circuit corresponding to the target test coverage.

[0105] For example, the target test coverage can be the test coverage required to perform functional safety testing on the integrated circuit, as determined by the safety level of the integrated circuit. In some examples, the target test coverage can be any value less than 100%, for example, the target test coverage can be 80% or 90%. This disclosure does not limit the specific size of the target test coverage. This disclosure uses a target test coverage of 90% as an example for illustration.

[0106] For example, referring to Figure 3 or Figure 4, step 505 may include: the test device 32 determines the latest test coverage of the integrated circuit based on the first target logic circuit and the second target logic circuit. Then, it determines whether the latest test coverage and the target test coverage satisfy a preset numerical relationship. When it is determined that the latest test coverage satisfies the preset numerical relationship, the integrated circuit corresponding to the first target logic circuit and the second target logic circuit is determined as the target integrated circuit corresponding to the target test coverage. When it is determined that the latest test coverage and the target test coverage do not satisfy the preset numerical relationship, the logic unit (first unit under test) coupled to the comparator 33 or the first hash generator 341 in the logic circuit 11, and the copy logic unit (second unit under test) coupled to the comparator 33 or the second hash generator 342 in the adjustable proportional logic circuit 31 are adjusted. Then, the first target logic circuit and the second target logic circuit are updated until the latest test coverage determined based on the updated first target logic circuit and the updated second target logic circuit satisfies the preset numerical relationship with the target test coverage. The integrated circuit corresponding to the latest first target logic circuit and the latest second target logic circuit is then determined as the target integrated circuit corresponding to the target test coverage.

[0107] In this embodiment, functional safety testing is performed on the first logic circuit and the second logic circuit to obtain consistency test results of the first test data output by each first unit under test in the first logic circuit and the second test data output by each second unit under test in the second logic circuit. Therefore, the consistency test results are related to each first unit under test in the first logic circuit and each second unit under test in the second logic circuit. The current test coverage of the integrated circuit determined based on the consistency test results is also related to each first unit under test in the first logic circuit and each second unit under test in the second logic circuit. Furthermore, when the current test coverage does not meet the preset numerical relationship with the target test coverage, adjusting the first test unit in the first logic circuit and the second test unit in the second logic circuit can accurately adjust the current test coverage to the target test coverage, thus obtaining the target integrated circuit corresponding to the target test coverage. Simultaneously, since adjusting the first test unit in the first logic circuit and the second test unit in the second logic circuit is relatively simple and does not require redesigning the integrated circuit, it can effectively save human development costs.

[0108] As shown in Figure 6, based on the embodiment shown in Figure 5 above, step 502 may include the following steps 5021 to 5023.

[0109] Step 5021: Perform functional safety tests on the first logic circuit and the second logic circuit to obtain first test data and second test data.

[0110] For example, step 5021 may include: inputting corresponding first data to be processed to each logic unit in the first logic circuit, and inputting corresponding second data to be processed to each copy logic unit in the second logic circuit; each first unit under test in the first logic circuit will process the first data to be processed to obtain first test data; each second unit under test in the second logic circuit will process the second data to be processed to obtain second test data.

[0111] In some examples, at least one first unit under test includes a first logic unit 111 and a second logic unit 112, and at least one second unit under test includes a first replica logic unit 121 and a second replica logic unit 122. Referring to FIG4, step 5021 may specifically include: inputting corresponding first data to be processed to the first logic units 111 to the fourth logic units 114 in the logic circuit 11, and inputting corresponding second data to be processed to the first replica logic units 121 to the fourth replica logic units 124 in the adjustable proportional logic circuit 31. The first logic unit 111 and the second logic unit 112, in response to the received first data to be processed, respectively process the first data to be processed to obtain first test data (first processed data), and output the first test data to the hash generator 34; the first replica logic unit 121 and the second replica logic unit 122, in response to the received second data to be processed, respectively process the second data to be processed to obtain second test data (second processed data), and output the second test data to the hash generator 34.

[0112] Step 5022: The hash generator in the integrated circuit performs hash calculations on the first test data and the second test data respectively to obtain the first hash value corresponding to the first test data and the second hash value corresponding to the second test data.

[0113] For example, referring to FIG4, step 5022 may include: hash generator 34 performing hash calculations on the first test data and the second test data respectively, and outputting the first hash value corresponding to the first test data to the first input terminal of comparator 33, and outputting the second hash value corresponding to the second test data to the second input terminal of comparator 33.

[0114] In some embodiments of this disclosure, the hash generator may include a first hash generator and a second hash generator. Step 5022 may include: performing a hash calculation on the first test data using the first hash generator to obtain a first hash value; and performing a hash calculation on the second test data using the second hash generator to obtain a second hash value.

[0115] For example, referring to FIG4, the first logic unit 111 and the second logic unit 112 can output the first test data to the first hash generator 341 in the hash generator 34, and the first copy logic unit 121 and the second copy logic unit 122 can output the second test data to the second hash generator 342 in the hash generator 34. Correspondingly, step 5022 may include: the first hash generator 341 processes the first test data using a corresponding first hash algorithm to obtain a first hash value of a first fixed length, and outputs the first hash value to the first input terminal of the comparator 33; the second hash generator 342 processes the second test data using a corresponding second hash algorithm to obtain a second hash value of a second fixed length, and outputs the second hash value to the second input terminal of the comparator 33.

[0116] In some examples, the first hash algorithm and the second hash algorithm can be the same algorithm. The first fixed length and the second fixed length can be the same length, and the first fixed length and / or the second fixed length can be simultaneously smaller than the bit width of the first test data and the bit width of the second test data. In this way, the first hash generator and the second hash generator can respectively obtain the first hash value and the second hash value with the same bit width but a smaller bit width.

[0117] Step 5023: Determine the consistency test result based on the first hash value and the second hash value.

[0118] For example, referring to Figure 4, the comparator 33 can compare the first hash value and the second hash value to obtain the consistency test result and output the consistency test result to the test device 32.

[0119] In this embodiment, a first hash generator performs hash calculations on the first test data to obtain a first hash value representing the first test data; a second hash generator performs hash calculations on the second test data to obtain a second hash value representing the second test data. Thus, when the first hash value and the second hash value have the same length, and both are shorter than the lengths of the first and second test data, comparing the first hash value and the second hash value can not only accurately determine the consistency test result of the first and second test data, but also reduce the computational load and complexity during comparison.

[0120] As shown in Figure 7, based on the embodiment shown in Figure 5 above, the functional safety testing method for the integrated circuit may further include the following step 506.

[0121] Step 506: In response to the current test coverage and the target test coverage satisfying a preset numerical relationship, the target integrated circuit is determined based on the first logic circuit and the second logic circuit.

[0122] For example, step 506 may include: when the current test coverage and the target test coverage satisfy a preset numerical relationship, determining the first logic circuit as the first target logic circuit, removing all logic units in the second logic circuit except for the second unit under test (retaining at least one second unit under test in the second logic circuit), and determining the remaining at least one second unit under test as the second target logic circuit. Finally, determining the integrated circuits corresponding to the first target logic circuit and the second target logic circuit as target integrated circuits.

[0123] In some examples, at least one first unit under test includes a first logic unit 111 and a second logic unit 112, and at least one second unit under test includes a first replicated logic unit 121 and a second replicated logic unit 122. Referring to Figure 3 or Figure 4, step 506 may specifically include: when the current test coverage and the target test coverage meet a preset numerical relationship, taking integrated circuit 11 as the first target logic circuit, and automatically removing the third replicated logic unit 123 and the fourth replicated logic unit 124 in the adjustable scaling logic circuit 31 using the EDA software test tool in the test equipment 32, and taking the remaining first replicated logic unit 121 and second replicated logic unit 122 as the second target logic circuit. Finally, the integrated circuit 11, the first replicated logic unit 121, and the second replicated logic unit 122 are determined as the target integrated circuit.

[0124] In this embodiment, since the current test coverage is determined based on the consistency test results, and the consistency test results are related to each first unit under test in the first logic circuit and each second unit under test in the second logic circuit, the current test coverage corresponds to each first unit under test in the first logic circuit and each second unit under test in the second logic circuit. Furthermore, when the current test coverage and the target test coverage satisfy a preset numerical relationship, the target integrated circuit corresponding to the target test coverage can be accurately determined based on the first logic circuit and the second logic circuit.

[0125] As shown in Figure 8, based on the embodiment shown in Figure 5 above, step 504 may include the following steps 5041 and 5042.

[0126] Step 5041: In response to the difference between the current test coverage and the target test coverage being greater than or equal to a difference threshold, an adjustment strategy for adjusting the first unit under test in the first logic circuit and the second unit under test in the second logic circuit is determined based on the difference between the current test coverage and the target test coverage.

[0127] For example, a preset numerical relationship between the current test coverage and the target test coverage can be expressed as the difference between the current test coverage and the target test coverage being greater than or equal to a difference threshold. The difference threshold represents the degree of closeness between the current test coverage and the target test coverage and can be determined based on the test accuracy of the integrated circuit functional safety test system. In some examples, since the current test coverage can approach the target test coverage in a positive direction (from smallest to largest) or in a negative direction (from largest to smallest), the difference threshold can be positive or negative. This disclosure does not limit the sign or specific size of the difference threshold.

[0128] For example, the adjustment strategy may include a first adjustment strategy for a first unit under test (DUT) in a first logic circuit and a second adjustment strategy for adjusting a second DUT in a second logic circuit. In some examples, the first adjustment strategy may correspond to the second adjustment strategy. For instance, if the first adjustment strategy is to add the first DUT, the second adjustment strategy may correspond to adding the second DUT. As another example, if the first adjustment strategy is to reduce the first DUT, the second adjustment strategy may correspond to reducing the second DUT. Yet another example, if the first adjustment strategy is to replace the first DUT, the second adjustment strategy may correspond to replacing the second DUT.

[0129] For example, referring to Figure 3 or Figure 4, step 5041 may include: when the test device 32 determines that the difference between the current test coverage and the target test coverage is greater than or equal to a difference threshold, it generates a first adjustment strategy for adjusting the logic unit (first unit under test) coupled to the comparator 33 or the first hash generator 341 in the logic circuit 11 and a second adjustment strategy for adjusting the replicated logic unit (second unit under test) coupled to the comparator 33 or the second hash generator 342 in the adjustable proportional logic circuit 31.

[0130] Step 5042: Adjust the first unit under test in the first logic circuit and the second unit under test in the second logic circuit based on the adjustment strategy to obtain the first target logic circuit and the second target logic circuit.

[0131] For example, referring to FIG3 or FIG4, step 5042 may include: the test device 32 adjusting the logic unit coupled to the comparator 33 or the first hash generator 341 in the logic circuit 11 based on a first adjustment strategy to obtain a first target logic circuit; and adjusting the replication logic unit coupled to the comparator 33 or the second hash generator 342 in the adjustable ratio logic circuit 31 based on a second adjustment strategy to obtain a second target logic circuit.

[0132] In this embodiment, since the current test coverage corresponds to each first unit under test (UDT) in the first logic circuit and each second UDT in the second logic circuit, when the difference between the current test coverage and the target test coverage is greater than or equal to a difference threshold, an adjustment strategy for adjusting the first UDT in the first logic circuit and the second UDT in the second logic circuit can be accurately determined based on this difference. Furthermore, by adjusting the first UDT in the first logic circuit and the second UDT in the second logic circuit based on this adjustment strategy, a first target logic circuit and a second target logic circuit corresponding to the target test coverage can be obtained. This allows for faster acquisition of the target integrated circuit based on the first target logic circuit and the second target logic circuit.

[0133] As shown in Figure 9, based on the embodiment shown in Figure 8 above, step 5041 may include the following steps 901 and 902.

[0134] Step 901: In response to the difference between the current test coverage and the target test coverage being greater than or equal to the difference threshold and greater than the first threshold, the adjustment strategy is determined to be to reduce the number of the first unit under test in the first logic circuit and the number of the second unit under test in the second logic circuit.

[0135] For example, a first threshold is used to indicate the magnitude relationship between the current test coverage and the target test coverage. If the difference between the current test coverage and the target test coverage is greater than the first threshold, then the current test coverage is greater than the target test coverage. In some examples, the first threshold can be equal to the value 0.

[0136] For example, taking at least one first unit under test comprising two logic units (first logic unit 111 and second logic unit 112) and at least one second unit under test comprising two replicated logic units (first replicated logic unit 121 and second replicated logic unit 122) as an example, referring to Figure 3 or Figure 4, step 901 may include: when the difference between the current test coverage and the target test coverage is greater than or equal to a difference threshold, and greater than a first threshold, the test device 32 determines an adjustment strategy including a first adjustment strategy of reducing the number of at least one first unit under test from 2 to 1 and a second adjustment strategy of reducing the number of at least one second unit under test from 2 to 1.

[0137] In some examples, taking at least one first unit under test including a first logic unit 111 and a second logic unit 112 as an example, the first adjustment strategy may include removing the coupling between the first logic unit 111 or the second logic unit 112 and the comparator 33 or the first hash generator 341.

[0138] In some examples, taking at least one second unit under test including a first replication logic unit 121 and a second replication logic unit 122 as an example, the second adjustment strategy may include removing the coupling between the first replication logic unit 121 or the second replication logic unit 122 and the comparator 33 or the second hash generator 342.

[0139] Step 902: In response to the difference between the current test coverage and the target test coverage being greater than or equal to the difference threshold and less than the second threshold, the adjustment strategy is determined to be to increase the number of the first unit under test in the first logic circuit and the number of the second unit under test in the second logic circuit.

[0140] For example, the second threshold is also used to indicate the magnitude relationship between the current test coverage and the target test coverage. If the difference between the current test coverage and the target test coverage is less than the second threshold, then the current test coverage is less than the target test coverage. In some examples, the second threshold can be the same as the first threshold. For example, the second threshold can also be the value 0.

[0141] For example, taking at least one first unit under test comprising two logic units (first logic unit 111 and second logic unit 112) and at least one second unit under test comprising two replicated logic units (first replicated logic unit 121 and second replicated logic unit 122) as an example, referring to Figure 3 or Figure 4, step 902 may include: when the difference between the current test coverage and the target test coverage is greater than or equal to a difference threshold and less than a second threshold, the test device 32 determines an adjustment strategy including a first adjustment strategy of increasing the number of at least one first unit under test from 2 to 3 and a second adjustment strategy of increasing the number of at least one second unit under test from 2 to 3.

[0142] In some examples, taking at least one first unit under test including a first logic unit 111 and a second logic unit 112 as an example, the first adjustment strategy may include increasing the coupling of a third logic unit 113 or a fourth logic unit 114 with the comparator 33 or the first hash generator 341.

[0143] In some examples, taking at least one second unit under test including a first replication logic unit 121 and a second replication logic unit 122 as an example, the second adjustment strategy may include increasing the coupling between a third replication logic unit 123 or a fourth replication logic unit 124 and a comparator 33 or a second hash generator 342.

[0144] In this embodiment, since the current test coverage corresponds to the first unit under test (UDT) in the first logic circuit and the second UDT in the second logic circuit, when the difference between the current test coverage and the target test coverage is greater than or equal to a difference threshold and greater than a first threshold, the adjustment strategy is determined to be to reduce the number of the first UDT in the first logic circuit and the second UDT in the second logic circuit. This effectively reduces the current test coverage, bringing it closer to the target test coverage. When the difference between the current test coverage and the target test coverage is greater than or equal to a difference threshold and less than a second threshold, the adjustment strategy is determined to be to increase the number of the first UDT in the first logic circuit and the second UDT in the second logic circuit. This effectively increases the current test coverage, bringing it closer to the target test coverage.

[0145] In some other embodiments of this disclosure, step 5041 may further include: in response to the difference between the current test coverage and the target test coverage being greater than or equal to a difference threshold and greater than a first threshold, determining an adjustment strategy of replacing the first unit under test in the first logic circuit and the second unit under test in the second logic circuit; in response to the difference between the current test coverage and the target test coverage being greater than or equal to a difference threshold and less than a second threshold, determining an adjustment strategy of replacing the first unit under test in the first logic circuit and the second unit under test in the second logic circuit.

[0146] For example, taking at least one first unit under test including a first logic unit 111 and a second logic unit 112 as an example, referring to FIG3 or FIG4, taking at least one first unit under test including a first logic unit 111 and a second logic unit 112, and at least one second unit under test including a first replication logic unit 121 and a second replication logic unit 122 as an example.

[0147] Referring to Figure 3 or Figure 4, in response to the difference between the current test coverage and the target test coverage being greater than or equal to a difference threshold and greater than a first threshold, determining an adjustment strategy to replace the first unit under test in the first logic circuit and the second unit under test in the second logic circuit may include: when the difference between the current test coverage and the target test coverage is greater than or equal to a difference threshold and greater than a first threshold, the test device 32 determines an adjustment strategy including a first adjustment strategy of replacing the first logic unit 111 or the second logic unit 112 with the third logic unit 113 or the fourth logic unit 114, and a second adjustment strategy of replacing the first copy logic unit 121 or the second copy logic unit 122 with the third copy logic unit 123 or the fourth copy logic unit 124.

[0148] In some examples, replacing the first logic unit 111 or the second logic unit 112 with the third logic unit 113 or the fourth logic unit 114 may include: first removing the coupling between the first logic unit 111 or the second logic unit 112 and the comparator 33 or the first hash generator 341, and then adding the coupling between the third logic unit 113 or the fourth logic unit 114 and the comparator 33 or the first hash generator 341.

[0149] As shown in Figure 10, based on the embodiment shown in Figure 8 above, step 5042 may include the following steps 1001 to 1003.

[0150] Step 1001: Adjust the first unit under test in the first logic circuit based on the adjustment strategy, and determine the adjusted first logic circuit as the first target logic circuit.

[0151] For example, taking the first adjustment strategy in the adjustment strategy as adding a first unit under test in the first logic circuit as an example, referring to FIG3 or FIG4, step 1001 may include: the test device 32, based on the first adjustment strategy, adds the coupling of the third logic unit 113 (or the fourth logic unit 114) to the comparator 33 or the first hash generator 341, and uses the integrated circuit 11 after adding the coupling of the third logic unit 113 (or the fourth logic unit 114) to the comparator 33 or the first hash generator 341 as the first target logic circuit.

[0152] Step 1002: Adjust the second unit under test in the second logic circuit based on the adjustment strategy, and retain the adjusted second unit under test in the second logic circuit to obtain at least one adjusted second unit under test.

[0153] For example, taking the second adjustment strategy in the adjustment strategy as increasing the number of second test units in the second logic circuit as an example, referring to Figure 3 or Figure 4, step 1002 may include: the test device 32, based on the second adjustment strategy, increases the coupling between the third replication logic unit 123 (or the fourth replication logic unit 124) and the comparator 33 or the second hash generator 342 to obtain the adjusted adjustable proportional logic circuit 31. Then, the fourth replication logic unit 124 (or the third replication logic unit 123) is removed.

[0154] Step 1003: Determine at least one adjusted second unit under test as the second target logic circuit.

[0155] For example, the second adjustment strategy specifically includes increasing the coupling between the third replication logic unit 123 and the comparator 33 or the second hash generator 342. Referring to FIG3 or FIG4, step 1003 may include: the test device 32 determining the logic circuit after removing the fourth replication logic unit 124 in the adjustable proportional logic circuit 31 as the second target logic circuit.

[0156] In this embodiment of the disclosure, when the adjustment strategy is an adjustment strategy that enables the current test coverage to meet a preset ratio with the target test coverage, the first unit under test in the first logic circuit can be adjusted by the adjustment strategy to obtain the first logic circuit corresponding to the target test coverage; the second unit under test in the second logic circuit can be adjusted based on the adjustment strategy to obtain the second target logic circuit corresponding to the target test coverage.

[0157] Exemplary System

[0158] Based on the above embodiments, this disclosure provides yet another functional safety testing system for integrated circuits. FIG11 is a schematic structural diagram of another functional safety testing system for integrated circuits provided in an exemplary embodiment of this disclosure. As shown in FIG11, the functional safety testing system 110 for integrated circuits may include an integrated circuit 111 and a test device 112 for performing functional safety testing on the integrated circuit 111. The integrated circuit 111 includes a first logic circuit 1110, a second logic circuit 1111, and a comparator 1112.

[0159] Test equipment 112 is used to determine at least one first unit under test in the first logic circuit 1110 and a second unit under test in the second logic circuit 1111 corresponding to each first unit under test;

[0160] The first logic circuit 1110 is coupled to the comparator 1112 and is used to output first test data to the comparator 1112 based on at least one first unit under test in the first logic circuit 1110.

[0161] The second logic circuit 1111 is coupled to the comparator 1112 and is used to output second test data to the comparator 1112 based on at least one second unit under test in the second logic circuit 1111.

[0162] Comparator 1112, coupled to test equipment 112, is used to output a consistency test result to test equipment 112 based on first test data and second test data;

[0163] Test equipment 112 is used to determine the current test coverage of integrated circuit 111 based on the consistency test results; in response to the current test coverage not meeting the preset numerical relationship with the target test coverage, the first unit under test in the first logic circuit 1110 and the second unit under test in the second logic circuit 1111 are adjusted to obtain the first target logic circuit and the second target logic circuit; based on the first target logic circuit and the second target logic circuit, the target integrated circuit corresponding to the target test coverage is determined.

[0164] As shown in Figure 12, based on the embodiment shown in Figure 10 above, the integrated circuit 111 may further include: a hash generator 1113;

[0165] Hash generator 1113 is coupled to first logic circuit 1110, second logic circuit 1111 and comparator 1112, and is used to perform hash calculation on first test data and second test data respectively to obtain first hash value corresponding to first test data and second hash value corresponding to second test data, and output the first hash value and the second hash value to comparator 1112.

[0166] Comparator 1112 is used to determine the consistency test result based on the first hash value and the second hash value.

[0167] As shown in Figure 13, based on the embodiment shown in Figure 12 above, the hash generator 1113 includes a first hash generator 1301 and a second hash generator 1302.

[0168] The first hash generator 1301 is coupled to the first logic circuit 1110 and the comparator 1112, and is used to perform hash calculation on the first test data and output the obtained first hash value to the comparator 1112.

[0169] The second hash generator 1302 is coupled to the second logic circuit 1111 and the comparator 1112, and is used to perform hash calculation on the second test data and output the obtained second hash value to the comparator 1112.

[0170] Exemplary device

[0171] Based on the above embodiments, this disclosure provides a functional safety testing apparatus for integrated circuits. Figure 14 is a schematic diagram of the structure of a functional safety testing apparatus for integrated circuits provided in an exemplary embodiment of this disclosure. The integrated circuit includes a first logic circuit and a second logic circuit for performing functional safety testing on the first logic circuit. As shown in Figure 14, the functional safety testing apparatus 140 for the integrated circuit may include a first determining module 1401, a functional safety testing module 1402, a second determining module 1403, an adjustment module 1404, and a third determining module 1405.

[0172] The first determining module 1401 is used to determine at least one first unit under test in the first logic circuit and a second unit under test in the second logic circuit corresponding to each first unit under test.

[0173] Functional safety test module 1402 is used to perform functional safety tests on the first logic circuit and the second logic circuit to obtain the consistency test results of the first test data output by each first unit under test and the corresponding second test data output by each second unit under test.

[0174] The second determining module 1403 is used to determine the current test coverage of the integrated circuit based on the conformance test results;

[0175] The adjustment module 1404 is used to adjust the first unit under test in the first logic circuit and the second unit under test in the second logic circuit in response to the fact that the current test coverage and the target test coverage do not meet the preset numerical relationship, so as to obtain the first target logic circuit and the second target logic circuit.

[0176] The third determining module 1405 is used to determine the target integrated circuit corresponding to the target test coverage based on the first target logic circuit and the second target logic circuit.

[0177] As shown in Figure 15, based on the embodiment shown in Figure 14 above, the functional safety test module 1402 may include a functional safety test unit 1501, a hash calculation unit 1502, and a first determination unit 1503.

[0178] The functional safety test unit 1501 is used to perform functional safety tests on the first logic circuit and the second logic circuit to obtain first test data and second test data.

[0179] The hash calculation unit 1502 is used to perform hash calculations on the first test data and the second test data respectively through the hash generator in the integrated circuit to obtain the first hash value corresponding to the first test data and the second hash value corresponding to the second test data.

[0180] The first determining unit 1503 is used to determine the consistency test result based on the first hash value and the second hash value.

[0181] As shown in Figure 16, based on the embodiment shown in Figure 15 above, the hash calculation unit 1502 includes a first hash calculation subunit 1601 and a second hash calculation subunit 1602.

[0182] The first hash calculation subunit 1601 is used to perform hash calculation on the first test data through the first hash generator to obtain the first hash value;

[0183] The second hash calculation subunit 1602 is used to perform hash calculation on the second test data through the second hash generator to obtain the second hash value;

[0184] The hash generator includes a first hash generator and a second hash generator.

[0185] As shown in Figure 17, based on the embodiment shown in Figure 14 above, the functional safety testing device 140 for the integrated circuit may further include a fourth determining module 1406.

[0186] The fourth determining module 1406 is used to determine the target integrated circuit based on the first logic circuit and the second logic circuit in response to the current test coverage and the target test coverage satisfying a preset numerical relationship.

[0187] As shown in Figure 18, based on the embodiment shown in Figure 14 above, the adjustment module 1404 may include a second determining unit 1801 and an adjustment unit 1802.

[0188] The second determining unit 1801 is used to determine an adjustment strategy for adjusting the first unit under test in the first logic circuit and the second unit under test in the second logic circuit based on the difference when the difference between the current test coverage and the target test coverage is greater than or equal to the difference threshold.

[0189] The adjustment unit 1802 is used to adjust the first unit under test in the first logic circuit and the second unit under test in the second logic circuit based on the adjustment strategy to obtain the first target logic circuit and the second target logic circuit.

[0190] As shown in Figure 19, based on the embodiment shown in Figure 18 above, the second determining unit 1801 includes a first determining subunit 1901 and a second determining subunit 1902.

[0191] The first determining subunit 1901 is used to determine, in response to a difference greater than a first threshold, an adjustment strategy of reducing the number of the first unit under test in the first logic circuit and the number of the second unit under test in the second logic circuit.

[0192] The second determining subunit 1902 is used to determine, in response to a difference less than a second threshold, an adjustment strategy of increasing the number of the first unit under test in the first logic circuit and the number of the second unit under test in the second logic circuit.

[0193] As shown in Figure 20, based on the embodiment shown in Figure 18 above, the adjustment unit 1802 may include a first adjustment subunit 2001, a second adjustment subunit 2002, and a third determination subunit 2003.

[0194] The first adjustment subunit 2001 is used to adjust the first unit under test in the first logic circuit based on the adjustment strategy, and to determine the adjusted first logic circuit as the first target logic circuit.

[0195] The second adjustment subunit 2002 is used to adjust the second unit under test in the second logic circuit based on the adjustment strategy, and to retain the adjusted second unit under test in the second logic circuit to obtain at least one adjusted second unit under test.

[0196] The third determining subunit 2003 is used to determine at least one adjusted second test unit as the second target logic circuit.

[0197] Exemplary electronic devices

[0198] Figure 21 is a schematic diagram of the structure of an electronic device provided by an exemplary embodiment of the present disclosure. As shown in Figure 21, the electronic device 210 includes one or more processors 2101 and memory 2102.

[0199] The processor 2101 may be a central processing unit (CPU) or other form of processing unit with data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device 210 to perform desired functions.

[0200] The memory 2102 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 2101 may execute the program instructions to implement the functional safety testing methods for integrated circuits of the various embodiments of this disclosure described above, and / or other desired functions.

[0201] In one example, the electronic device 210 may also include an input device 2103 and an output device 2104, which are interconnected via a bus system and / or other forms of connection mechanism (not shown).

[0202] Of course, for simplicity, Figure 21 only shows some of the components of the electronic device 210 that are relevant to this disclosure, omitting components such as buses, input / output interfaces, etc. In addition, the electronic device 210 may include any other suitable components depending on the specific application.

[0203] Exemplary computer program products and computer-readable storage media

[0204] In addition to the methods and apparatus described above, embodiments of this disclosure may also be computer program products, including computer program instructions that, when executed by a processor, cause the processor to perform the steps in the functional safety testing methods for integrated circuits according to various embodiments of this disclosure as described in the "Exemplary Methods" section of this specification.

[0205] Computer program products can be written in any combination of one or more programming languages ​​to perform the operations of embodiments of this disclosure. The programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on a user's computing device, partially on a user's computing device, as a standalone software package, partially on a user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0206] Furthermore, embodiments of this disclosure may also be computer-readable storage media storing computer program instructions thereon, which, when executed by a processor, cause the processor to perform the steps in the functional safety testing methods for integrated circuits according to various embodiments of this disclosure as described in the "Exemplary Methods" section above.

[0207] Computer-readable storage media may take the form of any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may, for example, include, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatuses, or devices, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: electrical connections having one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, compact disc read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0208] The basic principles of this disclosure have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the aforementioned specific details for implementation.

[0209] Various modifications and variations can be made to this disclosure without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include such modifications and variations.

Claims

1. A method of functional safety testing of an integrated circuit, wherein, The integrated circuit comprises a first logic circuit and a second logic circuit for function safety testing of the first logic circuit, and the method comprises: determining at least one first unit under test in the first logic circuit and a second unit under test corresponding to each of the first units under test in the second logic circuit; function safety testing of the first logic circuit and the second logic circuit to obtain consistency test results of first test data output by each of the first units under test and second test data output by each of the corresponding second units under test; based on the consistency test results, determining a current test coverage of the integrated circuit; in response to the current test coverage and the target test coverage not satisfying a preset numerical relationship, adjusting the first units under test in the first logic circuit and the second units under test in the second logic circuit to obtain a first target logic circuit and a second target logic circuit; based on the first target logic circuit and the second target logic circuit, determining a target integrated circuit corresponding to the target test coverage.

2. The method of claim 1, wherein, The function safety testing of the first logic circuit and the second logic circuit to obtain consistency test results of first test data output by each of the first units under test and second test data output by each of the corresponding second units under test, comprises: function safety testing of the first logic circuit and the second logic circuit to obtain the first test data and the second test data; hash calculation of the first test data and the second test data by a hash generator in the integrated circuit to obtain a first hash value corresponding to the first test data and a second hash value corresponding to the second test data; based on the first hash value and the second hash value, determining the consistency test results.

3. The method of claim 2, wherein, The hash calculation of the first test data and the second test data by the hash generator in the integrated circuit to obtain a first hash value and a second hash value, comprises: hash calculation of the first test data by a first hash generator to obtain the first hash value; hash calculation of the second test data by a second hash generator to obtain the second hash value; wherein the hash generator comprises the first hash generator and the second hash generator.

4. The method of claim 1, further comprising: in response to the current test coverage and the target test coverage satisfying the preset numerical relationship, determining the target integrated circuit based on the first logic circuit and the second logic circuit.

5. The method according to any one of claims 1 to 4, wherein, The response to the current test coverage and the target test coverage not satisfying the preset numerical relationship, adjusting the first units under test in the first logic circuit and the second units under test in the second logic circuit to obtain a first target logic circuit and a second target logic circuit, comprises: in response to the difference between the current test coverage and the target test coverage being greater than or equal to a difference threshold, determining, based on the difference, an adjustment strategy for adjusting first units under test in the first logic circuit and second units under test in the second logic circuit; adjusting, based on the adjustment strategy, the first units under test in the first logic circuit and the second units under test in the second logic circuit to obtain the first target logic circuit and the second target logic circuit.

6. The method of claim 5, wherein, The determining, based on the difference, of the adjustment strategy for adjusting the first units under test in the first logic circuit and the second units under test in the second logic circuit comprises: in response to the difference being greater than a first threshold, determining that the adjustment strategy is to reduce the number of the first units under test in the first logic circuit and the second units under test in the second logic circuit; in response to the difference being less than a second threshold, determining that the adjustment strategy is to increase the number of the first units under test in the first logic circuit and the second units under test in the second logic circuit.

7. The method of claim 5, wherein, The adjusting, based on the adjustment strategy, of the first units under test in the first logic circuit and the second units under test in the second logic circuit to obtain the first target logic circuit and the second target logic circuit comprises: adjusting the first units under test in the first logic circuit based on the adjustment strategy, and determining the adjusted first logic circuit as the first target logic circuit; adjusting the second units under test in the second logic circuit based on the adjustment strategy, and retaining the adjusted second units under test in the second logic circuit to obtain at least one of the adjusted second units under test; determining the at least one of the adjusted second units under test as the second target logic circuit.

8. A functional safety test system for an integrated circuit, comprising: An integrated circuit and a test device for performing a functional safety test on the integrated circuit; the integrated circuit comprises a first logic circuit, a second logic circuit, and a comparator; The test device is configured to determine at least one first unit under test in the first logic circuit and a second unit under test in the second logic circuit corresponding to each of the first units under test; The first logic circuit is coupled to the comparator and configured to output first test data to the comparator based on at least one first unit under test in the first logic circuit; The second logic circuit is coupled to the comparator and configured to output second test data to the comparator based on at least one second unit under test in the second logic circuit; The comparator is coupled to the test device and configured to output a consistency test result to the test device based on the first test data and the second test data; The test device is configured to determine a current test coverage of the integrated circuit based on the consistency test result, and in response to the current test coverage and a target test coverage not satisfying a preset numerical relationship, to adjust first units under test in the first logic circuit and second units under test in the second logic circuit to obtain a first target logic circuit and a second target logic circuit. Based on the first target logic circuit and the second target logic circuit, the target integrated circuit corresponding to the target test coverage is determined.

9. The system of claim 8, wherein the integrated circuit further comprises a hash generator; The hash generator, coupled to the first logic circuit, the second logic circuit, and the comparator, is used to perform hash calculations on the first test data and the second test data respectively to obtain a first hash value corresponding to the first test data and a second hash value corresponding to the second test data, and output the first hash value and the second hash value to the comparator. The comparator is used to determine the consistency test result based on the first hash value and the second hash value.

10. The system of claim 9, wherein, The hash generator includes a first hash generator and a second hash generator; The first hash generator, coupled to the first logic circuit and the comparator, is used to perform hash calculation on the first test data and output the obtained first hash value to the comparator; A second hash generator, coupled to the second logic circuit and the comparator, is used to perform hash calculation on the second test data and output the obtained second hash value to the comparator.

11. A functional safety testing apparatus for an integrated circuit, the integrated circuit comprising a first logic circuit and a second logic circuit for performing functional safety testing on the first logic circuit, comprising: The first determining module is used to determine at least one first unit under test in the first logic circuit and a second unit under test in the second logic circuit corresponding to each of the first units under test. The functional safety test module is used to perform functional safety tests on the first logic circuit and the second logic circuit, and obtain the consistency test results of the first test data output by each first unit under test and the corresponding second test data output by each second unit under test. The second determining module is used to determine the current test coverage of the integrated circuit based on the consistency test results; An adjustment module is used to adjust the first unit under test in the first logic circuit and the second unit under test in the second logic circuit in response to the current test coverage and the target test coverage not meeting a preset numerical relationship, so as to obtain the first target logic circuit and the second target logic circuit. The third determining module is used to determine the target integrated circuit corresponding to the target test coverage based on the first target logic circuit and the second target logic circuit.

12. A computer-readable storage medium storing a computer program for performing a functional safety testing method for an integrated circuit according to any one of claims 1 to 7.

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