Data packet forwarding method, gateway device, storage medium, and program

Abstract

Embodiments of the present disclosure provide a data packet forwarding method, a gateway device, a storage medium, and a program. The gateway device comprises a plurality of processors and a network interface card, the network interface card comprising a programmable chip. The programmable chip receives an original data packet sent by a source-end device, forwards packet header information of the original data packet to a target processor for encapsulation, and caches payload data of the original data packet; and upon receiving the encapsulated packet header information which corresponds to the original data packet and is fed back by the target processor, the programmable chip reads the cached payload data of the original data packet, generates a target data packet on the basis of the read payload data of the original data packet and the encapsulated packet header information, and transmits the target data packet to a destination-end device. A plurality of pieces of packet header information corresponding to a plurality of original data packets sent by the source-end device are forwarded to different processors for encapsulation. By means of the solution, high-speed forwarding of data packets can be implemented.

Description

[0001] This disclosure relates to the field of network technology, and more particularly to a packet forwarding method, gateway device, storage medium, and program. Background: The communication traffic carried on the Internet is constantly growing and changing. Among them, the transmission of "elephant flows" consumes more network resources. An elephant flow refers to network traffic that lasts a long time and has a large data volume. For example, an elephant flow, which accounts for about 5% of the network traffic, may account for about 40% of the network bandwidth. Common examples of elephant flows include virtual machine migration, data migration, and data processing in distributed databases. In scenarios such as data centers, there is often a need to forward elephant flows. For example, a gateway device in a data center may forward an elephant flow received from a switch to a corresponding cloud server. Currently, in gateway devices, the processor (usually a CPU) can use the Data Plane Development Kit (DPDK) application to accelerate packet processing. In simple terms, DPDK applications run in the operating system's user space, utilizing their own data plane libraries for packet sending and receiving, bypassing the kernel-mode protocol stack to improve packet processing efficiency. A single CPU handles a large volume of packets, and since this CPU is a general-purpose processor with limited processing power and may also need to handle other tasks, the packet forwarding performance remains low despite the acceleration provided by the DPDK application. This invention discloses a packet forwarding method, gateway device, storage medium, and program to improve packet forwarding performance.In a first aspect, embodiments of this disclosure provide a gateway device, comprising: a plurality of processors, the plurality of processors being configured to encapsulate received packet header information; a network interface card (NIC), the NIC being communicatively connected to the plurality of processors, the NIC including a programmable chip; the programmable chip being configured to receive a first raw data packet sent by a first source device, forward the packet header information of the first raw data packet to a target processor for encapsulation processing, and cache the payload data of the first raw data packet; and, in response to receiving encapsulated packet header information corresponding to the first raw data packet fed back by the target processor, reading the cached payload data of the first raw data packet, generating a first target data packet based on the read payload data of the first raw data packet and the encapsulated packet header information, and sending the first target data packet to a corresponding destination device; wherein, the first raw data packet is any one of the plurality of raw data packets sent by the first source device, the plurality of packet header information corresponding to the plurality of raw data packets are forwarded to different processors for encapsulation processing, and the target processor is one of the plurality of processors. Secondly, this disclosure provides a data packet forwarding method applied to a programmable chip in a gateway device. The gateway device includes multiple processors and network interface cards (NICs), and the programmable chip is located in the NIC. The method includes: receiving a raw data packet sent by a source device, wherein the raw data packet is any one of multiple raw data packets sent by the source device; forwarding the header information of the raw data packet to a target processor for encapsulation processing, wherein the target processor is one of the multiple processors, and wherein multiple header information corresponding to the multiple raw data packets is forwarded to different processors for encapsulation processing; caching the payload data of the raw data packet; in response to receiving encapsulated header information corresponding to the raw data packet fed back by the target processor, reading the cached payload data of the raw data packet; generating a target data packet based on the read payload data of the raw data packet and the encapsulated header information; and sending the target data packet to a corresponding destination device.Thirdly, embodiments of this disclosure provide a data packet forwarding device applied to a programmable chip in a gateway device. The gateway device includes multiple processors and network interface cards (NICs). The programmable chip is located in the NIC. The device includes: a receiving module configured to receive raw data packets sent by a source device, wherein the raw data packet is any one of multiple raw data packets sent by the source device; a first sending module configured to forward the header information of the raw data packet to a target processor for encapsulation processing, wherein the target processor is one of the multiple processors, and wherein multiple header information corresponding to the multiple raw data packets is forwarded to different processors for encapsulation processing; a read / write module configured to cache the payload data of the raw data packet, and, in response to receiving the encapsulated header information corresponding to the raw data packet fed back by the target processor, read the cached payload data of the raw data packet; a generation module configured to generate a target data packet based on the read payload data of the raw data packet and the encapsulated header information; and a second sending module configured to send the target data packet to a corresponding destination device. Fourthly, embodiments of this disclosure provide a non-transitory machine-readable storage medium storing executable code, which, when executed by a programmable chip of a gateway device, enables the programmable chip to at least implement the packet forwarding method as described in the second aspect. Fifthly, embodiments of this disclosure provide a computer program product comprising a computer program, which, when executed by a programmable chip of a gateway device, enables the programmable chip to at least implement the packet forwarding method as described in the second aspect. Sixthly, this disclosure provides a network interface card (NIC), which includes a programmable chip. The NIC is communicatively connected to multiple processors in a gateway device, and is located in the gateway device. The programmable chip is configured to receive raw data packets sent by a source device, forward the header information of the raw data packets to a target processor for encapsulation processing, and cache the payload data of the raw data packets. In response to receiving encapsulated header information corresponding to the raw data packets from the target processor, the chip reads the cached payload data of the raw data packets, generates a target data packet based on the read payload data and the encapsulated header information, and sends the target data packet to a corresponding destination device. The raw data packet is any one of multiple raw data packets sent by the source device, and the header information corresponding to the multiple raw data packets is forwarded to different processors for encapsulation processing. The target processor is one of the multiple processors.The gateway device provided in this embodiment includes multiple processors and a network interface card (NIC) with an internal programmable chip. This leverages the inherent high-speed parallel processing capability of the programmable chip to achieve high-speed forwarding of data packets from the source device to the destination device. To enable high-speed forwarding of data packets from the source device to the destination device via this gateway device, the payload data portion of the data packets is buffered within the programmable chip. Specifically, after receiving a first raw data packet from the first source device, the programmable chip forwards the header information of the first raw data packet to the target processor for encapsulation processing, and simultaneously buffers the payload data of the first raw data packet. The first raw data packet is any one of multiple raw data packets sent by the first source device, and the header information corresponding to these multiple raw data packets is forwarded to different processors for encapsulation processing. Upon receiving the encapsulated header information corresponding to the first raw data packet from the target processor, the buffered payload data of the first raw data packet is read, and the payload data and encapsulated header information of the first raw data packet are concatenated to generate a first target data packet, which is then sent to the destination device. In the aforementioned gateway device architecture, the payload data of data packets is cached at high speed in the programmable chip. The header information is often relatively small, reducing the bandwidth requirements for interaction between the programmable chip and the processor. By distributing the processing tasks of header information for different data packets among multiple processors, the high-speed forwarding of large-volume data packets can be improved, reducing forwarding latency. The accompanying drawings are provided to more clearly illustrate the technical solutions in the embodiments of this disclosure. Obviously, the drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Figure 1 is a schematic diagram of the composition of a gateway device provided in an embodiment of this disclosure; Figure 2 is a schematic diagram of the composition of another gateway device provided in an embodiment of this disclosure; Figure 3 is a schematic diagram of the composition of another gateway device provided in an embodiment of this disclosure; Figure 4 is a schematic diagram of the composition of another gateway device provided in an embodiment of this disclosure; Figure 5 is a schematic diagram of the composition of another gateway device provided in an embodiment of this disclosure; Figure 6 is a flowchart of a data packet forwarding method provided in an embodiment of this disclosure; Figure 7 is a structural schematic diagram of a data packet forwarding device provided in an embodiment of this disclosure. To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of this disclosure, but not all embodiments.Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure. It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in the embodiments of this disclosure are all information and data authorized by the user or fully authorized by all parties. Furthermore, the collection, use, and processing of related data must comply with the relevant laws, regulations, and standards of the relevant countries and regions, and corresponding operation entry points are provided for users to choose to authorize or refuse. The following describes some embodiments of this disclosure in detail with reference to the accompanying drawings. Where there is no conflict between the embodiments, the following embodiments and features in the embodiments can be combined with each other. In addition, the timing of the steps in the following method embodiments is only an example and not a strict limitation. First, some concepts involved in the embodiments of this disclosure will be explained. Gateway device: This can be a gateway-type forwarding node in application scenarios such as data centers, and is the convergence point of traffic. Field-Programmable Gate Array (FPGA): A programmable chip, a type of integrated circuit that can be reconfigured at the hardware level. Random Access Memory (RAM): RAM is internally composed of small memory cells.

[0002] BRAM, or Block RAM, is a dedicated RAM resource within an FPGA chip, fixedly located in a specific area inside the FPGA chip. Round Robin (RR) algorithm: In the packet distribution process described below, it refers to distributing packets to various CPUs in a round-robin fashion for processing. Weighted Round Robin (WRR) algorithm: Adds weights to the simple round-robin scheduling algorithm. To cope with high bandwidth-consuming network traffic such as elephant flows, currently, in gateway devices, CPUs can use DPDK applications to accelerate packet forwarding. Currently, one elephant flow is centrally processed by a single CPU (i.e., one CPU core). Since CPUs are general-purpose processors with limited processing power and may also need to handle other tasks, even with acceleration through DPDK applications, packet forwarding performance remains unsatisfactory. In view of this, this disclosure provides a novel network interface card (NIC) structure, which includes a programmable chip, such as an FPGA chip, to achieve high-speed forwarding of data packets from source devices to destination devices by leveraging its high-speed parallel processing capabilities. In summary, the programmable chip in the NIC receives raw data packets corresponding to various network traffic streams from one or more source devices, distributes the header information of different raw data packets to different CPUs for processing, such as encapsulating the header information and caching the payload data of the raw data packets locally on the programmable chip. Finally, the programmable chip receives the encapsulated header information from each CPU, concatenates it with the corresponding cached payload data to obtain the corresponding target data packet, and forwards the target data packet to the corresponding destination device. This network traffic diversion protects the CPU, preventing excessive load on a single CPU's data packet processing task. Moreover, distributing only the header information to the CPU for encapsulation further reduces the CPU's processing load, contributing to high-performance data packet forwarding. However, this requires implementing a certain capacity of high-speed caching within the programmable chip. Therefore, this disclosure proposes a high-performance data caching design based on a programmable chip, which can cache data packets (mainly their payload data) that need to be forwarded at high speed, reducing the interaction bandwidth between the programmable chip and the CPU, thereby improving the data packet forwarding rate of the network card and reducing forwarding latency. Furthermore, it has the ability to prevent duplicate cache release and cache leakage in scenarios such as CPU packet loss and duplicate packet transmission. The following section, with reference to Figure 1, describes the composition structure of the gateway device provided in this disclosure embodiment.Figure 1 is a schematic diagram of the composition of a gateway device provided in an embodiment of this disclosure. As shown in Figure 1, the gateway device includes multiple processors and network interface cards (NICs), and the NICs include programmable chips. In this context, multiple processors can typically be multiple CPUs, such as CPU1, CPU2, ..., CPUn shown in Figure 1. The programmable chip can be, for example, the FPGA chip shown in Figure 1, but is not limited to this; other dedicated integrated chips can also be used. The following explanation uses CPUs as the processors and FPGA chips as the programmable chip. In summary, for any network traffic sent by any source device, the FPGA chip receives individual data packets corresponding to that network traffic sent by the source device (data packet reception; for clarity, the data packets sent by the source device are referred to as raw data packets). It then sequentially distributes the header information of different raw data packets to different CPUs for encapsulation processing (header distribution) and caches the payload data of each raw data packet locally (payload data caching). Each raw data packet consists of two parts: header information and payload data. The header information includes information such as the source IP address, source port number, destination IP address, destination port number, and protocol number. The payload data is the actual data content being transmitted. Taking the FPGA chip receiving the first raw data packet sent by the first source device as an example... On one hand, the header information of the first raw data packet is forwarded to the target CPU for encapsulation processing; on the other hand, the payload data of the first raw data packet is cached. The first raw data packet is any one of multiple raw data packets sent by the first source device. The header information corresponding to these multiple raw data packets is forwarded to different CPUs for encapsulation processing. When the FPGA chip receives the encapsulated header information corresponding to the first raw data packet from the target CPU, it reads the cached payload data of the first raw data packet, concatenates the payload data and the encapsulated header information to generate the first target data packet, and sends the first target data packet to the destination device. In practical applications, the source device can be a switch or similar device, and the destination device can be a cloud server. The target CPU can be one of the multiple CPUs shown in Figure 1. In practical applications, the FPGA chip can use a pre-defined scheduling algorithm, such as the Round Robin (RR) algorithm, to poll and distribute the header information of the raw data packet to the CPU. Due to the high-speed parallel processing advantage of programmable chips such as FPGAs, data packets sent by multiple source devices can be forwarded in parallel, achieving better forwarding performance.In the aforementioned gateway device architecture, multiple CPUs and FPGA chips work together to share the task of encapsulating and processing the header information of a large number of raw data packets. Compared to a single CPU processing all raw data packets of a single network traffic stream, this results in faster processing efficiency. Furthermore, the payload data of the raw data packets is cached at high speed within the FPGA chip. Since the header information is often relatively small, this reduces the bandwidth requirements between the FPGA chip and the CPU, enabling faster data transmission between them. This improves the high-speed forwarding of large volumes of data packets and reduces forwarding latency. Figure 2 is a schematic diagram of another gateway device provided in this embodiment. As shown in Figure 2, based on the gateway device architecture shown in Figure 1, the FPGA chip includes a cache management system. The FPGA chip primarily uses this cache management system to cache and read / write the payload data of the raw data packets. To forward the original data packets, the FPGA chip, in addition to using the cache management system, needs to perform actions that interact with the cache management system and with the source and destination devices. In this paper, these actions can be described as actions performed by the FPGA chip. In practical applications, the FPGA chip can contain program code to perform these actions, called a forwarding program. The FPGA chip can specifically use this forwarding program to execute these actions. The cache management system is built upon the BRAM resources within the FPGA chip and consists of multiple hardware units. In fact, besides the aforementioned cache management system, the FPGA chip also includes some peripheral hardware units, and the forwarding program is code burned into these peripheral hardware units.

[0003] The FPGA chip, through the cooperation of the forwarding program and the cache management system, realizes the forwarding processing of raw data packets sent by various source devices. Taking the first raw data packet sent by the first source device as an example, the forwarding process is as follows: The forwarding program receives the first raw data packet, that is, the raw data packet of multiple network traffic sent by multiple source devices, forwards the header information of the first raw data packet to the target CPU for encapsulation processing, and sends the payload data of the first raw data packet to the cache management system, that is, writes the payload data of the multiple data packets; The cache management system caches the payload data of the first raw data packet; In response to receiving the encapsulated header information of the first raw data packet fed back by the target CPU, the forwarding program triggers a read request to the cache management system corresponding to the first raw data packet; The cache management system reads the cached payload data of the first raw data packet based on the read request, that is, reads the payload data of the multiple data packets, and feeds back the read payload data of the first raw data packet to the forwarding program; The forwarding program generates the first target data packet based on the payload data of the first raw data packet and the encapsulated header information, that is, the data packet after splicing multiple network traffic, and sends the first target data packet to the corresponding destination device. As described above, the forwarding program is mainly used to interact with the CPU to complete the distribution and reception of packet header information, while the cache management system is mainly used to write and read payload data to and from the cache space. In practical applications, the FPGA chip can support a set number of parallel channels, that is, it can simultaneously access the network traffic of multiple source devices. For example, as shown in Figure 2, the number of parallel channels is 4, so the cache management system also provides 4 read / write channels to support the writing and reading of 4 network traffic streams. The first original data packet sent by the first source device is a data packet corresponding to one of the network traffic streams. The two forwarding programs shown in Figure 2 are actually one; they are only drawn for ease of illustration. As shown in Figure 3, in an optional embodiment, the cache management system may include the following hardware units: a write scheduling unit (multi-channel), a read scheduling unit (multi-channel), and a cache unit. Taking the first raw data packet sent by the first source device as an example, the specific working process of these hardware units during the forwarding of the first raw data packet is as follows: The write scheduling unit receives the payload data of the first raw data packet sent by the forwarding program and stores the payload data of the first raw data packet into the buffer unit; The read scheduling unit receives the read request sent by the forwarding program, reads the payload data of the first raw data packet from the buffer unit based on the read request, and feeds back the read payload data of the first raw data packet to the forwarding program.Specifically, after receiving the first raw data packet from the first source device, the forwarding program parses the header information and distributes it to the determined target CPU according to a set scheduling algorithm (such as RR algorithm, WRR algorithm, etc.). The remaining payload data is sent to the cache management system, where it is received by the write scheduling unit. The write scheduling unit writes the payload data of the first raw data packet into the cache unit for caching. In an optional embodiment, the write scheduling unit can obtain the cache address corresponding to the payload data in the cache unit and feed this cache address back to the forwarding program. The forwarding program can then establish a correspondence between the first raw data packet and the cache address, for example, by establishing a correspondence between a certain identifier of the first raw data packet and the cache address. Subsequently, when the forwarding program receives the encapsulated header information corresponding to the first raw data packet from the target CPU, it can trigger a read request corresponding to the first raw data packet to the cache management system, which is received by the read scheduling unit in the cache management system. The header information before and after encapsulation can be associated with the aforementioned identifier, allowing the forwarding program to determine that the received encapsulated header information corresponds to the first raw data packet. Furthermore, the read request sent by the forwarding program contains the aforementioned cache address. Therefore, the read scheduling unit can read the data at the corresponding address in the cache unit—that is, the payload data in the first original data packet—based on the cache address included in the read request, and feed it back to the forwarding program. The forwarding program can then concatenate the payload data of the first original data packet and the encapsulated header information received from the target CPU to obtain the first target data packet and send it to the corresponding destination device. As mentioned above, when the cache management unit can support, for example, concurrent processing of four channels, the write scheduling unit provides four write channels (or write interfaces), and the read scheduling unit provides four read channels (or read interfaces) to support simultaneous processing of four network traffic streams. In practical applications, the write scheduling unit can be considered to respond instantly; that is, whenever payload data is received from an original data packet, it is immediately written to the cache unit for caching. The read scheduling unit can set up a queue for each read channel to cache read requests. When the cache management system can handle concurrent processing across multiple channels, the issue of concurrent scheduling arises. Taking the write scheduling unit as an example, if the write scheduling unit concurrently receives the first-shot payload data of the first original data packet and the first-shot payload data of the second original data packet sent by the forwarding program, it determines, based on the set scheduling algorithm, to prioritize writing the multi-shot payload data of the first original data packet, wherein the second original data packet is sent by the second source device.This scenario assumes that the scheduling algorithm's result indicates that the multi-phase payload data of the first original data packet should be written first. Firstly, it is assumed that the first and second source devices concurrently send original data packets to the FPGA chip. One original data packet sent by the first source device is called the first original data packet, and one original data packet sent by the second source device is called the second original data packet. Secondly, taking the payload data contained in the first original data packet as an example, optionally, the forwarding program can perform multi-phase segmentation on this payload data to obtain multi-phase payload data. This segmentation can be based on a set data size (e.g., 64 bytes). Then, the forwarding program transmits this multi-phase payload data to the write scheduling unit step-by-step through a write channel. Similarly, the payload data in the second original data packet is also segmented into multi-phase payload data and sent to the write scheduling unit step-by-step. In the above embodiment, in the write scheduling unit, each write channel initiates competition when the first phase of payload data is written. The competition is determined by a set scheduling algorithm (e.g., the RR algorithm), and the selected write channel can continuously write the corresponding multi-phase payload data. The first payload data refers to the first payload data in the aforementioned multi-payload data. For ease of understanding, for example, the multi-payload data of the first original data packet is arranged sequentially as follows: A1, A2, A3…An; the multi-payload data of the second original data packet is arranged sequentially as follows: B1, B2, B3…Bn. The first original data packet corresponds to write channel C1, and the second original data packet corresponds to write channel C2. In practical applications, the write scheduling unit can schedule once per clock cycle (not limited to this). Each time it schedules, it checks whether the "first" payload data has been received through the provided multiple write channels. Assuming there are four write channels C1-C4, and at the current scheduling time t1, it is found that no first-shot payload data has been received through any of these four write channels, then no scheduling processing is performed; simply write the non-first-shot payload data received through these four channels into the buffer unit. If, at this time, write channels C1 and C2 have no payload data being written, while write channels C3 and C4 are respectively writing non-first-shot payload data from, for example, a third source device and a fourth source device, a third original data packet and a fourth original data packet, then the write scheduling unit simply writes the non-first-shot payload data from the third original data packet and the fourth original data packet into the buffer unit respectively.Under the above assumptions, C3 and C4 of the four write channels will be continuously occupied by the third and fourth original data packets until the last bit of payload data of the third and fourth original data packets is written. Only then will channels C3 and C4 participate in subsequent scheduling. Further assuming that at the next scheduling time t2, it is found that the first bit of payload data of the first original data packet and the first bit of payload data of the second original data packet are written through write channels C1 and C2, these two first bit payload data will trigger contention. That is, the write scheduling unit will use the set scheduling algorithm to determine whether the first bit of payload data of the first original data packet or the first bit of payload data of the second original data packet is currently scheduled. Assuming the Round Robin (RR) algorithm is used, with a polling order of C1, C2, C3, C4, in the example scenario above, since channels C3 and C4 are occupied, let's assume that channel C1 is polled first. If the first payload data of the first raw data packet is found on channel C1, then the contention for the first payload data of the first raw data packet is successful. The write scheduling unit prioritizes writing the first payload data of the first raw data packet into the buffer unit, and subsequent payload data of the first raw data packet are continuously received through channel C1 and written into the buffer unit. Since the first payload data of the second raw data packet, received through channel C2, was not successfully polled in this round, it waits for the next scheduling time t3 to participate in the next round of polling. Assuming that at scheduling time t3, channels C1, C3, and C4 are all transmitting non-first-shot payload data, then the first-shot payload data of the second original data packet corresponding to channel C2 successfully competes for. The write scheduling unit writes the first-shot payload data of the second original data packet into the buffer unit, and subsequent payload data of the second original data packet are continuously received through channel C2 and written into the buffer unit. The above describes the concurrent scheduling logic for the write scheduling unit; the concurrent scheduling logic for read requests in the read scheduling unit is similar. Assuming the read scheduling unit provides four read channels C5-C8, each read channel has a corresponding queue used to buffer read requests sent by the forwarding program through the corresponding read channel. Taking the first original data packet as an example, since its multi-shot payload data often needs to be stored in multiple buffer addresses in the buffer unit, optionally, the read request sent by the forwarding program to the read scheduling unit can sequentially include these multiple buffer addresses.When the read scheduling unit starts processing read requests at the head of different queues, it needs to read the corresponding payload data based on the first cache address. At this time, multiple queues compete for data, so the read scheduling unit can schedule the requests using algorithms such as Recursive Round Robin (RR). Assuming the read request corresponding to the first original data packet succeeds in the competition and is successfully scheduled, the read scheduling unit can continuously read the payload data of each cache iteration of the first original data packet. After reading, the corresponding read channel participates in the next scheduling iteration. Based on the parallel processing capability of the FPGA chip, the above-mentioned cache management system that supports multi-channel parallel processing can realize the parallel forwarding processing of multiple network traffic, thereby improving the forwarding performance of data packets. In another optional embodiment, as shown in Figure 4, the cache management system may also include a pointer management unit (pointer marking, timeout reclamation). The pointer management unit is used to manage pointers pointing to different cache addresses in the cache unit. The above-mentioned write scheduling unit (multi-channel) and read scheduling unit (multi-channel) can write and read the payload data of the first original data packet based on the pointers provided by the pointer management unit. Specifically, when the write scheduling unit receives the payload data of the first raw data packet (such as the payload data of each cycle mentioned above) sent by the forwarding program, it obtains an available target pointer from the pointer management unit. That is, the pointer management unit allocates a target pointer to the write scheduling unit, stores the payload data of the first raw data packet into the corresponding target cache address in the cache unit based on the target pointer, and sends the target pointer to the forwarding program. Here, the target pointer refers to multiple pointers corresponding to the multi-cycle payload data of the first raw data packet; one pointer can be used to write at least one cycle of payload data. The target cache address is the cache address corresponding to the target pointer. Based on the received target pointer, when the forwarding program triggers a read request corresponding to the first raw data packet to the read scheduling unit, it can include the target pointer in the read request. Thus, the read scheduling unit reads the payload data of the first raw data packet from the cache unit based on the target pointer included in the read request. In practical applications, the pointer management unit mainly provides pointer allocation and release / reclaim functions. Assuming there are N cache addresses in the cache unit, the pointer management unit maintains N pointers corresponding to the N cache addresses. In the pointer management unit, a status flag is used to record the usage status of each pointer. The usage status of a pointer can include an occupied state and a released state. Pointers that are currently in use and have been allocated to the write scheduling unit are in the occupied state, while pointers that have not been allocated or have been reclaimed after allocation can be considered to be in the released state.By using status flags, the duplicate allocation and release of the same pointer can be prevented. That is, a pointer can only be allocated once at a time, and can only be allocated again after being reclaimed and released. Furthermore, once a pointer is released, it cannot be released twice consecutively unless it is reassigned, as this would cause an error. Based on this, taking the forwarding process of the first original data packet as an example, after receiving the payload data of the first original data packet sent by the forwarding program (which could be after receiving each packet of payload data), the write scheduling unit sends a request instruction to the pointer management unit. The pointer management unit, based on the status flags of each pointer it maintains, allocates a target pointer that may not be occupied to the write scheduling unit, marking the target pointer as occupied. Thus, the write scheduling unit completes the writing of the payload data to the corresponding cache address based on the allocated target pointer and sends the target pointer to the forwarding program. After receiving the encapsulated header information of the first raw data packet from the target CPU, the forwarding program triggers a read request containing the target pointer to the read scheduling unit. Based on the target pointer included in the read request, the read scheduling unit reads the payload data of the first raw data packet from the cache unit and sends a release instruction corresponding to the target pointer to the pointer management unit. Thus, the pointer management unit marks the target pointer as being in a released state based on this release instruction. Optionally, the pointer management unit can also provide a pointer timeout reclamation function to prevent cache leaks. Specifically, if the pointer management unit determines that the target pointer has been in an occupied state for a set duration, it changes the target pointer's state to a released state, i.e., reclaims the target pointer. In practical applications, the target CPU may, due to high load or other reasons, delay the encapsulation processing of the header information of the distributed first raw data packet, causing the forwarding program to not receive the encapsulated header information from the target CPU for a long time, thus preventing the triggering of the read request. To improve pointer utilization, after assigning the target pointer (which may actually include multiple pointers) to the write scheduling unit for writing the payload data of the first raw data packet, the pointer management unit will automatically mark the target pointer as released if it does not receive a release instruction for the target pointer within a set time period. This avoids the problem of the target pointer remaining unusable due to the target CPU not providing the encapsulated header information. For example, if the target CPU fails to receive the header information or loses it due to a runtime error, the target CPU will not provide the encapsulated header information.However, if the target CPU only delays in feeding back the encapsulated header information, and the pointer management unit has already marked the target pointer as released based on the timeout reclamation function, then after the read scheduling unit successfully reads the payload data of the first original data packet based on the target pointer included in the received read request, it sends a release instruction to the pointer management unit. In this case, the pointer management unit will discard the release instruction because the target pointer has already been marked as released, thus preventing the same pointer from being repeatedly marked as released. Furthermore, assuming an anomaly in the target CPU causes the same encapsulated header information to be fed back repeatedly, the forwarding program may repeatedly trigger the same read request to the read scheduling unit. In this case, based on the first read request, the read scheduling unit has already triggered the target pointer release instruction to the pointer management unit, marking the target pointer as released. Therefore, subsequent identical read requests will not be marked as released again by the pointer management unit, thus preventing duplicate releases. In practical applications, optionally, when a pointer is marked as released, the corresponding release time can also be marked, so that when allocating available pointers again, they can be reallocated in order of release time from earliest to latest. Pointers marked as released are all available pointers; initially, all pointers can be marked as released. Based on the management of pointers to cache addresses by the above pointer management unit, efficient use of the cache unit can be achieved. In another optional embodiment, as shown in Figure 5, the cache management system may further include a linked list management unit. This linked list management unit is mainly used to record the multiple pointers occupied by the payload data of an original data packet. Taking the forwarding process of the first original data packet as an example, the forwarding program splits the payload data of the first original data packet into multi-phase payload data and sends the multi-phase payload data sequentially to the write scheduling unit. The write scheduling unit then sequentially retrieves multiple available pointers (i.e., the target pointers mentioned above) from the pointer management unit. Based on these pointers, it stores multi-frame payload data into corresponding cache addresses in the cache unit. It also sequentially sends these pointers, i.e., the target pointer linked list information, to the linked list management unit, and can send the first pointer among the pointers to the forwarding program. The first pointer corresponds to the first frame of payload data. In practice, one pointer can be used to store at least one frame of payload data; therefore, the first pointer corresponding to the first frame of payload data can be used to write the first frame of payload data and the subsequent frames of payload data. Afterward, the linked list management unit generates linked list information for these pointers, indicating that these pointers correspond to the same original data packet and the order of the pointers.Assuming the write scheduling unit obtains multiple pointers from the pointer management unit for each payload data iteration of the first original data packet, namely R0, R1, R2, and R3, then after sending these four pointers sequentially (i.e., the target pointer linked list information) to the linked list management unit, the linked list management unit organizes these four pointers into a linked structure and marks them sequentially within this linked structure. Based on the linked list management unit's chained management of multiple pointers corresponding to the same original data packet, the pointer that the write scheduling unit feeds back to the forwarding program can be the first pointer among these multiple pointers, without needing to feed back all of them. Therefore, when the forwarding program receives the encapsulated header information of the first original data packet, it only needs to include this first pointer in the read request sent to the read scheduling unit. Based on the first pointer included in the read request, the read scheduling unit queries the linked list management unit to obtain the multiple pointers mentioned above, and then reads the multi-step payload data of the first original data packet from the cache unit based on these retrieved pointers. Specifically, the read scheduling unit inputs the aforementioned first pointer to the linked list management unit. The linked list management unit determines the linked list structure starting with the first pointer from the maintained linked list information and feeds back the aforementioned multiple pointers contained in the linked list structure to the read scheduling unit. In summary, in this embodiment of the present disclosure, by using an FPGA chip and multiple CPUs to share the forwarding processing task of a large number of data packets, a faster forwarding speed can be obtained. Moreover, by setting up multiple hardware units such as a cache unit in the FPGA chip, not only can the payload data with a large proportion of data in the data packets be cached at high speed in the FPGA chip, reducing the interaction bandwidth requirements between the FPGA chip and the CPU, but also the cache resources can be used efficiently, which helps to obtain better data packet forwarding performance. This embodiment of the present disclosure provides a network interface card (NIC) that includes a programmable chip. The NIC is communicatively connected to multiple processors in a gateway device, and the NIC is located in the gateway device. The programmable chip is used to receive raw data packets sent by a source device, forward the header information of the raw data packets to a target processor for encapsulation processing, and cache the payload data of the raw data packets; and, in response to receiving the encapsulated header information corresponding to the raw data packets fed back by the target processor, read the cached payload data of the raw data packets, generate a target data packet based on the read payload data of the raw data packets and the encapsulated header information, and send the target data packet to the corresponding destination device. Figure 6 is a flowchart of a data packet forwarding method provided in an embodiment of this disclosure. This data packet forwarding method is applied to a programmable chip in a gateway device, which includes multiple processors and network interface cards (NICs), with the programmable chip located in the NIC. As shown in Figure 6, the method may include the following steps:

[0004] 601. Receive a raw data packet sent by the source device, which is any one of multiple raw data packets sent by the source device.

[0005] 602. The header information of the original data packet is forwarded to the target processor for encapsulation processing, and the payload data of the original data packet is cached. The target processor is one of multiple processors, and the header information corresponding to multiple original data packets is forwarded to different processors for encapsulation processing.

[0006] 603. In response to receiving the encapsulated header information corresponding to the original data packet fed back by the target processor, read the payload data of the cached original data packet. 604. Generate a target data packet based on the read payload data of the original data packet and the encapsulated header information, and send the target data packet to the corresponding destination device. The internal composition of the programmable chip and the specific processing procedure can be referred to the relevant descriptions in the foregoing embodiments, and will not be repeated here. The following will describe in detail one or more embodiments of the data packet forwarding device of this disclosure. Those skilled in the art will understand that these devices can all be configured using commercially available hardware components through the steps taught in this solution. Figure 7 is a schematic diagram of the structure of a data packet forwarding device provided in an embodiment of this disclosure. The device is applied to a programmable chip in a network card. The network card is located in a gateway device, and the gateway device also includes multiple processors that are communicatively connected to the network card. As shown in Figure 7, the device includes: a receiving module 11, a first sending module 12, a read / write module 13, a generating module 14, and a second sending module 15. oA receiving module 11 is used to receive raw data packets sent by a source device, wherein the raw data packet is any one of a plurality of raw data packets sent by the source device. A first sending module 12 is used to forward the header information of the raw data packet to a target processor for encapsulation processing, wherein the target processor is one of the plurality of processors, wherein the header information corresponding to the plurality of raw data packets is forwarded to different processors for encapsulation processing. A read / write module 13 is used to cache the payload data of the raw data packet, and, in response to receiving the encapsulated header information corresponding to the raw data packet fed back by the target processor, read the cached payload data of the raw data packet. A generating module 14 is used to generate a target data packet based on the read payload data of the raw data packet and the encapsulated header information. A second sending module 15 is used to send the target data packet to the corresponding destination device. The device shown in Figure 7 can execute the steps executed by the programmable chip in the foregoing embodiments. For detailed execution process and technical effects, please refer to the description in the foregoing embodiments, which will not be repeated here. Furthermore, this disclosure provides a non-transitory machine-readable storage medium storing executable code. When the executable code is executed by a programmable chip in a gateway device, the programmable chip can at least implement the packet forwarding method provided in the foregoing embodiments. The device embodiments described above are merely illustrative. The network elements described as separate components may or may not be physically separate. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without creative effort. Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of necessary general-purpose hardware platforms, or by a combination of hardware and software. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a computer product. This disclosure can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit it. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this disclosure. Industrial Applicability The gateway device provided in the embodiments of this disclosure includes multiple processors and a network card with a programmable chip inside. Thus, the high-speed parallel processing advantage inherent in the programmable chip can be used to achieve high-speed forwarding of data packets sent by the source device to the destination device. In order to achieve high-speed forwarding of data packets sent by the source device to the destination device through this gateway device, the payload data part of the data packet is cached inside the programmable chip. Specifically, after the programmable chip receives the first original data packet sent by the first source device, on the one hand, it forwards the header information of the first original data packet to the target processor for encapsulation processing, and on the other hand, it caches the payload data of the first original data packet. In this architecture, the first raw data packet is any one of multiple raw data packets sent by the first source device. The header information corresponding to these multiple raw data packets is forwarded to different processors for encapsulation processing. Upon receiving the encapsulated header information corresponding to the first raw data packet from the target processor, the payload data of the cached first raw data packet is read, and the payload data and encapsulated header information are concatenated to generate the first target data packet. This first target data packet is then sent to the destination device. In this gateway device architecture, the payload data of the data packets is cached at high speed in the programmable chip. The header information is often relatively small, which reduces the bandwidth requirements for interaction between the programmable chip and the processor. By distributing the processing tasks of the header information of different data packets among multiple processors, the high-speed forwarding of large volumes of data packets can be improved, and forwarding latency can be reduced.

Claims

Claims 1. A gateway device, comprising: Multiple processors are used to encapsulate the received packet header information; A network interface card (NIC) is communicatively connected to the plurality of processors, and the NIC includes a programmable chip. The programmable chip is used to receive a first raw data packet sent by a first source device, forward the header information of the first raw data packet to a target processor for encapsulation processing, and cache the payload data of the first raw data packet. In response to receiving the encapsulated header information corresponding to the first original data packet fed back by the target processor, the payload data of the cached first original data packet is read, a first target data packet is generated based on the read payload data of the first original data packet and the encapsulated header information, and the first target data packet is sent to the corresponding destination device. Wherein, the first original data packet is any one of a plurality of original data packets sent by the first source device, and the header information corresponding to the plurality of original data packets is forwarded to different processors for encapsulation processing, and the target processor is one of the plurality of processors.

2. The gateway device according to claim 1, wherein, The programmable chip includes a cache management system; the programmable chip is used to receive the first original data packet, forward the header information of the first original data packet to the target processor for encapsulation processing, and send the payload data of the first original data packet to the cache management system; The cache management system is used to cache the payload data of the first original data packet; The programmable chip is configured to, in response to receiving the encapsulated header information corresponding to the first original data packet fed back by the target processor, trigger a read request corresponding to the first original data packet to the cache management system; the cache management system is configured to read the payload data of the cached first original data packet based on the read request, and feed back the read payload data of the first original data packet to the programmable chip. The programmable chip is used to generate the first target data packet based on the payload data of the first original data packet and the encapsulated header information, and send the first target data packet to the corresponding destination device.

3. The gateway device according to claim 2, wherein, The cache management system includes: a write scheduling unit, a read scheduling unit, and a cache unit; the write scheduling unit is used to receive the payload data of the first original data packet sent by the programmable chip, and store the payload data of the first original data packet into the cache unit; the read scheduling unit is used to receive the read request sent by the programmable chip, read the payload data of the first original data packet from the cache unit based on the read request, and feed back the read payload data of the first original data packet to the programmable chip.

4. The gateway device according to claim 3, wherein, The cache management system further includes: a pointer management unit, which manages pointers to different cache addresses in the cache unit; and a write scheduling unit, which obtains an available target pointer from the pointer management unit, stores the payload data of the first original data packet into the corresponding target cache address in the cache unit based on the target pointer, and sends the target pointer to the programmable chip. The read scheduling unit is used to read the payload data of the first original data packet from the cache unit based on the target pointer contained in the read request.

5. The gateway device according to claim 4, wherein, The write scheduling unit is configured to send an application instruction to the pointer management unit after receiving the payload data of the first original data packet; the pointer management unit is configured to allocate the target pointer, which may not be occupied, to the write scheduling unit according to the status flags of each maintained pointer, and mark the target pointer as occupied; the read scheduling unit is configured to send a release instruction corresponding to the target pointer to the pointer management unit after reading the payload data of the first original data packet; the pointer management unit is configured to mark the target pointer as released based on the release instruction.

6. The gateway device according to claim 5, wherein, The pointer management unit is further configured to change the state of the target pointer to a released state if it is determined that the target pointer has been in an occupied state for a set duration.

7. The gateway device according to any one of claims 4-6, wherein, The cache management system further includes: a linked list management unit; the programmable chip, specifically configured to split the payload data of the first original data packet into multi-phase payload data, and sequentially send the multi-phase payload data to the write scheduling unit; the write scheduling unit, specifically configured to sequentially obtain multiple available pointers from the pointer management unit, store the multi-phase payload data into multiple corresponding cache addresses in the cache unit based on the multiple pointers, and sequentially send the multiple pointers to the linked list management unit, sending the first pointer among the multiple pointers to the programmable chip; the linked list management unit, configured to generate linked list information for the multiple pointers, the linked list information indicating that the multiple pointers correspond to the same data packet and the order of the multiple pointers; and the read scheduling unit, specifically configured to query the linked list management unit based on the first pointer included in the read request to obtain the multiple pointers, and read the multi-phase payload data from the cache unit based on the multiple pointers.

8. The gateway device according to any one of claims 3-6, wherein, The write scheduling unit is further configured to, if concurrently receiving the first-shot payload data of the first original data packet and the first-shot payload data of the second original data packet sent by the programmable chip, determine, based on a set scheduling algorithm, to prioritize writing the multi-shot payload data of the first original data packet, wherein the second original data packet is sent by the second source device.

9. A network interface card (NIC), the NIC including a programmable chip, the NIC being communicatively connected to a plurality of processors in a gateway device, the NIC being located in the gateway device; The programmable chip is used to receive raw data packets sent by the source device, forward the header information of the raw data packets to the target processor for encapsulation processing, and cache the payload data of the raw data packets; In response to receiving the encapsulated header information corresponding to the original data packet from the target processor, the payload data of the cached original data packet is read, a target data packet is generated based on the read payload data of the original data packet and the encapsulated header information, and the target data packet is sent to the corresponding destination device; wherein, the original data packet is any one of a plurality of original data packets sent by the source device, the plurality of header information corresponding to the plurality of original data packets is forwarded to different processors for encapsulation processing, and the target processor is one of the plurality of processors. 16 10. A packet forwarding method, applied to a programmable chip in a network interface card (NIC), the NIC being located in a gateway device, the gateway device including multiple processors, the method comprising: Receive raw data packets sent by the source device, wherein the raw data packets are any one of a plurality of raw data packets sent by the source device; The header information of the original data packet is forwarded to a target processor for encapsulation processing. The target processor is one of the plurality of processors, wherein the header information corresponding to the plurality of original data packets is forwarded to different processors for encapsulation processing; the payload data of the original data packet is cached; in response to receiving the encapsulated header information corresponding to the original data packet fed back by the target processor, the cached payload data of the original data packet is read; a target data packet is generated based on the read payload data of the original data packet and the encapsulated header information; and the target data packet is sent to the corresponding destination device.

1. The data packet forwarding method according to claim 10, wherein, The programmable chip includes a cache management system; it receives the first raw data packet, forwards the header information of the first raw data packet to the target processor for encapsulation processing, and sends the payload data of the first raw data packet to the cache management system; The cache management system is used to cache the payload data of the first original data packet; In response to receiving the encapsulated header information corresponding to the first original data packet from the target processor, a read request corresponding to the first original data packet is triggered to the cache management system; using the cache management system, the payload data of the cached first original data packet is read based on the read request, and the read payload data of the first original data packet is fed back to the programmable chip; the first target data packet is generated based on the payload data of the first original data packet and the encapsulated header information, and the first target data packet is sent to the corresponding destination device.

12. The data packet forwarding method according to claim 11, wherein, The cache management system includes: a write scheduling unit, a read scheduling unit, and a cache unit; the write scheduling unit receives the payload data of the first original data packet sent by the programmable chip and stores the payload data of the first original data packet in the cache unit; the read scheduling unit receives the read request sent by the programmable chip, reads the payload data of the first original data packet from the cache unit based on the read request, and feeds back the read payload data of the first original data packet to the programmable chip.

13. The data packet forwarding method according to claim 12, wherein, The cache management system further includes: a pointer management unit, which manages pointers to different cache addresses in the cache unit; using the write scheduling unit, obtaining an available target pointer from the pointer management unit, storing the payload data of the first original data packet into the corresponding target cache address in the cache unit based on the target pointer, and sending the target pointer to the programmable chip; and using the read scheduling unit, reading the payload data of the first original data packet from the cache unit based on the target pointer included in the read request.

14. The data packet forwarding method according to claim 13, wherein, The write scheduling unit, after receiving the payload data of the first raw data packet, sends a request instruction to the pointer management unit; and, using the pointer management unit, allocates the target pointer, which may not be occupied, to the write scheduling unit according to the maintained status flags of each pointer, and marks it.

17. The target pointer is currently in an occupied state; Using the read scheduling unit, after reading the payload data of the first original data packet, a release instruction corresponding to the target pointer is sent to the pointer management unit; using the pointer management unit, based on the release instruction, the target pointer is marked as being in a released state.

15. The data packet forwarding method according to claim 14, wherein, The pointer management unit is further configured to change the state of the target pointer to a released state if it is determined that the target pointer has been in an occupied state for a set duration.

16. The data packet forwarding method according to any one of claims 13-15, wherein, The cache management system further includes: a linked list management unit; splitting the payload data of the first original data packet into multi-phase payload data, and sequentially sending the multi-phase payload data to the write scheduling unit; using the write scheduling unit, sequentially obtaining multiple available pointers from the pointer management unit, storing the multi-phase payload data into multiple corresponding cache addresses in the cache unit based on the multiple pointers, and sequentially sending the multiple pointers to the linked list management unit, sending the first pointer among the multiple pointers to the programmable chip; using the linked list management unit, generating linked list information of the multiple pointers, the linked list information indicating that the multiple pointers correspond to the same data packet and the order of the multiple pointers; using the read scheduling unit, querying the linked list management unit based on the first pointer included in the read request to obtain the multiple pointers, and reading the multi-phase payload data from the cache unit based on the multiple pointers.

17. The data packet forwarding method according to any one of claims 13-15, wherein, The write scheduling unit is further configured to, if concurrently receiving the first-shot payload data of the first original data packet and the first-shot payload data of the second original data packet sent by the programmable chip, determine, based on a set scheduling algorithm, to prioritize writing the multi-shot payload data of the first original data packet, wherein the second original data packet is sent by the second source device.

18. A non-transitory machine-readable storage medium storing executable code, wherein when the executable code is executed by a programmable chip of a gateway device, the programmable chip performs the packet forwarding method as described in any one of claims 10 to 17.

19. A computer program product, comprising: A computer program, when executed by a programmable chip of a gateway device, causes the programmable chip to perform the packet forwarding method as described in any one of claims 10 to 17.

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