Smart IC substrate, smart IC module, and IC card comprising same

Abstract

A smart IC substrate according to an embodiment comprises: a substrate; a metal layer disposed on the substrate; and a cover layer disposed on the metal layer, wherein the substrate has through-holes passing through one surface and the other surface opposite to the one surface, and the cover layer includes a first cover layer disposed on one surface of the metal layer and a second cover layer disposed on the other surface of the metal layer, which vertically overlaps the through-holes, the first cover layer and the second cover layer comprising different materials, and the first cover layer comprising a nitride.

Description

Smart IC substrate, smart IC module and IC card including the same

[0001] The present invention relates to a smart IC substrate, and more particularly to a smart IC substrate including a nitride and a method for manufacturing the same.

[0002] An IC card is a plastic card with an integrated circuit chip capable of storing and processing information. An IC card contains an IC chip that stores the necessary information and transmits this information to a reader in the form of an electrical signal. These IC cards are manufactured by inserting a smart IC module into the card body.

[0003] Smart IC modules are classified as single-type or dual-type depending on the arrangement of the metal layers. Single-type modules have electrode patterns on only one side of the substrate. Dual-type modules have electrode patterns on both sides of the substrate.

[0004] Additionally, smart IC modules are categorized into contact, contactless, hybrid, and combi cards, depending on how the card is used. Contact cards transmit and receive information through physical contact. Contactless cards transmit and receive information without physical contact. Furthermore, hybrid and combi cards incorporate both contact and contactless functions.

[0005] Contact-type smart IC modules transmit and receive information through physical contact. Contactless smart IC modules use wireless communication capabilities (e.g., Near Field Communication (NFC)) to transmit and receive information without physical contact. Combi-type smart IC modules and hybrid smart IC modules incorporate both physical contact and contactless wireless communication capabilities.

[0006] Smart IC cards in these smart IC card modules are widely used in various fields such as credit cards, SIM cards, security cards, and ID cards. The smart IC substrate applied to these smart IC cards includes a substrate and an electrode pattern arranged on the substrate. The electrode pattern includes a bonding surface and a contact surface. The bonding surface of the electrode pattern refers to one surface of the electrode pattern. For example, the bonding surface of the electrode pattern refers to the surface of the electrode pattern that is connected to the IC chip. In addition, the contact surface of the electrode pattern refers to the other surface of the electrode pattern that is exposed to the outside of the smart IC card. For example, the contact surface of the electrode pattern refers to the surface that makes contact with an external device (e.g., a card reader).

[0007] At this time, the contact surface of the electrode pattern is provided with a plating layer of a metal material having a certain level of corrosion resistance, oxidation resistance, wear resistance, and hardness. This plating layer includes gold (Au).

[0008] However, gold (Au) has relatively low mechanical durability, and thus, depending on the number of times the smart IC card is used, problems with mechanical durability may arise. For example, depending on the number of times the smart IC card is used, scratches may occur on the contact surface of the electrode pattern formed by the gold plating layer, which may reduce the durability of the smart IC card. In addition, conventional smart IC cards have a problem in that the unit price of the product increases due to the relatively expensive gold plating layer. Furthermore, conventional smart IC cards require an additional seed layer to form the gold plating layer, which complicates the manufacturing process of the smart IC substrate and increases manufacturing costs.

[0009] (Patent Document 1) KR 10-2002-0011361 A

[0010] Embodiments provide a smart IC substrate, a smart IC module, an IC card, and a method for manufacturing the same, including an electrode pattern surface-treated with a new cover layer.

[0011] In addition, the embodiment provides a smart IC substrate, a smart IC module, an IC card, and a method for manufacturing the same with improved mechanical durability.

[0012] In addition, the embodiment provides a smart IC substrate, a smart IC module, an IC card, and a method for manufacturing the same, including a cover layer from which a seed layer has been removed.

[0013] In addition, the embodiment provides a smart IC substrate, a smart IC module, an IC card, and a method for manufacturing the same, including a cover layer capable of implementing various colors.

[0014] The technical tasks to be achieved in the proposed embodiment are not limited to the technical tasks mentioned above, and other technical tasks not mentioned can be clearly understood by a person having ordinary skill in the technical field to which the proposed embodiment belongs from the description below.

[0015] A smart IC substrate according to an embodiment comprises: a substrate; a metal layer disposed on the substrate; and a cover layer disposed on the metal layer, wherein the substrate has a through hole penetrating one surface and an opposite surface thereof, the cover layer comprises a first cover layer disposed on one surface of the metal layer, and a second cover layer disposed on the other surface of the metal layer overlapping the through hole along a vertical direction, wherein the first cover layer and the second cover layer comprise different materials, and the first cover layer comprises a nitride.

[0016] Additionally, the first cover layer includes at least one of titanium nitride (TiNx) and tantalum nitride (TaNx).

[0017] Additionally, the first cover layer has a thickness of 0.1 μm to 1.5 μm.

[0018] Additionally, the first cover layer has at least one color among gold, blue, and purple.

[0019] In addition, the second cover layer includes a first layer disposed on the other surface of the metal layer, and a second layer disposed under the first layer, and the hardness of the first cover layer is greater than the hardness of the second layer of the second cover layer.

[0020] Additionally, the second layer of the second cover layer includes gold (Au).

[0021] Additionally, the first cover layer has the same color as the color of the second layer of the second cover layer.

[0022] In addition, the device further includes a first adhesive layer disposed between the substrate and the conductive pattern portion, and the through hole penetrates the first adhesive layer.

[0023] In addition, it further includes a second adhesive layer disposed under the above description; and an antenna pattern portion disposed under the second adhesive layer.

[0024] In addition, the metal layer is an alloy including at least two metals, and a buffer layer is further provided between the substrate and the metal layer.

[0025] Additionally, the buffer layer includes a first buffer layer disposed on the substrate and including a first metal, and a second buffer layer disposed on the first buffer layer and including a second metal different from the first metal.

[0026] Additionally, the through hole is provided to penetrate at least one layer of the first buffer layer and the second buffer layer.

[0027] In addition, the through hole is provided to penetrate the first buffer layer and the second buffer layer, the metal layer includes a recess provided in an area overlapping the through hole along a vertical direction, and at least a portion of the second cover layer is disposed within the recess.

[0028] Meanwhile, a method for manufacturing a smart IC substrate according to an embodiment includes a step of disposing a metal layer on a substrate; and a step of depositing a nitride including at least one of titanium nitride (TiNx) and tantalum nitride (TaNx) on the metal layer, wherein the depositing step is performed through a sputtering method under temperature conditions of 100°C to 200°C and power conditions of 500 W to 2000 W.

[0029] Additionally, the depositing step includes a step of depositing the nitride to a thickness of 0.1 μm to 1.5 μm.

[0030] In addition, the depositing step includes a step of injecting argon gas and nitrogen gas, and the argon gas has an injection amount of 1.3 to 2.2 times the injection amount of nitrogen gas.

[0031] In addition, the method further includes a step of etching the deposited nitride, and the etching step includes a step of etching using at least one of a first etchant including an oxidizing agent including hydrofluoric acid and an auxiliary agent including ammonium chloride, a second etchant including an oxidizing agent including hydrogen peroxide and sulfuric acid or hydrochloric acid, and plasma.

[0032] A smart IC substrate of an embodiment includes a substrate and a conductive pattern portion. The conductive pattern portion includes a contact surface. The contact surface may be a terminal portion that is exposed to the outside and makes contact with an external device. In addition, the conductive pattern portion of the embodiment may include a metal layer, a first cover layer covering the contact surface of the metal layer, and a second cover layer covering a bonding surface of the metal layer. In this case, the first cover layer and the second cover layer may include different materials. In particular, the first cover layer may include a nitride.

[0033] Through this, the embodiment can improve the mechanical durability of the product while lowering the unit price. Furthermore, the embodiment can simplify the manufacturing process and further improve product yield. Furthermore, the embodiment can improve design satisfaction, which in turn can improve product satisfaction. Furthermore, the embodiment can improve design freedom.

[0034] That is, the first cover layer can be disposed on the surface of the metal layer corresponding to the contact surface of the conductive pattern portion. The first cover layer can have a certain level or higher of corrosion resistance, oxidation resistance, wear resistance, and hardness. At this time, the first cover layer according to the prior art includes gold (Au). At this time, gold (Au) is relatively expensive. Accordingly, when the first cover layer includes gold (Au), there is a problem that the unit price of the product increases. In addition, the hardness of the plating layer formed of gold (Au) is approximately 100 to 150 HV. At this time, the hardness in the above-mentioned range can satisfy the required hardness characteristics that the contact surface should have, but a reliability problem may occur due to a decrease in mechanical durability depending on the usage time of the smart IC substrate. For example, when the smart IC substrate is used for a long time, wear or scratches of the plating layer including gold (Au) may occur, which may lower the mechanical reliability of the smart IC substrate or cause a problem of a decrease in design satisfaction of the smart IC substrate. Furthermore, when a plating layer containing gold (Au) is directly placed on a metal layer, the adhesion between the metal layer and the first cover layer deteriorates. Therefore, conventionally, an additional seed layer was formed on the metal layer. In this case, the addition of the seed layer formation process complicates the manufacturing process of the smart IC substrate and increases manufacturing costs.

[0035] In contrast, the first cover layer of the embodiment may be a nitride having a certain level or higher of corrosion resistance, oxidation resistance, wear resistance, and hardness. Furthermore, the first cover layer of the embodiment may be provided as a nitride including a metal material having a gold color and a hardness greater than that of gold (Au). The first cover layer may include at least one of titanium nitride (TiNx) and tantalum nitride (TaNx). For example, titanium nitride (TiNx) and tantalum nitride (TaNx) have a gold color. Therefore, when the first cover layer is provided with at least one of titanium nitride (TiNx) and tantalum nitride (TaNx), mechanical resistance can be improved compared to a cover layer using existing gold (Au), and the product cost can be reduced while improving design satisfaction.

[0036] In addition, the first cover layer described above can be formed through a coating method and / or a deposition method. In this case, a separate seed layer for improving the adhesion between the first cover layer and the metal layer can be removed. Furthermore, the adhesion between the first cover layer including at least one of titanium nitride (TiNx) and tantalum nitride (TaNx) and the metal layer is higher than the adhesion between the plating layer including gold and the metal layer. Through this, the embodiment can eliminate the seed layer that should be placed between the first cover layer and the metal layer. Therefore, the manufacturing process for forming the first cover layer can be simplified, thereby further reducing the product cost and further improving the product yield.

[0037] At this time, the degree of nitridation of the first cover layer can be controlled during the coating reaction. Furthermore, the first cover layer can be implemented in various colors depending on the degree of nitridation. For example, the first cover layer can be provided in gold, blue, and purple, depending on the degree of nitridation. Therefore, the embodiment can provide a smart IC card having contact surfaces of various colors by controlling the degree of nitridation of the first cover layer, thereby further improving product satisfaction and further enhancing design freedom.

[0038] Also, the first cover layer is 2*10 -6 (mbar), a temperature condition of 100℃ to 200℃, a thickness condition of 0.1㎛ to 1.5㎛, a gas condition including nitrogen gas and argon gas 1.3 to 2.2 times more than nitrogen gas, and an input power condition of 500W to 2000W. In addition, the first cover layer can be wet-etched using an etchant mixed with an oxidizer including hydrofluoric acid and an auxiliary agent including ammonium chloride, or an etchant including an oxidizer including hydrogen peroxide and sulfuric acid or hydrochloric acid, or can be dry-etched using plasma. Through this, the embodiment can form a first cover layer having a target color on a metal layer with a uniform thickness.

[0039] FIG. 1 is a plan view of one side of a smart IC substrate according to the first embodiment.

[0040] Figure 2 is a plan view of the other surface of the smart IC substrate according to the first embodiment.

[0041] FIG. 3 is a cross-sectional view taken along the AA' direction of FIG. 2 according to the first embodiment.

[0042] FIG. 4 is a cross-sectional view taken along the AA' direction of FIG. 2 according to the second embodiment.

[0043] Figure 5 is a plan view of the other surface of a smart IC substrate according to the third embodiment.

[0044] Figure 6 is a cross-sectional view taken along the BB' direction of Figure 5.

[0045] Fig. 7 is a cross-sectional view taken along the AA' direction of Fig. 2 according to the fourth embodiment.

[0046] Fig. 8 is a cross-sectional view taken along the AA' direction of Fig. 2 according to the fifth embodiment.

[0047] FIG. 9 is a cross-sectional view taken along the AA' direction of FIG. 2 according to the sixth embodiment.

[0048] Fig. 10 is a cross-sectional view taken along the AA' direction of Fig. 2 according to the seventh embodiment.

[0049] Fig. 11 is a plan view showing a smart IC module according to one embodiment.

[0050] Fig. 12 is a cross-sectional view showing a smart IC module according to an embodiment.

[0051] Fig. 13 is a perspective view showing a smart IC card according to an embodiment.

[0052] Fig. 14 is a cross-sectional view schematically showing the smart IC card of Fig. 9.

[0053] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. However, the technical concept of the present invention is not limited to the described embodiments, but may be implemented in various different forms. Within the scope of the technical concept of the present invention, one or more of the components of the embodiments may be selectively combined or substituted for use.

[0054] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by a person of ordinary skill in the technical field to which the present invention belongs, unless explicitly and specifically defined and described, and terms that are commonly used, such as terms defined in a dictionary, may be interpreted in consideration of the contextual meaning of the relevant technology.

[0055] In addition, the terms used in the embodiments of the present invention are for the purpose of describing the embodiments and are not intended to limit the present invention. In this specification, the singular may also include the plural unless specifically stated in the phrase, and when it is described as “and (or at least one) of B, C,” it may include one or more of all combinations that can be combined with A, B, and C.

[0056] Additionally, in describing components of embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are only intended to distinguish the components from other components, and are not intended to limit the nature, order, or sequence of the components.

[0057] And, when a component is described as being 'connected', 'coupled' or 'connected' to another component, it may include not only cases where the component is directly connected, coupled or connected to the other component, but also cases where the component is 'connected', 'coupled' or 'connected' by another component between the component and the other component.

[0058] Additionally, when it is described as being formed or disposed "above or below" each component, above or below includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or disposed between the two components.

[0059] Additionally, when expressed as “upper or lower,” it can include the meaning of not only the upward direction but also the downward direction based on one component.

[0060]

[0061] Hereinafter, a smart IC substrate, a smart IC module, and a smart IC card including the same according to an embodiment will be described with reference to the drawings.

[0062]

[0063] FIG. 1 is a plan view of one side of a smart IC substrate according to a first embodiment, FIG. 2 is a plan view of the other side of the smart IC substrate according to the first embodiment, FIG. 3 is a cross-sectional view taken along the AA' direction of FIG. 2 according to the first embodiment, FIG. 4 is a cross-sectional view taken along the AA' direction of FIG. 2 according to the second embodiment, FIG. 5 is a plan view of the other side of a smart IC substrate according to a third embodiment, FIG. 6 is a cross-sectional view taken along the BB' direction of FIG. 5, FIG. 7 is a cross-sectional view taken along the AA' direction of FIG. 2 according to the fourth embodiment, FIG. 8 is a cross-sectional view taken along the AA' direction of FIG. 2 according to the fifth embodiment, FIG. 9 is a cross-sectional view taken along the AA' direction of FIG. 2 according to the sixth embodiment, and FIG. 10 is a cross-sectional view taken along the AA' direction of FIG. 2 according to the seventh embodiment.

[0064] Referring to FIGS. 1 and 2, the smart IC substrate (100) includes a substrate (110) and a conductive pattern portion (120).

[0065] At this time, the conductive pattern portion (120) of the smart IC substrate (100) in the first embodiment may be a single type arranged only on one side of the substrate (110).

[0066] The substrate (110) includes one side (110S1) and a second side (110S2) opposite to the first side (110S1). In addition, the conductive pattern portion (120) is arranged on the first side (110S1) of the substrate (110).

[0067] Here, being placed on one side (110S1) is not only understood as a configuration in which the conductive pattern portion (120) is in direct contact with one side (110S1) of the substrate (110), but can also be understood as another configuration between the one side (110S1) of the substrate (110) and the conductive pattern portion (120).

[0068] One side (110S1) of the substrate (110) and the other side (110S2) of the substrate (110) mean opposite sides. The one side (110S1) of the substrate (110) may be defined as a contact surface. For example, the one side (110S1) of the substrate (110) may mean a surface that can recognize information of a smart IC module through direct or indirect contact. In addition, the other side (110S2) of the substrate (110) may be defined as a bonding surface. For example, the other side (110S2) of the substrate (110) may mean a surface for bonding with a mounted chip when a chip (to be described later) is mounted.

[0069] The substrate (110) comprises a resin material. The substrate (110) may have a certain strength. The substrate (110) may include a reinforcing member. For example, the substrate (110) may be provided as a prepreg having a reinforcing member such as glass fiber. Specifically, the substrate (110) may be provided by dispersing glass fiber and silicon-based filler (Si filler) within an epoxy resin.

[0070] The substrate (110) may be rigid or flexible. For example, the substrate (110) may include glass or plastic. For example, the substrate (110) may include chemically strengthened / semi-strengthened glass such as soda lime glass or aluminosilicate glass. Alternatively, the substrate (110) may include polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), polycarbonate (PC), or sapphire.

[0071] The substrate (110) may include an optically isotropic film. For example, the substrate (110) may include a cyclic olefin copolymer (COC), a cyclic olefin polymer (COP), an optically isotropic polycarbonate (PC), or an optically isotropic polymethyl methacrylate (PMMA).

[0072] Alternatively, the substrate (110) may be bent while having a partially curved surface. That is, the substrate (110) may be bent while having a partially flat surface and a partially curved surface. In detail, the ends of the substrate (110) may be bent while having a curved surface. Alternatively, the substrate (110) may be bent while having a random curvature.

[0073] The substrate (110) may have a thickness within a set range. For example, the thickness of the substrate (110) may be 80 μm to 150 μm, 90 μm to 140 μm, or 100 μm to 120 μm. If the thickness of the substrate (110) is less than 80 μm, the support capacity and / or rigidity of the substrate (110) may be reduced, which may make it difficult to stably place the conductive pattern portion (120). If the thickness of the substrate (110) exceeds 150 μm, the thickness of the smart IC substrate may increase, and thereby the thickness of the smart IC card including the smart IC substrate (100) may increase, making it difficult to make it thin.

[0074] The substrate (110) has insulating properties. For example, the substrate (110) may be provided to support the conductive pattern portion (120) and provide insulation between the plurality of electrode patterns constituting the conductive pattern portion (120). For example, the substrate (110) may prevent short circuits between the plurality of electrode patterns.

[0075] The substrate (110) may have through holes. For example, the substrate (110) may include a plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) spaced apart from each other in the horizontal direction. At this time, although the drawing illustrates that the plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) are provided in eight numbers, the present invention is not limited thereto. For example, the number of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) provided in the substrate (110) may increase or decrease depending on the type of chip mounted on the smart IC substrate (100). For example, the number of terminals of a chip mounted on a smart IC substrate (100) may be less than 8 or more than 8, and accordingly, the number of a plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) provided in the substrate (110) may be less than 8 or more than 8.

[0076] The plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may be regions for electrically connecting the conductive pattern portion (120) arranged on one surface (110S1) of the substrate (110) and the terminal of the chip. Preferably, the plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may be regions for wire bonding between the terminal of the chip and the conductive pattern portion (120).

[0077] Each of the plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) has a width (W1) of a set range. The width (W1) of each of the plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may mean a diameter of each of the plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8). Alternatively, the width (W1) of each of the plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may be defined as a minimum distance between inner walls of the through holes passing through the central axis in the horizontal direction of each of the plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8).

[0078] The width (W1) of each of the plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may be 500 µm to 1000 µm, 600 µm to 900 µm, or 700 µm to 800 µm. If the width (W1) of at least one through hole among the plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) is less than 500 µm, it may be difficult to secure a wire bonding space, and thus, process characteristics in the wire bonding process may deteriorate. In addition, when the width (W1) of at least one of the plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) exceeds 1000 μm, the planar area of ​​the substrate (110) may decrease and the rigidity of the substrate (110) may decrease accordingly, or it may be difficult to stably place the conductive pattern portion (120) on the substrate (110).

[0079] The conductive pattern portion (120) may be arranged on one side (110S1) of the substrate (110). Preferably, the conductive pattern portion (120) may be in direct contact with the one side (110S1) of the substrate (110). For example, in the smart IC substrate (100) of the first embodiment, no additional configuration may be interposed between the one side (110S1) of the substrate (110) and the lower surface of the conductive pattern portion (120).

[0080] That is, the metal layer (for example, a copper layer) constituting the conductive pattern portion (120) can be directly attached onto the substrate (110). For example, a resin laminate in which the metal layer constituting the conductive pattern portion (120) is directly attached onto the substrate (110) through a direct bonding method can be provided, and the smart IC substrate of the embodiment can be manufactured using the above-described resin laminate. As another example, the substrate (110) can be a prepreg, and the prepreg can be directly molded onto the metal layer constituting the conductive pattern portion (120). In this case, the above-described resin laminate can be a CCL (Copper Clad Laminate).

[0081] The conductive pattern portion (120) may refer to a pattern placed on the contact surface of the substrate (110).

[0082] The conductive pattern portion (120) may include a plurality of electrode patterns. For example, the conductive pattern portion (120) has a plurality of pads spaced apart from each other along a horizontal direction. For example, the conductive pattern portion (120) may include a plurality of pads. At this time, the number of the plurality of pads of the conductive pattern portion (120) may correspond to the number of the plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8). For example, the number of the plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may be eight, and accordingly, the conductive pattern portion (120) may include first to eighth pads (121, 122, 123, 124, 125, 126, 127, 128) spaced apart from each other along a horizontal direction. One surface of the first to eighth pads (121, 122, 123, 124, 125, 126, 127, 128) may be a contact surface that makes contact or does not make contact with an external terminal in order to transmit information of the smart IC substrate (100) to the outside. In addition, the other surface of the first to eighth pads (121, 122, 123, 124, 125, 126, 127, 128) may be a bonding surface that is wire-bonded to a terminal of a chip mounted on the smart IC substrate (100). The first to eighth pads (121, 122, 123, 124, 125, 126, 127, 128) may also be referred to as an upper pad.

[0083] Each of the first to eighth pads (121, 122, 123, 124, 125, 126, 127, 128) may be provided in multiple layers. The first to eighth pads (121, 122, 123, 124, 125, 126, 127, 128) may have the same layer structure.

[0084] Referring to FIG. 3, each of the first to eighth pads (121, 122, 123, 124, 125, 126, 127, 128) may include a metal layer (120a) disposed on one surface of the substrate (110) and a cover layer covering an exposed surface of the metal layer (120a). At this time, the cover layer may also be referred to as a surface treatment layer disposed on the surface of the metal layer (120a). The cover layer may include a first cover layer (120b) and a second cover layer (120c) depending on the location.

[0085] The metal layer (120a) is disposed on one surface (110S1) of the substrate (110). The metal layer (120a) may include at least one material selected from the group consisting of gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). Preferably, the metal layer (120a) may be a copper foil layer attached to the substrate (110), and thus may include copper.

[0086] The metal layer (120a) may have a thickness within a set range. For example, the thickness of the metal layer (120a) may be 20 μm to 75 μm, 22 μm to 65 μm, or 25 μm to 60 μm. When the thickness of the metal layer (120a) is less than 20 μm, the resistance of the metal layer (120a) may increase, and thus the resistance of the conductive pattern portion (120) may increase, resulting in deterioration of signal characteristics. When the thickness of the metal layer (120a) exceeds 75 μm, the thickness of the smart IC substrate may increase, and the thickness of the smart IC card may increase. Furthermore, when the thickness of the metal layer (120a) exceeds 75 μm, the time for forming the conductive pattern portion (120) may increase, which may lower process efficiency and lower product yield. For example, the conductive pattern portion (120) can be manufactured by patterning a metal layer (120a) having a certain thickness placed on a substrate (110) using an etching method. In addition, as the thickness of the metal layer (120a) increases, the etching time of the metal layer (120a) can increase, and thus the manufacturing time can increase.

[0087] The first cover layer (120b) and the second cover layer (120c) may be disposed on the surface of the above-described patterned metal layer (120a). That is, a portion of the surface of the metal layer (120a) may not be covered by the substrate (110). In addition, the first cover layer (120b) and the second cover layer (120c) may be provided to cover the surface of the metal layer (120a) that is not covered by the substrate (110).

[0088] In addition, the first cover layer (120b) and the second cover layer (120c) can enable the contact surface and / or bonding surface of the conductive pattern portion (120) to satisfy a certain level of required characteristics. For example, the first cover layer (120b) and the second cover layer (120c) can enable the contact surface and / or bonding surface of the conductive pattern portion (120) to have a certain level or higher of corrosion resistance, oxidation resistance, wear resistance, hardness, gloss, and wire bonding properties.

[0089] The contact surface and bonding surface of the conductive pattern portion (120) may be required to have different characteristics. The contact surface of the conductive pattern portion (120) may be a surface exposed to the outside, and thus may be required to have a certain level of corrosion resistance, oxidation resistance, wear resistance, and hardness for continuous connection with an external device. In addition, the bonding surface of the conductive pattern portion (120) may be a surface electrically connected to the terminal of the chip, and thus may be required to have a certain level of wire bondability.

[0090] The first cover layer (120b) may be disposed on the surface of the metal layer (120a) corresponding to the contact surface of the conductive pattern portion (120). The first cover layer (120b) may satisfy the required characteristics that the contact surface of the conductive pattern portion (120) should have. For example, the first cover layer (120b) may have a certain level or higher of corrosion resistance, oxidation resistance, wear resistance, and hardness. At this time, the metal layer (120a) may be disposed on the upper surface corresponding to one side (110S1) of the substrate (110). Accordingly, the first cover layer (120b) may cover the upper surface of the metal layer (120a). In addition, the first cover layer (120b) may not be provided on the side of the metal layer (120a) that is not substantially used as a contact surface. However, the embodiment is not limited thereto. The first cover layer (120b) may extend from the upper surface of the metal layer (120a) and cover at least a portion of the side surface of the metal layer (120a), according to an embodiment.

[0091] At this time, the first cover layer according to the prior art includes gold (Au). That is, gold (Au) can have a certain level of corrosion resistance, oxidation resistance, wear resistance, and hardness. Accordingly, conventionally, the surface treatment of the contact surface of the conductive pattern portion (120) was performed using gold (Au). At this time, gold (Au) is relatively expensive. Accordingly, when surface treatment is performed on each of the contact surface and bonding surface of the conductive pattern portion (120) with a metal including gold (Au), there is a problem of increasing the unit price of the product.

[0092] In addition, the hardness of the plating layer formed of gold (Au) is approximately 100 to 150 HV. At this time, the hardness in the above-described range can satisfy the hardness requirement characteristic that the contact surface of the conductive pattern portion (120) must have, but a reliability problem may occur due to a decrease in mechanical durability depending on the usage time of the smart IC substrate. For example, when the smart IC substrate is used for a long time, the plating layer including gold (Au) may be worn or scratched, and this may lower the mechanical reliability of the smart IC substrate or cause a problem of a decrease in design satisfaction of the smart IC substrate.

[0093] Furthermore, when a plating layer containing gold (Au) is directly disposed on the metal layer (120a), the adhesion between copper and gold (Au) is reduced, which may cause reliability issues in which the plating layer containing gold (Au) separates from the metal layer (120a). Accordingly, conventionally, a seed layer was additionally formed for disposing a plating layer containing gold (Au) on the metal layer (120a). In this case, the manufacturing process of the smart IC substrate becomes complicated and the manufacturing cost increases due to the addition of the process for forming the seed layer described above.

[0094] Therefore, the embodiment provides a novel cover layer that can solve the above-described problems of a gold (Au) plating layer on a conventional contact surface.

[0095] In the embodiment, the first cover layer (120b) may be a nitride. Preferably, the first cover layer (120b) may be a nitride having a certain level of corrosion resistance, oxidation resistance, wear resistance, and hardness. For example, the first cover layer (120b) may have a hardness greater than that of gold (Au). In this case, if the first cover layer (120b) only has a hardness greater than that of gold (Au), the design satisfaction of the smart IC substrate may be reduced.

[0096] For example, the above-described contact surface is a surface exposed to the outside of the final product, a smart IC card, and this can act as a factor in determining the design satisfaction of the smart IC card. In this case, if the contact surface is formed of a plating layer containing gold (Au), a gold-colored terminal portion corresponding to the plating layer containing gold (Au) is exposed to the outside, which improves the design satisfaction of the smart IC card while making it possible to provide a more luxurious smart IC card. Therefore, if the first cover layer (120b) has a color other than gold, the design satisfaction may be lowered, and thus the product satisfaction may be lowered.

[0097] Accordingly, the embodiment provides a first cover layer (120b) using a nitride including a metal material having a gold color and a hardness greater than that of gold (Au).

[0098] That is, the first cover layer (120b) may include at least one of titanium nitride (TiNx) and tantalum nitride (TaNx). For example, titanium nitride (TiNx) and tantalum nitride (TaNx) have a gold color. Therefore, when the first cover layer (120b) is comprised of at least one of titanium nitride (TiNx) and tantalum nitride (TaNx), mechanical resistance can be improved compared to a cover layer using conventional gold (Au), and the product cost can be reduced while improving design satisfaction.

[0099] That is, titanium nitride (TiNx) and tantalum nitride (TaNx) can have a hardness in the range of 2000 to 2500 HV, which is 20 times the hardness of gold (Au). Accordingly, when the embodiment provides the first cover layer (120b) using titanium nitride (TiNx) and tantalum nitride (TaNx), the mechanical resistance of the contact surface of the conductive pattern portion (120) can be improved to a level of 20 times or more compared to the existing one.

[0100] Furthermore, titanium nitride (TiNx) and tantalum nitride (TaNx) are relatively cheaper than gold (Au), and thus, when the first cover layer (120b) is provided using titanium nitride (TiNx) and tantalum nitride (TaNx), the unit price of the product can be lowered, and thus product satisfaction can be improved.

[0101] Additionally, titanium nitride (TiNx) and tantalum nitride (TaNx) have a gold color, and thus can provide products that meet the design satisfaction of contact surfaces containing gold (Au) at a relatively low unit price.

[0102] Meanwhile, the first cover layer (120b) described above may be disposed to cover the upper surface of the metal layer (120a) through a coating method and / or a deposition method. Accordingly, titanium nitride (TiNx) and tantalum nitride (TaNx) constituting the first cover layer (120b) may be in direct contact with the upper surface of the metal layer (120a). Furthermore, the adhesion between the first cover layer (120b) and the metal layer (120a) is higher than the adhesion between the plating layer containing gold and the metal layer (120a). For example, the adhesion between the first cover layer (120b) and the metal layer (120a) may be 2 times or more, 3 times or more, or 5 times or more than the adhesion between the plating layer containing gold and the metal layer (120a). Through this, the embodiment can eliminate the seed layer that should be disposed between the first cover layer (120b) and the metal layer (120a). Accordingly, the manufacturing process for forming the first cover layer (120b) can be simplified, thereby further reducing the product unit price and further improving the product yield.

[0103] At this time, the degree of nitridation of the first cover layer (120b) can be controlled during the coating reaction. In addition, the first cover layer (120b) can be implemented in various colors depending on the degree of nitridation. For example, the first cover layer (120b) can be provided in gold, blue, purple, etc. depending on the degree of nitridation. Therefore, the embodiment can provide a smart IC card having a contact surface of various colors by controlling the degree of nitridation of the first cover layer (120b), thereby further improving product satisfaction and further improving design freedom.

[0104] At this time, the first cover layer (120b) may have a different structure depending on the lamination order in the manufacturing process. For example, as illustrated in FIG. 3a, the first cover layer (120b) may be provided to entirely cover the upper and side surfaces of the metal layer (120a). Alternatively, as illustrated in FIG. 3b, the first cover layer (120b) may be provided to cover the upper surface of the metal layer (120a) without contacting the side surfaces of the metal layer (120a).

[0105] For example, the first cover layer (120b) may be formed after the first to eighth pads (121, 122, 123, 124, 125, 126, 127, 128) are formed using a base metal layer (a metal layer before the pads are formed). In this case, the first cover layer (120b) may be provided to entirely cover the upper surface and side surfaces of the metal layer (120a), as illustrated in FIG. 3A.

[0106] In addition, the first cover layer (120b) may be formed on the base metal layer before forming the first to eighth pads (121, 122, 123, 124, 125, 126, 127, 128). Thereafter, in the embodiment, after the first cover layer (120b) is formed, the first cover layer (120b) and the base metal layer may be etched to form the first to eighth pads (121, 122, 123, 124, 125, 126, 127, 128) including the metal layer (120a) and the first cover layer (120b). In this case, the first cover layer (120b) may be provided so as to cover only the upper surface of the metal layer (120a) without covering the side surfaces of the metal layer (120a), unlike the structure illustrated in FIG. 3.

[0107] Hereinafter, it is explained that the first cover layer (120b) is arranged to entirely cover the upper surface and side surface of the metal layer (120a).

[0108] Referring still to FIG. 3, the second cover layer (120c) may be positioned at a different location from where the first cover layer (120b) is positioned. For example, the second cover layer (120c) may be provided on the bonding surface of the metal layer (120a) that is not covered by the first cover layer (120b). The second cover layer (120c) may be positioned on the lower surface of the metal layer (120a).

[0109] That is, at least a portion of the lower surface of the metal layer (120a) of each of the first to eighth pads (121, 122, 123, 124, 125, 126, 127, 128) may overlap with the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) in the vertical direction. Accordingly, the region of the lower surface of the metal layer (120a) that overlaps with the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) in the vertical direction may not be covered by the first cover layer (120b) and the substrate (110). In addition, the second cover layer (120c) can be placed on the lower surface of the metal layer (120a) that is vertically overlapped with the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8).

[0110] That is, the second cover layer (120c) can be placed within the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8). For example, the second cover layer (120c) can be placed within the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) to cover the lower surface of the metal layer (120a).

[0111] The second cover layer (120c) may include a metal material different from the metal material constituting the first cover layer (120b). The second cover layer (120c) may include a metal material having a hardness different from the hardness of the metal material constituting the first cover layer (120b). For example, the second cover layer (120c) may include a first layer (120c1) and a second layer (120c2).

[0112] The first layer (120c1) and the second layer (120c2) of the second cover layer (120c) are arranged on the lower surface of the metal layer (120a), thereby providing a wire bonding property of a certain level or higher required to the bonding surface of the conductive pattern portion (120).

[0113] The first layer (120c1) of the second cover layer (120c) may be disposed on the lower surface of the metal layer (120a). The first layer (120c1) of the second cover layer (120c) may be in direct contact with the lower surface of the metal layer (120a). The first layer (120c1) of the second cover layer (120c) may include nickel. The first layer (120c1) of the second cover layer (120c) may mean a seed layer for forming the second layer (120c2). The first layer (120c1) of the second cover layer (120c) may be a barrier layer that prevents the metal material constituting the metal layer (120a) from diffusing into the second layer (120c2). Additionally, the first layer (120c1) of the second cover layer (120c) may be an oxidation prevention layer that prevents oxidation of the metal layer (120a).

[0114] The second layer (120c2) of the second cover layer (120c) may be disposed on the lower surface of the first layer (120c1) of the second cover layer (120c). The second layer (120c2) of the second cover layer (120c) may provide a wire bonding property of a certain level or higher required for the bonding surface of the conductive pattern portion (120). The second layer (120c2) of the second cover layer (120c) may include at least one of gold (Au) and silver (Ag).

[0115] A dummy pattern portion (DP) may be further provided on one side (110S1) of the substrate (110). The dummy pattern portion (DP) may include the same material as the first conductive pattern portion (120), and preferably, may have the same layer structure as the first conductive pattern portion (120). The dummy pattern portion (DP) may be electrically spaced from the first conductive pattern portion (120), thereby improving the rigidity of the smart IC substrate (100). In addition, the dummy pattern portion (DP) may be provided at a corner region of the one side (110S1) of the substrate (110) to improve process characteristics in the assembly process of the smart IC substrate (100). For example, the dummy pattern portion (DP) may include first to fourth dummy patterns (DP1, DP2, DP3, DP4) respectively provided at a corner region of the one side (110S1) of the substrate (110).

[0116] Meanwhile, referring to FIG. 4, the smart IC substrate according to the second embodiment may further include a first adhesive layer (140). The first adhesive layer (140) may be disposed between one surface (110S1) of the substrate (110) and the conductive pattern portion (120). For example, the first adhesive layer (140) may be disposed between one surface of the substrate (110) and the lower surface of the metal layer (120a).

[0117] The first adhesive layer (140) may be provided for bonding between the conductive pattern portion (120) and the substrate (110). The first adhesive layer (140) may be referred to as a bonding sheet. The first adhesive layer (140) may be provided for bonding a copper foil layer (not shown), which is a metal layer prior to implementing a circuit such as the conductive pattern portion (120), to one surface (110S1) of the substrate (110).

[0118] For example, as in the first embodiment, the conductive pattern portion (120) may be placed directly on one surface of the substrate (110) without the first adhesive layer (140). However, in order to further improve the adhesion between the substrate (110) and the conductive pattern portion (120), a first adhesive layer (140) may be additionally placed between the substrate (110) and the conductive pattern portion (120).

[0119] The first adhesive layer (140) comprises a resin material. For example, the first adhesive layer (140) may comprise at least one of an epoxy resin, an acrylic resin, and a polyimide resin. In addition, the first adhesive layer (140) may comprise at least one additive selected from the group consisting of natural rubber, a plasticizer, a curing agent, and a phosphorus-based flame retardant. In this case, the flexibility of the first adhesive layer (140) may be improved.

[0120] The first adhesive layer (140) may have a thickness (T1) within a set range. For example, the thickness (T1) of the first adhesive layer (140) may be 8 μm to 35 μm, 10 μm to 30 μm, or 12 μm to 25 μm. If the thickness (T1) of the first adhesive layer (140) is less than 8 μm, the adhesive strength of the first adhesive layer (140) may decrease, thereby causing the first conductive pattern portion (120) to be separated from the first adhesive layer (140). In addition, if the thickness (T1) of the first adhesive layer (140) exceeds 35 μm, the thickness of the smart IC substrate or the thickness of the smart IC card may increase.

[0121] At this time, a plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may be provided to penetrate the substrate (110) and the first adhesive layer (140). For example, the plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may penetrate from one surface of the first adhesive layer (140) to the other surface (110S2) of the substrate (110). For example, the plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may be formed through a process such as punching while the first adhesive layer (140) is disposed on the substrate (110), thereby commonly penetrating the substrate (110) and the first adhesive layer (140).

[0122] The planar area of ​​the first adhesive layer (140) may correspond to the planar area of ​​the substrate (110). For example, the first adhesive layer (140) may entirely cover one side (110S1) of the substrate (110). Accordingly, the rigidity of the substrate (110) may be further improved.

[0123] At this time, when the smart IC substrate includes the first adhesive layer (140), the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may be provided to penetrate the first adhesive layer (140) together with the substrate (110). For example, in the case of the second embodiment, the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may include a first portion penetrating the substrate (110) and a second portion penetrating the first adhesive layer (140) while being connected to the first portion described above.

[0124] According to the second embodiment, by additionally disposing a first adhesive layer (140) between the substrate (110) and the conductive pattern portion (120), the adhesion between the substrate (110) and the conductive pattern portion (120) can be further improved. Accordingly, the physical reliability and / or electrical reliability of the smart IC substrate can be further improved.

[0125] Referring to FIGS. 5 and 6, the smart IC substrate may be provided in a dual type. For example, the smart IC substrate may have a structure in which conductive pattern portions are provided on each side of the substrate (110). For example, the smart IC substrate may be disposed on one side (110S1) of the substrate (110) and may include the conductive pattern portion (120) described with reference to FIGS. 1 to 4. In this case, the conductive pattern portion (120) described with reference to FIGS. 1 to 4 may be referred to as a first conductive pattern portion (120) or an upper conductive pattern portion (120) in the dual type smart IC substrate.

[0126] In addition, the smart IC substrate may further include a second conductive pattern portion (130, 135) or a lower conductive pattern portion (130, 135) arranged on the other surface (110S2) of the substrate (110). Hereinafter, this will be described as a second conductive pattern portion.

[0127] The second conductive pattern portion (130, 135) may be spaced apart from the first conductive pattern portion (120) with the substrate (110) interposed therebetween. The second conductive pattern portion (130, 135) may be an antenna pad for antenna function. For example, the second conductive pattern portion (130, 135) may be an antenna pad that electrically connects a chip mounted on a smart IC substrate (100) and an antenna pattern.

[0128] At this time, the second conductive pattern portion (130, 135) may be formed in a different manner from the first conductive pattern portion (120). For example, the first conductive pattern portion (120) may be formed by etching the metal layer (120a) through an exposure and development process. For example, the first conductive pattern portion (120) may be formed through a photolithography process.

[0129] In contrast, the second conductive pattern portion (130, 135) may be attached to the other surface (110S2) of the substrate (110) in a pick and place manner. For example, the second conductive pattern portion (130, 135) may be formed on a separate structure and then attached to the other surface (110S2) of the substrate (110).

[0130] To this end, a second adhesive layer (150) may be provided between the other surface (110S2) of the substrate (110) and the second conductive pattern portion (130, 135). The second adhesive layer (150) may provide adhesive strength for attaching the pre-manufactured second conductive pattern portion (130, 135) to the other surface (110S2) of the substrate (110).

[0131] In this way, the embodiment can form the first conductive pattern portion (120) and the second conductive pattern portion (130, 135) on one side (110S1) and the other side (110S2) of the substrate (110) in different ways, respectively. Therefore, the embodiment can solve the problem that the manufacturing process of the double-sided wiring structure is complicated due to the product structure characteristics of the smart IC substrate (100), and the manufacturing cost increases as the product yield decreases. That is, the embodiment can simplify the manufacturing process of the smart IC substrate (100) by forming the antenna pattern by attaching the second conductive pattern portion (130, 135) manufactured in advance to the substrate (110). Furthermore, the embodiment can easily adjust the attachment position of the second conductive pattern portion (130, 135) according to various product designs, can be applied to products of various designs, and can improve the design freedom accordingly. Furthermore, the embodiment can reduce manufacturing costs by simplifying the process, and further improve product yield.

[0132] By virtue of the characteristics described above, the second adhesive layer (150) can have the structure and / or properties of the first adhesive layer (140).

[0133] The second adhesive layer (150) may be selectively provided on the other surface (110S2) of the substrate (110). The second adhesive layer (150) may be selectively provided only in the area where the second conductive pattern portion (130, 135) is to be arranged on the other surface (110S2) of the substrate (110). Through this, the embodiment can reduce the plane area of ​​the second adhesive layer (150) and further reduce the manufacturing cost by reducing the amount of the second adhesive layer (150). Through this, the other surface (110S2) of the substrate (110) may include a portion covered with the second adhesive layer (150) and a portion not covered with the second adhesive layer (150). In addition, the portion not covered with the second adhesive layer (150) can provide a space for a separate adhesive material to be arranged in a later process of assembling the smart IC card. Therefore, in the embodiment, it is possible to increase the thickness of the above-described adhesive material in a smart IC substrate (100) having the same thickness as the comparative example, thereby improving process characteristics in the assembly process and enabling the smart IC substrate (100) to be more stably bonded.

[0134] In addition, the second adhesive layer (150) may have a predetermined thickness (T2). For example, the second adhesive layer (150) may be greater than the thickness (T1) of the first adhesive layer (140). For example, the thickness (T2) of the second adhesive layer (150) may satisfy a range of 105% to 220%, or 110% to 210%, or 115% to 200% of the thickness (T1) of the first adhesive layer (140). That is, the embodiment allows the thickness (T2) of the second adhesive layer (150) to be greater than the thickness (T1) of the first adhesive layer (140), thereby enabling the second conductive pattern portion (130, 135) to be more stably attached to the other surface (110S2) of the substrate (110), thereby improving product reliability. Furthermore, the embodiment can reduce the height difference between the terminal of the chip and the second conductive pattern portion (130, 135) by the difference in the thicknesses (T1, T2) described above by making the thickness (T2) of the second adhesive layer (150) greater than the thickness (T1) of the first adhesive layer (140). Therefore, the embodiment can improve the process characteristics in the process of wire-bonding the terminal of the chip and the second conductive pattern portion (130, 135), and can further improve the wire bonding reliability accordingly. At this time, if the thickness (T2) of the second adhesive layer (150) is less than 105% of the thickness (T1) of the first adhesive layer (140), the product reliability improvement effect and the process characteristic improvement effect as described above may be insufficient. Additionally, if the thickness (T2) of the second adhesive layer (150) exceeds 200% of the thickness (T1) of the first adhesive layer (140), the thickness of the smart IC substrate (100) may increase.

[0135] The second adhesive layer (150) can be formed of various adhesive materials by being selectively disposed only in the area where the second conductive pattern portion (130, 135) is disposed. For example, the second adhesive layer (150) can be provided as a paste having adhesive properties. For example, the second adhesive layer (150) can be provided as a conductive paste or a non-conductive paste.

[0136] The second conductive pattern portion (130, 135) can be attached to the other surface (110S2) of the substrate (110) by adhesive force provided through the second adhesive layer (150). The second conductive pattern portion (130, 135) can have a predetermined width (W2) and thickness (W3).

[0137] At this time, the embodiment can form the second conductive pattern portion (130, 135) by attaching the pre-manufactured conductive pattern as described above, and thus, formation is possible without restrictions on the width (W2) of the second conductive pattern portion (130, 135). To this end, the embodiment makes the width (W2) of the second conductive pattern portion (130, 135) larger than the width (W1) of the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8). For example, the width (W2) of the second conductive pattern portion (130, 135) can be larger than the width of the lower surface of the first conductive pattern portion (120) exposed through the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8). For example, the width (W2) of the second conductive pattern portion (130, 135) may be either the width in the longitudinal direction and / or the width in the width direction. The width (W2) of the second conductive pattern portion (130, 135) may satisfy a range of 105% to 220%, or a range of 110% to 210%, or a range of 120% to 200% of the width (W1) of the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8).

[0138] In the embodiment, the width (W2) of the second conductive pattern portion (130, 135) is made larger than the width (W2) of the first conductive pattern portion (120), thereby increasing the contact area between the second conductive pattern portion (130, 135) and the second adhesive layer (150), increasing their bonding strength, and thereby enabling the second conductive pattern portion (130, 135) to be more stably attached to the other surface (110S2) of the substrate (110). Through this, the embodiment can further improve product reliability. In addition, in the embodiment, the width (W2) of the second conductive pattern portion (130, 135) is made larger than the width (W2) of the first conductive pattern portion (120), thereby increasing the allowable current of the second conductive pattern portion (130, 135), thereby improving antenna characteristics.

[0139] At this time, if the width (W2) of the second conductive pattern portion (130, 135) is less than 105% of the width (W1) of the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8), the product reliability improvement effect and / or antenna characteristic improvement effect as described above may be insufficient. In addition, if the width (W2) of the second conductive pattern portion (130, 135) exceeds 220% of the width (W1) of the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8), the thickness of the smart IC substrate (100) may increase.

[0140] In addition, the thickness (T3) of the second conductive pattern portion (130, 135) may be different from the thickness of the first conductive pattern portion (120). Preferably, the thickness (T3) of the second conductive pattern portion (130, 135) may satisfy a range of 105% to 220% of the thickness of the first conductive pattern portion (120). In this case, the thickness of the first conductive pattern portion (120) may mean the thickness of the metal layer (120a), or may mean the sum of the thicknesses of the metal layer (120a), the first conductive layer (120b), and the second conductive layer (120c) in the vertical direction. In the embodiment, the thickness (T3) of the second conductive pattern portion (130, 135) is made larger than the thickness of the first conductive pattern portion (120), thereby improving the allowable current of the second conductive pattern portion (130, 135), and thus further improving the antenna characteristics. In addition, in the embodiment, the thickness (T3) of the second conductive pattern portion (130, 135) is made larger than the thickness of the first conductive pattern portion (120), thereby reducing the step between the second conductive pattern portion (130, 135) and the terminal of the chip, thereby improving the wire bonding process characteristics. Therefore, the embodiment can improve the product reliability of the smart IC substrate (100).

[0141] At this time, the second conductive pattern portion (130, 135) may be provided as an alloy. For example, the second conductive pattern portion (130, 135) may be provided as a Cu / Sn / Ag alloy, a Fe / Ni / Ag alloy, or a Cu / Sn / Ag / Al / Ni alloy.

[0142] The second conductive pattern portion (130, 135) may include a plurality of pads that are electrically spaced apart from each other. For example, the second conductive pattern portion (130, 135) may include a first antenna pad (130) and a second antenna pad (135) that is electrically spaced apart from the first antenna pad (130). For example, the first antenna pad (130) may be a pad to which positive polarity power is applied, and the second antenna pad (135) may be a pad to which negative polarity power is applied.

[0143] Each of the first antenna pad (130) and the second antenna pad (135) can be divided into a plurality of parts. At this time, the first antenna pad (130) and the second antenna pad (135) can be referred to as lower pads placed on the other surface (110S2) of the substrate (110).

[0144] The first antenna pad (130) may include a first portion (131) that is positioned most adjacent to the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) without overlapping with the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) in a vertical direction. The first portion (131) of the first antenna pad (130) may be a wire bonding area for electrically connecting with a terminal of the chip.

[0145] The first antenna pad (130) may include a second portion (132) of the first antenna pad (130) that is located further from the through-holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) than the first portion (131) of the first antenna pad (130). The second portion (132) of the first antenna pad (130) may be an area closest to the edge of the other surface (110S2) of the substrate (110) in the first antenna pad (130). The second portion (132) of the first antenna pad (130) may be a terminal area for connection with an antenna pattern (not shown).

[0146] The first antenna pad (130) may include a third portion (133) connecting the first portion (131) and the second portion (132). The third portion (133) of the first antenna pad (130) may electrically connect the first portion (131) and the second portion (132) of the first antenna pad (130) while spacing them apart from each other by a predetermined distance. For example, the third portion (133) of the first antenna pad (130) may facilitate an electrical connection process with a chip in the first portion (131) of the first antenna pad (130) and a connection process with an antenna pattern in the second portion (132) of the first antenna pad (130) at predetermined distances, respectively.

[0147] The second antenna pad (135) may include a first portion (136) of the second antenna pad (135) that is positioned most adjacent to the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) without overlapping with the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) in a vertical direction. The first portion (136) of the second antenna pad (135) may be a wire bonding area for electrically connecting to a terminal of the chip.

[0148] The second antenna pad (135) may include a second portion (137) of the second antenna pad (135) that is located further from the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) than the first portion (136) of the second antenna pad (135). The second portion (137) of the second antenna pad (135) may be an area closest to the edge of the other surface (110S2) of the substrate (110) in the second antenna pad (135). The second portion (137) of the second antenna pad (135) may be a terminal area for connection with an antenna pattern (not shown).

[0149] The second antenna pad (136) may include a third portion (138) of the second antenna pad (135) that connects the first portion (136) of the second antenna pad (135) and the second portion (137) of the second antenna pad (135). The third portion (138) of the second antenna pad (135) may electrically connect the first portion (136) of the second antenna pad (135) and the second portion (137) of the second antenna pad (135) while spacing them apart from each other by a predetermined distance. For example, the third portion (138) of the second antenna pad (135) may facilitate an electrical connection process with a chip in the first portion (136) of the second antenna pad (135) and a connection process with an antenna pattern in the second portion (137) of the second antenna pad (135) at a predetermined distance from each other.

[0150] Below, the process of forming the first cover layer (120b) according to the embodiment is described in detail.

[0151] The first cover layer (120b) can be deposited on the metal layer (120a) through a sputtering process. In addition, the sputtering process can be performed under vacuum conditions in a chamber.

[0152] At this time, the vacuum level of the chamber is 2*10 -6 It can be (mbar).

[0153] In addition, the temperature of the smart IC substrate including the substrate (110) for depositing the first cover layer (120b) may be 100°C to 200°C, 110°C to 195°C, or 115°C to 190°C. At this time, if the temperature of the smart IC substrate is less than 100°C, it may be difficult to stably form the first cover layer (120b) on the metal layer (120a). Alternatively, if the temperature of the smart IC substrate is less than 100°C, it may be difficult to form the first cover layer (120b) with a uniform thickness on the metal layer (120a). In addition, if the temperature of the smart IC substrate exceeds 200°C, the substrate (110) or the metal layer (120a) may be damaged during the process of depositing the first cover layer (120b), thereby deteriorating the physical reliability and / or electrical reliability of the smart IC substrate.

[0154] In addition, the thickness of the first cover layer (120b) may be 0.1 µm to 1.5 µm, or 0.1 µm to 1.3 µm, or 0.1 µm to 1.0 µm. If the thickness of the first cover layer (120b) is less than 0.1 µm, it may be difficult for the first cover layer (120b) to be formed with a uniform thickness on the metal layer (120a). In addition, if the thickness of the first cover layer (120b) is less than 0.1 µm, it may be difficult for the first cover layer (120b) to be formed with a target color. In addition, if the thickness of the first cover layer (120b) exceeds 1.5 µm, the processability in the process of etching the first cover layer (120b) may be degraded. Additionally, if the thickness of the first cover layer (120b) exceeds 1.5 μm, the process time in the process of depositing the first cover layer (120b) may increase.

[0155] At this time, the first cover layer (120b) can be deposited by injecting a mixture of argon gas and nitrogen gas into a vacuum chamber. At this time, the injection amount of argon gas can be greater than the injection amount of nitrogen gas. That is, the injection amount of argon gas can be at least 1.3 times that of nitrogen gas. Preferably, the injection amount of argon gas can be at least 1.5 times that of nitrogen gas. More preferably, the injection amount of argon gas can be at least 1.8 times that of nitrogen gas.

[0156] That is, the ratio of the injection amount of argon gas and the injection amount of nitrogen gas within the vacuum chamber can affect the color of the first cover layer (120b).

[0157] Accordingly, the amount of argon gas injected may be between 1.3 and 2.2 times, or between 1.5 and 2.1 times, or between 1.5 and 2 times, the amount of nitrogen gas injected. In addition, if the amount of argon gas injected and the amount of nitrogen gas injected are outside the above-described range, it may be difficult for the first cover layer (120b) to have the target color.

[0158] Additionally, the input power within the vacuum chamber may range from 500 W to 2000 W. In addition, if the input power exceeds the above-described range, it may be difficult for the first cover layer (120b) to have the target color.

[0159] Additionally, the etching process after the first cover layer (120b) is deposited can be performed through wet etching or dry etching.

[0160] And, when the first cover layer (120b) is etched through a wet etching process, an etchant that combines an oxidizer and an auxiliary agent in an appropriate range can be used.

[0161] For example, the etchant may use hydrofluoric acid as the oxidizing agent and ammonium chloride as the adjuvant. Alternatively, the etchant may use hydrogen peroxide as the oxidizing agent and sulfuric acid or hydrochloric acid as the adjuvant.

[0162] Additionally, when the first cover layer (120b) is etched through a dry etching process, plasma can be used.

[0163] Through this, the embodiment can form a first cover layer (120b) having a target color on a metal layer (120a) with a uniform thickness.

[0164]

[0165] Hereinafter, smart IC substrates according to the fourth to seventh embodiments will be described with reference to FIGS. 7 to 10. At this time, the smart IC substrates of FIGS. 7 to 10 may have differences in the material of the metal layer (120a) constituting the conductive pattern portion (120) compared to the smart IC substrates of FIGS. 1 to 6.

[0166] Referring to FIG. 7, a smart IC substrate according to the fourth embodiment includes a metal layer (120a) disposed on one surface of a substrate (110).

[0167] At this time, the metal layer (120a) may include a binary alloy or a ternary alloy, unlike the metal layers of the first to third embodiments.

[0168] For example, the metal layer (120a) may include an alloy containing nickel (Ni), iron (Fe), and chromium (Cr). For example, the metal layer (120a) may include a Monel series alloy or an Inconel series alloy. Specifically, the metal layer (120a) may be a nickel (Ni)-chromium (Cr)-iron (Fe) alloy containing nickel as a main component and chromium and iron. In the alloy, the main component is defined as a metal having the largest weight percent among a plurality of metals constituting the alloy.

[0169] Alternatively, the metal layer (120a) may include a sus series alloy. Specifically, the metal layer (120a) may be an iron (Fe)-chromium (Cr)-nickel (Ni) alloy containing iron as a main component and chromium and nickel.

[0170] When the metal layer (120a) is formed of a nickel (Ni)-chromium (Cr)-iron (Fe) alloy or an iron (Fe)-chromium (Cr)-nickel (Ni) alloy as described above, a portion of the cover layer disposed on the metal layer (120a) may be omitted. For example, the metal layer (120a) including a nickel (Ni)-chromium (Cr)-iron (Fe) alloy or an iron (Fe)-chromium (Cr)-nickel (Ni) alloy may have a certain level or higher of corrosion resistance, wear resistance, oxidation resistance, and hardness. Therefore, when the metal layer (120a) includes a nickel (Ni)-chromium (Cr)-iron (Fe) alloy or an iron (Fe)-chromium (Cr)-nickel (Ni) alloy, the first cover layer (120b) described in the previous embodiment may be omitted.

[0171] However, when the metal layer (120a) includes a nickel (Ni)-chromium (Cr)-iron (Fe) alloy or an iron (Fe)-chromium (Cr)-nickel (Ni) alloy and the first cover layer (120b) is omitted, the contact surface of the conductive pattern portion (120) may not have a gold color. In this case, design satisfaction may be reduced, and thus user satisfaction may be reduced.

[0172] Accordingly, the embodiment can provide the first cover layer (120b) even if the metal layer (120a) includes a nickel (Ni)-chromium (Cr)-iron (Fe) alloy or an iron (Fe)-chromium (Cr)-nickel (Ni) alloy. This can improve design satisfaction and further enhance user comfort.

[0173] At this time, when the metal layer (120a) includes a nickel (Ni)-chromium (Cr)-iron (Fe) alloy or an iron (Fe)-chromium (Cr)-nickel (Ni) alloy, the metal layer (120a) may be provided by a rolling process. In this case, the surface roughness of the metal layer (120a) may be reduced, thereby lowering the adhesion with the substrate (110).

[0174] Accordingly, a buffer layer (160) may be disposed between one surface (110S1) of the substrate (110) and the metal layer (120a). The buffer layer (160) may include a first buffer layer (161) and a second buffer layer (162). The first buffer layer (161) may be disposed on one surface (110S1) of the substrate (110). The second buffer layer (162) may be disposed on the first buffer layer (161). That is, the second buffer layer (162) is disposed between the first buffer layer (161) and the metal layer (120a).

[0175] The first buffer layer (161) may include a metal. For example, the first buffer layer (161) may include copper (Cu). The adhesion between the metal layer (120a) and the substrate (110) is improved by the first buffer layer (161).

[0176] Additionally, the second buffer layer (162) may include a metal. For example, the second buffer layer (162) may include nickel. The adhesion between the metal layer (120a) and the first buffer layer (161) may be improved by the second buffer layer (162).

[0177] The first buffer layer (161) may be divided into a plurality of regions along the thickness direction. For example, the first buffer layer (161) may be divided into an upper region adjacent to the second buffer layer (162), and a lower region adjacent to one surface (110S1) of the substrate (110).

[0178] The upper region of the first buffer layer (161) may include a metal. That is, the upper region of the first buffer layer (161) is a metal layer. For example, the upper region of the first buffer layer (161) may include copper. The lower region of the first buffer layer (161) may include a metal oxide. That is, the lower region of the first buffer layer (161) is a metal oxide layer. For example, the lower region of the first buffer layer (161) may include copper oxide.

[0179] The lower region of the first buffer layer (161) may be formed by oxidizing a portion of the first buffer layer (161). The surface roughness of the lower region of the first buffer layer (161) may be increased by the oxidation process. That is, the surface roughness of the lower region of the first buffer layer (161) facing one side (110S1) of the substrate (110) may be greater than the surface roughness of the upper region of the first buffer layer (161). In detail, the surface roughness of the lower region of the first buffer layer (161) may be greater than the surface roughness of the metal layer (120a). In addition, the surface roughness of the lower region of the first buffer layer (161) may be greater than the surface roughness of the first buffer layer.

[0180] The thickness of the lower region of the first buffer layer (161) may be smaller than the thickness of the upper region of the first buffer layer (161). For example, the thickness of the lower region of the first buffer layer (161) may be 20% or less, 10% or less, or 5% or less of the total thickness of the first buffer layer (161). In addition, the adhesion between the first buffer layer (161) and one surface (110S1) of the substrate (110) may be further improved by utilizing the lower region of the first buffer layer (161c).

[0181] At this time, the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) of the smart IC substrate of the fourth embodiment may further penetrate the buffer layer (160). For example, the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may include a first portion penetrating the substrate (110) and a second portion penetrating the buffer layer (160). According to an embodiment, a first adhesive layer may further be disposed between the buffer layer (160) and the substrate (110), and in this case, the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may penetrate the first adhesive layer.

[0182] In addition, the second cover layer (120c) of the smart IC substrate according to the fourth embodiment may be disposed within the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8). At this time, the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may penetrate the buffer layer (160) and have a second portion, and the second cover layer (120c) may be disposed within the second portion of the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8).

[0183] At this time, the first cover layer (120b) in one embodiment may be disposed only on the upper surface of the metal layer (120a). Alternatively, the first cover layer (120b) in another embodiment may extend from the upper surface of the metal layer (120a) to cover at least a portion of the side surface of the metal layer (120a) and at least a portion of the side surface of the buffer layer (160).

[0184]

[0185] Referring to FIG. 8, the smart IC substrate of the fifth embodiment may be different from the smart IC substrate of the fourth embodiment in that through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) are not provided in the buffer layer (160).

[0186] The lower surface of the buffer layer (160) in the smart IC substrate of the fifth embodiment may overlap with the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) in the vertical direction. For example, the buffer layer (160) in the region that overlaps with the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) in the vertical direction may not be removed. In this case, a part of the lower surface of the buffer layer (160) may be exposed through the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8), and the second cover layer (120c) may be disposed on the lower surface of the buffer layer (160) exposed through the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8).

[0187] Referring to FIG. 9, the smart IC substrate of the sixth embodiment may be different from the smart IC substrate of the fourth embodiment in that through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) are provided in a portion of the buffer layer (160).

[0188] The lower surface of the buffer layer (160) in the smart IC substrate of the sixth embodiment may overlap with the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) in the vertical direction. For example, a part of the buffer layer (160) in the region that overlaps with the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) in the vertical direction may be removed.

[0189] That is, the buffer layer (160) may include a first buffer layer (161) and a second buffer layer (162). In addition, the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may penetrate the first buffer layer (161) but not penetrate the second buffer layer (162). In this case, a part of the lower surface of the second buffer layer (162) may be exposed through the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8), and the second cover layer (120c) may be disposed on the lower surface of the second buffer layer (162) exposed through the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8).

[0190] Referring to FIG. 10, the smart IC substrate of the seventh embodiment can penetrate at least a portion of the metal layer (120a) while having through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) that penetrate the buffer layer (160) compared to the smart IC substrate of the fourth embodiment.

[0191] For example, the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) can penetrate the first buffer layer (161) and the second buffer layer (162) together with the substrate (110).

[0192] Additionally, the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may penetrate a portion of the metal layer (120a). For example, the metal layer (120a) may include a recess (not shown) provided in an area that overlaps the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) along the vertical direction.

[0193] And, the second cover layer (120c) can be placed in the recess of the metal layer (120a) that is vertically overlapped with the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8).

[0194]

[0195] Fig. 11 is a plan view illustrating a smart IC module according to an embodiment, and Fig. 12 is a cross-sectional view illustrating a smart IC module according to an embodiment. Preferably, Fig. 11 may be a plan view illustrating the other side of the smart IC module in a state where a molding member (1300) is not arranged.

[0196] Referring to FIGS. 11 and 12, the smart IC module (1000) may include a smart IC substrate having the plan views of FIGS. 1 and 2. However, the embodiment is not limited thereto, and the smart IC substrate provided in the smart IC module (1000) may include any one smart IC substrate selected from FIGS. 3 to 10.

[0197] A smart IC module (1000) may include a chip (1100) placed in a chip mounting area. Here, the chip mounting area may be an inner area of ​​an area surrounded by a plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) on the other surface (110S2) of the substrate (110).

[0198] At this time, an adhesive member (not shown) may be placed in the inner region described above, and the chip (1100) may be attached on the adhesive member described above.

[0199] The chip (1100) may include a plurality of terminals (not shown). For example, the chip (1100) may include first to eighth terminals.

[0200] In addition, it may include a connecting member (1200) that connects the terminals of the chip (1100) and the pads of the smart IC substrate (100). The connecting member (1200) may be a wire, but is not limited thereto. The connecting member (1200) may include first to eighth connecting members. For example, the connecting member (1200) may include first to eighth connecting members that connect the first to eighth pads (121, 122, 123, 124, 125, 126, 127, 128) exposed through a plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) to the first to eighth terminals of the chip (1100), respectively.

[0201] At this time, the smart IC module (1000) may further include a molding member (1200). The molding member (1200) may mold the chip (1100). In addition, the molding member (1200) may mold the connection member (1200). Accordingly, the molding member (1200) may be provided to cover the chip (1100) and the connection member (1200) while filling the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8).

[0202]

[0203] Fig. 13 is a perspective view showing a smart IC card according to an embodiment, and Fig. 14 is a cross-sectional view schematically showing the smart IC card of Fig. 9.

[0204] Referring to FIGS. 13 and 14, a smart IC card (3000) according to an embodiment may include a main body (3100), a first protective layer (3210), and a second protective layer (3220).

[0205] The main body (3100) includes a receiving portion (3110). At this time, any one smart IC module (2000) according to FIGS. 1 to 12 can be manufactured, and the manufactured smart IC module (2000) can be placed inside the receiving portion (3110).

[0206] The receiving portion (3110) may have a step. For example, the inner wall of the receiving portion (3110) may have a step. Preferably, the receiving portion (3110) may have a width in an area corresponding to the upper portion of the smart IC card (3000) greater than a width in an area corresponding to the lower portion of the smart IC card (3000). Accordingly, the receiving portion (3110) may include a first portion having a first width and a second portion having a second width greater than the first width. In addition, the second portion of the receiving portion (3110) may receive a chip (1100) and a molding member (1200) provided in the smart IC module, and the remaining components of the smart IC module excluding at least a portion of the chip (1100) and the molding member (1200) may be received in the first portion of the receiving portion (3110). Accordingly, the embodiment can further dramatically reduce the thickness of the smart IC card and enable the chip (1100) to be inserted more stably into the smart IC card.

[0207] At this time, the smart IC module (1000) may include a dual-type smart IC substrate according to FIGS. 5 and 6. In this case, an antenna pattern (not shown) may be arranged on the main body (3100). Specifically, the antenna pattern may be arranged in a coil shape at the edge of the main body (3100). The second portions (132, 137) of the antenna pads provided in the smart IC module (2000) may be connected to the antenna pattern arranged on the main body (3100) described above. An IC card including a smart IC module according to this operates as a contactless card, a combination card, or a hybrid card.

[0208] The smart IC module (2000) is inserted into the receiving portion (3110). The smart IC module (2000) and the main body (3100) are bonded by an adhesive layer (3120). As a result, the smart IC module (2000) is inserted into and fixed in the receiving portion (3110).

[0209] The first protective layer (3210) is disposed on the upper portion of the main body (3100). The first protective layer (3210) may include a transparent material. The first protective layer (3210) may include a transparent resin material. The first protective layer (3210) may be disposed as at least one layer. That is, the first protective layer (3210) may include multiple layers.

[0210] The second protective layer (3220) is disposed at the lower portion of the main body (3100). A magnetic stripe may be disposed on the second protective layer (3220). The second protective layer (3220) may include a transparent material. The second protective layer (3220) may include a transparent resin material. The second protective layer (3220) may be disposed as at least one layer. That is, the second protective layer (3220) may include a plurality of layers.

[0211]

[0212] The features, structures, effects, etc. described in the above-described embodiments are included in at least one embodiment of the present invention, and are not necessarily limited to just one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by those skilled in the art to which the embodiments pertain. Therefore, the contents related to such combinations and modifications should be construed as falling within the scope of the present invention.

[0213] In addition, although the above description focuses on embodiments, these are merely examples and do not limit the present invention. Those skilled in the art to which the present invention pertains will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the present embodiments. For example, each component specifically shown in the embodiments can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the present invention defined in the appended claims.

Claims

1. Description; a metal layer disposed on the above substrate; and Including a cover layer disposed on the above metal layer, The above-mentioned device has a through hole penetrating one side and the other side opposite to the one side, The cover layer includes a first cover layer disposed on one surface of the metal layer, and a second cover layer disposed on the other surface of the metal layer overlapping the through hole along the vertical direction. The first cover layer and the second cover layer contain different materials, A smart IC substrate, wherein the first cover layer comprises nitride.

2. In paragraph 1, A smart IC substrate, wherein the first cover layer comprises at least one of titanium nitride (TiNx) and tantalum nitride (TaNx).

3. In paragraph 1, A smart IC substrate, wherein the first cover layer has a thickness of 0.1 μm to 1.5 μm.

4. In paragraph 3, A smart IC substrate, wherein the first cover layer has at least one color among gold, blue, and purple.

5. In paragraph 1, The above second cover layer is, It includes a first layer disposed on the other surface of the metal layer, and a second layer disposed under the first layer, A smart IC substrate, wherein the hardness of the first cover layer is greater than the hardness of the second layer of the second cover layer.

6. In paragraph 5, A smart IC substrate, wherein the second layer of the second cover layer comprises gold (Au).

7. In paragraph 6, A smart IC substrate, wherein the first cover layer has the same color as the second layer of the second cover layer.

8. In paragraph 1, Further comprising a first adhesive layer disposed between the above substrate and the conductive pattern portion, A smart IC substrate, wherein the above through hole penetrates the first adhesive layer.

9. In paragraph 1, A second adhesive layer disposed under the above description; and A smart IC substrate further comprising an antenna pattern portion disposed under the second adhesive layer.

10. In paragraph 1, The above metal layer is an alloy containing at least two metals, A smart IC substrate further comprising a buffer layer between the above substrate and the metal layer.

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