Encoding method, decoding method, and communication apparatus

Abstract

An encoding method, a decoding method, and a communication apparatus. The encoding method comprises: an encoding device acquires A information bits and the number nPC of PC bits, and generates a first sequence. The first sequence comprises the A information bits and the nPC PC bits. nPC-nPC wm PC bits among the nPC PC bits are located at nPC-nPC wm PC bit positions having the lowest reliability in a first position set S1, and nPC wm PC bits are located at nPC wm bit positions having the minimum row deduplication and the lowest reliability in a second position set S2. The method not only retains PC bits to improve the performance of a code spectrum, for example, the PC bits can assist in decoding path selection based on path metric values, thereby ensuring the reliability of path selection to improve the code spectrum, but also prevents the positions of the PC bits from affecting the reliability of a message set.

Description

Coding and decoding method and communication device

[0001] The present application claims priority to the Chinese patent application No. 202410710681.4, filed on June 3, 2024, and entitled "Coding and decoding method and communication device", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the field of channel coding, and more particularly, to a coding and decoding method and a communication device. BACKGROUND

[0003] Currently, in the Polar code encoding process, the Polar code obtained by using parity check (PC) as the pre-encoding method before Polar encoding can be referred to as a PC-Polar code. The working principle of the PC-Polar code is to select a part of the position set in the frozen position as the PC position, which is also referred to as the dynamic frozen bit position. The value on the PC position is related to the value of the message bit in front of the PC position.

[0004] Generally, there are various decoding algorithms for Polar codes, such as the Successive cancellation decoding (SC) algorithm, the successive cancellation list (SCL) algorithm, the cyclic redundancy check (CRC) aided SCL (referred to as CA-SCL) algorithm, and the like. Among them, the CA-SCL algorithm can significantly improve the performance of the Polar code, and is the current commonly used Polar code decoding algorithm. When the PC-Polar code adopts the CA-SCL algorithm for decoding, considering that the placement method of the PC position may affect the reliability of the message bit, and further affect the decoding performance. Therefore, how to reduce the influence of the PC position on the decoding performance is a research hotspot in the field. SUMMARY

[0005] The present application provides a coding and decoding method, which can improve the code spectrum while ensuring the reliability of the information bits.

[0006] In a first aspect, a coding method is provided, which can be executed by a coding device, or by a component (such as a chip or a circuit or a chip system) of the coding device, or by a logic module or software capable of realizing all or part of the functions of the coding device. For ease of understanding, the following description is made with the coding device as an example.

[0007] The method includes: the encoding device acquiring A information bits and the number n of parity check (PC) bits. PC The A information bits consist of K message bits and L cyclic redundancy check (CRC) bits, where A, K, L, and n are... PC All are positive integers; the encoding device generates a first sequence, the first sequence comprising N bits, the N bits comprising the A information bits and the n bits. PC PC bits, the A information bits and the n PC The PC bits are located in the sequence with the highest sequence reliability (A+n) in the first sequence. PC In ) positions, where N is 2 to the power of n, and n is a positive integer, where, The sequence with the lowest reliability is located in the first position set S1 where the PC bits are located. Each bit position The PC bits located in the second position set S2 have the smallest row weight and the lowest sequence reliability. There are n bit positions, and the first position set S1 is the (A+n) PC The first set of A bit positions is the set of A bit positions in the first sequence, and the second set of A bit positions is the set of A bit positions with the highest sequence reliability in the first sequence. The first sequence is an integer greater than or equal to 0; the encoding device performs polar encoding on the first sequence to obtain a Polar codeword sequence; the encoding device sends the Polar codeword sequence.

[0008] It should be understood that the sequence reliability in this application can also be replaced by Gaussian approximation reliability.

[0009] It should also be understood that The PC bits located in the second position set S2 have the smallest row weight and the lowest sequence reliability. 1 bit position. Where, assuming When the value is 1, the The PC bits are located at the bit position with the smallest row weight and the lowest sequence reliability in the second position set S2; and assume that... Values ​​greater than 1 (e.g.) When the number of bit positions with the smallest row weight in the second position set S2 is 1, then the The PC bits are located at the bit position with the smallest row weight and lowest sequence reliability in the second position set S2, and the bit position with the second smallest row weight and lowest sequence reliability in the second position set S2. That is, it can be understood that when When the value of is greater than or equal to 2, the The i th PC bit is located in the position set S2 with the minimum row weight from small to large, and the sequence reliability is the lowest The i th PC bit is located in the position set S2 with the minimum row weight from small to large, and the sequence reliability is the lowest

[0010] According to the technical scheme provided in the present application, n PC The i th PC bit is located in the position set S2 with the minimum row weight from small to large, and the sequence reliability is the lowest The i th PC bit is located in the position set S2 with the minimum row weight from small to large, and the sequence reliability is the lowest The i th PC bit is located in the position set S2 with the minimum row weight from small to large, and the sequence reliability is the lowest The i th PC bit is located in the position set S2 with the minimum row weight from small to large, and the sequence reliability is the lowest The i th PC bit is located in the position set S2 with the minimum row weight from small to large, and the sequence reliability is the lowest

[0011] In some possible implementation manners, the i th PC position in the n PC PC positions is determined according to the row weight corresponding to the i th candidate position in the third position set S3 and the minimum row weight corresponding to the second position set S2, wherein the third position set S3 indicates n PC positions with the lowest sequence reliability in the first position set S1, 1≤i≤n PC If the row weight corresponding to the i th candidate position is less than the minimum row weight corresponding to the second position set S2, a first position in a fourth position set S4 is taken as a PC position, the first position is a position with the lowest reliability in a fifth position set S5, the fifth position set S5 includes positions in the fourth position set S4 with the row weight equal to the minimum row weight corresponding to the second position set S2, the fourth position set S4 is composed of the second position set S2 and the i th candidate position, and if the row weight corresponding to the i th candidate position is greater than or equal to the minimum row weight corresponding to the second position set S2, a position with the lowest sequence reliability in the fourth position set S4 is taken as the PC position.

[0012] It should be understood that in the initial state, the A information bits are located in the A positions with the highest sequence reliability in the first position set, i.e., the position set of the A bit positions included in the second position set, and in the initial state, the A bit positions are used to carry the A information bits.

[0013] In some possible implementation manners, the n PC≥2, where the first position determined by at least two candidate positions in the third position set S3 is the same, and the first position is used as the PC position determined by the first candidate position among the at least two candidate positions, the PC position determined by the second candidate position among the at least two candidate positions is determined based on the row weight corresponding to the second candidate position and the minimum row weight corresponding to the updated second position set S2. The updated second position set S2 is the position set corresponding to the PC position after deleting the PC position in the fourth position set S4. If the row weight corresponding to the second candidate position is less than the minimum row weight corresponding to the updated second position set S2, the updated... The second position in the fourth position set S4 is taken as the PC position. The second position is the position with the lowest reliability in the updated fifth position set S5. The updated fifth position set S5 includes the minimum row weight in the updated fourth position set S4 that is equal to the row weight corresponding to the updated second position set S2. The updated fourth position set S4 is the position set after deleting the PC position in the fourth position set S4. If the row weight corresponding to the second candidate position is greater than or equal to the minimum row weight corresponding to the updated second position set S2, the position with the lowest sequence reliability in the updated fourth position set S4 is taken as the PC position.

[0014] In conjunction with the first aspect, in some possible implementations, the n PC =3, the n PC The first PC position out of the three PC positions is determined based on the row weight corresponding to the first candidate position in the third position set S3 and the first minimum row weight corresponding to the second position set S2. The third position set S3 includes three candidate positions, indicating the three positions with the lowest sequence reliability in the first position set S1. The first candidate position is the position with the highest sequence reliability in the third position set S3.

[0015] If the row weight corresponding to the first candidate position is less than the first minimum row weight, the position with the lowest sequence reliability in the fifth position set S5 is taken as the first PC position. The fifth position set S5 indicates the set of positions in the fourth position set S4 whose row weight is equal to the first minimum row weight. The fourth position set S4 includes the second position set S2 and the first candidate position.

[0016] If the row weight corresponding to the first candidate position is greater than or equal to the first minimum row weight, the position with the lowest sequence reliability in the fourth position set S4 is taken as the first PC position.

[0017] In conjunction with the first aspect, in some possible implementations, the nPC The third PC position of the three PC positions is determined according to a row weight corresponding to a second candidate position in the third position set S3 and a second minimum row weight corresponding to the second position set S2 after a first update, wherein the second candidate position is a position with a second highest sequence reliability in the third position set S3, and the second position set S2 after the first update is a position set after the first PC position in the fourth position set S4 is deleted; if the row weight corresponding to the second candidate position is less than the second minimum row weight, a position with a lowest sequence reliability in a fifth position set S5 after the first update is taken as the third PC position, the fifth position set S5 after the first update indicates a position set equal to the second minimum row weight in the fourth position set S4 after the first update, and the fourth position set S4 after the first update includes the second position set S2 after the first update and the second candidate position; if the row weight corresponding to the second candidate position is greater than or equal to the second minimum row weight, a position with a lowest sequence reliability in the fourth position set S4 after the first update is taken as the third PC position.

[0018] With reference to the first aspect, in some possible implementation manners, the n PC The third PC position of the three PC positions is determined according to a row weight corresponding to a second candidate position in the third position set S3 and a second minimum row weight corresponding to the second position set S2 after a first update, wherein the second candidate position is a position with a second highest sequence reliability in the third position set S3, and the second position set S2 after the first update is a position set after the first PC position in the fourth position set S4 is deleted; if the row weight corresponding to the second candidate position is less than the second minimum row weight, a position with a lowest sequence reliability in a fifth position set S5 after the first update is taken as the third PC position, the fifth position set S5 after the first update indicates a position set equal to the second minimum row weight in the fourth position set S4 after the first update, and the fourth position set S4 after the first update includes the second position set S2 after the first update and the second candidate position; if the row weight corresponding to the second candidate position is greater than or equal to the second minimum row weight, a position with a lowest sequence reliability in the fourth position set S4 after the first update is taken as the third PC position.

[0019] With reference to the first aspect, in some possible implementation manners, the n PCThe j-th PC position among the PC positions is determined based on the row weight corresponding to the j-th candidate position in the third position set S3 and the minimum row weight corresponding to the second position set S2, wherein the third position set S3 indicates the n-th position in the first position set S1 with the lowest sequence reliability. PC The n positions in the third position set S3 PC A PC position is determined by sequentially selecting candidate positions from highest to lowest sequence reliability, where the j-th candidate position is the position of the n-th candidate position. PC The fourth position set S4 is the position with the highest reliability in the sequence among the positions. It is composed of the j-th candidate position from the second position set S2 and the third position set S3. When j = 1, the fourth position set S4 indicates the A+1 positions with the highest reliability in the first sequence, where 1 ≤ j ≤ n. PC -1. If the row weight corresponding to the j-th candidate position is less than the minimum row weight corresponding to the second position set S2, the position with the lowest sequence reliability in the fifth position set S5 is taken as the j-th PC position. The fifth position set S5 indicates the set of positions in the fourth position set S4 whose row weight is equal to the minimum row weight corresponding to the second position set S2. If the row weight corresponding to the j-th candidate position is greater than or equal to the minimum row weight corresponding to the second position set S2, the position with the lowest sequence reliability in the fourth position set S4 is taken as the j-th PC position. Update the second position set S2. The updated second position set S2 is the set of positions corresponding to the j-th PC position after deleting the fourth position set S4. Update the fourth position set S4. The updated fourth position set S4 includes the updated second position set S2 and the (j+1)-th candidate position. Determine the (j+1)-th PC position based on the row weight corresponding to the (j+1)-th candidate position and the minimum row weight corresponding to the updated second position set S2. Repeat the above operation until n is obtained. PC PC locations.

[0020] In conjunction with the first aspect, in some possible implementations, the n PC The PC positions are the n positions with the lowest sequence reliability in the first position set S1. PC n bit positions, or, the n PC The PC positions are selected from the second position set S2, which has the lowest sequence reliability and the smallest row weight. The sequence with the lowest reliability among the positions in the first position set S1 and the position sets excluding the second position set S2. It consists of 10 bit positions.

[0021] In conjunction with the first aspect, in some possible implementations, the A information bits are located in the first location set S1 excluding the n bits.PC a position other than the bit position.

[0022] In a second aspect, a method for encoding is provided. The method can be performed by an encoding device, a component (e.g., a chip or a circuit or a chip system) of the encoding device, or a logic module or software capable of implementing all or part of the functions of the encoding device. For ease of understanding, the method is described below with the encoding device performing the method as an example.

[0023] The method includes: obtaining A information bits and a number n of parity check PC bits PC , the A information bits being composed of K message bits and L cyclic redundancy check CRC bits, the A, the K, the L, and the n PC all being positive integers; generating a first sequence, the first sequence including N bits, the N bits including the A information bits and the n PC PC bits, the A information bits and the n PC PC bits being located at (A+n PC ) positions with the highest sequence reliability in the first sequence, wherein the N is a power of 2, n is a positive integer,

[0024] The ith PC position in the n PC PC positions is determined according to a row weight corresponding to an ith candidate position in a third position set S3 and a minimum row weight corresponding to a second position set S2, the third position set S3 indicating n PC positions with the lowest sequence reliability in the first position set S1, 1≤i≤n PC , if the row weight corresponding to the ith candidate position is less than the minimum row weight corresponding to the second position set S2, a first position in a fourth position set S4 is a PC position, the first position being a position with the lowest reliability in a fifth position set S5, the fifth position set S5 including positions in the fourth position set S4 with the row weight equal to the minimum row weight corresponding to the second position set S2, the fourth position set S4 being composed of the second position set S2 and the ith candidate position, if the row weight corresponding to the ith candidate position is greater than or equal to the minimum row weight corresponding to the second position set S2, a position with the lowest sequence reliability in the fourth position set S4 is the PC position, the first sequence is polar encoded to obtain a Polar codeword sequence, and the Polar codeword sequence is transmitted.

[0025] In a third aspect, an encoding method is provided, which can be executed by an encoding device, a component (e.g., a chip or a circuit or a chip system) of the encoding device, or a logic module or software capable of realizing all or part of the functions of the encoding device. For ease of understanding, the encoding device is taken as an example in the following description.

[0026] The method comprises: obtaining, by an encoding device, A information bits and a number n of parity check PC bits PC , the A information bits being composed of K message bits and L cyclic redundancy check CRC bits, the A, the K, the L and the n PC all being positive integers; generating, by the encoding device, a first sequence, the first sequence comprising N bits, the N bits comprising the A information bits and the n PC PC bits, the A information bits and the n PC PC bits being located at (A+n PC ) positions with the highest sequence reliability in the first sequence, wherein the N is a power of 2, n is a positive integer, the jth PC position in the n PC PC positions is determined according to a row weight corresponding to the jth candidate position in a third position set S3 and a minimum row weight corresponding to a second position set S2,

[0027] wherein the third position set S3 indicates n PC positions with the lowest sequence reliability in the first position set S1, the n PC positions in the third position set S3 are sequentially determined as candidate positions for a PC position in order of sequence reliability from high to low, the jth candidate position is a position with the jth highest sequence reliability in the n PC positions, and a fourth position set S4 is composed of the jth candidate position in the third position set S3 and the second position set S2, when j = 1, the fourth position set S4 indicates A+1 positions with the highest sequence reliability in the first sequence, 1≤j≤n PC -1,

[0028] if the row weight corresponding to the jth candidate position is less than the minimum row weight corresponding to the second position set S2, a position with the lowest sequence reliability in a fifth position set S5 is taken as the jth PC position, the fifth position set S5 indicating a position set with the minimum row weight corresponding to the second position set S2 in the fourth position set S4,

[0029] if the row weight corresponding to the jth candidate position is greater than or equal to the minimum row weight corresponding to the second position set S2, a position with the lowest sequence reliability in the fourth position set S4 is taken as the jth PC position.

[0030] updating the second position set S2, and the updated second position set S2 is a position set corresponding to deleting the jth PC position in the fourth position set S4.

[0031] updating the fourth position set S4, and the updated fourth position set S4 includes the updated second position set S2 and a (j+1)th candidate position;

[0032] determining a (j+1)th PC position based on a row weight corresponding to the (j+1)th candidate position and a minimum row weight corresponding to the updated second position set S2, and repeating the above operations until n PC PC positions are obtained;

[0033] performing Polar encoding on the first sequence to obtain a Polar codeword sequence;

[0034] sending the Polar codeword sequence.

[0035] In a fourth aspect, a decoding method is provided. The decoding method can be executed by a decoding device, a component (such as a chip or a circuit or a chip system) of the decoding device, or a logic module or software capable of implementing all or part of the functions of the decoding device. For ease of understanding, the decoding device is taken as an example in the following description.

[0036] The method includes: receiving, by the decoding device, a symbol sequence; performing, by the decoding device, a cyclic redundancy check (CRC)-aided successive cancellation list (CA-SCL) algorithm decoding on the symbol sequence to determine a first path, the first path corresponding to a minimum path metric value (PM); determining, by the decoding device, a first sequence according to the first path, the first sequence including N bits, the N bits including A information bits and n PC PC bits, the A information bits and the n PC PC bits being located in (A+n PC ) positions with the highest sequence reliability in the first sequence, wherein the N is 2 raised to the power of n, n is a positive integer, and wherein the first position set S1 includes bit positions with the lowest sequence reliability, the second position set S2 includes bit positions with the lowest sequence reliability and the minimum row weight, the first position set S1 is a position set of the (A+n PC ) bit positions in the first sequence, the second position set S2 is a position set of A bit positions with the highest sequence reliability in the first sequence, and the is an integer greater than or equal to 0; the decoding device determines the A information bits according to the first sequence.

[0037] In combination with the fourth aspect, in a possible implementation manner, the n PC bit positions with the lowest sequence reliability in the first position set S1, or the n PC bit positions consist of n PC bit positions with the lowest sequence reliability and the smallest row weight in the second position set S2, and bit positions with the lowest sequence reliability in a position set in the first position set S1 except the second position set S2.

[0038] In combination with the fourth aspect, in a possible implementation manner, the A information bits are located at positions in the first position set S1 except the n PC bit positions.

[0039] Other implementation manners of the fourth aspect can refer to any of the other implementation manners of the first aspect to the third aspect, which will not be described herein.

[0040] The fifth aspect provides a communication apparatus having the functions of implementing the method of the first aspect to the third aspect, or the method in any possible implementation manner of the first aspect to the third aspect. The functions can be implemented by hardware, or by hardware executing corresponding software. The hardware or software includes one or more units corresponding to the above functions.

[0041] The sixth aspect provides a communication apparatus including at least one processor, the at least one processor being coupled with at least one memory, the at least one memory being configured to store computer programs or instructions, and the at least one processor being configured to invoke and run the computer programs or instructions from the at least one memory, so that the communication apparatus executes the method in the first aspect or any possible implementation manner thereof, or executes the method in the second aspect or any possible implementation manner thereof, or executes the method in the third aspect or any possible implementation manner thereof.

[0042] The seventh aspect provides a communication apparatus including a communication interface and a circuit, the communication interface being configured to acquire A information bits and a number n PC of parity check PC bits, and input the A information bits and the number n PC of PC bits to the circuit; the circuit is configured to generate a first sequence; and the communication interface is further configured to output a codeword sequence.

[0043] ​​As an example, the communication apparatus of the fifth aspect to the seventh aspect is an encoding apparatus, e.g., an encoder.

[0044] In an eighth aspect, a communication apparatus is provided, which has the function of implementing the method of the fourth aspect, or the method in any possible implementation of the fourth aspect. The function can be realized by hardware, or by executing corresponding software with hardware. The hardware or software includes one or more units corresponding to the above functions.

[0045] In a ninth aspect, the present application provides a communication apparatus, comprising at least one processor, wherein the at least one processor is coupled with at least one memory, and the at least one memory is configured to store computer programs or instructions, and the at least one processor is configured to invoke and run the computer programs or instructions from the at least one memory, so that the communication apparatus executes the method in the fourth aspect or any possible implementation of the fourth aspect.

[0046] In a tenth aspect, the present application provides a communication apparatus, comprising a communication interface and a circuit, wherein the communication interface is configured to receive a sequence of code words, and input the sequence of code words to the circuit.

[0047] As an example, the communication apparatus of the eighth aspect to the tenth aspect is a decoding apparatus, e.g., a decoder.

[0048] In an eleventh aspect, the present application provides a computer readable storage medium, wherein the computer readable storage medium stores computer program codes or instructions, and when the computer instructions are run on a computer, the method in the first aspect or any possible implementation of the first aspect is implemented, or the method in the second aspect or any possible implementation of the second aspect is implemented, or the method in the third aspect or any possible implementation of the third aspect is implemented, or the method in the fourth aspect or any possible implementation of the fourth aspect is implemented.

[0049] In a twelfth aspect, the present application provides a computer program product, wherein the computer program product comprises computer program codes or instructions, and when the computer program codes or instructions are run on a computer, the method in the first aspect or any possible implementation of the first aspect is implemented, or the method in the second aspect or any possible implementation of the second aspect is implemented, or the method in the third aspect or any possible implementation of the third aspect is implemented, or the method in the fourth aspect or any possible implementation of the fourth aspect is implemented.

[0050] In a thirteenth aspect, the present application provides a wireless communication system, comprising the encoding apparatus in any one of the fifth aspect to the seventh aspect, and the decoding apparatus in any one of the eighth aspect to the tenth aspect. BRIEF DESCRIPTION OF DRAWINGS

[0051] FIG. 1 is a schematic diagram of a system architecture of a communication system suitable for embodiments of the present application.

[0052] FIG. 2 is a schematic diagram of a flow of a communication system.

[0053] FIG. 3 is a schematic diagram of a Polar code with a length of 8.

[0054] FIG. 4 is a schematic diagram of a PC-check relationship of a PC-Polar code.

[0055] FIG. 5 is a schematic diagram of SC decoding.

[0056] FIG. 6 is a schematic diagram of a binary tree of SCL-2 decoding of a Polar code.

[0057] FIG. 7 is a schematic diagram of a PC bit placement manner.

[0058] FIG. 8 is a schematic diagram of a flow of encoding and decoding provided by embodiments of the present application.

[0059] FIG. 9 is a schematic diagram of a code spectrum simulation provided by embodiments of the present application.

[0060] FIG. 10 is a schematic structural diagram of a communication apparatus provided by the present application.

[0061] FIG. 11 is a schematic structural diagram of another communication apparatus provided by the present application.

[0062] FIG. 12 is a schematic structural diagram of still another communication apparatus provided by the present application. DETAILED DESCRIPTION

[0063] The technical solutions in the present application will be described below with reference to the accompanying drawings.

[0064] The technical solutions of the embodiments of the present application can be applied to various communication systems, including but not limited to: satellite communication systems, the 5th generation (5G) system, long term evolution (LTE) systems (LTE frequency division duplex (FDD) systems, LTE time division duplex (TDD) systems), and the like. The technical solutions provided in the present application can also be applied to future communication systems, such as the 6th generation mobile communication system. In addition, it can also be applied to device to device (D2D) communication, vehicle-to-everything (V2X) communication, machine to machine (M2M) communication, machine type communication (MTC), and internet of things (IoT) communication systems, or other communication systems, etc., which are not limited herein.

[0065] The technical solutions of the embodiments of the present application can also be applied to narrow band-internet of things (NB-IoT), global system for mobile communications (GSM), enhanced data rate for gsm evolution (EDGE), wideband code division multiple access (WCDMA), code division multiple access 2000 (CDMA2000), time division-synchronization code division multiple access (TD-SCDMA), and the three major application scenarios of future communication networks: enhanced mobile broadband (eMBB), ultra-reliable and low-latency communications (URLLC), and massive machine type communications (eMTC).

[0066] FIG. 1 is a schematic diagram of a system architecture of a communication system applicable to the technical solutions of the present application. The communication system can include one or more network devices, and one or more terminal devices.

[0067] Exemplarily, the terminal device can also be referred to as a user equipment (UE), an access terminal, a subscriber unit, a subscriber station, a mobile station, a mobile station, a mobile terminal (MT), a remote station, a remote terminal, a mobile device, a user terminal, a terminal, a wireless communication device, a user agent, or a user apparatus. The terminal device in the embodiments of the present application can refer to a device that provides voice and / or data connectivity for a user, and can be used to connect people, things and machines, such as handheld devices with wireless connection functions, vehicle-mounted devices, etc. The terminal device in the embodiments of the present application can be a mobile phone, a pad, a notebook computer, a palm computer, a mobile internet device (MID), a wearable device, a virtual reality (VR) device, an augmented reality (AR) device, a personal digital assistant, a wireless terminal in industrial control, a wireless terminal in self driving, a wireless terminal in remote medical surgery, a wireless terminal in smart grid, a wireless terminal in transportation safety, a wireless terminal in smart city, a wireless terminal in smart home, a vehicle-mounted mobile terminal, etc. Optionally, the UE can be used to act as a base station. For example, the UE can act as a scheduling entity, which provides sidelink signals between UEs in V2X or D2D, etc.

[0068] In the embodiments of the present application, the device for implementing the function of the terminal can be a terminal, or a device capable of supporting the terminal to implement the function, such as a chip system or a chip, which can be installed in the terminal. In the embodiments of the present application, the chip system can be composed of a chip, or can include a chip and other discrete devices.

[0069] Exemplarily, the network device can be a device with a wireless transceiving function, which can be a device providing a wireless communication function service, and is usually located at a network side, including but not limited to a next-generation base station (gNodeB, gNB) in a 5th generation (5G) communication system, a base station in a future mobile communication system or an access node in a wireless fidelity (Wi-Fi) system, an evolved node B (eNB) in a long term evolution (LTE) system, a radio network controller (RNC), a node B (NB), a base station controller (BSC), a home base station (for example, a home evolved NodeB or a home Node B, HNB), a base band unit (BBU), a transmission reception point (TRP), a transmitting point (TP), a base transceiver station (BTS) and the like. In a network structure, the network device can include a centralized unit (CU) node, or include a distributed unit (DU) node, or include a RAN device including a CU node and a DU node, or include a RAN device including a control plane CU node and a user plane CU node and a DU node, or the network device can also be a wireless controller in a cloud radio access network (CRAN) scenario, a relay station, a vehicle-mounted device and a wearable device and the like. In addition, the base station can be a macro base station, a micro base station, a relay node, a donor node or a combination thereof. The base station can also refer to a communication module, a modem or a chip for being arranged in the foregoing devices or apparatuses. The base station can also be a mobile switching center and a device assuming a base station function in D2D, V2X, M2M communication, a network side device in a future communication network, a device assuming a base station function in a future communication system and the like. The base station can support networks of the same or different access technologies, without limitation.

[0070] In an embodiment of the present application, the apparatus for implementing the function of the network device can be a network device, or can be an apparatus capable of supporting the network device to implement the function, such as a chip system or a chip, which can be installed in the network device. In an embodiment of the present application, the chip system can be composed of a chip, or can include a chip and other discrete devices.

[0071] It should be understood that the coding and decoding method provided in the present application can be used in special communication equipment or general equipment, and can be applied to various network equipment (for example, base station equipment) as described above, and can also be applied to various terminal equipment as described above. Specifically, the scheme is mainly implemented through a channel coding and decoding unit in the equipment.

[0072] The method provided in the embodiments of the present application can also be implemented through an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), and the like, or can be implemented through software (for example, program code in a memory), without limitation.

[0073] FIG. 2 is a schematic diagram of a communication system. As shown in FIG. 2, the technical scheme of the present application mainly involves a channel coding and decoding part. Channel coding is located between source coding and modulation, and is responsible for channel coding of information bits generated by a source. After modulation, the modulated symbols are sent by a sending end through a noisy channel to a receiving end. After demodulation, the receiving end performs channel decoding. Channel decoding is located between demodulation and source decoding, and is responsible for recovering a source bit stream.

[0074] The sending end performs channel coding on a source from a media / medium access control (MAC), and the receiving end sends the demodulated log likelihood ratio (LLR) soft information into a decoder, and then recovers the source information and uploads it to the MAC.

[0075] When wireless technology is used for communication, the source of the sending end generally needs to be subjected to source coding, channel coding and modulation before being sent on a channel. After receiving the signal, the receiving end obtains the sink by sequentially performing demodulation, channel decoding and source decoding.

[0076] Channel coding and decoding is one of the core technologies in the field of wireless communication, and improvement of the performance thereof will directly improve network coverage and user transmission rate.

[0077] Next, in order to facilitate understanding of the embodiments provided in the present application, the terms involved in the present application will be briefly introduced as follows:

[0078] 1. Polar code

[0079] Polar code, also known as Polar code, is a new coding method based on channel polarization, with a deterministic construction method, and is the only channel coding method that has been strictly proved to "reach" the Shannon channel capacity. From the perspective of algebraic coding and probabilistic coding, Polar code has the characteristics of both. Polar code has the advantages of good decoding performance and low complexity, and is currently determined by the Third Generation Partnership Project (3GPP) as the control channel coding scheme for 5G eNBB scenarios.

[0080] FIG. 3 is a schematic diagram of a Polar code with a length of 8. In the encoding construction, a plurality of polarization kernel operations (as shown in FIG. 3) are included, in which the polarization kernel multiplies another two input bits with It can be seen that the Polar code is recursively constructed, and the Polar code with a length of 8 (i.e., N = 8) can be obtained by coupling two Polar codes with a length of 4, and the Polar code with a length of 4 can be obtained by coupling two Polar codes with a length of 2.

[0081] In the construction process of the Polar code, the information bit positions and the frozen bit positions of the Polar code need to be determined. Generally, the reliability of each subchannel is first sorted, the K positions with the highest reliability are set as information bit positions, and the remaining N-K positions are set as frozen bit positions. As shown in FIG. 3, a Polar code with N = 8 and K = 4 is constructed, in which u3, u5, u6, and u7 are information bit positions, and the remaining positions are frozen bit positions.

[0082] 2. Parity check (PC)-Polar code

[0083] PC encoding can also be used as a pre-encoding method before Polar encoding. According to the PC check relationship and the message bit sequence, the check bits at the PC positions can be determined, and then the sequence composed of the message bits, the PC bits, and the frozen bits is input into the Polar encoder for encoding to obtain a Polar code sequence, i.e., a PC-Polar code sequence.

[0084] Among them, the main technical principle of PC-Polar code is to pick out a part of bit position set from the frozen positions as PC positions, the values at these PC positions are different from other frozen bits, and the values at the PC positions are not fixed as 0, but are determined according to the values of the message bits before the PC positions, i.e., the PC positions can also be called dynamic frozen bits, and the positions come from the frozen bits, but the values are not fixed as 0.

[0085] Figure 4 is a schematic diagram of PC check relationship of PC-Polar code. As shown in Figure 5, the PC-Polar code word sequence includes frozen bits, information bits, PC bits and truncated bits. The position of the truncated bits is the rate matching shortened position, which is not sent to the channel. The value of the PC bit is determined based on the value of the message bit before the PC position. As shown in Figure 5, the 10th position is the PC position, and the value at this position is determined by XOR operation based on the value of the message bit at the 4th position and the value of the message bit at the 7th position; the 13th position is the PC position, and the value at this position is determined by XOR operation based on the value of the message bit at the 4th position and the value of the message bit at the 6th position. Specifically, the value of the PC position is determined based on the value of the message bit at the position before the PC position, and the specific information bit position can be determined according to the PC equation.

[0086] 3. CA-polar code

[0087] The CA-Polar encoding is to perform CRC precoding before Polar encoding of the message bit sequence, and then perform Polar encoding on the CRC code word obtained by precoding to obtain the final Polar code word sequence.

[0088] 4. PCCA-polar code

[0089] The PCCA-polar code combines CRC precoding and PC precoding. Since the objects of CRC precoding and PC precoding are both message bit sequences, i.e., the two are in parallel relationship. Therefore, there is no sequence between CRC precoding and PC precoding, and the final Polar code word sequence is called PCCA-polar code.

[0090] 5. Polar code decoding

[0091] In the process of Polar code decoding, the Polar code can be decoded by SC algorithm. In the SC algorithm, the LLR of the information bit is calculated step by step. For the information bit position, if the LLR>0, the bit is determined as 0; if the LLR<0, the bit is determined as 1. For the frozen bit position, no matter what the value of the LLR is, the bit is set to 0.

[0092] Fig. 5 is a schematic diagram of SC decoding. As shown in Fig. 5, there are totally 8 computing nodes, including 4 f nodes and 4 g nodes. The computation of an f node requires 2 LLR inputs from its right side, and the computation of a g node requires 2 LLR inputs from its right side and 1 "Partial Sum" input from above. The output can be computed only after the computation of the input is completed. According to the above rules, as shown in Fig. 4, the 8 nodes are computed in sequence starting from the right side of the received signal, and the decoding order is ①→②→③→④, which is the SC decoding process.

[0093] It should be understood that, since the information bits only have two values of 0 and 1, the SC decoding of the Polar code can be abstracted as a binary tree search problem. Further, since each step of hard decision is only based on local information, the SC can also be regarded as a kind of greedy search algorithm.

[0094] In the process of Polar code decoding, the Polar code can be decoded by the SCL algorithm. The SCL algorithm is an extension of the SC algorithm.

[0095] Fig. 6 is a schematic diagram of a binary tree of Polar code SCL-2 decoding. As shown in Fig. 6, instead of directly determining the decoding result by hard decision in the middle process, the SCL algorithm saves both the decoding results corresponding to 0 and 1 as two branch decoding paths. By the above method, the SCL algorithm can save a total of L decoding paths, and finally selects the correct path by the path metric (PM) used to judge the path quality, i.e., outputs the path with the optimal PM as the final codeword. The SCL decoder outputs the path with the smaller PM (more like the correct codeword) of the two paths shown in Fig. 6 as the final decoding result.

[0096] In the process of Polar code decoding, the Polar code can be decoded by the CA-SCL algorithm. The CA-SCL algorithm performs CRC check on each path according to the PM value of the path in ascending order of the PM value, and selects the first path that passes the CRC check as the final codeword. If all paths do not pass the CRC check, the decoding is declared to fail.

[0097] It should be understood that, compared with the CA-SCL decoding algorithm, the SCL decoding algorithm outputs the path with the minimum PM as the final codeword, while the CA-SCL decoding algorithm starts from the path corresponding to the minimum PM value and filters out the correct path by CRC checking, thereby obtaining better error correction performance than the SCL decoding algorithm. It can be seen that the CA-SCL algorithm significantly improves the performance of the Polar code, and therefore, the CA-SCL algorithm is a common algorithm for the current Polar code application. In particular, in the medium-short code region, the CA-SCL algorithm enables the Polar code to show stronger competitiveness in code type comparison, and promotes the commercial use of the Polar code in 5G new radio (NR).

[0098] Based on the above introduction, it can be seen that in the PCCA-Polar code encoding process, the CRC precoding and the PC precoding are effective ways to improve the spectrum of the polar code, and when the CRC precoding and the PC precoding coexist, the placement method of the PC bit may affect the CA-SCL decoding performance.

[0099] Next, two PC bit placement methods will be introduced.

[0100] Method 1: Place the PC bit in the position with the lowest reliability of the sequence.

[0101] It should be understood that, in the case of E r -K r +3≤192, method 1 is performed. Wherein, E r represents the length of the sequence after rate matching, K r represents the length of the information bit.

[0102] For example, the length of the sequence is N = 16, and the number of PC bits is 3, then the 3 PC bits are placed in the 3 positions with the lowest reliability of the sequence with a length of 16. As shown in (1) of FIG. 7, the PC bit is located in the first 3 positions with the lowest reliability of the sequence.

[0103] Method 2: Place the PC bit in the position with the highest reliability and the minimum row weight (referred to as wmin) corresponding to the current position.

[0104] It should be understood that, in the case of E r -K r +3>192, method 2 is performed.

[0105] Wherein, each position included in the sequence corresponds to a row weight, which generally represents w. The row weight corresponding to the current position can be calculated in the following way:

[0106] Suppose the number of the current position is i, the row weight corresponding to the position i is wherein the binary representation of the i is (b0, b1, b2,.., b m-1 ). For example, the i = 0, the binary representation of the 0 is (0), then the row weight of the position 0 is 1; for example, the i = 7, the binary representation of the 7 is (1, 1, 1), then the row weight of the position 7 is 2 3 = 8.

[0107] For example, the PC bits are placed in the position with the highest reliability and the row weight of the current position is the minimum row weight. As shown in (2) of FIG. 7, two of the three PC positions are located in the two positions with the lowest sequence reliability, and one is located in the position with the highest sequence reliability and the row weight of the current position is the minimum row weight. The PC bit located in the position with the highest sequence reliability and the row weight of the current position is the minimum row weight can be referred to as a wmin PC bit, and the number of the wmin PC bits can be represented as n wmin , that is, the example in (2) of FIG. 7, the n wmin = 1.

[0108] Based on the placement manner of the PC bits introduced in the above manner 1 and manner 2, the manner 1 does not trigger n r , and directly places the PC bits in the bit position with the lowest sequence reliability when E r -K wmin + 3 ≤ 192; the manner 2 triggers n r when E r -K wmin + 3 > 192, and one PC bit is placed in the bit position with the highest reliability and the row weight equal to wmin, and the remaining PC bits are placed in the bit position with the lowest sequence reliability. It can be seen that the manner 1 does not have wmin PC bits, that is, the code spectrum cannot be improved by using the PC bits, and the manner 2 has wmin PC bits, but the placement position of the wmin PC bits is the position with the minimum row weight and the highest reliability, that is, the manner 2 improves the code spectrum by using the PC bits, but sacrifices the reliability of the message set.

[0109] Based on the above manners, if the current PC bit is a wmin PC bit and the current PC bit position is not the position with the lowest sequence reliability during the decoding process, the wmin PC bit sacrifices the reliability of the current wmin position for placing the PC bit, thereby losing the reliability of the message set, and further affecting the decoding performance of the Polar code.

[0110] In view of the problems of the above manner 1 and manner 2, the present application provides a method for encoding and decoding, which can improve the code spectrum by using the PC bits during the Polar code encoding process while ensuring the reliability of the information bits.

[0111] It should be understood that the reliability in this application can be understood as sequence reliability or Gaussian approximation reliability. The sequence reliability is taken as an example for description in the embodiments of this application.

[0112] It should also be understood that the sequence before polarization encoding includes N to-be-encoded positions with different reliabilities. The N is a power of 2. Generally, A information bits need to be placed in the A most reliable positions in the sequence, and the remaining N-A positions are used to place frozen bits. The receiving end and the decoding side know the values at the frozen positions in advance, and the frozen bit values can be fixed as 0. n PC positions in the frozen positions can be selected as dynamic frozen bit positions, or PC bit positions, or PC positions. The values of the PC positions are related to the values of the message bits before the PC positions, and the specific values are determined according to the PC check equation.

[0113] FIG. 8 is a schematic flowchart of encoding and decoding provided by an embodiment of this application. As shown in FIG. 8:

[0114] It should be understood that the method shown in FIG. 8 can be performed by an encoding device and a decoding device. Unless otherwise specified, the “encoding device” or “decoding device” can refer to the encoding device or decoding device itself, or can refer to an apparatus capable of supporting the encoding device or decoding device to implement the function. For the convenience of description, the encoding device and the decoding device are used to describe below. The encoding device can be a terminal device or a network device, and the decoding device can be a terminal device or a network device.

[0115] It should also be understood that the encoding device is also referred to as a “sending end device” or a “sending device”, and the decoding device is also referred to as a “receiving end device” or a “receiving device”.

[0116] 801. The encoding device obtains A information bits and the number n PC of PC bits.

[0117] The A information bits include K message bits and L CRC bits. The A, K, L, and n PC are all positive integers.

[0118] It should be understood that the values of A, K, L, and n PC are not limited in this application. The values of the above parameters can be determined by negotiation between the encoding device and the decoding device, or determined by the encoding device itself, or predefined by the system / protocol, or determined by the decoding device and indicated to the encoding device.

[0119] 802. The encoding device generates a first sequence.

[0120] It should be understood that the first sequence includes N bits, and the N bits include A information bits and nPC A information bits and n PC PC bits are located in the first sequence in the (A+n PC ) positions with the highest sequence reliability.

[0121] Wherein, the N is 2 raised to the power of n, n is a positive integer. For example, n = 4, N is 16, n = 8, N is 256.

[0122] It should be understood that the N bits in the first sequence correspond to N positions one by one, and the reliability of the N positions corresponding to the N bits is not the same. The reliability can refer to the sequence reliability, or the Gaussian approximation reliability, and the sequence reliability in the embodiments of the application is taken as an example for introduction, of course, the sequence reliability in the application can be replaced by the Gaussian approximation reliability. Wherein, the Gaussian approximation reliability is the reliability calculated based on Gaussian approximation.

[0123] It should also be understood that the n PC PC bits can be divided into PC bits and PC bits. Wherein, PC bits are located in the first position set, PC bits are located in the second position set. is a positive integer greater than or equal to 0.

[0124] Wherein, the first position set S1 is a position set composed of (A+n PC ) bit positions, and the first position set S1 includes the (A+n PC ) bit positions with the highest sequence reliability in the first sequence. The second position set is a position set composed of the A bit positions with the highest sequence reliability in the first sequence, that is, the second position set includes the A bit positions with the highest sequence reliability in the first sequence, or it can also be understood that the second position set includes the A bit positions with the highest sequence reliability in the first position set.

[0125] Wherein, PC bits are located in the first position set S1 in the bit position with the lowest sequence reliability, PC bits are located in the second position set S2 in the bit position with the minimum row weight and the lowest sequence reliability.

[0126] It should be understood that assuming The value is 1, the PC bits are located in the second position set S2 in the 1 bit position with the minimum row weight and the lowest sequence reliability; and assuming The value is greater than 1 (for example When ), the number of bit positions with the smallest row weight in the second position set S2 is 1. Therefore, the two PC bits are located at the bit position with the smallest row weight and lowest sequence reliability in the second position set S2, and the bit position with the second smallest row weight and lowest sequence reliability, respectively. That is, it can be understood that when When the value of is greater than or equal to 2, the The bits located in the second position set S2, with row weights increasing from smallest to largest, and the sequence with the lowest reliability. Each bit position.

[0127] Next, for n PC An exemplary method for determining the specific position of each PC bit in the first sequence is described.

[0128] Method 1

[0129] It should be understood that n PC The i-th PC position in a set of PC bits is determined by the row weight corresponding to the i-th candidate position in the third position set S3 and the minimum row weight corresponding to the second position set S2, where the third position set S3 indicates the n-th position in the first position set S1 with the lowest sequence reliability. PC There are n positions, 1≤i≤n PC .

[0130] In one possible implementation, if the row weight corresponding to the i-th candidate position is less than the minimum row weight corresponding to the second position set S2, the first position in the fourth position set S4 is taken as a PC position. The first position is the position with the lowest reliability in the fifth position set S5. The fifth position set S5 includes the positions in the fourth position set S4 whose row weight is equal to the minimum row weight corresponding to the second position set S2. The fourth position set S4 is composed of the second position set S2 and the i-th candidate position.

[0131] In one possible implementation, if the row weight corresponding to the i-th candidate position is greater than or equal to the minimum row weight corresponding to the second position set S2, the position with the lowest sequence reliability in the fourth position set S4 is taken as a PC position.

[0132] Example 1:

[0133] Assume A = 21, N = 256, n PC= 3, wherein A information bits are located in the A positions of the first sequence with the highest sequence reliability. In Table 1, the rightmost sequence reliability is the highest, and the leftmost sequence reliability is the lowest. The first position set is the 24 positions corresponding to the sequence indexes (220, 232, 249,..., 256) in Table 1, and the second position set includes the A positions with the highest sequence reliability in Table 1, that is, the second position set S2 is the 21 positions corresponding to the sequence indexes (191, 222, 236,..., 256) in Table 1. In the initial state, the A information bits are located in the second position set S2, and the minimum row weight corresponding to the second position set S2 is 64. The third position set S3 includes the 3 positions with the lowest sequence reliability in the first position set, that is, the third position set S3 is the 3 positions corresponding to the sequence indexes (220, 232, 249) in Table 1.

[0134] Table 1

[0135] In combination with Table 1 described above: the first candidate position (for example, the position corresponding to the sequence index 249) in the third position set S3 corresponds to a row weight of 32, the row weight 32 corresponding to the first candidate position is less than the minimum row weight 64 corresponding to the second position set S2, that is, the first position in the fourth position set S4 is taken as a PC bit. The fourth position set S4 is composed of the second position set S2 and the first candidate position, for example, the fourth position set S4 is the position set corresponding to the sequence indexes 249, 191, 222, 236,..., 256 in Table 1. The first position is the position with the lowest reliability in the fifth position set S5, the fifth position set S5 includes the positions in the fourth position set S4 with the row weight equal to the minimum row weight corresponding to the second position set S2, and the fifth position set S5 is the position set corresponding to the sequence indexes 191, 222, 236, 223, 238, 244, 239, 246, 247, 250, 251 in Table 1. It can be seen that the first position is the position corresponding to the sequence index 191 in Table 1, that is, the first position is taken as a PC bit.

[0136] In combination with Table 1 described above: the second candidate position (for example, the position corresponding to the sequence index 232) in the third position set S3 corresponds to a row weight of 64, the row weight 64 corresponding to the second candidate position is equal to the minimum row weight 64 corresponding to the second position set S2, that is, the position with the lowest sequence reliability in the fourth position set S4 is taken as a PC bit. In this case, the fourth position set S4 is composed of the second position set S2 and the second candidate position, for example, the fourth position set S4 is the position set corresponding to the sequence indexes 232, 191, 222, 236,..., 256 in Table 1. The position with the lowest sequence reliability in the fourth position set S4 (for example, the position corresponding to the sequence index 232) is taken as a PC position.

[0137] In combination with the above Table 1, the row weight corresponding to the 3rd candidate position (e.g. the position corresponding to sequence index 220) in the third position set S3 is 64, and the row weight corresponding to the 2nd candidate position is 64, which is equal to the minimum row weight 64 corresponding to the second position set S2, i.e. the position with the lowest sequence reliability in the fourth position set S4 is taken as a PC bit. The fourth position set S4 is composed of the second position set S2 and the 3rd candidate position, for example, the fourth position set S4 is the position set corresponding to sequence indexes 220, 191, 222, 236, …, 256 in Table 1. The position with the lowest sequence reliability in the fourth position set S4 (e.g. the position corresponding to sequence index 220) is taken as a PC position.

[0138] It should be understood that based on the example shown in the above Table 1, i.e. the 3 candidate positions included in the third position set S3 can determine 3 PC positions (e.g. the positions corresponding to sequence indexes 191, 232, 220) respectively in different cases. The order of determining the PC positions by the 3 candidate positions included in the third position set S3 is not limited in the present application, for example, the 3 candidate positions can simultaneously determine 3 PC positions, or determine 3 PC positions in sequence, which is not limited in the present application.

[0139] Example II:

[0140] It should be understood that when the PC positions determined by at least two candidate positions in the third position set S3 are the same, i.e. the first position in the fourth position set S4 determined by the at least two candidate positions in the third position set S3 is the same, wherein one candidate position (e.g. the first candidate position) in the at least two candidate positions determines the first position as a PC position, and the other candidate position (e.g. the second candidate position) in the at least two candidate positions needs to determine a PC position again.

[0141] The PC position determined by the second candidate position is determined according to the row weight corresponding to the second candidate position and the minimum row weight corresponding to the updated second position set S2, and the updated second position set S2 is a position set determined after deleting the PC position in the fourth position set S4.

[0142] Suppose A = 21, N = 256, n PC= 3, wherein A information bits are located in the first sequence in A positions with the highest sequence reliability, wherein the rightmost sequence reliability in Table 2 is the highest and the leftmost sequence reliability in Table 2 is the lowest. The first position set is the 24 positions corresponding to the sequence indexes (243, 249, 190, 256) in Table 2, and the second position set includes A positions with the highest sequence reliability in Table 2, i.e., the second position set S2 is the 21 positions corresponding to the sequence indexes (191, 216, 220, 256) in Table 2. In the initial state, the A information bits are located in the second position set S2, and the minimum row weight corresponding to the second position set S2 is 64. The third position set S3 includes 3 positions with the lowest sequence reliability in the first position set, i.e., the third position set S3 is the 3 positions corresponding to the sequence indexes (243, 249, 190) in Table 2.

[0143] Table 2

[0144] In combination with Table 2 described above: the first candidate position (e.g., the position corresponding to the sequence index 190) in the third position set S3 corresponds to a row weight of 64, and the row weight 64 corresponding to the first candidate position is equal to the minimum row weight 64 corresponding to the second position set S2, i.e., the position with the lowest sequence reliability in the fourth position set S4 is taken as a PC bit. The fourth position set S4 is composed of the second position set S2 and the first candidate position, e.g., the fourth position set S4 is the position set corresponding to the sequence indexes 190, 191, 216, 220, 256 in Table 2. The position (e.g., the position corresponding to the sequence index 190) with the lowest sequence reliability in the fourth position set S4 is taken as a PC position.

[0145] In combination with Table 2 described above: the second candidate position (e.g., the position corresponding to the sequence index 249) in the third position set S3 corresponds to a row weight of 32, and the row weight 32 corresponding to the second candidate position is less than the minimum row weight 64 corresponding to the second position set S2, i.e., the first position in the fourth position set S4 is taken as a PC bit. The fourth position set S4 is composed of the second position set S2 and the second candidate position, e.g., the fourth position set S4 is the position set corresponding to the sequence indexes 249, 191, 216, 220, 256 in Table 2. The first position is the position with the lowest reliability in the fifth position set S5, the fifth position set S5 includes positions with a row weight equal to the minimum row weight corresponding to the second position set S2 in the fourth position set S4, and the fifth position set S5 is the position set corresponding to the sequence indexes 191, 216, 220, 239, 247, 250, 251, 253 in Table 2. It can be seen that the first position is the position corresponding to the sequence index 191 in Table 2, i.e., the first position is taken as a PC bit.

[0146] According to the above table 2, the row weight of the third candidate position (for example, the position corresponding to the sequence index 243) in the third position set S3 is 32. The row weight 32 of the third candidate position is less than the minimum row weight 64 of the second position set S2, that is, the first position in the fourth position set S4 is taken as a PC bit. The fourth position set S4 is composed of the second position set S2 and the third candidate position. For example, the fourth position set S4 is the position set corresponding to the sequence indexes 243, 191, 216, 220, …, 256 in table 2. The first position is the position with the lowest reliability in the fifth position set S5. The fifth position set S5 includes positions with the minimum row weight of the second position set S2 in the fourth position set S4. The fifth position set S5 is the position set corresponding to the sequence indexes 191, 216, 220, …, 239, 247, 250, 251, 253 in table 2. It can be seen that the first position is the position corresponding to the sequence index 191 in table 2, that is, the first position is taken as a PC bit.

[0147] It can be seen that the PC positions determined by the second candidate position (for example, the position corresponding to the sequence index 249) in the third position set S3 and the third candidate position (for example, the position corresponding to the sequence index 243) in the third position set S3 are both the position corresponding to the sequence index 191. It is assumed that the second candidate position in the third position set S3 takes the position corresponding to the sequence index 191 as a PC position in advance, that is, the third candidate position in the third position set S3 re-determines the PC position. The PC position determined by the third candidate position is determined according to the row weight corresponding to the third candidate position and the minimum row weight of the updated second position set S2.

[0148] As shown in table 2, the updated second position set S2 is the position set corresponding to the indexes 249, 216, 220, …, 256 in table 2. The minimum row weight of the updated second position set is 32. The row weight of the third candidate position (for example, the position corresponding to the sequence index 243) in the third position set S3 is 32. The row weight 32 of the third candidate position is equal to the minimum row weight 32 of the updated second position set S2, that is, the position with the lowest sequence reliability in the fourth position set S4 is taken as a PC bit. The fourth position set S4 is composed of the updated second position set S2 and the third candidate position. For example, the fourth position set S4 is the position set corresponding to the sequence indexes 243, 249, 216, 220, …, 256 in table 2. The position with the lowest sequence reliability (for example, the position corresponding to the sequence index 243) in the fourth position set S4 is taken as a PC position.

[0149] Method 2

[0150] It should be understood that the n PC th PC position in the PC bits is determined according to the jth candidate position in the third position set S3 and the minimum row weight corresponding to the second position set S2, 1≤j≤n PC -1.

[0151] The third position set S3 indicates n PC positions in the first position set S1 with the lowest sequence reliability, and the n PC positions in the third position set S3 are sequentially determined as candidate positions in the order from high to low sequence reliability, the jth candidate position is the jth highest position in the n PC positions in sequence reliability, and the fourth position set S4 is composed of the jth candidate position in the third position set S3 and the second position set S2. When j=1, the fourth position set S4 indicates A+1 positions in the first sequence with the highest reliability, 1≤j≤n PC -1.

[0152] In one possible implementation, if the row weight corresponding to the jth candidate position is less than the minimum row weight corresponding to the second position set S2, the position with the lowest sequence reliability in the fifth position set S5 is taken as the jth PC position, and the fifth position set S5 indicates the position set in the fourth position set S4 with the row weight equal to the minimum row weight corresponding to the second position set S2. If the row weight corresponding to the jth candidate position is greater than or equal to the minimum row weight corresponding to the second position set S2, the position with the lowest sequence reliability in the fourth position set S4 is taken as the jth PC position. After determining the jth PC position, the second position set S2 is updated, and the updated second position set S2 is the position set corresponding to the fourth position set S4 after deleting the jth PC position; the fourth position set S4 is updated, and the updated fourth position set S4 includes the updated second position set S2 and the j+1th candidate position; the j+1th PC position is determined based on the row weight corresponding to the j+1th candidate position and the minimum row weight corresponding to the updated second position set S2, and the above operation is repeated until n PC PC positions are obtained.

[0153] It can be seen that the n PC PC positions are dynamically determined according to the minimum row weight in the current second position set. With each PC position added, the minimum row weight of the second position set may change, for example, the minimum row weight corresponding to the second position set may be lower, unchanged or increased compared to the minimum row weight of the original second position set.

[0154] Suppose the number of PC bits is n PC , the nPC The specific position of each PC bit can be determined using the following pseudocode:

[0155] Based on the pseudocode above, the following will illustrate with specific examples:

[0156] Example 3

[0157] Assume A = 21, N = 256, n PC =3, where A information bits are located at the A positions with the highest sequence reliability in the first sequence. Among them, the rightmost sequence in Table 3 has the highest reliability, and the leftmost sequence has the lowest reliability. The first position set S1 consists of 24 positions corresponding to sequence indices 220, 232, ..., 256 in Table 3. The position corresponding to sequence index 220 is the position with the lowest sequence reliability in the first position set S1, and the position corresponding to sequence index 256 is the position with the highest sequence reliability in the first position set S1. The second position set S2 consists of 21 positions corresponding to sequence indices 191, 222, 236, ..., 256. In the initial state, the A information bits are located in the second position set S2, and the minimum row weight corresponding to the second position set S2 is 64. The third position set S3 consists of 3 positions corresponding to sequence indices 220, 232, 249. The first candidate position in the third position set S3 is the position corresponding to sequence index 249, which is the position with the highest sequence reliability in the third position set S3.

[0158] Table 3

[0159] Referring to Table 3 above: If the row weight corresponding to the first candidate position in the third position set S3 (e.g., the position corresponding to sequence index 249) is 32, and the row weight 32 corresponding to the first candidate position is less than the minimum row weight (or first minimum row weight) 64 corresponding to the second position set S2, then the position with the lowest sequence reliability in the fifth position set S5 is taken as the first PC position. The fifth position set S5 indicates the set of positions in the fourth position set S4 whose row weight is equal to the first minimum row weight. The fourth position set S4 includes the second position set S2 and the first candidate position. For example, the fourth position set S4 is the set of positions corresponding to sequence indices 249, 191, 222, 236, ..., 256 in Table 3, and the fifth position set S5 is the set of positions corresponding to sequence indices 191, 222, 236, ..., 246, 247, 250, 251, 253 in Table 3. As can be seen, the PC position determined by the first candidate position is the position corresponding to sequence index 191 in Table 3, that is, the first position is taken as a PC bit.

[0160] The second position set S2 after the first update indicates the position set corresponding to the sequence indexes 249, 222, 236, …, 256, or the second position set S2 after the first update indicates the position set corresponding to the sequence indexes 249, 222, 236, …, 256. The minimum row weight (or referred to as the second minimum row weight) corresponding to the second position set S2 after the first update is updated from 64 to 32.

[0161] In combination with the above Table 3, if the second candidate position (for example, the position corresponding to the sequence index 232) in the third position set S3 corresponds to a row weight of 64, the row weight 64 corresponding to the second candidate position is greater than the second minimum row weight 32, and the position with the lowest sequence reliability in the fourth position set S4 after the first update is taken as the second PC position. The fourth position set S4 after the first update indicates the positions corresponding to the sequence indexes 232, 249, 222, …, 256 in Table 3. The second candidate position takes the position with the lowest reliability in the fourth position set S4 after the first update as the second PC position, that is, takes the position corresponding to the sequence index 232 as the second PC position.

[0162] The second position set S2 after the first update indicates the position set corresponding to the sequence indexes 249, 222, 236, …, 256, or the second position set S2 after the first update indicates the position set corresponding to the sequence indexes 249, 222, 236, …, 256. The minimum row weight (or referred to as the second minimum row weight) corresponding to the second position set S2 after the first update is updated from 64 to 32.

[0163] In combination with the above Table 3, if the second candidate position (for example, the position corresponding to the sequence index 232) in the third position set S3 corresponds to a row weight of 64, the row weight 64 corresponding to the second candidate position is greater than the second minimum row weight 32, and the position with the lowest sequence reliability in the fourth position set S4 after the first update is taken as the second PC position. The fourth position set S4 after the first update indicates the positions corresponding to the sequence indexes 232, 249, 222, …, 256 in Table 3. The second candidate position takes the position with the lowest reliability in the fourth position set S4 after the first update as the second PC position, that is, takes the position corresponding to the sequence index 232 as the second PC position.

[0164] Fig. 9 is a code spectrum diagram of a Polar code determined based on the data in the above-described Example Three, in which the horizontal coordinate represents the code distance and the vertical coordinate represents the number of code. As can be seen, one of the three PC positions determined in the above-described Example Three is located at the position with the minimum row weight and the lowest reliability in the second position set, that is, the position corresponding to the sequence index 249 in Example Three. The PC position method in this approach balances the effects of minimizing reliability loss and improving code spectrum. In this example three, the minimum number of codewords is small, and the error correction capability is strong.

[0165] Example 4

[0166] Assume A = 25, N = 256, n PC =3, where A information bits are located at the A positions with the highest sequence reliability in the first sequence. Among them, the rightmost sequence in Table 4 has the highest reliability, and the leftmost sequence has the lowest reliability. The first position set S1 consists of 28 positions corresponding to sequence indices 243, 245, ..., 256 in Table 4. The position corresponding to sequence index 243 is the position with the lowest sequence reliability in the first position set S1, and the position corresponding to sequence index 256 is the position with the highest sequence reliability in the first position set S1. The second position set S2 consists of 25 positions corresponding to sequence indices 216, 220, 232, ..., 256. In the initial state, the A information bits are located in the second position set S2, and the minimum row weight corresponding to the second position set S2 is 32. The third position set S3 consists of 3 positions corresponding to sequence indices 243, 245, and 190. The first candidate position in the third position set S3 is the position corresponding to sequence index 190, which is the position with the highest sequence reliability in the third position set S3.

[0167] Table 4

[0168] Referring to Table 4 above: If the row weight corresponding to the first candidate position in the third position set S3 (e.g., the position corresponding to sequence index 190) is 64, and this row weight 64 is greater than the minimum row weight (or first minimum row weight) 32 corresponding to the second position set S2, then the position with the lowest sequence reliability in the fourth position set S4 is taken as the first PC position. This fourth position set S4 indicates the positions corresponding to sequence indices 190, 216, 220, 232, ..., 256 as shown in Table 4. The first candidate position is the position with the lowest reliability in the fourth position set S4, that is, the position corresponding to sequence index 190 is taken as the first PC position.

[0169] The second position set S2, after its first update, becomes the set of positions corresponding to sequence indices 216, 220, 232, ..., 256. Alternatively, the updated second position set S2 indicates the set of positions corresponding to sequence indices 216, 220, 232, ..., 256. It is evident that the minimum row weight (or second minimum row weight) corresponding to the updated second position set S2 remains unchanged at 32.

[0170] In combination with the above Table 4, if the second candidate position (e.g., the position corresponding to the sequence index 245) in the third position set S3 corresponds to a row weight of 32, the row weight 32 corresponding to the second candidate position is equal to the second minimum row weight 32, and the position with the lowest sequence reliability in the first updated fourth position set S4 is taken as the second PC position. The first updated fourth position set S4 indicates the positions corresponding to the sequence indexes 245, 216, 220, …, 256 in Table 4. The second candidate position takes the position corresponding to the sequence index 245 in the first updated fourth position set S4 as the second PC position.

[0171] The second updated second position set S2 is updated for the second time to obtain a position set corresponding to the sequence indexes 216, 220, 232, …, 256, or the second updated second position set S2 indicates the position set corresponding to the sequence indexes 216, 220, 232, …, 256. The minimum row weight (or the third minimum row weight) corresponding to the second updated second position set S2 is 32.

[0172] In combination with the above Table 4, if the third candidate position (e.g., the position corresponding to the sequence index 243) in the third position set S3 corresponds to a row weight of 32, the row weight 32 corresponding to the third candidate position is equal to the third minimum row weight 32, and the position with the lowest sequence reliability in the second updated fourth position set S4 is taken as the third PC position. The second updated fourth position set S4 indicates the positions corresponding to the sequence indexes 243, 216, 220, …, 256 in Table 4. The third candidate position takes the position corresponding to the sequence index 243 in the second updated fourth position set S4 as the third PC position.

[0173] Optionally, the n PC positions can be located in the n PC bit positions with the lowest sequence reliability in the first position set S1, or the n PC positions can be composed of the position with the lowest sequence reliability in the second position set S2 and the position set other than the second position set S2 in the first position set S1. PC PC bit positions with the lowest sequence reliability in the position set other than the second position set S2 in the first position set S1. bit positions with the lowest sequence reliability in the position set other than the second position set S2 in the first position set S1.

[0174] It should be understood that the A information bits are located in the positions other than the n PC bit positions in the first position set S1. PC

[0175] ​​​803, the encoding device performs Polar encoding on the first sequence to obtain a Polar codeword sequence.

[0176] The encoding device performs Polar encoding on the first sequence determined in step 802 to obtain a Polar codeword sequence. The step is similar to the Polar encoding process, and details can be referred to the Polar encoding process of the encoding device, which will not be described here.

[0177] 804, the encoding device sends the Polar codeword sequence. Correspondingly, the decoding device receives a symbol sequence.

[0178] It should be noted that the Polar codeword sequence may introduce channel noise signals in the transmission process. The Polar codeword sequence output or sent by the encoding device and the codeword sequence received by the decoding device may be different. The symbol sequence is the Polar codeword sequence sent by the encoding device in the transmission process, and the sequence obtained by introducing channel noise signals is called a symbol sequence.

[0179] 805, the decoding device decodes the symbol sequence to obtain a first path.

[0180] After receiving the symbol sequence, the decoding device decodes the symbol sequence, for example, using the CA-SCL algorithm to decode the symbol sequence. In the CA-SCL decoding process of the decoding device on the symbol sequence, the first path with the minimum PM value and passing the CRC check is taken as the first path.

[0181] The first path is the path with the minimum PC value and passing the CRC check.

[0182] 806, the decoding device determines the first sequence according to the first path.

[0183] The decoding device determines the first sequence according to the first path. The first sequence is the same as the first sequence generated in step 802 described above, and details can be referred to the description of the sending device described above, which will not be described here.

[0184] 807, determine A information bits according to the first sequence.

[0185] According to the placement method of n PC PC bits introduced in the method shown in FIG. 8, The bits are located in the A The bits are located in the A The bits are located in the A The method can not only reserve the PC bits to assist the path metric value in coding path selection, ensure the reliability of path selection, and improve the code spectrum, but also avoid the placement position of the PC bits from affecting the reliability of the message set and ensuring the reliability of the information bits.

[0186] The communication method provided in the present application is described in detail above, and the communication device provided in the present application is introduced below.

[0187] As shown in FIG. 10, the present application provides a communication device 1000.

[0188] The communication device 1000 can be an encoding device, or a device applied to an encoding device and capable of realizing the corresponding functions of the encoding device in the embodiment of the present application in FIG. 8, such as a chip, a chip system, or a circuit.

[0189] Optionally, the communication device 1000 includes a communication module 1002 and a processing module 1001, which can be a processor, a processing board, a processing unit, or a processing device. The communication module can also be referred to as a transceiver module, a transceiver, a transceiver, or a transceiver device, and is used to perform receiving (or inputting) and / or sending (or outputting) operations.

[0190] For example, the communication module 1002 is configured to obtain A information bits and the number n of parity check PC bits PC ; the processing module 1001 is configured to generate a first sequence and perform Polar encoding on the first sequence to obtain a Polar codeword sequence, and the communication module 1002 is further configured to send the Polar codeword sequence, and the like. The specific process can refer to the detailed description in the embodiment of the present application in FIG. 8, and will not be described here.

[0191] Alternatively, the communication device 1000 shown in FIG. 10 can be a decoding device, or a device applied to a decoding device and capable of realizing the corresponding functions of the decoding device in the communication method 300 and the communication method 400 of the embodiment of the present application, such as a chip, a chip system, or a circuit.

[0192] Optionally, the communication device 1000 includes a communication module 1002 and a processing module 1001, which can be a processor, a processing board, a processing unit, or a processing device. The communication module can also be referred to as a transceiver module, a transceiver, a transceiver, or a transceiver device, and is used to perform receiving (or inputting) and / or sending (or outputting) operations.

[0193] For example, the communication apparatus 1000 is configured to receive a sequence of symbols, and the processing module 1001 is configured to decode the sequence of symbols to obtain a first path, and determine a first sequence according to the first path. The processing module 1001 is further configured to determine A information bits according to the first sequence, and the like. Details can be referred to the description of the embodiment of the application in FIG. 8, which will not be repeated here.

[0194] In some embodiments, the foregoing communication module and / or processing module can be implemented by a virtual module, for example, the processing module can be implemented by a software function unit or a virtual device, and the communication module can be implemented by a software function or a virtual device. Alternatively, the processing module or the communication module can also be implemented by an entity device, for example, if the device is implemented by a chip / circuit (for example, an integrated circuit, a special-purpose circuit, a logic circuit, etc.). The communication module can be an input / output circuit and / or a communication interface, which performs an input operation (corresponding to the foregoing receiving operation) and an output operation (corresponding to the foregoing sending operation); and the processing module is an integrated processor or a microprocessor or a circuit (for example, an integrated circuit, a logic circuit, etc.).

[0195] The division of the modules in the present application is illustrative, and is only a logical function division. In actual implementation, another division manner can be used. In addition, each function module in each example of the present application can be integrated in one processor, or can be physically separated, or two or more modules can be integrated in one module. The integrated module can be implemented in the form of hardware or in the form of a software function module.

[0196] As shown in FIG. 11, the present application further provides a communication apparatus 1100. The communication apparatus 1100 includes at least one processor 1110, which implements the functions of the encoding device or the decoding device described in the foregoing method embodiments.

[0197] Optionally, the processor 1110 is coupled with a memory. The memory can be located in the communication apparatus, or the memory can be integrated with the processor, or the memory can be located outside the communication apparatus. The communication apparatus 1100 can further include at least one memory 1120. The memory 1120 stores computer programs, instructions or data necessary for implementing any one of the foregoing method embodiments. The processor 1110 can execute the computer programs, instructions or data stored in the memory 1120 to complete the communication method of any one of the foregoing embodiments.

[0198] Optionally, the communication apparatus 1100 can further include a communication interface 1130. The communication apparatus 1100 can exchange information with other devices through the communication interface 1130. For example, the communication interface 1130 can be a transceiver, a circuit, a bus, a module, a pin or other types of interfaces.

[0199] The coupling in the present application is an indirect coupling or communication connection between devices, units or modules, which can be electrical, mechanical or other forms, for information interaction between devices, units or modules. The processor 1110 can operate in conjunction with the memory 1120 and the communication interface 1130. The specific connection medium between the processor 1110, the memory 1120 and the communication interface 1030 is not limited in the present application.

[0200] It should be understood that when the communication device 1100 is used as an encoding device or a chip applied to an encoding device, and performs the steps performed by the encoding device in the above method embodiments. The transceiver module is used to specifically perform the sending and / or receiving actions performed by the encoding device, for example, supporting other processes of the encoding device to perform the techniques described herein. The processing module can be used to support the communication device to perform the processing actions in the above method embodiments, for example, supporting other processes of the encoding device to perform the techniques described herein.

[0201] As an example, when the encoding device or the decoding device is a terminal device or a network device, and the terminal device or the network device is a chip, the transceiver module can be a communication interface, a pin or a circuit, etc. The communication interface can be used to input data to be processed to the processor, and can output the processing result of the processor to the outside. In specific implementation, the communication interface can be a general purpose input output (GPIO) interface, and can be connected with a plurality of peripheral devices (such as a display (LCD), a camera, a radio frequency (RF) module, an antenna, etc.). The communication interface is connected with the processor through a bus.

[0202] The processing module can be a processor that can execute computer execution instructions stored in the storage module to cause the chip to perform the method involved in any of the embodiments. Further, the processor can include a controller, an arithmetic unit, and a register. For example, the controller is mainly responsible for instruction decoding and sending control signals for corresponding operations of the instructions. The arithmetic unit is mainly responsible for performing fixed-point or floating-point arithmetic operations, shift operations, and logic operations, etc., and can also perform address operations and conversion. The register is mainly responsible for storing register operands and intermediate operation results temporarily stored during instruction execution, etc. In a specific implementation, the hardware architecture of the processor can be an ASIC architecture, a microprocessor without interlocked piped stages architecture (MIPS) architecture, an advanced RISC machines (ARM) architecture, or a network processor (NP) architecture, etc. The processor can be single-core or multi-core. The storage module can be a storage module in the chip, such as a register, a cache, etc. The storage module can also be a storage module located outside the chip, such as a ROM or other types of static storage devices that can store static information and instructions, a RAM, etc.

[0203] It should be noted that the functions of the processor and the interface can be implemented by hardware design, software design, or a combination of software and hardware, and this is not limited here.

[0204] As shown in FIG. 12, the present application also provides a chip (or a chip system). The chip (or the chip system) 1200 can include a circuit 1210 and an input / output interface 1220. The circuit 1210 can be a logic circuit, an integrated circuit, etc., and the input / output interface 1220 can also be an input / output circuit or an interface circuit that can input information (or receive information) and output information (or send information). Optionally, the chip system can be composed of a chip, or can include a chip and other discrete devices. The chip 1200 can be used to perform the method performed by the encoding device or the decoding device in the embodiments of the present application.

[0205] In addition, the present application also provides a computer readable storage medium, which stores computer instructions, and when the computer instructions run on a computer, the operations and / or processes performed by the encoding device or the decoding device in the method embodiments of the present application are performed.

[0206] The present application also provides a computer program product, which comprises computer program codes or instructions, when the computer program codes or instructions are run on a computer, the operations and / or processes performed by the encoding device or the decoding device in any of the method embodiments of the present application are executed.

[0207] Further, the present application also provides a chip, which comprises a processor. A memory for storing a computer program is arranged independently of the chip, and the processor is configured to execute the computer program stored in the memory, so that the operations and / or processes performed by the encoding device or the decoding device in any of the method embodiments are executed. Further, the chip can also comprise a communication interface. The communication interface can be an input / output interface, an interface circuit or the like. Further, the chip can also comprise a memory, which stores codes and / or instructions required by the chip to execute the encoding method of the present application.

[0208] The present application provides a communication system, which comprises the encoding device in the embodiments of the present application and the decoding device, the encoding device is configured to implement the steps performed by the encoding device in the above method embodiments, and the decoding device is configured to implement the steps performed by the decoding device in the above method embodiments.

[0209] In the embodiments of the present application, "a plurality of" includes two or more.

[0210] Those skilled in the art can understand that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be realized by electronic hardware or a combination of computer software and electronic hardware. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0211] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described system, device and unit can refer to the corresponding processes in the foregoing method embodiments, which will not be described here.

[0212] In several embodiments provided in the present application, it should be understood that the disclosed system, device and method can be implemented in other manners. For example, the described device embodiments are merely schematic. The division of the units is merely logical function division. There can be other division manners in actual implementation. For example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections can be indirect couplings or communication connections through some interfaces, devices or units, and can be in electrical, mechanical or other forms.

[0213] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, i.e., can be located in one place, or can be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0214] In addition, each functional unit in the various embodiments of the present application can be integrated into a processing unit, or each unit can be a physically separate unit, or two or more units can be integrated into one unit.

[0215] If the functions are realized in the form of software function units and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application can be embodied in the form of a software product, and the computer software product is stored in a storage medium, and includes a number of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0216] The above description is merely a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. An encoding method characterized by, The method comprises: obtaining A information bits and a number n of parity check PC bits PC , the A information bits consisting of K message bits and L cyclic redundancy check CRC bits, the A, the K, the L and the n PC are positive integers; generating a first sequence, the first sequence comprising N bits, the N bits comprising the A information bits and the n PC PC bits, the A information bits and the n PC PC bits being located in (A+n PC ) positions of the first sequence with highest sequence reliability, wherein the N is 2 raised to the power of n, n being a positive integer, wherein, A PC bit is located in the sequence reliability lowest first position set S1 a bit position, A PC bit is located in the second set S2 of rows with the smallest weight and the lowest sequence reliability a first position set S1 is a position set of the (A+n PC ) bit positions in the first sequence, a second position set S2 is a position set of the A bit positions with the highest sequence reliability in the first sequence, and the an integer greater than or equal to 0; performing Polar encoding on the first sequence to obtain a Polar codeword sequence; sending the Polar codeword sequence.

2. The method of claim 1, wherein, n PC = 3, The n PC The first PC position in the three PC positions is determined according to the first candidate position in the third position set S3 and the first minimum row weight corresponding to the second position set S2. The third position set S3 includes three candidate positions, the third position set S3 indicates three positions with the lowest sequence reliability in the first position set S1, the first candidate position is a position with the highest sequence reliability in the third position set S3, if the row weight corresponding to the first candidate position is less than the first minimum row weight, a position with the lowest sequence reliability in the fifth position set S5 is taken as the first PC position, the fifth position set S5 indicates a position set with the first minimum row weight in the fourth position set S4, and the fourth position set S4 includes the second position set S2 and the first candidate position; if the row weight corresponding to the first candidate position is greater than or equal to the first minimum row weight, a position with the lowest sequence reliability in the fourth position set S4 is taken as the first PC position.

3. The method of claim 2, wherein the second candidate position is a position with the second highest sequence reliability in the third position set S3, the second position set S2 after the first update is a position set corresponding to the fourth position set S4 after the first candidate position is deleted, The n PC The second PC position in the 3 PC positions is determined according to the second minimum row weight corresponding to the second position set S2 after the first update and the row weight corresponding to the second candidate position in the third position set S3, if the row weight corresponding to the second candidate position is less than the second minimum row weight, a position with the lowest sequence reliability in the fifth position set S5 after the first update is taken as the second PC position, the fifth position set S5 after the first update indicates a position set equal to the second minimum row weight in the fourth position set S4 after the first update, and the fourth position set S4 after the first update includes the second position set S2 after the first update and the second candidate position; if the row weight corresponding to the second candidate position is greater than or equal to the second minimum row weight, a position with the lowest sequence reliability in the fourth position set S4 after the first update is taken as the second PC position.

4. The method of claim 3, wherein the third candidate position is a position with the lowest sequence reliability in the third position set S3, the second position set S2 after the second update is a position set corresponding to the fourth position set S4 after the first candidate position is deleted, if the row weight corresponding to the third candidate position is less than the third minimum row weight, a position with the lowest sequence reliability in the fifth position set S5 after the second update is taken as the third PC position, the fifth position set S5 after the second update indicates a position set equal to the third minimum row weight in the fourth position set S4 after the second update, and the fourth position set S4 after the second update includes the second position set S2 after the second update and the third candidate position; The n PC The third PC position in the 3 PC positions is determined according to the third minimum row weight corresponding to the third candidate position in the third position set S3 and the second position set S2 after the second update, ​ ​ If the row weight corresponding to the third candidate position is greater than or equal to the third minimum row weight, the PC position is the position with the lowest sequence reliability in the fourth position set S4 after the second update.

5. The method of claim 1, wherein, The n PC The jth PC position in the n PC positions is determined according to the jth candidate position in the third position set S3 corresponding to the row weight and the minimum row weight corresponding to the second position set S2. The third position set S3 indicates n positions with the lowest sequence reliability in the first position set S1 PC The n positions in the third position set S3 are sequentially determined as candidate positions in order of sequence reliability from high to low PC The jth candidate position is a position with the jth highest sequence reliability in the n positions PC The fourth position set S4 is composed of the second position set S2 and the jth candidate position in the third position set S3 PC -1, If the row weight corresponding to the jth candidate position is less than the minimum row weight corresponding to the second position set S2, the jth PC position is the position with the lowest sequence reliability in a fifth position set S5, the fifth position set S5 comprising a position set in the fourth position set S4 with a row weight equal to the minimum row weight corresponding to the second position set S2, If the row weight corresponding to the jth candidate position is greater than or equal to the minimum row weight corresponding to the second position set S2, the jth PC position is the position with the lowest sequence reliability in the fourth position set S4; updating the second position set S2, the updated second position set S2 being a position set corresponding to the fourth position set S4 after the jth PC position is deleted, updating the fourth position set S4, the updated fourth position set S4 comprising the updated second position set S2 and a (j+1)th candidate position; determining the j+1th PC position based on the row weight corresponding to the j+1th candidate position and the minimum row weight corresponding to the updated second position set S2, repeating the above operation until n PC positions are obtained. PC PC positions are obtained.

6. The method of claim 1, wherein, The n PC The i-th PC position in the n PC positions is determined according to the i-th candidate position in the third position set S3 corresponding to the row weight and the minimum row weight corresponding to the second position set S2. wherein the third set of positions S3 indicates n positions in the first set of positions S1 with the lowest sequence reliability, 1≤i≤n PC PC ,​ If the row weight corresponding to the ith candidate position is less than the minimum row weight corresponding to the second position set S2, the PC position is a first position in the fourth position set S4, the first position being the position with the lowest sequence reliability in a fifth position set S5, the fifth position set S5 comprising a position set in the fourth position set S4 with a row weight equal to the minimum row weight corresponding to the second position set S2, the fourth position set S4 being composed of the second position set S2 and the ith candidate position, If the row weight corresponding to the ith candidate position is greater than or equal to the minimum row weight corresponding to the second position set S2, the PC position is the position with the lowest sequence reliability in the fourth position set S4.

7. The method of claim 6, wherein, In the n PC ≥2, at least two candidate positions in the third position set S3 determine the same first position, and the first position is determined as the PC position of a first candidate position in the at least two candidate positions. the PC position determined by a second candidate position in the at least two candidate positions is determined according to a row weight corresponding to the second candidate position and a minimum row weight corresponding to an updated second position set S2, the updated second position set S2 being a position set corresponding to the fourth position set S4 after the PC position in the fourth position set S4 is deleted, If the row weight corresponding to the second candidate position is less than the minimum row weight corresponding to the updated second position set S2, the PC position is a second position in the updated fourth position set S4, the second position being the position with the lowest sequence reliability in an updated fifth position set S5, the updated fifth position set S5 comprising a position set in the updated fourth position set S4 with a row weight equal to the minimum row weight corresponding to the updated second position set S2, the updated fourth position set S4 being a position set corresponding to the fourth position set S4 after the PC position in the fourth position set S4 is deleted, ​ If the row weight corresponding to the second candidate position is greater than or equal to the minimum row weight corresponding to the updated second position set S2, a position with the lowest sequence reliability in the updated fourth position set S4 is taken as the PC position.

8. The method of any one of claims 1-7, wherein, The n PC PC positions are n PC bit positions with the lowest sequence reliability in the first position set S1. or, The n PC PC positions are the positions with the lowest sequence reliability and the smallest row weight in the second position set S2 a position in the first position set S1 and a position in the position set S1 excluding the second position set S2 in which the sequence reliability is the lowest one bit position.

9. The method according to any one of claims 1 to 8, characterized in that, The A information bits are located at positions other than the n PC bit positions in the first position set S1.

10. A decoding method, comprising: The method comprises: receiving a symbol sequence; performing a Chase Combining List, CA-SCL, algorithm decoding on the symbol sequence based on a cyclic redundancy check, CRC, to determine a first path; determining a first sequence according to the first path, the first sequence comprising N bits, the N bits comprising A information bits and n PC PC bits, the A information bits and the n PC PC bits being located at (A+n PC ) positions with highest sequence reliability in the first sequence, wherein the N is 2 raised to the power of n, and n is a positive integer, wherein, A PC bit is located in the sequence reliability lowest first position set S1 a bit position, A PC bit is located in the second set S2 of rows with the smallest weight and the lowest sequence reliability a first position set S1 is a position set of the A+n PC ) bit positions in the first sequence, a second position set S2 is a position set of A bit positions with the highest sequence reliability in the first sequence, and the for an integer greater than or equal to 0; determining A information bits according to the first sequence.

11. The method of claim 10, wherein, The n PC PC positions are n PC bit positions with the lowest sequence reliability in the first position set S1. or, The n PC PC positions are the positions in the second position set S2 with the lowest sequence reliability and the smallest row weight a position in the first position set S1 and a position in the position set S1 excluding the second position set S2 one bit position.

12. The method according to claim 10 or 11, characterized in that, The A information bits are located at positions other than the n PC bit positions in the first position set S1.

13. A communications device, characterized by comprising a communication interface and a circuit, The communication interface is configured to obtain A information bits and a number n of parity check PC bits PC and input the A information bits and the number n of PC bits PC to the circuit. the circuit is configured to enable the method of any one of claims 1-9 to be implemented.

14. A communications device, characterized by comprising a communication interface and a circuit, the communication interface is configured to receive a symbol sequence and input the symbol sequence to the circuit; the circuit is configured to enable the method of any one of claims 10-12 to be implemented.

15. A communications device, characterized by comprising: a processor coupled to a memory, the processor configured to execute a computer program or instructions stored in the memory to enable the method of any one of claims 1-12 to be implemented.

16. A computer-readable storage medium, characterized in that, The computer readable storage medium has stored therein computer instructions which, when executed on a computer, enable the method of any one of claims 1-12 to be implemented.

17. A computer program product, characterised in that, The computer program product comprises computer program code or instructions which, when executed on a computer, enable the method of any one of claims 1-12 to be implemented.

18. A communication system, characterized by The communication system comprises an encoding device and a decoding device, the encoding device is configured to perform the method of any one of claims 1-9; the decoding device is configured to perform the method of any one of claims 10-12.

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