Data verification method and apparatus, and chip

Abstract

Embodiments of the present application provide a data verification method and apparatus, and a chip. The data verification method comprises: acquiring a computation result outputted by a computing core; verifying the computation result on the basis of a first task, and obtaining a first verification result; verifying the computation result on the basis of a second task, and obtaining a second verification result, the first task being the latest computation task of the computing core, and the second task being a previous computation task before the first task; and determining the validity of the computation result on the basis of the first verification result and the second verification result. According to the technical solutions of the embodiments of the present application, it is possible to avoid misjudgment caused by an incorrect correspondence relationship between a computing task and a computing result during a computing task update stage, thereby avoiding computing power loss and improving the accuracy of verification while ensuring that the computing core can continue computing.

Description

Data verification method, device and chip

[0001] The present application claims priority to the Chinese patent application No. 2024107215281, filed on June 4, 2024, and entitled "Data verification method, device and chip", the whole content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the chip technical field, and particularly relates to a data verification method, device and chip. BACKGROUND

[0003] In the related art, after the computing core of the chip completes the calculation of the task and outputs the calculation result, the verification module verifies the calculation result with the task to ensure the validity of the calculation result. However, there is a delay in the data path of the task issued to each computing core. When the chip issues a new task, if the computing core is outputting the calculation result of the previous task, it will be judged that the calculation result does not match the current new task. At this time, the valid calculation result may be misjudged as an error, resulting in a loss of computing power. SUMMARY

[0004] The embodiments of the present application provide a data verification method, device and chip to solve the problems in the related art, and the technical solutions are as follows:

[0005] In the first aspect, the embodiments of the present application provide a data verification method, comprising: obtaining a calculation result output by a computing core; verifying the calculation result based on a first task to obtain a first verification result; verifying the calculation result based on a second task to obtain a second verification result; the first task is the latest calculation task of the computing core, and the second task is the previous calculation task of the first task; and determining the validity of the calculation result based on the first verification result and the second verification result.

[0006] In one implementation, determining the validity of the calculation result based on the first verification result and the second verification result comprises: in the case that the first verification result is that the first task matches the calculation result and the second verification result is that the second task does not match the calculation result, determining that the calculation result is valid.

[0007] In one implementation, determining the validity of the calculation result based on the first verification result and the second verification result comprises: in the case that the first verification result is that the first task does not match the calculation result and the second verification result is that the second task matches the calculation result, determining that the calculation result is valid.

[0008] In an embodiment, the validity of the calculation result is determined based on the first check result and the second check result, including: in the case that the first check result indicates that the first task does not match the calculation result and the second check result indicates that the second task does not match the calculation result, it is determined that the calculation result is invalid.

[0009] In an embodiment, the validity of the calculation result is determined based on the first check result and the second check result, including: first, the calculation result is checked based on the first task; in the case that the first check result indicates that the first task matches the calculation result, it is directly determined that the calculation result is valid; if not, the calculation result is checked based on the second task; in the case that the second check result indicates that the second task matches the calculation result, it is directly determined that the calculation result is valid; if not, it is determined that the calculation result is invalid.

[0010] In an embodiment, the validity of the calculation result is determined based on the first check result and the second check result, including: first, the calculation result is checked based on the second task; in the case that the second check result indicates that the second task matches the calculation result, it is directly determined that the calculation result is valid; if not, the calculation result is checked based on the first task; in the case that the first check result indicates that the first task matches the calculation result, it is directly determined that the calculation result is valid; if not, it is determined that the calculation result is invalid.

[0011] In an embodiment, the data checking method further includes: checking the calculation result based on a third task to obtain a third check result; the third task is a previous calculation task of the second task; and the validity of the calculation result is determined based on the first check result, the second check result and the third check result.

[0012] In an embodiment, the data checking method further includes: in the case that the calculation result is determined to be valid, the calculation result and the calculation task matching the calculation result are packaged and submitted.

[0013] In an embodiment, the data checking method further includes: in the case that the latest calculation task is updated, the latest calculation task is recorded as the first task and a previous calculation task of the latest calculation task is recorded as the second task, and the first task and / or the second task are stored.

[0014] In a second aspect, an embodiment of the present application provides a data checking device, including: a checking module configured to obtain a calculation result output by a calculation core, check the calculation result based on a first task to obtain a first check result, and check the calculation result based on a second task to obtain a second check result; the first task is a latest calculation task of the calculation core, and the second task is a previous calculation task of the first task; and an effectiveness determination module configured to determine the validity of the calculation result based on the first check result and the second check result.

[0015] In an implementation, the checking module includes a first checking module and a second checking module; the first checking module checks the calculation result based on a first task to obtain a first checking result; and the second checking module checks the calculation result based on a second task to obtain a second checking result.

[0016] In an implementation, the validity determining module includes a multiplexer including a first input end, a second input end and an output end, the first input end being configured to input the first checking result, the second input end being configured to input the second checking result, and the output end being configured to output a validity result of the calculation result.

[0017] In an implementation, the checking module is further configured to check the calculation result based on a third task to obtain a third checking result, the third task being a previous calculation task of the second task; and the validity determining module is further configured to determine the validity of the calculation result based on the first checking result, the second checking result and the third checking result.

[0018] In an implementation, the data checking device further includes a packing module configured to pack and submit the calculation result and the calculation task matched with the calculation result in a case where the calculation result is determined to be valid.

[0019] In an implementation, the data checking device further includes a buffer connected to the checking module and configured to store the first task and / or the second task.

[0020] In an implementation, the data checking device further includes a pre-calculation module including a pre-calculation input end and a pre-calculation output end, the pre-calculation input end being configured to receive the first task, and the pre-calculation output end being connected to the calculation core and configured to output pre-calculation data.

[0021] In a third aspect, an embodiment of the present application provides a chip for implementing the method according to any of the embodiments of the first aspect of the present application.

[0022] The technical solution described above can effectively avoid misjudgment due to the error of the correspondence between the calculation task and the calculation result in the calculation task updating phase, thereby avoiding the loss of computing power and improving the accuracy of the checking while ensuring that the calculation core can continue to calculate.

[0023] The above summary is only for the purpose of the description and is not intended to limit in any way. In addition to the illustrative aspects, embodiments and features described above, further aspects, embodiments and features of the present application will be readily apparent to those skilled in the art by reference to the drawings and the following detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0024] In the drawings, like reference numerals refer to like elements throughout the various figures. The drawings are not necessarily to scale, the emphasis instead being placed upon illustrating principles of the application. It should be understood that the drawings are merely depictions of some embodiments of the application and that they should not be construed as limiting the scope of the application.

[0025] FIG. 1 shows a data verification schematic diagram of a chip in an embodiment of the related art.

[0026] FIG. 2 shows a data verification schematic diagram of a chip in another embodiment of the related art.

[0027] FIG. 3 shows a flowchart of a data verification method of a chip according to an embodiment of the application.

[0028] FIG. 4 shows an architectural schematic diagram of a data verification apparatus of a chip according to an embodiment of the application.

[0029] FIG. 5 shows a data verification schematic diagram of a data verification apparatus of a chip according to an embodiment of the application.

[0030] FIG. 6 shows a data verification schematic diagram of a data verification apparatus of a chip according to another embodiment of the application.

[0031] Reference signs: 400: data verification apparatus; 410: verification module; 411: first verification module; 412: second verification module; 430: validity determination module; 431: multiplexer; 440: packing module; 450: buffer; 460: pre-computation module; 470: computation core. DETAILED DESCRIPTION

[0032] In the following, only some exemplary embodiments are briefly described. As will be obvious to those skilled in the art, the embodiments described can be modified in various different manners and can be carried out in various different ways without departing from the spirit or the scope of the application. Therefore, the drawings and descriptions should be considered in a sense of illustration rather than in a limiting sense.

[0033] The following terms are used herein

[0034] Computing power: refers to the computing ability of a high-performance computing chip to achieve the output of a target result by processing information data (i.e., a task).

[0035] Computation core: refers to a basic computing unit within a high-performance computing chip to complete a certain specific computation.

[0036] Verification module: an internal module of a high-performance computing chip to complete verification with an initial task before the output of a target result.

[0037] The check error rate is a calculation error rate of the calculation core detected by the check module, that is, a ratio of the number of error calculation outputs in a period to the number of all calculation outputs in the period.

[0038] In the related art, the computing power and the correctness rate are important indicators for measuring the performance of a high-performance computing chip. In order to improve the computing power, a multi-core calculation array in the chip usually transmits and processes the same group of tasks in the form of multicasting or broadcasting. After the calculation core completes the calculation of the task and outputs the calculation result, the check module checks the calculation result and the task. The check can be that the check module recalculates the task to output a check result, and compares whether the check result and the calculation result are consistent, so as to ensure the validity of the calculation result. In the chip with multiple calculation cores, in order to improve the computing power, the update of the task is non-handshake and non-back pressure, that is, the update of the task does not need to wait for the response of the calculation core. Since there is a delay in the data path of the task when it is sent to each calculation core, when the chip receives a new task, if the calculation core is outputting the calculation result of the previous task, it will be judged that the calculation result does not match the current new task.

[0039] FIG. 1 shows a data check schematic diagram of an embodiment in the related art. As shown in FIG. 1, the chip uses a single check module. After the calculation core completes the calculation of task one and outputs the calculation result of task one, the check module is used to check the current task and the calculation result of task one. In the case where the chip does not receive a new task, the current task is task one, and the correspondence between the current task and the calculation result is correct. The check module can recalculate task one or obtain a check result by performing other verification calculation on task one. In the case where the check result of task one matches the calculation result of task one, the check passes.

[0040] FIG. 2 shows a data check schematic diagram of another embodiment in the related art. As shown in FIG. 2, in the case where the chip receives a new task, the current task is updated to task two, and at this time, the correspondence between the current task and the calculation result is incorrect. Because task two is different from task one, the calculation result of task two does not match the calculation result of task one, so the check will fail with a high probability. However, the calculation result corresponds to task one for calculation check, which is correct with a high probability, so the check can pass. At this time, if it is determined that the calculation result of task one is invalid according to task two, the computing power will be lost.

[0041] In view of the above problems, the following two solutions are usually used:

[0042] The first kind is to ignore the detection error result. Since the time interval of task update accounts for a small proportion in the total working time of the computing core, the probability of the computing core outputting the calculation result of the previous task in the task update interval is relatively small. This scheme does not consider the influence of misjudgment and directly discards all detection error results. However, in the case of discarding the effective calculation result as an error, direct computing power loss will be caused. Moreover, the increase of the verification error rate will also affect the subsequent work configuration, such as adjusting the voltage or working frequency of the computing core, but at this time the actual error rate of the computing core may be within the normal range and there is no need to adjust the working configuration. The wrong working configuration may thus cause indirect computing power loss.

[0043] The second kind is to suspend the calculation of the computing core in the new task update phase. This scheme can ensure that the computing core will not continue to calculate the previous task and will not output the calculation result of the previous task within the time interval from when the chip receives a new task to when the new task is loaded into the computing core. Although this scheme reduces the verification error rate, suspending the computing core will cause waste of calculation time, and the computing power of the computing core is zero during the suspension period.

[0044] The above task can be a neural network calculation task, a hash function calculation task, or a large model data calculation task. Those skilled in the art can select any information data requiring calculation and verification in the prior art and apply it to the technical scheme of the present application.

[0045] FIG. 3 shows a flowchart of a data verification method according to an embodiment of the present application. As shown in FIG. 3, the data verification method comprises:

[0046] Step S301: obtaining the calculation result output by the computing core;

[0047] Step S302: verifying the calculation result based on a first task to obtain a first verification result;

[0048] Step S303: verifying the calculation result based on a second task to obtain a second verification result; the first task is the latest calculation task of the computing core, and the second task is the previous calculation task of the first task;

[0049] Step S304: determining the validity of the calculation result based on the first verification result and the second verification result.

[0050] It should be noted that the present application does not limit the execution order of steps S302 and S303. For example, step S302 can be executed first and step S303 can be executed later; or step S303 can be executed first and step S302 can be executed later; of course, steps S302 and S303 can also be executed simultaneously.

[0051] Exemplarily, when the chip receives a latest computing task, i.e., a first task, the first task is sent to the computing core to make the computing core compute the first task. In a case that the computing core completes the computation of the first task and outputs a computation result of the first task, if the chip does not receive a new task, the current task is still the first task, the correspondence between the first task and the computation result is correct, and the correspondence between a previous task (i.e., a second task) of the first task and the computation result is incorrect. At this time, a first check result obtained by checking the computation result based on the first task is a target check result, and if the first check result is that the first task matches the computation result, it is determined that the computation result is valid. In a case that the computing core completes the computation of the first task and outputs the computation result of the first task, if the chip receives a new task, the latest computing task is updated, the latest computing task is recorded as the first task, and a previous computing task of the first task is recorded as the second task. At this time, the correspondence between the latest computing task (the first task) and the computation result is incorrect, and the correspondence between the previous task (i.e., the second task) of the latest computing task and the computation result is correct. At this time, a second check result obtained by checking the computation result based on the second task is the target check result, and if the second check result is that the second task matches the computation result, it is determined that the computation result is valid.

[0052] According to the data check method provided in the embodiments of the present application, a first check result can be obtained by checking the computation result based on the latest computing task, and a second check result can be obtained by checking the computation result based on a previous task of the latest computing task. In a case that the latest computing task is not updated, the correspondence between the latest computing task and the computation result is correct, and the first check result is the target check result. In a case that the latest computing task is updated, the correspondence between the previous task of the latest computing task and the computation result is correct, and the second check result is the target check result. The method can effectively avoid misjudgment due to incorrect correspondence between the computing task and the computation result in the computing task update stage, thereby avoiding loss of computing power and improving the accuracy of the check while ensuring that the computing core can continue to compute.

[0053] Optionally, in step S304, determining the validity of the computation result based on the first check result and the second check result can include: in a case that the first check result is that the first task matches the computation result and the second check result is that the second task does not match the computation result, determining that the computation result is valid.

[0054] Exemplarily, two check modules can be used to check the computation result based on the first task and the second task respectively. For example, the two check modules are a first check module and a second check module. The first check module checks the computation result based on the first task to obtain a first check result. The second check module checks the computation result based on the second task to obtain a second check result.

[0055] In the case of calculating the computing result of the first task by the computing core, if the chip does not receive a new task, the latest computing task is not updated. At this time, the correspondence between the first task and the computing result is correct, the correspondence between the previous task (i.e., the second task) of the first task and the computing result is incorrect, the second verification module verifies the computing result based on the second task, and the obtained second verification result is that the second task does not match the computing result. At this time, the first verification module verifies the computing result based on the first task, and the obtained first verification result is the target verification result. If the first verification result is that the first task matches the computing result, it is determined that the computing result is valid. Further, if the first verification result is that the first task does not match the computing result, it is determined that the computing result is invalid.

[0056] In the embodiment, in the case that the chip does not receive a new task, i.e., the latest computing task is not updated, the correspondence between the current task and the computing result is correct, and the first verification result is a valid target verification result. In the case that the current task matches the computing result, the verification can pass, so that the validity of the computing result can be accurately determined, and important guarantee for real-time task processing and result verification is provided. Moreover, through the verification of the first task and the second task, the result confusion or incorrect judgment caused by the updating of the computing task can be avoided, so that the verification error rate of the chip can be reduced, and the stability and reliability of the system can be effectively improved.

[0057] Optionally, in step S304, determining the validity of the computing result based on the first verification result and the second verification result can include: in the case that the first verification result is that the first task does not match the computing result and the second verification result is that the second task matches the computing result, determining that the computing result is valid.

[0058] Exemplarily, two verification modules can be adopted to verify the computing result based on the first task and the second task respectively. For example, the two verification modules are a first verification module and a second verification module. The first verification module verifies the computing result based on the first task, and obtains a first verification result. The second verification module verifies the computing result based on the second task, and obtains a second verification result.

[0059] In the case of calculating the computing result of the core output for the first task, if the chip receives a new task, the latest computing task is updated, the updated latest computing task is recorded as the first task, and the previous computing task of the latest computing task is recorded as the second task. At this time, the correspondence between the latest computing task (the first task) and the computing result is wrong, the first verification module verifies the computing result based on the first task, and the first verification result obtained is that the first task does not match the computing result. The correspondence between the previous task (i.e., the second task) of the latest computing task and the computing result is correct. The second verification module verifies the computing result based on the second task, and the second verification result obtained is the target verification result. If the second verification result is that the second task matches the computing result, it is determined that the computing result is valid. Further, if the second verification result is that the second task does not match the computing result, it is determined that the computing result is invalid.

[0060] In the embodiments of the present application, in the case of updating the latest computing task, the correspondence between the previous task (i.e., the second task) of the latest computing task and the computing result is correct, and the second verification result is the valid target verification result. In the case where the second task matches the computing result, the verification can pass, thereby effectively improving the fault tolerance rate of verification and avoiding misjudgment due to the wrong correspondence between the task and the computing result in the verification process, and avoiding the loss of computing power.

[0061] Optionally, in step S304, determining the validity of the computing result based on the first verification result and the second verification result can include: in the case where the first verification result is that the first task does not match the computing result and the second verification result is that the second task does not match the computing result, determining that the computing result is invalid.

[0062] Exemplarily, the embodiments can also use two verification modules to verify the computing result based on the first task and the second task, respectively. For example, the two verification modules are the first verification module and the second verification module. The first verification module verifies the computing result based on the first task, and obtains the first verification result. The second verification module verifies the computing result based on the second task, and obtains the second verification result. The first verification result is that the first task does not match the computing result, and the second verification result is that the second task does not match the computing result, including the following two cases.

[0063] The first case is that the chip does not receive a new task, i.e., the latest computing task is not updated, in the case that the computing core outputs the computing result for the first task. At this time, the correspondence between the first task and the computing result is correct, the correspondence between the previous task (i.e., the second task) of the first task and the computing result is incorrect, the second verification module verifies the computing result based on the second task, and the obtained second verification result is that the second task does not match the computing result. The first verification module verifies the computing result based on the first task, and the obtained first verification result is the target verification result, and the first verification result is that the first task does not match the computing result. At this time, it can be determined that the computing result is invalid.

[0064] The second case is that the chip receives a new task, i.e., the latest computing task is updated, in the case that the computing core outputs the computing result for the first task. At this time, the correspondence between the latest computing task (i.e., the first task) and the computing result is incorrect, the first verification module verifies the computing result based on the first task, and the obtained first verification result is that the first task does not match the computing result. The previous task (i.e., the second task) of the latest computing task and the computing result are correct. The second verification module verifies the computing result based on the second task, and the obtained second verification result is the target verification result, and the second verification result is that the second task does not match the computing result. At this time, it can be determined that the computing result is invalid.

[0065] In the embodiment, the computing result can be determined to be invalid in the case that the first verification result is that the first task does not match the computing result, and the second verification result is that the second task does not match the computing result. Through the two verification manners, the possibility of error can be reduced, so that the accuracy and reliability of the output result can be more reliably guaranteed, and the efficiency and stability of data processing can be improved.

[0066] Optionally, in step S304, determining the validity of the computing result based on the first verification result and the second verification result can include: first verifying the computing result based on the first task; in the case that the first verification result is that the first task matches the computing result, directly determining that the computing result is valid; if not, verifying the computing result based on the second task; in the case that the second verification result is that the second task matches the computing result, directly determining that the computing result is valid; if not, determining that the computing result is invalid.

[0067] Exemplarily, a checking module can perform checking in sequence, i.e., the checking module first checks the calculation result based on the first task and obtains a first checking result. In a case where the first checking result is that the first task matches the calculation result, it is directly determined that the calculation result is valid, and the checking module does not need to check the calculation result based on the second task. In a case where the first checking result is that the first task does not match the calculation result, the checking module checks the calculation result based on the second task and obtains a second checking result. In a case where the second checking result is that the second task matches the calculation result, it is determined that the calculation result is valid; in a case where the second checking result is that the second task does not match the calculation result, it is determined that the calculation result is invalid.

[0068] In one example, in a case where the calculation core outputs the calculation result for the first task, the chip does not receive a new task, i.e., the latest calculation task is not updated. At this time, the correspondence between the first task and the calculation result is correct, and the correspondence between the second task and the calculation result is incorrect. The checking module first checks the calculation result based on the first task and obtains a first checking result. In a case where the first checking result is that the first task matches the calculation result, it is directly determined that the calculation result is valid, and the checking module does not need to check the calculation result based on the second task. In a case where the first checking result is that the first task does not match the calculation result, the checking module checks the calculation result based on the second task, and since the correspondence between the second task and the calculation result is incorrect, the second checking result is that the second task does not match the calculation result. Therefore, the first checking result is that the first task does not match the calculation result, and the second checking result is that the second task does not match the calculation result, and it can be determined that the calculation result is invalid.

[0069] In another example, in a case where the calculation core outputs the calculation result for the first task, the chip receives a new task, i.e., the latest calculation task is updated, and the updated latest calculation task is recorded as the first task, and the previous calculation task of the latest calculation task is recorded as the second task. At this time, the correspondence between the first task and the calculation result is incorrect, and the correspondence between the second task and the calculation result is correct. The checking module first checks the calculation result based on the first task and obtains a first checking result. Since the correspondence between the first task and the calculation result is incorrect, the first checking result is that the first task does not match the calculation result. Then the checking module checks the calculation result based on the second task, and if the second checking result is that the second task matches the calculation result, it is determined that the calculation result is valid; if the second checking result is that the second task does not match the calculation result, it is determined that the calculation result is invalid.

[0070] In this embodiment, only one verification module is used for verification. If the first verification result is that the first task matches the calculation result, the calculation result is directly determined to be valid, and the calculation result does not need to be verified based on the second task additionally, the validity of the calculation result can be determined more quickly, and the efficiency of data processing is improved. In addition, if the first verification result is that the first task does not match the calculation result, the calculation result can be verified based on the second task, so that the fault tolerance of verification can be enhanced, and the risk of misjudgment can be avoided.

[0071] Optionally, in step S304, determining the validity of the calculation result based on the first verification result and the second verification result can include: first verifying the calculation result based on the second task; in the case that the second verification result is that the second task matches the calculation result, directly determining that the calculation result is valid; if not, verifying the calculation result based on the first task; in the case that the first verification result is that the first task matches the calculation result, directly determining that the calculation result is valid; if not, determining that the calculation result is invalid.

[0072] Exemplarily, one verification module can be used to verify in sequence, that is, the verification module first verifies the calculation result based on the second task, and obtains the second verification result. In the case that the second verification result is that the second task matches the calculation result, the verification module does not need to verify the calculation result based on the first task. In the case that the second verification result is that the second task does not match the calculation result, the verification module verifies the calculation result based on the first task again, and obtains the first verification result. In the case that the first verification result is that the first task matches the calculation result, it is determined that the calculation result is valid; in the case that the first verification result is that the first task does not match the calculation result, it is determined that the calculation result is invalid.

[0073] In one example, in the case that the calculation core outputs the calculation result of the first task, the chip does not receive a new task, that is, the latest calculation task is not updated. At this time, the correspondence between the first task and the calculation result is correct, and the correspondence between the second task and the calculation result is incorrect. The verification module first verifies the calculation result based on the second task. Since the correspondence between the second task and the calculation result is incorrect, the second verification result is that the second task does not match the calculation result. Then the verification module verifies the calculation result based on the first task. If the first verification result is that the first task matches the calculation result, it is determined that the calculation result is valid; if the first verification result is that the first task does not match the calculation result, it is determined that the calculation result is invalid.

[0074] In another example, in a case where the computing core outputs a computing result of a first task, the chip receives a new task, i.e., a latest computing task update, the updated latest computing task is recorded as the first task, and a previous computing task of the latest computing task is recorded as a second task. At this time, the first task is incorrectly corresponding to the computing result, and the second task is correctly corresponding to the computing result. The verification module first verifies the computing result based on the second task to obtain a second verification result. In a case where the second verification result is that the second task matches the computing result, it is directly determined that the computing result is valid, and the verification module does not need to verify the computing result based on the first task. In a case where the second verification result is that the second task does not match the computing result, the verification module verifies the computing result based on the first task. Since the first task is incorrectly corresponding to the computing result, the first verification result is that the first task does not match the computing result. Therefore, the first verification result is that the first task does not match the computing result, and the second verification result is that the second task does not match the computing result, and it can be determined that the computing result is invalid.

[0075] In this embodiment, only one verification module is needed for verification. If the second verification result is that the second task matches the computing result, it can be directly determined that the computing result is valid, and the computing result does not need to be verified based on the first task additionally, the validity of the computing result can be determined more quickly, and the efficiency of data processing is improved. In addition, in a case where the second verification result is that the second task does not match the computing result, the computing result can be verified based on the first task, so that the fault tolerance of verification can be enhanced, and the risk of misjudgment can be avoided.

[0076] Optionally, the data verification method can further include: pre-computing a computing task, and correspondingly obtaining a pre-computing result, computing the pre-computing result, and correspondingly obtaining a computing result.

[0077] When computing information data such as a neural network computing task, a hash function computing task, and a large model data computing task, it can be necessary to uniformly pre-compute an initial task, and then synchronously send a pre-computing result to multiple computing cores for parallel computing. The pre-computing module plays a role of pre-computing and pre-processing data.

[0078] Optionally, the data verification method can further include: verifying the computing result based on a third task to obtain a third verification result, the third task being a previous computing task of the second task; and determining the validity of the computing result based on the first verification result, the second verification result, and the third verification result.

[0079] In one example, three verification modules can be employed to verify the calculation result based on the first task, the second task and the third task respectively. For example, the three verification modules are a first verification module, a second verification module and a third verification module. The first verification module verifies the calculation result based on the first task to obtain a first verification result. The second verification module verifies the calculation result based on the second task to obtain a second verification result. The third verification module verifies the calculation result based on the third task to obtain a third verification result. If the first verification result is that the first task matches the calculation result, the second verification result is that the second task does not match the calculation result, and the third verification result is that the third task does not match the calculation result, it is determined that the calculation result is valid. If the first verification result is that the first task does not match the calculation result, the second verification result is that the second task matches the calculation result, and the third verification result is that the third task does not match the calculation result, it is determined that the calculation result is valid. If the first verification result is that the first task does not match the calculation result, the second verification result is that the second task does not match the calculation result, and the third verification result is that the third task matches the calculation result, it is determined that the calculation result is valid. If the first verification result is that the first task does not match the calculation result, the second verification result is that the second task does not match the calculation result, and the third verification result is that the third task does not match the calculation result, it is determined that the calculation result is invalid.

[0080] In another example, one verification module can be employed to verify in sequence. For example, the verification module can first verify the calculation result based on the first task to obtain a first verification result. In a case where the first verification result is that the first task matches the calculation result, it is directly determined that the calculation result is valid, and the verification module does not need to verify the calculation result based on the second task and the third task. In a case where the first verification result is that the first task does not match the calculation result, the verification module verifies the calculation result based on the second task to obtain a second verification result. In a case where the second verification result is that the second task matches the calculation result, it is directly determined that the calculation result is valid, and the verification module does not need to verify the calculation result based on the third task. In a case where the second verification result is that the second task does not match the calculation result, the verification module verifies the calculation result based on the third task to obtain a third verification result. In a case where the third verification result is that the third task matches the calculation result, it is determined that the calculation result is valid. In a case where the third verification result is that the third task does not match the calculation result, it is determined that the calculation result is invalid.

[0081] In the above examples, the verification modules are taken as an example to verify in the order of the first task, the second task and the third task. It can be understood by those skilled in the art that the verification modules can verify in any order, for example, in the order of the first task, the third task and the second task, the order of the second task, the first task and the third task, etc. The verification order of the calculation tasks is not limited in the present application.

[0082] The embodiments of the present application take three computing tasks, i.e., a first task, a second task and a third task, as an example for illustration. Optionally, the first task is pre-calculated in the pre-calculation module, the second task is calculated in the calculation core, and the third task is verified in the verification module. Those skilled in the art can understand that the scheme can be applied to technical solutions of other numbers of computing tasks after reading the technical solutions of the present application, for example, the fourth task, the fifth task, the sixth task, etc. can also be included, which also falls within the protection scope of the present application. Of course, in another case, the pre-calculation module can pre-calculate one or more computing tasks at the same time, the calculation core can calculate one or more computing tasks, the verification module can verify one or more computing tasks, and the verification module 410 can verify multiple computing tasks.

[0083] In the embodiments, the validity of the calculation result is determined based on the first verification result, the second verification result and the third verification result, which can further avoid misjudgment due to the incorrect correspondence between the computing task and the calculation result in the computing task updating stage, so as to avoid the loss of computing power and further improve the accuracy of verification while ensuring that the calculation core can continue to calculate.

[0084] Optionally, the data verification method can further include: in the case where the calculation result is determined to be valid, the calculation result and the computing task matched with the calculation result are packaged and submitted.

[0085] Exemplarily, in the case where the first verification result is that the first task is matched with the calculation result and the second verification result is that the second task is not matched with the calculation result, the calculation result is packaged and submitted with the first task; in the case where the first verification result is that the first task is not matched with the calculation result and the second verification result is that the second task is matched with the calculation result, the calculation result is packaged and submitted with the second task. The packaged calculation result and task can be submitted to other modules to realize corresponding functions. For example, in the case where the chip is an artificial intelligence (AI) chip, the packaged calculation result and task can be submitted to a central processing unit (CPU) to perform next step calculation and the like; in the case where the chip is a computing power chip, the packaged calculation result and task can be submitted to a host.

[0086] Optionally, the data verification method can further include: recording the latest computing task as the first task and recording the previous computing task of the latest computing task as the second task when the latest computing task is updated, and storing the first task and / or the second task.

[0087] Exemplarily, in a case where the computing core outputs a calculation result, if the chip receives a new task, the latest calculation task is updated, at this time, the latest calculation task is recorded as a first task, and a previous calculation task of the first task is recorded as a second task. At this time, the second task can be sent to the buffer, so that the second task is temporarily stored in the buffer. The first task is incorrectly corresponding to the calculation result, and the first task does not match the calculation result. The second task is correctly corresponding to the calculation result, and if the second task matches the calculation result, it is determined that the calculation result is valid. In a case where the first task is completely sent to the computing core, and the computing core can calculate the first task and output a calculation result of the first task, the first task is correctly corresponding to the calculation result, and in a case where the first task matches the calculation result, it is determined that the calculation result is valid.

[0088] Therefore, the first task and / or the second task can be stored, and compared with the related art, the calculation result can be verified based on the first task and the second task, so that the computing power loss in the calculation task updating stage is avoided, and the accuracy of verification is effectively ensured.

[0089] Optionally, the data verification method can further include: after the calculation result of the second task is completely verified, the second task is cleared. In this way, the calculation task that has been verified can be cleared in time, so that the memory occupation can be reduced, and the memory space can be released.

[0090] In the embodiment, since the proportion of the time interval of task updating in the total working time of the computing core is very small, the probability that the computing core outputs the calculation result of the previous task in the task updating interval is relatively small. At this time, if the first task is updated for a period of time, and the calculation result of the verification is completely irrelevant to the second task, the second task can be cleared, and only the verification of the first task is performed. In this way, while ensuring the accuracy of verification, the consumption of calculation verification is saved.

[0091] The data verification apparatus 400 according to the second aspect of the present application will be described below in combination with FIGS. 4-6.

[0092] FIG. 4 shows an architecture schematic diagram of the data verification apparatus 400 according to an embodiment of the present application. As shown in FIG. 4, the data verification apparatus 400 includes a verification module 410 and a validity determination module 430.

[0093] Specifically, the verification module 410 is configured to obtain a calculation result output by a computing core, verify the calculation result based on a first task to obtain a first verification result, and verify the calculation result based on a second task to obtain a second verification result; the first task is a latest calculation task of the computing core, and the second task is a previous calculation task of the first task. The validity determination module 430 is configured to determine validity of the calculation result based on the first verification result and the second verification result.

[0094] Exemplarily, when the chip receives a latest computing task, i.e., a first task, the first task is sent to the computing core to make the computing core compute the first task. In a case that the computing core completes the computation of the first task and outputs a computation result of the first task, if the chip does not receive a new task, the current task is still the first task, the correspondence between the first task and the computation result is correct, and the correspondence between a previous task (i.e., a second task) of the first task and the computation result is incorrect. At this time, the first check result obtained by the check module 410 is the target check result. If the first check result is that the first task matches the computation result, it is determined that the computation result is valid. If the first check result is that the first task does not match the computation result, it is determined that the computation result is invalid. In a case that the computing core completes the computation of the first task and outputs the computation result of the first task, if the chip receives a new task, the latest computing task is updated, the latest computing task is recorded as the first task, and a previous computing task of the first task is recorded as the second task. At this time, the correspondence between the latest computing task (the first task) and the computation result is incorrect, and the correspondence between the previous task (i.e., the second task) of the latest computing task and the computation result is correct. At this time, the second check result obtained by the check module 410 is the target check result. If the second check result is that the second task matches the computation result, it is determined that the computation result is valid. If the second check result is that the second task does not match the computation result, the computation result is invalid.

[0095] According to the data check device 400 provided in the embodiments of the present application, compared with the related art, in a case that any one of the first check result and the second check result obtained by the check module 410 passes, it is determined that the computation result is valid, and only in a case that neither the first check result nor the second check result obtained by the check module 410 passes, it is determined that the computation result is invalid, which can effectively avoid misjudgment due to incorrect correspondence between the computing task and the computation result in the computing task update stage, thereby effectively improving the accuracy of the check.

[0096] Optionally, the check module 410 can include a first check module and a second check module. The first check module checks the computation result based on the first task to obtain a first check result. The second check module checks the computation result based on the second task to obtain a second check result. In this way, the data processing efficiency can be improved.

[0097] FIG. 5 shows a data check schematic diagram of a data check device according to an embodiment of the present application, and FIG. 6 shows a data check schematic diagram of a data check device according to another embodiment of the present application. Optionally, referring to FIG. 5 and FIG. 6, the validity determination module 430 includes a multiplexer 431, the multiplexer 431 includes a first input end, a second input end and an output end, the first input end is used to input the first check result, the second input end is used to input the second check result, and the output end is used to output a validity result of the computation result.

[0098] Exemplarily, when the chip receives the first task, the first task is sent to the computing core 470 to make the computing core 470 perform computation on the first task. In the case that the computing core 470 completes the computation on the first task and outputs the first computation result of the first task, if the chip does not receive a new task, i.e., the latest computation task is not updated, the latest computation task is still the first task. At this time, the second check result obtained by the second check module 412 is that the second task does not match the first computation result (as shown by the dashed line in FIG. 5). In the case that the first check result obtained by the first check module 411 is that the first task matches the first computation result, it is determined that the computation result is valid. If the latest computation task is updated, the latest computation task is recorded as the first task, and the previous computation task of the latest computation task is recorded as the second task. At this time, the first check result obtained by the first check module 411 is that the first task does not match the first computation result (as shown by the dashed line in FIG. 6). In the case that the second check result obtained by the second check module 412 is that the second task matches the first computation result, it is determined that the computation result is valid.

[0099] Therefore, by setting the multiplexer 431, in the case that either the first check result obtained by the first check module 411 or the second check result obtained by the second check module 412 is passed, the output end of the multiplexer 431 can output the validity result that the computation result is valid, effectively solving the problem of loss of computing power and decrease of accuracy caused by the single check module receiving the computation result that does not match the current new task in the related art.

[0100] Optionally, the check module 410 is further configured to check the computation result based on a third task to obtain a third check result, the third task being a previous computation task of the second task; and the validity determination module 430 is further configured to determine the validity of the computation result based on the first check result, the second check result and the third check result.

[0101] In one example, the checking module 410 can include a first checking module, a second checking module and a third checking module. The first checking module checks the calculation result based on the first task to obtain a first checking result. The second checking module checks the calculation result based on the second task to obtain a second checking result. The third checking module checks the calculation result based on the third task to obtain a third checking result. If the first checking result is that the first task matches the calculation result, the second checking result is that the second task does not match the calculation result, and the third checking result is that the third task does not match the calculation result, it is determined that the calculation result is valid. If the first checking result is that the first task does not match the calculation result, the second checking result is that the second task matches the calculation result, and the third checking result is that the third task does not match the calculation result, it is determined that the calculation result is valid. If the first checking result is that the first task does not match the calculation result, the second checking result is that the second task does not match the calculation result, and the third checking result is that the third task matches the calculation result, it is determined that the calculation result is valid. If the first checking result is that the first task does not match the calculation result, the second checking result is that the second task does not match the calculation result, and the third checking result is that the third task does not match the calculation result, it is determined that the calculation result is invalid.

[0102] In another example, one checking module 410 can be used to perform the checking in sequence. For example, the checking module 410 can first check the calculation result based on the first task to obtain a first checking result. If the first checking result is that the first task matches the calculation result, it is directly determined that the calculation result is valid, and the checking module 410 does not need to check the calculation result based on the second task and the third task. If the first checking result is that the first task does not match the calculation result, the checking module 410 checks the calculation result based on the second task to obtain a second checking result. If the second checking result is that the second task matches the calculation result, it is directly determined that the calculation result is valid, and the checking module 410 does not need to check the calculation result based on the third task. If the second checking result is that the second task does not match the calculation result, the checking module 410 checks the calculation result based on the third task to obtain a third checking result. If the third checking result is that the third task matches the calculation result, it is determined that the calculation result is valid. If the third checking result is that the third task does not match the calculation result, it is determined that the calculation result is invalid.

[0103] In the above examples, the checking module 410 is taken as an example to perform the checking in the order of the first task, the second task and the third task. Those skilled in the art can understand that the checking module can perform the checking in any order, for example, in the order of the first task, the third task and the second task, the order of the second task, the first task and the third task, etc. The checking order of the calculation task is not limited in the present application.

[0104] The embodiments of the present application take three computing tasks, i.e., the first task, the second task and the third task, as an example for illustration. Those skilled in the art can understand that the scheme can be applied to technical solutions of other numbers of computing tasks after reading the technical solutions of the present application, for example, the fourth task, the fifth task, the sixth task, etc. This also falls within the protection scope of the present application.

[0105] In the embodiment, the validity of the computing result is determined based on the first check result, the second check result and the third check result, which can further avoid misjudgment due to the error of the correspondence between the computing task and the computing result in the computing task updating stage, so as to avoid the loss of computing power and further improve the accuracy of the check while ensuring that the computing core can continue to compute.

[0106] Optionally, as shown in FIGS. 5 and 6, the data check device 400 further includes a packaging module 440 configured to package and submit the computing result and the computing task matched with the computing result in the case that the computing result is determined to be valid. The packaged computing result and computing task can be submitted to a subsequent module to realize corresponding functions. For example, in the case that the chip is an artificial intelligence chip, the packaged computing result and computing task can be submitted to a central processing unit to perform the next step of computing and the like; in the case that the chip is a computing power chip, the packaged computing result and computing task can be submitted to a host.

[0107] Optionally, in combination with FIGS. 5 and 6, the data check device 400 further includes a buffer 450 connected to the check module 410 and configured to store the first task and / or the second task. Thus, the first task and / or the second task can be temporarily stored in the buffer 450, and compared with the related art, the computing result can be checked based on the first task and the second task, so as to avoid the loss of computing power in the task updating stage and effectively ensure the accuracy of the check.

[0108] Optionally, as shown in FIGS. 5 and 6, the data check device 400 further includes a pre-computing module 460 including a pre-computing input end and a pre-computing output end. The pre-computing input end is configured to receive the first task, and the pre-computing output end is connected to the computing core 470 and configured to output pre-computing data.

[0109] Exemplarily, as shown in FIG. 5, when the chip receives the first task, the pre-computation module 460 first pre-computes the first task and outputs first pre-computation data. The computing core 470 is configured to compute the first pre-computation data and output a first computation result. If the chip does not receive a new computation task, the latest computation task is still the first task, at this time, only one group of computation tasks (i.e., the first task) in the chip is processed, the correspondence between the first task and the first computation result is correct, the correspondence between the previous task of the first task and the first computation result is incorrect, and the multiplexer 431 outputs a first check result. As shown in FIG. 6, if the chip receives a new task, the latest computation task is updated, the latest computation task is recorded as the first task, and the previous computation task of the first task is recorded as the second task. At this time, the pre-computation module 460 pre-computes the first task and outputs second pre-computation data, the computing core 470 outputs a first computation result of the second task, and there are at least two groups of tasks (i.e., the first task and the second task) in the chip being processed. The correspondence between the first task and the first computation result is incorrect, the correspondence between the second task and the first computation result is correct, and the multiplexer 431 outputs a second check result.

[0110] Therefore, by setting the pre-computation module 460, the latest computation task can be pre-computed, so that the pre-computation data is output to the computing core 470, and the computing core 470 can compute the pre-computation data and further output the final computation result of the task.

[0111] According to the third aspect of the embodiments of the present application, the chip is used to implement the data check method of the chip of any of the first aspect of the present application.

[0112] According to the chip of the embodiments of the present application, the misjudgment caused by the incorrect correspondence between the computation task and the computation result in the case of updating the computation task can be effectively avoided, so that the overall computing power and fault tolerance of the chip can be improved while ensuring that the computing core can continue to compute.

[0113] In the above embodiments, all or part of the embodiments can be implemented by software, hardware, firmware or any combination thereof. When implemented by software, all or part of the embodiments can be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on the computer, all or part of the processes or functions according to the present application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network or other programmable device. The computer instructions can be stored in a computer readable storage medium or transferred from one computer readable storage medium to another computer readable storage medium.

[0114] In the description of the application, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the application. Moreover, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in one or more embodiments or examples. In addition, different embodiments or examples described in the specification and characteristics of different embodiments or examples can be combined and combined by those skilled in the art without contradiction.

[0115] In addition, the terms "first", "second" are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include at least one of the features. In the description of the application, the meaning of "multiple" is two or more, unless otherwise specifically limited.

[0116] Any process or method descriptions in flow charts or described elsewhere herein can be understood as representing code modules, segments, or portions of code that include one or more executable instructions for implementing specific logic functions or steps in the process. And the scope of preferred embodiments of the present application includes additional implementation in which the functions are performed in different orders, in substantially simultaneous fashion, or in reverse order.

[0117] The logic and / or steps represented in flow charts or otherwise described herein, for example, can be considered as a sequence of executable instructions, which can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor- based system, or other system that can fetch instructions from a instruction execution system, apparatus, or device and execute the instructions, or in conjunction with which the instructions may be executed.

[0118] It should be understood that parts of the present application can be realized in hardware, software, firmware or a combination thereof. In the above-described embodiments, a plurality of steps or methods can be realized by software or firmware stored in a memory and executed by a suitable instruction execution system. All or part of the steps of the above-described embodiment method can be instructed by a program to complete the relevant hardware, and the program can be stored in a computer readable storage medium, and the program includes one or a combination of the steps of the method embodiment when executed.

[0119] In addition, each of the function units in each embodiment of the present application can be integrated in one processing module, or each unit can be physically present separately, or two or more units can be integrated in one module. The integrated module can be realized in the form of hardware or in the form of a software function module. When the integrated module is realized in the form of a software function module and sold or used as an independent product, it can also be stored in a computer readable storage medium. The storage medium can be a read-only memory, a magnetic disk or an optical disk, etc.

[0120] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited to this. Any person skilled in the art can easily think of various changes or replacements within the technical scope disclosed in the present application, and these should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A data checking method, characterized by, The method comprises: obtaining a calculation result output by a calculation core; verifying the calculation result based on a first task to obtain a first verification result; verifying the calculation result based on a second task to obtain a second verification result; the first task is a latest calculation task of the calculation core, and the second task is a previous calculation task of the first task; determining the validity of the calculation result based on the first verification result and the second verification result.

2. The method of claim 1, wherein, Determining the validity of the calculation result based on the first verification result and the second verification result comprises: in the case that the first verification result is that the first task matches the calculation result, and the second verification result is that the second task does not match the calculation result, determining that the calculation result is valid.

3. The method of claim 1, wherein, Determining the validity of the calculation result based on the first verification result and the second verification result comprises: in the case that the first verification result is that the first task does not match the calculation result, and the second verification result is that the second task matches the calculation result, determining that the calculation result is valid.

4. The method of claim 1, wherein, Determining the validity of the calculation result based on the first verification result and the second verification result comprises: in the case that the first verification result is that the first task does not match the calculation result, and the second verification result is that the second task does not match the calculation result, determining that the calculation result is invalid.

5. The method of claim 1, wherein, Determining the validity of the calculation result based on the first verification result and the second verification result comprises: first, verifying the calculation result based on the first task; in the case that the first verification result is that the first task matches the calculation result, directly determining that the calculation result is valid; if not, verifying the calculation result based on the second task; in the case that the second verification result is that the second task matches the calculation result, directly determining that the calculation result is valid; if not, determining that the calculation result is invalid.

6. The method of claim 1, wherein, Determining the validity of the calculation result based on the first verification result and the second verification result comprises: first, verifying the calculation result based on the second task; in the case that the second verification result is that the second task matches the calculation result, directly determining that the calculation result is valid; if not, verifying the calculation result based on the first task; in the case that the first verification result is that the first task matches the calculation result, directly determining that the calculation result is valid; if not, determining that the calculation result is invalid.

7. The method of claim 1, wherein, The method further comprises: verifying the calculation result based on a third task to obtain a third verification result; the third task is a previous calculation task of the second task; determining the validity of the calculation result based on the first verification result, the second verification result and the third verification result.

8. The method of claim 1, wherein, The method further comprises: in the case that the calculation result is determined to be valid, packaging and submitting the calculation result and a calculation task matching the calculation result.

9. The method of claim 1, wherein, The method further comprises: store the first task and / or the second task.

10. A data checking apparatus, characterized by comprising: comprise: a verification module, configured to obtain a calculation result output by the calculation core, verify the calculation result based on the first task to obtain a first verification result, and verify the calculation result based on the second task to obtain a second verification result; the first task is a latest calculation task of the calculation core, and the second task is a previous calculation task of the first task; an effectiveness determination module, configured to determine effectiveness of the calculation result based on the first verification result and the second verification result.

11. The apparatus of claim 10, wherein: the verification module comprises a first verification module and a second verification module; the first verification module verifies the calculation result based on the first task to obtain the first verification result; the second verification module verifies the calculation result based on the second task to obtain the second verification result.

12. The apparatus of claim 11, wherein, the effectiveness determination module comprises: a multiplexer comprising a first input end, a second input end, and an output end, the first input end being configured to input the first verification result, the second input end being configured to input the second verification result, and the output end being configured to output an effectiveness result of the calculation result.

13. The apparatus of claim 10, wherein: the verification module is further configured to verify the calculation result based on a third task to obtain a third verification result; the third task is a previous calculation task of the second task; the effectiveness determination module is further configured to determine the effectiveness of the calculation result based on the first verification result, the second verification result, and the third verification result.

14. The apparatus of claim 10, wherein, further comprise: a packaging module, configured to, in a case where the calculation result is determined to be effective, package and submit the calculation result and a calculation task matched with the calculation result.

15. The apparatus of claim 10, wherein, further comprise: a buffer connected to the verification module, configured to store the first task and / or the second task.

16. The apparatus of claim 10, wherein, further comprise: a pre-calculation module comprising a pre-calculation input end and a pre-calculation output end, the pre-calculation input end being configured to receive the first task, and the pre-calculation output end being connected to the calculation core and configured to output pre-calculation data.

17. A chip, characterized by for implementing the method according to any one of claims 1-9.

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