Data processing device, data processing method, and data processing system

Abstract

Provided is a technology for a device communicating with a plurality of pieces of equipment to achieve a good balance between communication efficiency and calculation efficiency.　This data processing device includes: a communication buffer that stores, for each of a plurality of control targets, control-related data acquired through communication with the plurality of control targets; a CPU that has a plurality of arithmetic units for executing control-related calculations for the plurality of control targets, and a plurality of RAMs for holding control-related data for each arithmetic unit; and a data transfer unit that continuously transfers control-related data stored in consecutive addresses, between the communication buffer and the plurality of RAMs in units of consecutive addresses a prescribed number of times.

Description

Data processing device, data processing method, and data processing system

[0001] The present invention relates to the configuration of a data processing device that processes data from industrial equipment, and more particularly to a data processing device, data processing method, and data processing system that receive and process data from a plurality of devices.

[0002] In configurations where multiple devices, such as industrial robots and power supply systems, communicate periodically, the increasing complexity of control requires high-speed processing of large amounts of data. In data communication, a communications driver on the operating system (OS) installed in the central processing unit (CPU) accesses memory and peripheral devices to send and receive data. This increases the load on the CPU in response to the amount of data received, potentially affecting the operation of control applications and data processing applications.

[0003] As a background technique in this technical field, for example, there is a technique such as Patent Document 1. Patent Document 1 discloses "a method for controlling parallel processing of the operation of a parallel data processor, comprising: monitoring one or more conditions related to processing executed by the parallel data processor; executing one or more instructions in parallel in two parallel processing elements of the data processor providing a data path of a first width when the monitored one or more conditions correspond to a first state; and executing one or more instructions in a first one of the two parallel processing elements so as to process data having a second width narrower than the first width when the monitored one or more conditions correspond to a second state, wherein a second one of the two parallel processing elements is inactive."

[0004] According to Patent Document 1, in a control device or data processing device, data to be processed by multiple arithmetic units is arranged in a continuous area of ​​the main memory, thereby making it possible to efficiently transfer data between the main memory and registers.

[0005] Special Publication No. 2008-544350

[0006] In Patent Document 1, data is transferred in batches of a predetermined number of bits, thereby improving the transfer efficiency between the main memory and the arithmetic unit. However, Patent Document 1 does not describe a method for improving the efficiency of arithmetic operations when each piece of data is distributed at locations farther apart than that.

[0007] An object of the present invention is to provide a technology that achieves both communication efficiency and calculation efficiency in a device that communicates with multiple devices.

[0008] In order to solve the above problems, the data processing device of the present invention is a data processing device that communicates control-related data with a plurality of control objects, and has a communication buffer that stores control-related data obtained through communication with the plurality of control objects for each control object, a CPU that has a plurality of arithmetic units that perform calculations related to control for the plurality of control objects and a plurality of RAMs that hold control-related data for each arithmetic unit, and a data transfer unit that continuously transfers the control-related data stored in consecutive addresses between the communication buffer and the plurality of RAMs in consecutive individual address units a predetermined number of times.

[0009] According to the present invention, in a data processing device that receives data from multiple external devices, by continuously accessing the received data stored in the main memory, it is possible to improve the efficiency of data transfer between the main memory and the arithmetic units. Furthermore, by providing a RAM for each arithmetic unit, it is possible to achieve arithmetic performance that is proportional to the number of arithmetic units.

[0010] This makes it possible to achieve both efficient data communication between devices and efficient computation for multiple targets in systems where multiple devices send and receive data, such as industrial robots and power supply systems.

[0011] Problems, configurations, and effects other than those described above will become apparent from the following description of the embodiments.

[0012] FIG. 1 is a functional block diagram of a data processing system according to a first embodiment of the present invention. FIG. 2 is a configuration example of a communication buffer according to the first embodiment of the present invention. FIG. 3 is a functional block diagram of a RAM according to the first embodiment of the present invention. FIG. 4 is a configuration example of a data holding unit according to the first embodiment of the present invention. FIG. 5 is a functional block diagram of a data transfer circuit according to the first embodiment of the present invention. FIG. 6 is a configuration example of a transfer address management unit according to the first embodiment of the present invention. FIG. 7 is an operation flow example of a RAM write data transfer unit according to the first embodiment of the present invention. FIG. 8 is an operation flow example of a RAM read data transfer unit according to the first embodiment of the present invention. FIG. 9 is a functional block diagram of a data processing system according to a second embodiment of the present invention. FIG. 10 is a configuration example of an arithmetic control unit according to the second embodiment of the present invention. FIG. 11 is a diagram showing the contents of arithmetic processing executed by an arithmetic unit according to the second embodiment of the present invention. FIG. 12 is a functional block diagram of a data transfer circuit according to the second embodiment of the present invention. FIG. 13 is a functional block diagram of an arithmetic control unit according to the third embodiment of the present invention. FIG. 14 is a configuration example of a condition determination unit according to the third embodiment of the present invention.

[0013] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In each drawing, the same components are basically designated by the same reference numerals, and detailed explanations of overlapping parts will be omitted. However, when the same components are designated by different reference numerals for the sake of convenience, an explanation to that effect will be added.

[0014] The examples are illustrative of the present invention, and have been omitted or simplified as appropriate for clarity of explanation. The present invention can be implemented in various other forms. Unless otherwise specified, each component may be singular or plural.

[0015] In order to facilitate understanding of the invention, the position, size, shape, range, etc. of each component shown in the drawings may not represent the actual position, size, shape, range, etc. Therefore, the present invention is not necessarily limited to the position, size, shape, range, etc. disclosed in the drawings.

[0016] Although various types of information may be described using expressions such as "table" and "list" as examples, the various types of information may also be expressed using data structures other than these. For example, various types of information such as "XX table" and "XX list" may also be expressed as "XX information." When describing identification information, expressions such as "identification information," "identifier," "name," "ID," and "number" are used, but these are interchangeable.

[0017] When there are multiple components with the same or similar functions, they may be described using the same reference numeral with different subscripts. When there is no need to distinguish between these multiple components, the subscripts may be omitted.

[0018] For convenience of explanation, the same components may be denoted by different reference numerals in different drawings.

[0019] In the embodiments, processing performed by executing a program may be described. Here, a computer executes the program using a processor (e.g., a CPU or a GPU) and performs processing defined by the program using storage resources (e.g., memory) and interface devices (e.g., communication ports). Therefore, the entity performing the processing by executing the program may be the processor. Similarly, the entity performing the processing by executing the program may be a controller, device, system, computer, or node having a processor. The entity performing the processing by executing the program may be any computing unit, and may include a dedicated circuit that performs specific processing. Here, the dedicated circuit may be, for example, an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), or a CPLD (Complex Programmable Logic Device).

[0020] A program may be installed on a computer from a program source. The program source may be, for example, a program distribution server or a computer-readable storage medium. When the program source is a program distribution server, the program distribution server may include a processor and storage resources for storing the program to be distributed, and the processor of the program distribution server may distribute the program to be distributed to other computers. In addition, in the embodiments, two or more programs may be realized as one program, or one program may be realized as two or more programs.

[0021] Before describing each embodiment in detail, an outline of the present invention will be described.

[0022] As mentioned above, when controlling industrial equipment such as industrial robots and power supply systems, it is necessary to process data and perform control calculations in parallel for a large number of targets based on the large amount of communication data generated between devices.Communication between devices acquires status information of the controlled targets, such as motor angle and operating status, as well as peripheral information from cameras and sensors, and calculates command values ​​from the received information and converts them into drive formats such as pulses for the controlled targets.

[0023] These information acquisition, command value calculation, and control according to the command values ​​are each performed by separate devices, and equipment control is achieved by sending and receiving data between the devices. In addition to the trend of an increasing number of information acquisition devices and control targets, the amount of data sent and received between devices is also increasing due to improvements in the resolution of acquired information and the increasing complexity of control content. In order to process the data sent from these many targets and calculate control commands, parallel calculations using multiple arithmetic units are used to speed up processing.

[0024] This requires real-time data processing and control that combines efficient communication with a large number of devices with efficient computation.

[0025] When performing parallel calculations using multiple arithmetic units, there is a problem with the efficiency of data transfer within the data processing device or control device. Data received from each device may be stored in a communication buffer provided in main memory. In this case, to efficiently receive data from each device, it is desirable to store the received data together for each target device.

[0026] On the other hand, when the received data is stored in main memory for each target device, each arithmetic unit provided for parallel calculations must access data in separate locations in main memory. Conventionally, calculation efficiency was improved by transferring data in a batch. However, when each piece of data is stored in a separate location, it cannot be transferred in a batch, and the effect of parallel calculations using multiple arithmetic units cannot be fully realized, resulting in reduced efficiency.

[0027] Therefore, in a data processing device that receives control-related data from multiple external devices, the efficiency of data transfer between the main memory and the arithmetic units can be improved by continuously accessing the received data stored in the main memory. Also, by providing a RAM for each arithmetic unit, it is possible to achieve arithmetic performance proportional to the number of arithmetic units.

[0028] The configuration of a data processing device and its control method according to a first embodiment of the present invention will be described with reference to FIGS.

[0029] FIG. 1 is an overall configuration diagram of a data processing system including a data processing device 101 and a plurality of control targets 105 according to this embodiment. A functional block diagram of the data processing device 101 is also shown. FIG. 2 is a configuration example of the communication buffer 102. FIG. 3 is a functional block diagram of RAM1 to RAMn (108-1 to 108-3). FIG. 4 is a configuration example of the data holding unit 301. FIG. 5 is a functional block diagram of the data transfer circuit 103. FIG. 6 is a configuration example of the address information management unit 501. FIG. 7 is an example of the operation flow of the RAM write data transfer unit 502. FIG. 8 is an example of the operation flow of the RAM read data transfer unit 503.

[0030] As shown in FIG. 1, the data processing device 101 of this embodiment mainly comprises a communication buffer 102 prepared in main memory, a data transfer circuit 103 that continuously transfers data from the communication buffer to a CPU 104, and the CPU 104 that performs calculations based on input data in accordance with a predetermined program (not shown).

[0031] The communication buffer 102 stores object 1 data 106-1 to object n data 106-3 for each of the control objects 1 (105-1) to n (105-3).

[0032] The CPU 104 includes a plurality of arithmetic units 1 to n (107-1 to 107-3) and RAMs 1 to n (108-1 to 108-3) dedicated to each arithmetic unit.

[0033] The devices that communicate with the data processing device 101 may be control targets 1 to n (105-1 to 105-3), as well as information gathering devices such as sensors and cameras, and other data processing devices and control devices that make up the system.

[0034] The CPU 104 has n computing units 107-1 to 107-3, and uses the object 1 data 106-1 in the computing unit 1 (107-1), the object 2 data 106-2 in the computing unit 2 (107-2), and the object n data 106-3 in the computing unit n (107-3).

[0035] Each computing unit 107 processes input data according to a program by combining addition, subtraction, multiplication, division, etc. The processed data is used as the analysis result of the input data, the control command value for each target, etc. RAMs 1 to n (108-1 to 108-3) are assigned to each computing unit 1 to n (107-1 to 107-3), respectively, and the computing unit 107 obtains data from the assigned RAM 108 and performs calculations. The calculation results are then stored again in the assigned RAM 108.

[0036] In the following examples, unless the subject of the operation processing is specified, it is assumed that the processing is performed by one of the computing units 107 in the CPU 104 or another computing unit not shown executing a specified program, etc.

[0037] The RAMs 108 store data 106 for each object. For example, object 1 data 106-1 is stored in RAM 1 (108-1), object 2 data 106-2 is stored in RAM 2 (108-2), and object n data 106-3 is stored in RAM n (108-3).

[0038] An example of the configuration of the communication buffer 102 will be described using Figure 2. The communication buffer 102 stores data received collectively for each control target 105. Target 1 data 106-1 received from control target 1 (105-1) stores m pieces of data, including data 1-1, 1-2, and so on, up to 1-m. Similarly, data received from n control targets, from target 2 data to target n data, is stored in m sets. Data for the same target is stored collectively at consecutive addresses, but data for different targets may be stored at distant addresses.

[0039] The configuration of the RAM 108 will be described using Figure 3. RAM 108-1 to RAM 108-3 represent n RAMs with the same structure. RAM 108 is composed of a data holding unit 301, write ports 1 and 2, and read ports 1 and 2, which control data input and output. In the example of Figure 3, there are two write ports and two read ports. Write port 1 and read port 1 are used to read and write data from the arithmetic unit 107. Write port 2 and read port 2 are configured to be used for continuous data read and write to the communication buffer 102. The same port may be used for both reading and writing, or more ports may be provided.

[0040] A write instruction signal indicating a flag indicating that data is to be written, a write destination address, and write data are input to the write port 1 from the arithmetic unit 107. A read instruction signal indicating a flag indicating that data is to be read, and an address of the read data are input to the read port 1, and the corresponding data is read out as read data. In this case, the write instruction signal, read instruction signal, and address information are generated by the CPU 104.

[0041] Similarly, in the case of continuous transfer using the data transfer circuit 103, operation management and data input / output are performed at the write port 2 and the read port 2. In this case, the write instruction signal, read instruction signal, and address information for continuous transfer are generated by the data transfer circuit 103.

[0042] The configuration of the data storage unit 301 will be described using Figure 4. The data storage unit 301 is stored in RAM1 (108-1) as data storage unit 1 (301-1), and in RAM2 (108-2) as data storage unit 2 (301-2), one for each. Data storage unit 1 (301-1) stores the target 1 data 106-1 input by the data transfer circuit 103. In addition, the results of data processing by the calculator 1 (108-1) may be stored. Similarly, data storage unit 2 (301-2) stores the target 2 data 106-2, and data storage unit n (301-3) stores the target n data 106-3, as well as the data processing results of the corresponding calculator 108.

[0043] 5, the configuration of the data transfer circuit 103 will be described. The data transfer circuit 103 has an address information management unit 501, a RAM write data transfer unit 502, and a RAM read data transfer unit 503.

[0044] The address information management unit 501 stores the address of the data stored in the communication buffer 102 when continuously transferring data and the corresponding address information in the RAM 108, and specifies the combination of addresses to be transferred next by each data transfer unit (502, 503) based on the address correspondence information.

[0045] When transferring data from the communication buffer 102 to the RAM 108, the RAM write data transfer unit 502 issues a communication buffer read source address and a communication buffer read instruction signal to instruct data reading from the communication buffer. Then, it issues a RAM consecutive write destination address and a RAM consecutive write instruction signal to instruct data writing to the RAM 108. The communication buffer read data received from the communication buffer 102 is sent to the corresponding RAM 108 as RAM consecutive write data.

[0046] The RAM continuous write instruction signal is made up of n bits, each bit corresponding to a continuous write instruction for each of the RAMs 108-1 to 108-3. When continuously transferring data from the RAM 108 to the communication buffer 102, the RAM read data transfer unit 503 issues a RAM continuous read source address and a RAM continuous read instruction signal to instruct the RAM 108 to read data, and issues a communication buffer write destination address and a communication buffer write instruction signal to instruct the communication buffer 102 to write data. The RAM continuous read data received from the RAM 108 is transmitted to the communication buffer 102 as a communication buffer write instruction signal.

[0047] 6, the data configuration of the address information management unit 501 in the data transfer circuit 103 will be described. The address information management unit 501 holds information for when data is read from the communication buffer 102 and written to the RAM 108, and information for when data is read from the RAM 108 and written to the communication buffer 102. In the former case, the transfer direction 501A is distinguished as "RAM write," and in the latter case, the transfer direction 501A is distinguished as "RAM read."

[0048] In other words, in the case of RAM writing, each piece of information means the number (RAM number) 501B of RAM 108 to which data is written, the starting address (RAM address) 501C of the data writing destination in RAM 108 for continuous transfer, the starting address (communication buffer address) 501D of the data to be continuously transferred from communication buffer 102 to RAM 108, and the amount of data to be continuously transferred (transfer data amount) 501E.

[0049] On the other hand, when transferring data in the direction of reading data from RAM 108 and writing it to communication buffer 102 (RAM read), each piece of information means the number of RAM 108 from which the data is read (RAM number) 501B, the starting address of the data to be read from RAM 108 (RAM address) 501C, the starting address of the data to be written to communication buffer 102 (communication buffer address) 501D, and the amount of data to be continuously transferred (transfer data amount) 501E.

[0050] Here, by making the data write destination address and read source address of the RAM 108 common to each RAM (108-1 to 108-3), it is possible to perform processing more efficiently.

[0051] 7, the operation of the RAM write data transfer unit 502 will be described. The RAM write data transfer unit 502 first initializes the number of the RAM 108 to which data is to be transferred to 1 and the amount of transferred data to 0 (step S701).

[0052] Next, in accordance with the information of the address information management unit 501 (information indicating that the transfer direction 501A in FIG. 6 is "RAM write"), the RAM write data transfer unit 502 sets the RAM continuous write destination address (RAM address 501C in FIG. 6) and the communication buffer read source address (communication buffer address 501D in FIG. 6) (step S702).

[0053] Thereafter, the RAM write data transfer unit 502 raises the bit of the RAM continuous write instruction signal, which is composed of multiple bits, corresponding to the RAM 108 specified by the RAM number, and also raises the read instruction signal for the communication buffer 102 (step S703). Here, "raise" means designating the corresponding location or operation instruction from "0: OFF" to "1: ON." This enables continuous data transfer between the corresponding RAM 108 and communication buffer 102.

[0054] When the RAM write data transfer unit 502 receives the data from the communication buffer 102, it writes (transfers) the data to the selected RAM 108 (step S704).

[0055] When the data transfer is completed, the RAM write data transfer unit 502 increments the RAM consecutive write destination address, the communication buffer read source address, and the transferred data amount by one transfer (step S705). The increment amount at this time may be changed depending on the amount of data that can be transferred at one time.

[0056] The RAM write data transfer unit 502 checks whether all data has been transferred for the RAM 108 (step S706), and if not completed ("No" in step S706), transfers the data again (step S704).

[0057] When all data transfer for the RAM 108 has been completed ("Yes" in step S706), the RAM write data transfer unit 502 checks whether data transfer to all RAMs has been completed (step S707).

[0058] If there is a RAM 108 to which data has not been transferred ("No" in step S707), the RAM write data transfer unit 502 increments the RAM number by 1 (step S708) and repeats the process from specifying the RAM continuous write destination address and the communication buffer read source address (step S702).

[0059] If data transfer to all of the RAMs 108 is completed (“Yes” in step S707), the RAM write data transfer unit 502 ends the continuous transfer in the RAM write direction.

[0060] 8, the operation of the RAM read data transfer unit 503 will be described. The RAM read data transfer unit 503 first initializes the number of the RAM 108 that is the data transfer source to 1 and the amount of transferred data to 0 (step S801).

[0061] Next, the RAM read data transfer unit 503 sets the RAM continuous read source address and the communication buffer write destination address according to the information in the address information management unit 501 (information indicating that the transfer direction 501A in FIG. 6 is "RAM read") (step S802).

[0062] Thereafter, the RAM read data transfer unit 503 raises the bit of the RAM continuous read instruction signal corresponding to the RAM 108 specified by the RAM number, and raises the write instruction signal for the communication buffer (step S803). This enables continuous data transfer between the corresponding RAM 108 and the communication buffer 102.

[0063] When the RAM read data transfer unit 503 receives the data from the selected RAM 108, it writes (transfers) the data to the communication buffer 102 (step S804).

[0064] When the data transfer is completed, the RAM read data transfer unit 503 increments the RAM continuous read source address, the communication buffer write destination address, and the transferred data amount by one transfer (step S805). The increment amount at this time may be changed depending on the amount of data that can be transferred at one time.

[0065] The RAM read data transfer unit 503 checks whether all data has been transferred for the RAM 108 (step S806), and if not ("No" in step S806), transfers the data again (step S804).

[0066] When all data transfer for the RAM 108 has been completed ("Yes" in step S806), the RAM read data transfer unit 503 checks whether data transfer from all RAMs 108 has been completed (step S807).

[0067] If there is a RAM 108 to which data has not been transferred ("No" in step S807), the RAM read data transfer unit 503 increments the RAM number by 1 (step S807) and repeats the process from specifying the RAM continuous read source address and the communication buffer write destination address (step S802).

[0068] If data transfer from all of the RAMs 108 is completed ("Yes" in step S807), the RAM read data transfer unit 503 ends the continuous transfer in the RAM read direction.

[0069] As described above, according to this embodiment, in a data processing device that receives data from a plurality of external devices, by continuously accessing the received data stored in the main memory, it is possible to improve the efficiency of data transfer between the main memory and the arithmetic units. Furthermore, by providing a RAM for each arithmetic unit, it is possible to achieve arithmetic performance that is proportional to the number of arithmetic units.

[0070] This makes it possible to achieve both efficient data communication between devices and efficient computation for multiple targets in systems where multiple devices send and receive data, such as industrial robots and power supply systems.

[0071] A data processing system according to a second embodiment of the present invention will be described with reference to Figs. 9 to 12. Fig. 9 shows an example of the configuration of a data processing system having a data processing device 101A according to this embodiment. Fig. 10 shows an example of the configuration of an arithmetic control unit 901 arranged in the CPU 104 in Fig. 9. Fig. 11 shows the contents of the arithmetic processing executed by the arithmetic unit 107 in Fig. 9. Fig. 12 shows an example of the configuration of a data transfer circuit 103A according to this embodiment.

[0072] The configuration of the data processing device 101A of this embodiment will be described with reference to Figure 9. The data processing device 101A of this embodiment has an arithmetic control unit 901 in a CPU 104A, which specifies the content of the arithmetic operation to each arithmetic unit 107, specifies the source address and destination address of data to each RAM 108, and instructs the data transfer circuit 103A to transfer data continuously.

[0073] 10, the configuration of the arithmetic control unit 901 will be described. The arithmetic control unit 901 has an instruction group holding unit 1001, a continuous transfer instruction unit 1002, a RAM address determination unit 1003, an arithmetic result holding unit 1004, and an input value selection unit 1005.

[0074] The instruction set holding unit 1001 holds instructions for continuous transfer, RAM addresses for reading and writing, and instructions for operation of each arithmetic unit and instructions for determining input values. The same value of the instruction for operation of each arithmetic unit is sent to all arithmetic units as a control operation signal.

[0075] When the instruction group holding unit 1001 issues an instruction to instruct continuous data transfer, the continuous transfer instruction unit 1002 issues a continuous transfer instruction (RAM write) or continuous transfer instruction (RAM read) to the data transfer circuit 103 .

[0076] The RAM address determination unit 1003 determines the RAM source address and write destination address in accordance with the instruction issued from the instruction group holding unit 1001, in combination with the value of the operation result holding unit 1004. The RAM reference address is determined by adding the value issued from the instruction group holding unit 1001 to the value of the operation result holding unit 1004, in which the operation results of each arithmetic unit 107 are temporarily stored. However, whether or not to add the value of the operation result holding unit 1004 is determined by the issued instruction.

[0077] In this embodiment, the calculator 107 is assumed to receive a calculator input value from the calculation control unit 901 as a first input value and a value read from the RAM 108 as a second input value, and to perform a predetermined calculation process on these values.The input value selection unit 1005 selects one of the calculator input values ​​from either a value issued by the instruction group holding unit 1001 or a value held by the calculation result holding unit 1004 in accordance with an instruction issued by the instruction group holding unit 1001, and transmits the selected value to each calculator 107.

[0078] In this embodiment, the input to the calculator 107 is an example in which either the value issued by the instruction group storage unit 1001 or the value of the calculation result storage unit 1004 is used as the first input value, and the value read from RAM is used as the second input value, but the value issued by the instruction group storage unit 1001 and the value of the calculation result storage unit 1004 may also be used as the first input value and the second input value of the calculator 107, respectively.

[0079] In addition, the calculation result holding unit 1004 may hold one value per calculation unit (107), or may hold multiple calculation results per calculation unit (107) and select one based on the instruction issued from the instruction group holding unit 1001.

[0080] An example of the arithmetic processing of the arithmetic unit 107 in this embodiment will be described with reference to Fig. 11. Fig. 11 is an arithmetic processing table 1100 showing the content of the arithmetic processing executed by the arithmetic unit 107, and each arithmetic unit 107 performs an arithmetic operation 1102 in accordance with an arithmetic control signal 1101 issued from the arithmetic control unit 901. That is, the arithmetic unit 107 performs an arithmetic operation 1102 such as addition, subtraction, logical sum, or comparison of two input values ​​("a" and "b" in Fig. 11) in accordance with the value indicated by the arithmetic control signal 1101, and outputs the arithmetic result ("z" in Fig. 11).

[0081] The output operation results are stored in the operation control unit 901 and in designated write addresses in the RAMs 108 corresponding to the operation units 107. In this embodiment, the operation control signal is represented by 4 bits, but the length may be changed depending on the type of operation.

[0082] The configuration of the data transfer circuit 103 in this embodiment will be described with reference to Figure 12. The data transfer circuit 103 starts continuous data transfer in response to a continuous transfer command output from the arithmetic and control unit 901. When a continuous transfer command (RAM write) is issued, data is continuously transferred from the communication buffer 102 to the RAM 108, as in the first embodiment. When a continuous transfer command (RAM read) is issued, data is continuously transferred from the RAM 108 to the communication buffer 102.

[0083] According to the present embodiment described above, by providing an arithmetic control unit 901 in addition to the configuration of the first embodiment, it becomes possible to manage multiple arithmetic operations and RAM data specification with a single instruction, and it becomes easier to control parallel arithmetic operations using multiple arithmetic units and RAMs corresponding to each arithmetic unit.

[0084] A data processing device according to a third embodiment of the present invention will be described with reference to Fig. 13 and Fig. 14. Fig. 13 shows an example of the configuration of an arithmetic and control unit 901B according to this embodiment. Fig. 14 shows a processing table for a condition determination unit 1301 in the arithmetic and control unit 901B shown in Fig. 13.

[0085] The configuration of the arithmetic and control unit 901B of this embodiment will be described with reference to Fig. 13. The arithmetic and control unit 901B of this embodiment has a configuration in which a condition determination unit 1301 is added to the arithmetic and control unit 901 of the second embodiment (Fig. 10).

[0086] In the operation control unit 901 of this embodiment, the output of the instruction group holding unit 1001 is first acquired by a condition determination unit 1301. The condition determination unit 1301 receives the operation results (including intermediate operation states) output by each operation unit 107 as states 1301a from the operation result holding unit 1004, and grasps the states of each operation unit 107.

[0087] The instruction set holding unit 1001 indicates the condition 1301b for executing the operation in addition to the operation instruction of each arithmetic unit. The condition decision unit 1301 determines whether or not to execute the instruction of each arithmetic unit based on the condition 1301b and the state 1301a of each arithmetic unit 107, and transmits the instruction issued by the instruction set holding unit 1001 only to the arithmetic units 107 and RAM 108 that it has determined to execute, and invalidates the instruction for the arithmetic units 107 and 108 that it has determined not to execute.

[0088] The processing of the condition decision unit 1301 will be described with reference to Fig. 14. The condition decision unit 1301 decides whether to execute an instruction based on a condition 1301b issued from the instruction group holding unit 1001 and a state 1301a of each arithmetic unit 107. An arithmetic unit 107 whose condition 1301b matches the state 1301a executes the instruction and outputs the instruction from the instruction group holding unit 1001. An arithmetic unit 107 whose condition and state do not match invalidates the instruction.

[0089] In this embodiment, the comparison operation result of the calculator 107 is stored for each bit of the state, but the method of expressing the conditions and states and the bit length are not limited, and may be stored for multiple bits, or the results of arithmetic operations or logical operations.

[0090] As described above, according to this embodiment, a condition determination unit 1301 is added to the calculation control unit 901B, and conditional determination is made on the instruction execution of the multiple calculation units 107 and RAM 108, thereby enabling different processes to be executed in parallel in each calculation unit by conditional branching.

[0091] 101: Data processing device 101A: Data processing device 102: Communication buffer 103: Data transfer circuit 103A: Data transfer circuit 104: CPU 105: Control target 106: Target data 107: Arithmetic unit 108: RAM 301: Data holding unit 501: Address information management unit 502: RAM write data transfer unit 503: RAM read data transfer unit 901: Arithmetic control unit 901B: Arithmetic control unit 1001: Instruction group holding unit 1005: Input value selection unit 1301 Condition decision unit

Claims

1. A data processing device that communicates control-related data with a plurality of control objects, comprising: a communication buffer that stores the control-related data obtained through communication with the plurality of control objects for each of the control objects; a CPU having a plurality of arithmetic units that perform calculations related to the control of the plurality of control objects and a plurality of RAMs that hold the control-related data for each of the arithmetic units; and a data transfer unit that continuously transfers the control-related data stored in consecutive addresses between the communication buffer and the plurality of RAMs in units of each consecutive address a predetermined number of times.

2. A data processing device according to claim 1, wherein data received from said plurality of control targets is stored in said communication buffer consecutively for each of said control targets.

3. A data processing device according to claim 2, wherein the data transfer unit comprises: an address information management unit having correspondence information between the communication buffer and the corresponding RAM when the control-related data is continuously transferred; a RAM write data transfer unit that issues a control signal when data is transferred from the communication buffer to the RAM based on the correspondence information of the address information management unit; and a RAM read data transfer unit that issues a control signal when data is transferred from the RAM to the communication buffer based on the correspondence information of the address information management unit.

4. A data processing device according to claim 3, wherein the address information management unit holds the starting address of the control-related data stored in the communication buffer to be continuously transferred, a RAM number and its starting address that identify the RAM to which the control-related data of the communication buffer is continuously transferred, and the amount of the control-related data to be continuously transferred.

5. A data processing device according to claim 4, wherein the arithmetic unit acquires the control-related data from the allocated RAM, performs a predetermined calculation, and stores the calculation result in the allocated RAM.

6. A data processing device according to claim 5, characterized in that it has an arithmetic control unit which specifies the content of the arithmetic operation to said arithmetic unit, specifies the source address and destination address of data to be read from and written to RAM allocated to said arithmetic unit, and instructs said data transfer unit to continuously transfer said control-related data.

7. A data processing device according to claim 6, wherein said arithmetic control unit instructs each of said arithmetic units to perform the same arithmetic operation.

8. A data processing device according to claim 7, wherein said calculation control unit has a condition decision unit which decides whether or not to execute a calculation for each of said calculation units based on the calculation results of each of said calculation units.

9. A data processing method in a data processing device having a communication buffer and multiple RAMs for communicating control-related data with multiple control objects, characterized in that the control-related data obtained through communication with the multiple control objects is stored in the communication buffer for each of the control objects, the control-related data is stored in the multiple RAMs provided for each of multiple arithmetic units that perform calculations related to the control of the multiple control objects, and the control-related data stored in consecutive addresses between the communication buffer and the multiple RAMs is continuously transferred in units of each consecutive address a predetermined number of times.

10. A data processing system comprising: a plurality of control objects; and a data processing device for communicating control-related data with said plurality of control objects, wherein said data processing device comprises: a communication buffer for storing the control-related data acquired through communication with said plurality of control objects for each of said control objects; a CPU having a plurality of arithmetic units for executing calculations relating to the control of said plurality of control objects and a plurality of RAMs for holding the control-related data for each of said arithmetic units; and a data transfer unit for continuously transferring the control-related data stored in consecutive addresses between said communication buffer and said plurality of RAMs for each of said consecutive addresses a predetermined number of times.

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