Communication method and communication apparatus

Abstract

Provided in the present application are a communication method and a communication apparatus. Particularly provided is a nested construction method for a parity-check matrix. A parity-check matrix required for encoding may be a submatrix read from a mother parity-check matrix, such that flexible code lengths and code rates can be supported. The element in an i-th row and j-th column of the mother parity-check matrix is different from the element in the i-th row and a k-th column of the mother parity-check matrix, where k is the maximum column index that is smaller than j and meets the condition that the elements in the first (i-1) rows and the k-th column of the mother parity-check matrix are the same as the elements in the first (i-1) rows and the j-th column of the mother parity-check matrix. The mother parity-check matrix comprises a core part and a parity part, wherein the core part is a dense matrix, the parity part is a lower triangular matrix, and using the lower triangular matrix can implement fast encoding. In addition, using the parity-check matrix can reduce decoding complexity, and improve the code distance, thereby improving decoding performance and ensuring stable decoding performance.

Description

Communication methods and communication devices

[0001] This application claims priority to Chinese Patent Application No. 202410799117.4, filed on June 19, 2024, entitled "Communication Method and Communication Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of communication technology, and in particular to a communication method and communication device. Background Technology

[0003] Guessing random additive noises decoding (GRAND) and recoding GRAND are two decoding schemes for linear codes. GRAND is a decoding method that repeatedly attempts to flip one, two, three, ..., several bits (not exceeding the flip order) of the hard-decision codeword in the received sequence to find the codeword closest to the received symbol as the decoding result. The flip order refers to the maximum number of bits flipped. GRAND decoding has high complexity. Recoding GRAND differs from GRAND in that it only flips the information bits and then recodes them. Each flip yields a valid codeword. Compared to GRAND, which flips the codeword, recoding GRAND has the advantages of lower complexity and better performance. However, recoding GRAND involves multiple recoding operations during the decoding process.

[0004] Given the characteristics of the two decoding schemes mentioned above, there is an urgent need for an encoding scheme that can achieve fast encoding while improving the code spectrum to enhance decoding performance. Summary of the Invention

[0005] This application provides a communication method and a communication device that can achieve fast encoding and improve decoding performance.

[0006] Firstly, a communication method is provided, which can be executed by a communication device or a module applied to the communication device (e.g., a processor, chip, chip system, integrated circuit, etc., or a logic module, hardware, and / or software capable of implementing all or part of the functions of the communication device). The communication device can be a terminal device or a network device. When the communication method is an encoding method, the communication device is also called an encoding device, without limitation. The communication method may include: acquiring an information bit sequence; encoding the information bit sequence based on a first parity check matrix to obtain a first codeword, wherein the first parity check matrix is ​​a submatrix of a second parity check matrix, the element in the i-th row and j-th column of the second parity check matrix is ​​different from the element in the i-th row and k-th column, k is the largest column index less than j that satisfies the condition that the element in the first i-1 rows and k-th column of the second parity check matrix is ​​the same as the element in the first i-1 rows and j-th column of the second parity check matrix, i is an integer greater than 1, and j is an integer; and outputting the first codeword.

[0007] This application provides a verification matrix H. m The construction method (corresponding to the second parity check matrix in the embodiment) allows for nested construction that meets certain conditions. The first parity check matrix (corresponding to the parity check matrix H in the embodiment) corresponding to (K, N) required for encoding or decoding can be read from the second parity check matrix (as the parent matrix), where K is the number of information bits and N is the length of the first codeword. Parity check matrix H m The element in the i-th row and j-th column is different from the element in the i-th row and k-th column, where k is less than j and satisfies the verification matrix H. m The elements in the first i-1 rows and k-th column of the parity matrix H m The largest column index where the elements in the first i-1 rows and j-th column are identical. Using the check matrix H... m Fast encoding can be achieved. Additionally, the parity-check matrix H... m If any two columns are different, then two identical columns will produce a valid codeword with a weight of 2. Therefore, the parity check matrix H... m The design reduces the number of low-duplicate codewords, thereby improving the code spectrum, enhancing performance, and ensuring stable decoding performance. Furthermore, its code distance and error correction performance at high code rates are superior to random codes.

[0008] Secondly, a communication method is provided, which can be executed by a communication device or a module applied to the communication device (e.g., a processor, chip, chip system, integrated circuit, etc., or a logic module, hardware, and / or software capable of implementing all or part of the functions of the communication device). The communication device can be a terminal device or a network device. When the communication method is a decoding method, the communication device is also called a decoding device, without limitation. The communication method may include: acquiring information to be decoded; decoding the information to be decoded based on a first parity check matrix to obtain a decoding result, wherein the first parity check matrix is ​​a submatrix of a second parity check matrix, the element in the i-th row and j-th column of the second parity check matrix is ​​different from the element in the i-th row and k-th column of the second parity check matrix, k is the largest column index less than j that satisfies the condition that the element in the first i-1 rows and k-th column of the second parity check matrix is ​​the same as the element in the first i-1 rows and j-th column of the second parity check matrix, i is an integer greater than 1, and j is an integer; and outputting the decoding result.

[0009] The technical effects of the second aspect are explained in the first aspect and will not be repeated here.

[0010] In conjunction with the second aspect, in some implementations of the second aspect, the decoding of the information to be decoded based on the first parity check matrix includes: decoding the information to be decoded based on the first parity check matrix and the guessing random additive noise decoding GRAND method; or, decoding the information to be decoded based on the first parity check matrix and the recoded guessing random additive noise decoding GRAND method.

[0011] In this implementation, the verification matrix H provided in this application m (Alternatively, the parity check matrix H) is suitable for GRAND or recoded GRAND, improving decoding performance and ensuring stable decoding performance.

[0012] In conjunction with the second aspect, in some implementations of the second aspect, the decoding of the information to be decoded based on the first parity check matrix and the recoding guess random additive noise decoding GRAND method includes: determining the hard decision sequence and the corresponding confidence sequence of the information to be decoded; sequentially encoding candidate codewords based on the hard decision sequence and the first parity check matrix, and calculating the path metric PM value corresponding to each candidate codeword based on the confidence sequence; and outputting the candidate codeword with the smallest PM value as the decoding result.

[0013] In this implementation, the information to be decoded can be a channel received sequence or a log-likelihood ratio (LLR) sequence. When decoding using the first parity-check matrix and recoding GRAND provided in this application, the hard-decision sequence or the reversed hard-decision sequence of the information to be decoded is recoded based on the first parity-check matrix to obtain recoded codewords as candidate codewords, and the PM value of each candidate codeword is calculated. Finally, by comparing the PM values, the candidate codeword corresponding to the smallest PM is output as the decoding result.

[0014] In some implementations of the first or second aspect, the second verification matrix includes a core portion and a verification portion, wherein the core portion is a dense matrix and the verification portion is a lower triangular matrix.

[0015] In this implementation, the check portion of the second parity-check matrix is ​​a lower triangular matrix, which enables fast recoding. In some implementations of the first or second aspect, the second parity-check matrix is ​​N. m -K m row, N m A matrix of columns, the first to the Kth columns of the second parity matrix. m The core component is listed below, and the K of the second verification matrix is... m +1 column to Nth m The column is the verification part, where N m N is the maximum length of the codeword corresponding to the first parity check matrix. m -K m This represents the maximum number of check bits.

[0016] In some implementations of the first or second aspect, the first row of the core portion of the second check matrix is ​​always 1.

[0017] In some implementations of the first or second aspect, the 0s and 1s of the core portion of the second check matrix are uniformly distributed.

[0018] In some implementations of the first or second aspect, the first row to the NKth row and the Kth row of the second parity check matrix m -K+1 column to Kth column m The +NK column represents the first parity check matrix, where N is the length of the codeword corresponding to the first parity check matrix, K is the number of information bits, and NK is the number of parity bits, where NK is less than or equal to N. m -K m K is less than or equal to K m .

[0019] In this implementation, since the design of the second parity check matrix can support nested construction, it can support flexible code length and code rate.

[0020] In some implementations of the first or second aspect, the i-th check bit is obtained by encoding the information bit sequence, the first i-1 check bits, and the first to K+i-1 columns of the i-th row of the first check matrix, where i is greater than or equal to 1 and less than or equal to NK.

[0021] Thirdly, a communication device is provided, which has the function of implementing the method of the first aspect or the second aspect, or any possible implementation of the method of the first aspect or the second aspect. The function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more units corresponding to the above-described function.

[0022] Fourthly, a communication device is provided, comprising at least one processor configured to cause the communication device to perform the method of the first aspect or any possible implementation thereof. Optionally, the at least one processor is coupled to at least one memory for storing computer programs or instructions, and the at least one processor is configured to call and run the computer program or instructions from the at least one memory, causing the communication device to perform the method of the first aspect or any possible implementation thereof, or to perform the method of the second aspect or any possible implementation thereof. Optionally, the at least one processor may be included in the communication device or may be configured outside the communication device. Optionally, the communication device further includes the at least one memory. Furthermore, the communication device may optionally include a communication interface coupled to the at least one processor, which can be used to input information and / or data to the at least one processor, or to output information and / or data from the at least one processor.

[0023] In one example, the communication device described in the third or fourth aspect may be an encoding device or a decoding device.

[0024] Optionally, the communication device of the third or fourth aspect can be a chip. As an example, the chip can be a modem chip, also known as a baseband chip, or a system-on-chip (SoC) chip containing a modem, or a system-in-package (SIP) chip, etc., without limitation.

[0025] Fifthly, a communication device is provided, comprising a communication interface and a circuit. The communication interface is used to acquire an information bit sequence; the circuit is used to execute the encoding method described in the first aspect to encode the information bit sequence to obtain a first codeword. Optionally, the communication interface is further used to output the first codeword. The communication device may be an encoding device. Optionally, the communication device may be a chip.

[0026] Sixthly, a communication device is provided, comprising a communication interface and a circuit, wherein the communication interface is used to receive a channel received sequence; the circuit is used to execute a decoding method as described in the second aspect or any possible implementation thereof, to decode the channel received sequence and obtain a decoding result. Optionally, the communication interface is further used to output the decoding result. The communication device may be a decoding device. Optionally, the communication device may be a chip.

[0027] In a seventh aspect, a computer-readable storage medium is provided, wherein computer program code or instructions are stored therein, which, when executed on a computer, cause the method of the first aspect to be implemented; or, the method of the second aspect or any possible implementation thereof to be implemented.

[0028] Eighthly, a computer program product is provided, the computer program product comprising computer program code or instructions that, when executed on a computer, cause the method of the first aspect to be implemented; or, as in the second aspect or any possible implementation thereof, the method to be implemented.

[0029] A ninth aspect provides a wireless communication system including a decoding device as described in the first aspect. Optionally, the communication system further includes a corresponding encoding device. Attached Figure Description

[0030] Figure 1 is a schematic diagram of the GRAND decoding process.

[0031] Figure 2 is a schematic diagram of the decoding process of the recoded GRAND.

[0032] Figure 3 is a schematic diagram of a communication system applicable to the technical solution of this application.

[0033] Figure 4 is a schematic diagram of the basic process of wireless communication.

[0034] Figure 5 is a schematic flowchart of the encoding / decoding method provided in this application.

[0035] Figure 6 shows the verification matrix H provided in this application. m A schematic diagram.

[0036] Figure 7 shows the results from the verification matrix H.m A schematic diagram of reading a submatrix.

[0037] Figures 8 to 10 are simulation diagrams illustrating the performance of the encoding / decoding methods provided in the embodiments of this application.

[0038] Figures 11 to 13 are simulation diagrams illustrating the performance of the encoding / decoding methods provided in the embodiments of this application.

[0039] Figure 14 is a schematic structural diagram of a communication device provided in this application.

[0040] Figure 15 is another schematic structural diagram of the communication device provided in this application.

[0041] Figure 16 is a schematic structural diagram of the chip provided in this application. Detailed Implementation

[0042] The technical solutions in this application will now be described with reference to the accompanying drawings.

[0043] To facilitate understanding, a brief introduction to the relevant concepts involved in this application is provided.

[0044] (1) Linear code generation matrix

[0045] In coding theory, a generator matrix is ​​a matrix whose rows form a basis for linear codes. All codewords are linear combinations of the rows of this matrix; that is, a linear code is the row space of its generator matrix. If G is a coding matrix, the way to generate codewords for a linear code C is: w = s * G, where w is a codeword of the linear code C, and s is an arbitrary vector (also the information to be encoded). The generator matrix of a linear (N,K,d,q) code has the format K*N, where N is the code length, K is the number of information bits (as the dimension of the vector subspace C), d is the minimum distance between symbolic elements, and q is the size of the finite field, i.e., the number of symbols in the dictionary (therefore q = 2 represents a binary code). The number of check bits is represented by r = NK.

[0046] (2) Verification matrix

[0047] The parity check matrix can also be used to define linear codes. E = H * w, where H represents a (NK) * N parity check matrix, and E represents the check result. When all values ​​of E are 0, the check passes. In this case, w is a codeword. If H has d linearly dependent columns, that is, ... in For H's j-th i List, Not all values ​​are 0. Therefore, w is a codeword with a weight less than or equal to d, where... The remaining positions of w are 0.

[0048] (3) Guessing random additive noise decoding (GRAND)

[0049] GRAND decoding requires a parity check matrix H and a hard decision result of the channel received sequence. The GRAND decoding process is as follows:

[0050] 1. To Perform a verification; if If the result is all zeros, then the verification is passed and the decoding ends.

[0051] 2. If the verification fails, then... A certain position is randomly flipped (0->1 or 1->0). The flipped value is then... Perform a verification; if the verification passes, the decoding ends; otherwise, proceed with the decoding. Flip it at another position and check it until a flipped vector that passes the check is found, or... Flip the value once at any position. Here, "0->1" means 0 is flipped to 1; similarly, "1->0" means 1 is flipped to 0.

[0052] 3. If the verification fails even after flipping the element at any position, then... Flip any two positions and determine if the check passes.

[0053] 4. After trying all the combinations of flipping two positions, proceed to flipping combinations of 3, 4, 5, ... and so on, until the result is verified to be correct.

[0054] Figure 1 illustrates the GRAND decoding process. As shown in Figure 1, the channel received sequence is (0.3, -1.1, 2, -0.5), and the corresponding hard decision sequence is (0, 1, 0, 1). The hard decision sequence also corresponds to a flip order of 0, meaning no flipping is performed. When the flip order is 1, a bit at one position in the hard decision sequence is flipped. For example, the first bit of the hard decision sequence is flipped first, resulting in a flipped sequence. If this flipped sequence fails verification, the second bit of the hard decision sequence is flipped. The flipped sequence obtained by flipping the second bit is then verified. If the verification fails, the third bit can be flipped, and so on. If the flipped sequence obtained by flipping the third bit of the hard decision sequence passes verification, the verified flipped sequence is output as the decoding result. In Figure 1, as an example, the verified flipped sequence is (0, 1, 1, 1), therefore, the decoding result is (0, 1, 0, 1). Furthermore, Figure 1 uses the example of flipping the bits at positions 1, 2, ... in sequence. As can be seen from the above GRAND decoding process, the flipping order can be randomly selected.

[0055] As can be seen, GRAND decoding is a decoding method that finds the codeword closest to the received symbol by continuously trying to flip 1, 2, 3... symbols and uses it as the decoding result.

[0056] The advantage of GRAND decoding is that it only requires a parity check matrix for decoding and is applicable to any code. For extremely high code rates or very short code lengths, GRAND decoding can quickly obtain the decoding result.

[0057] (4) Re-encoding GRAND

[0058] The difference between recoded GRAND and GRAND is that recoded GRAND only flips the information bits and then recodes them; that is, each flip yields a valid codeword. The decoding process of recoded GRAND is as follows:

[0059] 1. Hard decision on the received sequence Re-encoding to obtain Path metrics (PM) values ​​are calculated based on the soft information of the received sequence.

[0060] 2. Regarding A specific bit of information is randomly flipped (0->1 or 1->0). The flipped bits... Re-encoding to obtain The PM is calculated based on the soft information of the received sequence, compared with the previously obtained PM, and the codeword with the smallest PM is retained. As candidate codewords.

[0061] 3. Enter the combination of flipping 2, 3, 4, 5, ..., until the preset flip order is reached.

[0062] 4. Output the smallest codeword in PM As the result of decoding.

[0063] Figure 2 illustrates the decoding process of the recoded GRAND. As shown in Figure 2, as an example, the codeword obtained by recoding the hard decision sequence of the channel received sequence is (0,1,1,0), with a PM value of 2.5. A flip order of 0 indicates bit flipping. When the flip order is 1, one information bit in the hard decision sequence is flipped, and the flipped sequence is recoded to obtain a codeword, while simultaneously calculating its PM value. Following the above GRAND decoding process, the PM value of each recoded codeword is calculated, and finally, the codeword with the smallest PM value is output as the decoding result.

[0064] Compared to GRAND that flips the codeword, recoded GRAND has the advantages of lower complexity and better performance. However, recoded GRAND involves multiple recodings during the decoding process, necessitating a solution that enables fast recoding.

[0065] In view of this, this application provides an encoding / decoding method that can achieve fast recoding and has superior decoding performance.

[0066] The technical solution provided in this application is described below.

[0067] The technical solutions of this application can be applied to various communication systems, including but not limited to: satellite communication systems, fifth-generation (5G) systems or new radio (NR) systems, long-term evolution (LTE) systems, LTE frequency division duplex (FDD) systems, LTE time division duplex (TDD) systems, etc. The technical solutions provided in this application can also be applied to future communication systems. Furthermore, they can be applied to sidelink (SL) communication, vehicle-to-everything (V2X) communication, machine-to-machine (M2M) communication, machine-type communication (MTC), and Internet of Things (IoT) communication systems, or other communication systems, etc., which are not limited herein.

[0068] The communication system applicable to this application may include one or more transmitters and one or more receivers. Optionally, one of the transmitter and receiver may be a terminal device, and the other may be a network device. Alternatively, both the transmitter and receiver may be terminal devices. The transmitter may also be considered an encoder or encoder device, and the receiver may be considered a decoder or decoder device.

[0069] For example, a terminal device may also be referred to as user equipment (UE), access terminal, user unit, user station, mobile station, mobile station, mobile terminal (MT), remote station, remote terminal, mobile device, user terminal, terminal, wireless communication device, user agent, or user apparatus. In the embodiments of this application, the terminal device may be a device that provides voice and / or data connectivity to a user, and can be used to connect people, objects, and machines, such as a handheld device with wireless connectivity, in-vehicle equipment, etc. The terminal device in the embodiments of this application may be a mobile phone, tablet computer, laptop computer, PDA, mobile internet device (MID), wearable device, virtual reality (VR) device, augmented reality (AR) device, wireless terminal in industrial control, wireless terminal in self-driving, wireless terminal in remote medical surgery, wireless terminal in smart grid, wireless terminal in transportation safety, wireless terminal in smart city, wireless terminal in smart home, etc. Optionally, the UE may be used to act as a base station. For example, the UE may act as a scheduling entity, providing sidelink signals between UEs in V2X or SL, etc.

[0070] In this embodiment, the device for implementing the functions of the terminal device can be the terminal device itself, or any device capable of supporting the terminal device in implementing those functions, such as a chip, a chip system, hardware circuitry, software modules, or a combination of hardware circuitry and software modules. This device can be installed in or used in conjunction with the terminal device. A chip system can consist of chips or include chips and other discrete components. In this embodiment, the terminal device is used as an example to illustrate the device for implementing the functions of the terminal device.

[0071] The network device in this application embodiment may include a device for communicating with a terminal device. This network device may include an access network device or a radio access network device; for example, the network device may be a base station. In this application embodiment, the access network device may refer to a radio access network (RAN) node (or device) that connects the terminal device to the wireless network. A base station can broadly encompass, or be replaced by, various names such as: NodeB, evolved NodeB (eNB), next-generation NodeB (gNB), relay station, access point, transmitting and receiving point (TRP), transmitting point (TP), master station, auxiliary station, motor slide retainer (MSR) node, home base station, network controller, access node, wireless node, access point (AP), transmission node, transceiver node, baseband unit (BBU), remote radio unit (RRU), active antenna unit (AAU), remote radio head (RRH), central unit (CU), distributed unit (DU), radio unit (RU), positioning node, etc. A base station can be a macro base station, micro base station, relay node, donor node, or a combination thereof. A base station can also refer to a communication module, modem, or chip installed within the aforementioned equipment or apparatus. A base station can also be a mobile switching center, equipment performing base station functions in D2D, V2X, and M2M communications, network-side equipment in 6G networks, and equipment performing base station functions in future communication systems. A base station can support networks using the same or different access technologies. Optionally, a RAN node can also be a server, wearable device, vehicle, or in-vehicle equipment. For example, the access network equipment in vehicle-to-everything (V2X) technology can be a roadside unit (RSU). The embodiments of this application do not limit the specific technologies or equipment forms used in the network equipment.

[0072] Base stations can be fixed or mobile. For example, a helicopter or drone can be configured to act as a mobile base station, and one or more cells can move depending on the location of the mobile base station. In other examples, a helicopter or drone can be configured as a device to communicate with another base station.

[0073] In some deployments, the network devices mentioned in the embodiments of this application may be devices including CU, DU, or CU and DU, or devices with control plane CU nodes (central unit-control plane (CU-CP)) and user plane CU nodes (central unit-user plane (CU-UP)) and DU nodes. For example, the network devices may include gNB-CU-CP, gNB-CU-UP, and gNB-DU.

[0074] In some deployments, multiple RAN nodes collaborate to assist terminals in achieving wireless access, with different RAN nodes each implementing some of the base station's functions. For example, RAN nodes can be CUs, DUs, CU-CPs, CU-UPs, or RUs. CUs and DUs can be configured separately or included in the same network element, such as a BBU. RUs can be included in radio frequency equipment or radio frequency units, such as RRUs, AAUs, or RRHs.

[0075] In different systems, CU (or CU-CP and CU-UP), DU, or RU may have different names, but those skilled in the art will understand their meaning. For example, in an open radio access network (ORAN / O-RAN) system, CU can also be called an open CU (open CU, O-CU), and DU can also be called an open DU (open DU, O-DU). CU-CP can also be called O-CU-CP, CU-UP can also be called O-CU-UP, and RU can also be called O-RU. Any of the units among CU (or CU-CP, CU-UP), DU, and RU in this application can be implemented through software modules, hardware modules, or a combination of software modules and hardware modules.

[0076] In this embodiment, the apparatus for implementing the functions of a network device can be a network device itself; it can also be an apparatus capable of supporting the network device in implementing those functions, such as a chip system, hardware circuitry, software module, or a combination of hardware circuitry and software module. This apparatus can be installed in or used in conjunction with the network device. In this embodiment, the example of a network device is used only to illustrate the apparatus for implementing the functions of the network device, and does not constitute a limitation on the solutions described in this embodiment.

[0077] It should be understood that the encoding / decoding scheme provided in this application, also known as the channel coding / decoding scheme, can be used in dedicated network equipment or general-purpose equipment. It can be applied to various network equipment (e.g., base stations) as described above, and also to various terminal equipment as described above. Specifically, the channel coding scheme is mainly implemented through the channel coding unit (e.g., encoder) in these devices; while the channel decoding scheme is mainly implemented through the channel decoding unit (e.g., decoder) in these devices.

[0078] In the embodiments of this application, the functions of the transmitting end or the receiving end can be implemented by application-specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), or by software (e.g., program code in memory), without limitation.

[0079] The encoding / decoding method provided in this application can be applied to various communication scenarios. Figure 3 shows an example of a communication system applicable to the technical solution of this application. The encoding / decoding method provided in this application can be applied to communication between the network device and the terminal device shown in Figure 3, i.e., uplink communication or downlink communication. In this communication scenario, the sending end can be the terminal device in uplink communication or the network device in downlink communication, and the receiving end can be the network device in uplink communication or the terminal device in downlink communication. For example, the technical solution of this application can also be applied to sidelink communication, in which the sending end is the sending terminal device in sidelink communication, and the receiving end is the receiving terminal device in sidelink communication. Furthermore, it can be applied to other communication scenarios without limitation.

[0080] Figure 4 illustrates the basic process of wireless communication. As shown in Figure 4, at the signal transmitting end, the signal source sequentially undergoes source coding, channel coding, and digital modulation before being transmitted. At the signal receiving end, the received signal undergoes digital demodulation, channel decoding, and source decoding before being output to the destination. Among these processes, channel coding and decoding are one of the core technologies in the field of wireless communication.

[0081] The GRAND or recoded GRAND mentioned above can correspond to the channel decoding module in Figure 4. In other words, when the receiver performs channel decoding, if it uses GRAND or recoded GRAND, the parity check matrix required in the GRAND and the parity check matrix required for the recoding operation in the recoded GRAND (corresponding to the first parity check matrix in the following embodiments) can both use the parity check matrix provided in this application. This parity check matrix is ​​a sub-matrix read from a pre-stored master parity check matrix (corresponding to the second parity check matrix in the following embodiments). The master parity check matrix provided in this application will be described in detail below.

[0082] Figure 5 is a schematic flowchart of the encoding / decoding method 500 provided in this application. Steps 510-540 can be performed by an encoding device or by means of a device within the encoding device (e.g., a chip, chip system, or circuit). Steps 550-580 can be performed by a decoding device or by means of a device within the decoding device (e.g., a chip, chip system, or circuit). As an example, one of the encoding and decoding devices is a network device (e.g., a base station), and the other is a terminal device.

[0083] 510. The encoding device encodes the information bit sequence based on the first parity check matrix to obtain the first codeword.

[0084] The first parity-check matrix is ​​a submatrix of the second parity-check matrix, or in other words, the first parity-check matrix is ​​a submatrix read from the second parity-check matrix. In the embodiments of this application, the second parity-check matrix is ​​also called the parent parity-check matrix, denoted as H. m For ease of description, the second parity check matrix can also be referred to as parity check matrix H in the following embodiments. m or H m The verification matrix H will be used. m The submatrix read from the parity check matrix is ​​called the parity check matrix H. m It can be pre-stored on the encoding device.

[0085] Figure 6 shows the verification matrix H provided in this application. m A partial schematic diagram. The parity check matrix H is the parity check matrix H. m The submatrix. The parity matrix H m The element in the i-th row and j-th column is different from the parity check matrix H m The element in the i-th row and k-th column, where k is a variable satisfying the parity check matrix H. m The first i-1 rows and k-th column of the parity check matrix H m The largest column index that is the same in the first i-1 rows and j-th column, where i is an integer greater than 1 and k is an integer less than j.

[0086] In addition, the verification matrix H m It is divided into two parts: the core part and the verification part. The core part is a dense matrix, and the verification part is a lower triangular matrix.

[0087] The parent check matrix H provided in this application m It can support NK≤N m -K m ,K≤K m Nested construction. In other words, reading the parity matrix H m Line 1 to line NK, line K m -K+1 column to Kth columnm The +NK column serves as the parity check matrix H, which can be used for encoding information bit sequences of length K and code length N. Where N... m The maximum value of the length of the codeword corresponding to the parity check matrix H (i.e., the first codeword mentioned above) can also be considered as the parity check matrix H. m The corresponding codeword length. N m -K m This represents the maximum number of check bits.

[0088] Verification matrix H m The first line of the core part is always 1.

[0089] Figure 7 shows the results from the verification matrix H. m A schematic diagram of reading a submatrix from a matrix. As shown in Figure 7, the parity-check matrix H... m Contains N m -K m row and N m The column can be viewed as a parent parity check matrix. The parity check matrix H m K m +1 column to N m The column represents the parity section, which is a lower triangular matrix. The parity matrix H in GRAND decoding, or the parity matrix H required for recoding in GRAND decoding, can be derived from the parity matrix H. m Reading is performed on demand. Specifically, reading can be based on K and N. Here, N is the length of the codeword corresponding to the first parity check matrix, K is the number of information bits, and NK is the number of parity bits, where NK is less than or equal to N. m -K m K is less than or equal to K m As an example, N m =128, K m =96, N=6, K=4, read the parity check matrix H m Rows 1 to 2 and columns 93 to 98 are used as the verification matrix.

[0090] Optionally, the encoding method may also include steps 520 to 530.

[0091] 520. The encoding device acquires the information bit sequence.

[0092] 530. The encoding device outputs the first codeword.

[0093] It should be understood that the first codeword refers to the codeword obtained after encoding the information bit sequence using the first parity check matrix.

[0094] Optionally, the encoding method may also include step 540.

[0095] 540. The encoding device obtains the first check matrix.

[0096] There are several ways for the encoding device to obtain the first parity check matrix. For example, the encoding device may read a submatrix from a second parity check matrix pre-stored in memory as the first parity check matrix; or the processing module of the encoding device (e.g., a processor, circuit, chip, or chip system) may read a submatrix from a second parity check matrix pre-stored in memory as the first parity check matrix. Optionally, the memory may be integrated with the processing module or exist as a separate physical entity, without limitation.

[0097] The above describes the methods used on the encoding side.

[0098] The following explanation uses a decoding device as an example to illustrate the decoding method.

[0099] 550. The decoding device decodes the information to be decoded based on the first parity check matrix to obtain the decoding result.

[0100] The information to be decoded can refer to the channel received sequence or the LLR sequence (as shown in Figure 1 or Figure 2).

[0101] The parity check matrix used by the decoding device in step 560 is the same as the parity check matrix used for encoding on the encoding side; it is the first parity check matrix. For an explanation of the first parity check matrix, please refer to the explanation in step 510, which will not be repeated here.

[0102] Optionally, the decoding method may also include steps 560 to 570.

[0103] 560. The decoding device acquires the information to be decoded.

[0104] 570. The decoding device outputs the decoding result.

[0105] Optionally, the decoding method may also include step 580.

[0106] 580. The decoding device obtains the first verification matrix.

[0107] There are several possible ways for the decoding device to obtain the first parity check matrix. For example, the decoding device receives the first parity check matrix from the encoding device. Alternatively, the decoding device reads the first parity check matrix used for this decoding from a pre-stored second parity check matrix based on an instruction (e.g., an index) from the encoding device. Or, the decoding device reads a corresponding submatrix from a pre-stored second parity check matrix in memory as the first parity check matrix, etc., without limitation.

[0108] In one possible implementation, both the encoding and decoding devices pre-store the parity check matrix H. m It is used for encoding or decoding.

[0109] It should be noted that the sequence numbers of each step in Figure 5 are only used to distinguish different steps in order to clearly describe the technical solution. The number of each step does not mean the order of execution. The execution order of each step should be determined by the internal logic of the encoding / decoding method.

[0110] In the technical solution of this application, the decoding device pre-stores a check matrix H. m To perform GRAND decoding or re-encode GRAND decoding.

[0111] Hard decision processing is performed on the information to be decoded to obtain a hard decision sequence. Then, the obtained first parity-check matrix can be used for recoding and GRAND decoding. The decoding process is illustrated in Figure 2 and will not be repeated here.

[0112] The verification matrix H provided in this application m It supports nested construction, enabling fast encoding under various N and K conditions, with stable decoding performance. When the parity-check matrix H provided in this application... m When applied to decoding, its complexity is lower than that of GRAND. Furthermore, at high code rates, the code spectrum and error correction performance of the proposed scheme are superior to random codes. Random codes refer to the lower triangular portions of the core and check parts being randomly selected from 0 or 1. Moreover, as the code length decreases and the code rate increases, the decoding performance advantage of the check matrix provided in this application becomes even greater.

[0113] In addition, a parity check matrix H is pre-stored. m For each encoding requirement of N and K, it can be derived from this single check matrix H. m The corresponding submatrix is ​​read as the parity check matrix, avoiding the need to design separate parity check matrices for each N and K, thus supporting flexible code length and code rate.

[0114] Verification matrix H m The above characteristics can avoid the verification matrix H m Any two columns of the parity check matrix H are identical. In other words, the parity check matrix H... m Any two columns must be distinct. Since two identical columns will produce a valid codeword with a weight of 2, the design of this application can reduce the number of low-similarity codewords, thereby improving the code spectrum and enhancing performance.

[0115] Figures 8 to 10 are simulation diagrams illustrating the performance of the encoding / decoding method provided in this application. The code rates are R = 4 / 5, R = 7 / 8, and R = 9 / 10, respectively, where R = K / N. As shown in Table 1, the minimum code weight of the random code is 2, while the minimum code weight is 3 when using the parity check matrix H provided in this application. It is evident that the technical solution of this application can improve the code distance and reduce the bit error rate. In Figures 8 to 10, the black curve represents the performance of the random code, and the red curve represents the performance of the encoding / decoding method provided in this application.

[0116] Table 1

[0117] As can be seen from Figures 8 to 10, under the same signal-to-interference-plus-noise ratio (SNR), the proposed scheme has a lower block error ratio (BLER) and better decoding performance.

[0118] The parity check matrix H provided in this application can be used on the decoding side without limiting the decoding method employed by the decoding device. As an example, the decoding device can employ a GRAND or a re-encoded GRAND. For instance, when the decoding side employs a re-encoded GRAND, the decoding device can achieve fast re-encoding using the lower triangular structure of the parity check matrix H. The decoding process can be as follows:

[0119] The S810 decoding device, based on the channel received sequence, i.e., the log likelihood ratio (LLR) sequence, obtains the hard decision sequence z and the confidence sequence α. Wherein, if the LLR... i ≥0,z i =0; if LLR i <0,z i =1. α i =|LLR i For example, the LLR sequence = (-0.5, -1.1, -0.7, 2.1, 0.6, 0.3), z = (1, 1, 1, 0, 0, 0), α = (0.5, 1.1, 0.7, 2.1, 0.6, 0.3).

[0120] S820, decoding device obtains parity matrix H (e.g., from parity matrix H) m The decoding process involves reading the corresponding submatrix (as a parity check matrix H) according to the values ​​of N and K. For a recoded GRAND with a flip order of order, candidate codewords corresponding to the test sequence e are generated sequentially using the parity check matrix H, where the test sequence e is a sequence of length K. The number of 1s in the test sequence e is less than or equal to order. The test sequence e is used to indicate the flip position corresponding to the flip operation during the decoding process based on the recoded GRAND. For example, "1" in the test sequence e indicates that the information bit at the corresponding position is flipped, while "0" in the test sequence e indicates that the bit at the corresponding position is not flipped. Different test sequences e correspond to different flipped information bit sequences, and different flipped information bit sequences are encoded to obtain corresponding candidate codewords. in, x e The corresponding path metric (PM) is:

[0121] For example, if the flip order is 1, then a 1st-order recoded GRAND has 5 test sequences e = (0,0,0,0), (1,0,0,0), (0,1,0,0), (0,0,1,0), and (0,0,0,1). Here, (0,0,0,0) indicates no flip, (1,0,0,0) indicates flipping the first bit corresponding to 1, (0,1,0,0) indicates flipping the second bit corresponding to 1, and so on. The candidate codewords x corresponding to these 5 test sequences e are... e =(1,1,1,0,1,1),(0,1,1,0,0,1),(1,0,1,0,0,0),(1,1,0,0,0,1),(1,1,1,1,0,0), the corresponding metric is PM e =0.9,0.8,1.1,1.0,2.1.

[0122] In the technical solution of this application, when encoding or decoding based on the parity check matrix H, the i-th parity bit is determined according to the information bit sequence, the first i-1 parity bits, and the first to K+i-1 columns of the i-th row of the parity check matrix H, where i is greater than or equal to 1 and less than or equal to NK. Specifically, in, For modulo 2 sum, u j For the j-th information bit, p i For the i-th parity bit, H i,j For the i-th row and j-th column of the parity check matrix H, the encoded codeword is x = (u1, ... u2). K ,p1,…,p N-K For example, the information bit sequence is (0,1,1,0). The codeword x = (0,1,1,0,0,1) is obtained.

[0123] The S830 decoding device compares the PM values ​​of different candidate codewords to measure PM. e The smallest candidate codeword x e As the output of the decoding result, such as PM e The minimum value is 0.8, and the output decoding result is:

[0124] Figures 11-13 are simulation diagrams illustrating the performance of the encoding / decoding methods provided in this application. Applying the parity-check matrix H provided in this application to either a GRAND or a recoded GRAND yields superior decoding performance compared to existing methods. The performance is even better when applied to a recoded GRAND. For example, as shown in the figures, the BLER of the recoded GRAND is smaller and the decoding performance is better at the same SNR. In Figures 11-13, the red curve represents the performance of the scheme applied to a GRAND with an order of 2, and the black curve represents the performance of the scheme applied to a recoded GRAND with an order of 2.

[0125] The encoding and decoding methods provided in this application have been described in detail above. The communication device provided in this application will now be described. It should be understood that the descriptions of the device embodiments correspond to the descriptions of the method embodiments. Therefore, any content not described in detail can be found in the method embodiments above. For the sake of brevity, some content will not be repeated.

[0126] To achieve the functions of the encoding or decoding device in the embodiments of this application, the encoding or decoding device can be implemented through hardware structure, software module, or a combination of hardware structure and software module. No limitation is made. For ease of description, the encoding device and decoding device will be collectively referred to as communication device.

[0127] Figure 14 is a schematic structural diagram of a communication device provided in this application. As shown in Figure 14, the communication device 1000 includes a processing module 1001 and a communication module 1002. The communication device 1000 can be a communication device, or a device applied to a communication device and capable of realizing the corresponding functions of the communication device, such as a chip, chip system, or circuit. Exemplarily, the communication device can be an encoding device or a decoding device as described in the method embodiment.

[0128] The communication module can also be a transceiver module, transceiver, transceiver device, or transceiver apparatus. The processing module can also be a processor, processing board, processing unit, or processing apparatus. Optionally, the communication module is used to perform the sending (or output) operation or receiving (or input) operation of the encoding or decoding device in any of the method embodiments. The device in the communication module that implements the receiving function can be considered a receiving unit, and the device in the communication module that implements the sending function can be considered a sending unit; that is, the communication module includes a receiving unit and a sending unit. The processing module is used to perform the relevant operations / processing implemented internally by the encoding or decoding device in any of the method embodiments.

[0129] For example, if the communication device 1000 corresponds to the encoding device, the communication module 1002 is used to acquire the information bit sequence; the processing module 1001 is used to encode the information bit sequence based on the first parity check matrix to obtain the first codeword; the communication module 1002 can also be used to output the first codeword.

[0130] For example, if the communication device 1000 corresponds to the decoding device, the communication module 1002 can be used to acquire the information to be decoded and send the information to be decoded to the processing module 1001; the processing module 1001 is used to decode the information to be decoded based on the first parity check matrix to obtain the decoding result; the communication module 1002 can also be used to output the decoding result.

[0131] Alternatively, the communication module and / or processing module can be implemented as virtual modules. For example, the processing module can be implemented as a software functional unit or a virtual device, and the communication module can be implemented as a software function or a virtual device. Alternatively, the processing module or communication module can also be implemented as a physical device. For example, the encoding or decoding device can be a chip, such as a system-on-chip (SoC) or hardware circuit. The communication module can be an input / output circuit and / or a communication interface, performing input and output operations; the processing module can be an integrated circuit or logic circuit, etc.

[0132] The module division in this application is illustrative and represents only one logical functional division. In actual implementation, other division methods are possible. Furthermore, the functional modules in the various examples of this application can be integrated into one module, exist as separate physical entities, or be integrated into one module. The integrated modules described above can be implemented in hardware, as software functional modules, or as a combination of hardware and software functional modules; no limitation is imposed.

[0133] As an example, the communication device 1000 can implement the corresponding software in hardware, as shown in Figure 15.

[0134] In another embodiment, the communication device 1000 can also be implemented in hardware.

[0135] Figure 15 is a schematic structural diagram of another communication device provided in this application. The communication device 1100 can be used to implement the communication method described in any of the foregoing method embodiments, specifically an encoding method or a decoding method. The communication device 1100 may include at least one processor 1110. Optionally, the processor 1110 (or processing device) is coupled to a memory, which may be located within the decoding device, or integrated with the processor, or located outside the decoding device. For example, the decoding device 1100 may also include at least one memory 1120. The memory 1120 stores computer programs, instructions, or data necessary for implementing any of the above method embodiments; the processor 1110 may execute the computer programs, instructions, or data stored in the memory 1120 to perform the corresponding functions of the encoding or decoding device in any of the above embodiments.

[0136] Optionally, the decoding device 1100 may further include a communication interface 1130, through which the communication device 1100 can interact with other devices. For example, the communication interface 1130 may be a transceiver, circuit, bus, module, pin, or other type of communication interface. When the decoding device 1100 is a chip or circuit, the communication interface 1130 may also be an input / output circuit, capable of inputting information (or receiving information) and / or outputting information (or sending information). The processor may be an integrated circuit or logic circuit, etc., and the processor can determine the output information based on the input information.

[0137] The coupling in this application refers to indirect coupling or communication connection between devices, units, or modules, which can be electrical, mechanical, or other forms, used for information exchange between devices, units, or modules. The processor 1110 may operate in conjunction with the memory 1120 and the communication interface 1130. This application does not limit the connection medium between the processor 1110, the memory 1120, and the communication interface 1130.

[0138] Figure 16 is a schematic structural diagram of the chip (or chip system) provided in this application. The chip (or chip system) 30 includes a circuit 31 and a communication interface 32. The circuit 31 can be a logic circuit, integrated circuit, etc., and the communication interface 32 can also be called an input / output circuit, input / output interface, interface circuit, etc., and can input information (or receive information) or output information (or send information). The chip 30 can execute the methods executed by the encoding device or decoding device in the various embodiments of this application. Optionally, the chip system can be composed of a chip, or it can include chips and other discrete devices. The chip 30 can be used to execute the encoding method executed by the encoding device in the various embodiments of this application, or to execute the decoding method executed by the decoding device in the various embodiments.

[0139] In addition, this application also provides a computer-readable storage medium storing computer instructions that, when executed on a computer, cause operations and / or processes performed by an encoding or decoding device in the various method embodiments of this application to be executed.

[0140] This application also provides a computer program product, which includes computer program code or instructions. When the computer program code or instructions are run on a computer, the operations and / or processes performed by the encoding or decoding device in the various method embodiments of this application are executed.

[0141] Furthermore, this application also provides a chip including a processor. A memory for storing a computer program is provided independently of the chip, and the processor is used to execute the computer program stored in the memory, so that the operations and / or processes performed by the decoding device in any method embodiment are executed. Further, the chip may also include a communication interface. The communication interface may be an input / output interface or an interface circuit, etc. Further, the chip may also include a memory storing code and / or instructions required for the chip to execute the encoding and / or decoding methods of this application.

[0142] This application provides a communication system including the encoding device and decoding device described in the above method embodiments. As an example, one of the encoding device and the decoding device may be a terminal device and the other a network device; in this example, the communication system includes both a terminal device and a network device.

[0143] The processor in this embodiment has signal processing capabilities and can be a general-purpose processor, digital signal processor, application-specific integrated circuit, field-programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component. It can implement or execute the methods, steps, and logic block diagrams disclosed in this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in this application can be directly manifested as execution by the hardware processor, or executed by a combination of hardware and software modules within the processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above methods.

[0144] In the embodiments of this application, the memory can be volatile memory or non-volatile memory, or it can include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM). It should be noted that the memory used in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0145] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0146] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0147] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0148] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0149] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0150] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A communication method, characterized in that, include: Obtain the information bit sequence; The information bit sequence is encoded based on the first parity check matrix to obtain the first codeword. The first parity check matrix is ​​a submatrix of the second parity check matrix. The element in the i-th row and j-th column of the second parity check matrix is ​​different from the element in the i-th row and k-th column. k is the largest column index less than j that satisfies the condition that the element in the first i-1 rows and k-th column of the second parity check matrix is ​​the same as the element in the first i-1 rows and j-th column of the second parity check matrix. i is an integer greater than 1 and j is an integer. Output the first codeword.

2. A communication method, characterized in that, include: Obtain the information to be decoded; The information to be decoded is decoded based on the first parity check matrix, wherein the first parity check matrix is ​​a submatrix of the second parity check matrix, the element in the i-th row and j-th column of the second parity check matrix is ​​different from the element in the i-th row and k-th column, k is the largest column index less than j that satisfies the condition that the element in the first i-1 rows and k-th column of the second parity check matrix is ​​the same as the element in the first i-1 rows and j-th column of the second parity check matrix, i is an integer greater than 1, and j is an integer; Output the decoding result.

3. The method as described in claim 2, characterized in that, The decoding of the channel received sequence based on the first parity check matrix includes: Based on the first parity check matrix and the guessing random additive noise decoding GRAND method, the information to be decoded is decoded; or, The information to be decoded is decoded based on the first parity check matrix and the GRAND method of recoding guessing random additive noise decoding.

4. The method as described in claim 2 or 3, characterized in that, The decoding of the information to be decoded based on the first parity-check matrix and the recoding guess random additive noise decoding GRAND method includes: Determine the hard decision sequence and the corresponding confidence sequence of the information to be decoded; Based on the hard decision sequence and the first check matrix, candidate codewords are generated sequentially through encoding, and the path metric PM value corresponding to each candidate codeword is calculated based on the confidence sequence. The candidate codeword with the smallest PM value is output as the decoding result.

5. The method according to any one of claims 1 to 4, characterized in that, The second verification matrix includes a core part and a verification part. The core part is a dense matrix, and the verification part is a lower triangular matrix.

6. The method according to any one of claims 1 to 5, characterized in that, The second check matrix is ​​N m -K m row, N m A matrix of columns, the first to the Kth columns of the second parity matrix. m The core component is listed below, and the K of the second verification matrix is... m +1 column to Nth m The column is the verification part, where N m N is the maximum length of the codeword corresponding to the first parity check matrix. m -K m This represents the maximum number of check bits.

7. The method according to any one of claims 1 to 6, characterized in that, The first row of the core part of the second check matrix consists of 1s.

8. The method according to any one of claims 1 to 7, characterized in that, The first row to the NKth row and the Kth row of the second parity check matrix m -K+1 column to Kth column m The +NK column represents the first parity check matrix, where N is the length of the codeword corresponding to the first parity check matrix, K is the number of information bits, and NK is the number of parity bits, where NK is less than or equal to N. m -K m K is less than or equal to K m .

9. The method according to any one of claims 1 to 8, characterized in that, The i-th parity bit is obtained by encoding the information bit sequence, the first i-1 parity bits, and the first parity matrix, where i is greater than or equal to 1 and less than or equal to NK.

10. A communication device, characterized in that, include: The communication module is used to acquire information bit sequences; The processing module is used to encode the information bit sequence based on the first parity check matrix to obtain a first codeword, wherein the first parity check matrix is ​​a submatrix of the second parity check matrix, the element in the i-th row and j-th column of the second parity check matrix is ​​different from the element in the i-th row and k-th column, k is the largest column index less than j that satisfies the condition that the element in the first i-1 rows and k-th column of the second parity check matrix is ​​the same as the element in the first i-1 rows and j-th column of the second parity check matrix, i is an integer greater than 1, and j is an integer; The communication module is also used to output the first codeword.

11. A communication device, characterized in that, include: The communication module is used to acquire the information to be decoded. The processing module is used to decode the information to be decoded based on the first parity check matrix to obtain the decoding result. The first parity check matrix is ​​a submatrix of the second parity check matrix. The element in the i-th row and j-th column of the second parity check matrix is ​​different from the element in the i-th row and k-th column of the first parity check matrix. k is the largest column index less than j that satisfies the condition that the element in the first i-1 rows and k-th column of the second parity check matrix is ​​the same as the element in the first i-1 rows and j-th column of the second parity check matrix. i is an integer greater than 1 and j is an integer. The communication module is also used to output the decoding result.

12. A chip, characterized in that, include: The input interface is used to acquire the information bit sequence; A circuit is used to encode the information bit sequence based on a first parity check matrix to obtain a first codeword, wherein the first parity check matrix is ​​a submatrix of a second parity check matrix, the element in the i-th row and j-th column of the second parity check matrix is ​​different from the element in the i-th row and k-th column, k is the largest column index less than j that satisfies the condition that the element in the first i-1 rows and k-th column of the second parity check matrix is ​​the same as the element in the first i-1 rows and j-th column of the second parity check matrix, i is an integer greater than 1, and j is an integer; The output interface is used to output the first codeword.

13. A chip, characterized in that, include: Input interface, used to obtain the information to be decoded; The circuit is used to decode the information to be decoded based on a first parity check matrix to obtain a decoding result, wherein the first parity check matrix is ​​a submatrix of the second parity check matrix, the element in the i-th row and j-th column of the second parity check matrix is ​​different from the element in the i-th row and k-th column, k is the largest column index less than j that satisfies the condition that the element in the first i-1 rows and k-th column of the second parity check matrix is ​​the same as the element in the first i-1 rows and j-th column of the second parity check matrix, i is an integer greater than 1, and j is an integer; The output interface is used to output the decoding result.

14. A communication device, characterized in that, It includes modules or units for performing the method of any one of claims 1, 5 to 9, or modules or units for performing the method of any one of claims 2 to 9.

15. A communication device, characterized in that, It includes at least one processor, the at least one processor being configured to execute a computer program or instructions stored in a memory to cause the method of any one of claims 1, 5 to 9 to be executed, or to cause the method of any one of claims 2 to 9 to be executed.

16. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program or instructions that, when executed on a communication device, cause the communication device to perform the method as described in any one of claims 1, 5 to 9, or cause the communication device to perform the method as described in any one of claims 2 to 9.

17. A computer program product, characterized in that, The computer program product includes a computer program or instructions for performing the method as described in any one of claims 1, 5 to 9, or includes a computer program or instructions for performing the method as described in any one of claims 2 to 9.

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