Wireless communication system

Abstract

The purpose of the present disclosure is to provide a wireless communication system capable of improving error correction capability. The wireless communication system includes a transmission device and a reception device. The transmission device is configured to execute: processing for generating a concatenated packet by concatenating three or more packets including the same bit string; and processing for transmitting the concatenated packet. The reception device is configured to execute: processing for receiving the concatenated packet; and processing for comparing bit strings among the packets included in the concatenated packet, and correcting non-matching bits on the basis of a majority vote among the packets.

Description

wireless communication system

[0001] The present disclosure relates to wireless communication systems, and more particularly to wireless communication systems suitable for correcting bit errors.

[0002] It is known that radio waves are easily affected by noise, and a typical example is noise interference caused by power transmission lines in the VHF band, UHF band, etc. (see Non-Patent Document 1).

[0003] Conventionally, error control is performed by error correction coding and interleaving to deal with continuous bit errors (also called burst errors) caused by fading or burst interference waves (see Non-Patent Document 2). In some cases, these techniques are combined with packet retransmission control techniques.

[0004] "Noise Interference Caused by Power Lines", Jushin Service Co., Ltd., https: / / www.jushin-s.co.jp / michi / download / 122_k24.pdf "Knowledge Base 4 Group 1 Part 5 Application of Error Correction Technology", Shuji Kubota, Institute of Electronics, Information and Communication Engineers, Ver.1 / 2010.11.9, https: / / www.ieice-hbkb.org / files / 04 / 04gun_01hen_05.pdf

[0005] However, even with the above techniques, bit errors exceeding a certain percentage cannot be corrected completely. Since retransmission of packets means delays, it is desirable to improve error correction capabilities.

[0006] In order to solve the above-mentioned problems, an object of the present disclosure is to provide a wireless communication system capable of improving error correction capabilities.

[0007] An aspect of the present disclosure is preferably a wireless communication system comprising a transmitting device and a receiving device, wherein the transmitting device is configured to perform a concatenation process of generating a concatenated packet by concatenating three or more packets each containing the same bit sequence, and a process of transmitting the concatenated packet, and the receiving device is configured to perform a process of receiving the concatenated packet, and a comparison and correction process of comparing the bit sequences between the packets included in the concatenated packet and correcting bits whose values ​​do not match by majority vote between the packets.

[0008] In the wireless communication system of the present disclosure, error correction is performed by majority vote, thereby improving the correction capability, and therefore it is possible to provide a wireless communication system that can improve the error correction capability.

[0009] 1 is a configuration example of a wireless communication system according to a first embodiment; FIG. 2 is a diagram illustrating hardware configurations of a transmitting device and a receiving device according to the first embodiment; FIG. 3 is a diagram illustrating processing performed by a replica circuit; FIG. 4 is a diagram illustrating concatenation processing performed by a concatenation circuit; FIG. 5 is a diagram illustrating interleaving performed by a concatenation circuit; FIG. 6 is a diagram illustrating bit errors that occur when transmitting concatenated packets; FIG. 7 is a diagram illustrating processing performed by a restoration circuit; FIG. 8 is a diagram illustrating forward error correction decoding performed by a restoration circuit; FIG. 9 is a diagram illustrating comparison and correction processing performed by a comparison circuit; FIG. 10 is a flowchart illustrating processing performed by CPUs of a transmitting device and a receiving device according to the first embodiment; FIG. 11 is a diagram illustrating processing performed by a replica circuit according to a second embodiment; FIG. 12 is a diagram illustrating concatenation processing performed by a concatenation circuit according to the second embodiment; FIG. 13 is a diagram illustrating interleaving performed by a concatenation circuit according to the second embodiment; FIG. 14 is a diagram illustrating forward error correction decoding performed by a restoration circuit according to the second embodiment; FIG. 15 is a diagram illustrating processing performed by a restoration circuit according to the second embodiment; FIG. 16 is a diagram illustrating comparison and correction processing performed by a comparison circuit according to the second embodiment; FIG. 17 is a flowchart illustrating processing performed by CPUs of a transmitting device and a receiving device according to the second embodiment;

[0010] Embodiments of the present disclosure will be described with reference to the drawings. The same or corresponding components will be designated by the same reference numerals, and repeated description may be omitted.

[0011] 1 shows an example of the configuration of a wireless communication system 100 according to embodiment 1. The wireless communication system 100 includes a transmitting device 110 and a receiving device 120 that perform wireless communication.

[0012] First, the functions of the transmitting device 110 will be described. The interface circuit 111 receives user signals to be transmitted from an upper layer or another device. The framing circuit 112 functions as a buffer that stores a certain number of user signals from the interface circuit 111. The framing circuit 112 divides the user signals into bits to generate multiple payloads 2. The framing circuit 112 also calculates an FCS (Frame Check Sequence) 3 for each of the multiple payloads 2. The framing circuit 112 generates multiple packets by adding a header 1 based on the communication protocol to the front of each payload 2 and adding the calculated FCS 3 to the end.

[0013] The duplication circuit 113 duplicates the packet 10 received from the framing circuit 112. The duplication circuit 113 combines the duplicated packet 10 with the original packet 10 to generate three or more packets 10 containing the same bit sequence. For the sake of explanation, it is assumed below that three packets 10-1, 10-2, and 10-3 are generated.

[0014] The concatenation circuit 114 receives the packets 10-1, 10-2, and 10-3 from the duplication circuit 113. The concatenation circuit 114 executes a concatenation process to concatenate the packets 10-1, 10-2, and 10-3 into one concatenated packet 30. Furthermore, the concatenation circuit 114 performs interleaving on the concatenated packet 30 to rearrange the order of bits.

[0015] The modulation circuit 115 modulates the interleaved concatenated packet 30 after adding a code for forward error correction (FEC).

[0016] The RF transmission circuit 116 converts the concatenated packet 30 received from the modulation circuit 115 into a radio signal suitable for transmission. The RF transmission circuit 116 amplifies the radio signal, removes unnecessary frequency components from the radio signal, and then transmits the signal to the antenna 117.

[0017] The antenna 117 transmits the radio signal to the receiving device 120 .

[0018] The control circuit 118 controls each circuit of the transmitting device 110. When the control circuit 118 receives an alarm from the modulation circuit 115 and the RF transmitting circuit 116, it performs necessary control on the source of the alarm. The control circuit 118 also monitors and controls each other with the control circuit 128 of the receiving device 120, and exchanges information necessary for synchronizing the transmission and reception of radio signals.

[0019] Next, a description will be given of the functions of the receiving device 120. The antenna 121 receives a radio signal from the transmitting device 110. The RF receiving circuit 122 amplifies and performs automatic gain control (AGC) on the received signal.

[0020] The demodulation circuit 123 demodulates the concatenated packet 30 contained in the received signal, and also monitors the BER based on the received signal.

[0021] The restoration circuit 124 deinterleaves the concatenated packet 30 received from the demodulation circuit 123, and restores the original order of the bits that were rearranged by the transmitting device 110. Furthermore, the restoration circuit 124 restores packets 10-1, 10-2, and 10-3 from the deinterleaved concatenated packet 30. Furthermore, the restoration circuit 124 performs forward error correction decoding on each of the packets 10-1, 10-2, and 10-3.

[0022] The comparison circuit 125 corrects bit error 5 that could not be completely corrected by the restoration circuit 124. Specifically, the comparison circuit 125 compares the bit strings of packets 10-1, 10-2, and 10-3, each of which has been forward error correction decoded, and performs a comparison and correction process to correct bits whose values ​​do not match by majority vote among the packets 10. The comparison circuit 125 sends packet 50 obtained by performing the comparison and correction process to the deframing circuit 126 as the final error correction result.

[0023] The deframing circuit 126 functions as a buffer that stores a certain number of packets 50 from the comparison circuit 125. The deframing circuit 126 arranges the stored packets 50 in the order in which they were generated by the transmitting device 110, and reassembles the user signal.

[0024] The interface circuit 127 outputs the user signal to an upper layer or other device.

[0025] The control circuit 128 controls each circuit of the receiving device 120. When the control circuit 128 receives an alarm from the demodulation circuit 123 and the RF receiving circuit 122, the control circuit 128 performs necessary control on the source of the alarm.

[0026] 2 is a diagram showing the hardware configuration of the transmitting device 110 and the receiving device 120 according to the first embodiment. The processing performed by the transmitting device 110 and the receiving device 120 may be executed by a program using a computer having a CPU and memory and storing a wireless communication program in the memory. Alternatively, the processing may be executed by a program using an integrated circuit such as an FPGA (Field Programmable Gate Array). The wireless communication program may be provided by being recorded on a storage medium or provided via a network.

[0027] The transmitting device 110 and the receiving device 120 have computer functions, with an input unit 40, an output unit 41, a communication unit 42, a CPU (Central Processing Unit, also called a processor) 43, a memory 44, and an HDD (Hard Disk Drive) 45 connected via a bus 46. The transmitting device 110 and the receiving device 120 are also capable of inputting and outputting data to and from a computer-readable storage medium 47.

[0028] The input unit 40 is, for example, a keyboard and a mouse, etc. The output unit 41 is, for example, a display device such as a display.

[0029] The communication unit 42 is a communication interface that enables the transmitting device 110 and the receiving device 120 to communicate with each other, for example.

[0030] The memory 44 may be, for example, a volatile or non-volatile semiconductor memory such as a RAM, a ROM, or a flash memory, or a magnetic disk, a flexible disk, an optical disk, a DVD, or the like.

[0031] The CPU 43 controls each component of the transmitting device 110 or the receiving device 120 and performs predetermined processing, etc. The memory 44 and the HDD 45 are storage devices that store, for example, data of a wireless communication program, etc.

[0032] The storage medium 47 is capable of storing a wireless communication program or the like that causes the transmitting device 110 and the receiving device 120 to execute the functions of the transmitting device 110 and the receiving device 120. The storage medium 47 is a USB (Universal Serial Bus) memory, a CD-ROM (Compact Disc Read Only Memory), or the like.

[0033] The architecture configuring the transmitting device 110 and the receiving device 120 is not limited to the example shown in the figure.

[0034] 3 to 5 are diagrams illustrating the processing executed by the transmitting device 110. Fig. 3 is a diagram illustrating the processing executed by the duplication circuit 113. The duplication circuit 113 collectively duplicates the header 1, payload 2, and FCS 3 contained in the original packet 10.

[0035] 4 is a diagram illustrating the concatenation process executed by the concatenation circuit 114. The concatenation circuit 114 concatenates the payloads 2 of the packets 10-1, 10-2, and 10-3 into one. Furthermore, the concatenation circuit 114 adds one header 1 to the front of the concatenated payload 2 and one FCS 3 to the end, thereby generating a concatenated packet 30. Because the header 1 and FCS 3 can be duplicated on the receiving side, adding only the minimum number necessary can reduce the load associated with creating the concatenated packet 30.

[0036] 5 is a diagram illustrating the interleaving performed by the concatenation circuit 114. Interleaving changes the order of the bits in the header 1, FCS 3, and three payloads 2 contained in the concatenated packet 30. This disperses burst errors that occur during transmission and turns them into random errors, preventing consecutive errors. This makes forward error correction decoding easier on the receiving side.

[0037] 6 is a diagram illustrating a bit error 5 that occurs during transmission of a concatenated packet 30. A bit error 5 occurs in the concatenated packet 30 transmitted from the transmitting device 110 due to the influence of an interference wave.

[0038] 7 to 9 are diagrams illustrating the processing executed by the receiving device 120. FIG. 7 is a diagram illustrating the processing executed by the restoration circuit 124. The restoration circuit 124 decomposes the deinterleaved concatenated packet 30 to extract three payloads 2. Furthermore, the restoration circuit 124 duplicates the header 1 and FCS 3 included in the concatenated packet 30 to match the number of packets 10 to be restored. The restoration circuit 124 restores packets 10-1, 10-2, and 10-3 by adding the duplicated header 1 and FCS 3 to each of the extracted payloads 2.

[0039] 8 is a diagram illustrating forward error correction decoding performed by the restoration circuit 124. The restoration circuit 124 decodes the forward error correction codes assigned to each of the packets 10-1, 10-2, and 10-3, and corrects the bit error 5. The FCS3 of each packet 10 is used to detect the bit error 5. The error correction by the restoration circuit 124 reduces the bit error 5 in each packet 10. However, as shown in this figure, there are cases where the bit error 5 remains and cannot be completely corrected.

[0040] 9 is a diagram illustrating the comparison and correction process performed by the comparison circuit 125. Here, the bit strings of packets 10-1, 10-2, and 10-3, each of which has been forward error correction decoded, are shown. The comparison circuit 125 compares the bit strings of packets 10-1, 10-2, and 10-3. The comparison circuit 125 determines that bits whose values ​​match among the three packets 10 are not in error.

[0041] On the other hand, the comparator circuit 125 determines that a bit whose value does not match among the three packets 10 is an error. In this case, the comparator circuit 125 determines the corrected bit value by majority vote of the bit values ​​indicated by the three packets 10. For example, if the bit values ​​in the three packets 10 are 0, 0, and 1, respectively, the comparator circuit 125 will adopt 0, which accounts for the majority, as the corrected bit value. This is based on the probabilistic grounds that the probability of a bit error 5 occurring simultaneously in the majority of packets 10 is low.

[0042] The comparison circuit 125 performs comparison and correction processing to generate a packet 50 which is the final error correction result.

[0043] 10 is a flowchart illustrating processing executed by the CPU 43 of the transmitting device 110 and the receiving device 120 according to the first embodiment. The CPU 43 reads a wireless communication program stored in the memory 44 or the HDD 45 and executes the following processing.

[0044] First, the transmitting device 110 combines the duplicated packet 10 with the original packet 10 to generate three or more packets 10 containing the same bit sequence (step S01). Next, the transmitting device 110 performs a concatenation process to generate a concatenated packet 30 by concatenating packets 10-1, 10-2, and 10-3 into one (step S02). The transmitting device 110 then interleaves the concatenated packet 30 (step S03). The transmitting device 110 then transmits the concatenated packet 30 to the receiving device 120 (step S04).

[0045] Next, receiving device 120 receives concatenated packet 30 (step S05). Next, receiving device 120 deinterleaves concatenated packet 30 (step S06). Furthermore, receiving device 120 restores packets 10-1, 10-2, and 10-3 from concatenated packet 30 (step S07). Furthermore, receiving device 120 performs forward error correction decoding on each of packets 10-1, 10-2, and 10-3 (step S08).

[0046] Furthermore, the receiving device 120 performs a comparison and correction process on the packets 10-1, 10-2, and 10-3, and detects bit error 5 by comparing the bit strings among the three packets 10. If bit error 5 is detected, the receiving device 120 determines the corrected bit value by majority vote of the bit values ​​indicated by the three packets 10 (step S09).

[0047] In this way, in the wireless communication system 100 of this embodiment, the receiving device 120 performs error correction by majority vote, thereby improving the correction capability.

[0048] Second Embodiment The following describes changes from the first embodiment.

[0049] 11 to 13 are diagrams illustrating the processing executed by the transmitting device 110 according to the second embodiment. Fig. 11 is a diagram illustrating the processing executed by the duplication circuit 113 according to the second embodiment. In this embodiment, the original packet 10 includes a header 1 and a payload 2, but does not include an FCS 3. Therefore, the packet 10 duplicated by the duplication circuit 113 does not include an FCS 3 either.

[0050] 12 is a diagram illustrating the concatenation process executed by the concatenation circuit 114 in the second embodiment. As in the first embodiment, the concatenation circuit 114 concatenates the payloads 2 of the packets 10-1, 10-2, and 10-3, and adds a header 1 to the front of the concatenated payload 2. In this embodiment, an FCS 31 is calculated for the concatenated payload 2. The concatenation circuit 114 generates a concatenated packet 30 by adding the calculated FCS 31 to the end of the concatenated payload 2.

[0051] 13 is a diagram for explaining interleaving performed by the concatenation circuit 114 of embodiment 2. As in embodiment 1, the concatenation circuit 114 performs interleaving on the concatenated packet 30.

[0052] 14 to 16 are diagrams illustrating the processing executed by the receiving device 120 according to the second embodiment. Fig. 14 is a diagram illustrating forward error correction decoding executed by the restoration circuit 124 according to the second embodiment. The restoration circuit 124 performs forward error correction decoding on the concatenated packets 30 that have been deinterleaved. By performing error correction on the concatenated packets 30, the packet constraint length can be made longer than in the first embodiment, thereby improving the correction capability.

[0053] 15 is a diagram illustrating the processing executed by the restoration circuit 124 according to the second embodiment. The restoration circuit 124 restores packets 10-1, 10-2, and 10-3 from the forward error correction decoded concatenated packet 30. The FCS 31 is necessary for forward error correction decoding, but is not required for processing after decoding. Therefore, the FCS 31 is omitted from the restored packet 10.

[0054] 16 is a diagram illustrating the comparison and correction process executed by the comparison circuit 125 of embodiment 2. As in embodiment 1, the comparison circuit 125 detects bit error 5 by comparing bit strings between three packets 10. When bit error 5 is detected, the comparison circuit 125 determines the corrected bit value by majority vote of the bit values ​​indicated by the three packets 10.

[0055] 17 is a flowchart illustrating the processing executed by the CPU 43 of the transmitting device 110 and the receiving device 120 according to the second embodiment. The processing from steps S01 to S04 executed by the transmitting device 110 is the same as that in the first embodiment, and therefore the description thereof will be omitted.

[0056] After step S04, the receiving device 120 receives the concatenated packet 30 (step S05). Next, the receiving device 120 deinterleaves the concatenated packet 30 (step S06). Furthermore, the receiving device 120 performs forward error correction decoding on the concatenated packet 30 (step S07). Furthermore, the receiving device 120 restores packets 10-1, 10-2, and 10-3 from the concatenated packet 30 (step S08).

[0057] Furthermore, the receiving device 120 performs a comparison and correction process on the packets 10-1, 10-2, and 10-3 (step S09).

[0058] As described above, the present disclosure can provide a wireless communication system 100 that can improve error correction capabilities.

[0059] <Modification 1> In the above description, it has been explained that the transmitting device 110 concatenates three packets 10. It has also been explained that the receiving device 120 performs comparison and correction processing using three packets 10. However, the number of packets 10 to be concatenated and the number of packets 10 used for majority voting do not have to be limited to three, and may be more than three. In this case, too, the effects described in the first and second embodiments can be obtained.

[0060] <Modification 2> In the above description, it has been explained that the receiving device 120 performs a comparison and correction process on packets 10-1, 10-2, and 10-3 that have been forward error correction decoded. By combining forward error correction decoding and comparison and correction, it is possible to improve the error correction capability compared to when comparison and correction is performed alone. However, comparison and correction does not necessarily have to be performed on packets 10 that have been forward error correction decoded. Comparison and correction may be performed alone, or comparison and correction may be performed before forward error correction decoding. In this case, the same effects as those of the first and second embodiments can be obtained.

[0061] <Variation 3> In the above description, the transmitting device 110 generates the concatenated packet 30 by adding one header 1 to the front of the concatenated payloads 2 and one FCS 3 to the end. However, the codes added to the concatenated payloads 2 are not limited to the header 1 and FCS 3, and may be any code necessary for the receiving device 120 to restore the packet 10 from the concatenated packet 30. Furthermore, the number of codes added to the concatenated packet 30 does not have to be one, and may be multiple.

[0062] <Modification 4> In the above description, the transmitting device 110 concatenates the payloads 2 of the packets 10-1, 10-2, and 10-3 into one. However, the concatenated packet 30 may be generated by simply concatenating the packets 10-1, 10-2, and 10-3.

[0063] The present disclosure is not limited to the above-described embodiments, and various modifications can be made in the implementation stage without departing from the spirit of the present disclosure. Furthermore, the embodiments and modifications may be implemented in appropriate combinations, in which case the combined effects can be obtained.

[0064] 1 Header, 2 Payload, 3 Frame Check Sequence (FCS), 10 Packet, 30 Concatenated Packet, 40 Input Unit, 41 Output Unit, 42 Communication Unit, 43 CPU, 44 Memory, 46 Bus, 47 Storage Medium, 50 Packet, 100 Wireless Communication System, 110 Transmitter, 111 Interface Circuit, 112 Framing Circuit, 113 Replicator Circuit, 114 Concatenator Circuit, 115 Modulator Circuit, 116 RF Transmitter Circuit, 117 Antenna, 118 Control Circuit, 120 Receiver, 121 Antenna, 122 RF Receiver Circuit, 123 Demodulator Circuit, 124 Restoration Circuit, 125 Comparison Circuit, 126 Deframing Circuit, 127 Interface Circuit, 128 Control Circuit

Claims

1. A wireless communication system comprising a transmitting device and a receiving device, wherein the transmitting device is configured to perform a concatenation process of generating a concatenated packet by concatenating three or more packets each containing the same bit sequence, and a process of transmitting the concatenated packet, and the receiving device is configured to perform a process of receiving the concatenated packet, and a comparison and correction process of comparing the bit sequences of the packets included in the concatenated packet and correcting bits whose values ​​do not match by majority vote between the packets.

2. The wireless communication system according to claim 1, wherein the receiving device further performs a process of performing forward error correction decoding on the concatenated packet or the packet restored from the concatenated packet, and the forward error correction decoded packet is used for the comparison and correction process.

3. The wireless communication system of claim 1 or 2, wherein the concatenation process further includes a process of assigning to the concatenated packet a code required for the receiving device to restore the packet from the concatenated packet, and the receiving device further executes a process of duplicating the code to match the number of packets to be restored, a process of disassembling the concatenated packet to extract packets that are the basis of the packets, and a process of restoring the packets by assigning the copied code to the basis packets.

4. A wireless communication system as described in claim 1 or 2, wherein the transmitting device further performs a process of interleaving the concatenated packets, and the receiving device further performs a process of deinterleaving the concatenated packets to restore the interleaving before the comparison and correction process.

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