Display panel, display device, and method for manufacturing display panel

Abstract

A display panel, a display device, and a method for manufacturing a display panel. The display panel comprises: an array substrate (1) and an opposite substrate (2) which are opposingly arranged; a sealant (3) located between the array substrate (1) and the opposite substrate (2) and located in a non-display area (BB); and a conductive portion (4), comprising a first conductive portion (41) and a second conductive portion (42), wherein the first conductive portion (41) is located between the array substrate (1) and the opposite substrate (2) and located in a bonding area (DP); part of the first conductive portion (41) overlaps the sealant (3), and the remaining part extends to an area outside the sealant (3) and facing one side of a display area (AA); the second conductive portion (42) is located between the array substrate (1) and the opposite substrate (2) and located in a bonding opposite area (DPO); part of the second conductive portion (42) overlaps the sealant (3), and the remaining part extends to an area outside the sealant (3) and facing away from one side of the display area (AA); and the conductive portion (4) is configured to conduct electrical signals between the array substrate (1) and the opposite substrate (2).

Description

Display panel, display device, and method of manufacturing display panel Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display panel, a display device, and a method for manufacturing the display panel. Background Technology

[0002] The principle of Vertical Alignment (VA) display technology is that the electrodes of the array substrate and the electrodes of the opposing substrate are energized to form an upper and lower voltage field, which drives the liquid crystal in the liquid crystal cell to rotate. Different rotation angles of the liquid crystal result in different light transmission intensities, which control the display. The sealant acts as an encapsulation within the liquid crystal cell, sealing the array substrate and the opposing substrate. At the same time, the conductive particles (e.g., gold balls) in the sealant also facilitate the conduction of the upper and lower electrodes.

[0003] Summary of the Invention

[0004] This disclosure provides a display panel, a display device, and a method for manufacturing the display panel. The display panel has a display area and a non-display area located around the display area; the non-display area includes: a bonding area located on one side of the display area, and a bonding opposite area located on the other side of the display area and opposite to the bonding area, wherein the display panel includes:

[0005] An array substrate and a facing substrate arranged opposite to each other;

[0006] The sealing adhesive is located between the array substrate and the opposing substrate, and is located in the non-display area;

[0007] The conductive portion includes: a first conductive portion and a second conductive portion; the first conductive portion is located between the array substrate and the opposing substrate, and is located in the bonding region, wherein the first conductive portion partially overlaps with the sealant, and partially extends beyond the sealant and faces the display area; the second conductive portion is located between the array substrate and the opposing substrate, and is located in the bonding opposite region, wherein the second conductive portion partially overlaps with the sealant, and partially extends beyond the sealant and is away from the display area; the conductive portion is configured to conduct electrical signals between the array substrate and the opposing substrate.

[0008] In one possible implementation, the sealing adhesive includes: a first sealing adhesive edge and a second sealing adhesive edge; the minimum distance between the first sealing adhesive edge and the display area is less than the minimum distance between the second sealing adhesive edge and the display area;

[0009] The first conductive part overlaps with the edge of the first sealing adhesive, and the second conductive part overlaps with the edge of the second sealing adhesive.

[0010] In one possible implementation, the display panel includes: a first panel outer edge and a second panel outer edge; the first panel outer edge and the bonding area are located on the same side of the display area, and the second panel outer edge and the bonding opposite side area are located on the same side of the display area;

[0011] The minimum distance between the sealing adhesive and the first outer edge is less than the minimum distance between the sealing adhesive and the second outer edge.

[0012] In one possible implementation, the display panel further includes: a first blocking portion and a second blocking portion;

[0013] The first barrier portion is located between the first conductive portion and the display area; the second barrier portion is located between the second conductive portion and the outer edge of the second panel.

[0014] In one possible implementation, the first blocking portion includes: a first sub-blocking portion and a second sub-blocking portion; the extending direction of the first sub-blocking portion is the same as the extending direction of the outer edge of the first conductive portion toward the display area; the second sub-blocking portion is connected to the end of the first sub-blocking portion and is bent toward the first conductive portion.

[0015] The second blocking portion includes: a third sub-blocking portion and a fourth sub-blocking portion; the extending direction of the third sub-blocking portion is the same as the extending direction of the outer edge of the second conductive portion toward the display area; the fourth sub-blocking portion is connected to the end of the third sub-blocking portion and is bent toward the side of the second conductive portion.

[0016] In one possible implementation, the display panel includes a plurality of first conductive portions, and / or a plurality of second conductive portions;

[0017] The plurality of first conductive parts are all located in the bonding area and are arranged sequentially along the extension direction of the bonding area; the plurality of second conductive parts are all located in the bonding opposite side area and are arranged sequentially along the extension direction of the bonding opposite side area.

[0018] In one possible implementation, the first conductive portion is strip-shaped and extends along the extension direction of the bonding region; the second conductive portion is strip-shaped and extends along the extension direction of the bonding opposite side region.

[0019] In one possible implementation, the array substrate includes: a first substrate and a plurality of first common patterns;

[0020] The orthographic projection of the first common electrode pattern onto the first substrate at least partially overlaps with the orthographic projection of the conductive portion onto the first substrate.

[0021] In one possible implementation, the outer contour of the first common pattern is a pentagon, hexagon, or octagon.

[0022] In one possible implementation, the first common pattern includes: a peripheral wiring portion, a plurality of first wiring portions located inside the peripheral wiring portion, and a plurality of second wiring portions; the first wiring portions and the second wiring portions intersect to form a plurality of first opening areas;

[0023] At least two of the plurality of first opening regions have different areas.

[0024] In one possible implementation, at least one of the peripheral wiring portion, the first wiring portion, and the second wiring portion has a plurality of second opening areas; the area of ​​the second opening area is smaller than the area of ​​the first opening area.

[0025] In one possible implementation, the array substrate includes: a transfer electrode located on the side of the first common pattern facing the opposing substrate, and a first insulating layer located between the transfer electrode and the first common pattern; the transfer electrode is electrically connected to the conductive portion.

[0026] The first insulating layer has a first via, and the first common pattern is electrically connected to the adapter electrode through the first via.

[0027] In one possible implementation, the first common pattern corresponds to the first via, and the area of ​​the first via is 50% to 90% of the area of ​​the first common pattern.

[0028] In one possible implementation, the first via includes: a plurality of first sub-vias; the orthographic projections of the plurality of first sub-vias of the same first via onto the first substrate are all located within the orthographic projection of the first common pattern onto the first substrate.

[0029] In one possible implementation, the first via includes a second sub-via and a plurality of third sub-vias; the size of the third sub-via is smaller than the size of the second sub-via; the first common pattern portion overlaps with the sealing adhesive, and a portion does not overlap with the sealing adhesive;

[0030] The second sub-via's orthographic projection onto the first substrate is located in the area where the first common pattern overlaps with the sealant; the third sub-via's orthographic projection onto the first substrate is located in the area outside the area where the first common pattern overlaps with the sealant.

[0031] In one possible implementation, the array substrate includes a first common electrode trace; the opposing substrate includes a second common electrode trace; the first common electrode trace and the second common electrode trace are electrically connected through the conductive portion.

[0032] The first common electrode trace includes the first common pattern.

[0033] In one possible implementation, the orthographic projection of the first common pattern onto the first substrate does not overlap with the orthographic projection of the first common electrode trace onto the substrate; and the orthographic projection of the first via onto the substrate overlaps with the orthographic projection of the first common electrode trace onto the first substrate.

[0034] The first common pattern is electrically connected to the first common electrode trace via the first via through the adapter electrode.

[0035] In one possible implementation, the display panel further includes: a first non-display area located outside the display area and connecting the binding area and the binding opposite side area;

[0036] Of the binding area, the binding opposite area, and the first non-display area, only the binding area and the binding opposite area are provided with the conductive part.

[0037] In one possible implementation, the first non-display area includes: a gate driving unit, and a gate driving signal trace located on the side of the gate driving unit away from the display area;

[0038] In the first non-display area, the sealing adhesive overlaps with at least a portion of the gate drive signal traces.

[0039] This disclosure also provides a display device, which includes: the display panel as provided in this disclosure.

[0040] This disclosure also provides a method for manufacturing a display panel as described in this disclosure, wherein the manufacturing method includes:

[0041] A sealing adhesive is applied around the display area of ​​the opposing substrate and / or the array substrate;

[0042] A first conductive portion is formed in the bonding area, and the first conductive portion partially overlaps with the sealant, and partially extends beyond the sealant and faces the display area.

[0043] A second conductive portion is formed in the bonding opposite area, and the second conductive portion partially overlaps with the sealant, and partially extends beyond the sealant and away from the display area.

[0044] The opposing substrate and the array substrate are pressed together to bond the array substrate and the opposing substrate. Attached Figure Description

[0045] Figure 1A is one of the top views of a display panel provided in an embodiment of this disclosure;

[0046] Figure 1B is one of the enlarged partial schematic diagrams of the binding area DP in Figure 1A;

[0047] Figure 1C is one of the enlarged schematic diagrams of the DPO binding on the contralateral region in Figure 1A;

[0048] Figure 1D is a second enlarged schematic diagram of the binding area DP in Figure 1A;

[0049] Figure 1E is a second enlarged schematic diagram of the DPO binding on the contralateral region in Figure 1A;

[0050] Figure 2 is a second top view of the display panel provided in an embodiment of this disclosure;

[0051] Figure 3 is a top view of the display panel provided in an embodiment of this disclosure;

[0052] Figure 4 is a schematic diagram of one of the first public patterns provided in the embodiments of this disclosure;

[0053] Figure 5 is a second schematic diagram of the first public pattern provided in the embodiments of this disclosure;

[0054] Figure 6 is a schematic diagram of the third type of the first public pattern provided in the embodiments of this disclosure;

[0055] Figure 7A is one of the schematic cross-sectional views of a display panel provided in an embodiment of this disclosure;

[0056] Figure 7B is a top view corresponding to Figure 7A;

[0057] Figure 8A is a second schematic cross-sectional view of the display panel provided in an embodiment of this disclosure;

[0058] Figure 8B is a top view corresponding to Figure 8A;

[0059] Figure 9A is a third schematic cross-sectional view of the display panel provided in an embodiment of this disclosure;

[0060] Figure 9B is a top view corresponding to Figure 9A;

[0061] Figure 10 is a schematic diagram of the routing of the first common electrode provided in an embodiment of this disclosure;

[0062] Figure 11 is a schematic diagram showing the position of another first via and a first common pattern provided in an embodiment of this disclosure;

[0063] Figure 12 is a partial schematic diagram of the first non-display area BB1;

[0064] Figure 13 is a schematic diagram of the display panel manufacturing process provided in the embodiments of this disclosure. Detailed Implementation

[0065] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure. Implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into one or more forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0066] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0067] As used herein, “approximately” or “substantially the same” includes the stated value and means within an acceptable range of deviation from the specific value, as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., limitations of the measurement system). For example, “substantially the same” may mean a difference relative to the stated value within one or more standard deviations, or within ±30%, 20%, 10%, or 5%. In this specification, “substantially the same” may mean a difference of less than 10%.

[0068] In the accompanying drawings, the thicknesses of layers, films, panels, regions, etc., are enlarged for clarity. Exemplary embodiments are described herein with reference to cross-sectional views that are schematic diagrams of idealized embodiments. Thus, deviations from the shapes shown in the drawings will be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as limited to the specific shapes of the regions shown herein, but rather include deviations in shape caused, for example, by manufacturing processes. For example, regions illustrated or described as flat may typically have rough and / or non-linear characteristics. Furthermore, sharp corners illustrated may be rounded. Thus, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the regions, nor are they intended to limit the scope of the claims.

[0069] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the direction in which the constituent elements are described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0070] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection or an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate.

[0071] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on the "elements that have a certain electrical function," as long as they enable the transmission of electrical signals between the connected components. Examples of "elements that have a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with one or more functions.

[0072] In this specification, "parallel" refers to a state in which two straight lines form an angle of -10° or more and less than 10°, and therefore can include a state in which the angle is -5° or more and less than 5°. Similarly, "perpendicular" refers to a state in which two straight lines form an angle of 80° or more and less than 100°, and therefore can include a state in which the angle is 85° or more and less than 95°.

[0073] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0074] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0075] To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted.

[0076] Currently, VA display products typically place the conductive particles (e.g., gold balls) of the conductive array substrate and the opposing substrate near one side of the display area or the edge of the display panel. For example, in the non-display area surrounding the entire display area of ​​the display panel, the conductive particles are all placed near one side of the display panel edge. This placement method causes the sealant to overflow beyond the edge of the display panel during the lamination of the array substrate and the opposing substrate, due to the small gap between the sealant and the outer edge of the display panel. This is detrimental to the smooth cutting process of the display panel and the subsequent assembly of the display panel with other structures. In addition, existing methods that fill the sealant entirely with conductive particles place it away from the signal lines in the non-display area to prevent the conductive particles from electrically connecting with the signal lines in the non-display area of ​​the display panel, resulting in a larger display panel bezel.

[0077] Referring to Figures 1A-1C and 7A, this disclosure provides a display panel having a display area AA and a non-display area BB located around the display area AA. The non-display area BB includes a bonding area DP located on one side of the display area AA and a bonding opposite area DPO located on the other side of the display area AA and opposite to the bonding area DP. The bonding area DP includes multiple bonding pads that can be used for bonding and electrical connection with a circuit board. The display panel includes:

[0078] Array substrate 1 and opposing substrate 2 are arranged opposite to each other;

[0079] The sealing adhesive 3 is located between the array substrate 1 and the opposing substrate 2, and is located in the non-display area BB;

[0080] The conductive portion 4 includes a first conductive portion 41 and a second conductive portion 42. The first conductive portion 41 is located between the array substrate 1 and the opposing substrate 2, and is located in the bonding region DP. The first conductive portion 41 partially overlaps with the sealant 3 and partially extends beyond the sealant 3 and faces the display region AA. The second conductive portion 42 is located between the array substrate 1 and the opposing substrate 2, and is located in the bonding opposite region DPO. The second conductive portion 42 partially overlaps with the sealant 3 and partially extends beyond the sealant 3 and faces away from the display region AA. The conductive portion 4 is configured to conduct electrical signals between the array substrate 1 and the opposing substrate 2.

[0081] In the non-display area BB surrounding the display area AA of the display panel, on the one hand, the bonding area DP is wider along its extension direction than the other non-display areas BB (e.g., bonding the opposite side area DPO, and the first non-display area BB1 where the gate drive circuit GOA is located) (as shown in Figure 1A, the width c1 of the bonding area DP along its extension direction is greater than the width c2 of the opposite side area DPO along its extension direction); on the other hand, on the side where the bonding area DP is located, the sealing adhesive 3 usually needs to be closer to the outer edge of the display panel. Optionally, the edge of the display panel refers to the edge of the color filter substrate in the display panel. (For example, as shown in Figures 1B and 1C, the distance b1 between the sealant 3 of the bonding area DP and the outer edge of the display panel is smaller than the distance b2 between the sealant 3 of the bonding area DPO and the outer edge of the display panel.) This ensures a smaller gap between the sealant 3 and the outer edge of the display panel, avoiding a larger gap that would easily accumulate moisture, which would hinder the subsequent bonding of the terminals of the bonding area DP to the control chip IC. Therefore, in this embodiment of the disclosure, for As shown in Figure 1B, in the bonding area DP, the first conductive part 41 partially overlaps with the sealing adhesive 3, and partially extends beyond the sealing adhesive 3 towards the display area AA. That is, the first conductive part 41 can be placed on the side closer to the display area AA. On the one hand, since the bonding area DP is relatively wide, even if the first conductive part 41 is placed on the side closer to the display area AA, it will not affect the normal display of the display area AA. On the other hand, since the bonding area DP has a relatively small distance between the sealing adhesive 3 and the outer edge of the display panel, if the first conductive part 41 is partially placed on the sealing adhesive... 3. When the sealant 3 extends to the outer edge of the display panel, the first conductive part 41 may overflow to the outer edge of the display panel or beyond during the pressing of the array substrate and the opposing substrate. This makes it difficult to divide the display panel (i.e., when cutting a motherboard containing multiple display panels to form multiple display panels, if the first conductive part 41 overflows, it will be difficult to separate the display panels from the motherboard). Moreover, the overflow of the first conductive part 41 is also not conducive to the subsequent assembly of the display panel with other structures. Furthermore, when bonding the opposite side area DPO, as shown in Figure 1C... As shown, the second conductive part 42 partially overlaps with the sealant 3 and extends beyond the sealant 3 to a region away from the display area AA. That is, the second conductive part 42 can be provided on the side away from the display area AA (i.e., near the outer edge of the display panel). On the one hand, since the distance b2 between the sealant 3 binding the opposite area DPO and the outer edge of the display panel is relatively large (for example, the distance b2 between the sealant 3 binding the opposite area DPO and the outer edge of the display panel is 0.4mm to 0.8mm, optionally 0.55mm, while the distance b1 between the sealant 3 binding the DP and the outer edge of the display panel is 0.08 to 0.3mm, optionally 0.15mm, for example, b2 is 0.08mm larger than b1).Therefore, by placing the second conductive portion 41 on the side away from the display area AA (i.e., the side closer to the outer edge of the display panel), there will be no overflow of the second conductive portion 42 into the area beyond the outer edge of the display panel, thus avoiding problems such as difficulties in display panel segmentation and assembly with other structures. On the other hand, since the width of the bonding opposite area DPO along its extension direction is relatively narrow, if the second conductive portion 42 is placed on the side closer to the display area AA, it is easy for the second conductive portion 42 to overflow into the display area when the array substrate and the opposing substrate are pressed together, affecting the normal display of the display panel.

[0082] In this embodiment, the first conductive part 41 and / or the second conductive part 42 are partially located in the sealing adhesive 3 and partially extend beyond the sealing adhesive 3. This can reduce the overlap area between the first conductive part 41 and / or the second conductive part 42 and the sealing adhesive 3, and improve the situation where the film layer in the area where the first conductive part 41 and / or the second conductive part 42 is located is thicker than in other locations, resulting in different cell spacing. This causes the area where the first conductive part 41 and / or the second conductive part 42 is located to appear white, affecting the normal display of the display panel.

[0083] In a specific implementation, a first colloid (which can form a sealing adhesive after pressing and curing) can be formed on the opposing substrate first, followed by a second colloid containing conductive particles (e.g., gold balls) (which can form a first conductive part 41 and a second conductive part 42 after pressing and curing). Then, the array substrate and the opposing substrate are pressed together, and the first and second colloids are cured to form the sealing adhesive 3, the first conductive part 41, and the second conductive part 42. The second colloid may have better flowability than the first colloid to facilitate pressing and leveling, which is beneficial for consistent adhesive thickness at the locations of conductive parts 4 and non-conductive parts 4. Optionally, the first colloid may be a colloid without conductive particles. Optionally, the material of the first colloid may be the same as or different from the material of the second colloid; this is not limited here.

[0084] In one possible implementation, referring to FIG7A, the first conductive part 41 may include: frame adhesive 401 and conductive particles 402 mixed in the frame adhesive 401; the second conductive part 42 may include: frame adhesive 401 and conductive particles 402 mixed in the frame adhesive 401; wherein, the conductive particles 402 may include gold balls; the frame adhesive material of the first conductive part 41 and the second conductive part 42 may be the same. Referring to Figure 1B, on the bonding area DP side, after the first conductive part 41 is disposed in the sealing adhesive 3, the sealing adhesive 3 located on the side of the first conductive part 41 away from the display area AA may not have conductive particles. The width d1 of the area without conductive particles may account for 20% to 60% of the width d2 of the sealing adhesive 3. For example, the width d1 of the area without conductive particles may account for 40% of the width d2 of the sealing adhesive 3. Referring to Figure 1C, on the bonding opposite area DPO, after the second conductive part 42 is disposed in the sealing adhesive 3, the sealing adhesive 3 located on the side of the first conductive part 41 close to the display area AA may not have conductive particles. The width d3 of the area without conductive particles may account for 20% to 60% of the width d4 of the sealing adhesive 3. For example, the width d3 of the area without conductive particles may account for 40% of the width d4 of the sealing adhesive 3.

[0085] In one possible implementation, referring to Figures 1B and 1C, the sealing adhesive 3 includes: a first sealing adhesive edge 31 and a second sealing adhesive edge 32; the minimum distance a1 between the first sealing adhesive edge 31 and the display area AA is less than the minimum distance a2 between the second sealing adhesive edge 32 and the display area AA; that is, the first sealing adhesive edge 31 can be the inner edge of the sealing adhesive 3, and the second sealing adhesive edge 32 can be the outer edge of the sealing adhesive 3; the first conductive part 41 overlaps with the first sealing adhesive edge 31, and the second conductive part 42 overlaps with the second sealing adhesive edge 32.

[0086] In one possible implementation, the minimum distance a1 between the first sealing edge 31 and the display area AA can be the distance between the first sealing edge 31 and the edge of the nearest display sub-pixel opening area; the minimum distance a2 between the second sealing edge 32 and the display area AA can be the distance between the second sealing edge 32 and the edge of the nearest display sub-pixel opening area.

[0087] In one possible implementation, as shown in Figures 1B and 1C, the central region of the first conductive portion 41 is located within the sealing adhesive 3; the central region of the second conductive portion 42 is located within the sealing adhesive 3, that is, most of the first conductive portion 41 and / or the second conductive portion 42 are located within the area where the sealing adhesive 3 is located; optionally, 60% to 90% of the first conductive portion 41 and / or the second conductive portion 42 are located within the area where the sealing adhesive 3 is located.

[0088] In one possible implementation, referring to Figures 1B and 1C, the display panel includes: a first panel outer edge w1 and a second panel outer edge w2; the first panel outer edge w1 and the bonding area DP are located on the same side of the display area AA, and the second panel outer edge w2 and the bonding opposite side area DPO are located on the same side of the display area AA. That is, as shown in Figure 1A, the first panel outer edge w1 can be the lower edge of the display panel, and the second panel outer edge w2 can be the upper edge of the display panel; the minimum distance b1 between the sealant 3 and the first outer edge w1 is smaller than the minimum distance b2 between the sealant 3 and the second outer edge w2. This ensures a smaller distance between the sealant 3 of the bonding area DP and the first panel outer edge w1, avoiding a larger gap that would easily accumulate moisture, which would be detrimental to the subsequent bonding of the terminals of the bonding area DP to the control chip IC.

[0089] In one possible implementation, referring to Figures 1B and 1C, the display panel further includes: a first blocking portion 51 and / or a second blocking portion 52; the first blocking portion 51 is located between the first conductive portion 41 and the display area AA; the second blocking portion 52 is located between the second conductive portion 42 and the outer edge w2 of the second panel.

[0090] In this embodiment, the design factors regarding the positional relationship between the first conductive part 41 and / or the second conductive part 42 and the sealing adhesive 3 include: considering that when the first conductive part 41 and / or the second conductive part 42 overlaps with the sealing adhesive 3, the height of the sealing adhesive at that location will be higher than the location of the sealing adhesive where the first conductive part 41 and / or the second conductive part 42 is not provided. If the first conductive part 41 and / or the second conductive part 42 is too close to the display area AA, it will cause the in-plane gap to be too high, resulting in white stripes (mura); if the first conductive part 41 and / or the second conductive part 42 is too close to the outer edge of the display panel, it will cause the sealing adhesive 3 to be coated on the display panel cutting line, resulting in abnormal segmentation; in this embodiment, on the bonding area DP side, the first conductive part 41 is located at a position of the sealing adhesive 3 close to the display area AA. This design takes into account the bonding area DP sealing... The frame adhesive 3 is about 0.15mm away from the outer edge of the display panel. The size of the first conductive part 41 is about 1mm. The dotting accuracy of the first conductive part 41 and / or the second conductive part 42 and the coating accuracy of the frame adhesive 3 are important. If the first conductive part 41 is placed close to the outer edge of the display panel, it must completely overlap with the frame adhesive 3. This design will inevitably lead to the frame adhesive being too thick at the dotting position, resulting in an abnormally high gap, causing mura or uneven frame adhesive height, leading to the risk of frame adhesive peeling. At the same time, considering that the alignment liquid is coated on the inner side of the frame adhesive 3, in order to prevent the alignment liquid from covering the first conductive part 41, a first barrier part 51 is designed at the edge of the first conductive part 41. This not only effectively prevents the alignment liquid from covering the first conductive part 41 at this location, causing abnormal conduction between the array substrate and the opposing substrate, but also prevents the first conductive part 41 from flowing out to the display area AA and causing display abnormalities. To bond the opposite side area DPO, the second conductive part 42 is positioned near the outer edge of the display panel by the sealant 3. This design takes into account the bonding of the opposite side area DPO. Because the sealant 3 has a large coating width, corresponding space needs to be reserved. Therefore, the sealant 3 is about 0.55mm away from the outer edge of the display panel, which is greater than the 0.4mm away from the outer edge of the display panel by the sealant 3 in the bonding area DP. The second conductive part 42 is positioned outside the sealant 3, away from the AA area, to effectively reduce the risk of mura caused by high gap. At the same time, a second barrier part 52 is positioned outside the dotted position of the second conductive part 42 to prevent the sealant from overflowing onto the break line.

[0091] In one possible implementation, referring to Figures 1B and 1C, the first blocking portion 51 includes: a first sub-blocking portion 511 and a second sub-blocking portion 512; the extending direction of the first sub-blocking portion 511 is the same as the extending direction of the outer edge of the first conductive portion 41 toward the display area AA; the second sub-blocking portion 512 is connected to the end of the first sub-blocking portion 511 and is bent toward the first conductive portion 41; thus, effective blocking of the alignment liquid is achieved.

[0092] The second barrier portion 52 includes a third sub-barrier portion 521 and a fourth sub-barrier portion 522. The extension direction of the third sub-barrier portion 521 is the same as the extension direction of the outer edge of the second conductive portion 42 toward the display area AA. The fourth sub-barrier portion 522 is connected to the end of the third sub-barrier portion 521 and is bent toward the side of the second conductive portion 42, thereby achieving effective blocking of the alignment liquid.

[0093] In one possible implementation, referring to Figures 1D and 1E, the first barrier portion 51 further includes: a fifth barrier portion 515; the fifth barrier portion 515 is connected to the other end of the second sub-barrier portion 512; the orthographic projection of the extension line of the fifth barrier portion 515 onto the substrate 11 overlaps with the orthographic projection of the first conductive portion 41 and / or the first common pattern 6 onto the substrate 11; the fifth barrier portion 515 can extend the blocking area against the alignment liquid; the second barrier portion 52 further includes: a sixth barrier portion 516; the sixth barrier portion 516 is connected to the other end of the fourth sub-barrier 522; the orthographic projection of the extension line of the sixth barrier portion 516 onto the substrate 11 overlaps with the orthographic projection of the second conductive portion 42 and / or the first common pattern 6 onto the substrate 11; the sixth barrier portion 516 can extend the blocking area against the alignment liquid.

[0094] In one possible implementation, referring to Figures 1B and 1C, the extending direction of the second sub-blocking portion 512 may be perpendicular to the extending direction of the first sub-blocking portion 511; the extending direction of the fourth sub-blocking portion 522 may be perpendicular to the extending direction of the third sub-blocking portion 521; in another possible implementation, referring to Figures 1D and 1E, the smaller of the included angles formed by the intersection of the second sub-blocking portion 512 and the first sub-blocking portion 511 is an acute angle; the smaller of the included angles formed by the intersection of the fourth sub-blocking portion 522 and the third sub-blocking portion 521 is an acute angle.

[0095] In another possible implementation, as shown in Figures 1D and 1E, the extending direction of the fifth blocking portion 515 may be parallel to the extending direction of the first sub-blocking portion 511; and the extending direction of the sixth blocking portion 516 may be parallel to the extending direction of the third sub-blocking portion 521.

[0096] In one possible implementation, the first barrier portion 51 and the second barrier portion 52 may be disposed on the opposing substrate; in another possible implementation, the first barrier portion 51 and the second barrier portion 52 may be disposed on the array substrate; in yet another possible implementation, the first barrier portion 51 and the second barrier portion 52 may be located on the same side substrate as the sealing adhesive 3. For example, if the sealing adhesive 3 is located on the opposing substrate 2, then the first barrier portion 51 and the second barrier portion 52 may also be disposed on the opposing substrate 2.

[0097] In one possible implementation, referring to FIG1A, the display panel includes a plurality of first conductive portions 41 and a plurality of second conductive portions 42; the plurality of first conductive portions 41 are all located in the bonding region DP and are arranged sequentially along the extension direction of the bonding region DP; the plurality of second conductive portions 42 are all located in the bonding opposite region DPO and are arranged sequentially along the extension direction of the bonding opposite region DPO. That is, the first conductive portions 41 are a plurality of discrete independent structures, and the second conductive portions 42 are a plurality of discrete independent structures.

[0098] In one possible implementation, the number of first conductive portions 41 provided in the bonding region DP is different from the number of second conductive portions 42 provided in the bonding opposite region DPO. The number of second conductive portions 42 provided in the bonding opposite region DPO can be greater than the number of first conductive portions 41 provided in the bonding region DP. For example, the number of first conductive portions 41 provided in the bonding region DP can be 4-8, for example, 6; the number of second conductive portions 42 provided in the bonding opposite region DPO can be 8-12, for example, 10.

[0099] In one possible implementation, at least a portion of the first conductive portion 4 may be disposed in the area between adjacent flexible circuit boards in the bonding region DP.

[0100] In one possible implementation, referring to FIG2, the first conductive portion 41 is strip-shaped and extends along the extension direction of the bonding region DPO; the second conductive portion 42 is strip-shaped and extends along the extension direction of the bonding opposite region DPO. In this embodiment of the present disclosure, the strip-shaped first conductive portion 41 and second conductive portion 42 can also be formed by linear coating. Reducing the dot-shaped first conductive portion 41 and / or second conductive portion 42 will result in a larger gap formed by the inward movement of the frame adhesive, producing moisture residue and causing corrosion problems.

[0101] In one possible implementation, referring to FIG3, the display panel includes a plurality of first conductive portions 41, all of which are located in the bonding region DP and are arranged sequentially along the extension direction of the bonding region DP; the second conductive portions 42 are strip-shaped and extend along the extension direction of the bonding opposite region DPO. In another possible implementation, the first conductive portions 41 are strip-shaped and extend along the extension direction of the bonding region DP; the display panel includes a plurality of second conductive portions 42, all of which are located in the bonding opposite region DPO and are arranged sequentially along the extension direction of the bonding opposite region DPO.

[0102] In one possible implementation, referring to Figures 4, 5, and 6, the array substrate includes: a first substrate 11, and a plurality of first common patterns 6 located on one side of the first substrate 1; the orthographic projection of the first common electrode pattern 6 on the first substrate 1 at least partially overlaps with the orthographic projection of the conductive portion 4 on the first substrate 11. In one possible implementation, the orthographic projection of the conductive portion 4 (first conductive portion 41 and / or second conductive portion 42) on the first substrate 1 covers the orthographic projection of the first common pattern 6 on the first substrate 1. In this embodiment, the array substrate further includes a plurality of first common patterns 6, which can serve as position marks when the first conductive portion 41 and / or the second conductive portion 42 are marked; that is, a plurality of first common patterns 6 can be formed first, and subsequently, the first conductive portion 41 and / or the second conductive portion 42 can be marked at these positions using the first common patterns 6 as position marks.

[0103] In one possible implementation, the first common pattern 6 and the conductive part 4 can be provided in a one-to-one correspondence.

[0104] In one possible implementation, the outer contour of the first common pattern 6 is a pentagon, hexagon, or octagon. In one possible implementation, referring to Figures 4-6, the outer contour of the first common pattern 6 is an octagon. The octagonal first common pattern 6 is easy to identify and facilitates the marking of dots on the first conductive part 41 and / or the second conductive part 42.

[0105] In one possible implementation, the size range of the first public pattern 6 can be (0.5mm to 1.5mm)*(0.5mm to 1.5mm).

[0106] In one possible implementation, referring to Figures 4, 5, and 6, the first common pattern 6 includes: a peripheral wiring portion 61, multiple first wiring portions 62 and multiple second wiring portions 63 located inside the peripheral wiring portion 61; the first wiring portions 62 and the second wiring portions 63 intersect to form multiple first opening areas 60; at least two of the multiple first opening areas 60 have different areas. In this embodiment, the first common pattern 6 includes multiple first opening areas 60 to avoid the problem that when the first common pattern 6 is a solid, opaque structure, it will affect the light transmission at that location, leading to difficulties in curing the sealant. Optionally, the opening ratio of the first common pattern 6 can be greater than or equal to 50% and less than 100%.

[0107] In one possible implementation, referring to Figure 4, the first common pattern 6 includes two first traces 62 and two second traces 63. Each first trace 62 connects to two opposite endpoints of an octagon, and each second trace 63 connects to two opposite endpoints of an octagon. The first traces 62 and the second traces 63 intersect perpendicularly to form nine first opening areas 60. Each first opening area 60 has a large opening area, making it easier to identify as a Mark shape. However, not too many first traces 62 and two second traces 63 are configured to avoid affecting the thickness of the frame adhesive at this point.

[0108] In one possible implementation, as shown in Figure 5, the first common pattern 6 includes a greater number of first traces 62 and second traces 63, for example, nine first traces 62 and nine second traces 63. Each first trace 62 connects to two opposite endpoints of an octagon. The first traces 62 and second traces 63 intersect perpendicularly to form more first opening areas 60. The first traces 62 and second traces 63 are evenly distributed, which can reduce trace resistance. However, when used as a Mark, it has the problem of being difficult to identify.

[0109] In one possible implementation, referring to FIG6, the first common pattern 6 includes: three obliquely extending first trace portions 62 and three obliquely extending second trace portions 63. Part of the first trace portion 62 is perpendicular to the peripheral trace portion 61, and part of the second trace portion 63 is perpendicular to part of the peripheral trace portion 61. The first trace portion 62 and the second trace portion 63 intersect perpendicularly to form a plurality of first opening areas 60. The first trace portion 62 and the second trace portion 63 shown in FIG6 are evenly distributed and are easily identifiable as Mark morphology.

[0110] In one possible implementation, referring to FIG4, at least one of the peripheral wiring portion 61, the first wiring portion 62, and the second wiring portion 63 has a plurality of second opening areas 600; the area of ​​the second opening area 600 is smaller than the area of ​​the first opening area 60. In one possible implementation, at least one of the peripheral wiring portion 61, the first wiring portion 62, and the second wiring portion 63 has a plurality of semi-opening areas (for example, the location 600 shown in FIG4 is a semi-opening area, that is, the thickness of the metal film layer at this location is less than the thickness of the metal film layer without a semi-opening area). Optionally, the metal film at this location can also be hollowed out to form a through-hole state, which improves the curing of the frame adhesive. Referring to FIG4, in the direction perpendicular to the display panel, the second opening areas overlap with those in the peripheral wiring portions 61, the first wiring portion 62, and the second wiring portion 63.

[0111] In one possible implementation, referring to Figures 7A-7B, 8A-8B, and 9A-9B, where Figure 7B can be a partial cross-sectional view along the dashed line e1 in Figure 7A, Figure 8B can be a partial cross-sectional view along the dashed line e2 in Figure 8A, and Figure 9B can be a partial cross-sectional view along the dashed line e3 in Figure 9A, the array substrate includes: a transfer electrode 13 located on the side of the first common pattern 6 facing the opposing substrate 2, and a first insulating layer 14 located between the transfer electrode 13 and the first common pattern 6; the transfer electrode 13 is electrically connected to the conductive portion 4; the first insulating layer 14 has a first via K1, through which the first common pattern 6 is electrically connected to the transfer electrode 13. In this embodiment of the present disclosure, at the conductive part 4 (first conductive part 41 and / or second conductive part 42), the first insulating layer 14 is provided with a first via K1 so that the first common pattern 6 of the array substrate is electrically connected to the transfer electrode 13 through the first via K1; wherein, the design of the first via K1 mainly considers the conduction resistance. The smaller the effective conduction area, the larger the conduction resistance and the worse the conduction effect.

[0112] In one possible implementation, referring to Figures 7A-7B, 8A-8B, 9A-9B, and 10, the array substrate includes a first common electrode trace 12; the opposing substrate includes a second common electrode trace 23; the first common electrode trace 12 and the second common electrode trace 23 are electrically connected through a conductive portion 4; that is, the second common electrode trace 23 of the opposing substrate 2 is electrically connected to the first common electrode trace 12 of the array substrate through the conductive portion 4; the first common electrode trace 12 includes a first common pattern 6, that is, by setting the first common pattern 6 on the first common electrode trace 12, it serves as a dot mark for the conductive portion 4.

[0113] In one possible implementation, the first common pattern 6 can be on the same layer and made of the same material as the grid lines.

[0114] Optionally, the adapter electrode 13 can be made of the same material as the common electrode layer or the pixel electrode layer; optionally, the material of the adapter electrode 13 may include indium tin oxide.

[0115] In one possible implementation, as shown in Figures 7A-7B, the first common pattern 6 corresponds one-to-one with the first via K1. That is, a larger first via K1 is provided at the location of a first common pattern 6, and the area of ​​the first via K1 is 50% to 90% of the area of ​​the first common pattern 6. In this embodiment, the first via K1 is larger, resulting in a larger conductive area, lower conductive resistance, and better conductivity. However, the large-area opening at the conductive part 4 causes the film layer at this location to be thinner than at other locations, leading to a thinner sealant thickness and abnormal gaps. In addition, the conductive particles 402 have a larger vertical spacing, which increases the probability of non-conductivity.

[0116] In one possible implementation, as shown in Figure 7B, the first insulating layer 14 is further provided with a plurality of second vias K2 around the first via K1; the plurality of second vias K2 can improve the problem of large thickness difference between the first via K1 and the surrounding film layer, which leads to abnormal gap.

[0117] In one possible implementation, the area of ​​the first via K1 is more than 70% of the area of ​​the first common pattern 6, so as to have a better conduction effect.

[0118] In one possible implementation, as shown in Figures 8A-8B, the first via K1 includes a plurality of first sub-vias K11; the orthographic projections of the plurality of first sub-vias K11 of the same first via K1 onto the first substrate 11 are all located within the orthographic projection of the first common pattern 6 onto the first substrate. In this embodiment of the present disclosure, the first via K1 includes a plurality of first sub-vias K11, which adopts a small-hole design, resulting in good conductivity of the conductive particles 402. However, the small conductive area of ​​the first sub-vias K11 leads to a problem of high on-resistance.

[0119] In one possible implementation, referring to Figures 9A-9B, the first via K1 includes a second sub-via K12 and a plurality of third sub-vias K13; the size of the third sub-via K13 is smaller than the size of the second sub-via K12; the first common pattern 6 partially overlaps with the sealing adhesive 3, and partially does not overlap with the sealing adhesive 3; the orthographic projection of the second sub-via K12 on the first substrate 11 is located in the area where the first common pattern 6 overlaps with the sealing adhesive 3; the orthographic projection of the third sub-via K13 on the first substrate 11 is located in the area outside the area where the first common pattern 6 overlaps with the sealing adhesive 3. In this embodiment, a large hole is drilled at the overlap of the first common pattern 6 and the sealing adhesive 3, and a small hole is drilled at other locations, which not only solves the problem of excessive sealing adhesive height at the overlap of the conductive part 4 and the sealing adhesive 3, but also increases the via conductive area.

[0120] The structures shown in Figures 7A-7B, 8A-8B, and 9A-9B all involve drilling a hole at the location of the conductive part 4. In another possible embodiment, as shown in Figure 11, the orthographic projection of the first common pattern 6 on the first substrate 11 does not overlap with the orthographic projection of the first common electrode trace 12 on the substrate; however, the orthographic projection of the first via K1 on the substrate 11 overlaps with the orthographic projection of the first common electrode trace 12 on the first substrate 11; the first common pattern 6 is electrically connected to the first common electrode trace 12 via the first via K1 through the adapter electrode 13. That is, in this embodiment, the first via K1 is designed on the outside of the sealing adhesive 3 and connected to the conductive part 4 (i.e., the first common pattern 6) through the adapter electrode 13. The first common pattern 6 serves only as a mark for inspection.

[0121] In conventional technology, VA display product designs use a sealant incorporating gold balls. This gold-ball-containing sealant is coated around the perimeter of the display panel. Because the sealant contains gold balls, only the common signal (COM) conductive electrodes can be configured for the traces underneath it; conductive electrodes for other signals cannot be configured. The advantage of this sealant type is good conductivity between the top and bottom electrodes, and the entire sealant can serve a conductive function. However, there are some problems: 1. It is prone to electrostatic discharge (ESD) defects. Because the sealant contains gold balls, if it covers other signal traces, the distance between the top and bottom signals becomes shorter due to the conductivity of the gold balls, making it easy for the top and bottom electrodes to break or for ESD defects to occur during reliability or ESD testing; 2. It is not suitable for narrow... The bezel, located on both sides of the non-display area where the gate drive circuit is configured in the display panel, requires transparent electrodes (such as adapter electrodes) due to the need for metal wiring. These transparent electrodes are exposed. If gold-plated frame adhesive is applied to them, a short circuit problem will occur between the two signals. Therefore, the frame adhesive and the gate drive circuit cannot be configured in the same position at the same time. This increases the bezel of the non-display area where the gate drive circuit is located, which is contrary to the current narrow bezel design trend. If we want to adapt to the narrow bezel, we have to compress the width of the frame adhesive, which will lead to poor sealing of the frame adhesive. This will make it easy for moisture to enter, causing defects or bubbles, affecting product yield and reliability.

[0122] In one possible implementation, referring to Figure 1A, the display panel further includes: a first non-display area BB1 located around the display area AA and connecting the bonding area DP and the bonding opposite area DPO; among the bonding area DP, the bonding opposite area DPO, and the first non-display area BB1, only the bonding area DP and the bonding opposite area DPO are provided with conductive parts 4. In this way, the first non-display area BB1 where the gate drive circuit GOA is located does not have conductive parts 4 containing conductive particles 402, thus avoiding the situation where the first non-display area BB1 is simultaneously provided with conductive parts 4 and the gate drive circuit GOA and / or the gate drive signal trace GZ, thereby avoiding electrostatic discharge problems. Also, since the conductive parts 4 and the gate drive circuit GOA and / or the gate drive signal trace GZ cannot overlap, if the first non-display area BB1 is simultaneously provided with conductive parts 4 and the gate drive circuit GOA and / or the gate drive signal trace GZ, and the projections do not overlap, the first non-display area BB1 will be wider, which is not conducive to narrow bezel design.

[0123] In one possible implementation, referring to Figure 12, the first non-display area BB1 includes: the outer edge w3 of the third display panel, the gate driving unit GOA, and the gate driving signal trace GZ located on the side of the gate driving unit GOA away from the display area 11; in the first non-display area BB1, the sealant 3 overlaps with at least a portion of the gate driving signal trace GZ. In this embodiment, the bonding area DP and the bonding opposite area DPO are provided with conductive parts 4, and the first non-display area BB1 is not provided with conductive parts 4, which allows the sealant 3 and the gate driving signal trace GZ to be combined together, which is beneficial for saving space and realizing a narrow bezel design.

[0124] Based on the same inventive concept, this disclosure also provides a display device, which includes: a display panel as provided in the embodiments of this disclosure.

[0125] Based on the same inventive concept, this disclosure also provides a method for manufacturing a display panel as provided in this disclosure, wherein, referring to FIG13, the manufacturing method includes:

[0126] Step S100: Apply a sealing colloid around the display area of ​​the opposing substrate and / or the array substrate;

[0127] Step S200: A first conductive portion is formed in the bonding area, and the first conductive portion partially overlaps with the sealant and partially extends beyond the sealant and faces the display area.

[0128] Step S300: The second conductive part formed on the opposite side area is bonded, and the second conductive part partially overlaps with the sealant, and partially extends beyond the sealant and away from the display area.

[0129] Step S400: Press the opposing substrate and the array substrate together to bond the array substrate and the opposing substrate.

[0130] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0131] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if these modifications and variations to the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention also intends to include these modifications and variations.

Claims

1. A display panel having a display area and a non-display area located around the periphery of the display area; the non-display area comprising: A bonding area located on one side of the display area, and a bonding opposite area located on the other side of the display area and opposite to the bonding area, wherein the display panel includes: An array substrate and a facing substrate arranged opposite to each other; The sealing adhesive is located between the array substrate and the opposing substrate, and is located in the non-display area; The conductive portion includes: a first conductive portion and a second conductive portion; the first conductive portion is located between the array substrate and the opposing substrate, and is located in the bonding region, wherein the first conductive portion partially overlaps with the sealant, and partially extends beyond the sealant and faces the display area; the second conductive portion is located between the array substrate and the opposing substrate, and is located in the bonding opposite region, wherein the second conductive portion partially overlaps with the sealant, and partially extends beyond the sealant and is away from the display area; the conductive portion is configured to conduct electrical signals between the array substrate and the opposing substrate.

2. The display panel as claimed in claim 1, wherein, The sealing adhesive includes: a first sealing adhesive edge and a second sealing adhesive edge; the minimum distance between the first sealing adhesive edge and the display area is less than the minimum distance between the second sealing adhesive edge and the display area; The first conductive part overlaps with the edge of the first sealing adhesive, and the second conductive part overlaps with the edge of the second sealing adhesive.

3. The display panel as described in claim 1 or 2, wherein, The display panel includes: a first panel outer edge and a second panel outer edge; the first panel outer edge and the bonding area are located on the same side of the display area, and the second panel outer edge and the bonding opposite side area are located on the same side of the display area; The minimum distance between the sealing adhesive and the first outer edge is less than the minimum distance between the sealing adhesive and the second outer edge.

4. The display panel as claimed in claim 3, wherein, The display panel further includes: a first blocking part, and / or, a second blocking part; The first barrier portion is located between the first conductive portion and the display area; the second barrier portion is located between the second conductive portion and the outer edge of the second panel.

5. The display panel as claimed in claim 4, wherein, The first blocking portion includes: a first sub-blocking portion and a second sub-blocking portion; the extending direction of the first sub-blocking portion is the same as the extending direction of the outer edge of the first conductive portion toward the display area; the second sub-blocking portion is connected to the end of the first sub-blocking portion and is bent toward the first conductive portion. The second blocking portion includes: a third sub-blocking portion and a fourth sub-blocking portion; the extending direction of the third sub-blocking portion is the same as the extending direction of the outer edge of the second conductive portion toward the display area; the fourth sub-blocking portion is connected to the end of the third sub-blocking portion and is bent toward the side of the second conductive portion.

6. The display panel according to any one of claims 1-5, wherein, The display panel includes a plurality of first conductive portions and a plurality of second conductive portions; The plurality of first conductive parts are all located in the bonding area and are arranged sequentially along the extension direction of the bonding area; the plurality of second conductive parts are all located in the bonding opposite side area and are arranged sequentially along the extension direction of the bonding opposite side area.

7. The display panel as described in any one of claims 1-5, wherein, The first conductive portion is strip-shaped and extends along the extension direction of the bonding region; the second conductive portion is strip-shaped and extends along the extension direction of the bonding opposite side region.

8. The display panel according to any one of claims 1-7, wherein, The array substrate includes: a first substrate and a plurality of first common patterns; The orthographic projection of the first common electrode pattern onto the first substrate at least partially overlaps with the orthographic projection of the conductive portion onto the first substrate.

9. The display panel as claimed in claim 8, wherein, The outer contour of the first common pattern is a pentagon, hexagon, or octagon.

10. The display panel as claimed in claim 8 or 9, wherein, The first common pattern includes: an outer wiring portion, multiple first wiring portions located inside the outer wiring portion, and multiple second wiring portions; the first wiring portions and the second wiring portions intersect to form multiple first opening areas; At least two of the plurality of first opening regions have different areas.

11. The display panel as claimed in claim 10, wherein, At least one of the peripheral wiring section, the first wiring section, and the second wiring section has a plurality of second opening areas; the area of ​​the second opening area is smaller than the area of ​​the first opening area.

12. The display panel as claimed in any one of claims 8-11, wherein, The array substrate includes: a transfer electrode located on the side of the first common pattern facing the opposing substrate, and a first insulating layer located between the transfer electrode and the first common pattern; the transfer electrode is electrically connected to the conductive portion; The first insulating layer has a first via, and the first common pattern is electrically connected to the adapter electrode through the first via.

13. The display panel as claimed in claim 12, wherein, The first common pattern corresponds to the first via, and the area of ​​the first via is 50% to 90% of the area of ​​the first common pattern.

14. The display panel as claimed in claim 12, wherein, The first via includes: a plurality of first sub-vias; the orthographic projections of the plurality of first sub-vias of the same first via onto the first substrate are all located within the orthographic projection of the first common pattern onto the first substrate.

15. The display panel as claimed in claim 12, wherein, The first via includes: a second sub-via and a plurality of third sub-vias; the size of the third sub-via is smaller than the size of the second sub-via; the first common pattern part overlaps with the sealing adhesive, and part does not overlap with the sealing adhesive; The second sub-via's orthographic projection onto the first substrate is located in the area where the first common pattern overlaps with the sealant; the third sub-via's orthographic projection onto the first substrate is located in the area outside the area where the first common pattern overlaps with the sealant.

16. The display panel according to any one of claims 9-15, wherein, in, The array substrate includes a first common electrode trace; the opposing substrate includes a second common electrode trace; the first common electrode trace and the second common electrode trace are electrically connected through the conductive portion; The first common electrode trace includes the first common pattern.

17. The display panel as claimed in claim 12, wherein, The orthographic projection of the first common pattern onto the first substrate does not overlap with the orthographic projection of the first common electrode trace onto the substrate; and the orthographic projection of the first via onto the substrate overlaps with the orthographic projection of the first common electrode trace onto the first substrate. The first common pattern is electrically connected to the first common electrode trace via the first via through the adapter electrode.

18. The display panel according to any one of claims 1-17, wherein, The display panel further includes: a first non-display area located outside the display area and connecting the binding area and the binding opposite side area; Of the binding area, the binding opposite area, and the first non-display area, only the binding area and the binding opposite area are provided with the conductive part.

19. The display panel as claimed in claim 18, wherein, The first non-display area includes: a gate driving unit, and a gate driving signal trace located on the side of the gate driving unit away from the display area; In the first non-display area, the sealing adhesive overlaps with at least a portion of the gate drive signal traces.

20. A display device, wherein, include: The display panel as described in any one of claims 1-19.

21. A method for manufacturing a display panel as described in any one of claims 1-19, wherein, The manufacturing method includes: A sealing adhesive is applied around the display area of ​​the opposing substrate and / or the array substrate; A first conductive portion is formed in the bonding area, and the first conductive portion partially overlaps with the sealant, and partially extends beyond the sealant and faces the display area. A second conductive portion is formed in the bonding opposite area, and the second conductive portion partially overlaps with the sealant, and partially extends beyond the sealant and away from the display area. The opposing substrate and the array substrate are pressed together to bond the array substrate and the opposing substrate.

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