Display panel, display apparatus, and method for driving display panel

Abstract

A display panel, a display apparatus, and a method for driving a display panel. The display panel comprises multiple sub-pixels arranged in an array, at least one data line group, at least one data bus group, and at least one control switch group. The multiple sub-pixels comprise first-color sub-pixels, and the first-color sub-pixels comprising first-type first-color sub-pixels and second-type first-color sub-pixels; the at least one data line group comprises multiple data lines, connected to a display unit, one column of sub-pixels being connected to two data lines, and one data line being connected to a same type of pixels in one column of sub-pixels; the data bus group is connected to the display unit; a first data bus of the data bus group is connected to the first-type first-color sub-pixels, and a second data bus thereof is connected to the second-type first-color sub-pixels; the at least one control switch group comprises multiple control switches connected to the data bus group.

Description

Display panel, display device and driving method of display panel

[0001] The present application claims priority to Chinese Patent Application No. 202410875457.0, filed on July 01, 2024, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] The present disclosure relates to the technical field of display, and in particular to a display panel, a display device and a driving method of the display panel. BACKGROUND

[0003] At present, OLED (Organic Light-Emitting Diode) display devices are widely used due to their characteristics of self-emission, fast response, wide viewing angle and being able to be made on a flexible substrate. An OLED display device includes a plurality of sub-pixels. Each sub-pixel includes a pixel driving circuit and a light-emitting device. The light-emitting device is driven by the pixel driving circuit to emit light, thereby realizing display. SUMMARY

[0004] In one aspect, a display panel is provided. The display panel includes a plurality of sub-pixels arranged in an array, at least one data line group, at least one data bus group, and at least one control switch group. The plurality of sub-pixels includes first color sub-pixels, the first color sub-pixels including first type first color sub-pixels and second type first color sub-pixels; the plurality of sub-pixels includes at least one display unit, the display unit including at least four columns of sub-pixels, at least two columns of sub-pixels in the at least four columns of sub-pixels being first sub-pixel columns, one column of other sub-pixels being arranged between every two of the first sub-pixel columns, the at least two columns of first sub-pixel columns including a first type first sub-pixel column and a second type first sub-pixel column arranged in sequence, wherein the first type first sub-pixel column includes a first type first color sub-pixel and a second type first color sub-pixel arranged in sequence in a column direction, and the second type first sub-pixel column includes a second type first color sub-pixel and a first type first color sub-pixel arranged in sequence in the column direction. The at least one data line group includes a plurality of data lines connected to the display unit, one column of sub-pixels being connected to two data lines, and one of the data lines being connected to sub-pixels of the same type in the one column of sub-pixels. The at least one data bus group includes a plurality of data buses connected to the display unit; the data bus group includes a first data bus and a second data bus, the first data bus being connected to the first type first color sub-pixels in the at least two first sub-pixel columns through at least two data lines, and the second data bus being connected to the second type first color sub-pixels in the at least two first sub-pixel columns through at least two data lines. The at least one control switch group includes a plurality of control switches connected to the data bus group; the control switch group includes a first control switch and a second control switch, the first data bus being connected to each data line connected thereto through the first control switch, and the first data bus being connected to each data line connected thereto through the second control switch.

[0005] In some embodiments, the plurality of sub-pixels further comprises second color sub-pixels and third color sub-pixels; the display unit further comprises at least one column of second sub-pixel columns and at least one column of third sub-pixel columns arranged in sequence along the row direction, and the first sub-pixel column is located between the second sub-pixel column and the third sub-pixel column; the second sub-pixel column comprises second color sub-pixels and third color sub-pixels arranged in sequence along the column direction, and the third sub-pixel column comprises third color sub-pixels and second color sub-pixels arranged in sequence along the column direction; the data bus group further comprises a third data bus and a fourth data bus, the third data bus is connected with the second color sub-pixels of the at least one column of second sub-pixel columns and the at least one column of third sub-pixel columns through at least two data lines, and the fourth data bus is connected with the third color sub-pixels of the at least one column of second sub-pixel columns and the at least one column of third sub-pixel columns through at least two data lines; the plurality of control switches further comprises third control switches and fourth control switches, and each data line connected with the third data bus is connected with a third control switch, and each data line connected with the fourth data bus is connected with a fourth control switch.

[0006] In some embodiments, the data bus comprises a fan-out line, a transfer line, and at least two connection lines; the fan-out line is connected with the transfer line, the at least two connection lines are connected with the transfer line, and the connection line is connected with the control switch.

[0007] In some embodiments, the first data bus comprises a first fan-out line, a first transfer line, and at least two first connection lines; the first fan-out line is connected with the first transfer line, the at least two first connection lines are connected with the first transfer line, and the first connection line is connected with the first control switch; the second data bus comprises a second fan-out line, a second transfer line, and at least two second connection lines; the second fan-out line is connected with the second transfer line, the at least two second connection lines are connected with the second transfer line, and the second connection line is connected with the second control switch; the third data bus comprises a third fan-out line, a third transfer line, and at least two third connection lines; the third fan-out line is connected with the third transfer line, the at least two third connection lines are connected with the third transfer line, and the third connection line is connected with the third control switch; the fourth data bus comprises a fourth fan-out line, a fourth transfer line, and at least two fourth connection lines; the fourth fan-out line is connected with the fourth transfer line, the at least two fourth connection lines are connected with the fourth transfer line, and the fourth connection line is connected with the fourth control switch.

[0008] In some embodiments, the first transfer line, the second transfer line, the third transfer line and the fourth transfer line all extend along a row direction and are arranged along a column direction; the first fan-out line, the second fan-out line, the third fan-out line and the fourth fan-out line are all arranged on a side of the first transfer line, the second transfer line, the third transfer line and the fourth transfer line away from the plurality of sub-pixels; the first connection line, the second connection line, the third connection line and the fourth connection line all extend along a column direction and are arranged on a side of the first transfer line, the second transfer line, the third transfer line and the fourth transfer line close to the plurality of sub-pixels.

[0009] In some embodiments, the display unit includes at least four sub-pixels in the first row and at least four sub-pixels in the second row; the display panel further includes a plurality of control lines for controlling the control switches; at least two control switches corresponding to the connection of adjacent at least two sub-pixels in the same row are connected to the same control line.

[0010] In some embodiments, the display unit includes eight columns of sub-pixels adjacent to each other, and the display unit includes four columns of first sub-pixel columns, two columns of second sub-pixel columns and two columns of third sub-pixel columns; the display unit includes at least eight sub-pixels in the first row and at least eight sub-pixels in the second row, the eight sub-pixels in the first row are divided into a first group of sub-pixels and a second group of sub-pixels, and the eight sub-pixels in the second row are divided into a third group of sub-pixels and a fourth group of sub-pixels, each group of sub-pixels including four adjacent sub-pixels; the four control switches corresponding to the connection of the first group of sub-pixels are connected to a first control line, and the four control switches corresponding to the connection of the second group of sub-pixels are connected to a second control line; the four control switches corresponding to the connection of the third group of sub-pixels are connected to a third control line, and the four control switches corresponding to the connection of the fourth group of sub-pixels are connected to a fourth control line.

[0011] In some embodiments, the first control line, the second control line, the third control line and the fourth control line all extend along a row direction and are arranged along a column direction, the plurality of control switches are arranged between the plurality of control lines and the plurality of sub-pixels, the control switch includes an active layer pattern, a gate pattern, a first electrode pattern and a second electrode pattern, the gate pattern overlaps the active layer pattern, one end of the gate pattern is connected to the corresponding control line, the first electrode pattern is connected to the active layer pattern and connected to the corresponding data bus, the second electrode pattern is connected to the active layer pattern and connected to the corresponding data line; in the case that the data bus includes a fan-out line, a transfer line and at least two connection lines, the first electrode pattern is connected to one of the connection lines of the corresponding data bus.

[0012] In some embodiments, the display unit includes four adjacent columns of sub-pixels; the first data bus and the second data bus are the same data bus as a first common data bus, and the third data bus and the fourth data bus are the same data bus as a second common data bus; the first common data bus is connected to the first type of first color sub-pixels and the second type of first color sub-pixels in the two first sub-pixel columns through at least two data lines; and the second common data bus is connected to the second color sub-pixels and the third color sub-pixels of the second sub-pixel column and the third sub-pixel column through at least two data lines.

[0013] In some embodiments, the first common data bus includes a common first fan-out line, a common first adapter line, and at least two common first connection lines; the common first fan-out line is connected to the common first adapter line, and the at least two common first connection lines are connected to the common first adapter line, and one of the common first connection lines is connected to the first control switch and the second control switch corresponding to one column of sub-pixels; the second common data bus includes a common second fan-out line, a common second adapter line, and at least two common second connection lines; the common second fan-out line is connected to the common second adapter line, and the at least two common second connection lines are connected to the common second adapter line, and one of the common second connection lines is connected to the third control switch and the fourth control switch corresponding to one column of sub-pixels.

[0014] In some embodiments, the first common adapter line and the second common adapter line both extend in the row direction and are arranged in the column direction; the common first fan-out line and the common second fan-out line are disposed on a side of the common first adapter line and the common second adapter line away from the plurality of sub-pixels; and the common first connection line and the common second connection line are disposed on a side of the common first adapter line and the common second adapter line close to the plurality of sub-pixels.

[0015] In some embodiments, the display unit includes at least a first pixel group and a second pixel group located in a first row, and a second pixel group and a first pixel group located in a second row; the first pixel group includes a first type of first sub-pixel and a second sub-pixel, and the second pixel group includes a second type of first sub-pixel and a third sub-pixel; the display panel further includes a plurality of control lines for controlling the control switches; wherein the first control switch and the third control switch corresponding to the first pixel group in the first row are both connected to a first control line, and the second control switch and the fourth control switch corresponding to the second pixel group in the first row are both connected to a second control line; the second control switch and the fourth control switch corresponding to the second pixel group in the second row are both connected to a third control line, and the first control switch and the third control switch corresponding to the first pixel group in the second row are both connected to a fourth control line.

[0016] In some embodiments, the first control line, the second control line, the third control line and the fourth control line all extend along a row direction and are arranged along a column direction, two control switches corresponding to a column of sub-pixels form a shared control switch, the shared control switch is arranged between the plurality of control lines and the plurality of sub-pixels, the shared control switch comprises a shared active layer pattern, two gate patterns, a shared first electrode pattern and two second electrode patterns, the two gate patterns overlap with the shared active layer pattern, the two gate patterns are respectively located on two sides of the shared first electrode pattern, and one end of each of the gate patterns is connected with a corresponding control line, the shared first electrode pattern is connected with the shared active layer pattern and a corresponding data bus, the two second electrode patterns are connected with the active layer pattern, and the two second electrode patterns are respectively connected with corresponding data lines; in the case where the shared data bus comprises a shared fan-out line, a shared adapter line and at least two shared connection lines, the shared first electrode pattern is connected with one of the shared connection lines of the corresponding shared data bus.

[0017] In some embodiments, in the case where the display unit comprises at least four columns of sub-pixels, each of the four columns of sub-pixels comprises, in sequence, a second column of sub-pixels, a first column of first sub-pixels of a first type, a third column of sub-pixels and a first column of first sub-pixels of a second type, wherein the second column of sub-pixels, the first column of first sub-pixels of the first type and the third column of sub-pixels, the first column of first sub-pixels of the second type are mirror-symmetrically arranged, and the data lines connecting the second column of sub-pixels and the first column of first sub-pixels of the first type are mirror-symmetrically arranged with the data lines connecting the third column of sub-pixels and the first column of first sub-pixels of the second type.

[0018] In another aspect, a display device is provided. The display device comprises the display panel according to any one of the above aspects and a driving chip connected with the data bus group.

[0019] In yet another aspect, a driving method applied to the display panel according to any one of the above embodiments is provided. The driving method comprises: in a first time period t1 of a first scanning time, controlling the first data bus, the second data bus, the third data bus and the fourth data bus to respectively output display signals, and controlling the first control switch connected with the first column of first sub-pixels and the third control switch connected with the second column of sub-pixels in the display unit to be in an open state; and in a first time period t3 of a second scanning time, controlling the first data bus, the second data bus, the third data bus and the fourth data bus to respectively output display signals, and controlling the second control switch connected with the first column of first sub-pixels and the fourth control switch connected with the second column of sub-pixels in the display unit to be in an open state.

[0020] In some embodiments, the display unit includes eight adjacent columns of sub-pixels, the display unit includes a first sub-display unit and a second sub-display unit arranged along a row direction; the first sub-display unit includes four adjacent columns of sub-pixels, and the second sub-display unit includes four adjacent columns of sub-pixels; the driving method further includes: in a first time period of a first scanning time, controlling the first data bus, the second data bus, the third data bus and the fourth data bus to respectively output display signals, and controlling the second control switch connected to the second type of first sub-pixel column in the first sub-display unit, the fourth control switch connected to the third sub-pixel column, the first control switch connected to the first type of first sub-pixel column, and the third control switch connected to the second sub-pixel column to be in an open state; in a second time period of the first scanning time, controlling the first data bus, the second data bus, the third data bus and the fourth data bus to respectively output display signals, and controlling the first control switch connected to the first type of first sub-pixel column in the second sub-display unit, the second control switch connected to the second type of first sub-pixel column, the third control switch connected to the second sub-pixel column, and the fourth control switch connected to the third sub-pixel column to be in an open state; in a first time period of a second scanning time, controlling the first data bus, the second data bus, the third data bus and the fourth data bus to respectively output display signals, and controlling the first control switch connected to the second type of first sub-pixel column in the first sub-display unit, the third control switch connected to the third sub-pixel column, the second control switch connected to the first type of first sub-pixel column, and the fourth control switch connected to the second sub-pixel column to be in an open state; and in a second time period of the second scanning time, controlling the first data bus, the second data bus, the third data bus and the fourth data bus to respectively output display signals, and controlling the second control switch connected to the first type of first sub-pixel column in the second sub-display unit, the first control switch connected to the second type of first sub-pixel column, the fourth control switch connected to the second sub-pixel column, and the third control switch connected to the third sub-pixel column to be in an open state.

[0021] In some embodiments, in the second time period of the first scanning time, the first data bus, the second data bus, the third data bus and the fourth data bus are controlled to respectively output display signals, and the second control switch connected to the second type of first sub-pixel column and the fourth control switch connected to the third sub-pixel column in the display unit are controlled to be in an open state.

[0022] In a second time period of the second scanning time, the first data bus, the second data bus, the third data bus and the fourth data bus are controlled to output display signals respectively, and the first control switch connected to the second type of first sub-pixel column and the third control switch connected to the third sub-pixel column in the display unit are controlled to be in an open state. BRIEF DESCRIPTION OF DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the present disclosure, the drawings needed to be used in some embodiments of the present disclosure will be briefly introduced as follows. Obviously, the drawings in the following description are only some drawings of the embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art according to these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limited to the actual size, actual process, actual timing of signals, etc. of the products involved in the embodiments of the present disclosure.

[0024] FIG. 1 is a planar structure diagram of a display panel according to some embodiments of the present disclosure;

[0025] FIG. 2 is a driving timing diagram of a display panel according to some embodiments of the present disclosure;

[0026] FIG. 3A is a planar structure diagram of a display panel according to some embodiments of the present disclosure;

[0027] FIG. 3B is a driving timing diagram of a display panel according to some embodiments of the present disclosure;

[0028] FIG. 4 is another planar structure diagram of a display panel according to some embodiments of the present disclosure;

[0029] FIG. 5A is a planar structure diagram of a display panel according to some embodiments of the present disclosure;

[0030] FIG. 5B is a driving timing diagram of a display panel according to some embodiments of the present disclosure;

[0031] FIG. 6 is still another planar structure diagram of a display panel according to some embodiments of the present disclosure;

[0032] FIG. 7A is a planar structure diagram of a display panel according to some embodiments of the present disclosure;

[0033] FIG. 7B is a driving timing diagram of a display panel according to some embodiments of the present disclosure;

[0034] FIG. 8 is still another planar structure diagram of a display panel according to some embodiments of the present disclosure;

[0035] FIG. 9 is a planar structure diagram of a display panel according to some embodiments of the present disclosure;

[0036] FIG. 10 is a structure diagram of a driving pixel circuit of a display panel according to some embodiments of the present disclosure;

[0037] FIG. 11 is a plan structure diagram of a display device according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0038] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings. It should be apparent that the described embodiments are only a part of the embodiments of the present disclosure, and not all the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0039] Unless otherwise required by context, the term “comprise” and other forms of the term “comprise”, such as “comprises” and “comprising”, are used in an open, inclusive sense, that is, as “including, but not limited to”. In the description of the specification, the terms “one embodiment”, “some embodiments”, “exemplary embodiments”, “example”, “specific example” or “some examples” are intended to mean that a particular feature, structure, material, or characteristic included in at least one embodiment or example of the present disclosure. The illustrative representation of the above terms does not necessarily mean the same embodiment or example. In addition, the specific features, structures, materials or characteristics described can be included in any one or more embodiments or examples in any appropriate manner.

[0040] Hereinafter, the terms “first” and “second” are used only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with “first” and “second” can explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, the meaning of “a plurality of” is two or more, unless otherwise specified.

[0041] In describing some embodiments, "coupled" and "connected," along with their derivatives, can be used. It should be understood that these terms are not intended as synonyms for each other. Rather, "connected" can be used to indicate that two or more elements are in direct physical or electrical contact with each other. "Coupled" can be used to indicate that two or more elements are in either physical or electrical contact with each other, even at a remote location from each other. The term "coupled" or "communicatively coupled" can also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. The embodiments disclosed herein are not necessarily limited to any particular recited embodiment.

[0042] "at least one of A, B, and C" has the same meaning as "at least one of A, B, or C" and includes the following combinations for A, B, and C: A only, B only, C only, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C.

[0043] "at least one of A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0044] As used herein, the term "if' is, optionally, interpreted as meaning "when" or "while" or "in response to a determination" or "in response to a detection of," depending on the context. Similarly, the phrase "if determined" or "if detected [a stated condition or event]" is, optionally, interpreted as meaning "upon a determination" or "in response to a determination" or "upon a detection of [a stated condition or event]" or "in response to a detection of [a stated condition or event]," depending on the context.

[0045] The use of "adapted to" or "configured to," as used herein, means an open and inclusive language that does not exclude additional tasks or steps.

[0046] Additionally, the use of "based on" means an open and inclusive language that does not exclude additional conditions or values.

[0047] As used herein, "about," "approximately," or "circa" includes the recited value and the average value within an acceptable range of deviation from the stated value, as determined by one of ordinary skill in the art considering the measurement in question and the error in measuring the particular quantity (i.e., the limitations of the measurement system).

[0048] As used herein, "parallel," "perpendicular," "equal" include the recited condition and conditions approximating the recited condition within an acceptable range of deviation, where the acceptable range of deviation is as determined by one of ordinary skill in the art taking into account the measurement at issue and the error associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallel and near parallel, where the acceptable range of deviation for near parallel can be, for example, within 5 degrees of deviation; "perpendicular" includes absolute perpendicular and near perpendicular, where the acceptable range of deviation for near perpendicular can also be, for example, within 5 degrees of deviation. "Equal" includes absolute equality and near equality, where the acceptable range of deviation for near equality can be, for example, a difference between the two that is less than or equal to 5% of either.

[0049] It will be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers can also be present.

[0050] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are idealized examples. In the interest of clarity, not all of the circular features can be shown in the drawings. It will be appreciated that in the development of any such actual implementation, numerous implementation-specific decisions can be made. These implementation-specific decisions can include, for example, manufacturing processes that vary from the idealized examples shown in the drawings, and / or variations in shapes and / or dimensions of the regions. Thus, the exemplary embodiments are not to be construed as limited to the shapes and / or dimensions shown in the drawings, but rather, are to be construed broadly to include any and all shapes and / or dimensions that fall within the scope of the exemplary embodiments. For example, the etched regions shown as rectangular will typically have curved features. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the devices, and are not intended to limit the scope of the exemplary embodiments.

[0051] At present, in the display driving of display devices, a multiplexing driving scheme has been developed. Each source channel of a driving chip drives two or more sub-pixel columns in a time-division manner, so as to reduce the number of source channels on the basis of improving the display resolution, and achieve the effects of improving the resolution and reducing the manufacturing cost.

[0052] As shown in FIG. 1 and FIG. 2, in some embodiments, the display panel includes a plurality of arrayed sub-pixels P and a plurality of data lines DT (DT1- DT4, DT1'- DT4') arranged along a vertical direction, and a plurality of gate lines GT (GT1, GT2) extending along a horizontal direction. Each data line DT is connected to a plurality of sub-pixels in a same column of sub-pixels, for inputting a data signal to the corresponding connected sub-pixels, and a column of sub-pixels includes sub-pixels of multiple colors, such as red sub-pixels and blue sub-pixels. Each gate line is connected to a plurality of sub-pixels in a same row of sub-pixels, for controlling the sub-pixels to be turned on to write the data signal when turned on. The plurality of data lines are divided into multiple groups, each group of data lines is connected to a data channel D of a driving chip Q through a fan-out line FT, and a control switch K is arranged on a line connected to the data channel of each data line. The control switch can be a demultiplexer, and the control switches connected to the plurality of data lines are opened in turn in a time-division driving manner to input the data signal to the sub-pixels connected to the corresponding data lines. The plurality of gate lines are scanned row by row to control a plurality of rows of sub-pixels to be turned on in turn to input the data signal transmitted by the data lines to the corresponding sub-pixels. For example, each group of data lines includes four data lines (DT1, DT1', DT2, DT2'), the four data lines are connected to a fan-out line, and a control switch is arranged between the fan-out line and each data line. The four control switches are controlled by control lines MUX1-MUX4 to be opened in turn to input the data signal to the corresponding data lines in turn, and the data line inputs the corresponding data signal to the sub-pixel when the sub-pixel is turned on.

[0053] Since the gamma voltages corresponding to sub-pixels of different colors are different, and a fan-out line FT is connected to a plurality of data lines DT, and the plurality of data lines are connected to sub-pixels of different colors, the initial data signal in the fan-out line jumps between different color gamma voltages to generate additional power consumption. For example, as shown in FIG. 2, the fan-out line FT1 is responsible for driving the sub-pixels connected to the data lines DT1, DT1', DT2, and DT2', and the gamma voltage of the initial data signal transmitted by the fan-out line jumps between the red gamma voltage, the green gamma voltage, the blue gamma voltage, the green gamma voltage, and the red gamma voltage in turn. The number of jumps is frequent. Since each fan-out line needs to transmit the gamma voltages of the sub-pixels of multiple colors connected thereto, the number of jumps of the gamma voltage output by the data channel of the driving chip connected thereto is frequent. Frequent voltage jumps can cause high power consumption of the driving chip.

[0054] Based on this, some embodiments of the present disclosure provide a display panel, a display device, and a driving method of the display panel. By adjusting the line arrangement, different fan-out lines control different color gamma voltage ranges, the number of jumps of the initial data signal jumping between different color gamma voltages is reduced, power consumption is reduced, and the reliability of the display panel is improved.

[0055] The display panel, the display device and the driving method of the display panel provided by the present disclosure are introduced below.

[0056] As shown in FIG. 3A and FIG. 7A, some embodiments of the present disclosure provide a display panel 100, which includes a plurality of sub-pixels 10 arranged in an array, at least one data line group 30, at least one data bus group 40 and at least one control switch group 50.

[0057] The plurality of sub-pixels 10 includes first color sub-pixels 11, and the first color sub-pixels 11 include first type first color sub-pixels 111 and second type first color sub-pixels 112. The plurality of sub-pixels 10 includes at least one display unit 20, and the display unit 20 includes at least four columns of sub-pixels 10 arranged adjacently, at least two columns of sub-pixels 10 in the at least four columns of sub-pixels 10 are first sub-pixel columns 210, and one column of other sub-pixels is arranged between every two first sub-pixel columns 210. The at least two columns of first sub-pixel columns 210 include a first type first sub-pixel column 2101 and a second type first sub-pixel column 2102 arranged in sequence. The first type first sub-pixel column 2101 includes the first type first color sub-pixels 111 and the second type first color sub-pixels 112 arranged in sequence along the column direction Y, and the second type first sub-pixel column 2102 includes the second type first color sub-pixels 112 and the first type first color sub-pixels 111 arranged in sequence along the column direction Y.

[0058] As shown in FIG. 3A and FIG. 7A, the plurality of sub-pixels are arranged in an array, and are arranged into multiple rows along the row direction and multiple columns along the column direction. Taking the example that the display unit 20 includes four columns of sub-pixels arranged adjacently, two columns of sub-pixels 10 in the four columns of sub-pixels 10 are first sub-pixel columns 210, and the two columns of first sub-pixel columns 210 are not adjacent. In FIG. 3A, the first sub-pixel columns 210 are located in the second column and the fourth column respectively, and the sub-pixels in the second column are the first type first sub-pixel columns 2101, the sub-pixels in the fourth column are the second type first sub-pixel columns 2102, and the sub-pixels in the first column and the third column are other sub-pixels. It should be noted that the first sub-pixel columns 210 in FIG. 3A are only an example, and the two columns of first sub-pixel columns 210 can also be located in the first column and the third column, that is, the first column of sub-pixels is the first type first sub-pixel column 2101, and the third column of sub-pixels is the second type first sub-pixel column 2102.

[0059] Exemplarily, the first color sub-pixel 11 is a green sub-pixel, the first type of first color sub-pixel 111 can be regarded as a light green sub-pixel, and the second type of first color sub-pixel 112 can be regarded as a dark green sub-pixel, where the light green sub-pixel and the dark green sub-pixel are only for distinguishing the two types of first color sub-pixels, and do not represent the actual display of the lightness of green. The first type of first color sub-pixel 111 and the second type of first color sub-pixel 112 in the first type of first sub-pixel column 2101 and the second type of first sub-pixel column 2102 are arranged in opposite orders.

[0060] The at least one data line group 30 includes a plurality of data lines DT, and is connected with the display unit 20. Two data lines DT are connected with one column of sub-pixels 10, and one data line DT is connected with the same type of pixels in one column of sub-pixels 10.

[0061] As shown in FIG. 3A and FIG. 7A, one data line group 30 corresponds to one display unit 20. When the display unit 20 includes four adjacent columns of sub-pixels, the data line group 30 includes eight data lines DT. One column of sub-pixels 10 is connected with two data lines DT, for example, the first column of sub-pixels is connected with two data lines DT (DT1, DT1’), and the third column of sub-pixels is connected with two data lines DT (DT3, DT3’). The first type of first sub-pixel column 2101 (the second column of sub-pixels) is connected with two data lines DT (DT2, DT2’), and the first type of first color sub-pixel 111 is connected with the data line DT2, and the second type of first color sub-pixel 112 is connected with the data line DT2’. The second type of first sub-pixel column 2102 (the fourth column of sub-pixels) is connected with two data lines DT (DT4, DT4’), and the first type of first color sub-pixel 111 is connected with the data line DT4, and the second type of first color sub-pixel 112 is connected with the data line DT4’.

[0062] The at least one data bus group 40 includes a plurality of data buses 41, and the data bus group 40 is connected with the display unit 20. The data bus group 40 includes a first data bus 411 and a second data bus 412. The first data bus 411 is connected with the first type of first color sub-pixel 111 in at least two first sub-pixel columns 210 through at least two data lines DT, and the second data bus 412 is connected with the second type of first color sub-pixel 112 in at least two first sub-pixel columns 210 through at least two data lines DT.

[0063] As shown in FIG. 3A and FIG. 7A, one data bus group 40 corresponds to one display unit, and the data bus 41 is connected with the driving chip and the data line DT. The data bus 41 is configured to transmit the initial data signal provided by the driving chip to each data line connected therewith, and the data line transmits the data signal to the corresponding sub-pixel, so that the sub-pixel realizes display. The data bus group 40 includes a first data bus 411 and a second data bus 412. For example, the first data bus 411 and the second data bus 412 transmit the initial data signal required by the green sub-pixel. The first data bus 411 is connected with the first type of first color sub-pixel 111 in the two first sub-pixel columns 210 through two data lines DT2 and DT4, and the second data bus 412 is connected with the second type of first color sub-pixel 112 in the two first sub-pixel columns 210 through two data lines DT2' and DT4'. The black dot in the figure represents the connection between the data line and the sub-pixel.

[0064] The at least one control switch group 50 includes a plurality of control switches 51, and is connected with the data bus group 40. The control switch group 50 includes a first control switch K1 and a second control switch K2. The first data bus 411 is connected with the first control switch K1 between each data line DT connected therewith, and the first data bus 411 is connected with the second control switch K2 between each data line DT connected therewith.

[0065] As shown in FIG. 3A and FIG. 7A, one control switch group 50 corresponds to one data bus group 40, that is, one control switch group 50 corresponds to one display unit. The data bus group 40 is provided with the control switch 51 between each data line connected therewith. The control switch group 50 includes a first control switch K1 and a second control switch K2. The first data bus 411 is connected with the first control switch K1 between the two data lines DT2 and DT4 connected therewith, and the first data bus 411 is connected with the second control switch K2 between the two data lines DT2' and DT4' connected therewith.

[0066] In combination with FIG. 5B, the first data bus 411 transmits initial data signals required for the display of the first color sub-pixels (green sub-pixels), the second data bus 412 transmits initial data signals required for the display of the first color sub-pixels (green sub-pixels), and the first control switch K1 and the second control switch K2 are opened or closed in response to a control signal. When the first control switch K1 is opened, the first data bus 411 transmits the initial data signals to at least two data lines (data lines DT2 and DT4) through the first control switch K1, thereby controlling the first type of first color sub-pixels 111 in at least two first sub-pixel columns 210 connected to the data lines to display. When the second control switch K2 is opened, the second data bus 412 transmits the initial data signals to at least two data lines (data lines DT2' and DT4') through the second control switch K2, thereby controlling the second type of first color sub-pixels 112 in at least two first sub-pixel columns 210 connected to the data lines to display.

[0067] With the above-described connection and arrangement of the lines in the display panel, on the one hand, the first data bus 411 is connected to the first type of first color sub-pixels 111 through corresponding data lines DT, and the second data bus 412 is connected to the second type of first color sub-pixels 112 through corresponding data lines DT, for example, the first type of first color sub-pixels 111 and the second type of first color sub-pixels 112 are both green sub-pixels, that is, the first data bus 411 and the second data bus 412 control the gamma voltage range of the same color, so that the initial data signals transmitted by the first data bus and the second data bus do not need to jump between different color gamma voltages, thereby reducing the number of times the first data bus 411 and the second data bus 412 jump between different color gamma voltages, thereby reducing power consumption and improving the quality and service life of the display panel. On the other hand, the plurality of sub-pixel arrays in the display unit 20 in the display panel 100 are arranged, each column of sub-pixels is connected to two data lines, and the two data lines are connected to different data buses. The connection of the above-described data lines to the corresponding sub-pixels can ensure that the line arrangement is more orderly, ensure the consistency of the line connection in the first sub-pixel column and other sub-pixel columns, and be conducive to the uniformity of the data signals received by each sub-pixel column, ensure the brightness consistency of the display unit 20, and improve the uniformity of the display.

[0068] In some embodiments, continuing to refer to FIG. 3A and FIG. 7A, the plurality of sub-pixels 10 further comprises second color sub-pixels 12 and third color sub-pixels 13; the display unit 20 further comprises at least one second sub-pixel column 220 and at least one third sub-pixel column 230 arranged in sequence along the row direction X, and the first sub-pixel column 210 is located between the second sub-pixel column 220 and the third sub-pixel column 230; the second sub-pixel column 220 comprises second color sub-pixels 12 and third color sub-pixels 13 arranged in sequence along the column direction Y, and the third sub-pixel column 230 comprises third color sub-pixels 13 and second color sub-pixels 12 arranged in sequence along the column direction Y. Wherein, one column of other sub-pixels is arranged between every two first sub-pixel columns, and the one column of other sub-pixels is the second sub-pixel column 220 or the third sub-pixel column 230.

[0069] For example, the second color sub-pixel 12 is a red sub-pixel, the third color sub-pixel 13 is a green sub-pixel, and the display unit 20 comprises four sub-pixel columns, which are the second sub-pixel column 220, the first type first sub-pixel column 2101, the third sub-pixel column 230, and the second type first sub-pixel column 2102 arranged in sequence, and the arrangement order of the second color sub-pixels 12 and the third color sub-pixels 13 in the second sub-pixel column 220 and the third sub-pixel column 230 is opposite.

[0070] The data bus group 40 further comprises a third data bus 413 and a fourth data bus 414, the third data bus 413 is connected with the second color sub-pixels 12 of the at least one second sub-pixel column 220 and the at least one third sub-pixel column 230 through at least two data lines DT, and the fourth data bus 414 is connected with the third color sub-pixels 13 of the at least one second sub-pixel column 220 and the at least one third sub-pixel column 230 through at least two data lines DT. The plurality of control switches K further comprises a third control switch K3 and a fourth control switch K4, and the third control switch K3 is connected between the third data bus 413 and each data line DT connected with the third data bus 413, and the fourth control switch K4 is connected between the fourth data bus 414 and each data line DT connected with the fourth data bus 414.

[0071] For example, the third data bus 413 is connected with the second color sub-pixels 12 of the second sub-pixel column 220 and the third sub-pixel column 230 through two data lines DT (data lines DT1 and DT3), and the third control switch K3 is connected between the third data bus 413 and the two data lines DT; and the fourth data bus 414 is connected with the third color sub-pixels 13 of the second sub-pixel column 220 and the third sub-pixel column 230 through two data lines DT (data lines DT1' and DT3'), and the fourth control switch K4 is connected between the fourth data bus 414 and the two data lines DT.

[0072] In combination with FIG. 3B, the first data bus 411 transmits initial data signals required for the display of the first color sub-pixels (green sub-pixels), the second data bus 412 transmits initial data signals required for the display of the first color sub-pixels (green sub-pixels), the third data bus 413 transmits initial data signals required for the display of the second color sub-pixels (red sub-pixels), the fourth data bus 414 transmits initial data signals required for the display of the third color sub-pixels (blue sub-pixels), and the first control switch K1, the second control switch K2, the third control switch K3, and the fourth control switch K4 are opened or closed in response to control signals. When the first control switch K1 is opened, the first data bus 411 transmits initial data signals to at least two data lines (data lines DT2 and DT4) through the first control switch K1, thereby controlling the first type of first color sub-pixels 111 in at least two first sub-pixel columns 210 connected to the data lines to display. When the second control switch K2 is opened, the second data bus 412 transmits initial data signals to at least two data lines (data lines DT2' and DT4') through the second control switch K2, thereby controlling the second type of first color sub-pixels 112 in at least two first sub-pixel columns 210 connected to the data lines to display. When the third control switch K3 is opened, the third data bus 413 transmits initial data signals to at least two data lines (data lines DT1 and DT3) through the third control switch K3, thereby controlling the second color sub-pixels 12 in at least two second sub-pixel columns 220 connected to the data lines to display. When the fourth control switch K4 is opened, the fourth data bus 414 transmits initial data signals to at least two data lines (data lines DT1' and DT3') through the fourth control switch K4, thereby controlling the third color sub-pixels 13 in at least two third sub-pixel columns 230 connected to the data lines to display.

[0073] For example, the control lines 61, 62, 63, and 64 sequentially input working levels, the control switches corresponding to the control lines are sequentially opened, and data signals are sequentially filled into the data lines connected to the control switches. For example, as shown in FIG. 3B, data signals are simultaneously filled into DT1 and DT2, then DT3' and DT4', then DT1' and DT2', and finally DT3 and DT4. When the gate lines GT1 and GT2 control the opening of the corresponding row of sub-pixels, the sub-pixels display under the control of the data signals. Thus, the display sequence of the two rows and four columns of sub-pixels in FIG. 3A is from top to bottom and from left to right, first the red sub-pixels (12) and the green sub-pixels (111) display, then the blue sub-pixels (13) and the green sub-pixels (112) display, then the blue sub-pixels (13) and the green sub-pixels (112) display, and finally the red sub-pixels (12) and the green sub-pixels (111) display.

[0074] It should be noted that the third data bus 413 is connected with the second color sub-pixel 12 through the corresponding data line DT, the fourth data bus 414 is connected with the third color sub-pixel 13 through the corresponding data line DT, for example, the second color sub-pixel 12 is a red sub-pixel, the third color sub-pixel 13 is a blue sub-pixel, the third data bus 413 and the fourth data bus 414 control the gamma voltage range of the second color sub-pixel 12 and the third color sub-pixel 13 respectively, and the third data bus 413 and the fourth data bus 414 are arranged in this way to correspond to control the threshold voltage compensation time and the voltage range of the corresponding color sub-pixel, so as to avoid additional power consumption caused by frequent jumps between the voltages of the red and blue sub-pixels. In combination with the foregoing content, the first data bus 411 is connected with the first color sub-pixel 111 of the first type through the corresponding data line DT, and the second data bus 412 is connected with the first color sub-pixel 112 of the second type through the corresponding data line DT, that is, the first data bus 411 and the second data bus 412 control the gamma voltage range of the green sub-pixel, that is, the number of times of jumps of the data voltage transmitted by the data bus 41 between the red, green and blue sub-pixels is reduced, thereby reducing the power consumption of the display panel, improving the quality and service life of the display panel, and further enhancing the picture display. In addition, since each column of sub-pixels is connected with two data lines, each data line controls the same type of sub-pixel in each column of sub-pixels, the arrangement of each data line and the connection with the data bus are consistent, and in combination with FIG. 5B, the jump frequency of the gamma voltage of the data signal transmitted by each data line is consistent, for example, the jump frequency of the red gamma voltage transmitted by the data line DT1 is consistent with the jump frequency of the green gamma voltage transmitted by the data line DT1', at least two adjacent sub-pixels in the row direction can display at the same time, which is beneficial to further improve the uniformity of the data signal received by each column of sub-pixels, reduce the difference between each data line, ensure the uniformity of the brightness of the display unit 20, and improve the uniformity of the display.

[0075] In some embodiments, continuing to refer to FIGS. 3A and 4, the data bus 41 includes a fan-out line 410, a transfer line 420, and at least two connection lines 430; the fan-out line 410 is connected with the transfer line 420, the at least two connection lines 430 are connected with the transfer line 420, and the connection line 430 is connected with the control switch K.

[0076] It can be understood that the fan-out line is connected with the data channel of the driving chip, the adapter line 420 is arranged, the adapter line 420 is connected with at least two connection lines 430, the connection line is connected with the corresponding data line DT, the initial data signal output by the driving chip can be transmitted to the plurality of connection lines 430 through the adapter line, and then transmitted to the corresponding data line. The control switch is arranged between the adapter line and the data line, and the data signal corresponding to the data line in the initial data signal transmitted by the data bus is transmitted to the data line by opening or closing the control switch. Such an arrangement can realize connection of one data bus to a plurality of data lines, and simplify the line of the fan-out line 410 part of the data bus 41, thereby reducing the number of fan-out lines 410 in the data bus group 40 in the display panel 100, further simplifying the line arrangement of the data bus group 40, and reducing the signal interference phenomenon between different data buses 41.

[0077] In some embodiments, as shown in FIG. 3A, the first data bus 411 includes a first fan-out line 411a, a first adapter line 411b and at least two first connection lines 411c; the first fan-out line 411a is connected with the first adapter line 411b, the at least two first connection lines 411c are connected with the first adapter line 411b, and the first connection line 411c is connected with the first control switch K1. The second data bus 412 includes a second fan-out line 412a, a second adapter line 412b and at least two second connection lines 412c; the second fan-out line 412a is connected with the second adapter line 412b, the at least two second connection lines 412c are connected with the second adapter line 412b, and the second connection line 412c is connected with the second control switch K2. The third data bus 413 includes a third fan-out line 413a, a third adapter line 413b and at least two third connection lines 413c; the third fan-out line 413a is connected with the third adapter line 413b, the at least two third connection lines 413c are connected with the third adapter line 413b, and the third connection line 413c is connected with the third control switch K3. The fourth data bus 414 includes a fourth fan-out line 414a, a fourth adapter line 414b and at least two fourth connection lines 414c; the fourth fan-out line 414a is connected with the fourth adapter line 414b, the at least two fourth connection lines 414c are connected with the fourth adapter line 414b, and the fourth connection line 414b is connected with the fourth control switch K4.

[0078] Exemplarily, as shown in FIG. 3A, the first data bus 411 includes a first fan-out line 411a, a first adapter line 411b, and two first connection lines 411c; the first fan-out line 411a is connected with the first adapter line 411b, the two first connection lines 411c are connected with the first adapter line 411b, and each of the first connection lines 411c is connected with a first control switch K1, one of the first control switches K1 is connected with a data line DT2, and the data line DT2 is connected with the first color sub-pixel 111 of the first type through the data line DT2, and the other first control switch K1 is connected with a data line DT4, and the data line DT4 is connected with the first color sub-pixel 111 of the first type through the data line DT4. Similarly, the second data bus 412, the third data bus 413, and the fourth data bus 414 are connected with the second color sub-pixel 12, the third color sub-pixel 13, and the second color sub-pixel 112 of the first type through corresponding data lines respectively.

[0079] Exemplarily, as shown in FIG. 5A, the first data bus 411 includes a first fan-out line 411a, a first adapter line 411b, and four first connection lines 411c; the first fan-out line 411a is connected with the first adapter line 411b, the four first connection lines 411c are connected with the first adapter line 411b, and each of the first connection lines 411c is connected with a first control switch K1, the four first control switches K1 are connected with data lines DT2, DT4, DT6, and DT8 respectively, and the data lines DT2, DT4, DT6, and DT8 are connected with corresponding first color sub-pixels 111 of the first type respectively. Similarly, the second data bus 412, the third data bus 413, and the fourth data bus 414 are connected with the second color sub-pixel 12, the third color sub-pixel 13, and the second color sub-pixel 112 of the first type through corresponding data lines respectively.

[0080] In some embodiments, the film layer wiring design of the data bus and the data line in the display panel is introduced as follows.

[0081] As shown in FIG. 4, the first adapter line 411b, the second adapter line 412b, the third adapter line 413b, and the fourth adapter line 414b all extend along the row direction X and are arranged along the column direction Y; the first fan-out line 411a, the second fan-out line 412a, the third fan-out line 413a, and the fourth fan-out line 414a are all arranged on the side of the first adapter line 411b, the second adapter line 412b, the third adapter line 413b, and the fourth adapter line 414b away from the plurality of sub-pixels 10; the first connection line 411c, the second connection line 412c, the third connection line 413c, and the fourth connection line 414c all extend along the column direction Y and are arranged on the side of the first adapter line 411b, the second adapter line 412b, the third adapter line 413b, and the fourth adapter line 414b close to the plurality of sub-pixels 10.

[0082] It should be noted that the display panel 100 includes a display area AA and a frame area BB, the frame area BB is arranged at least one side of the display area AA, a plurality of sub-pixels and a plurality of data lines are arranged in the display area AA, and the data bus group and the control switch group are located in the peripheral area BB.

[0083] The first fan-out line 411a, the second fan-out line 412a, the third fan-out line 413a and the fourth fan-out line 414a are used to transmit the initial data signal from the frame area BB to the display area AA, and are respectively connected to the at least two first connection lines 411c, the at least two second connection lines 412c, the at least two third connection lines 413c and the at least two fourth connection lines 414c through the first adapter line 411b, the second adapter line 412b, the third adapter line 413b and the fourth adapter line 414b, and the data voltage signal is transmitted to the corresponding sub-pixel 10 by the first connection line 411c, the second connection line 412c, the third connection line 413c and the fourth connection line 414c, so that according to the signal transmission mode combined with FIG. 4, the first adapter line 411b, the second adapter line 412b, the third adapter line 413b and the fourth adapter line 414b are close to the display area AA relative to the first fan-out line 411a, the second fan-out line 412a, the third fan-out line 413a and the fourth fan-out line 414a, the first connection line 411c, the second connection line 412c, the third connection line 413c and the fourth connection line 414c are close to the display area AA relative to the first adapter line 411b, the second adapter line 412b, the third adapter line 413b and the fourth adapter line 414b, and the first fan-out line 411a, the second fan-out line 412a, the third fan-out line 413a and the fourth fan-out line 414a are far away from the display area AA, which is convenient for connection with the driving chip, and the above-mentioned line arrangement is regular, which can reduce the signal interference phenomenon between different data buses 41.

[0084] Exemplarily, referring to FIG. 4, the display panel includes a substrate, and a first gate layer 102, a second gate layer 103, a first source-drain metal layer 104 and a second source-drain metal layer 105 are arranged on the substrate in a stack. Among them, a plurality of fan-out lines can be located in the first gate layer 102 or the second gate layer 103, for example, two adjacent fan-out lines are located in different gate layers to share the wiring pressure and improve the space utilization rate, the distance between the adjacent fan-out lines in the same layer is increased, and the short-circuit probability is reduced. For example, the first fan-out line 411a and the third fan-out line 413a are located in the second gate layer 103, and the second fan-out line 412a and the fourth fan-out line 414a are located in the first gate layer 102, or the first fan-out line 411a and the third fan-out line 413a are located in the first gate layer 102, and the second fan-out line 412a and the fourth fan-out line 414a are located in the second gate layer 103.

[0085] The first transfer line 411b, the second transfer line 412b, the third transfer line 413b and the fourth transfer line 414b are located in the first source-drain metal layer 104, and the first connection line 411c, the second connection line 412c, the third connection line 413c and the fourth connection line 414c are located in the second gate layer 103. The first fan-out line 411a and the second fan-out line 412a located in the first gate layer 102 are alternately arranged with the third fan-out line 413a and the fourth fan-out line 414a located in the second gate layer 103. The layered wiring mode can increase the wiring space, and the interval between adjacent two lines is large, so that the short circuit phenomenon is less likely to occur, and the reliability of the display panel is improved.

[0086] In some embodiments, as shown in FIG. 3A, the display unit 20 includes at least four sub-pixels 10 located in the first row H1 and at least four sub-pixels 10 located in the second row H2; the display panel 100 further includes a plurality of control lines 60 for controlling the control switches K; at least two control switches K1 corresponding to the connection of adjacent at least two sub-pixels 10 in the same row are connected with the same control line 60.

[0087] In some examples, referring to FIG. 3A, the display unit 20 includes four columns of adjacent sub-pixels, including four sub-pixels 10 located in the first row H1, which are a red sub-pixel, a green sub-pixel, a blue sub-pixel and a green sub-pixel in sequence, and four sub-pixels 10 located in the second row H2, which are a blue sub-pixel, a green sub-pixel, a red sub-pixel and a green sub-pixel in sequence; wherein the four sub-pixels 10 in the first row H1 are sequentially connected with the third control switch K3, the first control switch K1, the fourth control switch K4 and the second control switch K2, as shown in FIG. 3A, the third control switch K3 and the first control switch K1 are connected with the same control line 61, and the fourth control switch K4 and the second control switch K2 are connected with the same control line 62. Similarly, the fourth control switch K4 and the second control switch K2 connected in sequence in the four sub-pixels 10 in the second row H2 are connected with the same control line 63, and the third control switch K3 and the first control switch K1 are connected with the same control line 64.

[0088] In other examples, referring to FIGS. 5A and 6, the display unit 20 includes eight columns of adjacent sub-pixels 10, and the display unit 20 includes four columns of first sub-pixel columns 210, two columns of second sub-pixel columns 220 and two columns of third sub-pixel columns 230; the display unit 20 includes at least eight sub-pixels 10 located in the first row H1 and eight sub-pixels 10 located in the second row H1, and the eight sub-pixels 10 in the first row are divided into a first group of sub-pixels 10a and a second group of sub-pixels 10b, and the eight sub-pixels 10 in the second row are divided into a third group of sub-pixels 10c and a fourth group of sub-pixels 10d, each group of sub-pixels 10 includes four adjacent sub-pixels 10.

[0089] The first group of sub-pixels 10a and the second group of sub-pixels 10b are red sub-pixels, green sub-pixels, blue sub-pixels and green sub-pixels respectively, and the third group of sub-pixels 10c and the fourth group of sub-pixels 10d are blue sub-pixels, green sub-pixels, red sub-pixels and green sub-pixels respectively.

[0090] The four control switches K connected to the first group of sub-pixels 10a are connected to the first control line 61, and the four control switches K connected to the second group of sub-pixels 10b are connected to the second control line 62; the four control switches connected to the third group of sub-pixels 10c are connected to the third control line 63; and the four control switches K connected to the fourth group of sub-pixels 10d are connected to the fourth control line 64.

[0091] Exemplarily, the first control switch K1, the second control switch K2, the third control switch K3 and the fourth control switch K4 connected to the first group of sub-pixels 10a are connected to the first control line 61, and the first control switch K1, the second control switch K2, the third control switch K3 and the fourth control switch K4 connected to the second group of sub-pixels 10b are connected to the second control line 62; the first control switch K1, the second control switch K2, the third control switch K3 and the fourth control switch K4 connected to the third group of sub-pixels 10c are connected to the third control line 63; and the first control switch K1, the second control switch K2, the third control switch K3 and the fourth control switch K4 connected to the fourth group of sub-pixels 10d are connected to the fourth control line 64.

[0092] For example, the first control line 61 controls the first control switch K1, the second control switch K2, the third control switch K3 and the fourth control switch K4 connected to the first group of sub-pixels 10a to open, and the sub-pixels in the first group of sub-pixels 10a are in a display state. The first control line 61, the second control line 62, the third control line 63 and the fourth control line 64 output control signals in turn, and control the control switches connected thereto to open in turn, so that the sub-pixels in the first group of sub-pixels 10a, the sub-pixels in the second group of sub-pixels 10a, the sub-pixels in the third group of sub-pixels 10c and the sub-pixels in the fourth group of sub-pixels 10d are displayed in turn.

[0093] Exemplarily, referring to FIG. 5A and FIG. 6, the first data bus 411 is connected with the first color sub-pixels 111 in the four columns of the first sub-pixel columns 210 through four data lines DT2, DT4, DT6, and DT8, and the second data bus 412 is connected with the second color sub-pixels 112 in the four columns of the first sub-pixel columns 210 through four data lines DT2', DT4', DT6', and DT8'; the third data bus 413 is connected with the second color sub-pixels 12 in the two columns of the second sub-pixel columns 220 and the two columns of the third sub-pixel columns 230 through four data lines DT1, DT3, DT5, and DT7, and the fourth data bus 414 is connected with the third color sub-pixels 13 in the two columns of the second sub-pixel columns 220 and the two columns of the third sub-pixel columns 230 through four data lines DT1', DT3', DT5', and DT7'.

[0094] It should be noted that each data bus 41 is connected with four data lines DT in one display unit 20, and the four data lines are connected with sub-pixels of the same color. In this way, on the one hand, the number of fan-out lines in the data bus 41 can be reduced, and the line arrangement can be simplified; on the other hand, each data bus 41 controls the gamma voltage of one color, further controls the threshold voltage compensation time and voltage range of the corresponding sub-pixels of one color, and thus the extra power consumption caused by the jump between different colors can be eliminated, and the quality and service life of the display panel 100 can be improved.

[0095] In some embodiments, the following introduces the film layer wiring design of the control lines and control switches in the display panel.

[0096] Referring to FIG. 4, the first control line 61, the second control line 62, the third control line 63, and the fourth control line 64 all extend along the row direction X and are arranged along the column direction Y, and the control switch K is arranged between the plurality of control lines 60 and the plurality of sub-pixels 10. The control switch K includes an active layer pattern 50a, a gate pattern 50b, a first electrode pattern 50c, and a second electrode pattern 50d. The gate pattern 50b overlaps the active layer pattern 50a, and one end of the gate pattern 50b is connected with the corresponding control line 60. The first electrode pattern 50c is connected with the active layer pattern 50a and the corresponding data bus 41. The second electrode pattern 50d is connected with the active layer pattern 50a and the corresponding data line DT. In the case that the data bus 41 includes the fan-out line 410, the adapter line 420, and at least two connection lines 430, the first electrode pattern 50c is connected with one connection line 430 of the corresponding data bus 41.

[0097] The first control line 61, the second control line 62, the third control line 63 and the fourth control line 64, and the plurality of control switches are arranged in the peripheral region BB, the plurality of control switches are arranged along the row direction X, and two control switches correspond to one column of sub-pixels, and the two control switches are arranged on one side of the column of sub-pixels. From the direction Z of the peripheral region to the display region, a plurality of fan-out lines, a plurality of transfer lines, a plurality of control lines, a plurality of control switches and a plurality of sub-pixels are arranged in sequence, and the connection lines cross the plurality of control lines and connect the transfer lines and the control switches.

[0098] Exemplarily, the display panel further comprises an active layer 101 arranged between the substrate and the first gate layer, wherein the first control line 61, the second control line 62, the third control line 63 and the fourth control line 64 are arranged in the first source-drain metal layer 104, the active layer pattern 50a of the plurality of control switches K is arranged in the active layer 101, the first electrode pattern 50c and the second electrode pattern 50d are arranged in the first source-drain metal layer 104, and the gate pattern 50b is arranged in the first gate layer 102.

[0099] In some embodiments, referring to FIG. 7A, the display unit 20 comprises four adjacent columns of sub-pixels 10; the first data bus 411 and the second data bus 412 are the same data bus, serving as the first common data bus 401, and the third data bus 413 and the fourth data bus 414 are the same data bus, serving as the second common data bus 402; the first common data bus 401 is connected to the first type of first color sub-pixel 111 and the second type of first color sub-pixel 112 in the two first sub-pixel columns 210 through at least two data lines DT; and the second common data bus 402 is connected to the second color sub-pixel 12 and the third color sub-pixel 13 of the second sub-pixel column 220 and the third sub-pixel column 230 through at least two data lines DT.

[0100] Exemplarily, referring to FIG. 7A, the display unit 20 includes four adjacent sub-pixel columns 10, in sequence, a second sub-pixel column 220, a first sub-pixel column 2101 of the first type, a third sub-pixel column 230, and a first sub-pixel column 2102 of the second type, wherein the first common data bus 401 is connected with the first color sub-pixels 111 of the first type and the second color sub-pixels 112 of the second type through corresponding data lines DT, and the second common data bus 402 is connected with the second color sub-pixels 12 and the third color sub-pixels 13 through corresponding data lines DT. For example, the first color sub-pixels 111 of the first type and the second color sub-pixels 112 of the second type are both green sub-pixels, that is, the first common data bus 401 controls the gamma voltage range of the same color, and the second common data bus 402 controls the gamma voltage range of the other two colors. In this way, the number of times of jumping between different color gamma voltages of the first common data bus 401 and the second common data bus 402 is reduced. Exemplarily, referring to FIG. 7B, in the initial data signal transmitted by the second common data bus 402, two red gamma voltages are adjacent, and two blue gamma voltages are adjacent. Compared with the data voltage transmitted by the data bus in some technologies (such as FIG. 1 and FIG. 2), the number of times of gamma voltage jumping of the initial data signal transmitted by the second common data bus 402 is halved, and the gamma voltage jumping range is reduced. The first common data bus 401 does not jump the gamma voltage, which can reduce power consumption and improve the quality and service life of the display panel.

[0101] In some embodiments, as shown in FIG. 7A, the first common data bus 401 includes a common first fan-out line 401a, a common first adapter line 401b, and at least two common first connection lines 401c; the common first fan-out line 401a is connected with the common first adapter line 401b, the at least two common first connection lines 401c are connected with the common first adapter line 401b, and one common first connection line 401c is connected with the first control switch K1 and the second control switch K2 corresponding to one column of sub-pixels 10; the second common data bus 402 includes a common second fan-out line 402a, a common second adapter line 402b, and at least two common second connection lines 402c; the common second fan-out line 402a is connected with the common second adapter line 402b, the at least two common second connection lines 402c are connected with the common second adapter line 402b, and one common second connection line 402c is connected with the third control switch K3 and the fourth control switch K4 corresponding to one column of sub-pixels 10.

[0102] Exemplarily, referring to FIG. 7A, the first common data bus 401 includes a common first fan-out line 401a, a common first transition line 401b, and two common first connection lines 401c, the common first fan-out line 401a is connected with the common first transition line 401b, the two common first connection lines 401c are connected with the common first transition line 401b, and one common first connection line 401c is connected with the first control switch K1 and the second control switch K2 corresponding to one column of sub-pixels 10, wherein the first control switch K1 corresponding to one column of sub-pixels is connected with the corresponding first-type first-color sub-pixel 111 through the data line DT2, and the second control switch K2 is connected with the corresponding second-type first-color sub-pixel 112 through the data line DT2'. The first control switch K1 corresponding to another column of sub-pixels is connected with the corresponding first-type first-color sub-pixel 111 through the data line DT4, and the second control switch K2 is connected with the corresponding second-type first-color sub-pixel 112 through the data line DT4'. Similarly, the second common data bus 402 is connected with the second-type first-color sub-pixel 112, the second-color sub-pixel 12, and the third-color sub-pixel 13 through the corresponding data lines respectively.

[0103] In some embodiments, the film layer routing design of the common data bus and the data line in the display panel is introduced below.

[0104] Referring to FIG. 8, the common first transition line 401b and the second common transition line 402b both extend along the row direction X and are arranged along the column direction Y; the common first fan-out line 401a and the common second fan-out line 402a are arranged on the side of the common first transition line 401b and the common second transition line 402b away from the plurality of sub-pixels 10; and the common first connection line 401c and the common second connection line 402c are arranged on the side of the common first transition line 401b and the common second transition line 402b close to the plurality of sub-pixels 10.

[0105] Exemplarily, it should be noted that the display panel 100 includes a display area AA and a frame area BB, the frame area BB is arranged on at least one side of the display area AA, the plurality of sub-pixels and the plurality of data lines are arranged in the display area AA, and the data bus group and the control switch group are arranged in the peripheral area BB.

[0106] The common first fan-out line 401a and the common second fan-out line 402a are used to transmit a data voltage signal from the border area BB to the display area AA, are connected to the at least two common first connection lines 401c and the at least two common second connection lines 402c through the common first transfer line 401b and the common second transfer line 402b respectively, and the data voltage signal is transmitted to the corresponding sub-pixel 10 through the common first connection line 401c and the common second connection line 402c. Therefore, according to the signal transmission mode shown in FIG. 8, the common first transfer line 401b and the common second transfer line 402b are close to the display area AA relative to the common first fan-out line 401a and the common second fan-out line 402a, the common first connection line 401c and the common second connection line 402c are close to the display area AA relative to the common first transfer line 401b and the common second transfer line 402b, and the common first fan-out line 401a and the common second fan-out line 402a are far away from the display area AA, which is convenient for connection with the driving chip. The above-mentioned regular arrangement of lines can reduce the signal interference phenomenon between different data buses 41.

[0107] Exemplarily, the display panel includes a substrate, and a first gate layer 102, a second gate layer 103, a first source-drain metal layer 104 and a second source-drain metal layer 105 which are stacked on the substrate. The plurality of common fan-out lines can be located in the first gate layer 102 or the second gate layer 103. For example, the common first fan-out line 401a is located in the second gate layer 103, and the common second fan-out line 402a is located in the first gate layer 102, or the common second fan-out line 402a is located in the first gate layer 102, and the common first fan-out line 401a is located in the second gate layer 103. The common first transfer line 401b and the common second transfer line 402b are located in the first source-drain metal layer 104, and the common first connection line 401c and the common second connection line 402c are located in the second gate layer 102. The above-mentioned arrangement of the common second fan-out line 402a located in the first gate layer 102 and the common first fan-out line 401a located in the second gate layer 103 alternately, and the above-mentioned layered wiring mode can increase the wiring space, and the interval between the adjacent two lines is large, so that the short circuit phenomenon is not easy to occur, and the reliability of the display panel is improved.

[0108] In some embodiments, as shown in FIG. 7A, the display unit 20 at least includes a first pixel group 21 and a second pixel group 22 located in the first row H1, and the second pixel group 22 and the first pixel group 21 located in the second row H2. The first pixel group 21 includes the first color sub-pixel 11 and the second color sub-pixel 12, and the second pixel group 22 includes the second color sub-pixel 12 and the third color sub-pixel 13. The display panel 100 further includes a plurality of control lines 60 for controlling the control switch K.

[0109] The first control switch K1 and the third control switch K3 corresponding to the first pixel group 21 of the first row H1 are connected with the first control line 61, and the second control switch K2 and the fourth control switch K4 corresponding to the second pixel group 22 of the first row H1 are connected with the second control line 62; the second control switch K2 and the fourth control switch K4 corresponding to the second pixel group 22 of the second row H2 are connected with the third control line 63, and the first control switch K1 and the third control switch K3 corresponding to the first pixel group 21 of the second row H2 are connected with the fourth control line 64.

[0110] For example, referring to FIG. 7A, the display unit 20 includes the first pixel group 21 and the second pixel group 22 in the first row H1, the second pixel group 22 and the first pixel group 21 in the second row H2, the first pixel group 21 includes a red sub-pixel and a green sub-pixel in sequence, and the second pixel group 22 includes a blue sub-pixel and a green sub-pixel in sequence; the third control switch K3 and the first control switch K1 corresponding to the first pixel group 21 of the first row H1 are connected with the first control line 61 in sequence, and the fourth control switch K4 and the second control switch K2 corresponding to the second pixel group 22 of the first row H1 are connected with the second control line 62, as shown in FIG. 7A, the third control switch K3 and the first control switch K1 are connected with the same control line 61, and the fourth control switch K4 and the second control switch K2 are connected with the same control line 62. Similarly, the fourth control switch K4 and the second control switch K2 corresponding to the second pixel group 22 of the second row H2 are connected with the third control line 63 in sequence, and the third control switch K3 and the first control switch K1 corresponding to the first pixel group 21 of the second row H2 are connected with the fourth control line 64 in sequence.

[0111] For example, the first control line 61 controls the first control switch K1 and the third control switch K3 corresponding to the first pixel group 21 of the first row H1 to be opened, and the sub-pixels in the first pixel group 21 are in a display state; the second control line 62 controls the second control switch K2 and the fourth control switch K4 corresponding to the second pixel group 22 of the first row H1 to be opened, and the sub-pixels in the second pixel group 22 are in a display state. The first control line 61, the second control line 62, the third control line 63 and the fourth control line 64 output control signals in sequence, and control the control switches connected thereto to be opened in sequence, so that the sub-pixels in the first pixel group 21 and the second pixel group 22 of the first row H1, and the sub-pixels in the second pixel group 22 and the first pixel group 21 of the second row H2 are displayed in sequence.

[0112] In some embodiments, as shown in FIG. 8, the first control line 61, the second control line 62, the third control line 63 and the fourth control line 64 all extend along the row direction X and are arranged along the column direction Y, two control switches K corresponding to a column of sub-pixels form a shared control switch K1, the shared control switch K1 is arranged between the plurality of control lines 60 and the plurality of sub-pixels 10, the shared control switch K1 includes a shared active layer pattern 501a, two gate patterns 501b, a shared first electrode pattern 501c and two second electrode patterns 501d, the two gate patterns 501b overlap with the shared active layer pattern 501a, the two gate patterns 501b are located on both sides of the shared first electrode pattern 501c respectively, and one end of each gate pattern 501b is connected with a corresponding control line 60, the shared first electrode pattern 501c is connected with the shared active layer pattern 501a and a corresponding data bus 41, the two second electrode patterns 501d are connected with the active layer pattern 501a, and the two second electrode patterns 501b are connected with corresponding data lines DT respectively; in the case that the shared data bus 42 includes a shared fan-out line 42a, a shared adapter line 42b and at least two shared connection lines 42c, the shared first electrode pattern 501c is connected with a shared connection line 42c of the corresponding shared data bus 42.

[0113] The first control line 61, the second control line 62, the third control line 63 and the fourth control line 64, and the plurality of shared control switches GK are arranged in the peripheral area BB, the plurality of shared control switches GK are arranged along the row direction X, and one shared control switch (two control switches) corresponds to a column of sub-pixels, the shared control switch is arranged on one side of a column of sub-pixels from the direction Z pointing from the peripheral area to the display area, a plurality of shared fan-out lines, shared adapter lines, control lines, control switches and a plurality of sub-pixels are arranged in sequence, and the connection lines cross the plurality of control lines to connect the adapter lines and the control switches.

[0114] Exemplarily, the display panel further includes an active layer 101 arranged between the substrate and the first gate layer, wherein the first control line 61, the second control line 62, the third control line 63 and the fourth control line 64 are arranged in the first source-drain metal layer 104, the shared active layer pattern 501a of the plurality of shared control switches GK is arranged in the active layer, the shared first electrode pattern 501c and the second electrode pattern 501d are arranged in the first source-drain metal layer 104, and the shared gate pattern 501b is arranged in the first gate layer 102.

[0115] In some embodiments, as shown in FIG. 3A, FIG. 5A, FIG. 7A and FIG. 9, in the case that the display unit 20 comprises at least four adjacent columns of sub-pixels 10, each of the four adjacent columns of sub-pixels comprises a second column of sub-pixels 220, a first column of first sub-pixels 2101 of the first type, a third column of sub-pixels 230 and a first column of first sub-pixels 2102 of the second type arranged in sequence, wherein the second column of sub-pixels 220, the first column of first sub-pixels 2101 of the first type, the third column of sub-pixels 230 and the first column of first sub-pixels 2102 of the second type are mirror-symmetrically arranged, and the data lines DT connecting the second column of sub-pixels 220 and the first column of first sub-pixels 2101 of the first type are mirror-symmetrically arranged with the data lines DT connecting the third column of sub-pixels 230 and the first column of first sub-pixels 2102 of the second type.

[0116] As shown in FIG. 3A, FIG. 7A and FIG. 9, the display unit comprises four adjacent columns of sub-pixels, which are a second column of sub-pixels 220, a first column of first sub-pixels 2101 of the first type, a third column of sub-pixels 230 and a first column of first sub-pixels 2102 of the second type arranged in sequence, with the boundary between the first column of first sub-pixels 2101 of the first type and the third column of sub-pixels 230 as the axis of symmetry O, the second column of sub-pixels 220 and the first column of first sub-pixels 2102 of the second type are mirror-symmetrically arranged about the axis of symmetry O, the first column of first sub-pixels 2101 of the first type and the third column of sub-pixels 230 are mirror-symmetrically arranged about the axis of symmetry O, and the mirror-symmetry of the two columns of sub-pixels refers to the mirror-symmetry of the patterns of the layers of each sub-pixel. The data lines DT1, DT1', DT2, DT2' connecting the second column of sub-pixels 220 and the first column of first sub-pixels 2101 of the first type are mirror-symmetrically arranged with the data lines DT3, DT3', DT4, DT4' connecting the third column of sub-pixels 230 and the first column of first sub-pixels 2104 of the second type about the axis of symmetry O. Exemplarily, the connection position of the data line DT1 with the second color sub-pixel 12 is located in the left half region of the sub-pixel, and the connection position of the data line DT4' with the first column of first color sub-pixels 112 of the second type is located in the right half region of the sub-pixel, and the two connection positions are mirror-symmetrically arranged.

[0117] As shown in FIG. 5A, in the case that the display unit 20 comprises eight adjacent columns of sub-pixels 10, the eight columns of sub-pixels are divided into two groups, with each of the four adjacent columns of sub-pixels as a group, and each of the four adjacent columns of sub-pixels comprises a second column of sub-pixels 220, a first column of first sub-pixels 2101 of the first type, a third column of sub-pixels 230 and a first column of first sub-pixels 2102 of the second type arranged in sequence. The mirror-symmetry of the layers of each of the four adjacent columns of sub-pixels and the corresponding data lines can be referred to the above description.

[0118] Exemplarily, referring to FIG. 9, the arrangement of the sub-pixels and the data lines makes the arrangement of the lines in the display unit 20 more orderly, and in the manufacturing process, is not affected by the alignment offset, so that the parasitic of the pixels at different positions is consistent, the brightness in the display unit 20 is ensured to be consistent, the brightness unevenness caused by the parasitic difference is avoided, and the uniformity of the display panel is further improved.

[0119] Exemplarily, each sub-pixel 10 includes a pixel driving circuit 80, which can be a 7T1C, 8T1C or 9T1C circuit, where T represents a transistor, the number in front of T represents the number of transistors, C represents a capacitor, and the number in front of C represents the number of capacitors. Exemplarily, 7T1C represents 7 transistors and 1 capacitor.

[0120] In some embodiments, the structure of the pixel driving circuit 80 based on FIG. 10 is introduced, which is a 7T1C pixel driving circuit. The pixel driving circuit 80 includes a second reset transistor T1, a compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, and a first reset transistor T7.

[0121] Exemplarily, as shown in FIG. 10, the second reset transistor T1 includes a gate, a first electrode and a second electrode, the gate of the second reset transistor T1 is electrically connected with the third scan signal line Gate3, the first electrode of the second reset transistor T1 is electrically connected with the first initialization signal line Vinit1, and the second electrode of the second reset transistor T1 is electrically connected with the first node N1. The second reset transistor T1 is configured to reset the gate of the driving transistor T3 (the first node N1) in response to the reset signal received at the third scan signal line Gate3.

[0122] Exemplarily, as shown in FIG. 10, the compensation transistor T2 includes a gate, a first electrode and a second electrode, the gate of the compensation transistor T2 is electrically connected with the first scan signal line Gate1, the first electrode of the compensation transistor T2 is electrically connected with the first node N1, and the second electrode of the compensation transistor T2 is electrically connected with the third node N3. The compensation transistor T2 is configured to reset or threshold compensate the driving transistor T3 in response to the scan signal received at the first scan signal line Gate1.

[0123] Exemplarily, as shown in FIG. 10, the driving transistor T3 includes a gate, a first electrode and a second electrode, the gate of the driving transistor T3 is electrically connected with the first node N1, the first electrode of the driving transistor T3 is electrically connected with the second node N2, and the second electrode of the driving transistor T3 is electrically connected with the third node N3. The driving transistor T3 is configured to generate a driving current signal.

[0124] Exemplarily, as shown in FIG. 10, the data writing transistor T4 includes a gate, a first pole and a second pole, the gate of the data writing transistor T4 is electrically connected with the first scan signal line Gate1, the first pole of the data writing transistor T4 is electrically connected with the data signal line Data, and the second pole of the data writing transistor T4 is electrically connected with the second node N2. The data writing transistor T4 is configured to transmit the data signal received at the data signal line Data to the driving transistor T3 in response to the scan signal received at the first scan signal line Gate1.

[0125] Exemplarily, as shown in FIG. 10, the first light emitting control transistor T5 includes a gate, a first pole and a second pole, the gate of the first light emitting control transistor T5 is electrically connected with the light emitting control signal line EM, the first pole of the first light emitting control transistor T5 is electrically connected with the power signal line ELVDD, and the second pole of the first light emitting control transistor T5 is electrically connected with the second node N2. The first light emitting control transistor T5 is configured to transmit the power signal received at the power signal line ELVDD to the driving transistor T3 in response to the light emitting control signal received at the light emitting control signal line EM.

[0126] Exemplarily, as shown in FIG. 10, the second light emitting control transistor T6 includes a gate, a first pole and a second pole, the gate of the second light emitting control transistor T6 is electrically connected with the light emitting control signal line EM, the first pole of the second light emitting control transistor T6 is electrically connected with the third node N3, and the second pole of the second light emitting control transistor T6 is electrically connected with the fourth node N4. The second light emitting control transistor T6 is configured to transmit the driving current signal to the light emitting device L for driving the light emitting device L to emit light in response to the light emitting control signal received at the light emitting control signal line EM.

[0127] Exemplarily, as shown in FIG. 10, the first reset transistor T7 includes a gate, a first pole and a second pole, the gate of the first reset transistor T7 is electrically connected with the second scan signal line Gate2, the first pole of the first reset transistor T7 is electrically connected with the second initialization signal line Vinit2, and the second pole of the first reset transistor T7 is electrically connected with the fourth node N4. The first reset transistor T7 is configured to transmit the initialization signal received at the second initialization signal line Vinit2 to the light emitting device L for resetting the light emitting device L in response to the reset signal received at the second scan signal line Gate2.

[0128] Exemplarily, the anode of the light emitting device L is electrically connected with the fourth node N4, and the cathode of the light emitting device L is electrically connected with the reference voltage line ELVSS.

[0129] It should be noted that the first pole of the transistor in the present disclosure is one of the source and the drain of the transistor, and the second pole is the other of the source and the drain of the transistor. Since the source and the drain of the transistor can be symmetrical in structure, the source and the drain of the transistor can be indistinguishable in structure, that is, the first pole and the second pole of the transistor in the embodiments of the present disclosure can be indistinguishable in structure. For example, in the case of a P-type transistor, the first pole of the transistor is the source, and the second pole is the drain; for example, in the case of an N-type transistor, the first pole of the transistor is the drain, and the second pole is the source.

[0130] In the circuit provided by the embodiments of the present disclosure, the nodes do not represent actual components, but represent the convergence points of relevant electrical connections in the circuit diagram, that is, these nodes are nodes equivalent to the convergence points of relevant electrical connections in the circuit diagram.

[0131] For example, as shown in FIG. 10, the pixel driving circuit 80 further includes a capacitor Cst, the capacitor Cst including a first pole plate Cst1 and a second pole plate Cst2, the first pole plate Cst1 of the capacitor Cst being electrically connected to the first node N1, and the second pole plate Cst2 of the capacitor Cst being electrically connected to the power signal line ELVDD.

[0132] In combination with FIG. 9, in the film layer arrangement of the display panel, one sub-pixel 10 includes a plurality of patterns in each film layer, and the plurality of patterns include an active layer pattern, a gate pattern, a source pattern and a drain pattern of a transistor in the pixel driving circuit of the sub-pixel, a first pole plate pattern and a second base plate pattern of a capacitor. The display panel further includes a plurality of signal line patterns connected to the pixel driving circuit, such as a data line pattern, a power signal line pattern, etc.

[0133] The embodiments of the present disclosure further provide a display device 1000, which includes the display panel 100 provided by any of the above embodiments. Therefore, the display device 1000 provided by the present disclosure has all the beneficial effects of the display panel 100 provided by any of the above embodiments, which will not be repeated here.

[0134] For example, with reference to FIG. 3A, the above display device 1000 further includes a driving chip 70. The driving chip 70 is electrically connected to the data bus group 40. The driving chip 70 is configured to provide a driving signal to the display panel 100 and control the display of the display panel 100.

[0135] The display device 1000 described above can be any device that displays, regardless of motion (e.g., a video) or fixation (e.g., a still image), and regardless of text or an image. More specifically, it is contemplated that the embodiments can be implemented in or in association with a variety of electronic devices, such as, but not limited to, a mobile phone, a wireless device, a personal data assistant (PDA), a handheld or portable computer, a GPS receiver / navigator, a camera, an MP4 video player, a camcorder, a game console, a watch, a clock, a calculator, a television monitor, a flat panel display, a computer monitor, an automobile display (e.g., a speedometer display, etc.), a navigation system, an augmented reality (AR) device, a virtual reality (VR) device, a cockpit controller and / or display, a display of a camera view (e.g., a display of a rear view camera in a vehicle), an electronic photograph, an electronic billboard or sign, a projector, a building structure, a package and an aesthetic structure (e.g., a display of an image of a piece of jewelry), etc., any product or component having a display function.

[0136] Exemplarily, as shown in FIG. 11, the display device 1000 can be any product or component having a display function, such as a television, a notebook computer, a tablet computer, a mobile phone, a personal digital assistant (PDA), a navigation system, a vehicle display, a flight display, a wearable device, a virtual reality (VR) device, etc.

[0137] The display device 1000 described above can be any device that displays, regardless of motion (e.g., a video) or fixation (e.g., a still image), and regardless of text or an image. More specifically, it is contemplated that the embodiments can be implemented in or in association with a variety of electronic devices, such as, but not limited to, a mobile phone, a wireless device, a personal data assistant (PDA), a handheld or portable computer, a GPS receiver / navigator, a camera, an MP4 video player, a camcorder, a game console, a watch, a clock, a calculator, a television monitor, a flat panel display, a computer monitor, an automobile display (e.g., a speedometer display, etc.), a navigation system, an augmented reality (AR) device, a virtual reality (VR) device, a cockpit controller and / or display, a display of a camera view (e.g., a display of a rear view camera in a vehicle), an electronic photograph, an electronic billboard or sign, a projector, a building structure, a package and an aesthetic structure (e.g., a display of an image of a piece of jewelry), etc., any product or component having a display function.

[0138] The display device 1000 described above can be any device that displays, regardless of motion (e.g., a video) or fixation (e.g., a still image), and regardless of text or an image. More specifically, it is contemplated that the embodiments can be implemented in or in association with a variety of electronic devices, such as, but not limited to, a mobile phone, a wireless device, a personal data assistant (PDA), a handheld or portable computer, a GPS receiver / navigator, a camera, an MP4 video player, a camcorder, a game console, a watch, a clock, a calculator, a television monitor, a flat panel display, a computer monitor, an automobile display (e.g., a speedometer display, etc.), a navigation system, an augmented reality (AR) device, a virtual reality (VR) device, a cockpit controller and / or display, a display of a camera view (e.g., a display of a rear view camera in a vehicle), an electronic photograph, an electronic billboard or sign, a projector, a building structure, a package and an aesthetic structure (e.g., a display of an image of a piece of jewelry), etc., any product or component having a display function.

[0139] As shown in FIGS. 5B and 7B, some embodiments of the present disclosure further provide a driving method applied to the display panel 100 provided by any of the above embodiments. The driving method is based on the display panel 100 provided by the above embodiments, and thus the driving method provided by the present disclosure has all the beneficial effects of the display panel 100 provided by any of the above embodiments, which will not be repeated here.

[0140] In some embodiments, referring to FIG. 3A, FIG. 5B and FIG. 7B, at the first time period t1 of the first scanning time T10, the first data bus 411, the second data bus 412, the third data bus 413 and the fourth data bus 414 are controlled to output display signals respectively, and the first control switch K1 connected to the first sub-pixel column 2101 of the first type and the third control switch K3 connected to the second sub-pixel column 220 are controlled to be in the open state in the display unit 20;

[0141] At the first time period t3 of the second scanning time T20, the first data bus 411, the second data bus 412, the third data bus 413 and the fourth data bus 414 are controlled to output display signals respectively, and the second control switch K2 connected to the first sub-pixel column 2101 of the first type and the fourth control switch K4 connected to the second sub-pixel column 220 are controlled to be in the open state in the display unit 20.

[0142] Exemplarily, referring to FIG. 3A, FIG. 5B and FIG. 7A, the display unit includes at least four adjacent sub-pixel columns, wherein, in the case that the first control switch K1 connected to the first sub-pixel column 2101 of the first type and the third control switch K3 connected to the second sub-pixel column 220 are in the open state, the first control switch K1 controls the first color sub-pixel 111 in the first sub-pixel column 2101 of the first type to display, and the third control switch K3 controls the second color sub-pixel 12 in the second sub-pixel column 220 to display; in the case that the second control switch K2 connected to the first sub-pixel column 2101 of the first type and the fourth control switch K4 connected to the second sub-pixel column 220 are in the open state, the second control switch K2 controls the second type of first color sub-pixel 112 in the first sub-pixel column 2101 of the first type to display, and the fourth control switch K4 controls the third color sub-pixel 13 in the second sub-pixel column 220 to display.

[0143] In some embodiments, referring to FIG. 5A and FIG. 5B, the display unit 20 includes eight adjacent sub-pixel columns 10, and the display unit 20 includes a first sub-display unit 201 and a second sub-display unit 202 arranged along the row direction X; the first sub-display unit 201 includes four adjacent sub-pixel columns, and the second sub-display unit 202 includes four adjacent sub-pixel columns.

[0144] At the first time period t1 of the first scanning time T10, the first data bus 411, the second data bus 412, the third data bus 413 and the fourth data bus 414 are controlled to output display signals respectively, and the second control switch K2 connected to the second sub-pixel column 2102 of the first type in the first sub-display unit 201, the fourth control switch K4 connected to the third sub-pixel column 230, the first control switch K1 connected to the first sub-pixel column 2101 of the first type and the third control switch K3 connected to the second sub-pixel column 220 are controlled to be in the open state.

[0145] In the second period t2 of the first scanning time T10, the first data bus 411, the second data bus 412, the third data bus 413 and the fourth data bus 414 are controlled to output display signals respectively, and the first control switch K1 connected with the first sub-pixel column 2101 of the first type, the second control switch K2 connected with the first sub-pixel column 2102 of the second type, the third control switch K3 connected with the second sub-pixel column 220 and the fourth control switch K4 connected with the third sub-pixel column 230 in the second sub-display unit 202 are controlled to be in the open state.

[0146] In the first period t3 of the second scanning time T20, the first data bus 411, the second data bus 412, the third data bus 413 and the fourth data bus 414 are controlled to output display signals respectively, and the first control switch K1 connected with the second sub-pixel column 220 of the first type, the third control switch K3 connected with the third sub-pixel column 230, the second control switch K2 connected with the first sub-pixel column 2101 of the first type and the fourth control switch K4 connected with the second sub-pixel column 220 in the first sub-display unit 201 are controlled to be in the open state.

[0147] In the second period t4 of the second scanning time T20, the first data bus 411, the second data bus 412, the third data bus 413 and the fourth data bus 414 are controlled to output display signals respectively, and the second control switch K2 connected with the first sub-pixel column 2101 of the first type, the first control switch K1 connected with the second sub-pixel column 220 of the second type, the fourth control switch K4 connected with the second sub-pixel column 220 and the third control switch K3 connected with the third sub-pixel column 230 in the second sub-display unit 202 are controlled to be in the open state.

[0148] Exemplarily, with reference to FIGS. 5A and 5B, in the case that the display unit 20 includes eight adjacent sub-pixel columns 10, the display unit 20 includes at least eight sub-pixel columns 10 located in the first row H1 and eight sub-pixel columns 10 located in the second row H1, the eight sub-pixel columns 10 in the first row are divided into a first group of sub-pixel columns 10a and a second group of sub-pixel columns 10b, the eight sub-pixel columns 10 in the second row are divided into a third group of sub-pixel columns 10c and a fourth group of sub-pixel columns 10d, and each group of sub-pixel columns 10 includes four adjacent sub-pixel columns 10.

[0149] In the first period t1 of the first scanning time T10, the sub-pixels in the first group of sub-pixel columns 10a are displayed, in the second period t2 of the first scanning time T10, the sub-pixels in the second group of sub-pixel columns 10b are displayed, in the first period t3 of the second scanning time T20, the sub-pixels in the third group of sub-pixel columns 10c are displayed, and in the second period t4 of the second scanning time T20, the sub-pixels in the fourth group of sub-pixel columns 10d are displayed.

[0150] In some embodiments, referring to FIGS. 3A, 3B, 7A and 7B, at the second period t2 of the first scanning time T10, the first data bus 411, the second data bus 412, the third data bus 413 and the fourth data bus 414 are controlled to output display signals respectively, and the second control switch K2 connected to the second type first sub-pixel column 2102 and the fourth control switch K4 connected to the third sub-pixel column 230 in the display unit are controlled to be in the open state; at the second period t4 of the second scanning time T20, the first data bus 411, the second data bus 412, the third data bus 413 and the fourth data bus 414 are controlled to output display signals respectively, and the first control switch K1 connected to the second type first sub-pixel column 2102 and the third control switch K3 connected to the third sub-pixel column 230 in the display unit 20 are controlled to be in the open state.

[0151] Exemplarily, referring to FIGS. 3A, 3B, 7A and 7B, the display unit includes at least four columns of sub-pixels adjacent to each other, wherein, when the second control switch K2 connected to the second type first sub-pixel column 2102 and the fourth control switch K4 connected to the third sub-pixel column 230 are in the open state, the second control switch K2 controls the second type first color sub-pixel 112 in the second type first sub-pixel column 2102 to display, and the fourth control switch K4 controls the third color sub-pixel 13 in the third sub-pixel column 230 to display; when the first control switch K1 connected to the second type first sub-pixel column 2102 and the third control switch K3 connected to the third sub-pixel column 230 are in the open state, the first control switch K1 controls the first type first color sub-pixel 111 in the second type first sub-pixel column 2102 to display, and the third control switch K3 controls the second color sub-pixel 12 in the third sub-pixel column 230 to display.

[0152] In the description of the present specification, specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0153] The above description is merely specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can think of changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A display panel comprising: a plurality of sub-pixels arranged in an array, the plurality of sub-pixels comprising first color sub-pixels, the first color sub-pixels comprising first type first color sub-pixels and second type first color sub-pixels; the plurality of sub-pixels comprising at least one display unit, the display unit comprising at least four columns of sub-pixels, at least two columns of the at least four columns of sub-pixels being first sub-pixel columns, one column of other sub-pixels being arranged between each two of the first sub-pixel columns, the at least two columns of first sub-pixel columns comprising a first type first sub-pixel column and a second type first sub-pixel column arranged in sequence, wherein the first type first sub-pixel column comprises a first type first color sub-pixel and a second type first color sub-pixel arranged in sequence in a column direction, and the second type first sub-pixel column comprises a second type first color sub-pixel and a first type first color sub-pixel arranged in sequence in the column direction; at least one data line group comprising a plurality of data lines, the data line group being connected to the display unit, one column of sub-pixels being connected to two data lines, and one data line being connected to sub-pixels of the same type in the one column of sub-pixels; at least one data bus group comprising a plurality of data buses, the data bus group being connected to the display unit; the data bus group comprising a first data bus and a second data bus, the first data bus being connected to first type first color sub-pixels in the at least two columns of first sub-pixel columns through at least two data lines, and the second data bus being connected to second type first color sub-pixels in the at least two columns of first sub-pixel columns through at least two data lines; at least one control switch group comprising a plurality of control switches, the control switch group being connected to the data bus group; the control switch group comprising a first control switch and a second control switch, each data line connected to the first data bus being connected to a first control switch, and each data line connected to the first data bus being connected to a second control switch.

2. The display panel of claim 1, wherein, the plurality of sub-pixels further comprising second color sub-pixels and third color sub-pixels; the display unit further comprising at least one column of second sub-pixel columns and at least one column of third sub-pixel columns arranged in sequence in a row direction, and the first sub-pixel columns being located between the at least one column of second sub-pixel columns and the at least one column of third sub-pixel columns; the at least one column of second sub-pixel columns comprising second color sub-pixels and third color sub-pixels arranged in sequence in a column direction, and the at least one column of third sub-pixel columns comprising third color sub-pixels and second color sub-pixels arranged in sequence in the column direction; the data bus group further comprising a third data bus and a fourth data bus, the third data bus being connected to second color sub-pixels of the at least one column of second sub-pixel columns and the at least one column of third sub-pixel columns through at least two data lines, and the fourth data bus being connected to third color sub-pixels of the at least one column of second sub-pixel columns and the at least one column of third sub-pixel columns through at least two data lines; the plurality of control switches further comprising a third control switch and a fourth control switch, each data line connected to the third data bus being connected to a third control switch, and each data line connected to the fourth data bus being connected to a fourth control switch.

3. The display panel of claim 1 or 2, wherein, The data bus comprises a fan-out line, an adapter line and at least two connection lines; The fan-out line is connected with the adapter line, and the at least two connection lines are connected with the adapter line, and the connection lines are connected with the control switch.

4. The display panel of claim 3, wherein, The first data bus comprises a first fan-out line, a first adapter line and at least two first connection lines; The first fan-out line is connected with the first adapter line, and the at least two first connection lines are connected with the first adapter line, and the first connection lines are connected with the first control switch; The second data bus comprises a second fan-out line, a second adapter line and at least two second connection lines; The second fan-out line is connected with the second adapter line, and the at least two second connection lines are connected with the second adapter line, and the second connection lines are connected with the second control switch; The third data bus comprises a third fan-out line, a third adapter line and at least two third connection lines; The third fan-out line is connected with the third adapter line, and the at least two third connection lines are connected with the third adapter line, and the third connection lines are connected with the third control switch; The fourth data bus comprises a fourth fan-out line, a fourth adapter line and at least two fourth connection lines; The fourth fan-out line is connected with the fourth adapter line, and the at least two fourth connection lines are connected with the fourth adapter line, and the fourth connection lines are connected with the fourth control switch.

5. The display panel of claim 4, wherein, The first adapter line, the second adapter line, the third adapter line and the fourth adapter line all extend along a row direction and are arranged along a column direction; The first fan-out line, the second fan-out line, the third fan-out line and the fourth fan-out line are all arranged on a side of the first adapter line, the second adapter line, the third adapter line and the fourth adapter line away from the plurality of sub-pixels; The first connection line, the second connection line, the third connection line and the fourth connection line all extend along a column direction and are arranged on a side of the first adapter line, the second adapter line, the third adapter line and the fourth adapter line close to the plurality of sub-pixels.

6. The display panel according to any one of claims 1 to 5, wherein The display unit at least comprises at least four sub-pixels located in a first row and at least four sub-pixels located in a second row; the display panel further comprises a plurality of control lines for controlling the control switches; The at least two control switches corresponding to the connection of the adjacent at least two sub-pixels located in the same row are all connected with the same control line.

7. The display panel of claim 6, wherein, The display unit comprises eight columns of sub-pixels adjacent to each other, and the display unit comprises four columns of first sub-pixel columns, two columns of second sub-pixel columns and two columns of third sub-pixel columns; The display unit at least comprises eight sub-pixels located in a first row and eight sub-pixels located in a second row, the eight sub-pixels located in the first row are divided into a first group of sub-pixels and a second group of sub-pixels, the eight sub-pixels located in the second row are divided into a third group of sub-pixels and a fourth group of sub-pixels, and each group of sub-pixels comprises four adjacent sub-pixels. The four control switches corresponding to the first group of sub-pixels are connected with the first control line, the four control switches corresponding to the second group of sub-pixels are connected with the second control line, the four control switches corresponding to the third group of sub-pixels are connected with the third control line, and the four control switches corresponding to the fourth group of sub-pixels are connected with the fourth control line.

8. The display panel of claim 7, wherein, The first control line, the second control line, the third control line and the fourth control line extend along the row direction and are arranged along the column direction. The control switch is provided between the control line and the sub-pixel, and includes an active layer pattern, a gate pattern, a first electrode pattern and a second electrode pattern. The gate pattern overlaps with the active layer pattern, one end of the gate pattern is connected with the corresponding control line, the first electrode pattern is connected with the active layer pattern and the corresponding data bus, and the second electrode pattern is connected with the active layer pattern and the corresponding data line. In the case that the data bus includes a fan-out line, a switching line and at least two connection lines, the first electrode pattern is connected with one connection line of the corresponding data bus.

9. The display panel of any one of claims 1 or 2, wherein, The display unit includes four adjacent columns of sub-pixels. The first data bus and the second data bus are the same data bus as a first common data bus, and the third data bus and the fourth data bus are the same data bus as a second common data bus. The first common data bus is connected with the first type of first color sub-pixels and the second type of first color sub-pixels in the two first sub-pixel columns through at least two data lines, and the second common data bus is connected with the second color sub-pixels and the third color sub-pixels in the second sub-pixel column and the third sub-pixel column through at least two data lines.

10. The display panel of claim 9, wherein, The first common data bus includes a common first fan-out line, a common first switching line and at least two common first connection lines. The common first fan-out line is connected with the common first switching line, and the at least two common first connection lines are connected with the common first switching line. One common first connection line is connected with the first control switch and the second control switch corresponding to one column of sub-pixels. The second common data bus includes a common second fan-out line, a common second switching line and at least two common second connection lines. The common second fan-out line is connected with the common second switching line, and the at least two common second connection lines are connected with the common second switching line. One common second connection line is connected with the third control switch and the fourth control switch corresponding to one column of sub-pixels.

11. The display panel of claim 10, wherein The common first switching line and the common second switching line extend along the row direction and are arranged along the column direction. The common first fan-out line and the common second fan-out line are arranged on the side of the common first switching line and the common second switching line away from the sub-pixels. The common first connection line and the common second connection line are arranged on the side of the common first switching line and the common second switching line close to the sub-pixels.

12. The display panel of claim 10, wherein, The display unit includes at least a first pixel group and a second pixel group in a first row, and a second pixel group and a first pixel group in a second row; the first pixel group includes a first sub-pixel of a first type and a second color sub-pixel, and the second pixel group includes a first sub-pixel of a second type and a third color sub-pixel; the display panel further includes a plurality of control lines for controlling the control switches; The first control switch and the third control switch connected to the first pixel group in the first row are connected to a first control line, and the second control switch and the fourth control switch connected to the second pixel group in the first row are connected to a second control line; the second control switch and the fourth control switch connected to the second pixel group in the second row are connected to a third control line, and the first control switch and the third control switch connected to the first pixel group in the second row are connected to a fourth control line.

13. The display panel of claim 12, wherein, The first control line, the second control line, the third control line and the fourth control line extend along a row direction and are arranged along a column direction, Two control switches corresponding to a column of sub-pixels form a shared control switch, which is arranged between the plurality of control lines and the plurality of sub-pixels, and includes a shared active layer pattern, two gate patterns, a shared first electrode pattern and two second electrode patterns; the two gate patterns overlap with the shared active layer pattern, and are located on both sides of the shared first electrode pattern; one end of each gate pattern is connected to a corresponding control line; the shared first electrode pattern is connected to the shared active layer pattern and a corresponding data bus; the two second electrode patterns are connected to the active layer pattern, and each second electrode pattern is connected to a corresponding data line. In the case where the shared data bus includes a shared fan-out line, a shared adapter line and at least two shared connection lines, the shared first electrode pattern is connected to one shared connection line of the corresponding shared data bus.

14. The display panel according to any one of claims 1 to 13, wherein, In the case where the display unit includes at least four columns of adjacent sub-pixels, each of the four columns of adjacent sub-pixels includes a second sub-pixel column, a first sub-pixel column of a first type, a third sub-pixel column and a first sub-pixel column of a second type arranged in sequence; the second sub-pixel column, the first sub-pixel column of the first type, the third sub-pixel column and the first sub-pixel column of the second type are mirror-symmetrically arranged; and the data lines connected to the second sub-pixel column and the first sub-pixel column of the first type are mirror-symmetrically arranged with the data lines connected to the third sub-pixel column and the first sub-pixel column of the second type.

15. A display device comprising the display panel of any one of claims 1-14, and a driving chip connected to the data bus group.

16. A driving method applied to the display panel according to any one of claims 2 to 14, wherein The driving method comprises: In a first time period of a first scanning time, the first data bus, the second data bus, the third data bus and the fourth data bus are controlled to output display signals respectively, and the first control switch connected to the first sub-pixel column of the first type and the third control switch connected to the second sub-pixel column are controlled to be in an open state in the display unit. In the first time period of the second scanning time, the first data bus, the second data bus, the third data bus and the fourth data bus are controlled to output display signals respectively, and the second control switch connected with the first sub-pixel column of the first type in the display unit and the fourth control switch connected with the second sub-pixel column are controlled to be in the open state.

17. The driving method according to claim 16, wherein Further comprising: The display unit comprises eight columns of sub-pixels adjacent to each other, and the display unit comprises a first sub-display unit and a second sub-display unit arranged in a row direction; the first sub-display unit comprises four columns of sub-pixels adjacent to each other, and the second sub-display unit comprises four columns of sub-pixels adjacent to each other; In the first time period of the first scanning time, the first data bus, the second data bus, the third data bus and the fourth data bus are controlled to output display signals respectively, and the second control switch connected with the first sub-pixel column of the first type in the first sub-display unit, the fourth control switch connected with the third sub-pixel column, the first control switch connected with the first sub-pixel column of the first type, and the third control switch connected with the second sub-pixel column are controlled to be in the open state; In the second time period of the first scanning time, the first data bus, the second data bus, the third data bus and the fourth data bus are controlled to output display signals respectively, and the first control switch connected with the first sub-pixel column of the first type in the second sub-display unit, the second control switch connected with the first sub-pixel column of the second type, the third control switch connected with the second sub-pixel column, and the fourth control switch connected with the third sub-pixel column are controlled to be in the open state. In the first time period of the second scanning time, the first data bus, the second data bus, the third data bus and the fourth data bus are controlled to output display signals respectively, and the first control switch connected with the first sub-pixel column of the second type in the first sub-display unit, the third control switch connected with the third sub-pixel column, the second control switch connected with the first sub-pixel column of the first type, and the fourth control switch connected with the second sub-pixel column are controlled to be in the open state. In the second time period of the second scanning time, the first data bus, the second data bus, the third data bus and the fourth data bus are controlled to output display signals respectively, and the second control switch connected with the first sub-pixel column of the first type in the second sub-display unit, the first control switch connected with the first sub-pixel column of the second type, the fourth control switch connected with the second sub-pixel column, and the third control switch connected with the third sub-pixel column are controlled to be in the open state.

18. The driving method according to claim 16, wherein Further comprising: In the second time period of the first scanning time, the first data bus, the second data bus, the third data bus and the fourth data bus are controlled to output display signals respectively, and the second control switch connected with the first sub-pixel column of the second type in the display unit and the fourth control switch connected with the third sub-pixel column are controlled to be in the open state; In a second time period of the second scanning time, the first data bus, the second data bus, the third data bus and the fourth data bus are controlled to output display signals respectively, and the first control switch connected by the second type first sub-pixel column and the third control switch connected by the third sub-pixel column in the display unit are controlled to be in an open state.

Images