Communication method and communication apparatus based on LDPC code

Abstract

A communication method and communication apparatus based on an LDPC code. A device may perform encoding or decoding on the basis of an LDPC check matrix, wherein the LDPC check matrix is determined on the basis of an LDPC basis matrix, the LDPC basis matrix comprises at least two regions, any two regions among the at least two regions do not overlap with each other, and the any two regions correspond to different translation value acquisition manners. In the method, different translation value acquisition manners are designed for at least two regions in an LDPC basis matrix, thereby optimizing the cycle property of an LDPC code, and ensuring the stable performance of the LDPC code.

Description

Communication methods and devices based on LDPC codes

[0001] This application claims priority to Chinese Patent Application No. 202410939802.2, filed on July 12, 2024, entitled "Communication Method and Communication Device Based on LDPC Code", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of coding, and more specifically, to a communication method and communication apparatus based on low-density parity check (LDPC) codes. Background Technology

[0003] In the field of channel coding, LDPC codes are one of the most mature and widely used channel coding schemes. Quasi-cyclic low-density parity check (QC-LDPC) codes are a type of structured LDPC codes. Due to the unique structure of their parity check matrix, they can be encoded using a simple feedback shift register, reducing the coding complexity of LDPC codes.

[0004] Currently, the translation values ​​corresponding to the base graph of LDPC codes are obtained globally using the same method, resulting in significant limitations on these values. When the translation values ​​of the matrix need to play other roles and require different methods of determination (e.g., the translation values ​​of the coding region need to ensure local full rank for easy hardware encoding), the method for obtaining the translation values ​​corresponding to the base graph of the LDPC code needs to be modified. Existing nested methods are neither applicable to the global scope of the LDPC code base graph nor can they guarantee the good cyclic properties of the global LDPC base graph or the performance of the LDPC code. Summary of the Invention

[0005] The embodiments of this application provide a communication method and a communication device, which are specially designed for the translation values ​​corresponding to the base graph (or base matrix) of the LDPC code to ensure the performance stability of the LDPC code.

[0006] In the first aspect, a communication method based on LDPC code is provided. This method can be executed by a transmitting device. Unless otherwise specified, the term "transmitting device" in this application can refer to the transmitting device itself (e.g., a network device, a terminal device), a component in the transmitting device (e.g., a processor, a chip, or a chip system), or a logic module or software that can implement all or part of the functions of the transmitting device.

[0007] The method includes: acquiring an information bit sequence; determining an LDPC parity check matrix, wherein the LDPC parity check matrix is ​​determined based on an LDPC base matrix, the base matrix including at least two regions, wherein any two regions are non-overlapping, and the translation values ​​corresponding to the two regions are obtained in different ways; encoding the information bit sequence according to the LDPC parity check matrix to obtain a codeword sequence; and outputting the codeword sequence.

[0008] According to the scheme provided in this application, the translation values ​​of any two regions in at least two regions included in the LDPC base matrix are obtained in different ways, thereby realizing the design of different translation value acquisition methods for different regions of the LDPC base matrix. While meeting the requirements of different regions in the LDPC base matrix, the performance stability of the LDPC code is guaranteed.

[0009] Secondly, a communication method based on LDPC code is provided. This method can be executed by a receiving device. Unless otherwise specified, the term "receiving device" in this application can refer to the receiving device itself (e.g., a network device, a terminal device), a component in the receiving device (e.g., a processor, a chip, or a chip system), or a logic module or software that can implement all or part of the functions of the transmitting device.

[0010] The method includes: acquiring a codeword sequence; determining an LDPC parity-check matrix, wherein the LDPC parity-check matrix is ​​determined based on an LDPC base matrix, the base matrix includes at least two regions, any two regions in the at least two regions do not overlap, and the translation values ​​corresponding to the two regions are obtained in different ways; and decoding the codeword sequence according to the LDPC parity-check matrix to obtain an information bit sequence.

[0011] It should be understood that the second aspect corresponds to the first aspect, and the technical effects can be found in the introduction of the first aspect above.

[0012] In conjunction with the first or second aspect, in some possible implementations, the translation value corresponding to one of the at least two regions is determined in one of the following ways:

[0013] Method 1: or, or,

[0014] Method 2: SV i,j =P i,j *Zc / Z max Or, SV i,j =P i,j *Zc / Z max +w;

[0015] Method 3: or, or,

[0016] Method 4: SV i,j =P i,j Or, SV i,j =P i,j +w;

[0017] Method 5: SV i,j =mod(P i,j ,Zc), or SV i,j =mod(P i,j +w,Zc),

[0018] Wherein, the SV i,j P is the element at row i and column j in the base matrix. i,j The predefined translation values ​​of the base matrix are the predefined translation values ​​corresponding to the 1 element in the region, where w is a preset fixed value (e.g., w = 0), Zc is the lift value corresponding to the base matrix, and P... i,j It is determined based on Zc, where Z is... max Zc is the largest boost value in the predefined boost value set.

[0019] It should be understood that w is a row-related constant or a column-related constant. For example, if w is a row-related constant, it can be understood that w values ​​are the same for the same row or within the same row; if w is a column-related constant, it can be understood that w values ​​are the same for the same column or within the same column.

[0020] In conjunction with the first or second aspect, in some possible implementations, the translation value corresponding to the 1 element in another region of the at least two regions is determined by any of the remaining methods from method 1 to method 5 other than the method for determining the translation value corresponding to the one region.

[0021] In conjunction with the first or second aspect, in some possible implementations, at least one lift value corresponding to one of the at least two regions satisfies the first condition, and the translation value corresponding to the at least one lift value is determined in one of the following ways:

[0022] Method 1: or, or,

[0023] Method 2: SV i,j =P i,j *Zc / Zmax Or, SV i,j =P i,j *Zc / Z max +w;

[0024] Method 3: or, or,

[0025] Method 4: SV i,j =P i,j Or, SV i,j =P i,j +w;

[0026] Method 5: SV i,j =mod(P i,j ,Zc), or SV i,j =mod(P i,j +w,Zc),

[0027] Wherein, the SV i,j P is the element at row i and column j in the base matrix. i,j The predefined translation values ​​of the base matrix are the predefined translation values ​​corresponding to the 1 element in the region, where w is a preset fixed value, Zc is the lift value corresponding to the base matrix, and P... i,j It is determined based on Zc, where Z is... max The first condition is the largest boost value in the predefined boost value set to which Zc belongs, and is related to the threshold of the predefined boost value set to which Zc belongs.

[0028] It should be understood that the first condition is related to the value of the promotion value corresponding to the 1 element in the region, or it can be understood as a condition about the promotion value.

[0029] For example, if the first condition is that the boost value corresponding to the 1 element in the region is less than or equal to the boost value threshold, then the 1 element can obtain a translation value using any one of the methods 1 to 5 above; or, if the first condition is that the boost value corresponding to the 1 element in the region is greater than or equal to the boost value threshold, then the 1 element can obtain a translation value using any one of the methods 1 to 5 above; or, if the first condition is that the boost value corresponding to the 1 element in the region is within a preset boost value range, then the 1 element can obtain a translation value using any one of the methods 1 to 5 above.

[0030] The threshold for the boost value and the preset range for the boost value can both be predefined or preset, and this application does not limit the specific size.

[0031] For example, the first condition could be a piecewise function with respect to the lift value, which includes an interval corresponding to at least one lift value. If the lift value corresponding to the 1 element in the interval is within the interval corresponding to at least one lift value of the piecewise function, then the 1 element can be obtained as a translation value using any of the methods 1 to 5 described above.

[0032] In conjunction with the first or second aspect, the method for determining the translation value corresponding to the element 1 in another region of the at least two regions and the method for determining the translation value corresponding to the boost value in one region that does not satisfy the first condition are any of the remaining methods from methods 1 to 5, except for the method for determining the translation value corresponding to the at least one boost value.

[0033] In conjunction with the first or second aspect, when the region overlaps with the extended region in the base matrix, the overlapping portion of the region and the extended region is divided into a first part, a second part, and a third part. The number of edges corresponding to each row in the first part, the number of edges corresponding to each row in the second part, and the number of edges corresponding to the third part are all different. Specifically, the row number corresponding to the first part is less than a first threshold, the row number corresponding to the second part is greater than or equal to the first threshold and less than a second threshold, and the row number corresponding to the third part is greater than or equal to the second threshold and less than or equal to a third threshold.

[0034] It should be understood that the first threshold, the second threshold, and the third threshold are all line number thresholds, and the first threshold, the second threshold, and the third threshold are positive integers, the specific size of which is not limited in this application.

[0035] It should also be understood that there is a one-to-one correspondence between lines and bitrates.

[0036] In conjunction with the first or second aspect, the code rate corresponding to the first threshold is 1 / 2, the code rate corresponding to the second threshold is 1 / 3, and the code rate corresponding to the third threshold is 2 / 3.

[0037] Combining the first or second aspect, in In the case that each boost value in the predefined boost value group satisfies Where a is a positive integer, x0≥2 and is a preset constant, the value of a is different for each group of boost values, and k is from 0 to k max All integers, or k is from 1 to k max All integers, or k is from 2 to k max All integers.

[0038] In conjunction with the first or second aspect, the x0 corresponding to each group of boost values ​​is equal.

[0039] In conjunction with the first or second aspect, the P i,j satisfy:

[0040] Combining the first or second aspect, in In the case where each boost value in the predefined boost value group satisfies a×2 k or Alternatively, the predefined promotion group does not include the one being promoted. The group of promotion values ​​corresponding to divisible 'a'.

[0041] Where a is a positive integer, x0≥2 and is a preset constant, the value of a is different for each group of boost values, and k is from 0 to k max All integers, or k is from 1 to k max All integers, or k is from 2 to k max All integers.

[0042] In conjunction with the first or second aspect, the P i,j Satisfy: mod(P) i,j a×2 k ) = 0, Or the P mentioned above i,j Can be Divisible by.

[0043] In conjunction with the first or second aspect, the k max It is to satisfy The largest positive integer.

[0044] In conjunction with the first or second aspect, the Z max The possible values ​​are: 384, 256, 512, 1024, or 768.

[0045] In conjunction with the first or second aspect, the boost values ​​in the predefined boost value group to which Zc belongs satisfy the following conditions: The P i,j ,satisfy Wherein, k0 is a positive integer, and x is a positive integer.

[0046] In conjunction with the first or second aspect, k0 = x or k0 = x-1.

[0047] Combining the first or second aspect, x = 2, or k0 = 1, 2 or 3.

[0048] Based on the above scheme, when x=2, LDPC codes can achieve cyclic processing using the smallest units during the encoding and decoding process, maximizing the cyclic property and ensuring stable LDPC encoding and decoding performance. Simultaneously, it can also ensure that the density of the boost values ​​does not change significantly, contributing to the stable performance of fine-grained unique codes.

[0049] In addition, k0 = 1, 2 or 3, the segmentation method of k0 is simple and the hardware implementation is simple.

[0050] In conjunction with the first or second aspect, the region includes at least one column of the check column in the base matrix, or the region includes at least one column of the core check column in the base matrix, or the region includes the column corresponding to an odd number of column weights greater than 1 in the core check column.

[0051] In conjunction with the first or second aspect, the region includes the basis matrix H. BG1 The corresponding kb+1th column and rows 1 to 4; or, the region includes the H. BG1 The corresponding kb+1 to kb+4 columns, and rows 1 to 4; or, the region includes the H. BG1 The corresponding kb+1th column, and rows 1, 2, and 4; or, the region includes the H. BG1 The corresponding columns kb+1 to kb+4, and rows 1, 2, and 4, where kb is the number of information columns.

[0052] Thirdly, a communication apparatus is provided for performing the method provided by any of the above aspects or their implementations. Specifically, the apparatus may include units and / or modules for performing the method provided by any of the above aspects or their implementations, such as processing units and / or transceiver units.

[0053] In one implementation, the device is either a transmitting device or a receiving device. When the device is a transmitting device or a receiving device, the transceiver unit can be a transceiver, an input / output interface, or a communication interface; the processing unit can be at least one processor. Optionally, the transceiver is a transceiver circuit. Optionally, the input / output interface is an input / output circuit.

[0054] In another implementation, the device is a chip, chip system, or circuit used in a transmitting or receiving device. When the device is a chip, chip system, or circuit used in a transmitting or receiving device, the transceiver unit can be an input / output interface, interface circuit, output circuit, input circuit, pin, or related circuit on the chip, chip system, or circuit; the processing unit can be at least one processor, processing circuit, or logic circuit.

[0055] Fourthly, a communication device is provided, comprising: a memory for storing a program; and at least one processor for executing the computer program or instructions stored in the memory to perform the method provided in any of the foregoing aspects or their implementations.

[0056] In one implementation, the device is either a transmitting device or a receiving device.

[0057] In another implementation, the device is a chip, chip system, or circuit used in a transmitting or receiving device.

[0058] Fifthly, a communication device is provided, comprising: at least one processor and a communication interface, wherein the at least one processor is configured to obtain a computer program or instructions stored in a memory via the communication interface to execute the method provided in any of the foregoing aspects or their implementations. The communication interface may be implemented in hardware or software.

[0059] In one implementation, the device further includes the memory.

[0060] Sixthly, a processor is provided for executing the methods provided in the above aspects.

[0061] Unless otherwise specified, or if it does not contradict its actual function or internal logic in the relevant description, the transmission and acquisition / reception operations involved in the processor can be understood as processor output and reception, input and other operations, or as transmission and reception operations performed by radio frequency circuits and antennas. This application does not limit them in this regard.

[0062] In a seventh aspect, a computer-readable storage medium is provided that stores program code for execution by a device, the program code including methods for performing any of the foregoing aspects or their implementations.

[0063] Eighthly, a computer program product containing instructions is provided, which, when run on a computer, causes the computer to perform the method provided in any of the foregoing aspects or their implementations.

[0064] Ninthly, a chip is provided, comprising a processor and a communication interface. The processor reads instructions stored in a memory through the communication interface and executes the methods provided in any of the above aspects or their implementations. The communication interface can be implemented in hardware or software.

[0065] Optionally, as one implementation, the chip also includes a memory that stores computer programs or instructions. The processor is used to execute the computer programs or instructions stored in the memory. When the computer programs or instructions are executed, the processor is used to perform the methods provided by any of the above aspects or their implementations.

[0066] When the method provided in this application is executed by a chip, this application does not limit the specific number of chips implementing the method. For example, it can be executed by one chip, or by two or more chips. Furthermore, when the number of chips implementing the method is two or more, the chip manufacturers are not limited; they can be from the same manufacturer or different manufacturers.

[0067] In a tenth aspect, a computer program is provided that, when run on a computer, causes the methods provided by any of the foregoing aspects or their implementations to be executed.

[0068] Eleventhly, a communication system is provided, including at least one of the transmitting end device or receiving end device described above. Attached Figure Description

[0069] Figure 1 is a schematic diagram of a network architecture to which embodiments of this application can be applied.

[0070] Figure 2 is a schematic diagram of the parity check matrix H of an LDPC.

[0071] Figure 3 shows the Tanner plot of the parity-check matrix H of an LDPC.

[0072] Figure 4 is a schematic diagram of the structure of the parity check matrix.

[0073] Figure 5 is a schematic diagram of the information transmission process.

[0074] Figure 6 is a schematic flowchart of a communication method 600 provided in this application.

[0075] Figure 7 is a schematic block diagram of a communication device 700 provided in an embodiment of this application.

[0076] Figure 8 is a schematic block diagram of a communication device 800 provided in an embodiment of this application. Detailed Implementation

[0077] To facilitate understanding of the embodiments of this application, the following points will be explained before introducing the embodiments of this application.

[0078] The terms "for indicating" or "instruction" can include both direct and indirect indication, or they can be explicit and / or implicit. The various numerical designations such as "first," "second," etc., are merely for descriptive convenience and are not intended to limit the scope of the embodiments of this application, such as distinguishing different messages or different information. "Predefined" can be implemented by pre-storing corresponding codes, tables, or other methods that can be used to indicate relevant information in the device; this application does not limit the specific implementation method. The "protocol" involved can refer to standard protocols in the field of communication, such as the Long Term Evolution (LTE) protocol, the New Radio (NR) protocol, and related protocols applied to future communication systems; this application does not limit this. The words "exemplary," "for example," "exemplary," "as another example," etc., are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as an "example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. The terms "comprising," "including," "having," and variations thereof all mean "including but not limited to," unless otherwise specifically emphasized. "At least one" means one or more, while "more" means two or more. "At most one" means one or zero. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, and c can mean: a, or, b, or, c, or, a and b, or, a and c, or, b and c, or, a, b, and c. Here, a, b, and c can be single or multiple. Descriptions relating to network element A sending messages, information, or data to network element B, and network element B receiving messages, information, or data from network element A, aim to specify which network element the message, information, or data is intended for, without specifying whether the transmission is direct or indirect via other network elements. Descriptions such as "when," "under the circumstances," "if," and "if" indicate that the device will take corresponding action under certain objective conditions, not that there is a time limit, nor do they require the device to perform a judgment action during implementation, nor do they imply any other limitations.

[0079] Furthermore, the network architecture and business scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0080] The following describes a communication system to which embodiments of this application can be applied.

[0081] The embodiments of this application can be applied to various communication systems, including but not limited to: 5th generation (5G) systems, LTE systems, Long Term Evolution-Advanced (LTE-A) systems, LTE Frequency Division Duplex (FDD) systems, LTE Time Division Duplex (TDD) systems, etc. They can also be applied to future communication systems, such as 6th generation mobile communication systems. Furthermore, they can be applied to device-to-device (D2D) communication, vehicle-to-everything (V2X) communication, machine-to-machine (M2M) communication, machine-type communication (MTC), Internet of Things (IoT) communication systems, narrowband Internet of Things (NB-IoT) systems, or other communication systems. Furthermore, it can be extended to similar wireless communication systems, such as Wireless-Fidelity (WiFi), Worldwide Interoperability for Microwave Access (WIMAX), and communication systems related to the 3rd Generation Partnership Project (3GPP), without limitation.

[0082] The communication system applicable to embodiments of this application may include one or more transmitting devices and one or more receiving devices. Optionally, one of the transmitting device and the receiving device may be a terminal device, and the other may be a network device. Optionally, both the transmitting device and the receiving device may be terminal devices. Optionally, both the transmitting device and the receiving device may be network devices.

[0083] Figure 1 is a schematic diagram of a network architecture applicable to an embodiment of this application. As shown in Figure 1, the embodiments of this application can be applied to both uplink and downlink data transmission. Figure 1 only uses uplink or downlink data transmission between one network device and two terminal devices (such as terminal device 1 and terminal device 2) as an example. In uplink data transmission, the sending device is the terminal device and the receiving device is the network device; conversely, in downlink data transmission, the sending device is the network device and the receiving device is the terminal device. Furthermore, the applicability of the embodiments of this application in other communication scenarios is not limited; for example, they can also be applied to sidelink communication.

[0084] The terminal equipment in this application can also be referred to as user equipment (UE), access terminal, user unit, user station, mobile station, mobile station, mobile terminal (MT), remote station, remote terminal, mobile device, user terminal, terminal, drone, wireless communication equipment, user agent, or user device, etc. The terminal equipment in the embodiments of this application can be a device that provides voice and / or data connectivity to a user, and can be used to connect people, objects, and machines, such as handheld devices with wireless connectivity, vehicle-mounted devices, etc. The terminal devices in the embodiments of this application may be mobile phones, tablets, laptops, handheld computers, mobile internet devices (MIDs), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, etc.

[0085] The network equipment in this application can be a device with wireless transceiver capabilities, which can be a device that provides wireless communication services. It is usually located on the network side, including but not limited to next-generation base stations (gNodeB, gNB) in 5G systems, base stations in sixth-generation mobile communication systems, base stations in future mobile communication systems, or access nodes in wireless fidelity (WiFi) systems, evolved node B (eNB), radio network controller (RNC), node B (NB), base station controller (BSC), home base station (e.g., home evolved NodeB or home Node B, HNB), base band unit (BBU), transmission reception point (TRP), transmitting point (TP), base transceiver station (BTS), satellites, drones, etc. in long term evolution (LTE) systems. In a network architecture, network equipment may include centralized unit (CU) nodes, distributed unit (DU) nodes, or RAN equipment including CU and DU nodes, or RAN equipment including control plane CU nodes, user plane CU nodes, and DU nodes. Alternatively, network equipment may also be a radio controller, relay station, vehicle-mounted equipment, or wearable device in a cloud radio access network (CRAN) scenario. Furthermore, a base station may be a macro base station, micro base station, relay node, donor node, or a combination thereof. A base station may also refer to a communication module, modem, or chip installed within the aforementioned equipment or apparatus. A base station may also be a mobile switching center and equipment performing base station functions in D2D, V2X, and M2M communications, network-side equipment in future communication networks, or equipment performing base station functions in future communication systems. A base station may support networks with the same or different access technologies, without limitation.

[0086] Unless otherwise specified, the means for implementing the functions of a terminal device or network device in this application can refer to the terminal device or network device itself, or it can refer to a means that enables the terminal device or network device to implement the functions, such as a chip system or chip, specifically a system-on-a-chip (SoC) or a modem. This means can be installed in the terminal device or network device. In the embodiments of this application, the chip system can be composed of chips, or it can include chips and other discrete devices.

[0087] It should also be noted that some embodiments in this article use a 5G system as an example to introduce specific solution details. It is understood that when this solution is used in other communication systems, such as LTE systems, or future communication systems, the messages, channels, or information in the solution can be replaced with messages, channels, or information in other communication systems that can achieve the corresponding functions, and this application does not limit this.

[0088] Furthermore, the embodiments of this application can be applied to various application scenarios, such as high-throughput scenarios, high-reliability scenarios, low-latency scenarios, high-reliability low-latency scenarios, or low-power scenarios. Among them, high-throughput scenarios can be, for example, enhanced mobile broadband (eMBB) scenarios, high-reliability low-latency scenarios can be, for example, ultra-reliable low-latency communication (URLLC) scenarios, and low-power scenarios can be, for example, M2M scenarios, MTC scenarios, or IoT scenarios.

[0089] To facilitate understanding of the embodiments of this application, several concepts or terms involved in the embodiments of this application are briefly described. The concepts or terms described below are based on the concepts or terms specified in the agreement, but do not mean that the embodiments of this application can only be applied to existing systems. The concepts or terms involved in the embodiments of this application can be applied to future systems. Furthermore, the specific names of the concepts or terms (e.g., concepts or terms involving functional descriptions) can be adjusted as the system develops in the future.

[0090] 1. LDPC code

[0091] LDPC codes are a type of linear block code. Linear block codes divide the information sequence to be encoded into groups of q bits each. The encoder then performs linear operations on these q information bits to obtain m parity bits. These q information bits are then combined with the m parity bits to obtain a codeword of length n = q + m. The mapping from q information bits to an n-bit codeword is typically represented by a parity check matrix H. Based on the parity check matrix H, a codeword sequence can be generated to complete the encoding process. After the codeword sequence is transmitted through the channel, the receiving equipment decodes the received signal to determine the original information bits.

[0092] The parity-check matrix H of an LDPC is a sparse matrix. The number of zero elements in the parity-check matrix H is far greater than the number of non-zero elements; in other words, the row weight (or column weight) of the parity-check matrix is ​​far less than the number of elements in each row (or column) of the LDPC matrix. Specifically, an LDPC code with an information bit sequence length of q and a code length of n can be uniquely determined by its parity-check matrix H.

[0093] In 1981, Tanner represented the parity-check matrix H graphically, and this type of graph is now called a Tanner graph. There is a one-to-one correspondence between the Tanner graph and the parity-check matrix. A Tanner graph consists of two types of vertices: one type represents codeword bits and is called variable nodes, and the other type consists of parity nodes, representing parity constraints. Each parity node represents a parity constraint, which will be explained below with reference to Figures 2 and 3.

[0094] Figure 2 is a schematic diagram of the parity check matrix H of an LDPC.

[0095] In Figure 2, {V i} represents the set of variable nodes (VN), {C i} represents the set of check nodes (CNs). Each row of the check matrix H represents a check equation, and each check equation corresponds to a check node. Each column represents a codeword bit, and each codeword bit corresponds to a variable node. In Figure 2, there are 8 variable nodes and 4 check nodes. If a codeword bit is included in the corresponding check equation, a line is used to connect the involved variable nodes and check nodes to obtain the Tanner graph.

[0096] Figure 3 is a Tanner plot of the parity-check matrix H of an LDPC.

[0097] As shown in Figure 3, the Tanner graph represents the parity-check matrix of the LDPC. For example, for a parity-check matrix H of size m rows and n columns, the Tanner graph contains two types of nodes: n variable nodes and m parity nodes. The n variable nodes correspond to the n columns of the parity-check matrix H, and the m parity nodes correspond to the m rows of the parity-check matrix H. A cycle in the Tanner graph consists of interconnected vertices. The cycle starts and ends at one vertex in this group of vertices and passes through each node only once. The length of a cycle is defined as the number of edges it contains, and the perimeter of the graph, also known as the graph's circumference, is defined as the minimum cycle length in the graph. In Figure 3, the perimeter is 4, as shown by the bolded lines. The variable nodes in the Tanner graph correspond to each column of the parity-check matrix H, which is equivalent to each codeword bit in the LDPC. The parity nodes in the Tanner graph correspond to each row of the parity-check matrix H, which is equivalent to the parity bits in the LDPC. The connections between the two types of nodes correspond to the values ​​of the elements in the H matrix. If there is a connection between the i-th check node and the j-th variable node, then the element (i, j) in the H matrix has a value of 1; if there is no connection, the corresponding element is 0. The connection between a variable node and a check node can also be called an edge. A connection between a check node and a variable node can also be described as: there is a connection or an edge between the check node and the variable node. The edge relationship between a check node and a variable node can include either the presence of an edge or the absence of an edge. Furthermore, in a Tanner graph, a cycle is a closed loop formed by connecting variable nodes, check nodes, and edges end-to-end.

[0098] 2. QC-LDPC code

[0099] QC-LDPC codes are a type of structured LDPC codes. Due to the unique structure of their parity-check matrix, encoding can be implemented using a simple feedback shift register, reducing the encoding complexity of LDPC codes. In practice, QC-LDPC codes are represented using a base graph (BG), where elements are either 0 or 1. Expanding the 1s and 0s in the BG yields a parity-check matrix H, which can be used for encoding or decoding. In the embodiments of this application, the BG can be written in matrix form, which can be referred to as the base matrix H in this application. BG Basis matrix H BGAn element of 0 indicates that there are no edges in the base graph, while a value of 1 indicates that there are edges in the base graph (or that the corresponding check is associated with the corresponding variable). NR LDPC codes involve multiple base graph selection; currently, the standard stores two base graphs, BG1 and BG2. BG2 is used when the information length is less than or equal to 292, or when the information length is less than or equal to 3824 and the code rate is less than or equal to 2 / 3, or when the code rate is less than or equal to 0.25; otherwise, BG1 is used. The expansion process of the base matrix is ​​described below.

[0100] Based on the basis matrix and the boosting value Z c (Lifting size) allows the basis matrix to be expanded into a complete parity-check matrix for encoding or decoding. In this application, Z... c It can also be called the expansion factor, lifting factor, expansion value, expansion coefficient, lifting size, etc. The expansion process involves lifting all elements in the basis matrix to a Z-shape. c ×Z c A square matrix, in which 0 is promoted to Z. c ×Z c The zero matrix is ​​promoted to an identity matrix, and then cyclically shifted based on the shifting value (SV) corresponding to the 1. This cyclic shift can be to the left or right, which is not limited in this application. It can be understood that each 1 in the base matrix corresponds to a shifting value. Taking a 4*4 identity matrix as an example, if the shifting values ​​are 0, 1, 2, and 3, the cyclically shifted matrix after shifting to the right is as follows:

[0101] (1) When the translation value is 0 (i.e., remains unchanged), the corresponding cyclically shifted matrix is:

[0102] (2) When the translation value is 1, the corresponding cyclically shifted matrix is:

[0103] (3) When the translation value is 2, the corresponding cyclically shifted matrix is:

[0104] (4) When the translation value is 3, the corresponding cyclically shifted matrix is:

[0105] Alternatively, it can be understood that the complete parity check matrix H can be derived from an exponential matrix H. b H indicates b Each element in the array corresponds to a Z. c ×Z c The submatrix is ​​represented by an exponential matrix H, where each element indicates the number of times the corresponding submatrix has been cyclically shifted by the identity matrix. This significantly reduces the storage space required for the complete parity check matrix H. bThe elements in it can also be called QC blocks.

[0106] For example, the exponent matrix H of the QC-LDPC code b As shown below:

[0107] It can be seen that the exponent matrix H b The size is 4 rows and 24 columns, and the exponent matrix H b Each element i in the array represents a Z. c Square matrix of order Let represent a cyclic shift matrix, where i represents the cyclic shift value of the cyclic shift matrix, and i is an integer. Additionally, the exponent matrix H... b In this context, "-1" represents a zero matrix and "0" represents the identity matrix.

[0108] For example, As shown below:

[0109] Optional, exponent matrix H b In addition to "-1", zero elements in the matrix can also be represented in other ways, such as using "-" or null values ​​to represent a matrix of all zeros.

[0110] It is understandable that the above exponent matrix H b The matrix corresponding to the positions greater than or equal to 0 that are changed to 1 and the positions of -1 that are changed to 0 is the base matrix. The 1s in the base matrix are then expanded into a cyclic shift matrix based on the corresponding elements of the exponent matrix, and the 0s are expanded into a 0 matrix of the corresponding size. After expansion, the parity check matrix is ​​obtained.

[0111] 3. Increase value Z c (Lifting Size) and (Shifting Value)

[0112] The storage content of the 5G LDPC code regarding shifting values ​​includes: (1) a list of lifting sizes; and (2) a list of shifting values ​​that correspond one-to-one with the rows of the lifting size list.

[0113] For example, the list of Lifting Sizes is shown in Table 1.

[0114] Table 1

[0115] The j-th row of the Lifting Size list includes Where a j ∈{2,3,5,7,9,11,13,15}, max(kj )∈{7,7,6,5,5,5,4,4}; The row index of Lifting Size corresponds one-to-one with the column index of Shifting Value, that is, the lifting size in each row of the Lifting Size list corresponds to a set of Shifting Values.

[0116] For example, the list of Shifting Values ​​is shown in Table 2.

[0117] Table 2

[0118] It is understandable that the basis matrix H BG The elements in the matrix include 0 and 1, meaning all elements are either 0 or 1. Table 2 stores all rows of the base matrix and the associated columns for each row. If an associated column exists, it indicates that the value at that position in the base matrix is ​​1; otherwise, it is 0.

[0119] For a fixed lift index, a non-zero position in the base matrix corresponds to one translation value. For example, H... BG The shift value corresponding to row 0, column 0 when the promotion index is 0 is 211, H BG The shift value corresponding to the 6th column of the 1st row in the middle when the lifting index = 3 is 66, H BG The shift value corresponding to the second row and ninth column of the middle column when the promotion index is 7 is 206.

[0120] It's understandable that LDPC encoding requires first determining the lift value, and then constructing a parity check matrix based on the corresponding shift value. For example, if the determined lift value is 40, and the lift value index corresponding to 40 in Table 1 is 2, then the parity check matrix can be constructed based on the shift value in the column corresponding to lift value index = 2 in Table 2.

[0121] 4. Column weight and row weight

[0122] For a given column of a matrix, column weight refers to the number of non-zero elements contained in that column. For a given row of a matrix, row weight refers to the number of non-zero elements contained in that row. It can be understood that the matrix involved in the descriptions of row and column weights is the parity check matrix H.

[0123] 5. Structure of the basis matrix

[0124] Figure 4 is a schematic diagram of the structure of the parity check matrix.

[0125] As shown in Figure 4(a), the parity check matrix can include a high-rate region, an all-zero region, an incremental redundancy region, and a raptor-like region. The high-rate region can include parts A and B as shown in Figure 4(b). Part A corresponds to information bits (or information digits, system bits, etc.), and part B is a square matrix corresponding to the core parity bits (or core parity digits). The core parity can be the parity corresponding to the highest bit rate, or it can be a parity with a degree greater than or equal to 2, or it can be the parity node corresponding to the row set with the largest row weight (row weight significantly higher than other rows). The all-zero region can correspond to part C in Figure 4(b) and is an all-zero matrix. The incremental redundancy region can correspond to part D in Figure 4(b). The raptor-like region can correspond to part E in Figure 4(b) and can be an identity matrix corresponding to the parity bits of the low-rate extension.

[0126] The parity-check matrix of the LDPC code shown in Figure 4 adopts a "raptor-like" structure, which can be gradually extended to low code rates from a high code rate core matrix. In actual use, as shown in Figure 4(a), the first X rows and the first Y columns of the parity-check matrix can be extracted. As the code rate decreases, X and Y gradually increase, and the area of ​​the matrix used also gradually expands.

[0127] It should be noted that the parity check matrix can be represented by the LDPC basis matrix. Therefore, the structure of the LDPC basis matrix is ​​similar to that of the parity check matrix, and will not be described in detail here.

[0128] 6. Information column and validation column

[0129] The columns of the LDPC base matrix consist of information columns and check columns.

[0130] Information column: Corresponding to information bits (or information bits, system bits, etc.), it is the column corresponding to part A.

[0131] Check columns: Corresponding to check bits (or check digits, etc.), these can include core check columns and extended check columns. The core check columns are the columns corresponding to part B, and the extended check columns are the columns corresponding to part C or part E. Extended check columns can also be called raptor-like columns.

[0132] 7. Core rows, core columns, core matrix, and core check columns

[0133] Core rows: The core rows of the LDPC base matrix correspond to the core parity bits. In other words, the core rows are the rows corresponding to high bitrate regions, or the rows corresponding to parts A, B, or C.

[0134] Core columns: These can include all information columns and all core check columns. In other words, core columns are the columns corresponding to high bitrate areas, or the columns corresponding to part A plus part B.

[0135] The kernel matrix is ​​a matrix region consisting of all the kernel rows and columns of the LDPC base matrix. In other words, the kernel matrix is ​​the high-rate region of the LDPC base matrix, or the part consisting of part A and part B.

[0136] Core check columns: N columns following the information columns in the LDPC base matrix, where N equals the number of rows corresponding to the core rows. For example, the information columns are 1 to K. b If the column is K, then the core verification column is K. b +1 to K b +N columns. This core verification column corresponds to the verification region where both the lower and upper triangular areas have non-zero positions.

[0137] 8. Message length, code length, and code rate

[0138] The information length is the length of the bit sequence of information to be sent (i.e., the number of bits contained therein). This length can be the length of the payload information bits, or the length of the payload information bits after adding cyclic redundancy check (CRC) bits. This application does not impose any specific restrictions.

[0139] Code length refers to the length of the bit sequence to be transmitted, which can be the transmitted bit sequence corresponding to the modulated symbol.

[0140] Code rate refers to the ratio of the length of the bit sequence of information to be transmitted to the code length.

[0141] Optionally, the above three values ​​can be pre-configured by higher-layer signaling, media access control (MAC) layer, or downlink physical layer signals, or they can be directly obtained and calculated by the transceiver. For example, the code length can be determined by the frame structure, number of layers, and modulation scheme of the encoded and transmitted information bit sequence; the code rate can be indicated in the above manner or given in the modulation and coding scheme (MCS).

[0142] 9. Information Transmission Process

[0143] Figure 5 is a schematic diagram of the information transmission process applicable to this application. As shown in Figure 5, information is sent from the source, undergoes source coding, channel coding, modulation, air interface transmission, demodulation, channel decoding, and source recovery, and finally reaches the destination, completing the transmission of information from the source to the destination. The processing shown in the upper layer of Figure 5 (including source coding, channel coding, and modulation) is performed at the transmitting end device, while the processing shown in the lower layer (including demodulation, channel decoding, and source recovery) is performed at the receiving end device. The embodiments of this application mainly involve the source coding, channel coding, channel decoding, and source recovery shown in Figure 5.

[0144] It should be understood that the 5G communication protocol standard describes two base diagrams: BG1 and BG2. BG2 is used when the information length is less than or equal to 292, or less than or equal to 3840 and the code rate is less than or equal to 2 / 3, or less than or equal to 0.25; otherwise, BG1 is used. It can be understood that the BG1 (or BG2) described in this application refers to either the 5G BG1 (or BG2) or the NR BG1 (or BG2).

[0145] In NR systems, the translation values ​​corresponding to the base graph of LDPC codes are all obtained globally using the same method (which can be called the translation value acquisition method or the nested translation value method), resulting in significant limitations on the translation values. When the matrix translation values ​​need to play other roles, other methods must be used to determine them. For example, if the translation values ​​of the coding region need to ensure local full rank for easy hardware encoding, then the method for obtaining the translation values ​​corresponding to the base graph of the LDPC code needs to be modified. Many existing nested methods cannot be applied to the global scope of the LDPC code base graph, cannot guarantee the good cyclic properties of the global LDPC base graph, and cannot guarantee the performance of the LDPC code.

[0146] LDPC codes also include a double-diagonal encoding scheme. The main features of this double-diagonal encoding scheme include a double-diagonal structure, with the degree distribution consisting of one triple column and the remaining columns being double columns. The two translation values ​​of the double column are the same, and of the three translation values ​​of the triple column, two translation values ​​are the same, while the third translation value is different from the other two translation values.

[0147] It should be understood that the shift value characteristics of LDPC codes with double-diagonal encoding ensure that encoding can be performed in a simple manner. The specific encoding process involves XORing all parity equations to obtain the bit values ​​of the parity nodes corresponding to the three columns. Then, new parity bit values ​​are obtained based on the currently obtained bit values ​​until all parity bits are obtained. However, LDPC codes require high reliability and cannot have significant error floors. The special shift value characteristics of LDPC codes with double-diagonal encoding cause a large number of small trap sets at each boost value, making them prone to error floors.

[0148] In view of this, this application proposes a communication method based on LDPC codes, which can effectively solve the above-mentioned technical problems.

[0149] Figure 6 is a schematic flowchart of a communication method 600 based on LDPC codes provided in this application. The method includes the following steps.

[0150] It is understood that method 600 can be executed by both the sending device and the receiving device. Unless otherwise specified, "sending device" or "receiving device" can refer to the sending device or receiving device itself, or it can refer to a device that enables the sending device or receiving device to implement this function. For ease of description, the following text will use "sending device" and "receiving device" to describe it. Among them, the sending device can be a terminal device or a network device, and the receiving device can be a terminal device or a network device.

[0151] S610, the transmitting device obtains the information bit sequence.

[0152] It is understandable that if the sending device needs to communicate with the receiving device, that is, if the sending device needs to send a signal to the receiving device, then the sending device needs to first obtain the information bit sequence corresponding to the signal to be sent to the receiving device.

[0153] The process of the transmitting device acquiring the information bit sequence can refer to: the transmitting device performing source encoding on the source symbols to generate the information bit sequence; or, the transmitting device acquiring the information bit sequence can also refer to: the transmitting device receiving the information bit sequence from other communication devices. This application does not limit the method of acquiring the information bit sequence.

[0154] S620, the transmitting device determines the LDPC check matrix.

[0155] The LDPC parity-check matrix is ​​determined based on the LDPC base matrix (hereinafter referred to as the base matrix). The base matrix includes at least two regions, any two of which are complementary and coincident, and the translation values ​​corresponding to the two regions are obtained in different ways.

[0156] The following will provide an exemplary description of how to obtain the translation value corresponding to one of the at least two regions included in the base matrix.

[0157] It should be understood that the basis matrix is ​​assumed to include at least two regions, which include one region and another region, wherein the translation value corresponding to the one region is obtained in a different way than the translation value corresponding to the other region.

[0158] In one possible implementation, the translation value corresponding to the element 1 in one of the at least two regions can be obtained in one of the following ways:

[0159] Method 1: or, or,

[0160] Method 2: SV i,j =P i,j *Zc / Z max Or, SV i,j =P i,j *Zc / Z max +w;

[0161] Method 3: or, or,

[0162] Method 4: SV i,j =P i,j Or, SV i,j =P i,j +w;

[0163] Method 5: SV i,j =mod(P i,j ,Zc), or SV i,j =mod(P i,j +w,Zc),

[0164] Among them, SV i,j P is the element at row i and column j in the basis matrix. i,j Let w be a predefined translation value corresponding to the 1 element in a region, where w is a preset fixed value (e.g., w = 0), Zc is the lifting value corresponding to the basis matrix, and P is the predefined translation value. i,j It is determined based on Zc, Zmax The largest boost value in the predefined boost value set containing Zc.

[0165] It should be understood that w is a row-related constant or a column-related constant. For example, if w is a row-related constant, it can be understood that w values ​​are the same for the same row or within the same row; if w is a column-related constant, it can be understood that w values ​​are the same for the same column or within the same column.

[0166] It should also be understood that the translation value corresponding to the 1 element in one of the at least two regions is obtained in one of the methods 1 to 5 above. Correspondingly, the translation value corresponding to the 1 element in the other region of the at least two regions is obtained in any other method besides one of the methods 1 to 5 above.

[0167] In another possible implementation, the translation value corresponding to the 1 element that satisfies the first condition in one of the at least two regions can be obtained in one of the following ways:

[0168] Method 1: or, or,

[0169] Method 2: SV i,j =P i,j *Zc / Z max Or, SV i,j =P i,j *Zc / Z max +w;

[0170] Method 3: or, or,

[0171] Method 4: SV i,j =P i,j Or, SV i,j =P i,j +w;

[0172] Method 5: SV i,j =mod)P i,j ,Zc), or SV i,j =mod(P i,j +w,Zc),

[0173] Among them, SV i,j P is the element at row i and column j in the basis matrix. i,jLet w be a predefined translation value corresponding to the 1 element in a region, where w is a preset fixed value, Zc is the lifting value corresponding to the basis matrix, and P is the predefined translation value. i,j It is determined based on Zc, Z max The largest boost value in the predefined boost value set containing Zc.

[0174] It should be understood that the first condition is related to the value of the promotion value corresponding to the 1 element in the region, or it can be understood as a condition about the promotion value.

[0175] For example, if the first condition is that the boost value corresponding to the 1 element in the region is less than or equal to the boost value threshold, then the 1 element can obtain a translation value using any one of the methods 1 to 5 above; or, if the first condition is that the boost value corresponding to the 1 element in the region is greater than or equal to the boost value threshold, then the 1 element can obtain a translation value using any one of the methods 1 to 5 above; or, if the first condition is that the boost value corresponding to the 1 element in the region is within a preset boost value range, then the 1 element can obtain a translation value using any one of the methods 1 to 5 above.

[0176] The threshold for the boost value and the preset range for the boost value can both be predefined or preset, and this application does not limit the specific size.

[0177] For example, the first condition could be a piecewise function with respect to the lift value, which includes at least one segmented interval corresponding to the lift value. If the lift value corresponding to the 1 element in a region is within the interval corresponding to at least one lift value in the piecewise function, then the 1 element can be shifted using any of the methods 1 to 5 described above.

[0178] It should also be understood that the translation value corresponding to the 1 element that satisfies the first condition in a region can be obtained using methods 1 to 5 described above. For the 1 element in a region that does not satisfy the first condition and the other region in at least two regions, any of the remaining methods other than the method for obtaining the translation value corresponding to the 1 element that satisfies the first condition in one region can be selected. The method for obtaining the translation value corresponding to the 1 element that does not satisfy the first condition in one region and the method for obtaining the translation value corresponding to the other region in at least two regions can be the same or different methods.

[0179] Next, we will provide an illustrative description of the specific location of one of the at least two regions in the base matrix, as well as the edge characteristics of that region.

[0180] It should be understood that the specific location of a region within the base matrix can be divided according to columns.

[0181] It should be understood that, referring to the schematic diagram of the basis matrix shown in Figure 4 above, the basis matrix includes X rows and Y columns. Specifically, part A in Figure 4 is the region consisting of rows 1 to x1 and columns 1 to y1 of the basis matrix. Part B is the region consisting of rows 1 to x1 and columns y1+1 to y2 of the basis matrix; the matrix corresponding to part B is a square matrix. Part C is the region consisting of rows 1 to x1 and columns y2+1 to Y of the basis matrix; the matrix corresponding to part C is a matrix consisting of all zeros. Part D is the region consisting of rows x1+1 to X and columns 1 to y2 of the basis matrix. Part E is the region consisting of rows x1+1 to X and columns y2+1 to Y of the basis matrix; the matrix corresponding to part E is an identity matrix. Where 1 ≤ x1 ≤ X, 1 ≤ y1 ≤ y2 ≤ Y, and x1, X, y1, y2, and Y are all integers.

[0182] In one possible implementation, the region includes at least one column of the parity column in the base matrix. Referring to the five parts A, B, C, D, and E of the base matrix shown in Figure 4, the region including at least one column of the parity column can be at least one column of the region consisting of rows 1 to x1 to X and columns y1+1 to y2 in Figure 4.

[0183] In another possible implementation, the region includes at least one column of the core check column in the base matrix. Referring to the five parts A, B, C, D, and E of the base matrix shown in Figure 4, the region including at least one column of the core check column in the base matrix can be at least one column of the region consisting of rows 1 to x1 and columns y1+1 to y2 in Figure 4.

[0184] In another possible implementation, the region includes the columns corresponding to odd numbers with a column weight greater than 1 in the core check column of the base matrix.

[0185] It should be understood that, assuming the core check column in the base matrix (e.g., part B in Figure 4) has a double-diagonal coding matrix structure, this core check column has exactly one column with a weight of 3 and exactly one row with a row weight of 3. All columns in this core check column except those with a weight of 3 have a weight of 2, and all rows in this core check column except those with a row weight of 2 have a row weight of 2. The two 1 elements in the column with a weight of 2 have the same shift value. This region includes the column with a weight of 3 in this core check column.

[0186] Based on the specific location of this region in the basis matrix described above, the following will provide an example of the specific range of regions that this region may be located in the basis matrix.

[0187] For example, this region includes a basis matrix (e.g., H). BGthe (kb + 1)-th column and the 1st to 4th rows in BG the (kb + 1)-th to (kb + 4)-th columns and the 1st to 4th rows in BG the (kb + 1)-th column, and the 1st, 2nd, and 4th rows; or, the one region includes the (kb + 1)-th to (kb + 4)-th columns in the base matrix, and the 1st, 2nd, and 4th rows. Wherein, the kb (or referred to as Kb) is the number of information columns.

[0188] The above introduced determining the position of the one region in the base matrix based on the columns in the base matrix. Wherein, the columns in the one region can satisfy the following characteristics:

[0189] When there is an overlapping part between the one region and the extended region in the base matrix (such as part C in Figure 4), this overlapping part can be referred to as the extended region of the one region. The overall extended region of the one region has a gradually decreasing code rate as the row number gradually increases. Wherein, the extended region of the one region is a matrix region in the base matrix, the columns corresponding to the extended region of the one region are the core columns in the base matrix, and the rows corresponding to the extended region of the first region are the check rows corresponding to the non-core check bits (raptor-like check bits).

[0190] In a possible implementation manner, the number of connected edges of the extended region of the one region can be divided into different segments or parts according to the row number. For example, the extended region of the one region can be divided into three segments or three parts. In this application, it is exemplarily described by dividing it into three parts.

[0191] For example, the extended region of a region is divided into: the first part, the second part, and the third part. The number of connected edges corresponding to each row in the first part, the second part, and the third part is different. Wherein, the row number corresponding to the first part is less than the first threshold, the row number corresponding to the second part is greater than or equal to the first threshold and less than the second threshold, and the row number corresponding to the third part is greater than or equal to the second threshold and less than or equal to the third threshold.

[0192] Wherein, the first threshold, the second threshold, and the third threshold are all row number thresholds, and the first threshold, the second threshold, and the third threshold are positive integers, and the specific sizes are not limited in this application.

[0193] Assume that the first threshold is i1, the second threshold is i2, and the third threshold is i3, i1 < i2 < i3, and i1, i2, i3 are all positive integers. In the extended region of the one region, the rows with row numbers less than i1 are the first part, the rows with row numbers greater than or equal to i1 and less than i2 are the second part, and the rows with row numbers greater than or equal to i2 and less than or equal to i3 are the third part.

[0194] It should be understood that the number of edges in the first, second, and third parts of a region is a fixed value, and the number of non-regular grouping structures in each part can increase with the first, second, and third parts.

[0195] For example, the number of edges in each row of the first, second, and third parts is 0, 1, and 2, respectively; or there exists a row number i′ such that the number of edges in the extended region of a region less than or equal to row number i′ is 0, and the number of non-regular group structures of row numbers greater than i′ is 1 or 2. More specifically, this threshold can be the total number of rows (i.e., the number of edges is always 0); or the row number threshold (e.g., the first threshold, the second threshold, and the third threshold) corresponds to a code rate of 1 / 2, 1 / 3, and 2 / 3, respectively.

[0196] Next, we will introduce the relevant characteristics of the promotion value corresponding to the 1 element in this region.

[0197] In one possible implementation method, In this case, each set of boost values ​​in the predefined boost value set satisfies

[0198] Where 'a' is a positive integer, x0 ≥ 2, x0 is a preset constant (e.g., a positive integer), the value of 'a' is different for each boost value, and k ranges from 0 to k. max All integers, or k is from 1 to k max All integers, or k is from 2 to k max All integers.

[0199] Optionally, each set of boost values ​​in the predefined boost value set has the same x0.

[0200] Optionally, the P i,j satisfy:

[0201] For example, if a = 5 and x0 = 2, the set of lift values ​​satisfies 5 × 3 × 2k, where Z max =240, k0=1, translation value P i,j =100. Therefore, the translation value satisfies the condition mod(3*100,5×3)=0.

[0202] In another possible way of implementation, In this case, each boost value in the predefined boost value group satisfies a×2 k or Alternatively, the predefined promotion group does not include the one being promoted. The group of promotion values ​​corresponding to 'a' that are divisible by 'a'.

[0203] Where 'a' is a positive integer, x0 ≥ 2, x0 is a preset constant (e.g., a positive integer), the value of 'a' is different for each boost value, and k ranges from 0 to k. max All integers, or k is from 1 to k max All integers, or k is from 2 to k max All integers.

[0204] Optionally, each set of boost values ​​in the predefined boost value set has the same x0.

[0205] Optionally, the P i,j Satisfy: mod(P) i,j a×2 k ) = 0, Or P i,j Can be Divisible by P. i,j If any of the above conditions are met, the LDPC code can be guaranteed to form a stable structure during the encoding and decoding process. The units are cyclical to ensure the loop property of LDPC codes, avoid the formation of error flat layers, and ensure the performance stability of LDPC codes.

[0206] For example, the preset boost value group includes:

[0207] ID=0, a=2, Promotion group #0: {6, 12, 24, 48, 96, 192, 384}

[0208] ID=1, a=3, promotion group #1: {} (i.e., this promotion group does not exist).

[0209] ID=2, a=5, Promotion group #2: {15, 30, 60, 120, 240}

[0210] It should be understood that, or In this case, the k max It is to satisfy The largest positive integer Z. max The possible values ​​are: 384, 256, 512, 1024, or 768.

[0211] For example, when x0 = 2, LDPC codes can cycle through the smallest units during encoding and decoding, maximizing the cyclic property and thus ensuring performance stability. Simultaneously, the density of the boost values ​​does not change significantly, contributing to the stability of fine-grained unique code lengths.

[0212] For example, k0 = 1, 2, or 3. This k0 segmentation method is simple and easy to implement in hardware.

[0213] It should be understood that the general form of the lift value set described above can also be segmented with respect to k. That is, when k is less than or equal to a certain threshold (e.g., k0), the lift value set satisfies: a×2 k ,or Or the predefined promotion group does not include the recipient. The set of lift values ​​corresponding to divisible 'a'; when k is greater than k0, the set of lift values ​​satisfies: The specific characteristics are all the same as those described above, and all of them are valid.

[0214] In another possible implementation, the boost values ​​in this predefined boost value set satisfy... The P i,j ,satisfy

[0215] Where k0 is a positive integer and x is a positive integer.

[0216] It should be understood that the specific value of k0 can be the value of k corresponding to the aforementioned boost threshold. Therefore, k0 can be used as the segmented threshold for obtaining the shift value.

[0217] Optionally, k0 = x or k0 = x-1.

[0218] For example, x = 2, or k0 = 1, 2, or 3.

[0219] For example, if a = 3, the set of lift values ​​satisfies: 3 × 2 k Among them, Z max =192, k0=2, the translation value P i,j =16, then x=2, translation value P i,j The feature mod(3*16,12) = 0 is satisfied.

[0220] It should be understood that k0 = x, or k0 = x-1, can guarantee the loop property of LDPC codes during the encoding and decoding process, as well as the stability of their performance.

[0221] It should be understood that when x0 = 2, LDPC codes can cycle through the smallest units during the encoding and decoding process, maximizing the cyclic property and thus ensuring performance stability. Simultaneously, the density of the boost value does not change significantly, contributing to the stability of fine-grained unique code lengths.

[0222] It should also be understood that k0 = 1, 2, or 3. This k0 segmentation method is simple and easy to implement in hardware.

[0223] S630: The transmitting device encodes the information bit sequence according to the LDPC parity check matrix to obtain the codeword sequence.

[0224] S640, the transmitting device sends a codeword sequence to the receiving device. Correspondingly, the receiving device receives the codeword sequence from the transmitting device.

[0225] It should be noted that, since channel noise may be introduced during the transmission of the codeword sequence, the LDPC codeword sequence output or transmitted by the transmitting device may be different from the LDPC codeword sequence received by the receiving device.

[0226] In S650, the receiving device decodes the codeword sequence according to the LDPC parity check matrix to obtain the information bit sequence.

[0227] The LDPC check matrix used for decoding by the receiving device is the same as the LDPC check matrix used for encoding by the sending device. The specific method by which the receiving device determines the LDPC check matrix can be found in the description on the sending device side, and will not be detailed here.

[0228] The scheme shown in Figure 6 above uses different methods to obtain translation values ​​for at least two regions in the basis matrix, thereby optimizing the loop property of the LDPC code and ensuring the performance stability of the LDPC code.

[0229] It is understood that the steps in the above figures are merely illustrative and are not intended to be strictly limited. Furthermore, the sequence numbers of the processes described above do not imply a specific order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0230] It is also understood that some optional features in the various embodiments of this application may not depend on other features in some scenarios, or may be combined with other features in some scenarios, without limitation.

[0231] It is also understood that, in the above-described method embodiments, the methods and operations implemented by the device (transmitting device or receiving device) can also be implemented by components of the device (such as chips or circuits), without limitation.

[0232] The method embodiments provided in this application have been described in detail above with reference to Figures 1 to 6. The apparatus embodiments of this application will now be described with reference to Figures 7 and 8. It is understood that, in order to implement the functions in the above embodiments, the apparatuses in Figures 7 and 8 include hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should readily recognize that, based on the units and method steps of the various examples described in conjunction with the embodiments disclosed in this application, this application can be implemented in hardware or a combination of hardware and computer software. It is understood that the technical features described in the above method embodiments are also applicable to the following apparatus embodiments.

[0233] Figures 7 and 8 are schematic diagrams of possible apparatus structures provided in embodiments of this application. These apparatuses can be used to implement the functions of the transmitting or receiving devices in the above method embodiments, and thus can also achieve the beneficial effects of the above method embodiments.

[0234] Figure 7 is a schematic block diagram of a communication device 700 provided in an embodiment of this application. As shown in Figure 7, the device 700 may include a communication unit 710 and a processing unit 720. The communication unit 710 can communicate with the outside world, and the processing unit 720 is used for data processing. The communication unit 710 may also be referred to as a communication interface or a transceiver unit.

[0235] In one possible design, the device 700 can implement the steps or processes corresponding to those performed by the transmitting device in the above method embodiments, wherein the processing unit 720 is used to perform processing-related operations of the transmitting device in the above method embodiments, and the communication unit 710 is used to perform transmission-related operations of the transmitting device in the above method embodiments.

[0236] In another possible design, the device 700 can implement the steps or processes corresponding to those performed by the receiving device in the above method embodiments, wherein the communication unit 710 is used to perform the receiving-related operations of the receiving device in the above method embodiments, and the processing unit 720 is used to perform the processing-related operations of the receiving device in the above method embodiments.

[0237] It is understood that the device 700 here is embodied in the form of a functional unit. The term "unit" here can refer to an application-specific integrated circuit (ASIC), electronic circuitry, a processor (e.g., a shared processor, a proprietary processor, or a group processor, etc.) and memory for executing one or more software or firmware programs, combined logic circuitry, and / or other suitable components supporting the described functions. In an alternative example, those skilled in the art will understand that device 700 may specifically be the transmitting end device in the above embodiments, used to execute the various processes and / or steps corresponding to the transmitting end device in the above method embodiments; or, device 700 may specifically be the receiving end device in the above embodiments, used to execute the various processes and / or steps corresponding to the receiving end device in the above method embodiments. To avoid repetition, further details are omitted here.

[0238] The apparatus 700 of each of the above-described schemes has the function of implementing the corresponding steps performed by the transmitting device in the above-described method, or the apparatus 700 of each of the above-described schemes has the function of implementing the corresponding steps performed by the receiving device in the above-described method. The function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above functions; for example, the communication unit can be replaced by a transceiver (e.g., the transmitting unit in the communication unit can be replaced by a transmitter, and the receiving unit in the communication unit can be replaced by a receiver), and other units, such as processing units, can be replaced by a processor, respectively executing the transmission and reception operations and related processing operations in each method embodiment.

[0239] Furthermore, the aforementioned communication unit can also be a transceiver circuit (e.g., it may include a receiving circuit and a transmitting circuit), and the processing unit can be a processing circuit. In the embodiments of this application, the device in FIG7 can be the receiving end device or transmitting end device in the foregoing embodiments, or it can be a chip or a chip system, such as a system on chip (SoC). The communication unit can be an input / output circuit or a communication interface; the processing unit is a processor, microprocessor, or integrated circuit integrated on the chip. No limitation is made here.

[0240] Figure 8 is a schematic block diagram of a communication device 800 provided in an embodiment of this application. The device 800 includes a processor 810 and a transceiver 820. The processor 810 and the transceiver 820 communicate with each other through an internal connection path. The processor 810 is used to execute instructions to control the transceiver 820 to send and / or receive signals.

[0241] Optionally, the device 800 may further include a memory 830, which communicates with the processor 810 and the transceiver 820 via an internal connection path. The memory 830 stores instructions, and the processor 810 can execute the instructions stored in the memory 830. In one possible implementation, the device 800 is used to implement the various processes and steps corresponding to the transmitting device in the above method embodiments. In another possible implementation, the device 800 is used to implement the various processes and steps corresponding to the receiving device in the above method embodiments.

[0242] Optionally, the memory 830 can be integrated into the processor 810.

[0243] In one possible scenario, device 800 includes at least one processor with integrated memory, and other memory besides the memory integrated on the processor.

[0244] It is understood that the device 800 can specifically be the transmitting or receiving device in the above embodiments, or it can be a chip or a chip system. Correspondingly, the transceiver 820 can be the transceiver circuit of the chip, which is not limited here. Specifically, the device 800 can be used to execute the various steps and / or processes corresponding to the transmitting or receiving device in the above method embodiments.

[0245] Optionally, the memory 830 may include read-only memory and random access memory, and provide instructions and data to the processor. The memory may include non-volatile random access memory. For example, the memory may also store device type information. The processor 810 may be used to execute instructions stored in the memory, and when the processor 810 executes instructions stored in the memory, the processor 810 is used to perform the various steps and / or processes of the method embodiments corresponding to the transmitting or receiving devices described above.

[0246] In implementation, each step of the above method can be completed by integrated logic circuits in the processor's hardware or by instructions in software. The steps of the method disclosed in the embodiments of this application can be directly implemented by a hardware processor, or by a combination of hardware and software modules in the processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory, and the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method. To avoid repetition, detailed descriptions are omitted here.

[0247] It should be noted that the processor in the embodiments of this application can be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method embodiments can be completed by the integrated logic circuitry in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, digital signal processing (DSP), ASIC, field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The processor in the embodiments of this application can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied as being executed by a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can be located in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory, and the processor reads the information in the memory and, in conjunction with its hardware, completes the steps of the above methods.

[0248] It is understood that the memory in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM). It should be noted that the memory used in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0249] Optionally, the memory (e.g., 1130) in this embodiment may be integrated into the processor (e.g., 1110).

[0250] In addition, this application also provides a computer-readable storage medium storing computer instructions, which, when executed on a computer, cause the operations and / or processes performed by the sending or receiving device in the various method embodiments of this application to be executed.

[0251] This application also provides a computer program product, which includes computer program code or instructions. When the computer program code or instructions are run on a computer, the operations and / or processes performed by the sending end device or the receiving end device in the various method embodiments of this application are executed.

[0252] Furthermore, this application also provides a chip including a processor. A memory for storing a computer program is provided independently of the chip, and the processor is used to execute the computer program stored in the memory, such that operations and / or processes performed by a transmitting or receiving device in any method embodiment are performed.

[0253] Furthermore, the chip may also include a communication interface. The communication interface may be an input / output interface or an interface circuit, etc. Furthermore, the chip may also include a memory.

[0254] In addition, this application also provides a communication system, including the transmitting end device and the receiving end device in the embodiments of this application.

[0255] It should also be noted that the memory described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0256] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for example, the division of units is merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual coupling or direct coupling or communication connection may be through some interfaces; the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs. Furthermore, the functional units in the various embodiments of this application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0257] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, ROM, RAM, magnetic disks, or optical disks.

[0258] It is understood that the term "embodiment" used throughout the specification means that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this application. Therefore, various embodiments throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments.

[0259] It can also be understood that in this application, "when," "if," and "if" all refer to the network element making corresponding processing under certain objective circumstances, and are not time-limited, nor do they require the network element to make a judgment when it is implemented, nor do they mean that there are other limitations.

[0260] It can also be understood that in the various embodiments of this application, "B corresponding to A" means that B is associated with A, and B can be determined based on A. However, it can also be understood that determining B based on A does not mean that B is determined solely based on A; B can also be determined based on A and / or other information.

Claims

1. A communication method based on low-density parity-check (LDPC) codes, characterized in that, The method includes: Obtain the information bit sequence; The LDPC parity check matrix is ​​determined based on the LDPC base matrix. The base matrix includes at least two regions, where any two regions do not overlap, and the translation values ​​corresponding to any two regions are obtained in different ways. The information bit sequence is encoded according to the LDPC parity check matrix to obtain a codeword sequence; Output the codeword sequence.

2. A communication method based on low-density parity-check (LDPC) codes, characterized in that, The method includes: Obtain the codeword sequence; The LDPC parity check matrix is ​​determined based on the LDPC base matrix. The base matrix includes at least two regions, where any two regions do not overlap, and the translation values ​​corresponding to any two regions are obtained in different ways. The codeword sequence is decoded according to the LDPC parity check matrix to obtain the information bit sequence.

3. The method according to claim 1 or 2, characterized in that, The translation value corresponding to one of the at least two regions is determined in one of the following ways: Method 1: or, or, Method 2: SV i,j =P i,j *Zc / Z max Or, SV i,j =P i,j *Zc / Z max +w; Method 3: or, or, Method 4: SV i,j =P i,j Or, SV i,j =P i,j +w; Method 5: SV i,j =mod(P i,j ,Zc), or SV i,j =mod(P i,j +w,Zc), Wherein, the SV i,j P is the element at row i and column j in the base matrix. i,j The predefined translation values ​​of the base matrix are the predefined translation values ​​corresponding to the 1 element in the region, where w is a preset fixed value, Zc is the lift value corresponding to the base matrix, and P... i,j It is determined based on Zc, where Z is... max Zc is the largest boost value in the predefined boost value set.

4. The method according to claim 3, characterized in that, The translation value corresponding to the element 1 in another region of the at least two regions is determined by any of the remaining methods from methods 1 to 5, excluding the method for determining the translation value corresponding to the first region.

5. The method according to claim 1 or 2, characterized in that, At least one lift value corresponding to one of the at least two regions satisfies the first condition, and the translation value corresponding to the at least one lift value is determined in one of the following ways: Method 1: or, or, Method 2: SV i,j =P i,j *Zc / Z max Or, SV i,j =P i,j *Zc / Z max +w; Method 3: or, or, Method 4: SV i,j =P i,j Or, SV i,j =P i,j +w; Method 5: SV i,j =mod(P i,j ,Zc), or SV i,j =mod(P i,j +w,Zc), Wherein, the SV i,j P is the element at row i and column j in the base matrix. i,j The predefined translation values ​​of the base matrix are the predefined translation values ​​corresponding to the 1 element in the region, where w is a preset fixed value, Zc is the lift value corresponding to the base matrix, and P... i,h It is determined based on Zc, where Z is... max The first condition is the largest boost value in the predefined boost value set to which Zc belongs, and is related to the threshold of the predefined boost value set to which Zc belongs.

6. The method according to claim 5, characterized in that, The method for determining the translation value corresponding to the element 1 in another region of the at least two regions and the method for determining the translation value corresponding to the lift value in one region that does not meet the first condition are any of the remaining methods from methods 1 to 5, except for the method for determining the translation value corresponding to the at least one lift value.

7. The method according to any one of claims 3 to 6, characterized in that, When a region overlaps with an extended region in the base matrix, the overlapping portion is divided into a first part, a second part, and a third part. The number of edges corresponding to each row in the first part, the number of edges corresponding to each row in the second part, and the number of edges corresponding to each row in the third part are all different. Wherein, the row number corresponding to the first part is less than the first threshold, the row number corresponding to the second part is greater than or equal to the first threshold and less than the second threshold, and the row number corresponding to the third part is greater than or equal to the second threshold and less than or equal to the third threshold.

8. The method according to claim 7, characterized in that, The first threshold corresponds to a code rate of 1 / 2, the second threshold corresponds to a code rate of 1 / 3, and the third threshold corresponds to a code rate of 2 / 3.

9. The method according to any one of claims 3 to 8, characterized in that, exist In the case that each boost value in the predefined boost value group satisfies Where a is a positive integer, x0≥2 and is a preset constant, the value of a is different for each group of boost values, and k is from 0 to k max All integers, or k is from 1 to k max All integers, or k is from 2 to k max All integers.

10. The method according to claim 9, characterized in that, The x0 corresponding to each group of boost values ​​is equal.

11. The method according to any one of claims 9 to 10, characterized in that, The P i,j satisfy:

12. The method according to any one of claims 3 to 8, characterized in that, exist In the case where each boost value in the predefined boost value group satisfies a×2 k or Alternatively, the predefined promotion group does not include the one being promoted. The group of promotion values ​​corresponding to divisible 'a'. Where a is a positive integer, x0≥2 and is a preset constant, the value of a is different for each group of boost values, and k is from 0 to k max All integers, or k is from 1 to k max All integers, or k is from 2 to k max All integers.

13. The method according to claim 12, characterized in that, The P i,j Satisfy: mod(P) i,j a×2 k ) = 0, Or the P mentioned above i,j Can be Divisible by.

14. The method according to any one of claims 9 to 13, characterized in that, The k max It is to satisfy The largest positive integer.

15. The method according to claim 14, characterized in that, The Z max The possible values ​​are: 384, 256, 512, 1024, or 768.

16. The method according to any one of claims 3 to 8, characterized in that, The boost values ​​in the predefined boost value group containing Zc satisfy the following... The P i,j ,satisfy Wherein, k0 is a positive integer, and x is a positive integer.

17. The method according to claim 16, characterized in that, The k0 = x or the k0 = x-1.

18. The method according to claim 17, characterized in that, x = 2, or k0 = 1, 2 or 3.

19. The method according to any one of claims 3 to 18, characterized in that, The region includes at least one column of the check columns in the base matrix, or, The region includes at least one column of the core check column in the base matrix, or, The region includes the columns corresponding to odd numbers in the core verification column whose column weight is greater than 1.

20. The method according to claim 19, characterized in that, The region includes the basis matrix H BG1 The corresponding kb+1th column, and rows 1 to 4; or, The region includes the H BG1 The corresponding columns kb+1 to kb+4, and rows 1 to 4; or, The region includes the H BG1 The corresponding kb+1th column, and rows 1, 2, and 4; or, The region includes the H BG1 The corresponding columns kb+1 to kb+4, and rows 1, 2, and 4. Wherein, kb is the number of information columns.

21. A communication device, characterized in that, The device includes at least one processor and an interface circuit, the interface circuit being configured to receive signals from other communication devices besides the communication device and transmit them to the processor, or to send signals from the processor to other communication devices besides the communication device, the processor causing the method as described in any one of claims 1 to 20 to be implemented via logic circuits or executing code instructions.

22. The communication device according to claim 21, characterized in that, The communication device is a chip or chip system.

23. A computer-readable storage medium, characterized in that, The storage medium stores a computer program or instructions that, when executed, cause the method as described in any one of claims 1 to 20 to be implemented.

24. A computer program product, characterized in that, Includes a computer program that, when run, causes the method as described in any one of claims 1 to 20 to be implemented.

25. A communication device, characterized in that, Includes a module for performing the method as described in any one of claims 1 to 20.

26. A communication device, characterized in that, It includes at least one processor for executing a computer program or instructions stored in a memory, causing the communication device to perform the method as described in any one of claims 1 to 20.

27. The communication device according to claim 26, characterized in that, It also includes the memory.

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