Model verification device, model verification method, and program

By converting temporal logic formulas into MILP-based constraint information and using variable-length time intervals, the model checking device efficiently verifies complex systems, reducing computational burden and enhancing the synthesis of example signals.

WO2026014187A1PCT designated stage Publication Date: 2026-01-15INTER UNIV RES INST RES ORG OF INFORMATION & SYST
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Patent Information

Application Number
PCT/JP2025/022119
Authority / Receiving Office
WO · WO
Patent Type
Applications
Current Assignee / Owner
Priority Date
2024-07-10
Filing Date
2025-06-19
Publication Date
2026-01-15

AI Technical Summary

Technical Problem

Conventional model checking techniques require a significant amount of computation for verifying temporal logic formulas, particularly in trace synthesis, which is inefficient for complex systems.

Method used

The model checking device converts temporal logic formulas into constraint information using mixed integer linear programming (MILP) and performs verification based on variable-length time intervals, employing auxiliary variables to distinguish between open and closed intervals, thereby reducing computational complexity.

Benefits of technology

This approach allows for the verification of temporal logic formulas with a smaller computational effort, enabling efficient model checking and rapid synthesis of example signals that satisfy the formal specifications.

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Abstract

This model verification device comprises: an acquisition unit that acquires a state transition model and a temporal logic formula; a conversion unit that converts the temporal logic formula into constraint information encoded with variable-length time intervals on the basis of a mixed integer linear programming method; and a result output unit that outputs information indicating whether the state transition model satisfies the temporal logic formula on the basis of the state transition model and the constraint information.
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Citation Information

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