Model verification device, model verification method, and program
By converting temporal logic formulas into MILP-based constraint information and using variable-length time intervals, the model checking device efficiently verifies complex systems, reducing computational burden and enhancing the synthesis of example signals.
Patent Information
- Application Number
- PCT/JP2025/022119
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2024-07-10
- Filing Date
- 2025-06-19
- Publication Date
- 2026-01-15
AI Technical Summary
Conventional model checking techniques require a significant amount of computation for verifying temporal logic formulas, particularly in trace synthesis, which is inefficient for complex systems.
The model checking device converts temporal logic formulas into constraint information using mixed integer linear programming (MILP) and performs verification based on variable-length time intervals, employing auxiliary variables to distinguish between open and closed intervals, thereby reducing computational complexity.
This approach allows for the verification of temporal logic formulas with a smaller computational effort, enabling efficient model checking and rapid synthesis of example signals that satisfy the formal specifications.
Smart Images

Figure JP2025022119_15012026_PF_FP_ABST
Abstract
Citation Information
Patent Citations
Monitoring device and monitoring method
WO2022138778A1