Radio frequency integrated circuits using extended drain mosfets

Abstract

Circuits and methods for high-quality amplifiers (e.g., low-noise amplifiers and power amplifiers) that are sensitive, provide good amplification, are physically compact, and can withstand relatively high drain-to-source voltages. Some embodiments include a thin gate oxide N-type MOSFET device or N-type Extended Drain MOSFET (NEDMOS) device co-fabricated with one or more serially-coupled thick gate oxide P-type Extended Drain MOSFET (PEDMOS) devices of several types. Some embodiments include one or more multi-gate NEDMOS devices. Embodiments includes PEDMOS devices having at least source and drain regions that include germanium (e.g., as a heterogeneous or homogenous SiGe alloy, including Ge-doped Si and graded Ge and Si mixtures), particularly PEDMOS devices having a strained channel region. A significant benefit of the inventive IC structures and variants is the space savings in IC layouts resulting from the use of shared regions between adjacent devices, particularly when concatenating multiple PEDMOS and NEDMOS devices and sharing drain / source regions.

Description

RADIO FREQUENCY INTEGRATED CIRCUITS USING EXTENDED DRAIN MOSFETSCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] The present application claims priority to the following provisional patent application, assigned to the assignee of the present invention, the contents of which are incorporated by reference in their entirety: U.S. Provisional Patent Application Serial No. 63 / 670,489, filed July 12, 2024, entitled “Radio Frequency Integrated Circuits Using Extended Drain MOSFETS" .

[0002] The present application is also a continuation-in-part to the following patent application, assigned to the assignee of the present invention, the contents of which are incorporated by reference in their entirety: U.S. Patent Application Serial No. 18 / 420,465, filed January 23, 2024, entitled “PEDMOS Transistor Devices" .TECHNICAL FIELD

[0003] The invention relates to electronic circuits, and more particularly to amplifier circuits.BACKGROUND

[0004] Many modern electronic systems include radio frequency (RF) receivers; examples include cellular telephones, personal computers, tablet computers, wireless network components, televisions, cable system “set top” boxes, and radar systems. Many RF receivers are paired with RF transmitters in the form of transceivers, which often are quite complex two-way radios. In some cases, RF transceivers are capable of transmitting and receiving across multiple frequencies in multiple bands.

[0005] Amplifiers are a common component in RF transmitters, receivers, and transceivers, and are frequently used for power amplification of transmitted RF signals and for low-noise amplification of received RF signals. For many RF systems, particularly those requiring low power and / or portability (e.g., cellular telephones, WiFi-connected computers, cameras, and other devices), it has become common to use metal-oxide semiconductor field-effect transistors (MOSFETs) to create low-cost, low-power integrated circuits (ICs). MOSFET devices includebulk MOSFETs, silicon-on-insulator (SOI) MOSFETs, and silicon-on-sapphire (SOS) MOSFETs (SOS being a type of SOI fabrication technology).

[0006] In many environments, receiving an RF signal requires a high-quality low-noise amplifier (LN A) as part of an RF “front end” (RFFE) receiver or transceiver chain of circuits. It is desirable that an LNA be sensitive, provide suitable amplification, be physically compact, and in many applications be able to withstand relatively high drain-to-source voltages. The present invention is directed to novel embodiments of amplifiers that meet these and other criteria.SUMMARY

[0007] The present invention encompasses circuits and methods for high-quality amplifiers (e.g., low-noise amplifiers (LNA) and power amplifiers (PA)) that are sensitive, provide good amplification, are physically compact, and can withstand relatively high drain-to-source voltages. Some embodiments include a thin gate oxide N-type MOSFET (NFET) device or N-type Extended Drain MOSFET (NEDMOS) device co-fabricated with one or more serially-coupled thick gate oxide P-type Extended Drain MOSFET (PEDMOS) devices of several types. Some embodiments include one or more multi -gate NEDMOS devices.

[0008] A significant benefit of the IC structures described above, and variations of such structures, is the space savings in IC layouts resulting from the use of shared regions between adjacent devices, particularly when concatenating multiple PEDMOS and NEDMOS devices and sharing drain / source regions.

[0009] A first embodiment comprises an integrated circuit including an N-type MOSFET having a source, a body laterally adjacent the source, a gate structure positioned with respect to the body so as to be able to influence current flow through the body, and a drain laterally adjacent the body; and a P-type extended drain MOSFET having a source, a body laterally adjacent the source, a gate structure positioned with respect to the body so as to be able to influence current flow through the body, a drift region laterally adjacent the body, and a drain laterally adjacent the drift region; wherein the drain of the N-type MOSFET and the drain of the P-type extended drain MOSFET are shared regions within the integrated circuit having a common electrical contact.

[0010] A second embodiment comprises an integrated circuit including an N-type MOSFET having a source, a body laterally adjacent the source, a gate structure positioned with respect to the body so as to be able to influence current flow through the body, a drift region laterally adjacent the body, and a drain laterally adjacent the drift region; and a P-type extended drain MOSFET having a source, a body laterally adjacent the source, a gate structure positioned with respect to the body so as to be able to influence current flow through the body, a drift region laterally adjacent the body, and a drain laterally adjacent the drift region; wherein the drain of the N-type MOSFET and the drain of the P-type extended drain MOSFET are shared regions within the integrated circuit having a common electrical contact.

[0011] A third embodiment comprises an integrated circuit including an N-type MOSFET having a source, a body laterally adjacent the source, a gate structure positioned with respect to the body so as to be able to influence current flow through the body, and a drain laterally adjacent the body; and an N-type extended drain MOSFET having a source, a body laterally adjacent the source, a gate structure positioned with respect to the body so as to be able to influence current flow through the body, a drift region laterally adjacent the body, and a drain laterally adjacent the drift region; wherein the drain of the N-type MOSFET and the source of the N-type extended drain MOSFET are shared regions within the integrated circuit.

[0012] The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention should be apparent from the description and drawings, and from the claims.DESCRIPTION OF THE DRAWINGS

[0013] FIG. 1 is a simplified schematic diagram of a first amplifier circuit.

[0014] FIG. 2 is a simplified schematic diagram of a second amplifier circuit.

[0015] FIG. 3 is a stylized cross-sectional view of a first SOI IC structure of an amplifier core including an NFET device co-fabricated with one PEDMOS device of a set of one or more PEDMOS devices.

[0016] FIG. 4 is a stylized cross-sectional view of a second SOI IC structure of an amplifier core including an NFET device co-fabricated with one PEDMOS device of a set of one or more PEDMOS devices.

[0017] FIG. 5 is a stylized cross-sectional view of a third SOI IC structure of an amplifier core including an NFET device co-fabricated with one PEDMOS device of a set of one or more PEDMOS devices.

[0018] FIG. 6 is a stylized cross-sectional view of a fourth SOI IC structure of an amplifier core including an N-type device (e.g., an NFET or NEDMOS device) co-fabricated with one PEDMOS device of a set of one or more PEDMOS devices.

[0019] FIG. 7A is a stylized cross-sectional view of an SOI IC structure for a first PEDMOS FET that includes SiGe regions.

[0020] FIG. 7B is a stylized cross-sectional view showing only the BOX layer and active layer of a variant of the PEDMOS FET of FIG. 7A.

[0021] FIG. 7C is a stylized cross-sectional view of an SOI IC structure for a second PEDMOS FET that includes SiGe regions.

[0022] FIG. 7D is a stylized cross-sectional view showing only the BOX layer and active layer of a variant of the PEDMOS FET of FIG. 7C.

[0023] FIG. 7E is a stylized cross-sectional view of an SOI IC structure for a third PEDMOS FET that includes SiGe regions.

[0024] FIG. 7F is a stylized cross-sectional view showing only the BOX layer and active layer of a variant of the PEDMOS FET of FIG. 7E.

[0025] FIGS. 8A-8H are cross-sectional stylized views of example fabrication stages for the novel PEDMOS FET of FIG. 7A, where the active layer (by way of example only) is Si having a <110> orientation.

[0026] FIGS. 9A-9B are cross-sectional stylized views of a first set of alternative fabrication stages for a PEDMOS FET that includes SiGe regions.

[0027] FIGS. 10A-10B are cross-sectional stylized views of a second set of alternative fabrication stages for a PEDMOS FET that includes SiGe regions.

[0028] FIGS. 11A-11C are cross-sectional stylized views of a third set of alternative fabrication stages for a PEDMOS FET that includes SiGe regions.

[0029] FIG. 12 is a cross-sectional stylized view of an alternative PEDMOS FET that includes SiGe regions and a stepped insulating GOX layer.

[0030] FIG. 13 is a process flowchart showing one process that is suitable for some contemporary IC front-end-of-line (FEOL) foundries.

[0031] FIG. 14 is a stylized cross-sectional view of a fifth SOI IC structure of an amplifier core including an NFET and two co-fabricated and concatenated NEDMOS devices of a set of one or more NEDMOS devices.

[0032] FIG. 15 is a top plan view of a first configuration of BTS structures for multiple PEDMOS devices co-fabricated with an NFET.

[0033] FIG. 16 is a top plan view of a second configuration of BTS structures for multiple PEDMOS devices co-fabricated with an NFET.

[0034] FIG. 17 is a top plan view of a third configuration of BTS structures for multiple PEDMOS devices co-fabricated with an NFET.

[0035] FIG. 18 is a top plan view of a configuration of multiple PEDMOS devices lacking BTS structures and co-fabricated with an NFET.

[0036] FIG. 19 is a top plan view of a substrate that may be, for example, a printed circuit board or chip module substrate (e.g., a thin-film tile).

[0037] FIG. 20 illustrates a prior art wireless communication environment comprising different wireless communication systems, and which may include one or more mobile wireless devices.

[0038] FIG. 21 is a block diagram of a transceiver that might be used in a wireless device, such as a cellular telephone, and which may beneficially incorporate an embodiment of the present invention for improved performance.

[0039] Like reference numbers and designations in the various drawings indicate like elements unless the context requires otherwise.- 1 -DETAILED DESCRIPTION

[0040] The present invention encompasses circuits and methods for high-quality amplifiers (e g., low-noise amplifiers (LNA) and power amplifiers (PA)) that are sensitive, provide good amplification, are physically compact, and can withstand relatively high drain-to-source voltages. Some amplifier embodiments include a thin gate oxide N-type MOSFET (NFET) device or N-type Extended Drain MOSFET (NEDMOS) device co-fabricated with one or more serially-coupled thick gate oxide P-type Extended Drain MOSFET (PEDMOS) devices of several types. Some amplifier embodiments include one or more multi-gate NEDMOS devices.

[0041] FIG. 1 is a simplified schematic diagram of a first amplifier circuit 100. In the illustrated example, the amplifier circuit 100 includes an amplifier core 102 comprising a stack of two series-connected FETs: a common-source NFET Mcs and a common-gate PEDMOS device MCG coupled in a cascode arrangement. An optional PEDMOS device stack 104 may be coupled to the source of the PEDMOS device MCG to handle higher voltages. An RF input signal applied to an RF input terminal RFIN is coupled through an impedance matching inductor LIN and respective DC blocking capacitors Ccs, CCG to the control gate of the common-source NFET Mcs (which may be regarded as an input port INT of the amplification core 102) and to the control gate of the common-gate PEDMOS device MCG.

[0042] The source of the common-source NFET Mcs may be regarded as a degeneration port DT of the amplification core 102. A degeneration inductor LDG is coupled between the degeneration port DT of the amplification core 102 and a reference potential, such as circuit ground.

[0043] The drain of the common-gate PEDMOS device MCG is connected to the drain of the common-source FET Mcs. The source of the common-gate PEDMOS device MCG provides an amplified RF output signal (directly or through the optional PEDMOS stack 104) at what may be regarded as an amplified-signal port AST of the amplification core 102. A bias generator circuit (not shown) may be included to provide a suitable bias voltage CG VBIAS to the common-gate PEDMOS device MCG through a resistor RCG and a suitable bias voltage CS_VBIAS to the commonsource NFET Mcs through a resistor Res. In some embodiments, the common-source NFET Mcs may be replaced by a NEDMOS device.

[0044] In the illustrated example, the amplified-signal port AST is coupled to a voltage source terminal VDD through a load module 106. In the illustrated example, the load module 106 includes a load inductor LLD coupled in parallel with a de-queuing resistor RDQ. The amplified-signal port AST is also coupled to an RF output terminal RFOUT through a DC-blocking output capacitor Cour. The RF output terminal RFOUT would typically be coupled to a 50-ohm load for many modern RF circuits.

[0045] FIG. 2 is a simplified schematic diagram of a second amplifier circuit 200. Similar in many aspects to the amplifier circuit 100 of FIG. 1, the amplifier circuit 200 has a different configuration for the amplifier core 102. The amplifier core 102 for the amplifier circuit 200 comprises a stack of two series-connected FETs: a common-source NFET Mcs and a commongate NEDMOS device MCG coupled in a cascode arrangement. An optional NEDMOS device stack 105 may be coupled to the drain of the NEDMOS device MCG to handle higher voltages. The source of the common-gate NEDMOS device MCG is connected to the drain of the common-source FET Mcs. The drain of the common-gate NEDMOS device MCG provides an amplified RF output signal (directly or through the optional NEDMOS stack 105) at the amplified-signal port AST of the amplification core 102. A further difference is that capacitor CCG is coupled to a reference potential (e. ., circuit ground) rather than to a terminal of the matching inductor LIN.

[0046] In preferred embodiments of the amplifiers 100, 200, the common-source NFET Mcs would be fabricated as a thin-gate oxide device to provide high performance, while the commongate devices MCG (including the devices in the optional PEDMOS stack 104 or NEDMOS stack 105) may be fabricated as thick-gate oxide devices to withstand higher voltages.

[0047] An important aspect of the present invention is the implementation of the amplifiers 100, 200 in compact and efficient integrated circuits (ICs) capable of withstanding relatively high drain-to-source voltages. FIG. 3 is a stylized cross-sectional view of a first SOI IC structure 300 of an amplifier core including an NFET device 302 co-fabricated with one PEDMOS device 304 of a set of one or more PEDMOS devices. The IC structure 300 implements a first version of the amplifier core 102 shown in FIG. 1.

[0048] The SOI structure includes a substrate 306, a buried-oxide (BOX) insulator layer 308, and an active layer 310 (note that the dimensions for the elements of the SOI IC structure are notto scale; some dimensions have been exaggerated for clarity or emphasis). The substrate 306 is typically a semiconductor material such as silicon, but other materials may be used. The BOX layer 308 is a dielectric, and is often SiO2 formed as a “top” surface of the silicon substrate 306. For some insulating substrates (e.g., glass or sapphire), a BOX layer 308 may be omitted, since such a substrate provides the function of the BOX layer without a silicon handle wafer. Some embodiments may include a trap-rich layer (not shown) between the BOX layer 308 and the substrate 306. A trap-rich layer mitigates parasitic surface conduction and improves device performance at high frequencies.

[0049] The BOX layer 308 and the active layer 310 (which may include multiple FET devices) may be collectively referred to as a “device region” or “substructure” for convenience (noting that other structures or regions may intrude into the substructure in particular IC designs). The active layer 310 may include some combination of implants and / or layers that include dopants, dielectrics, polysilicon, conductors, passivation, and other materials to form active and / or passive electronic components and / or mechanical structures. A superstructure (not shown) of various elements, regions, and structures may be fabricated on or above the substructure in order to implement particular functionality. The superstructure may include, for example, conductive interconnections from one or more FET devices to other components (including other FET devices) and / or external contacts, passivation layers, and protective coatings.

[0050] The NFET 302 includes an N+ source SN, a P-type body BN, a gate structure GN, and an N+ drain DN. The designation “N- means a lesser concentration of N-type dopant (e.g., arsenic or phosphorous) than the designation “N+”. A conductive source contact 322, a conductive gate contact 324, and a conductive drain contact 326, which may be self-aligned silicides (also known as “salicides”), are respectively formed in contact with the source SN, the gate structure GN, and the drain DN. The salicides may be, for example, NiSi. Stylized electrical terminals SourceN, GateN, and shared DrainNP are shown coupled to the corresponding source contact 322, gate contact 324, and drain contact 326.

[0051] The illustrated gate structure GN of the NFET 302 includes a conductive layer 330, such as N+ doped polysilicon, atop an insulating gate oxide (GOX) layer 332. In the illustrated example, the gate structure GN is surrounded by insulating spacers 334. Parts of the gate structure GN andthe drain DN may be coated with a dielectric, such as SiCh, SisN4, etc., which in turn may be overlaid with a salicide block (SAB) layer, such as silicon nitride (SiN); for an example, see the description below with respect to the PEDMOS device 304.

[0052] In some embodiments of the NFET 302, a lightly-doped drain (LDD) region 336 may be formed underneath one or both of the spacers 334. In some embodiments, a doped halo region 338 may be formed between portions of the source SN and the body BN and / or between portions of the drain DN and the body Bp. A halo implant mitigates punch-through while an LDD region mitigates avalanche breakdown. More specifically, the halo region 338 increases a sub-surface electric field to reduce so-called punch-through, or short channel, conduction between the source SN and the drain DN, thus increasing the channel breakdown voltage. The LDD region 336 extends the source SN underneath the gate structure GN and modulates the threshold voltage VTH, transconductance Gm, and leakage current of the device.

[0053] The PFET 304 includes a P+ source Sp, a N-type body BN, a gate structure Gp, and a P+ drain Dp. Interposed between the body BN and the drain Dp is a P- drift region DRp to provide an improved ability to withstand relative high drain-to-source voltages. A conductive source contact 342, a conductive gate contact 344, and a conductive drain contact 346, which may be selfaligned silicides (also known as “salicides”), are respectively formed in contact with the source SP, the gate structure Gp, and the drain Dp. The salicides may be, for example, NiSi. Stylized electrical terminals Source?, Gatep, and shared Drainxp are shown coupled to the corresponding source contact 342, gate contact 344, and drain contact 346. Note that the drain contact 346 of the PFET 304 and the drain contact 326 of the NFET 302 may be formed as a unitary shared structure.

[0054] In some embodiments of the PFET 304, an LDD region 356 may be formed underneath the source-side spacer 354. In some embodiments, a doped halo region 358 may be formed between portions of the source Sp and the body BN.

[0055] The illustrated gate structure Gp includes a conductive layer 350, such as P+ doped poly silicon, atop an insulating gate oxide (GOX) layer 352. In the illustrated example, the gate structure Gp is surrounded by insulating spacers 354. Parts of the gate structure Gp and the drain Dp may be coated with a dielectric 360, such as SiCh, SisN4, etc., which in turn may be overlaid with a salicide block (SAB) layer 362, such as silicon nitride (SiN).- l i

[0056] The example embodiment of FIG. 3 shows that the GOX layer 352 in the PEDMOS gate structure Gp is thicker than the GOX layer 332 in the NEDMOS gate structure GN. In general, gate oxide thickness is a function of gate length, so “thin” and “thick” with respect to the gate oxide will depend on the gate length of a particular FET design. The thicker GOX layer 352 in the PEDMOS gate structure Gp reduces the electric-field at the interface of the gate and the drain region and improves both GIDL (gate-induced drain leakage) and TDDB (Time-Dependent Dielectric Breakdown) compared to a PEDMOS device having a thinner GOX layer. The thinner GOX layer 332 in the NEDMOS gate structure GN provides for higher performance. As should be clear, other dimensions for the thick GOX layer 352 and the thin GOX layer 332 may be used as a matter of design choice.

[0057] FIG. 4 is a stylized cross-sectional view of a second SOI IC structure 400 of an amplifier core including an NFET device co-fabricated with one PEDMOS device of a set of one or more PEDMOS devices. The IC structure 400 implements a second version of the amplifier core 102 shown in FIG. 1.

[0058] FIG. 4 includes a NEDMOS device 402 that may be used as an alternative to the NFET 302 of FIG. 3. Thus, the NEDMOS device 402 would be co-fabricated with at least one PEDMOS device 304, as in FIG. 3 (the PEDMOS device 304 in FIG. 4 is represented by a dotted-line block). The NEDMOS device 402 is similar in many aspects to the NFET 302 of FIG. 3, and accordingly similarly structures and regions use the same reference numbers in both figures. Differences include (1) an N- drift region DRN interposed between the body Bp and the drain DN to provide an improved ability to withstand relative high drain-to-source voltages, (2) the omission of a drainside LDD region 336 and a drain-side halo region 338, and (3) parts of the gate structure GN and the drain DN may be coated with a dielectric 460, such as SiO2, SisN4, etc., which in turn may be overlaid with a SAB layer 462, such as SiN.

[0059] FIG. 5 is a stylized cross-sectional view of a third SOI IC structure 500 of an amplifier core including an NFET device 302 co-fabricated with one PEDMOS device 304 of a set of one or more PEDMOS devices. The IC structure 500 implements a third version of the amplifier core 102 shown in FIG. 1.

[0060] The amplifier core of FIG. 5 is similar in many aspects to the amplifier core of FIG. 3, and accordingly similarly structures and regions use the same reference numbers in both figures. Differences include (1) the omission of a drain-side LDD region 336 in the NFET 302, resulting in an asymmetrical configuration for NFET 302, and (2) use of a stepped configuration for the GOX layer 352 in the PEDMOS device 304. The stepped GOX layer 352 includes a thin (in the Z dimension) subregion adjacent the source-side of the gate structure Gp and a thick subregion adjacent the drain-side of the gate structure Gp. The thin and thick subregions of the stepped GOX layer 352 will exhibit different threshold voltage (VTH) characteristics. The thin GOX subregion creates a higher potential barrier when negative gate voltages are applied compared to a PEDMOS having only a thick GOX, resulting in a substantial improvement (-25% in some embodiments) in the drain-to-source breakdown voltage VBD of the device. The thicker GOX subregion at the drainside of the gate structure Gp reduces the electric-field at the interface of the gate and the drain region and improves both GIDL and TDDB compared to a PEDMOS device having only a thin GOX layer. Note that the “thin” region of the GOX layer 352 may still be thicker than the GOX layer 332 of the NFET 302.

[0061] In variations of the third SOI IC structure 500 shown in FIG. 5, the NFET 302 may be identical to the NFET 302 of FIG. 3 ( / .<?., including the drain-side LDD region 336), or may be replaced by the NEDMOS device 402 shown in FIG. 4.

[0062] In some embodiments of the PFET 304, the P- drift region DRp may be segmented into two or more subregions, each pair of subregions spaced by an intervening P-type well regions overlayed by a gate structure. For example, FIG. 6 is a stylized cross-sectional view of a fourth SOI IC structure 600 of an amplifier core including an N-type device 602 (e.g., an NFET 302 or NEDMOS device 402, represented in FIG. 6 by a dotted-line block) co-fabricated with one PEDMOS device 604 of a set of one or more PEDMOS devices. The IC structure 600 implements a fourth version of the amplifier core 102 shown in FIG. 1.

[0063] Similar in many respects to the PEDMOS device 304 of FIG. 3, the illustrated PEDMOS device 604 differs by including a secondary gate structure GDR overlying a lightly-doped P-well region 610 adjacent at least one of a first or second P- drift region DRlp, DR2p. In the illustrated example, the P-well region 610 is doped to a lesser concentration of P-type materialthan the first or second P- drift regions DRlp, DR2p. In some embodiments, the second N- drift region DR2p may be omitted, in which case the P-well region 610 is located between and adjacent to the first P- drift region DRlp and the drain Dp. In any case, the combination of the secondary gate structure GDR and the P-well region 610 forms a secondary transistor.

[0064] The illustrated secondary gate structure GDR includes a conductive layer 612, such as P+ doped polysilicon, atop a secondary insulating gate oxide (G0X2) layer 614. In some embodiments, the GOX2 layer 614 may extend beyond the vertical edges of the P-well region 610, as shown. In some embodiments, the secondary GOX2 layer 614 may differ in thickness relative to the GOX layer 352 forming part of the primary gate structure Gp. In the illustrated example, the secondary gate structure GDR is surrounded by insulating spacers 616. Part of the secondary gate structure GDR is coated with a dielectric 618, such as SiCh, SislS , etc., which in turn is overlaid with an SAB layer, such as SiN, which may be co-extensive with the SAB layer 362 overlaying part of the primary gate structure Gp. A conductive contact 620, which may be a salicide, is formed in contact with the conductive layer 612 of the gate structure GDR. A stylized electrical terminal GBIAS is shown coupled to the conductive contact 620.

[0065] The electrical terminal GBIAS would generally be coupled to a voltage source within an overlying superstructure (not shown). In some embodiments, the GBIAS terminal may be coupled to the Gatep terminal of the primary gate structure Gp such that both terminals are biased by a common voltage source. In other embodiments, the voltage source for the GBIAS terminal may differ in value from the voltage source for the Gatep terminal.

[0066] Schematically, the first P- drift region DRlp may be represented as having an essentially fixed drain resistance Rdi, the P-well 610 may be represented as having a variable drain resistance Rd2, and the second P- drift region DR2p may be represented as having an essentially fixed drain resistance Rds. The total drain resistance Rd is thus equal to Rdi + Rd2 + Rds.

[0067] For the illustrated example embodiment, if a bias voltage GBIAS of 0V is applied to the GBIAS terminal, the secondary transistor is in an OFF state and the resistance Rd2 of the P-well 610 will have its highest value; accordingly, Rd will have its highest value. As a consequence, the device as a whole will have a high OFF state breakdown voltage. Conversely, if a negative bias voltage GBIAS greater in magnitude than the threshold voltage of the secondary transistor is appliedto the GBIAS terminal, the secondary transistor is in an ON state and the resistance Rdz of the P- well 610 will have a lower value; accordingly, Rd will have a lower value. A reduced total drain resistance Rd through the extended drift region improves the linearity and the error-vector magnitude (EVM) characteristics of the PEDMOS device 604.

[0068] For the IC structures shown in FIGS. 3-6, additional PEDMOS devices may be cofabricated and concatenated to the illustrated PEDMOS device within the IC structures to withstand even higher drain voltages.

[0069] As FET device dimensions are scaled down (e.g., a 45nm or smaller node fabrication node), the performance of PFETs comes closer to the performance of NFETs. For example, the m (transconductance) and / t (unity current gain cut-off frequency) of a PFET with a gate length LG of about 45nm are about 90% of an NFET. Applicant has realized that a PEDMOS device architecture having at least source and drain regions that include germanium (e.g., as a heterogeneous or homogenous SiGe alloy, including Ge-doped Si as well as graded Ge and Si mixtures), particularly PEDMOS device architectures having a strained channel region with a gate length LG of about 45nm or less, can achieve a hole mobility that approximately equals - and in many embodiments exceeds - the electron mobility of NFET and NEDMOS devices.

[0070] For the PEDMOS devices shown in FIGS. 3-6, performance may be improved by fabricating all or a portion of the source Sp, drift region DRp (or regions DRw), P-well 610, and / or drain Dp so as to include SiGe. The SiGe regions exert compression on the N-type Si channel (the body BN) of the device, thereby improving hole mobility within the PEDMOS device. In such embodiments, the active layer preferably is Si having a <110>, <100>, or <111> orientation. Resulting PEDMOS devices exhibit improved hole mobility, low leakage currents at active layer edges, low channel resistance, and GIDL characteristics. In addition, PEDMOS devices exhibit better hot-carrier injection characteristics compared to NFETs and NEDMOS devices since holes have a significantly lower impact ionization rate; consequently, the rate of hole injection into the gate oxide of a PEDMOS device will be significantly lower than with an NFET or NEDMOS device.

[0071] A further advantage of a PEDMOS device architecture is that it uses an N-type channel, and thus results in low leakage current at active layer edges (no dopant segregation to causeleakage) and a low channel resistance, which increases the BVON of the device. Low bipolar action of a PEDMOS device at its source also improves the BVON. Due to the presence of an extended drift region, a PEDMOS device also has a high junction breakdown BVDSS value.

[0072] FIG. 7A is a stylized cross-sectional view of an SOI IC structure for a first PEDMOS FET 700 that includes SiGe regions. The SOI structure includes a substrate 702, a buried-oxide (BOX) insulator layer 704, and an active layer 706 (note that the dimensions for the elements of the SOI IC structure are not to scale; some dimensions have been exaggerated for clarity or emphasis). The substrate 702 is typically a semiconductor material such as silicon, but may be other materials such as glass or sapphire. The BOX layer 704 is a dielectric and is often SiO2 formed as a “top” surface of the substrate 702; for some substrates (e.g., glass or sapphire), a BOX layer 704 may be omitted. Some embodiments may include a trap-rich Si layer (not shown) between the BOX layer 704 substrate 702.

[0073] The active layer 706 that includes a P+ source 710, an N-type body region or well 712 in which an electrically conductive channel can be formed, a first P- Si drift region 714, a second P- SiGe drift region 716, and a P+ drain 718, all bounded by an isolation structure 720, such as a shallow trench isolation (STI) structure. The designation “P- means a lesser concentration of P- type dopant (e.g., boron) than the designation “P+” Optional features within the active layer 706 include a halo region 722 and an LDD region 724 (“LDD” being somewhat of a misnomer, since the LDD region 724 is only on the source side of the illustrated embodiment).

[0074] The gate structure Gp is formed in contact with a surface of the active layer 706, between the source 710 and the drain 718. The gate structure Gp includes a conductive layer 708, such as P+ doped poly silicon, in contact with an insulating gate oxide (GOX) layer 710, the thickness of which may be varied for different applications. In the illustrated example, the gate structure Gp is surrounded by insulating spacers 718. Part of the gate structure Gp and the P- drift regions 714, 716 are coated with a dielectric 738 (e.g., SiCh or SisN4), which in turn is overlaid with a SAB layer 740 to prevent subsequent formation of silicide on those structures / regions.

[0075] A conductive source contact 742, a conductive gate contact 744, and a conductive drain contact 746, which may be salicides, are respectively formed in contact with the source 710, thegate structure Gp, and the drain 718. Stylized electrical terminals S, G, and D are shown coupled to the corresponding source contact 742, gate contact 744, and drain contact 746.

[0076] Importantly, the P+ source 710, the second P- drift region 716, and the P+ drain 718 all comprise Si and Ge in the form of a heterogeneous or homogenous SiGe alloy, including Ge- doped Si, graded Ge and Si mixtures, or the like. Hole mobility in Ge and SiGe generally is greater than hole mobility in Si alone, particularly when the active layer 706 has a <110> orientation. For example, in an active layer 706 of Si having a <110> orientation, Ge has about 4 to 5 times greater hole mobility than Si between 2 and 3 gigapascals (GPa), with various SiGe alloys having intermediate hole mobilities. However, increased hole mobility for Ge and SiGe also occurs in Si having a <100> or <111> orientation.

[0077] In FIG. 7A, the P+ source 710 and the P+ drain 718 are fabricated so that a portion of the SiGe extends into the source-side and drain-side edges of the channel region with a rounded shape resulting from use of a particular etchant (details below). The Si active layer 706 preferably has a <110> orientation, but may be Si having a <100> or <111> orientation. The introduction of Ge into Si increases the interatomic spacing within the crystal structure of the SiGe regions, thereby compressing the channel region of the device (within the N well 712). Such compression significantly improves hole mobility within the PEDMOS device.

[0078] FIG. 7B is a stylized cross-sectional view showing only the BOX layer 704 and active layer 706 of a variant of the PEDMOS FET 700 of FIG. 7A. In FIG. 7B, the P+ SiGe source 710, the second P- SiGe drift region 716, and the P+ SiGe drain 718 do not extend all the way down to the BOX layer 704 (the substrate 702, gate structure Gp, halo region 722, and LDD region 724 are omitted to reduce clutter).

[0079] FIG. 7C is a stylized cross-sectional view of an SOI IC structure for a second PEDMOS FET 750 that includes SiGe regions. Similar in most aspects to the first PEDMOS FET 700 of FIG. 7A, the P+ source 710, the second P- drift region 716, and the P+ drain 718 are fabricated so that a portion of the SiGe extends into the source-side and drain-side edges of the channel region with an angled or pointed shape resulting from use of a particular etchant (details below). The Si active layer 706 preferably has a <110> orientation, but may be Si having a <100> or <111> orientation. Again, the introduction of Ge into Si increases the interatomic spacing withing thecrystal structure of the SiGe regions, thereby compressing the channel region of the device to significantly improve hole mobility within the PEDMOS device.

[0080] FIG. 7D is a stylized cross-sectional view showing only the BOX layer 704 and active layer 706 of a variant of the PEDMOS FET 750 of FIG. 7C. In FIG. 7D, the P+ SiGe source 710, the second P- SiGe drift region 716, and the P+ SiGe drain 718 do not extend all the way down to the BOX layer 704.

[0081] FIG. 7E is a stylized cross-sectional view of an SOI IC structure for a third PEDMOS FET 760 that includes SiGe regions. Similar in most aspects to the first PEDMOS FET 700 of FIG. 7A, the P+ source 710 and the P+ drain 718 are fabricated so that the SiGe does not extend significantly into the channel region. Nevertheless, the introduction of Ge into Si increases the interatomic spacing withing the crystal structure of the SiGe regions, thereby compressing the channel region of the device to improve hole mobility within the PEDMOS device.

[0082] FIG. 7F is a stylized cross-sectional view showing only the BOX layer 704 and active layer 706 of a variant of the PEDMOS FET 760 of FIG. 7E. In FIG. 7F, the P+ SiGe source 710, the second P- SiGe drift region 716, and the P+ SiGe drain 718 do not extend all the way down to the BOX layer 704.

[0083] FIGS. 8A-8H are cross-sectional stylized views of example fabrication stages for the novel PEDMOS FET 700 of FIG. 7A, where the active layer 706 (by way of example only) is Si having a <110> orientation. The stages would be essentially the same for the PEDMOS FET 750 of FIG. 7C and the PEDMOS FET 760 of FIG. 7E with the exception of the selection of etchant for the regions in which the P+ SiGe source 710, the second P- SiGe drift region 716, and the P+ SiGe drain 718 are formed.

[0084] FIG. 8A shows a portion of an active layer 706 formed on a BOX layer 704, which is in turn formed on top of a substrate 702. Additionally, isolation structures 720 and a N-type body region or well 712 have been formed. In some embodiments, the active layer 706 may be formed directly on top of a bulk Si substrate 706, thus omitting the BOX layer 704, so long as some form of isolation is provided (and possibly a buried N+ layer). If needed, the semiconductor active layer 706 may be thinned to a suitable thickness, such as by chemical-mechanical polishing (CMP). Forexample, commercially available SOI wafers may have an active layer thickness of about 750A. It may be useful for some applications, particularly for RF ICs, to thin the active layer 706, for example, to about 500A.

[0085] FIG. 8B shows a gate structure Gp formed in contact with a surface of the active layer 706, between the source 710 and the drain 718. The gate structure Gp includes a conductive layer 732 (e.g., P+ doped polysilicon) in contact with an insulating GOX layer 734, and surrounding insulating spacers 736. The gate structure Gp may be formed by conventional MOSFET fabrication processes such as thermal oxidation, epitaxial deposition, photolithographic masking and etching, etc.

[0086] FIG. 8C shows that an etchant block 800 of SiCh has been formed over the conductive layer 732 of the gate structure Gp and that the active layer 706 has been masked and etched to form voids 802, 804 within the active layer 706. Void 802 is the location where the P+ SiGe source 710 is to be formed and void 804 is the location there the second P- SiGe drift region 716 and P+ SiGe drain 718 are to be formed.

[0087] In FIG. 8C, the voids 802, 804 extend into the <110> channel material with a rounded or undercut shape resulting from use of an isotropic silicon etchant such as NFUOH or ethylenediamine pyrocatechol (EDP). A pointed shape for the voids matching the SiGe regions shown in FIG. 7C may be formed by using an anisotropic silicon etchant such as tetra methyl ammonium hydroxide (TMAH). Straight-walled voids matching the SiGe regions shown in FIG. 7E may be formed by using, for example, dry plasma etching. As shown in FIGS. 7B, 7D, and 7F, the Z-dimension of the voids 802, 804 need not extend all the way down to the BOX layer 704, which may be controlled, for example, by the duration of etching. Indeed, it may be useful to leave a thin layer of Si within the voids 802, 804 to serve as a seed layer for subsequent epitaxial growth of a SiGe alloy.

[0088] FIG. 8D shows that the voids 802, 804 of FIG. 8C have been filled with a SiGe alloy, such as by chemical vapor deposition (CVD), to become filled SiGe regions 802', 804'.

[0089] FIG. 8E shows that the active layer 706 on the drain-side of the gate structure Gp is doped (e.g., by angled ion implantation after suitable masking) with a P- material e.g., boron) toform a first P- Si drift region 714 and a second P- SiGe drift region 716. The implantation is performed at an angle so that a portion of the N well material (including a portion underneath the gate structure Gp) is converted into the first P- Si drift region 714. The angled implantation also transforms the SiGe in the filled void 804' (see FIG. 8D) into the second P- SiGe drift region 716.

[0090] FIG. 8F shows that the active layer 706 on the source-side of the gate structure Gp is doped (e.g., by angled ion implantation after suitable masking) with a suitable dopant to form a halo region 722 and an LDD region 724 within the N well material (including a portion underneath the gate structure Gp).

[0091] FIG. 8G shows that the SiGe filled void 802' and a portion of the second P- SiGe drift region 716 of FIG. 8F have been defined by masking and then doped with a P+ dopant (e.g., boron) to transform those regions into the P+ SiGe source 710 and the P+ SiGe drain 718. Doping may be by ion implantation or diffusion. Subsequently, N+ material may be implanted in selective areas of the P+ SiGe source 710 and the P+ SiGe drain 718 to form body-tied-to-source connections.

[0092] FIG. 8H shows that part of the etchant block 800 (see FIG. 8G) has been removed, part of the gate structure Gp and the exposed portions of the P- drift regions 716, 718 have been coated with a dielectric 738 (SiCh, SisN4, etc ), and an SAB layer 740 (e.g., SiN) has been formed over the dielectric 738. A conductive source contact 742, a conductive gate contact 744, and a conductive drain contact 746, which may be salicides, have been respectively formed in contact with the P+ SiGe source 710, the gate structure Gp, and the P+ SiGe drain 718. Stylized electrical terminals S, G, and D are shown coupled to the corresponding source contact 742, gate contact 744, and drain contact 746.

[0093] FIGS. 9A-9B are cross-sectional stylized views of a first set of alternative fabrication stages for a PEDMOS FET that includes SiGe regions. The fabrication stages shown in FIGS. 8A- 8B would be followed by the fabrication stage shown in FIG. 9A.

[0094] FIG. 9A shows that the active layer 706 has been masked and etched (e.g., by dry plasma etching) down to the BOX layer 704 to form vertical-sidewall voids 902, 904 within the active layer 706. Void 902 is the location where the P+ SiGe source 710 is to be formed and void 904 is the location there the second P- SiGe drift region 716 and P+ SiGe drain 718 are to beformed. In some embodiments, etching is stopped before reaching the BOX layer 704, as in the example shown in FIG. 7F.

[0095] FIG. 9B shows that the voids 902, 904 of FIG. 9A have been filled with a SiGe alloy (such as by CVD, LPCVD, or an epitaxial deposition like process), to become filled SiGe regions 902', 904'. Fabrication may then continue as shown in FIGS. 8E-8H.

[0096] FIGS. 10A-10B are cross-sectional stylized views of a second set of alternative fabrication stages for a PEDMOS FET that includes SiGe regions. The fabrication stages shown in FIGS. 8A-8B would be followed by the fabrication stage shown in FIG. 10A. FIG. 10A shows that the active layer 706 has been masked to define Si regions 1002, 1004 within the active layer 706 and that the defined regions 1002, 1004 are implanted e.g., by ion implantation) with Ge. Region 1002 is the location where the P+ SiGe source 710 is to be formed and region 1004 is the location there the second P- SiGe drift region 716 and P+ SiGe drain 718 are to be formed.

[0097] FIG. 10B shows the device structure of FIG. 10A after implantation of Ge into the defined regions 1002, 1004 and annealing of the structure sufficiently to diffuse the Ge so as to create respective graded SiGe regions 1002', 1004'. As illustrated, some of the diffused Ge may intrude into the channel region underneath the gate structure 730. The graded SiGe regions 1002', 1004' impose compression across the channel region, thus improving hole mobility. Fabrication may then continue as shown in FIGS. 8E-8H.

[0098] FIGS. 11A-11C are cross-sectional stylized views of a third set of alternative fabrication stages for a PEDMOS FET that includes SiGe regions. The fabrication stages shown in FIGS. 2A-2B would be followed by the fabrication stage shown in FIG. 11 A.

[0099] FIG. 11A shows that the active layer 706 has been masked and partially etched (e.g., by dry plasma etching) to form vertical-sidewall voids 1102, 1104 within the active layer 706, each with a Si base 1106a, 1106b (i.e., an unetched remainder of the silicon active layer 706). Void 1102 and its underlying Si base 1106a is the location where the P+ SiGe source 710 is to be formed and void 1104 and its underlying Si base 1106b is the location there the second P- SiGe drift region 716 and P+ SiGe drain 718 are to be formed.

[0100] FIG. 1 IB shows the device structure of FIG. 1 1A after deposition of Ge into regions 1108a, 1108b (e.g., by CVD) occupying the respective voids 1102, 1104 ofFIG. 11 A.

[0101] FIG. 11C shows the device structure ofFIG. 1 IB after being subjected to heat treatment sufficient to diffuse the Ge regions 1108a, 1108b into the Si bases 1106a, 1106b to create respective graded SiGe regions 1110a, 1110b. As illustrated, some of the diffused Ge may intrude into the channel region underneath the gate structure 730. The graded SiGe regions 1110a, 1110b impose compression across the channel region, thus improving hole mobility. In some embodiments, diffusion of Ge is controlled so as to not reach all of way to the BOX layer 704. Fabrication may then continue as shown in FIGS. 8E-8H.

[0102] FIG. 12 is a cross-sectional stylized view of an alternative PEDMOS FET that includes SiGe regions and a stepped insulating GOX layer 734'. The stepped GOX layer 734' includes a thin (in the Z dimension) subregion adjacent the source-side of the gate structure 730 and a thick subregion adjacent the drain-side of the gate structure 730. As described above, the thin and thick subregions of the stepped GOX layer 734' will exhibit different VTH characteristics and result in improvement of a number of characteristics.

[0103] The stepped insulating GOX layer 734' may be fabricated using additive or subtractive process steps. For example, an additive process may include forming a thin layer of GOX over the active layer 706, then masking the GOX to expose stripes over which additional oxide may be grown to form the thick regions, then removing the masking material (e.g., a photolithographic polymer). As another example, a subtractive process may include forming a thick layer of GOX over the active layer 706, then masking the GOX to protect stripes of thick GOX material, then etching the unprotected GOX to a desired thinness, then removing the masking material.

[0104] In the examples above, it may be useful to fabricate the spacers 736 to be asymmetric. For example, the thickness (in the X dimension) of the drain-side spacer 736 may be greater than the thickness of the source-side spacer 736. Asymmetric spacers may provide a breakdown voltage due to being thicker on the drain-side of the gate structure 730.

[0105] It should be appreciated that fabrication of a NFET 302 and NEDMOS 402, as well as LDMOS variants, may be accomplished using process steps identical to, or very similar to, the process steps for fabricating the PEDMOS devices shown in FIGS. 7A-7F.

[0106] Note that not all steps that may be performed during the manufacture of NFET, NEDMOS, and PEDMOS devices as part of an IC are shown in the aforementioned figures. Such steps may vary between IC foundries and may include (but are not limited to) substrate thinning, planarization, special implantations, annealing, formation of ohmic contacts, and formation of additional temporary or permanent structures (e.g., drift regions, substrate contacts, passivation layers, salicide blocks, replacement metal gate (RMG)), etc. After formation of a basic MOSFET structure, back-end-of-line (BEOL) processes may be applied, such as fabrication of electrical contacts (pads), vias, insulating layers (dielectrics), metallization layers, and bonding sites for die- to-package connections.

[0107] A number of different processes may be used to fabricate the PEDMOS IC architectures shown in FIGS. 7A-7F. FIG. 13 is a process flowchart showing one fabrication process that is suitable for some contemporary IC front-end-of-line (FEOL) foundries. Note that some conventional steps, such as planarization, passivation, details of masking and etching, and superstructure formation have been omitted as known to those of ordinary skill in the art. The illustrated process includes:(1) If needed, thinning the semiconductor active layer (e. ., Si, Ge, SiGe, SiC, or the like) formed on a substrate to a suitable thickness (Step 1302).(2) Forming shallow trench isolation (STI) regions (Step 1304).(3) Implanting N-type wells (Step 1306).(4) Performing gate oxidation (Step 1308).(5) Depositing gate material (e.g., P+ poly-Si), patterning (e.g, masking and etching) to define gate structures, and forming gate structure spacers (Step 1310).(6) Defining and forming SiGe regions for the source 710, second drift region 716, and drain 718 (Step 1312). This may be done, for example, by etching voids in the active layer 706 anddepositing SiGe within the voids (see, e.g., FIGS. 8C-8D and 9A-9B); implanting Ge into defined regions of the Si active layer 706 to form SiGe regions (see, e.g., FIGS. 10A-10B); or etching partial voids in the Si active layer 706, depositing Ge within the partial voids, and thermally diffusing the Ge into the Si to form graded SiGe regions (see, e.g., FIGS. 11A- 11C).(7) Patterning a first Si drift region 714 and the second SiGe drift region 716 and angle implanting P- dopant (Step 1314)(8) Optionally, patterning halo and / or LDD regions and angle implanting dopant (Step 1316).(9) Implanting P+ source S and drain D regions and one or more N+ body contact regions (Step 1318).(10) Depositing a salicide block layer and patterning to define contact regions (Step 1320).(11) Depositing or forming salicide (e.g., NiSi) in the defined contact regions and annealing (Step 1322).

[0108] As should be appreciated, other “recipes” that include additive and / or subtractive process steps may be used to fabricate essentially the same PEDMOS structures of the type described in this disclosure. Further, the fabrications steps may be performed in any feasible order.

[0109] The IC structures shown in FIGS. 3-6 implement different versions of the amplifier core 102 shown in FIG. 1. A similar approach using NFETs and NEDMOS devices may be used to implement a version of the amplifier core 102 shown in FIG. 2. For example, FIG. 14 is a stylized cross-sectional view of a fifth SOI IC structure 1400 of an amplifier core including an NFET 302 and two co-fabricated and concatenated NEDMOS devices 402-1, 402-2 of a set of one or more NEDMOS devices. The drain of NEFT 302 and the source of NEDMOS device 402-1 are a shared N+ region 1402, while the drain of NEDMOS device 402-1 and the source of NEDMOS device 402-2 are a shared N+ region 1404 (similarly, the drain and source regions of abutting PEDMOS devices are shared). While not apparent in the drawing, the GOX layers of the NEDMOS devices 402-1, 402-2 may be thicker than the GOX layer of the NFET 302 in order to withstand high drain voltages.

[0110] In some embodiments, only the first NEDMOS device 402-1 may be needed. As should be clear, additional NEDMOS devices may be co-fabricated and concatenated with the illustrated NEDMOS devices 402-1, 402-1 to withstand even higher drain voltages.

[0111] Embodiments of the illustrated IC structures described above, and variations of such structures, may include raised (or sunken) source and / or drain regions. Raised source and / or drain regions reduce parasitic resistance. Doping for the drift regions DRN, DRP in NEDMOS and PEDMOS devices need not be uniform, and may vary along at least the X dimension of the device.

[0112] It is common to include a Body-Tied-to-Source (BTS) structure for MOSFETs, and a BTS configuration may be used with the device architectures described above. In N-type MOSFETS, a BTS structure generally comprises a small region of isolated P+ material located within the N+ source region of the device that couples to the body of the device. In P-type MOSFETS, a BTS structure generally comprises a small region of isolated N+ material located within the P+ source region of the device that couples to the body of the device. A BTS structure thus provides a body terminal for the device, which is commonly (but not necessarily) connected to the source.

[0113] A BTS structure in a PEDMOS device fabricated on an SOI substrate is of a special importance - the BTS structure eliminates or substantially mitigates the floating body current effect; mitigates turn-on of the parasitic bipolar devices inherent in the device; improves the breakdown voltage of the device; improves electro-static discharge (ESD) protection for the device; improves the output impedance of the device (very important for analog circuits); and improves device and circuitry performance and capability, and in particular improves circuit linearity, reliability, and power consumption in analog and digital circuitry, especially for such devices as RF and mmWave switches, low-noise amplifiers (LNAs), and power amplifiers (PAs).

[0114] FIG. 15 is a top plan view of a first configuration of BTS structures for multiple PEDMOS devices 304-1, 304-2, 304-3 co-fabricated with an NFET 302. Each device includes a respective gate, G1-G4; electrical terminals 1500 are shown as squares with an interior “X” (not all terminals are labeled to avoid clutter). The drain DN of the NFET 302 is shown as coupled to the drain Dp of a first PEDMOS device 304-1. The source Sp of PEDMOS device 304-1 is coupled to the drain Dp of a second PEDMOS device 304-2, and the source Sp of PEDMOS device 304-2is coupled to the drain Dp of a third PEDMOS device 304-3. Each PEDMOS device 304-n includes two end-positioned BTS structures comprising N+ body contact regions 1502 (associated terminals are omitted to avoid clutter). Placing the BTS structures along the X-dimension edges of the PEDMOS devices reduces current leakage by increasing the VTH at those edges. Having more than one BTS structure provides more efficient electron (e-) collection compared to a single central BTS structure. However, in some embodiments, a single central BTS structure may be sufficient.

[0115] FIG. 16 is a top plan view of a second configuration of BTS structures for multiple PEDMOS devices 304-1, 304-2, 304-3 co-fabricated with an NFET 302. Similar in most aspects to the example shown in FIG. 15, one difference is the inclusion of both end-positioned N+ body contact regions 1602 and multiple interior-positioned N+ body contact regions 1604 (not all interior body contact regions are labeled to avoid clutter). The added body contact regions 1604 provide even more efficient electron (e-) collection than the configuration shown in FIG. 15.

[0116] FIG. 17 is a top plan view of a configuration of BTS structures for multiple NEDMOS devices 402-1, 402-2, 402-3 co-fabricated with an NFET 302. Each device includes a respective gate, G1-G4; electrical terminals 1700 are shown as squares with an interior “X” (not all terminals are labeled to avoid clutter). The drain DN of the NFET 302 is shown as coupled to the source DN of a first NEDMOS device 402-1. The drain DN of NEDMOS device 402-1 is coupled to the source SN of a second NEDMOS device 402-2, and the drain DN of NEDMOS device 402-2 is coupled to the source SN of a third PEDMOS device 402-3. The illustrated embodiments includes both end- positioned P+ body contact regions 1702 and multiple interior-positioned P+ body contact regions 1704 (not all interior body contact regions are labeled to avoid clutter). The added body contact regions 1704 provide even more efficient hole collection compared to a configuration having only end-positioned BTS structures. However, in some embodiments, using only two end-positioned P+ body contact regions 1702 may be sufficient.

[0117] The multi-gate IC configuration shown in FIG. 17 is compact, owing to the shared source / drain regions, which shows results in modeled circuits of a reduction in the parasitic gatesource capacitance CGS of about 17% and in the parasitic gate-drain capacitance of about 27%. In addition, the ON resistance, RON, is lower by about 11%, a benefit when using such a configuration for in switches, particularly RF switches.

[0118] For some applications, it may not be necessary to include BTS structures since holes have a lower impact ionization rate. Omitting BTS structures may save IC layout area. FIG. 18 is a top plan view of a configuration of multiple PEDMOS devices 304-1, 304-2, 304-3 lacking BTS structures and co-fabricated with an NFET 302.

[0119] A benefit of the IC structures described above, and variations of such structures, is the space savings in IC layouts resulting from the use of shared regions between adjacent devices, particularly when concatenating multiple PEDMOS and NEDMOS devices and sharing drain / source regions. In addition, space savings may also be achieved due to the higher breakdown BVDSS value of such devices, which gives designers freedom to reduce the transistor count for a particular application.

[0120] It should be appreciated that a number of features described in this disclosure may be “mixed and matched” to create further variations without departing from the scope of the invention. For instance, in the examples shown in FIGS. 15, 16, and 18, one or more of the PEDMOS devices 304-1, 304-2, 304-3 may include a secondary gate structure GDR as shown in FIG. 6. As another example, one or more of the PEDMOS devices 304-1, 304-2, 304-3 may include a stepped GOX layer, as shown in FIGS. 5 and 12. Halo and LDD regions may be omitted from or included in one or both of the source-side and drain-side of an NFET, NEDMOS device, or PEDMOS device. Accordingly, the invention is not limited to the specific examples described and illustrated in this disclosure.

[0121] Circuits and devices in accordance with the present invention may be used alone or in combination with other components, circuits, and devices. Embodiments of the present invention may be encased in IC packages and / or in modules for ease of handling, manufacture, and / or improved performance. In particular, IC embodiments of this invention are often used in modules in which one or more of such ICs are combined with other circuit components or blocks (e.g., filters, amplifiers, passive components, and possibly additional ICs) into one package. The ICs and / or modules are then typically combined with other components, often on a printed circuit board, to form part of an end-product such as a cellular telephone, laptop computer, or electronic tablet, or to form a higher-level module which may be used in a wide variety of products, such asvehicles, test equipment, medical devices, etc. Through various configurations of modules and assemblies, such ICs typically enable a mode of communication, often wireless communication.

[0122] As one example of further integration of embodiments of the present invention with other components, FIG. 19 is a top plan view of a substrate 1900 that may be, for example, a printed circuit board or chip module substrate (e.g., a thin-film tile). In the illustrated example, the substrate 1900 includes multiple ICs 1902a-1902d having terminal pads 1904 which would be interconnected by conductive vias and / or traces on and / or within the substrate 1900 or on the opposite (back) surface of the substrate 1900 (to avoid clutter, the surface conductive traces are not shown and not all terminal pads are labelled). The ICs 1902a-1902d may embody, for example, signal switches, active and / or passive filters, amplifiers (including one or more LNAs), and other circuitry. For example, IC 1902b may incorporate one or more instances of an amplifier having an IC structure like the structures shown in the accompanying figures.

[0123] The substrate 1900 may also include one or more passive devices 1906 embedded in, formed on, and / or affixed to the substrate 1900. While shown as generic rectangles, the passive devices 1906 may be, for example, filters, capacitors, inductors, transmission lines, resistors, antennae elements, transducers (including, for example, MEMS-based transducers, such as accelerometers, gyroscopes, microphones, pressure sensors, etc.), batteries, etc., interconnected by conductive traces on or in the substrate 1900 to other passive devices 1906 and / or the individual ICs 1902a-1902d.

[0124] The front or back surface of the substrate 1900 may be used as a location for the formation of other structures. For example, one or more antennae may be formed on or affixed to the front or back surface of the substrate 1900; one example of a front-surface antenna 1908 is shown, coupled to an IC die 1902b, which may include RF front-end circuitry. Thus, by including one or more antennae on the substrate 1900, a complete radio may be created.

[0125] Embodiments of the present invention are useful in a wide variety of larger radio frequency (RF) circuits and systems for performing a range of functions, including (but not limited to) impedance matching circuits, RF power amplifiers, RF low-noise amplifiers (LNAs), phase shifters, attenuators, antenna beam-steering systems, charge pump devices, RF switches, etc. Suchfunctions are useful in a variety of applications, such as radar systems (including phased array and automotive radar systems), radio systems (including cellular radio systems), and test equipment.

[0126] Radio system usage includes wireless RF systems (including base stations, relay stations, and hand-held transceivers) that use various technologies and protocols, including various types of orthogonal frequency-division multiplexing (“OFDM”), quadrature amplitude modulation (“QAM”), Code-Division Multiple Access (“CDMA”), Time-Division Multiple Access (“TDMA”), Wide Band Code Division Multiple Access (“W-CDMA”), Global System for Mobile Communications (“GSM”), Long Term Evolution (“LTE”), 5G, 6G, and WiFi (e.g., 802.1 la, b, g, ac, ax, be) protocols, as well as other radio communication standards and protocols.

[0127] As an example of wireless RF system usage, FIG. 20 illustrates a prior art wireless communication environment 2000 comprising different wireless communication systems 2002 and 2004, and which may include one or more mobile wireless devices 2006. A wireless device 2006 may be a cellular phone, a wireless-enabled computer or tablet, or some other wireless communication unit or device. A wireless device 2006 may also be referred to as a mobile station, user equipment, an access terminal, or some other terminology known in the telecommunications industry.

[0128] A wireless device 2006 may be capable of communicating with multiple wireless communication systems 2002, 2004 using one or more of telecommunication protocols such as the protocols noted above. A wireless device 2006 also may be capable of communicating with one or more satellites 2008, such as navigation satellites (e.g., GPS) and / or telecommunication satellites. The wireless device 2006 may be equipped with multiple antennas, externally and / or internally, for operation on different frequencies and / or to provide diversity against deleterious path effects such as fading and multi-path interference.

[0129] The wireless communication system 2002 may be, for example, a CDMA-based system that includes one or more base station transceivers (BSTs) 2010 and at least one switching center (SC) 2012. Each BST 2010 provides over-the-air RF communication for wireless devices 2006 within its coverage area. The SC 2012 couples to one or more BSTs 2010 in the wireless system 2002 and provides coordination and control for those BSTs 2010.

[0130] The wireless communication system 2004 may be, for example, a TDMA-based system that includes one or more transceiver nodes 2014 and a network center (NC) 2016. Each transceiver node 2014 provides over-the-air RF communication for wireless devices 2006 within its coverage area. The NC 2016 couples to one or more transceiver nodes 2014 in the wireless system 2004 and provides coordination and control for those transceiver nodes 2014.

[0131] In general, each BST 2010 and transceiver node 2014 is a fixed station that provides communication coverage for wireless devices 2006, and may also be referred to as base stations or some other terminology known in the telecommunications industry. The SC 2012 and the NC 2016 are network entities that provide coordination and control for the base stations and may also be referred to by other terminologies known in the telecommunications industry.

[0132] An important aspect of any wireless system, including the systems shown in FIG. 20, is in the details of how the component elements of the system perform. FIG. 21 is a block diagram of a transceiver 2100 that might be used in a wireless device, such as a cellular telephone, and which may beneficially incorporate an embodiment of the present invention for improved performance. As illustrated, the transceiver 2100 includes a mix of RF analog circuitry for directly conveying and / or transforming signals on an RF signal path, non-RF analog circuity for operational needs outside of the RF signal path (e.g., for bias voltages and switching signals), and digital circuitry for control and user interface requirements. In this example, a receiver path Rx includes RF Front End (RFFE), Intermediate Frequency (IF) Block, Back-End, and Baseband sections (noting that in some implementations, the differentiation between sections may be different). The various illustrated sections and circuit elements may be embodied in one die or multiple IC dies. For example, the RF Front End in the illustrated example may include an RFFE module and a Mixing Block, which may be embodied in (or as part of) different IC dies or modules. The different dies and / or modules may be coupled by transmission lines TIN and TOUT (e.g., microstrips, co-planar waveguides, or an equivalent structure or circuit), either or both of which may have, for example, a 50 impedance.

[0133] The receiver path Rx receives over-the-air RF signals through at least one antenna 2102 and a switching unit 2104, which may be implemented with active switching devices (e.g., field effect transistors or FETs) and / or with passive devices that implement frequency-domainmultiplexing, such as a diplexer or duplexer. An RF fdter 2106 passes desired received RF signals to at least one low noise amplifier (LNA) 2108a, the output of which is coupled from the RFFE Module to at least one LNA 2108b in the Mixing Block (through transmission line TIN in this example). The LNA(s) 2108b may provide buffering, input matching, and reverse isolation. In some embodiments, the LNA(s) 2108a and 2108b may be a single LNA. The LNA(s) 2108a and 2108b may be implemented using combined N-type FET / PEDMOS device IC structures in accordance with the present invention.

[0134] The output of the LNA(s) 2108b is combined in a corresponding mixer 2110 with the output of a first local oscillator 2112 to produce an IF signal. The IF signal may be amplified by an IF amplifier 2114 and subjected to an IF filter 2116 before being applied to a demodulator 2118, which may be coupled to a second local oscillator 2120. The demodulated output of the demodulator 2118 is transformed to a digital signal by an analog-to-digital converter 2122 and provided to one or more system components 2124 (e. , a video graphics circuit, a sound circuit, memory devices, etc.). The converted digital signal may represent, for example, video or still images, sounds, or symbols, such as text or other characters.

[0135] In the illustrated example, a transmitter path Tx includes Baseband, Back-End, IF Block, and RF Front End sections (again, in some implementations, the differentiation between sections may be different). Digital data from one or more system components 2124 is transformed to an analog signal by a digital-to-analog converter 2126, the output of which is applied to a modulator 2128, which also may be coupled to the second local oscillator 2120. The modulated output of the modulator 2128 may be subjected to an IF filter 2130 before being amplified by an IF amplifier 2132. The output of the IF amplifier 2132 is then combined in a mixer 2134 with the output of the first local oscillator 2112 to produce an RF signal. The RF signal may be amplified by a driver 2136, the output of which is coupled to a power amplifier (PA) 2138 (through transmission line TOUT in this example). The amplified RF signal may be coupled to an RF filter 2140, the output of which is coupled to at least one antenna 2102 through the switching unit 804.

[0136] The operation of the transceiver 2100 is controlled by a microprocessor 2142 in known fashion, which interacts with system control components 2144 (e.g., user interfaces, memory / storage devices, application programs, operating system software, power control, etc.). Inaddition, the transceiver 2100 will generally include other circuitry, such as bias circuitry 2146 (which may be distributed throughout the transceiver 2100 in proximity to transistor devices), electro-static discharge (ESD) protection circuits, testing circuits (not shown), factory programming interfaces (not shown), etc.

[0137] In modern transceivers, there are often more than one receiver path Rx and transmitter path Tx, for example, to accommodate multiple frequencies and / or signaling modalities. Further, as should be apparent to one of ordinary skill in the art, some components of the transceiver 2100 may be positioned in a different order (e. ., filters) or omitted. Other components can be (and often are) added, such as (by way of example only) additional filters, impedance matching networks, variable phase shifters / attenuators, power dividers, etc.

[0138] Another aspect of the invention includes corresponding methods for fabricating an integrated circuit. A first method includes fabricating an N-type MOSFET having a source, a body laterally adjacent the source, a gate structure positioned with respect to the body so as to be able to influence current flow through the body, and a drain laterally adjacent the body; co-fabricating a P-type extended drain MOSFET having a source, a body laterally adjacent the source, a gate structure positioned with respect to the body so as to be able to influence current flow through the body, a drift region laterally adjacent the body, and a drain laterally adjacent the drift region; wherein the drain of the N-type MOSFET and the drain of the P-type extended drain MOSFET are shared regions within the integrated circuit having a common electrical contact.

[0139] A second method includes fabricating an N-type MOSFET having a source, a body laterally adjacent the source, a gate structure positioned with respect to the body so as to be able to influence current flow through the body, a drift region laterally adjacent the body, and a drain laterally adjacent the drift region; co-fabricating a P-type extended drain MOSFET having a source, a body laterally adjacent the source, a gate structure positioned with respect to the body so as to be able to influence current flow through the body, a drift region laterally adjacent the body, and a drain laterally adjacent the drift region; wherein the drain of the N-type MOSFET and the drain of the P-type extended drain MOSFET are shared regions within the integrated circuit having a common electrical contact.

[0140] A third method includes fabricating an N-type MOSFET having a source, a body laterally adjacent the source, a gate structure positioned with respect to the body so as to be able to influence current flow through the body, and a drain laterally adjacent the body; co-fabricating an N-type extended drain MOSFET having a source, a body laterally adjacent the source, a gate structure positioned with respect to the body so as to be able to influence current flow through the body, a drift region laterally adjacent the body, and a drain laterally adjacent the drift region; wherein the drain of the N-type MOSFET and the source of the N-type extended drain MOSFET are shared regions within the integrated circuit.

[0141] Additional aspects of the above methods includes one or more of the following: further including co-fabricating at least one additional P-type extended drain MOSFET, each having a source, a body laterally adjacent the source, a gate structure positioned with respect to the body so as to be able to influence current flow through the body, a drift region laterally adjacent the body, and a drain laterally adjacent the drift region, wherein the drain of each additional P-type extended drain MOSFET is shared in common with the drain of the P-type extended drain MOSFET or the drain of one of the additional P-type extended drain MOSFETs; wherein the gate structure of the P-type extended drain MOSFET includes a stepped gate oxide layer; wherein the P-type extended drain MOSFET includes a P-well region within the drift region of the P-type extended drain MOSFET and a secondary gate structure positioned with respect to the P-well region so as to be able to influence current flow through the P-well region; wherein the P-type extended drain MOSFET includes two end-positioned body-tied-to-source structures; wherein the P-type extended drain MOSFET includes two end-positioned body contact regions and at least one interior-positioned body contact region; wherein at least the source and the drain of the P-type extended drain MOSFET are fabricated at least in part with a silicon germanium alloy; wherein at least a portion of the drift region is fabricated at least in part with a silicon germanium alloy; further including co-fabricating at least one additional N-type extended drain MOSFET, each having a source, a body laterally adjacent the source, a gate structure positioned with respect to the body so as to be able to influence current flow through the body, a drift region laterally adjacent the body, and a drain laterally adjacent the drift region, wherein the source of each additional N-type extended drain MOSFET is shared in common with the drain of the N-type extended drain MOSFET or the drain of one of the additional N-type extended drain MOSFETs; and / or wherein the N-type extended drain MOSFET includes two end-positioned body-tied-to-source structures;wherein the N-type extended drain MOSFET includes two end-positioned body contact regions and at least one interior-positioned body contact region.

[0142] The term “MOSFET”, as used in this disclosure, includes any field effect transistor (FET) having an insulated gate whose voltage determines the conductivity of the transistor, and encompasses insulated gates having a metal or metal-like, insulator, and / or semiconductor structure. The terms “metal” or “metal-like” include at least one electrically conductive material (such as aluminum, copper, or other metal, or highly doped polysilicon, carbon-based materials (e.g, graphene), or other electrical conductor), “insulator” includes at least one insulating material (such as silicon oxide or other dielectric material), and “semiconductor” includes at least one semiconductor material.

[0143] As used in this disclosure, the term “radio frequency” (RF) refers to a rate of oscillation in the range of about 3 kHz to about 300 GHz. This term also includes the frequencies used in wireless communication systems. An RF frequency may be the frequency of an electromagnetic wave or of an alternating voltage or current in a circuit.

[0144] With respect to the figures referenced in this disclosure, the dimensions for the various elements are not to scale; some dimensions may be greatly exaggerated vertically and / or horizontally for clarity or emphasis. In addition, references to orientations and directions (e.g, “top”, “bottom”, “above”, “below”, “lateral”, “vertical”, “horizontal”, etc are relative to the example drawings, and not necessarily absolute orientations or directions.

[0145] Various embodiments of the invention can be implemented to meet a wide variety of specifications. Unless otherwise noted above, selection of suitable component values is a matter of design choice. Various embodiments of the invention may be implemented in any suitable integrated circuit (IC) technology (including but not limited to MOSFET structures), or in hybrid or discrete circuit forms. Integrated circuit embodiments may be fabricated using any suitable substrates and processes, including but not limited to standard bulk silicon, high-resistivity bulk CMOS, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS). Unless otherwise noted above, embodiments of the invention may be implemented in other transistor technologies, such as BiCMOS, LDMOS, and FinFET devices. However, embodiments of the invention are particularly useful when fabricated using an SOI or SOS based process, or when fabricated with processeshaving similar characteristics. Fabrication in CMOS using SOI or SOS processes enables circuits with low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high frequency operation ( / .< ., radio frequencies up to and exceeding 300 GHz). Monolithic IC implementation is particularly useful since parasitic capacitances generally can be kept low (or at a minimum, kept uniform across all units, permitting them to be compensated) by careful design.

[0146] Voltage levels may be adjusted, and / or voltage and / or logic signal polarities reversed, depending on a particular specification and / or implementing technology (e.g., NMOS, PMOS, or CMOS, and enhancement mode or depletion mode transistor devices). Component voltage, current, and power handling capabilities may be adapted as needed, for example, by adjusting device sizes, serially “stacking” components (particularly FETs) to withstand greater voltages, and / or using multiple components in parallel to handle greater currents. Additional circuit components may be added to enhance the capabilities of the disclosed circuits and / or to provide additional functionality without significantly altering the functionality of the disclosed circuits.

[0147] Conclusion

[0148] A number of embodiments of the invention have been described. It is to be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, some of the steps described above may be order independent, and thus can be performed in an order different from that described. Further, some of the steps described above may be optional. Various activities described with respect to the methods identified above can be executed in repetitive, serial, and / or parallel fashion.

[0149] It is to be understood that the foregoing description is intended to illustrate and not to limit the scope of the invention, which is defined by the scope of the following claims, and that other embodiments are within the scope of the claims. In particular, the scope of the invention includes any and all feasible combinations of one or more of the processes, machines, manufactures, or compositions of matter set forth in the claims below. (Note that the parenthetical labels for claim elements are for ease of referring to such elements, and do not in themselves indicate a particular required ordering or enumeration of elements; further, such labels may bereused in dependent claims as references to additional elements without being regarded as starting a conflicting labeling sequence).

Claims

CLAIMSWHAT IS CLAIMED IS:

1. An integrated circuit including:(a) an N-type MOSFET having a source, a body laterally adjacent the source, a gate structure positioned with respect to the body so as to be able to influence current flow through the body, and a drain laterally adjacent the body; and(b) a P-type extended drain MOSFET having a source, a body laterally adjacent the source, a gate structure positioned with respect to the body so as to be able to influence current flow through the body, a drift region laterally adjacent the body, and a drain laterally adjacent the drift region; wherein the drain of the N-type MOSFET and the drain of the P-type extended drain MOSFET are shared regions within the integrated circuit having a common electrical contact.

2. The integrated circuit of claim 1 , further including at least one additional P-type extended drain MOSFET, each having a source, a body laterally adjacent the source, a gate structure positioned with respect to the body so as to be able to influence current flow through the body, a drift region laterally adjacent the body, and a drain laterally adjacent the drift region, wherein the drain of each additional P-type extended drain MOSFET is shared in common with the drain of the P-type extended drain MOSFET or the drain of one of the additional P-type extended drain MOSFETs.

3. The integrated circuit of claim 1, wherein the gate structure of the P-type extended drain MOSFET includes a stepped gate oxide layer.

4. The integrated circuit of claim 1, wherein the P-type extended drain MOSFET includes a P- well region within the drift region of the P-type extended drain MOSFET and a secondary gate structure positioned with respect to the P-well region so as to be able to influence current flow through the P-well region.

5. The integrated circuit of claim 1, wherein the P-type extended drain MOSFET includes two end-positioned body-tied-to-source structures.

6. The integrated circuit of claim 1, wherein the P-type extended drain MOSFET includes two end-positioned body contact regions and at least one interior-positioned body contact region.

7. The integrated circuit of claim 1, wherein at least the source and the drain of the P-type extended drain MOSFET are fabricated at least in part with a silicon germanium alloy.

8. The integrated circuit of claim 7, wherein at least a portion of the drift region is fabricated at least in part with a silicon germanium alloy.

9. An integrated circuit including:(a) an N-type MOSFET having a source, a body laterally adj acent the source, a gate structure positioned with respect to the body so as to be able to influence current flow through the body, a drift region laterally adjacent the body, and a drain laterally adjacent the drift region; and(b) a P-type extended drain MOSFET having a source, a body laterally adjacent the source, a gate structure positioned with respect to the body so as to be able to influence current flow through the body, a drift region laterally adjacent the body, and a drain laterally adjacent the drift region; wherein the drain of the N-type MOSFET and the drain of the P-type extended drain MOSFET are shared regions within the integrated circuit having a common electrical contact.

10. The integrated circuit of claim 9, further including at least one additional P-type extended drain MOSFET, each having a source, a body laterally adjacent the source, a gate structure positioned with respect to the body so as to be able to influence current flow through the body, a drift region laterally adjacent the body, and a drain laterally adjacent the drift region, wherein the drain of each additional P-type extended drain MOSFET is shared in common with the drain of the P-type extended drain MOSFET or the drain of one of the additional P-type extended drain MOSFETs.

11. The integrated circuit of claim 9, wherein the gate structure of the P-type extended drain MOSFET includes a stepped gate oxide layer.

12. The integrated circuit of claim 9, wherein the P-type extended drain MOSFET includes a P- well region within the drift region of the P-type extended drain MOSFET and a secondary gatestructure positioned with respect to the P-well region so as to be able to influence current flow through the P-well region.

13. The integrated circuit of claim 9, wherein the P-type extended drain MOSFET includes two end-positioned body-tied-to-source structures.

14. The integrated circuit of claim 9, wherein the P-type extended drain MOSFET includes two end-positioned body contact regions and at least one interior-positioned body contact region.

15. The integrated circuit of claim 9, wherein at least the source and the drain of the P-type extended drain MOSFET are fabricated at least in part with a silicon germanium alloy.

16. The integrated circuit of claim 15, wherein at least a portion of the drift region is fabricated at least in part with a silicon germanium alloy.

17. An integrated circuit including:(a) an N-type MOSFET having a source, a body laterally adj acent the source, a gate structure positioned with respect to the body so as to be able to influence current flow through the body, and a drain laterally adjacent the body; and(b) an N-type extended drain MOSFET having a source, a body laterally adjacent the source, a gate structure positioned with respect to the body so as to be able to influence current flow through the body, a drift region laterally adjacent the body, and a drain laterally adjacent the drift region; wherein the drain of the N-type MOSFET and the source of the N-type extended drain MOSFET are shared regions within the integrated circuit.

18. The integrated circuit of claim 1, further including at least one additional N-type extended drain MOSFET, each having a source, a body laterally adjacent the source, a gate structure positioned with respect to the body so as to be able to influence current flow through the body, a drift region laterally adjacent the body, and a drain laterally adjacent the drift region, wherein the source of each additional N-type extended drain MOSFET is shared in common with the drain of the N-type extended drain MOSFET or the drain of one of the additional N-type extended drain MOSFETs.

19. The integrated circuit of claim 18, wherein the N-type extended drain MOSFET includes two end-positioned body-tied-to-source structures.

20. The integrated circuit of claim 18, wherein the N-type extended drain MOSFET includes two end-positioned body contact regions and at least one interior-positioned body contact region.

21. A method of fabricating an integrated circuit, including:(a) fabricating an N-type MOSFET having a source, a body laterally adjacent the source, a gate structure positioned with respect to the body so as to be able to influence current flow through the body, and a drain laterally adjacent the body; and(b) co-fabricating a P-type extended drain MOSFET having a source, a body laterally adjacent the source, a gate structure positioned with respect to the body so as to be able to influence current flow through the body, a drift region laterally adjacent the body, and a drain laterally adjacent the drift region; wherein the drain of the N-type MOSFET and the drain of the P-type extended drain MOSFET are shared regions within the integrated circuit having a common electrical contact.

22. A method of fabricating an integrated circuit, including:(a) fabricating an N-type MOSFET having a source, a body laterally adjacent the source, a gate structure positioned with respect to the body so as to be able to influence current flow through the body, a drift region laterally adjacent the body, and a drain laterally adjacent the drift region; and(b) co-fabricating a P-type extended drain MOSFET having a source, a body laterally adjacent the source, a gate structure positioned with respect to the body so as to be able to influence current flow through the body, a drift region laterally adjacent the body, and a drain laterally adjacent the drift region; wherein the drain of the N-type MOSFET and the drain of the P-type extended drain MOSFET are shared regions within the integrated circuit having a common electrical contact.

23. An integrated circuit including:(a) fabricating an N-type MOSFET having a source, a body laterally adjacent the source, a gate structure positioned with respect to the body so as to be able to influence current flow through the body, and a drain laterally adjacent the body; and(b) co-fabricating an N-type extended drain MOSFET having a source, a body laterally adjacent the source, a gate structure positioned with respect to the body so as to be able to influence current flow through the body, a drift region laterally adjacent the body, and a drain laterally adjacent the drift region; wherein the drain of the N-type MOSFET and the source of the N-type extended drain MOSFET are shared regions within the integrated circuit.

Images