Method for communication, device, storage medium, and program product

Abstract

Embodiments of the present application provide a method for communication, a device, a storage medium, and a program product. In the method, a decoding apparatus decodes a low density parity check (LDPC) code on the basis of a belief propagation (BP) algorithm to obtain an initial bit sequence that does not satisfy a parity-check equation set. In addition, the decoding apparatus performs multiple bit flipping operations on a predetermined bit range of the initial bit sequence to obtain a plurality of flipped bit sequences. In one bit flipping operation, at least one bit in the predetermined bit range is flipped. In addition, the decoding apparatus performs LDPC encoding on the plurality of flipped bit sequences to obtain a plurality of candidate bit sequences. Furthermore, the decoding apparatus determines, from among the plurality of candidate bit sequences, a target bit sequence meeting a predetermined condition as a decoding result of the LDPC code. In this way, a certain degree of randomness is introduced by performing bit flipping within the predetermined bit range, thereby resisting the influence of noise or interference, improving decoding performance, and reducing complexity.

Description

Method, device, storage medium and program product for communication

[0001] This application claims priority to the Chinese patent application No. 202411002658.6, filed on July 24, 2024, and entitled “Method, device, storage medium and program product for communication”, the entire content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] Embodiments of the present application generally relate to the field of communication, and more particularly to a method, apparatus, computer readable storage medium and computer program product for communication. BACKGROUND

[0003] A mobile or wireless communication network can be seen as a facility that enables wireless communication between two or more communication devices or provides wireless access to a data network for communication devices. In order to enable interworking between communication devices, such as network devices, terminal devices, etc., corresponding communication standards are developed, such as standards developed by the 3rd Generation Partnership Project (3GPP) or the European Telecommunications Standards Institute (ETSI). Examples of such standards include the 5th Generation (5G) standard, the future wireless communication standard, etc. In various communication scenarios, low density parity check (LDPC) codes can be used. However, some aspects of LDPC codes still need further optimization. rd th Generation, 5G) standard, the future wireless communication standard, etc. In various communication scenarios, low density parity check (LDPC) codes can be used. However, some aspects of LDPC codes still need further optimization. SUMMARY

[0004] Embodiments of the present application provide a technical solution for communication, in particular a technical solution for LDPC decoding or encoding.

[0005] ​In a first aspect, a decoding method is provided. The execution subject of the method can be a decoding apparatus or a chip applied to the decoding apparatus. Hereinafter, the execution subject is taken as an example of the decoding apparatus for description. Unless otherwise specified, the "decoding apparatus" in the present application can refer to the decoding apparatus itself, a component (for example, a communication module, a processor, a circuit, a chip, or a chip system) in the decoding apparatus, or a logic module or software capable of realizing all or part of the functions of the decoding apparatus. Hereinafter, the execution subject is taken as an example of the decoding apparatus for description. In the method, the decoding apparatus decodes a low-density parity-check (LDPC) code based on a belief propagation (BP) algorithm, and obtains an initial bit sequence that does not satisfy a check equation set. In addition, the decoding apparatus performs a plurality of bit flipping operations on a predetermined bit range of the initial bit sequence, and obtains a plurality of flipped bit sequences. In one bit flipping operation, at least one bit in the predetermined bit range is flipped. In addition, the decoding apparatus performs LDPC encoding on the plurality of flipped bit sequences, and obtains a plurality of candidate bit sequences. In addition, the decoding apparatus determines a target bit sequence that satisfies a predetermined condition from the plurality of candidate bit sequences as a decoding result of the LDPC code. The belief propagation algorithm can include a BP algorithm, a Min-Sum algorithm, and the like. The initial bit sequence can be a bit sequence obtained after a hard decision of a value of a variable node of the BP decoding. In this way, a certain randomness is introduced by flipping bits in the predetermined bit range, so as to resist the influence of noise or interference, improve decoding performance, and reduce complexity.

[0006] In some implementations, in one bit flipping operation, the number of flipped bits is greater than or equal to 1 and less than or equal to a predetermined flipping order. In this way, a plurality of bits can be flipped under the condition that the decoding delay is allowed, so as to improve decoding performance.

[0007] In some implementations, the predetermined flipping order is determined by the decoding apparatus or indicated at a physical layer. In this way, decoding flexibility can be improved.

[0008] In some implementations, the plurality of bit flipping operations performed by the decoding apparatus include: the decoding apparatus obtains a first group of flipped bit sequences based on a first group of bit flipping operations performed on the predetermined bit range. In the first group of bit flipping operations, different N bits in the predetermined bit range are flipped. In addition, the decoding apparatus obtains a second group of flipped bit sequences based on a second group of bit flipping operations performed on the predetermined bit range. In the second group of bit flipping operations, different N+1 bits in the predetermined bit range are flipped. N is greater than or equal to 1 and less than the predetermined flipping order. In this way, the number of flipped bits can be gradually increased, more candidate bit sequences can be obtained, and decoding performance can be improved.

[0009] In some embodiments, the performing, by the decoding device, the second set of bit flipping operations includes: performing, by the decoding device, the second set of bit flipping operations on the predetermined bit range based on a determination that the candidate bit sequence corresponding to the first set of flipped bits fails a cyclic redundancy check (CRC). In this way, flipping of higher bit numbers is stopped when passing the CRC check, thereby reducing computational complexity.

[0010] In some embodiments, the determining, by the decoding device, the target bit sequence includes: determining, by the decoding device, the target bit sequence among the plurality of candidate bit sequences based on an indicator associated with the set of channel probability information values corresponding to the LDPC code. In this way, a preference can be made among the plurality of candidate bit sequences that satisfy the set of check equations, thereby determining the target bit sequence and improving decoding performance.

[0011] In some embodiments, the indicator associated with the set of channel probability information values corresponding to the LDPC code includes a number of bits that are not equal between (i) the candidate bit sequence and (ii) a hard decision bit sequence obtained by performing a hard decision on the set of channel probability information values. In this way, a preference is made among the plurality of candidate bit sequences to determine the candidate target bit sequence, thereby improving decoding performance.

[0012] In some embodiments, the base matrix of the LDPC code includes an information column region, a core check column region, and an extension check column region, and the predetermined bit range includes: a bit range corresponding to the information column region of the base matrix; or a bit range corresponding to the information column region and the core check column region of the base matrix. In this way, the bit flipping range can be reduced, thereby reducing computational complexity.

[0013] In some embodiments, the predetermined bit range includes a bit range corresponding to the information column region. The obtaining, by the decoding device, the plurality of candidate bit sequences includes: obtaining, by the decoding device, a core check bit sequence based on a flipped information bit sequence in a flipped bit sequence in the plurality of flipped bit sequences. In addition, the obtaining, by the decoding device, the plurality of candidate bit sequences includes: obtaining, by the decoding device, an extension check bit sequence by performing a bit-wise XOR in an order of the extension check column based on the flipped information bit sequence and the core check bit sequence. In addition, the obtaining, by the decoding device, the plurality of candidate bit sequences includes: obtaining, by the decoding device, a candidate bit sequence in the plurality of candidate bit sequences based on the flipped information bit sequence, the core check bit sequence, and the extension check bit sequence. In this way, the flipped information bit sequence can be quickly LDPC re-encoded to obtain the candidate bit sequence, thereby improving decoding speed.

[0014] In some embodiments, the predetermined bit range includes bit ranges corresponding to the information column region and the core check column region. The decoding apparatus obtaining the plurality of candidate bit sequences includes: the decoding apparatus performing bit XOR according to the order of the extended check columns based on the flipped information bit sequence and the core check bit sequence in the flipped bit sequence in the plurality of flipped bit sequences, to obtain an extended check bit sequence. In addition, the decoding apparatus obtains the candidate bit sequence in the plurality of candidate bit sequences based on the flipped information bit sequence, the core check bit sequence, and the extended check bit sequence. In this way, the LDPC re-encoding can be quickly performed on the flipped information bit sequence and the core check bit sequence to obtain the candidate bit sequence, and the decoding speed is improved.

[0015] In some embodiments, the base matrix of the LDPC code is composed of an information column region and a check column region, and the check column region includes a lower triangular matrix. In this way, the LDPC code design can be simplified, and the decoding calculation complexity is reduced.

[0016] In some embodiments, the check column region includes an identity matrix. In this way, fast calculation can be performed using, for example, parallel calculation, the decoding calculation complexity is reduced, and the efficiency is improved.

[0017] In some embodiments, the predetermined bit range includes a bit range corresponding to the information column region of the base matrix. In this way, the range of bit flipping can be reduced, the decoding calculation complexity is reduced, and the efficiency is improved.

[0018] In some embodiments, the decoding apparatus obtaining the plurality of candidate bit sequences includes: the decoding apparatus performing bit XOR according to the order of the check columns based on the flipped bit sequence in the plurality of flipped bit sequences, to obtain a check bit sequence. In addition, the decoding apparatus obtains the candidate bit sequence based on the flipped bit sequence and the check bit sequence. In this way, the LDPC re-encoding can be quickly performed on the flipped information bit sequence to obtain the candidate bit sequence, and the decoding speed is improved.

[0019] In some embodiments, the column weight of the information column region of the base matrix is greater than the column weight of the check column region. In this way, it can be ensured that the information column part is the column with the highest reliability, and after BP decoding iteration, only the information column needs to be flipped to achieve the effect of ordered statistic decoding (OSD), without Gaussian elimination, and the calculation efficiency is improved.

[0020] In some embodiments, the column weight includes an average column weight, a total column weight, a maximum column weight, or a minimum column weight. In this way, the column weight can be implemented in various ways, and the flexibility is improved.

[0021] In some implementations, the minimum column weight of the information column region is greater than the maximum column weight of the check column region. In this way, the column weight of any information column can be made higher than the column weight of any check column, improving the fault tolerance performance of decoding and improving the computational efficiency.

[0022] In a second aspect, an encoding method is provided. The execution subject of the method can be an encoding device or a chip applied in the encoding device. Hereinafter, the execution subject is taken as an example of the encoding device for description. In the absence of special description, the "encoding device" in the present application can refer to the encoding device itself, a component (for example, a communication module, a processor, a circuit, a chip, or a chip system, etc.) in the encoding device, or a logic module or software capable of realizing all or part of the functions of the encoding device. Hereinafter, the execution subject is taken as an example of the encoding device for description. In the method, the encoding device performs LDPC encoding based on a base matrix of a low-density parity-check (LDPC) code. The base matrix is composed of an information column region and a check column region, and the check column region includes a lower triangular matrix. In this way, the LDPC code design can be simplified, and the encoding computation complexity can be reduced.

[0023] In some implementations, the check column region includes a unit matrix. In this way, fast computation can be performed using, for example, parallel computation, the encoding computation complexity can be reduced, and the efficiency can be improved.

[0024] In some implementations, the column weight of the information column region of the base matrix is greater than the column weight of the check column region. In this way, it can be ensured that the information column part is the column with the highest reliability, and after BP decoding iteration, only the information column needs to be flipped to achieve the effect of ordered statistic decoding (OSD), without Gaussian elimination, improving the computational efficiency.

[0025] In some implementations, the column weight includes an average column weight, a total column weight, a maximum column weight, or a minimum column weight. In this way, the column weight can be implemented in multiple ways, improving flexibility.

[0026] In some implementations, the minimum column weight of the information column region is greater than the maximum column weight of the check column region. In this way, the column weight of all information columns can be made higher than the column weight of the check column, improving the fault tolerance performance of decoding and improving the computational efficiency.

[0027] In a third aspect, a decoding apparatus is provided. The decoding apparatus can be a decoding device or a chip applied in the decoding device. Unless specifically stated, the decoding apparatus in the present application can refer to the decoding device itself, a component (for example, a communication module, a processor, a circuit, a chip, or a chip system) in the decoding device, or a logic module or software capable of realizing all or part of the functions of the decoding device. Hereinafter, the decoding apparatus is taken as an example of the decoding device. The decoding apparatus includes an obtaining module configured to obtain an initial bit sequence that does not satisfy a check equation set by decoding a low-density parity-check (LDPC) code based on a belief propagation (BP) algorithm. The decoding apparatus further includes an executing module configured to obtain a plurality of flipped bit sequences by performing a plurality of bit flipping operations on a predetermined bit range of the initial bit sequence. In one bit flipping operation, at least one bit in the predetermined bit range is flipped. The decoding apparatus further includes an encoding module configured to obtain a plurality of candidate bit sequences by performing LDPC encoding on the plurality of flipped bit sequences. The decoding apparatus further includes a determining module configured to determine a target bit sequence that satisfies a predetermined condition from the plurality of candidate bit sequences as a decoding result of the LDPC code. In this way, a certain randomness is introduced by performing bit flipping in the predetermined bit range, thereby resisting the influence of noise or interference, improving decoding performance, and reducing complexity.

[0028] In a fourth aspect, an encoding apparatus is provided. The encoding apparatus can be an encoding device or a chip applied in the encoding device. Unless specifically stated, the encoding apparatus in the present application can refer to the encoding device itself, a component (for example, a communication module, a processor, a circuit, a chip, or a chip system) in the encoding device, or a logic module or software capable of realizing all or part of the functions of the decoding device. Hereinafter, the encoding apparatus is taken as an example of the encoding device. The encoding apparatus includes an encoding module configured to perform LDPC encoding based on a base matrix of a low-density parity-check (LDPC) code. The base matrix is composed of an information column region and a check column region, and the check column region includes a lower triangular matrix. In this way, the LDPC code design can be simplified, and the encoding calculation complexity can be reduced.

[0029] In a fifth aspect, a computer-readable storage medium is provided. The computer-readable storage medium stores instructions. The instructions, when executed by a communication device, cause the communication device to perform the method in the first aspect.

[0030] In a sixth aspect, a computer-readable storage medium is provided. The computer-readable storage medium stores instructions. The instructions, when executed by a communication device, cause the communication device to perform the method in the second aspect.

[0031] In a seventh aspect, a chip is provided. The chip includes a processing circuit. The processing circuit is configured to perform the method in the first aspect.

[0032] In an eighth aspect, a chip is provided. The chip includes processing circuitry. The processing circuitry is configured to perform the method in the second aspect. BRIEF DESCRIPTION OF DRAWINGS

[0033] FIG. 1A illustrates a communication system in which embodiments of the present application can be implemented.

[0034] FIG. 1B illustrates another communication system in which embodiments of the present application can be implemented.

[0035] FIG. 2 illustrates a schematic diagram of a Tanner graph related to embodiments of the present application.

[0036] FIG. 3 illustrates a schematic diagram of a cyclic shift related to embodiments of the present application.

[0037] FIG. 4 illustrates a schematic diagram of a base matrix of an LDPC code related to embodiments of the present application.

[0038] FIG. 5 illustrates another schematic diagram of a base matrix of an LDPC code related to embodiments of the present application.

[0039] FIG. 6 illustrates a processing flowchart of a decoding apparatus in embodiments of the present application.

[0040] FIG. 7 illustrates a schematic diagram of a two-part block structure of an LDPC code in embodiments of the present application.

[0041] FIG. 8 illustrates a processing flowchart of an encoding apparatus in embodiments of the present application.

[0042] FIG. 9 illustrates a schematic diagram of decoding performance in embodiments of the present application.

[0043] FIG. 10 illustrates a block diagram of an apparatus in embodiments of the present application.

[0044] FIG. 11 illustrates a schematic diagram of a structure of an apparatus that can be used to implement a decoding apparatus in embodiments of the present application.

[0045] FIG. 12 illustrates a schematic diagram of a structure of an apparatus that can be used to implement an encoding apparatus in embodiments of the present application. DETAILED DESCRIPTION

[0046] In order to make the objectives, technical solutions and advantages of the present application clearer, the following will further describe the present application in detail with reference to the accompanying drawings. The specific operation methods, function descriptions, etc. in the method embodiments can also be applied to the apparatus embodiments or system embodiments.

[0047] As described above, in various communication scenarios, low density parity check (LDPC) codes can be used, and decoding of the LDPC codes needs to be optimized.

[0048] Embodiments of the present application provide a technical solution for decoding, in which a decoding device decodes a low-density parity-check (LDPC) code based on a belief propagation (BP) algorithm, and obtains an initial bit sequence that does not satisfy a set of check equations. In addition, the decoding device obtains a plurality of candidate bit sequences based on performing a plurality of bit flipping operations on the initial bit sequence. In one bit flipping operation, at least one bit of the initial bit sequence is flipped. In addition, the decoding device determines a target bit sequence that satisfies a predetermined condition from the plurality of candidate bit sequences as a decoding result of the LDPC code. In this way, a certain randomness is introduced in the form of bit flipping, so as to resist the influence of noise or interference and improve decoding performance.

[0049] FIG. 1A shows a communication system in which embodiments of the present application can be implemented.

[0050] In embodiment 100, the communication system includes a source 105, source encoding 110, an encoding device 120 such as channel encoding, modulation 125, demodulation 130, a decoding device 140 such as channel decoding, source recovery 145, and a sink 150. The encoding device 120 performs channel encoding operations such as LDPC code. The decoding device 140 performs channel decoding operations such as LDPC code.

[0051] FIG. 1B shows another communication system in which embodiments of the present application can be implemented.

[0052] In embodiment 160, the communication system includes a network device 165 such as a base station, terminal devices 170, 175. The network device 165 and the terminal devices 170, 175 communicate through uplink and downlink 180, 185, respectively. The terminal devices 170, 175 can also communicate through sidelink 190. In embodiment 160, the encoding device 120 can be located in the network device 165, the terminal devices 170, 175, and perform LDPC encoding on the sending side of the uplink and downlink 180, 185 and the sidelink 190. The decoding device 140 can be located in the network device 165, the terminal devices 170, 175, and perform LDPC decoding on the receiving side of the uplink and downlink 180, 185 and the sidelink 190.

[0053] The wireless communication system 100, 160 in embodiments of the present application can be applied to three major application scenarios of eMBB, URLLC and eMTC, etc. of the 5G mobile communication system, or communication system scenarios such as 5G advanced, 6G, future communication network, etc.

[0054] It should be understood that the above wireless communication system can be applied to both a high frequency scenario (above 6G) such as millimeter wave and a low frequency scenario (sub 6G). Application scenarios of the wireless communication system include, but are not limited to, a fifth generation system (5G), a new radio (NR) communication system, and the like existing communication system or a future evolved public land mobile network (PLMN) system and the like.

[0055] The terminal device 170, 175 shown above can be a user equipment (UE), a terminal, an access terminal, a terminal unit, a terminal station, a mobile station (MS), a remote station, a remote terminal, a mobile terminal, a wireless communication device, a terminal agent, or a terminal device, etc. The terminal device 170, 175 can also be a communication chip with a communication module, or a vehicle with a communication function, or a vehicle-mounted device (such as a vehicle-mounted communication device, a vehicle-mounted communication chip), etc. The terminal device 170, 175 can have a wireless transceiving function, which can communicate (such as wirelessly communicate) with one or more network devices of one or more communication systems and accept network services provided by the network devices, where the network devices include, but are not limited to, the network device 165 shown in the figure.

[0056] Among them, the terminal device 170, 175 can be a cellular phone, a cordless phone, a session initiation protocol (SIP) phone, a wireless local loop (WLL) station, a personal digital assistant (PDA) device, a handheld device with wireless communication function, a computing device, or other processing device connected to a wireless modem, a vehicle-mounted device, a wearable device, a terminal device in a 5G network, or a terminal device in a future evolved PLMN network, etc.

[0057] The terminal devices 170, 175 can specifically be a mobile phone, a pad, a computer with wireless transceiver function, a virtual reality (VR) terminal, an augmented reality (AR) terminal, a wireless terminal in industrial control, a wireless terminal in self driving, a wireless terminal in remote medical, a wireless terminal in smart grid, a wireless terminal in transportation safety, a wireless terminal in smart city, a wireless terminal in smart home, and the like.

[0058] In addition, the terminal devices 170, 175 can be deployed on land, including indoors or outdoors, handheld or vehicle-mounted; the terminal devices 170, 175 can also be deployed on water (such as ships, etc.); the terminal devices 170, 175 can also be deployed in the air (such as airplanes, balloons, and satellites, etc.). The network device 165 can be an access network device (or an access network site). The access network device refers to a device with network access function, such as a radio access network (RAN) base station and the like. For example, the network device 165 of the access network device can specifically include a base station (BS), or include a base station and a radio resource management device for controlling the base station, etc. The network device 165 of the access network device can also include a relay station (relay device), an access point, and a base station in a 5G network or an NR base station, a base station in a future evolved PLMN network, etc. The access network device (165) can be a wearable device or a vehicle-mounted device. The network device 165 of the access network device can also be a communication chip with a communication module.

[0059] For example, the network device 165 such as a cellular system access network device includes but is not limited to: a base station (gnodeB, gNB) in 5G, an evolved node B (eNB) in a long term evolution (LTE) system, a radio network controller (RNC), a radio controller under a cloud radio access network (CRAN) system, a base station controller (BSC), a home base station (for example, a home evolved nodeB, or a home node B, HNB), a baseband unit (BBU), a transmitting and receiving point (TRP), a transmitting point (TP), a mobile switching center, and can also be an evolved (eNB or eNodeB) in LTE, and can also be a base station device in a future 5G network or an access network device in a future evolved PLMN network, and can also be a wearable device or a vehicle-mounted device.

[0060] In some deployments, a network device 165, e.g., a cellular system access network device, can include a centralized unit (CU) and a distributed unit (DU). The network device can also include an active antenna unit (AAU). The CU implements part of the functionality of the network device, and the DU implements part of the functionality of the network device, e.g., the CU is responsible for handling non-real-time protocols and services, implements radio resource control (RRC), and functions of the packet data convergence protocol (PDCP) layer. The DU is responsible for handling physical layer protocols and real-time services, implements functions of the radio link control (RLC) layer, the media access control (MAC) layer, and the physical (PHY) layer. The AAU implements part of the physical layer processing functions, radio frequency processing, and related functions of the active antenna. Since information at the RRC layer eventually becomes or is transformed from information at the PHY layer, under this architecture, high layer signaling, such as RRC layer signaling, can also be considered as being transmitted by the DU or by the DU + AAU. It can be understood that a network device can be a device that includes one or more of a CU node, a DU node, and an AAU node. Further, a CU can be divided into a network device in a radio access network (RAN) or a network device in a core network (CN), which is not limited in the present application. Examples of network devices include, but are not limited to, a Node B (NodeB or NB), an evolved Node B (eNodeB or eNB), a next generation Node B (gNB), a transmission reception point (TRP), a remote radio unit (RRU), a radio head (RH), a remote radio head (RRH), an IAB node, a low power node such as a femto node, a pico node, a reconfigurable intelligent surface (RIS), a network controlled relay, etc. A network device 165, e.g., a base station, can contain a baseband unit (BBU) and a remote radio unit (RRU). The BBU and the RRU can be placed in different places, e.g., RRU pull-out, placed in a high traffic area, and the BBU placed in a central machine room. The BBU and the RRU can also be placed in the same machine room. The BBU and the RRU can also be different components under one rack.

[0061] In addition, the network device 165, for example, a cellular system access network device, can be connected to a core network (CN) device, which can be used to provide core network services for the access network device 165 and the terminal devices 170, 175. The core network device can correspond to different devices under different systems. For example, in 3G, the core network device can correspond to a serving GPRS support node (SGSN) and / or a gateway GPRS support node (GGSN) of a general packet radio service (GPRS). In 4G, the core network device can correspond to a mobility management entity (MME) and / or a serving gateway (S-GW). In 5G, the core network device can correspond to an access and mobility management function (AMF), a session management function (SMF), a user plane function (UPF), etc.

[0062] Embodiments 100, 160 can be used for various application scenarios such as enhanced mobile broadband (eMBB), ultra-reliable low latency communications (URLLC), and enhanced machine-type communication (eMTC).

[0063] Low-density parity-check (LDPC) code is a channel coding scheme very close to the Shannon limit, with good performance and low complexity, and has been determined by 3GPP as a 5G data channel coding scheme.

[0064] The encoding manner of the LDPC code is to use a generator matrix. The LDPC code has a quasi-cyclic (QC) structure, and by setting the shift amount of each block, bad structures such as short cycles are avoided, and the code distance is improved. The decoding algorithms of the LDPC code currently mainly include Min-Sum (MS) and Belief Propagation (BP) decoding algorithms. The theoretical performance of the BP decoding algorithm is better, but the information storage amount is large, and the m c→vThe calculation is complicated and is not conducive to hardware implementation, so Offset-MS and Normalized-MS decoding algorithms are used in actual communication systems at present. Offset-MS, Normalized-MS and other MS algorithms can be regarded as a simplified algorithm of the BP algorithm.

[0065] The QC-LDPC code actually used is represented by a base matrix BG, and the elements in the BG are 0 or 1. The 1 in the base matrix BG is extended to a cyclic shift matrix, and the 0 is extended to a 0 matrix of the corresponding size. After the extension, the check matrix is obtained. The BG graph model of the QC-LDPC code is BG=(X, Y, F), wherein X corresponds to the variable of the BG graph, Y corresponds to the check equation, and F is the edge relationship thereof. After QC expansion with a lifting factor of Z c , the Tanner graph is obtained, that is, a bipartite graph G=(V, C, E), wherein V is a variable node, C is a check node, and E is the edge relationship thereof.

[0066] For example, in the embodiment 200 of FIG. 2, the variable nodes are V1(235), …, V12(290), and the check nodes are C1(205), …, C6(230). There is an edge relationship 295 between C1(230) and V1(235). The number of variable nodes, the number of check nodes and the edge relationship in the embodiment 200 are exemplary and do not constitute a limitation on the present application. The number of variable nodes corresponds to the number of rows of the check matrix N=|V|=Z c |X|, the number of check nodes corresponds to the number of rows of the check matrix M=|C|=Z c |Y|, and the number of non-zero elements of the check matrix is |E|=Z|F|.

[0067] The BG can also be written in the form of a matrix as H BG . Based on the base matrix H BG and the lifting value Zc (lifting size), the base matrix H BG can be extended to a complete check matrix for encoding or decoding. Zc can also be referred to as an extension factor, a lifting factor, an extension value, an extension coefficient, a lifting size, etc.

[0068] The lifting process is to lift the elements in the matrix H BG to a Zc×Zc square matrix, wherein 0 is lifted to a Zc×Zc 0 matrix, and 1 is lifted to a matrix that is a unit matrix right-circu larly shifted by P i,j , wherein P i,jis the shifting value (SV value) corresponding to the ith row and jth column. The variable node, check node, and edge relationship of the promoted complete check matrix can also be shown in FIG. 2, where the number of variable nodes, check nodes, and edge relationships are exemplary and do not limit the present application.

[0069] FIG. 3 shows a schematic diagram of cyclic shift related to embodiments of the present application. The results of cyclically shifting a 4*4 unit matrix right by 1, 2, and 3 times are shown as 305, 310, and 315, respectively.

[0070] The base graphs of the 5G LDPC code are BG1 and BG2, which have a common matrix structure, as shown in embodiment 400 in FIG. 4. In embodiment 400, part A corresponds to the information column region of the high code rate, and part B corresponds to the core check region of the high code rate. Part C is a 0 matrix, and part D is the incremental redundancy part of the matrix, corresponding to the low code rate matrix, and part E is the incremental redundancy region, which is a unit matrix structure. The base matrix takes values of 0 and 1, where a value of 0 represents an empty element, and a value of 1 represents an edge in the base graph, or is associated with a corresponding check node and a corresponding variable node.

[0071] Related to embodiments of the present application, a flexible rate QC-LDPC code can be used, and the entire matrix is designed according to the lowest code rate. When different code rates need to be supported, the upper left part of the matrix is intercepted for use, as shown in FIG. 4, where the A and B regions constitute the highest code rate matrix. In 5G, the number of columns in part A of BG1 is 22, the number of columns in part B is 4, the puncturing column is 2, and the supported code rate is 22 / (22+4-2) = 11 / 12 ≈ 0.917.

[0072] When lower code rates need to be supported, one row and one column are added to the matrix region for use, until the lowest code rate. As shown in embodiment 500 of FIG. 5, based on the high code rate region, one row and one column are sequentially added in the check region with a column weight of 1, and one row is sequentially added in the incremental redundancy region, thereby obtaining an LDPC code with a lower code rate, until the lowest code rate. For example, the dashed line of 505 represents the intercepted matrix region under different code rates.

[0073] Related to embodiments of the present application, a belief propagation decoding algorithm or a min-sum decoding algorithm is used. Let the log-likelihood ratio (LLR) value received by the decoding device 140 be y, and the decoding is performed in an iterative manner. In the lth iteration, let the passing information from the variable node to the check node be The passing information from the check node to the variable node is Let Then the variable node passes information in the following manner:

[0074] where y v is the value corresponding to variable node v in the received LLRs.

[0075] In the BP decoding process, the information passed from check node c to variable node v is

[0076] In the min-sum decoding algorithm, formula (2) can be simplified to compute the approximate amplitude by

[0077] After each iteration, all v node information is summarized as and the hard decision is the symbol t v .

[0078] When the number of iterations reaches the upper limit, or t v can make all check equations in the check equation set pass, then the decoding terminates, and t v is taken as the result of decoding.

[0079] The belief propagation decoding method has good performance and complexity advantage on long code, low density LDPC code, but is low in efficiency on short code, especially on short circle, dense matrix. The belief propagation algorithm is easy to fall into a certain trap set and cannot be correctly decoded, so it has error floor, and is difficult to adapt to ultra-high reliability communication.

[0080] In relation to the embodiments of the present application, the GRAND bit flipping decoding can have a check matrix H and received LLR values, and the symbol w can be obtained by hard judging the LLR values. The GRAND decoding can adopt the following process.

[0081] 1. The w is checked, and if the result of H*w is all 0, the check passes, and the decoding ends.

[0082] 2. If the check fails, a certain position of w is randomly flipped (i.e. 0->1 or 1->0), the w1 after flipping is checked, and if the check passes, the decoding ends, otherwise another position of w is flipped, and checked, until a flipping vector that passes the check is found, or any position of w is flipped once.

[0083] 3. All positions of w are flipped once, and in the case that the check fails, any two positions of w are flipped, and it is judged whether the check passes.

[0084] 4. After all two-position flipping combinations are tried, enter the combination of flipping 3, 4, 5, … positions, and flip until the correct result of the check is found.

[0085] Therefore, the GRAND decoding is a decoding method that finds the codeword closest to the received symbol by continuously trying to flip 1, 2, 3, … symbols.

[0086] The advantage of the GRAND decoding is that it only needs a check matrix and can be used for any code, and can always find the codeword closest to the received symbol in Hamming distance as the decoding result. For example, TBCC and TURBO codes in 4G, Polar and LDPC in 5G, GRAND can quickly obtain the decoding result for a very high code rate or a very short code length. However, when the code rate is slightly reduced or the code length is slightly increased, the average complexity and maximum complexity of the decoding increase by a combination number level. Therefore, the application range is limited, and it is not suitable for current mainstream communication systems.

[0087] FIG. 6 shows a processing flowchart of a decoding device in an embodiment of the present application. In flowchart 600, at 610, the decoding device 140 decodes a low-density parity-check (LDPC) code based on a belief propagation (BP) algorithm to obtain an initial bit sequence that does not satisfy a check equation set. At 620, the decoding device 140 performs a plurality of bit flipping operations on a predetermined bit range of the initial bit sequence to obtain a plurality of flipped bit sequences. In one bit flipping operation, at least one bit in the predetermined bit range is flipped. At 630, the decoding device 140 performs LDPC encoding on the plurality of flipped bit sequences to obtain a plurality of candidate bit sequences. At 640, the decoding device 140 determines a target bit sequence that satisfies a predetermined condition from the plurality of candidate bit sequences as a decoding result of the LDPC code. The belief propagation algorithm can include a BP algorithm, a Min-Sum algorithm, etc. The initial bit sequence can be a bit sequence obtained after hard decision of values of variable nodes of the BP decoding. In this way, a certain randomness is introduced by performing bit flipping in the predetermined bit range, so as to resist the influence of noise or interference, improve decoding performance, and reduce complexity.

[0088] It can be seen that the embodiments of the present application can use a random noise guessing decoding method based on belief propagation decoding. As an example, this method can use the following steps or operations to specifically implement the flowchart 600.

[0089] In step 1, the decoding device 140 receives channel LLR values y, and obtains a decoding result t after BP (or Min-sum) decoding. The code length of t can be N, of which the first k bits are information bits. If t cannot satisfy all check equations in the check equation set, t is set as an initial bit sequence, that is, the current decoding result. The decoding device 140 records the number of bits x1 in which the symbol of t is not equal to the hard decision symbol of the channel LLR value, and performs the following process.

[0090] In step 2, the decoding device 140 flips the first bit in t in the predetermined bit range, and let the flipped symbol be t', and uses the bits in t' in the predetermined bit range to perform LDPC encoding, and thus obtains the whole codeword bits t".

[0091] In some implementations, the decoding device 140 determines the target bit sequence in the following manner. The decoding device 140 determines the target bit sequence among the plurality of candidate bit sequences based on an index associated with the set of channel probability information values corresponding to the LDPC code. The decoding device 140 receives the channel LLR values y corresponding to the set of channel probability information values corresponding to the LDPC code. In this way, in the presence of multiple candidate bit sequences satisfying the set of check equations, a preference can be made among them, and thus the target bit sequence is determined, improving the decoding performance.

[0092] In some implementations, the index associated with the set of channel probability information values corresponding to the LDPC code comprises the number of bits that are not equal between (i) the candidate bit sequence, and (ii) a hard decision bit sequence obtained by performing hard decision on the set of channel probability information values. In this way, a preference is made among the candidate bit sequences to determine the candidate target bit sequence, improving the decoding performance.

[0093] In step 3, the decoding device 140 records the number of bits x'1 that are not equal between t and the hard decision of the channel LLR values, and performs whether to update the decoding result t to t" according to the decision rule, while updating x1 to x'1.

[0094] In step 4, the decoding device 140 flips the second, third, fourth, and so on bits in t in the predetermined bit range, and repeats steps 2 and 3.

[0095] In some implementations, the decoding device 140 performs the multiple bit flipping operations in the following manner. The decoding device 140 obtains a first set of flipped bit sequences based on performing a first set of bit flipping operations on the predetermined bit range. In the first set of bit flipping operations, different N bits in the predetermined bit range are flipped. In addition, the decoding device 140 obtains a second set of flipped bit sequences based on performing a second set of bit flipping operations on the predetermined bit range. In the second set of bit flipping operations, different N+1 bits in the predetermined bit range are flipped. N is greater than or equal to 1 and less than the predetermined flipping order. In this way, the number of flipped bits can be increased step by step, and more candidate bit sequences can be obtained, improving the decoding performance.

[0096] In step 5, the decoding device 140 selects 2-bit flips in t in the predetermined bit range, and repeats steps 2, 3, and so on until the selection of 2-bit combinations is completed.

[0097] The decoding device 140 can perform the second set of bit flipping operations in the following manner. The decoding device 140 performs the second set of bit flipping operations on the predetermined bit range based on determining that the candidate bit sequence corresponding to the first set of flipped bits fails the cyclic redundancy check (CRC). In this way, flipping of higher numbers of bits is stopped when the CRC check passes, thereby reducing computational complexity.

[0098] In step 6, the decoding device 140 selects t 3, 4, 5…O bit flips in the predetermined bit range, and repeats step 2, 3 until the combination of the number of bits is selected. O is the maximum flipping order, or the predetermined flipping order. In the embodiment of the present application, the sequence obtained after each flipping of the initial bit sequence t corresponds to a candidate bit sequence.

[0099] In the embodiment of the present application, the number of bits flipped in one bit flipping operation is greater than or equal to 1, and less than or equal to the predetermined flipping order O. In this way, multiple bits can be flipped under the condition that the decoding delay is allowed, thereby improving decoding performance. In the embodiment of the present application, the predetermined flipping order O is determined by the decoding device 140, or indicated at the physical layer, for example, indicated by the encoding device 120 at the physical layer. In this way, decoding flexibility can be improved.

[0100] In step 7, the decoding device 140 retains the current decoding result t as the final decoding result.

[0101] In the embodiment of the present application, the decoding method of the random flipping noise described above has complexity and error correction performance depending on the maximum flipping order O, and the maximum flipping order is determined by the BER (bit error rate) of the received symbol. The complexity of directly flipping the symbol using the channel LLR is high, and the performance is poor. After BP iteration, even if there is no way to obtain the correct codeword, the BER can be greatly reduced, and the random flipping based on this can obtain high-order performance under the condition of low maximum flipping order.

[0102] Under the same limitation of the maximum flipping order O, the efficiency of the method of flipping bits in the predetermined bit range and then determining all the codeword bits is much higher than that of directly flipping the number of codewords. The method in the embodiment described above can include all the flipping results of the traditional technology GRAND. Therefore, the performance can be consistent with or exceed that of the traditional scheme.

[0103] Those skilled in the art can understand that the BP decoding can also be a Min-Sum decoding, offset-Min-Sum, or scale-Min-Sum decoding method, which is not limited in the present application.

[0104] In the embodiments of the present application, the predetermined bit range can be refined, thereby optimizing the decoding performance of the LDPC code.

[0105] In the embodiments of the present application, the base matrix of the LDPC code can adopt the block mode shown in FIG. 4. Details of each block are described as follows. The LDPC base matrix 405 can be a matrix of X rows by Y columns, and the LDPC base matrix includes a sub-matrix A, a sub-matrix B, a sub-matrix C (the C region is a full 0 matrix), a sub-matrix D, and a sub-matrix E. The E region is a lower triangular matrix, having 1 elements only at the diagonal line and below, and 0 elements at other positions. Further, the E region can be an identity matrix, i.e., having 1 elements only at the diagonal line, and 0 elements at other positions. The sub-matrix A is the 1st-x1th row and the 1st-y1th column of the LDPC base matrix 405, the sub-matrix B is the 1st-x1th row and the y1+1th-y2th column of the LDPC base matrix 405, the sub-matrix C is the 1st-x1th row and the y2+1th-Yth column of the LDPC base matrix 405, the sub-matrix D is the x1+1th-Xth row and the 1st-y2th column of the LDPC base matrix 405, and the sub-matrix E is the x1+1th-Xth row and the y2+1th-Yth column of the LDPC base matrix 405, 1≤x1≤X, 1≤y1≤y2≤Y, x1, X, y1, y2, Y are all integers.

[0106] In the embodiments of the present application, for the base matrix 405, the 1st-y1th column is the information column, the y1+1th-y2th column is the core check column, the 1st-y2th column is referred to as the core column, and the y2+1th-Yth column is the extended check column.

[0107] In the embodiments of the present application, the base matrix 405 of the LDPC code includes an information column region, a core check column region, and an extended check column region. The predetermined bit range includes a bit range corresponding to the information column region of the base matrix 405, or a bit range corresponding to the information column region and the core check column region of the base matrix. In this way, the bit flipping range can be reduced, and the computational complexity can be reduced.

[0108] In the embodiments of the present application, the predetermined bit range includes a bit range corresponding to the information column region and the core check column region. The decoding device 140 can obtain a plurality of candidate bit sequences in the following manner. The decoding device 140 performs bit XOR according to the order of the extended check column based on the flipping information bit sequence and the core check bit sequence in the flipping bit sequence in the plurality of flipping bit sequences, to obtain an extended check bit sequence. In addition, the decoding device 140 obtains a candidate bit sequence in the plurality of candidate bit sequences based on the flipping information bit sequence, the core check bit sequence, and the extended check bit sequence. In this way, the flipping information bit sequence and the core check bit sequence after flipping can be quickly LDPC re-encoded to obtain the candidate bit sequence, thereby improving the decoding speed.

[0109] Specifically, in the embodiment of the present application, the predetermined bit range is defined as the core columns, i.e., the 1st-y2 columns in FIG. 4, which includes the information columns and the core check columns. The bit flipping is only performed in this range, and the process of obtaining t" from the flipped symbol bit t' can be the process of determining the extension check bits. Since the E region of the base matrix 405 is a lower triangular region, the extension check bits can be determined in the order corresponding to the bits in the y2+1-Y columns, i.e., the LDPC re-encoding process is completed, and the candidate bit sequence is obtained. The advantage of this implementation is that the process of obtaining the candidate codeword bit sequence from the bits in the predetermined bit range is relatively simple, and can be implemented by simply performing XOR in the order corresponding to the extension check bits, thereby saving the calculation amount and improving the calculation efficiency. Furthermore, if the E region of the base matrix 405 is a unit matrix, the extension check bit sequence can be obtained by using parallel calculation, thereby further saving the calculation amount and improving the calculation efficiency.

[0110] In some implementations, the predetermined bit range includes a bit range corresponding to the information column region. The decoding apparatus 140 can obtain the plurality of candidate bit sequences by the following manner. The decoding apparatus 140 obtains a core check bit sequence based on a flipped information bit sequence in the flipped bit sequence in the plurality of flipped bit sequences. In addition, the decoding apparatus 140 obtains an extension check bit sequence by performing bit XOR in the order of the extension check columns based on the flipped information bit sequence and the core check bit sequence. Furthermore, the decoding apparatus 140 obtains a candidate bit sequence in the plurality of candidate bit sequences based on the flipped information bit sequence, the core check bit sequence, and the extension check bit sequence. In this way, the flipped information bit sequence can be quickly LDPC re-encoded to obtain the candidate bit sequence, thereby improving the decoding speed.

[0111] Specifically, in the embodiment of the present application, the predetermined bit range is defined as the information columns, i.e., the 1st-y1 columns in FIG. 4. At this time, the decoding apparatus 140 first obtains the core check bits corresponding to the y1+1-y2 columns of the base matrix 405, and then determines the extension check bits in the order corresponding to the bits in the y2+1-Y columns, i.e., the y2+1-Y columns of the base matrix 405. In this way, the LDPC re-encoding process is completed, and the candidate bit sequence is obtained. The advantage of this implementation is that the flipped bit range can be further reduced, and the complexity is reduced, while the process of obtaining all the codeword bits from the information bits in the predetermined bit range will slightly increase the complexity.

[0112] In the embodiment of the present application, the block structure of the LDPC code is not the 5-block form in FIG. 4, but a simpler 2-block manner, as shown in FIG. 7.

[0113] In the embodiment of the present application, the base matrix of the LDPC code is composed of an information column region and a check column region, and the check column region includes a lower triangular matrix. In this way, the LDPC code design can be simplified, and the decoding calculation complexity can be reduced.

[0114] Specifically, in the embodiment 700, the LDPC base matrix 705 is a matrix of T rows and Z columns, and the matrix is divided into two regions. The A1 region is a region corresponding to all information columns, i.e., all T rows and the first z1 columns. The B1 region is a region corresponding to all check columns, i.e., all T rows and the z1+1 to Z columns, wherein the B1 region is a lower triangular matrix.

[0115] In the embodiment of the present application, the predetermined bit range includes a bit range corresponding to the information column region of the base matrix 705. In this way, the bit flipping range can be reduced, the decoding calculation complexity can be reduced, and the efficiency can be improved.

[0116] In the embodiment of the present application, the decoding device 140 can obtain the plurality of candidate bit sequences in the following manner. The decoding device 140 performs bit XOR in the order of the check columns based on the flipping bit sequence in the plurality of flipping bit sequences, to obtain a check bit sequence. In addition, the decoding device 140 obtains the candidate bit sequence based on the flipping bit sequence and the check bit sequence. In this way, the LDPC re-encoding can be quickly performed on the flipped information bit sequence to obtain the candidate bit sequence, and the decoding speed can be improved.

[0117] In this implementation, the predetermined bit range is defined as the information columns, i.e., the first z1 columns of the base matrix 705. At this time, the LDPC re-encoding is performed in the order of the bits corresponding to the z1+1 to Z columns to determine the complete codeword bits. The advantage of this implementation is that the flipping bit range can be further reduced, the complexity can be reduced, and since the coding structure is simplified, the process of obtaining all the codeword bits from the bits in the predetermined bit range does not increase any additional complexity.

[0118] In the embodiment of the present application, the column weight of the information column region of the base matrix is greater than the column weight of the check column region. In this way, it can be ensured that the information column part is the column with the highest reliability, and after the BP decoding iteration, only the flipping in the information column is needed, i.e., the effect of the ordered statistic decoding (OSD) can be achieved, and the Gaussian elimination is not needed, thereby improving the calculation efficiency.

[0119] In the embodiment of the present application, the column weight includes an average column weight, a total column weight, a maximum column weight, or a minimum column weight. In this way, the column weight can be implemented in multiple ways, and the flexibility can be improved.

[0120] In the embodiments of the present application, the minimum column weight of the information column region is greater than the maximum column weight of the check column region. In this way, the column weight of any information column is higher than that of any check column, improving the fault tolerance performance of decoding and improving the calculation efficiency.

[0121] Specifically, in the base matrix 705, the column weight of the A1 region is greater than that of the B1 region. The column weight can be the average column weight, the total column weight, or the maximum column weight, the minimum column weight, or the minimum column weight of the A1 region is greater than the maximum column weight of the B1 region. The advantage of this implementation is that the information column part can be guaranteed to be the column with the highest reliability, and after BP decoding iteration, only the information column needs to be flipped to achieve the OSD effect, without Gaussian elimination, greatly improving the hardware efficiency.

[0122] In the embodiments of the present application, the check column region includes an identity matrix. In this way, fast calculation can be performed using, for example, parallel calculation, reducing the decoding calculation complexity and improving the efficiency. Specifically, in the base matrix 705, the B1 region is an identity matrix, and at this time, all code word bits can be obtained from the preset range of bits in a completely parallel manner to improve the efficiency.

[0123] Corresponding to the 2-region base matrix of FIG. 7, the LDPC encoding side also adopts a corresponding encoding method.

[0124] FIG. 8 shows a processing flowchart of an encoding device in the embodiments of the present application. In flowchart 800, at 810, the encoding device 120 performs LDPC encoding based on a base matrix of a low-density parity-check (LDPC) code. The base matrix is composed of an information column region and a check column region, and the check column region includes a lower triangular matrix. In this way, the LDPC code design can be simplified, and the encoding calculation complexity can be reduced.

[0125] FIG. 9 shows a schematic diagram of decoding performance in the embodiments of the present application. Specifically, the embodiment 900 is the simulation performance of LDPC decoding.

[0126] In the embodiment 900, the abscissa is the signal to noise ratio (SNR), the ordinate is the block error ratio (BLER), the code length of the simulation is 128, the code rate is 1 / 2, the code distance is 22, and the maximum number of GRAND maximum flips is 10. The curve 905 is the performance of 5-order GRAND decoding (GRAND 5), the curve 910 is the performance of 20-iteration BP decoding (BP), the curve 915 is the performance of 10-order GRAND decoding (GRAND 10), and the curve 920 is the performance of 20-iteration BP+5-order GRAND decoding (BP+GRAND 5). As can be seen from the curves, the performance from poor to good is: GRAND 5, BP, GRAND 10, and BP+GRAND 5. As can be seen from the embodiment 900, performing GRAND decoding on the result of BP can greatly improve the decoding performance of GRAND. As for the calculation complexity, the complexity of 20-iteration BP is 300,000 basic operations, the number of flips of GRAND 5-order is 150,000, the number of flips of GRAND 10-order is 185,000, and the actual once GRAND flip further includes the complexity of verification. Even without counting this complexity, the complexity of BP+GRAND 5 is far lower than that of GRAND 10 (about 1 / 4).

[0127] FIG. 10 is a block diagram that can be used to implement a device 1000 according to some embodiments of the present application. The encoding device 120, the decoding device 140 can be implemented in the device 1000, for example can be a part of the device 1000. The encoding device 120, the decoding device 140 can be implemented as a single chip, or a combination of several chips, or as hardware circuitry, or partially as hardware circuitry and partially as software, firmware or other forms, which the present application does not limit. In some embodiments, the device 1000 can be an element of a communication network infrastructure, such as a base station (e.g., NodeB, evolved Node B (eNodeB or eNB), next generation NodeB (sometimes referred to as gNodeB or gNB), home subscriber server (HSS), gateway (GW), such as packet gateway (PGW) or serving gateway (SGW), or various other nodes or functions within a core network (CN) or a public land mobile network (PLMN). In other embodiments, the device 800 can be a device connected to network infrastructure over a wireless interface, such as a mobile phone, smartphone or other such device that can be classified as user equipment (UE). In some embodiments, the device 1000 can be a machine type communications (MTC) device (also known as a machine-to-machine (M2M) device), or another such device that can be classified as a UE, although not providing direct services to a user. In some embodiments, the device 1000 can be a road side unit (RSU), a vehicle UE (V-UE), a pedestrian UE (P-UE) or an infrastructure UE (I-UE). In some scenarios, the device 800 can also be referred to as a mobile device, a term intended to reflect a device connected to a mobile network, regardless of whether the device itself is designed or capable to move. Particular devices can utilize all or only a subset of the components shown, and the level of integration can vary from device to device. Furthermore, a device 800 can contain multiple instances of a component, such as multiple processors, memories, transmitters, receivers, etc.

[0128] The device 1000 generally includes a processor 1002, such as a central processing unit (CPU), and can further include specialized processors such as a graphics processing unit (GPU) or other such processors, a memory 1004, a network interface 1006, and a bus 1008 to connect the components of the device 1000. Optionally, the device 1000 can also include components such as a mass storage device 1010, a video adapter 1012, and an I / O interface 1016 (shown in dashed lines).

[0129] The memory 1004 can include any type of non-transitory system memory readable by the processor 1002, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), read-only memory (ROM), or a combination thereof. In one embodiment, the memory 1004 can include more than one type of memory, such as ROM for programs at boot-up, and DRAM for program and data storage for programs at execution. The bus 808 can be one or more of several types of bus architectures including a memory bus or memory controller, a peripheral bus, or a video bus.

[0130] The device 1000 can also include one or more network interfaces 1006, which can include at least one of a wired network interface and a wireless network interface. As shown in FIG. 10, the network interface 1006 can include a wired network interface for connecting to a network 1022, and can also include a wireless access network interface 1020 for connecting to other devices over a wireless link. When the device 1000 is a network infrastructure element, the wireless access network interface 1020 can be omitted for nodes or functions that are elements of the PLMN and not at the wireless edge. When the device 1000 is infrastructure at the wireless edge of the network, both wired and wireless network interfaces can be included. When the device 1000 is a wirelessly connected device, such as a user equipment, the wireless access network interface 1020 can be present and can be supplemented by other wireless interfaces, such as a WiFi network interface. The network interface 1006 allows the device 1000 to communicate with remote entities such as those connected to the network 1022.

[0131] Mass storage 1010 can include any type of non-transitory storage device configured to store data, programs, and other information and to make the data, programs, and other information accessible via bus 808. Mass storage 1010 can include, for example, one or more of a solid state drive, a hard disk drive, a magnetic disk drive, or an optical disk drive. In some embodiments, mass storage 1010 can be remote from device 1000 and can be accessed through the use of a network interface such as interface 1006. In the illustrated embodiment, mass storage 1010 is distinct from memory 1004 of which it is comprised, and mass storage 1010 can generally perform storage tasks compatible with higher latencies, but can generally provide less or no volatility. In some embodiments, mass storage 1010 can be integrated with heterogeneous memory 804.

[0132] Optional video adapter 1012 and I / O interface 1016 (shown in phantom) provide interfaces to couple device 1000 to external input and output devices. Examples of input and output devices include a display 1014 coupled to video adapter 1012 and an I / O device 1018, such as a touchscreen, coupled to I / O interface 1016. Other devices can be coupled to device 1000, and additional or fewer interfaces can be utilized. For example, a serial interface such as a Universal Serial Bus (USB) (not shown) can be used to provide interface to external devices. Those skilled in the art will appreciate that, in embodiments in which device 1000 is part of a data center, I / O interface 1016 and video adapter 1012 can be virtualized and provided over network interface 1006.

[0133] FIG. 11 is a structural schematic diagram of an apparatus 1100 according to some embodiments of the present application. In some examples, the apparatus 1100 can be used to implement the coding apparatus 140 in the embodiments of the present application. As shown in FIG. 11, the apparatus 1100 includes an obtaining module 1102, an executing module 1104, an encoding module 1106, and a determining module 1108. The apparatus 1100 can be applied to the communication system as shown in FIG. 1 and FIG. 2, and can implement any of the coding methods in the methods provided by the foregoing embodiments. Optionally, the apparatus 1100 can be physically embodied as a communication device, such as a network device or a terminal device. Alternatively, the apparatus 1100 can be other apparatus capable of implementing the functions of the communication device, such as a processor or a chip inside the communication device, etc. Specifically, the apparatus 1100 can be a programmable chip, such as a field-programmable gate array (FPGA), a complex programmable logic device (CPLD), an application specific integrated circuit (ASIC), or a system on a chip (SOC), etc.

[0134] In some embodiments, the obtaining module 1102 can be configured to obtain an initial bit sequence that does not satisfy a set of check equations based on belief propagation (BP) algorithm for decoding a low-density parity-check (LDPC) code. The executing module 1104 performs a plurality of bit flipping operations on a predetermined bit range of the initial bit sequence, and obtains a plurality of flipped bit sequences. In one bit flipping operation, at least one bit in the predetermined bit range is flipped. The encoding module 1106 performs LDPC encoding on the plurality of flipped bit sequences, and obtains a plurality of candidate bit sequences. The determining module 1108 determines a target bit sequence that satisfies a predetermined condition from the plurality of candidate bit sequences as a decoding result of the LDPC code.

[0135] In some other embodiments, the apparatus 1100 can include various other units or modules, which can be configured to perform various operations or functions described with regard to the foregoing method embodiments. The specific details can be obtained by referring to the detailed description of the foregoing method embodiments, which will not be repeated here.

[0136] FIG. 12 is a structural schematic diagram of an apparatus 1200 according to some embodiments of the present application. In some examples, the apparatus 1200 can be configured to implement the encoding apparatus 120 in the embodiments of the present application. As shown in FIG. 12, the apparatus 1200 includes an encoding module 1202. The apparatus 1200 can be applied to the communication system as shown in FIG. 1, FIG. 2, and can implement any of the encoding methods in the methods provided by the foregoing embodiments. Optionally, the apparatus 1200 can be in the form of a communication device, such as a network device or a terminal device. Alternatively, the apparatus 1200 can be another device capable of implementing the functions of the communication device, such as a processor or a chip in the communication device, etc. Specifically, the apparatus 1200 can be a programmable chip, such as a field-programmable gate array (FPGA), a complex programmable logic device (CPLD), an application specific integrated circuit (ASIC), or a system on a chip (SOC), etc.

[0137] In some embodiments, the encoding module 1202 can be configured to perform LDPC encoding based on a base matrix of a low-density parity-check (LDPC) code. The base matrix is composed of an information column region and a check column region, and the check column region includes a lower triangular matrix.

[0138] In some other embodiments, the apparatus 1200 can include various other units or modules which can be configured to perform various operations or functions described with respect to the foregoing method embodiments. The specific details can be obtained by referring to the detailed description of the foregoing method embodiments, which will not be repeated here.

[0139] It should be noted that the division of the modules in the above embodiments of the present application is illustrative, and is only a logical function division. In actual implementation, another division manner can be used. In addition, each functional unit in each embodiment of the present application can be integrated in one processing unit, or can be physically separated, or two or more units can be integrated in one unit. The integrated unit can be implemented in the form of hardware or in the form of a software functional unit.

[0140] If the integrated unit is implemented in the form of a software function unit and sold or used as an independent product, it can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application can be embodied in the form of a software product in essence or all or part of the technical solutions. The computer software product is stored in a storage medium, and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor to execute all or part of the steps of the various embodiments of the method of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (Read-Only Memory, ROM), a random access memory (Random Access Memory, RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0141] Based on the above embodiments, the embodiments of the present application also provide a computer program, which, when running on a computer, causes the computer to execute any of the methods provided in the above embodiments.

[0142] Based on the above embodiments, the embodiments of the present application also provide a computer readable storage medium, which stores a computer program. The computer program is executed by a computer to cause the computer to execute any of the methods provided in the above embodiments. The storage medium can be any available medium that can be accessed by a computer. By way of example, and not limitation, the computer readable medium can include RAM, ROM, electrically erasable programmable read-only memory (Electrically Erasable Programmable Read-Only Memory, EEPROM), compact disc read-only memory (Compact Disc Read-Only Memory, CD-ROM) or other optical disk storage, magnetic disk storage medium or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and can be accessed by a computer.

[0143] Based on the above embodiments, the embodiments of the present application also provide a chip for reading a computer program stored in a memory, implementing any of the methods provided in the above embodiments.

[0144] Based on the above embodiments, the embodiments of the present application provide a chip system, which includes a processor for supporting a computer device to implement the functions involved in the communication devices in the above embodiments. In a possible design, the chip system further includes a memory for saving the necessary programs and data of the computer device. The chip system can be composed of a chip, or can include a chip and other discrete devices.

[0145] Those skilled in the art will appreciate that embodiments of the present application can be readily used as software, hardware, or a combination of software and hardware. In a software embodiment, the present application can be implemented with computer-executable instructions, such as programs stored in memory of a computer and executed by a processor of the computer. Of course, the present application can be implemented with programs stored in memory of any computer, and executed by a processor of any computer.

[0146] The present application is described in relation to flow diagrams and / or block diagrams of methods, apparatus (systems) and computer program products according to the present application. It is understood that each block of the flow diagrams and / or block diagrams, and combinations of blocks in the flow diagrams and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flow diagrams and / or block diagrams block or blocks.

[0147] These computer program instructions can also be stored in a computer- readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instructions which implement the function specified in the flow diagrams and / or block diagrams block or blocks.

[0148] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flow diagrams and / or block diagrams block or blocks.

[0149] Obviously, numerous modifications and variations of the present application are possible in light of the above teachings. It is therefore to be understood that within the scope of the claims and their equivalents, the present application can be practiced otherwise than as specifically described.

Claims

A decoding method comprising: decoding a low-density parity-check (LDPC) code based on a belief propagation (BP) algorithm to obtain an initial bit sequence that does not satisfy a set of check equations; performing a plurality of bit flipping operations on a predetermined bit range of the initial bit sequence to obtain a plurality of flipped bit sequences, wherein in one bit flipping operation, at least one bit in the predetermined bit range is flipped; performing LDPC encoding on the plurality of flipped bit sequences to obtain a plurality of candidate bit sequences; and determining a target bit sequence that satisfies a predetermined condition among the plurality of candidate bit sequences as a decoding result of the LDPC code. The method of claim 1, wherein in one bit flipping operation, a number of the at least one bit that is flipped is greater than or equal to 1 and less than or equal to a predetermined flipping order. The method of claim 2, wherein the predetermined flipping order is determined by a decoding device or indicated at a physical layer. The method of any one of claims 1-3, wherein performing the plurality of bit flipping operations comprises: obtaining a first set of flipped bit sequences based on performing a first set of bit flipping operations on the predetermined bit range, wherein in the first set of bit flipping operations, different N bits in the predetermined bit range are flipped; and obtaining a second set of flipped bit sequences based on performing a second set of bit flipping operations on the predetermined bit range, wherein in the second set of bit flipping operations, different N+1 bits in the predetermined bit range are flipped, wherein N is greater than or equal to 1 and less than the predetermined flipping order. The method of claim 4, wherein performing the second set of bit flipping operations comprises: performing the second set of bit flipping operations on the predetermined bit range based on determining that a candidate bit sequence corresponding to the first set of flipped bit sequences fails a cyclic redundancy check (CRC). The method of any one of claims 1-5, wherein determining the target bit sequence comprises: determining the target bit sequence among the plurality of candidate bit sequences based on an indicator associated with a set of channel probability information values corresponding to the LDPC code. The method of claim 6, wherein the indicator comprises a number of bits that are not equal between (i) a candidate bit sequence and (ii) a hard decision bit sequence obtained by performing a hard decision on the set of channel probability information values. The method of any one of claims 1-7, wherein a base matrix of the LDPC code comprises an information column region, a core check column region, and an extension check column region, and wherein the predetermined bit range comprises: a bit range corresponding to the information column region of the base matrix; or a bit range corresponding to the information column region and the core check column region of the base matrix. The method of claim 8, wherein the predetermined bit range comprises the bit range corresponding to the information column region, and wherein obtaining the plurality of candidate bit sequences comprises: obtaining a core check bit sequence based on a flipped information bit sequence in a flipped bit sequence among the plurality of flipped bit sequences; ​ ​ based on the flipped information bit sequence and the core check bit sequence, performing bit XOR in an order of extended check columns to obtain an extended check bit sequence; and based on the flipped information bit sequence, the core check bit sequence, and the extended check bit sequence, obtaining a candidate bit sequence from the plurality of candidate bit sequences. The method of claim 8, wherein the predetermined bit range comprises a bit range corresponding to the information column region and the core check column region, and wherein obtaining the plurality of candidate bit sequences comprises: based on the flipped information bit sequence and the core check bit sequence in a flipped bit sequence from the plurality of flipped bit sequences, performing bit XOR in an order of extended check columns to obtain an extended check bit sequence; and based on the flipped information bit sequence, the core check bit sequence, and the extended check bit sequence, obtaining a candidate bit sequence from the plurality of candidate bit sequences. The method of any of claims 1-7, wherein a base matrix of the LDPC code is composed of an information column region and a check column region, and the check column region comprises a lower triangular matrix. The method of claim 11, wherein the check column region comprises an identity matrix. The method of any of claims 11 or 12, wherein the predetermined bit range comprises a bit range corresponding to the information column region of the base matrix. The method of claim 13, wherein obtaining the plurality of candidate bit sequences comprises: based on the flipped bit sequence, performing bit XOR in an order of check columns to obtain a check bit sequence; and based on the flipped bit sequence and the check bit sequence, obtaining the candidate bit sequence. The method of any of claims 11-14, wherein a column weight of the information column region of the base matrix is greater than a column weight of the check column region. The method of claim 15, wherein the column weight comprises an average column weight, a total column weight, a maximum column weight, or a minimum column weight. The method of claim 15, wherein a minimum column weight of the information column region is greater than a maximum column weight of the check column region. A method of encoding, comprising: performing low-density parity-check (LDPC) encoding based on a base matrix of an LDPC code, wherein the base matrix is composed of an information column region and a check column region, and the check column region comprises a lower triangular matrix. The method of claim 18, wherein the check column region comprises an identity matrix. The method of any of claims 18 or 19, wherein a column weight of the information column region of the base matrix is greater than a column weight of the check column region. The method of claim 20, wherein the column weight comprises an average column weight, a total column weight, a maximum column weight, or a minimum column weight. The method of claim 20, wherein a minimum column weight of the information column region is greater than a maximum column weight of the check column region. A decoding device, comprising: An obtaining module is configured to obtain an initial bit sequence that does not satisfy a check equation set by decoding a low-density parity-check (LDPC) code based on a belief propagation (BP) algorithm; An executing module is configured to perform a plurality of bit flipping operations on a predetermined bit range of the initial bit sequence to obtain a plurality of flipped bit sequences, wherein at least one bit in the predetermined bit range is flipped in one bit flipping operation; An encoding module is configured to perform LDPC encoding on the plurality of flipped bit sequences to obtain a plurality of candidate bit sequences; And A determining module is configured to determine a target bit sequence that satisfies a predetermined condition from the plurality of candidate bit sequences as a decoding result of the LDPC code. An encoding apparatus comprising: An encoding module is configured to perform LDPC encoding based on a base matrix of a low-density parity-check (LDPC) code, wherein the base matrix is composed of an information column region and a check column region, and the check column region includes a lower triangular matrix. A computer-readable storage medium storing instructions that, when executed by a communication device, cause the communication device to perform the method according to any one of claims 1-17. A computer-readable storage medium storing instructions that, when executed by a communication device, cause the communication device to perform the method according to any one of claims 18-22. A chip comprising processing circuitry configured to perform the method according to any one of claims 1-17. A chip comprising processing circuitry configured to perform the method according to any one of claims 18-22.

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