Array substrate, display panel and display apparatus

Abstract

An array substrate (7), a display panel and a display apparatus. The array substrate (7) comprises a plurality of pixel units arranged in an array, a plurality of scan lines (300) and a plurality of data lines (100); each pixel unit comprises a transistor (400), a common electrode (500) and a pixel electrode (200), and a first end of the transistor (400) is electrically connected to the pixel electrode (200); one scan line (300) is electrically connected to control ends of the transistors (400) in two adjacent rows of pixel units; a second end of the transistor (400) in one pixel unit is electrically connected to an adjacent data line (100); each pixel electrode (200) comprises at least one hollow area (201) extending in the column direction of the array; in the direction perpendicular to the plane where the array substrate (7) is located, the hollow areas (201) overlap the data lines (100).

Description

Array substrate, display panel and display device

[0001] This application claims priority to the Chinese patent application No. 202421755537.4 filed on July 23, 2024 with the China Patent Office, the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the technical field of display, for example, to an array substrate, a display panel and a display device. BACKGROUND

[0003] Electronic paper screen is a display screen made by using electrophoretic display technology. The control circuit on the array substrate applies driving voltage to each pixel point to achieve the effect of displaying images. As a reflective display screen, electronic paper screen can maintain the display state for a long time without continuous refreshing after image update, so the power consumption is very low. Due to its low power consumption, wide viewing angle, high contrast, eye protection and many other characteristics, electronic paper screen is increasingly widely used in many fields such as electronic price tags, electronic books and billboards.

[0004] For a bar-shaped electronic paper screen, the resolution difference between the long side and the short side is very large. Taking a bar-shaped electronic paper screen with a resolution of 1600x160 as an example, the resolution of the long side is ten times that of the short side, which is difficult to drive by one driving chip. In order to realize the driving of one driving chip to the bar-shaped electronic paper screen, a Half Gate 2 Data (HG2D) pixel architecture is usually adopted, in which two rows of pixels share one scan line and each column of pixels contains two data lines, so that the number of scan lines of the long side is halved to 800 and the number of data lines of the short side is doubled to 320. In this way, only a driving chip with a resolution greater than or equal to 800x320 needs to be selected, so that one chip can drive the bar-shaped electronic paper screen.

[0005] For a bar-shaped electronic paper screen using the HG2D pixel architecture, due to the proximity of the length of the data line and the length of the long side of the electronic paper screen, there is a contradiction between the data line capacitance load and the inter-pixel ITO gap (ITO Gap) in the conventional pixel design as follows: 1. If the data line and the pixel electrode of the ITO layer (usually Indium Tin Oxide (ITO)) are overlapped, the ITO Gap between pixels will not increase, but the capacitance load of the data line will increase by about two to five times, resulting in serious lack of pixel charging and the screen cannot display normally; 2. If the data line and the pixel electrode of the ITO layer are not overlapped, the data line capacitance load will not increase, but the ITO Gap between pixels will increase by about two to three times, resulting in horizontal stripe defects between pixels. SUMMARY

[0006] The application provides an array substrate, a display panel and a display device, the array substrate is suitable for an electronic paper screen in an HG2D structure, by optimizing the positional relationship between a data line and a pixel electrode in an HG2D pixel architecture, the contradiction between a data line capacitance load and an ITO gap between pixels is eliminated, small data line capacitance and small ITO gap are realized at the same time without affecting the display effect.

[0007] According to an aspect of the application, an array substrate is provided, comprising a plurality of pixel units arranged in an array, a plurality of scan lines extending in an array row direction, and a plurality of data lines extending in an array column direction.

[0008] The pixel unit comprises a transistor, a common electrode and a pixel electrode, the first end of the transistor is electrically connected to the pixel electrode, one of the scan lines is electrically connected to the control end of the transistor in the pixel units of adjacent two rows, and the second end of the transistor in one of the pixel units is electrically connected to the adjacent data line.

[0009] The pixel electrode comprises at least one hollow area extending in the array column direction, the size of the hollow area in the extension direction is smaller than the size of the pixel electrode in the array column direction, and the hollow area overlaps the data line in the direction perpendicular to the plane where the array substrate is located.

[0010] In some embodiments, the pixel electrode comprises a block-shaped first electrode and a strip-shaped second electrode, the hollow area is located between the first electrode and the second electrode, and the first electrode and the second electrode are electrically connected by a connecting part extending in the array row direction.

[0011] In some embodiments, in the array column direction, the sum of the size of the hollow area and the size of the connecting part is equal to the size of the first electrode.

[0012] In some embodiments, the hollow area comprises a first hollow area and a second hollow area, the first hollow area is located on the first side of the first electrode, and the second hollow area is located on the second side of the first electrode.

[0013] The second electrode comprises a first branch electrode and a second branch electrode, the first branch electrode is located on the side of the first hollow area away from the first electrode, and the second branch electrode is located on the side of the second hollow area away from the first electrode.

[0014] In some embodiments, the connecting part comprises a first connecting part and a second connecting part, the first branch electrode is connected to the first electrode through the first connecting part, and the second branch electrode is connected to the first electrode through the second connecting part.

[0015] The first connecting portion and the second connecting portion are located on the same side of the first electrode or on different sides of the first electrode.

[0016] In some embodiments, the hollowed-out region is located on a first side of the first electrode or on a second side of the first electrode.

[0017] In some embodiments, in the same row of pixel units, the hollowed-out region of each pixel electrode is located on the same side of the first electrode in the pixel electrode.

[0018] In the same column of pixel units, the hollowed-out regions of the pixel electrodes in two adjacent pixel units are located on different sides of the respective first electrodes.

[0019] According to another aspect of the present application, a display panel is provided, comprising the array substrate as described above.

[0020] In some embodiments, a counter substrate is further provided opposite to the array substrate, and an electronic paper film sheet is arranged between the array substrate and the counter substrate.

[0021] According to still another aspect of the present application, a display device is further provided, comprising the display panel as described above. BRIEF DESCRIPTION OF DRAWINGS

[0022] FIG. 1 is a schematic diagram of a pixel structure of an array substrate in an embodiment;

[0023] FIG. 2 is a schematic diagram of another pixel structure of an array substrate in an embodiment;

[0024] FIG. 3 is a schematic diagram of a 2x2 pixel array corresponding to FIG. 1;

[0025] FIG. 4 is a schematic diagram of a 2x2 pixel array corresponding to FIG. 2;

[0026] FIG. 5 is a schematic diagram of a topology structure of an HG2D pixel array corresponding to FIG. 3;

[0027] FIG. 6 is a schematic diagram of a topology structure of an HG2D pixel array corresponding to FIG. 4;

[0028] FIG. 7 is a schematic diagram of a film layer structure of an array substrate in an embodiment;

[0029] FIG. 8 is a schematic diagram of a cross-sectional structure along the section line AA' in FIG. 1;

[0030] FIG. 9 is a schematic diagram of a cross-sectional structure along the section line BB' in FIG. 2;

[0031] FIG. 10 is a schematic diagram of a cross-sectional structure along the section line CC' in FIG. 5;

[0032] FIG. 11 is a schematic diagram of a cross-sectional structure along the section line DD' in FIG. 6;

[0033] FIG. 12 is a schematic view of a pixel structure of an array substrate according to an embodiment of the present application;

[0034] FIG. 13 is a schematic view of a 2x2 pixel array corresponding to FIG. 12;

[0035] FIG. 14 is a schematic view of a topology structure of an HG2D pixel array corresponding to FIG. 13;

[0036] FIG. 15 is a schematic view of a cross-sectional structure along the section line EE' in FIG. 12;

[0037] FIG. 16 is a schematic view of a cross-sectional structure along the section line FF' in FIG. 14;

[0038] FIG. 17 is a schematic view of a pixel structure of another array substrate according to an embodiment of the present application;

[0039] FIG. 18 is a schematic view of a 2x2 pixel array corresponding to FIG. 17;

[0040] FIG. 19 is a schematic view of a topology structure of an HG2D pixel array corresponding to FIG. 18;

[0041] FIG. 20 is a schematic view of a cross-sectional structure along the section line GG' in FIG. 17;

[0042] FIG. 21 is a schematic view of a cross-sectional structure along the section line HH' in FIG. 19;

[0043] FIG. 22 is a schematic view of a structure of a display panel according to an embodiment of the present application. DETAILED DESCRIPTION

[0044] The terms "first", "second", and the like, in the description and in the claims of the present application and in the above-described drawings mean for distinguishing between like objects and do not necessarily indicate a specific order or sequence. Unless otherwise indicated herein, like numbers in the drawings indicate the same elements throughout the several drawings. The use of the terms "first", "second", and the like, are used herein for purposes of nomenclature only and are not intended to imply a specific order or sequence unless otherwise indicated herein. The terms "including", "containing", "having", and the like are used herein in the sense of "including at least the recited item, but not to the exclusion of others". The terms "coupled" and "connected" are used broadly and encompass both direct and indirect coupling or connection, and are used in their plain and ordinary sense unless otherwise indicated herein.

[0045] FIG. 1 is a schematic diagram of a pixel structure of an array substrate in an embodiment, and FIG. 2 is a schematic diagram of a pixel structure of another array substrate in an embodiment. The array substrates in the embodiments of the present application can be used in an electronic paper screen. The electronic paper screen is taken as an example for description below. Referring to FIG. 1 and FIG. 2, FIG. 1 and FIG. 2 show two HG2D pixel designs of a conventional bar-shaped electronic paper screen. The pixel units in FIG. 1 adopt an overlapping manner of a data line 1 and a pixel electrode 2 of an ITO layer, and the pixel units in FIG. 2 adopt a non-overlapping manner of the data line 1 and the pixel electrode 2 of the ITO layer. A pixel unit mainly includes a horizontal scan line 3, a vertical data line 1 (including a left data line 1-1 and a right data line 1-2), a Thin Film Transistor (TFT) 4, a Common Voltage (VCOM) 5, a pixel electrode 2 (including an ITO layer pixel electrode 2-1 and a Source / Drain (SD) layer pixel electrode 2-2), and a connection hole 6, and the like. The scan line 3 is connected to a gate of the TFT 4, and is responsible for controlling the switching of the TFT 4. The left data line 1-1 is connected to a source of the TFT 4 of the current pixel unit, and the right data line 1-2 is connected to a source of the TFT 4 of the pixel in the next row, and is responsible for transmitting a voltage signal to the pixel electrode 2. The gate, the source and the drain of the TFT 4 are connected to the scan line 3, the data line 1 and the pixel electrode 2 respectively, and are responsible for transmitting the voltage signal in the data line 1 to the pixel electrode 2 in turn. The VCOM electrode formed by the gate layer is responsible for providing a VCOM voltage. The part where the pixel electrode 2-2 formed by the SD layer and the VCOM electrode formed by the gate layer overlap with each other forms a storage capacitor (Cst), which is used to store the pixel driving voltage transmitted by the data line 1, so as to drive the particle movement in the electronic paper film. The connection hole 6 includes a via hole 6-1 formed by an Over Cover (OC) and a via hole 6-2 formed by a Passivation (PVX), and is responsible for connecting the pixel electrode 2-2 formed by the SD layer and the pixel electrode 2-1 formed by the ITO. In the conventional pixel design, the TFT 4 serving as a control switch adopts a double-gate structure. Similarly, a single-gate TFT structure or a multi-gate TFT structure can also be used.

[0046] In the 1G1D (1 Gate 1 Data) pixel structure in which one scan line and one data line are arranged in each pixel unit, in order to realize the driving and control of the pixel unit, one horizontal scan line and one vertical data line are included in each pixel unit. Therefore, two horizontal scan lines and two vertical data lines are included in a 2x2 pixel array.

[0047] Fig. 3 is a schematic diagram of a 2x2 pixel array corresponding to Fig. 1, and Fig. 4 is a schematic diagram of a 2x2 pixel array corresponding to Fig. 2. As can be seen from Fig. 3 or Fig. 4, in a 2x2 HG2D pixel array, one horizontal scan line 3 connects the TFT gate of the pixels in the upper and lower rows, and two data lines 1 in the left and right of the column of pixels connect the TFT source of the pixels in the odd and even rows respectively. Compared with the 1G1D pixel architecture, the HG2D pixel architecture can halve the number of gate lines and double the number of data lines.

[0048] Fig. 5 is a schematic diagram of the topological structure of the HG2D pixel array corresponding to Fig. 3, and Fig. 6 is a schematic diagram of the topological structure of the HG2D pixel array corresponding to Fig. 4. For the convenience of description, only the topological structure of the data line 1 and the ITO layer pixel electrode 2-1 is shown in Fig. 5 and Fig. 6. As can be seen from Fig. 5, 1, the pixel electrodes 2-1 of the adjacent two pixel units are separated from each other, the distance between the pixel electrodes 2-1 is ITO Gap, and the ITO Gap in the horizontal and vertical directions of the pixel unit is equal; 2, inside each pixel unit, the data line 1 and the pixel electrode 2-1 overlap with each other, and the overlapping part will form a coupling capacitor, which will greatly increase the capacitive load on the data line 1, about two to five times. As can be seen from Fig. 6, 1, the pixel electrodes 2-1 of the adjacent two pixel units are separated from each other, the distance between the pixel electrodes 2-1 is ITO Gap, and the ITO Gap in the horizontal direction of the pixel unit is much larger than that in the vertical direction, about two to three times. 2, inside each pixel unit, the data line and the pixel electrode 2-1 do not overlap, and there is no coupling capacitor between the data line 1 and the pixel electrode 2-1 caused by overlapping.

[0049] Figure 7 is a schematic diagram of a film layer structure of an array substrate in an embodiment. Referring to Figure 7, the film layers are arranged on a glass substrate (Glass) 10 in the order of a gate layer (Gate) 20, a gate insulation layer (GI) 30, an active layer (Active) 40, a source-drain layer (SD) 50, a planarization layer (OC) 60, a passivation layer (PVX) 70, and an ITO layer 80 from bottom to top. The Gate layer is arranged to form scan lines, gates of TFTs, and VCOM electrodes, and is usually made of conductive materials such as Mo, Al, Nd, Cu, etc.; the GI layer is arranged to insulate the Gate layer and the SD layer, and is usually made of insulating materials such as SiNx or SiO2, etc.; the Active layer is arranged to form conductive channels of TFTs, and is usually made of a-Si, p-Si, IGZO, or other semiconductor materials; the SD layer is arranged to form data lines, source-drain electrodes of TFTs, and pixel electrodes, and is usually made of conductive materials such as Mo, Al, Nd, Cu, etc.; the OC layer and the PVX layer are used to insulate the SD layer and the ITO layer, the OC layer is usually made of organic resin materials, and the PVX layer is usually made of insulating materials such as SiNx or SiO2, etc.; and the ITO layer is arranged to form pixel electrodes, and is usually made of transparent conductive materials such as ITO, etc.

[0050] Figure 8 is a schematic diagram of a cross-sectional structure along the section line AA' in Figure 1, and Figure 9 is a schematic diagram of a cross-sectional structure along the section line BB' in Figure 2. Referring to Figures 8 and 9, the data line 1-1, the TFT-1, the TFT-2, the connecting hole 6, the common electrode 5, the storage capacitor Cst, and the data line 1-2 are arranged in the order from left to right. As can be seen from Figures 8 and 9, 1, the data line 1-1 is connected to the source of the TFT-1; 2, the drain of the TFT-1 is connected to the source of the TFT-2; 3, the drain of the TFT-2 is connected to the pixel electrode 2-2 of the SD layer; 4, the pixel electrode 2-2 of the SD layer is connected to the pixel electrode 2-1 of the ITO layer through the connecting hole 6 of the OC layer and the PVX layer; and 5, the VCOM electrode 5 of the Gate layer forms the storage capacitor Cst with the pixel electrode 2-2 of the SD layer. In Figure 8, the data line and the pixel electrode of the ITO layer overlap each other. In Figure 9, the data line and the pixel electrode of the ITO layer do not overlap each other.

[0051] Figure 10 is a schematic diagram of the cross-sectional structure along the section line CC' in Figure 5, and Figure 11 is a schematic diagram of the cross-sectional structure along the section line DD' in Figure 6. Referring to Figures 10 and 11, the positional relationship between the data line 1 and the pixel electrode 2-1 of the ITO layer is shown. Referring to Figure 10, it can be seen that: 1. The line width of the data line 1 is W1, which is usually about 6 μm. The data line 1 and the pixel electrode 2-1 of the ITO layer overlap each other, and the overlapping width is W1. This overlapping width will cause the capacitance load of the data line 1 to increase substantially; 2. The width of the pixel electrode 2-1 of the ITO layer wrapping the data line 1 is S1, which is usually about 3 μm. S1 is to ensure that the pixel electrode 2-1 wraps the data line 1 in the process fluctuation; 3. The ITO Gap is G1, which is usually about 12 μm. Referring to Figure 11, it can be seen that: 1. The line width of the data line 1 is W1, which is usually about 6 μm. The data line 1 and the pixel electrode 2-1 of the ITO layer do not overlap each other; 2. The distance between the data lines 1 is S2, which is usually about 6 μm; 3. The distance between the pixel electrode 2-1 of the ITO layer and the data line 1 is S3, which is usually about 3 μm. S3 is to ensure that the pixel electrode 2-1 and the data line 1 do not overlap each other in the process fluctuation; 4. The ITO Gap is G2, where G2 = W1 x 2 + S2 + S3 x 2. Calculation shows that G2 is about 24 μm. If the ITO Gap is greater than 14 μm, horizontal stripe defects will occur between the pixels.

[0052] For a bar electronic paper screen using the HG2D pixel architecture, because the length of the data line is close to the length of the long side of the electronic paper screen, there is a contradiction between the capacitance load of the data line and the ITO Gap between the pixels in the conventional pixel design as follows: 1. If the data line and the pixel electrode of the ITO layer overlap, the ITO Gap between the pixels does not increase, but the capacitance load of the data line increases substantially, by about two to five times, thereby causing the pixel charging to be seriously insufficient and the screen to be unable to display normally; 2. If the data line and the pixel electrode of the ITO layer do not overlap, the capacitance load of the data line does not increase, but the ITO Gap between the pixels increases substantially, by about two to three times, thereby causing horizontal stripe defects to occur in the display.

[0053] To solve the above problems, the embodiment of the present application provides an array substrate, comprising a plurality of pixel units arranged in an array, a plurality of scanning lines extending along an array row direction and a plurality of data lines extending along an array column direction; the pixel unit comprises a transistor, a common electrode and a pixel electrode, the first end of the transistor is electrically connected with the pixel electrode, one scanning line is electrically connected with the control end of the transistor in the adjacent two rows of pixel units, and the second end of the transistor in one pixel unit is electrically connected with the adjacent data line; the pixel electrode comprises at least one hollow area extending along the array column direction, the size of the hollow area in the extending direction is smaller than the size of the pixel electrode in the array column direction, and the hollow area overlaps the data line in the direction perpendicular to the plane where the array substrate is located.

[0054] In the embodiment of the present application, the pixel electrode comprises at least one hollow area extending along the array column direction, the size of the hollow area in the extending direction is smaller than the size of the pixel electrode in the array column direction, and the hollow area overlaps the data line in the direction perpendicular to the plane where the array substrate is located, so that the positional relationship between the data line and the pixel electrode in the HG2D pixel architecture is optimized, the strip-shaped pixel electrode (located outside the hollow area) is arranged between the two data lines of the adjacent pixels, and the strip-shaped pixel electrode is connected with the main pixel electrode, so that the data line capacitance load is not increased, the ITO gap is not increased, the contradiction between the data line capacitance load and the ITO gap between the pixels is eliminated, and the normal display of the strip-shaped electronic paper screen is ensured.

[0055] The above is the core idea of the present application, and the specific embodiments of the present application will be described below in combination with the drawings.

[0056] FIG. 12 is a schematic diagram of a pixel structure of an array substrate provided in an embodiment of the present application, which shows a new HG2D pixel design. The pixel unit mainly includes a horizontal scan line 300, a vertical data line 100 (including a data line 100-1 and a data line 100-2), a TFT 400, a VCOM electrode 500, a pixel electrode 200 (including an ITO layer pixel electrode 200-1 and an SD layer pixel electrode 200-2), and a connection hole 600, etc. The scan line 300 is connected to the gate (control end) of the TFT 400, and is responsible for controlling the switching of the TFT 400; the data line 100-1 is connected to the source (second end) of the TFT of the current pixel unit, and the data line 100-2 is connected to the source of the TFT of the next pixel unit, and is responsible for transmitting a voltage signal to the pixel electrode 200; the gate, source and drain (first end) of the TFT 400 are connected to the scan line 300, the data line 100 and the pixel electrode 200, respectively, and are responsible for transmitting the voltage signal in the data line 100 to the pixel electrode 200 in sequence; the VCOM electrode 500 formed by the Gate layer is responsible for providing a VCOM voltage; the overlapping part between the pixel electrode 200-2 formed by the SD layer and the VCOM electrode 500 formed by the Gate layer forms a storage capacitor Cst, which is used to store the pixel driving voltage transmitted by the data line 100 to drive the electronic paper film; the connection hole 600 includes a via hole 600-1 formed by the OC layer and a via hole 600-2 formed by the PVX layer, and is responsible for connecting the pixel electrode 200-2 formed by the SD layer and the pixel electrode 200-1 formed by the ITO. In a conventional pixel unit design, the TFT control switch adopts a double-gate TFT structure, and the same can also use a single-gate TFT structure or a multi-gate TFT structure.

[0057] In the present embodiment, the hollow area 201 is arranged in the ITO layer pixel electrode 200-1, and overlaps the data line 100 in the direction perpendicular to the plane of the array substrate, so as to effectively reduce the coupling capacitance on the data line 100. In some embodiments, with reference to FIG. 12, the pixel electrode 200-1 includes a block-shaped first electrode 202 and a strip-shaped second electrode 203, and the hollow area 201 is located between the first electrode 202 and the second electrode 203, and the first electrode 202 and the second electrode 203 are electrically connected through a connection part 204 extending in the array row direction.

[0058] In some embodiments, continuing to refer to FIG. 12, the hollow area 201 includes a first hollow area 201-1 and a second hollow area 201-2, the first hollow area 201-1 is located at a first side (left side in FIG. 12) of the first electrode 202, and the second hollow area 201-2 is located at a second side (right side in FIG. 12) of the first electrode 202; the second electrode 203 includes a first branch electrode 203-1 and a second branch electrode 203-2, the first branch electrode 203-1 is located at a side of the first hollow area 201-1 away from the first electrode 202, and the second branch electrode 203-2 is located at a side of the second hollow area 201-2 away from the first electrode 202. In some embodiments, the connecting part 204 includes a first connecting part 204-1 and a second connecting part 204-2, the first branch electrode 203-1 is connected to the first electrode 202 through the first connecting part 204-1, and the second branch electrode 203-2 is connected to the first electrode 202 through the second connecting part 204-2; wherein the first connecting part 204-1 and the second connecting part 204-2 are located at the same side or different sides of the first electrode 202.

[0059] The first connecting part 204-1 shown in FIG. 12 is located at the upper side of the first electrode 202, and the second connecting part 204-2 is located at the lower side of the first electrode 202, i.e. the first connecting part 204-1 and the second connecting part 204-2 are located at different sides of the first electrode 202 is illustrative. In other embodiments, the first connecting part 204-1 and the second connecting part 204-2 can be located at the same side of the first electrode 202, for example, at the same upper side or lower side, which can be designed according to actual conditions in specific implementation. In other embodiments, the number of connecting parts between the first electrode and the second electrode can also be set to multiple, which can be designed according to actual conditions in specific implementation.

[0060] For example, in the present embodiment, according to the shape of the pixel electrode 200-1 of the ITO layer, the pixel electrode 200-1 can be divided into five parts: 1, the first electrode 202 between the data line 100-1 and the data line 100-2; 2, the first branch electrode 203-1 on the left side of the data line 101-1; 3, the first connecting part 204-1 connecting the first electrode 202 and the first branch electrode 203-1; 4, the second branch electrode 203-2 on the right side of the data line 100-2; 5, the second connecting part 204-2 connecting the first electrode 202 and the second branch electrode 203-2. In some embodiments, along the array column direction (i.e. the vertical direction in FIG. 12), the size of the hollow area 201 and the size of the connecting part 204 are equal to the size of the first electrode 202.

[0061] In the above pixel structure, only the connecting part 204 overlaps with the data line 100, by setting the width of the connecting part 204 to the minimum width that can be guaranteed by the process, the increase of the capacitive load on the data line can be effectively controlled, and the increase rate is about 6%.

[0062] FIG. 13 is a schematic diagram of a 2x2 pixel array corresponding to FIG. 12. Referring to FIG. 13, a 2x2 array corresponding to the pixel units in FIG. 12 is shown. As can be seen from FIG. 13, in the 2x2 HG2D pixel array, one horizontal scan line 300 and four vertical data lines 100 are included, the horizontal scan line 300 connects the TFT gate electrodes of the pixel units in the upper and lower rows at the same time, and the two data lines 100 on the left and right of the column of pixel units are respectively used to connect the TFT source electrodes of the pixel units in the odd and even rows. Compared with the 1G1D pixel architecture, the HG2D pixel architecture can halve the number of gate lines and double the number of data lines.

[0063] FIG. 14 is a schematic diagram of the topological structure of the HG2D pixel array corresponding to FIG. 13. For the convenience of description, only the topological structure of the data line 100 and the pixel electrode 200-1 of the ITO layer is shown in FIG. 14. As can be seen from FIG. 14, 1, the pixel electrodes 200-1 of the adjacent two pixel units are separated from each other, the distance between the pixel electrodes 200-1 is ITO Gap, and the ITO Gap in the horizontal and vertical directions of the pixel unit is equal; 2, within each pixel unit, the pixel electrode 200-1 and the data line 100 are arranged at intervals, and there is a small area of overlap between the pixel electrode 200-1 and the two data lines 100, and the overlapping areas are about 60 μm2 respectively.

[0064] FIG. 15 is a schematic diagram of the cross-sectional structure along the section line EE' in FIG. 12. Referring to FIG. 15, from left to right, there are the data line 100-1, the TFT-1, the TFT-2, the connecting hole 600, the common electrode 500, the storage capacitor Cst, and the data line 100-2. As can be seen from FIG. 15, 1, the data line 100-1 is connected to the source electrode of the TFT-1; 2, the drain electrode of the TFT-1 is connected to the source electrode of the TFT-2; 3, the drain electrode of the TFT-2 is connected to the pixel electrode 200-2 of the SD layer; 4, the pixel electrode 200-2 of the SD layer is connected to the pixel electrode 200-1 of the ITO layer through the connecting hole 600 of the OC layer and the PVX layer; 5, the VCOM electrode 500 of the Gate layer forms a storage capacitor Cst with the pixel electrode 200-2 of the SD layer. In FIG. 15, two strip-shaped pixel electrodes (the first branch electrode 203-1 and the second branch electrode 203-2 shown in FIG. 12) are provided, the data line 100-1 and the data line 100-2 are located at the hollowed-out positions of the pixel electrode 200-1, and most of the area of the data line does not overlap with the pixel electrode of the ITO layer.

[0065] FIG. 16 is a sectional view of the structure along the section line FF' in FIG. 14, which shows the positional relationship between the data line 100 and the pixel electrode 200-1 of the ITO layer. As shown in FIG. 16, 1) the width of the data line 100 is W1, which is usually about 6 μm, and the data line 100 and the pixel electrode 200-1 of the ITO layer do not overlap; 2) the distance between the pixel electrode 200-1 of the ITO layer and the data line 100 is S3, which is usually about 3 μm, and S3 is to ensure that the pixel electrode and the data line do not overlap in the process fluctuation; 3) the width of the strip-shaped pixel sub-electrode is W2, which is usually more than 10 μm; and 4) the ITO Gap is G3, which is usually about 12 μm. In the above, the width of ±2 μm is acceptable due to the process error.

[0066] In this embodiment, two strip-shaped pixel sub-electrodes are arranged between the data lines of the two pixel units, so there are three ITO Gaps. However, the width of the three ITO Gaps is about 12 μm, which is equivalent to the ITO Gap of the conventional 1G1D pixel structure, so it will not significantly increase the capacitive load of the data line, nor will it increase the impact of the ITO Gap on the display effect.

[0067] FIG. 17 is a schematic view of another pixel structure of an array substrate provided by an embodiment of the present application, which shows another new HG2D pixel design. The pixel unit mainly includes a horizontal scan line 300, a vertical data line 100 (including a data line 100-1 and a data line 100-2), a TFT 400, a VCOM electrode 500, a pixel electrode 200 (including an ITO layer pixel electrode 200-1 and an SD layer pixel electrode 200-2), and a connecting hole 600. The other basic structures and connection relationships can refer to the foregoing embodiments, which will not be described in detail here.

[0068] In this embodiment, the hollow area 201 is arranged in the pixel electrode 200-1 of the ITO layer, and the hollow area 201 overlaps the data line 100 in the direction perpendicular to the plane of the array substrate, so as to effectively reduce the coupling capacitance on the data line 100. In some embodiments, continuing to refer to FIG. 17, the pixel electrode 200-1 includes a block-shaped first electrode 202 and a strip-shaped second electrode 203, the hollow area 201 is located between the first electrode 202 and the second electrode 203, and the first electrode 202 and the second electrode 203 are electrically connected through a connecting part 204 extending in the array row direction. In some embodiments, the hollow area 201 is located on the first side of the first electrode 202 or on the second side of the first electrode 202. For example, as shown in FIG. 17, the second electrode 203 is arranged on the left side of the first electrode 202, but in actual application, the second electrode 203 can be arranged on the left side of the first electrode 202 or on the right side of the first electrode 202.

[0069] For example, in this embodiment, according to the shape of the pixel electrode 200-1 of the ITO layer, the pixel electrode 200-1 can be divided into three parts: 1, the first electrode 202 between the data line 100-1 and the data line 100-2; 2, the first branch electrode 203 on the left side of the strip-shaped pixel electrode 200-1; and 3, the connecting part 204 connecting the first electrode 202 and the second electrode 203. In the above pixel structure, only the connecting part 204 overlaps the data line 100, and by setting the width of the connecting part 204 to the minimum width that can be ensured by the process, the increase in the capacitive load on the data line can be effectively controlled, and the increase rate is about 3%.

[0070] FIG. 18 is a schematic diagram of a 2x2 pixel array corresponding to FIG. 17. Referring to FIG. 18, a 2x2 array corresponding to the pixels in FIG. 17 is shown. In some embodiments, in the same row of pixel units, the hollow area 201 of each pixel electrode is located on the same side of the first electrode 202 in the pixel electrode; in the same column of pixel units, the hollow areas 201 of the pixel electrodes in adjacent two pixel units are located on different sides of the respective first electrodes 202. As can be seen from FIG. 18, in the 2x2 HG2D pixel array, there is one horizontal scan line 300 and four vertical data lines 100, the horizontal scan line 300 simultaneously connects the TFT gates of the upper and lower two rows of pixels, and the two data lines 100 on the left and right of a column of pixels are respectively used to connect the TFT sources of the odd and even rows in the column of pixels. Compared with the 1G1D pixel architecture, the HG2D pixel architecture can halve the number of gate lines and double the number of data lines.

[0071] FIG. 19 is a schematic diagram of the topological structure of the HG2D pixel array corresponding to FIG. 18. For convenience of illustration, only the topological structure of the data line 100 and the pixel electrode 200-1 of the ITO layer is shown in FIG. 19. As can be seen from FIG. 19: 1, the pixel electrodes 200-1 of adjacent two pixel units are separated from each other, the distance between the pixel electrodes 200-1 is ITO Gap, and the ITO Gap in the horizontal and vertical directions of the pixel unit is equal; 2, within each pixel unit, the pixel electrode 200-1 and the data line 100 are arranged in a spaced manner, and there is a very small area of overlap between the pixel electrode 200-1 and a single data line 100, and the overlapping area is about 60 μm2.

[0072] Fig. 20 is a schematic diagram of a cross-sectional structure along the section line GG' in Fig. 17. Referring to Fig. 20, from left to right, there are a data line 100-1, a TFT-1, a TFT-2, a connecting hole 600, a common electrode 500 storage capacitor Cst and a data line 100-2. Referring to Fig. 20, it can be seen that: 1, the data line 100-1 is connected to the source of the TFT-1; 2, the drain of the TFT-1 is connected to the source of the TFT-2; 3, the drain of the TFT-2 is connected to the pixel electrode 200-2 of the SD layer; 4, the pixel electrode 200-2 of the SD layer is connected to the pixel electrode 200-1 of the ITO layer through the connecting hole 600 of the OC layer and the PVX layer; 5, the VCOM electrode 500 of the Gate layer forms a storage capacitor Cst with the pixel electrode 200-2 of the SD layer. In Fig. 20, there is a strip-shaped pixel electrode (the second electrode 203 in Fig. 17), the data line 100-1 and the data line 100-2 are located at the hollowed-out position of the pixel electrode 200-1, and most of the area of the data line does not overlap with the pixel electrode of the ITO layer.

[0073] Fig. 21 is a schematic diagram of a cross-sectional structure along the section line HH' in Fig. 19, which shows the positional relationship between the data line 100 and the pixel electrode 200-1 of the ITO layer. Referring to Fig. 21, it can be seen that: 1, the line width of the data line 100 is W1, which is usually about 6 μm, and the data line 100 does not overlap with the pixel electrode 200-1 of the ITO layer; 2, the distance between the pixel electrode 200-1 of the ITO layer and the data line 100 is S3, which is usually about 3 μm, and S3 is to ensure that the pixel electrode does not overlap with the data line in process fluctuation; 3, the width of the strip-shaped pixel electrode (the second electrode) is W2, which is usually more than 10 μm; 4, the ITO Gap is G3, which is usually about 12 μm, wherein, due to process error, the above width ± 2 μm is acceptable.

[0074] In the embodiment, there is a strip-shaped pixel electrode between the data lines of the two pixel units, so there are two ITO Gaps, but the width of the two ITO Gaps is about 12 μm, which is comparable to the ITO Gap of the conventional 1G1D pixel architecture, so it does not significantly increase the capacitive load of the data line, nor does it increase the impact of the ITO Gap on the display effect.

[0075] The embodiment of the present application also provides a display panel, which comprises any one of the array substrates provided in the above embodiments.

[0076] Since the display panel provided by the embodiment of the present application comprises any one of the array substrates provided in the above embodiments, it has the same or corresponding technical effects as the array substrate, which will not be described in detail here.

[0077] In some embodiments, the display panel can be an electronic paper screen, and the display panel further includes a counter substrate 9 disposed opposite to the array substrate 7, and an electronic paper film 8 is disposed between the array substrate 7 and the counter substrate 9, as shown in FIG. 22.

[0078] The embodiments of the present application further provide a display device including the display panel. The display device can be an electronic price tag, an electronic book, a billboard, etc.

Claims

1. An array substrate, comprising: a plurality of pixel units arranged in an array, a plurality of scan lines extending in an array row direction, and a plurality of data lines extending in an array column direction; each of the pixel units comprises a transistor, a common electrode and a pixel electrode, a first end of the transistor is electrically connected to the pixel electrode, one of the scan lines is electrically connected to control ends of the transistors in two adjacent rows of the pixel units, and a second end of the transistor in one of the pixel units is electrically connected to an adjacent one of the data lines; the pixel electrode comprises at least one hollow region extending in the array column direction, a dimension of the hollow region in the extending direction is smaller than a dimension of the pixel electrode in the array column direction, and the hollow region overlaps the data line in a direction perpendicular to a plane on which the array substrate is located.

2. The array substrate according to claim 1, wherein, the pixel electrode comprises a block-shaped first electrode and a strip-shaped second electrode, the hollow region is located between the first electrode and the second electrode, and the first electrode and the second electrode are electrically connected by a connecting portion extending in the array row direction.

3. The array substrate according to claim 2, wherein, in the array column direction, a sum of a dimension of the hollow region and a dimension of the connecting portion is equal to a dimension of the first electrode.

4. The array substrate of claim 2, wherein, the hollow region comprises a first hollow region and a second hollow region, the first hollow region is located at a first side of the first electrode, and the second hollow region is located at a second side of the first electrode; the second electrode comprises a first branch electrode and a second branch electrode, the first branch electrode is located at a side of the first hollow region away from the first electrode, and the second branch electrode is located at a side of the second hollow region away from the first electrode.

5. The array substrate according to claim 4, wherein, the connecting portion comprises a first connecting portion and a second connecting portion, the first branch electrode is connected to the first electrode by the first connecting portion, and the second branch electrode is connected to the first electrode by the second connecting portion; wherein the first connecting portion and the second connecting portion are located at the same side or different sides of the first electrode.

6. The array substrate of claim 2, wherein, the hollow region is located at the first side of the first electrode or at the second side of the first electrode.

7. The array substrate according to claim 6, wherein, in the same row of the pixel units, the hollow region of each pixel electrode is located at the same side of the first electrode in the pixel electrode; in the same column of the pixel units, the hollow regions of the pixel electrodes in two adjacent pixel units are located at different sides of the first electrodes in the pixel electrodes, respectively. 8.A display panel, comprising the array substrate according to any one of claims 1 to 7.

9. The display panel of claim 8, further comprising: an opposite substrate arranged opposite to the array substrate, and an electronic paper film sheet arranged between the array substrate and the opposite substrate. 10.A display device, comprising the display panel according to claim 8 or 9.

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