Methods for UCI transmission across multiple OFDM symbols based on zadoff chu sequences or m-sequences

Abstract

Various examples of embodiments described herein relate to apparatuses and methods for transmitting payload based on Zadoff Chu sequences or m-sequences. One such example of an embodiment relates to an apparatus, comprising at least one processor, and at least one memory storing instructions that, when executed by the at least one processor, cause the apparatus at least to determine a set of phase ramp values for transmission of a payload via a Zadoff Chu sequence; determine a set of root indexes based on a size of the set of phase ramp values and a size of the payload to be transmitted; generate the Zadoff Chu sequence based the determined set of root indexes; determine a phase ramp based on the determined set of phase ramp values; and transmit the generated Zadoff Chu sequence with the determined phase ramp.

Description

[0001] Methods for UCI transmission across multiple OFDM symbols based on Zadoff Chu sequences or m-sequences

[0002] Field of the Invention

[0003] The present invention relates to an apparatus, a method and a computer program product for transmitting payload such as UCI transmission across multiple OFDM symbols based on Zadoff Chu sequences or m-sequences.

[0004] Related background Art

[0005] The following meanings for the abbreviations used in this specification apply:

[0006] BW: Bandwidth

[0007] CM : Cubic Metric

[0008] DFT: Discrete Fourier Transform

[0009] DL: Downlink

[0010] DMRS: Demodulation Reference Signal

[0011] FFT: Fast Fourier Transform

[0012] FH : Frequency Hopping

[0013] MCS: Modulation and Coding Scheme

[0014] MLS: maximum length sequence (m-sequence)

[0015] NR: New Radio (5G Radio -5th generation radio)

[0016] OFDM: Orthogonal Frequency Division Multiplexing

[0017] PA: power amplifier

[0018] PAPR: Peak to Average Power Ratio

[0019] PDCCH : Physical Downlink control channel

[0020] PUCCH: Physical Uplink Control channel

[0021] PRB: Physical Resource Block

[0022] RE: Resource Element

[0023] UCI: Uplink control information

[0024] UE: User Equipment

[0025] UL: Uplink ZC: Zadoff Chu

[0026] Example embodiments, although not limited to this, relate to transmission of a payload such as UCI via PUCCH. According to the prior art, various coding schemes are applied, by which the payload can be reliably transmitted from a transmitter such as a UE to a receiver such as a gNB.

[0027] However, there are coding schemes which require a considerable amount of complexity at the receiver.

[0028] Summary of the Invention

[0029] Example embodiments address this situation aim to provide a more effective way of transmitting payload (such as UCI on PUCCH) with a reduced complexity at the receiver side.

[0030] Several aspects of the various example embodiments will be described with respect to certain aspects. These aspects are not intended to indicate key or essential features of the various example embodiments, nor are they intended to be used to otherwise limit the scope of the subject disclosure. Other features, aspects and elements of the various example embodiments will be readily apparent to a person skilled in the art in view of the subject disclosure.

[0031] According to a first aspect, an apparatus is provided which comprises at least one processor, and at least one memory storing instructions that, when executed by the at least one processor, cause the apparatus at least to determine a set of phase ramp values for transmission of a payload via a Zadoff Chu sequence; determine a set of root indexes based on a size of the set of phase ramp values and a size of the payload to be transmitted; generate the Zadoff Chu sequence based the determined set of root indexes; determine a phase ramp based on the determined set of phase ramp values; and transmit the generated Zadoff Chu sequence with the determined phase ramp. According to a second aspect, an apparatus is provided which comprises at least one processor, and at least one memory storing instructions that, when executed by the at least one processor, cause the apparatus at least to receive a sequence; perform a cross correlation with a Zadoff Chu sequence for each value of a root index of a set of root indexes; perform a fast Fourier transformation for detecting a value of a root index and a value of a phase ramp value based on peak detection, and determine the payload based on the detected value of the root index and the detected value of the phase ramp value, wherein the set of root indexes is based on a size of a set of phase ramp values and a size of the transmitted payload.

[0032] According to a third aspect, a method is provided which comprises determining a set of phase ramp values for transmission of a payload via a Zadoff Chu sequence; determining a set of root indexes based on a size of the set of phase ramp values and a size of the payload to be transmitted; generating the Zadoff Chu sequence based the determined set of root indexes; determining a phase ramp based on the determined set of phase ramp values; and transmitting the generated Zadoff Chu sequence with the determined phase ramp.

[0033] According to a fourth aspect, a method is provided which comprises receiving a sequence, performing a cross correlation with a Zadoff Chu sequence for each value of a root index of a set of root indexes, performing a fast Fourier transformation for detecting a value of a root index and a value of a phase ramp value based on peak detection, and determining the payload based on the detected value of the root index and the detected value of the phase ramp value, wherein the set of root indexes is based on a size of a set of phase ramp values and a size of the transmitted payload. According to a fifth aspect, a computer program product is provided which comprises code means for performing a method according to any one of the third and fourth aspects when run on a processing means or module.

[0034] According to a sixth aspect, an apparatus is provided which comprises means for determining a set of phase ramp values for transmission of a payload via a Zadoff Chu sequence; means for determining a set of root indexes based on a size of the set of phase ramp values and a size of the payload to be transmitted; means for generating the Zadoff Chu sequence based the determined set of root indexes; means for determining a phase ramp based on the determined set of phase ramp values; and means for transmitting the generated Zadoff Chu sequence with the determined phase ramp.

[0035] According to a seventh aspect, an apparatus is provided which comprises means for receiving a sequence, means for performing a cross correlation with a Zadoff Chu sequence for each value of a root index of a set of root indexes, means for performing a fast Fourier transformation for detecting a value of a root index and a value of a phase ramp value based on peak detection, and means for determining the payload based on the detected value of the root index and the detected value of the phase ramp value, wherein the set of root indexes is based on a size of a set of phase ramp values and a size of the transmitted payload.

[0036] Brief Description of the Drawings

[0037] These and other objects, features, details and advantages will become more fully apparent from the following detailed description of example embodiments, which is to be taken in conjunction with the appended drawings, in which: Fig. 1A shows a UE 1 according to an example embodiment,

[0038] Fig. IB shows a procedure carried out by the UE 1 according to the example embodiment,

[0039] Fig. 2A shows a gNB 2 according to an example embodiment,

[0040] Fig. 2B shows a procedure carried out by the gNB 2 according to the example embodiment,

[0041] Fig. 3 shows a further procedure carried out by the UE 1 according to an example embodiment,

[0042] Fig. 4 shows a further procedure carried out by the gNB 2 according to an example embodiment,

[0043] Fig. 5 illustrates a mapping between phase ramp values ZC sequences root indexes and UCI according to an example embodiment, and

[0044] Fig. 6 illustrates a procedure for generating a ZC sequence with a phase ramp according to an example embodiment.

[0045] Detailed Description of example embodiments

[0046] In the following, description will be made to example embodiments. It is to be understood, however, that the description is given by way of example only, and that the described example embodiments are by no means to be understood as limiting the present invention thereto.

[0047] Before describing example embodiments, in the following, a technical context of example embodiments and problems of the prior art are discussed in some more detail. As mentioned above, some example embodiments relate to UCI transmission. UCI is transmitted via PUCCH across multiple OFDM symbols, for example.

[0048] In the following, some background on NR. PUCCH format 0 is described. The physical uplink control channel (PUCCH) in NR supports multiple formats as shown in Table below, which reproduces table 6.3.2.1-1 from TS38.211 :

[0049] Particularly for PUCCH format 0, the PUCCH is limited to a maximum of 2 OFDM symbols and a number of bits equal to 2. It is important to notice that even if the length of the PUCCH can be equal to 2 OFDM symbols, the underlying low PAPR sequence (as defined in Section 5.2.2 of TS 38.211) is generated based on the allocated resources in 1 OFDM symbol and repeated in the second OFDM symbol. In other words, in NR the low PAPR sequences (e.g. for PUCCH transmission) are generated only based on the resources in 1 OFDM symbol and not based on the overall allocated resources for the PUCCH transmission (i.e. across OFDM symbols).

[0050] In addition, it is worth remarking that for PUCCH format 0, the low-PAPR sequence is generated based on a cyclic shift of a base sequence in equation below taken from Section 5.2.2 of TS 38.211), wherein the base sequence is a computergenerated sequence. r^(n) =ejmru v(n\ 0<n<M / c The cyclic shift (as derivable from Section 6.3.2.2.2 of TS38.211) is in turn determined based on the information bits to transmit, but since the PUCCH format 0 is limited to 1 PRB in 1-2 OFDM symbols (but sequence is generated in 1 OFDM symbol), the number of cyclic shifts is determined by the number of subcarriers in a RB and does not depend on the actual allocation of the sequence in time domain.

[0051] Sequence based PUCCH was suggested in R.el-17 in R.l-2008627, for example, wherein in particular it is proposed to use m-sequences for conveying UCI information (via initialization of the m-sequence). Particularly it is proposed that for a given payload size k, 2km-sequences are generated (each of length 2kand each mapped to a given UCI information), and then each sequence is truncated to fit the allocation for the PUCCH.

[0052] This approach however entails large complexity at gNB receiver and exponentially growing with payload size since more and more sequences will have to be tried to retrieve the one that was sent.

[0053] That is, using truncated sequences such as m-sequences or Gold sequences for UCI transmission over multiple OFDM symbols is not optimal as it entails large complexity at gNB receiver, since the receiver needs to cross-correlate the received signal with all of the possible sequences to retrieve the transmitted information. In addition, large truncation of sequences destroys their crosscorrelation properties and therefore it is desirable to ensure no truncation (or minimal truncation).

[0054] Thus, example embodiments aim to reduce complexity, in particular on the receiver side, and to maintain the cross-correlation properties of the used sequences.

[0055] In the following, a general overview of some example embodiments is described by referring to Figs. 1A, IB, 2A, 2B, 3 and 4.

[0056] Fig. 1A shows a UE 1 according to the present example embodiment. The UE 1 is an example for an apparatus, which may be or be a part of a user equipment, for example. A procedure carried out by the UE 1 is illustrated in Fig. IB. The UE 1 shown in Fig. 1A comprises at least one processor 11 and at least one memory 12 storing instructions that, when executed by the at least one processor 11, cause the apparatus to: determine a set of phase ramp values for transmission of a payload via a Zadoff Chu sequence (Sil in Fig. IB), determine a set of root indexes based on a size of the set of phase ramp values and a size of the payload to be transmitted (S12 in Fig. IB), generate the Zadoff Chu sequence based on the determined set of root indexes (S13 in Fig. IB), determine a phase ramp based on the determined set of phase ramp values (S14 in Fig. IB) and transmit the generated Zadoff Chu sequence (S14 in Fig. IB).

[0057] Fig. 2A shows a gNB 2 according to an example embodiment. The gNB 2 is an example for an apparatus, which may be or may be a part of a network node or network control node, for example. A procedure carried out by the gNB 2 is illustrated in Fig. 2B. The gNB 2 shown in Fig. 2A comprises at least one processor 21 and at least one memory 22 storing instructions that, when executed by the at least one processor 21, cause the apparatus to: receive a sequence (S21 in Fig. 2B), perform a cross correlation with a Zadoff Chu sequence for each value of a root index of a set of root indexes (S22 in Fig. 2B), perform a fast Fourier transformation for detecting a value of a root index and a value of a phase ramp value based on peak detection (S23 in Fig. 2B), and determine the payload based on the detected value of the root index and the detected value of the phase ramp value (S24 in Fig. 2B), wherein the set of rout indexes is based on a size of the set of phase ramp values and a size of the transmitted payload.

[0058] The apparatuses 1 and 2 shown in Figs. 1A and 2A may comprise more components than described above, and may further comprise I / O units 13, 23, for example, which are capable of transmitting to and receiving from other network elements.

[0059] The example embodiments described above apply Zadoff Chu sequences. Alternatively, it is also possible to apply m-sequences, as shown in example embodiments illustrated in Figs. 3 and 4. Fig. 3 shows a procedure carried out by a UE, which may have the same hardware structure as the UE 1 shown in Fig. 1A. Thus, according to the example embodiment according to Fig. 3, the at least one memory 12 stores instructions that, when executed by the at least one processor 11, cause the apparatus to: determine a set of phase ramp values for transmission of a payload via an m- sequence (S31 in Fig. 3), generate an m-sequence for transmission of a payload based on at least one of a number of allocated resources and the payload to be transmitted (S32 in Fig. 3), determine a phase ramp based on the determined set of phase ramp values (S33 in Fig. 3, and transmit the generated m-sequence with the determined phase ramp (S34 in Fig. 3).

[0060] Fig. 4 shows a procedure carried out by a gNB, which may have the same hardware structure as the gNB 2 shown in Fig. 2A. Thus, according to the example embodiment according to Fig. 4, the at least one memory 22 stores instructions that, when executed by the at least one processor 21, cause the apparatus to: receive a sequence (S41 in Fig. 4), perform a cross correlation with all possible m- sequences (S42 in Fig. 4), perform a fast Fourier transformation for detecting at least one shift register initialization value and a value of a phase ramp value based on peak detection (S43 in Fig. 4), and determine the payload based on the value of the at least one shift register initialization value and the value of the phase ramp value (S44 in Fig. 4).

[0061] Hence, according to several example embodiments, a payload (such as UCI) is encoded by using a Zadoff Chu sequence or an m-sequence and by using a phase ramp. By applying the phase ramp, the necessary number of root indexes and hence sequence length for a certain payload size decreases considerably, and therefore also the amount of truncation necessary to fit the allocated resources decreases accordingly, improving the sequence cross-correlation and finally the performance of the method. Moreover, a phase ramp can easily be detected on the receiver side.

[0062] Hence, the complexity is reduced in particular on the receiver side. It is noted that a phase-ramped Zadoff Chu sequence (or m-sequence) is a Zadoff Chu sequence (or m-sequence) to which a phase ramp is applied.

[0063] A slope of the phase ramp is referred to as a phase ramp value. In other words, if the phase ramp is ej*a, a is the phase ramp value or slope of the phase ramp (value of the phase ramp). That is, "applying a phase ramp" means that a term (such as sequence, e.g., Zadoff Chu sequence or m-sequence) is multiplied by the term ej*a.

[0064] In the following, some example embodiments are described more detail.

[0065] Some example embodiments are directed to methods for UE transmission of UCI across multiple OFDM symbols with sequence selection mechanism based on use of phase ramped Zadoff Chu sequences. In particular, methods are provided for generating a phase ramped Zadoff Chu sequence set and selecting a sequence based on the allocated resources for UCI (i.e. PUCCH) transmission across multiple OFDM symbols and / or based on the size of the UCI to transmit. It is noted that the allocated resources refers to all allocated REs in multiple OFDM symbols, not only to the subcarriers on a single OFDM symbol.

[0066] In detail, according to an example embodiment (referred to as embodiment 1 in the following), methods are provided, by which a Zadoff Chu (ZC) sequence for UCI transmission is generated at the UE based at least on one of the number of allocated resources from a network node and the UCI to transmit. The number of allocated resources N is given by the number of allocated sub-carriers K multiplied by the number of allocated OFDM symbols L.

[0067] In one embodiment (referred to as embodiment l.a), the length of the ZC sequence to generate is the smallest prime number larger than the number of allocated resources.

[0068] In yet another embodiment (referred to as embodiment l.b), the length of the ZC sequence to generate is so that the number of ZC sequences with different root indexes with integer values that can be generated with such a length is at least equal to 2k, where k is the UCI size to transmit.

[0069] In one embodiment (referred to as embodiment l.b.i), the length of the ZC sequence to generate is the smallest prime number larger than 2k / N, where N is a number of available phase ramp values. The number of available phase ramp values is determined at the UE either via configuration from a network node or in relation to the number of allocated resources. In one example, the number of available phase ramp values is equal to the number of allocated resources. In another example (referred to as embodiment l.c in the following), the number of allocated resources is divided into multiple resource subsets, each containing Ni resources, and the number of available phase ramp values is equal to the number Ni of resources contained within each subset. The rationale behind this embodiment is that, although with a length of 2k / N a maximum of 2k / N ZC sequences with different root indexes with integer values can be generated, per each root index N additional sequences can be determined based on applying a phase ramp on the base sequence with the N available phase ramp values.

[0070] The number of resource subsets per transmission and resource subset size(s) (i.e. Ni) may be configured by network node or determined at the UE (e.g. based on standard specifications) so that the radio channel is expected to remain largely unchanged over the resource subset. For example, a resource subset is comprised within a single frequency hop in case of intra-slot frequency hopping and both the number of subcarriers and the number of OFDM symbols containing the resource subset are small enough in comparison to the channel coherence bandwidth and time, respectively.

[0071] In one embodiment (referred to as embodiment l.d), the root index of the ZC sequence to generate is selected based on all or part of the UCI information to transmit.

[0072] In one embodiment (referred to as embodiment l.d.i in the following), R is a number of available root indexes. In one example, R is determined based on a total number of root indexes available for a sequence length. Determination is based on standard specifications or network configuration from a network node (such as a gNB, for example). For example, R could be a fraction of the total number of root indexes available for a sequence length. In another example, R does not depend on the total number of root indexes available for a sequence length. For example, R is a specified number or configured number from a network node.

[0073] In one embodiment (referred to as embodiment l.e in the following), the generated ZC sequence is phase ramped and the phase ramp value depends on all or part of the UCI information to be transmitted.

[0074] According to an implementation of this embodiment (referred to as embodiment l.e.i), the number of available phase ramp values is limited by the number N of allocated resources. According to an alternative implementation of this embodiment (referred to as embodiment l.e.ii), the number of available phase ramp values is limited by the number Ni of resources within the resource subset. According to a further implementation of this embodiment (referred to as embodiment l.e.iii), the number of available phase ramp values is limited by gNB configuration. These three alternatives (embodiments l.e.i to l.e.iii) can be combined. For example, when the number of available phase ramp values based on the number N of allocated resources (or the number Ni of resources within a resource subset) is higher than the limit set by the gNB configuration, the number of available phase ramp values is limited to the limit set by the gNB configuration.

[0075] In one embodiment (referred to as embodiment l.f), UE selects the root index (for example from 0 to R-l) and phase ramp values (for example from 0 to N-l) for ZC sequence generation based on a mapping between the UCI bits and the root index and phase ramp values.

[0076] In one embodiment (referred to as embodiment l.f.i), the k UCI bits to transmit are split into two parts of size k / 2 (or ceiling or floor thereof), and the first (or, alternative, the second) k / 2 bits map to a value of phase ramp and the second (or, alternatively, the first) k / 2 bits map to a value of root index. In yet another embodiment (referred to as embodiment l.f.ii), the possible values of k UCI bits (i.e. from 0 to 2^k-l in decimal base) are mapped to the root index and phase ramp values following a specific ordering.

[0077] In one example, phase ramp value is mapped first - root index second, i.e. decimal value 0 for the UCI bits is mapped to (0, 0), decimal value 1 for the UCI bits is mapped to (1, 0), and so on, wherein the values in parenthesis are phase ramp value and root index, respectively. In alternative case, root index is mapped first - phase ramp value second.

[0078] It is to be noted that the phase ramp value entry may take values from 0 to N-l where N is the number of available phase ramp values, whereas the root index entry may take values from 0 to R.-1, where R. is the number of available root indexes for the generated sequence.

[0079] Fig. 5 shows an example of such a matrix, in which the phase ramp values, which are plotted vertically, may take values from 0 to 2 (i.e., in this example N=3), and the root indexes, which are plotted horizontally, may take values from 0 to 2 (i.e., in this example R=3). Hence, by combining the root index values and the phase ramp values, UCI up to 8 can be represented. For example, if the UCI value (from 0 to 8 in this example) takes a value 6, the phase ramp value is determined as 2 and the root index is determined as 0.

[0080] As an alternative, instead of the matrix based approach described above in connection with Fig. 5, also another approach can be applied based on modulo and flooring operation. As an example, with Ni=84, R=7, and k=9 (aligned with the assumptions given above), if UCI bits are [0 0 1 0 1 1 0 1 0] ^ UCI_decimal = 90. If it is further assumed that phase ramp (m) values are mapped first and root index (r) second, m = = 1 can be calculated.

[0081] In another implementation (referred to as embodiment l.f.iii), the k UCI bits to transmit are split into two parts of different sizes, each size determined at the UE based on the number of available phase ramp values. For example, if N phase ramp values are available to the UE for the transmission, the first [logzN] bits of the UCI are mapped to a value of phase ramp and the remaining k-LlogzN] bits are mapped to a value of root index among the number of available root indexes. Alternatively, the first [logzRJ bits of the UCI are mapped to a value of root index and the remaining k- [logzRJ bits are mapped to a value of phase ramp.

[0082] In another embodiment (referred to as embodiment l.g), the generated ZC sequence with the selected phase ramp is split into a number of sets equal to the number of allocated OFDM symbols for the transmission, and DFT spreading is performed per set.

[0083] This procedure guarantees low CM and PAPR for a ZC sequence allocated in multiple OFDM symbols. Indeed, even if the generate ZC sequence has low PAPR / CM when transmitted in one OFDM symbol, the distribution of the sequence within a number of OFDM symbols destroys its PAPR / CM characteristics. DFT spreading then helps recover the low CM / PAPR.

[0084] The UE then transmits the generated ZC sequence with the determined phase ramp in the resources allocated for UCI transmission. In the case of resource subsets, the generated ZC sequence with the determined phase ramp is transmitted in the each of the resource subsets allocated for UCI transmission.

[0085] In the example embodiments described previously, a Zadoff Chu (ZC) sequence was applied. However, alternatively it is also possible to apply an m-sequence, which is also referred to as Maximum Length Sequence (MLS).

[0086] In particular, according to an example embodiment (referred to as embodiment 2 in the following), methods are provided for generating, at the UE, an m-sequence for UCI transmission based at least on one of the number of allocated resources from a network node and the UCI to transmit. The number of allocated resources N is given by the number of allocated sub-carriers K multiplied by the number of allocated OFDM symbols L. In one embodiment (referred to as embodiment 2. a), a shift register of fixed size m is used at the UE for generation of (2m- 1) m-sequences (each of length 2m-l), and sequences are truncated or extended to fit the N allocated resources.

[0087] In one embodiment (referred to as embodiment 2.b), the generated m-sequence is phase ramped and the slope of such phase ramp depends on all or part of the UCI information to be transmitted. According to an implementation of this embodiment (referred to as embodiment 2.b.i), the number of different phase ramps is limited by the number N of allocated resources. According to an alternative implementation of this embodiment (referred to as embodiment 2.b.ii), the number of different phase ramps is limited by network configuration. The two alternatives (embodiments 2.b.i and 2.b.ii) can be combined. For example, when the number of different phase ramps based on the number N of allocated resources is higher than the limit set by the network configuration, the number of different phase ramps is limited to the limit set by the network configuration.

[0088] In one embodiment (referred to as embodiment 2.c), UE selects the shift register initialization value and phase ramp value for sequence generation based on a mapping of the UCI bits. For example, in one implementation of this embodiment, the shift register is initialized with the first (e.g. MSB) m bits of the UCI and the phase ramp value is selected based on the remaining k-m bits, wherein k is the size of the payload (number of bits of the payload).

[0089] In another embodiment (referred to as embodiment 2.d), the generated m- sequence with the selected phase ramp is split into a number of sets equal to the number of allocated OFDM symbols for the transmission, and DFT spreading is performed per set.

[0090] This procedure guarantees low CM and PAPR for a ZC sequence allocated in multiple OFDM symbols. Indeed, even if the generated m-sequence has low PAPR / CM when transmitted in one OFDM symbol, the distribution of the sequence within a number of OFDM symbols destroys its PAPR / CM characteristics. DFT spreading then helps recover the low CM / PAPR. Similar as described above in connection with the ZC sequences, the UE then transmits the generated m-sequence with the determined phase ramp in the resources allocated for UCI transmission. In the case of resource subsets, the generated m-sequence with the determined phase ramp is transmitted in the each of the resource subsets allocated for UCI transmission.

[0091] In the following, some example implementations are described.

[0092] First, an example implementation for the case of ZC sequences, is described, wherein particular the above based on embodiments l.b, l.c, l.e, l.f and l.g described above.

[0093] The following assumptions apply:

[0094] - The UE is allocated N = 168 resources over 14 OFDM symbols (i.e. one PRB).

[0095] - The UE is configured with intra-slot FH for PUCCH and to use resource subset of size Ni=N / 2 (=84) (according to embodiment l.c described above) and the number of available phase ramp values is equal to Ni (according to embodiment l.e.ii described above).

[0096] - The UE needs to transmit an UCI size of k=9 bits, therefore it needs 2k=512 sequences for transmission of the UCI, i.e. UE needs to select the sequence for transmission of the specific UCI among a set of 512 sequences to have an unambiguous 1-to-l mapping between sequences and UCI bits permutations.

[0097] In the following, a procedure for signal generation is described by referring to a block diagram shown in Fig. 5 showing a basic flow.

[0098] In block 61, the UE determines base sequence length (or equivalently a size of a set of root indexes) based on number of available phase ramp values to use (Ni in this case) and number of sequences needed for UCI size k, i.e. 2k(=512) sequences, based on embodiment l.b described above. In particular, since 512 sequences are needed and UE determines 84 available phase ramp values, UE determines the size of the set of root indexes as R = |^| = 7, which also implies that the sequence length is at least R.

[0099] Since Ni (=84) resources are allocated for transmission of the sequence in one hop, UE needs to fill in such allocation and therefore determines the sequence length as the smallest prime number P larger than L = max R, Ni') .. With these assumptions and procedure, Ni is larger than R and P=89. It is to be noted, that in other example implementations, the sequence length may be determined by the UE solely based on the number of allocated resources or may be determined by the UE based on standard specification as a fixed sequence length regardless of the number of allocated resources.

[0100] It is to be noticed that in this case P>R, so there will be more root indexes than necessary, then UE considers only R root indexes for the transmission, e.g. the first R root indexes from 0 to R-l. It is also to be noticed that since P > Ni, the resulting sequence is truncated to fit the allocated resources.

[0101] In block 62, for a given root index r (e.g. r e {0, ... , R - 1}), the ZC sequence is generated as: jnn (n+l)r

[0102] In block 63, phase ramp is then applied on root sequence xr(n) with each of phase ramp value m (e.g. m e {0, ... , Ni - 1}, as: j2irmn srm(n) = xr(n)eNt , 0 < n < Ni

[0103] Given UCI bits, the root index r and phase ramp value m are chosen for transmission based on embodiment f.ii described above. In other words, the UCI bits are converted into a decimal value, which indicates which combination of phase ramp and root index value to select for the transmission.

[0104] As an example, with Ni=84, R=7, and k=9 (aligned with the assumptions given above), if UCI bits are [0 0 1 0 1 1 0 1 0] UCI_decimal = 90. If it is further assumed that phase ramp (m) values are mapped first and root index (r) second, can be calculated.

[0105] The sequence to be transmitted s is generated based on the obtained value m and r

[0106] In block 64, transform precoding is performed. That is, the sequence srinis split into 7 sets (i.e. number of OFDM symbols allocated within one hop), each has the length of 12 (one PRB). DFT is then performed on each set resulting to the sequence yfm-

[0107] The sequence y is then used for the two resource subsets for intra-slot FH.

[0108] In the following, a procedure for signal reception (per frequency hop) is shortly described.

[0109] Assuming no noise and channel impairments for simplicity of notation, the sequence y is transform de-precoded and reconstructed into sfiK.

[0110] Sf is cross-correlated with xr(n), for each value of r (r e {0, ...,6} in this example), i.e. Sf-in is multiplied by the complex conjugate of xr(n), providing zrr= ■ conj (xr(n)) .

[0111] Each zrin(i.e. for each value of r) is FFT transformed for detection of the transmitted value of m and r, based on peak detection.

[0112] Thus, in this way UCI, i.e., the payload transmitted via the phase ramped sequences, can be detected with a reverse mapping stemming from the detected values of m and f.

[0113] In the following, an example implementation for the case of m-sequences is described.

[0114] The following assumptions apply: - UE is allocated N = 168 resources over 14 OFDM symbols (i.e. one PRB).

[0115] - UE needs to transmit an UCI size of k = 9 bits, therefore it needs 2k= 512 sequences for transmission of the UCI, i.e. UE needs to select the sequence for transmission of the specific UCI among a set of 512 sequences to have an unambiguous 1-to-l mapping between sequences and UCI bits permutations.

[0116] - Shift register length m assumed equal to 5, therefore 2m- 1 m-sequences are available for transmission.

[0117] In the following, a procedure for signal generation based on the above assumptions is described.

[0118] The UE determines the number of phase ramp values to use based on the payload size k. In this case, since 512 sequences are needed and UE can generate up to 2m— 1 = 31 m-sequences, UE determines that at least R = |^| = 17 phase ramp values are necessary for the transmission.

[0119] Then, UE determines the m-sequence for transmission based on the UCI bits first m MSB bits of the UCI are used for the determination.

[0120] UE determines the phase ramp value based on the remaining k - m UCI bits.

[0121] UE determines truncation of the generate sequence (phase ramped m-sequence) based on the number of allocated resources N.

[0122] The generated sequence of size N is split into 14 sets each has the length of 12 (one PRB). DFT is then performed on each set resulting to a transformed sequence.

[0123] Signal reception is the same as for the ZC sequence, except that the receiver will cross-correlate with all possible m-sequences before performing iFFT. In the following, advantages of example embodiments are described, wherein it is referred to the above example numbers.

[0124] It can be noticed that even though 512 sequences are necessary for 9 bits UCI, detection requires only 7 cross-correlations (step 2 of Rx procedure) and 7 FFTs (step 3 of Rx procedure), largely decreasing the number of computations necessary for sequence detection with this method. Indeed, differently than in the case of an extensive search where 2k■ N, = 512 ■ 84 = 43008 multiplications are needed per frequency hop, with this approach the reduced FFT complexity can be exploited to reduce the number of computations. 7 FFTs, each of length 84 require Nlog2(N) = 537 operations, summed to 7 cross-correlations, each requiring 84 multiplications, give a total of 4347 operations, and hence a reduction by a factor 10 in complexity.

[0125] In addition, by exploiting the phase ramping domain to convey part of the UCI information, the necessary sequence length for a certain UCI size decreases considerably and therefore also the amount of truncation necessary to fit the allocated resources decreases accordingly, improving the sequence crosscorrelation and finally the performance of the method.

[0126] Thus, according to example embodiments as described above, an effective reception procedure with reduced complexity at the receiver (gNB) can be achieved.

[0127] The above-described example embodiments are only examples and may be modified.

[0128] For example, in the some example embodiments, UCI was described as payload to be transmitted. However, this is only an example, and any kind of information can be transmitted as payload.

[0129] Moreover, a gNB was described as an example for a network node which may provide network configuration. However, such a network node is not limited to the gNB and can be any network node which is capable of providing a network configuration.

[0130] Names of network elements, protocols, and methods are based on current standards. In other versions or other technologies, the names of these network elements and / or protocols and / or methods may be different, as long as they provide a corresponding functionality.

[0131] In general, example embodiments may be implemented by computer software stored in the memory (memory resources, memory circuitry) 12, 22 and executable by the processor (processing resources, processing circuitry) 11, 21 or by hardware, or by a combination of software and / or firmware and hardware.

[0132] The terms "connected," "coupled," or any variant thereof, mean any connection or coupling, either direct or indirect, between two or more elements, and may encompass the presence of one or more intermediate elements between two elements that are "connected" or "coupled" together. The coupling or connection between the elements can be physical, logical, or a combination thereof. As employed herein two elements may be considered to be "connected" or "coupled" together by the use of one or more wires, cables and printed electrical connections, as well as by the use of electromagnetic energy, such as electromagnetic energy having wavelengths in the radio frequency region, the microwave region and the optical (both visible and invisible) region, as non-limiting examples.

[0133] The memory (memory resources, memory circuitry) 12, 22 may be of any type suitable to the local technical environment and may be implemented using any suitable data storage technology, such as semiconductor based memory devices, magnetic memory devices and systems, optical memory devices and systems, fixed memory and removable memory, and non-transitory computer-readable media. The processor (processing resources, processing circuitry) 11, 21 may be of any type suitable to the local technical environment, and may include one or more of general purpose computers, special purpose computers, microprocessors, digital signal processors (DSPs) and processors based on a multi core processor architecture, as non-limiting examples. Further, as used in this application, the term "circuitry" may refer to one or more or all of the following:

[0134] (a) hardware-only circuit implementations (such as implementations in only analog and / or digital circuitry) and

[0135] (b) combinations of hardware circuits and software, such as (as applicable):

[0136] (i) a combination of analog and / or digital hardware circuit(s) with software / firmware and

[0137] (ii) any portions of hardware processor(s) with software (including digital signal processor(s)), software, and memory(ies) that work together to cause an apparatus, such as a mobile phone or server, to perform various functions) and

[0138] (c) hardware circuit(s) and or processor(s), such as a microprocessor(s) or a portion of a microprocessor(s), that requires software (e.g., firmware) for operation, but the software may not be present when it is not needed for operation.

[0139] This definition of circuitry applies to all uses of this term in this application, including in any claims. As a further example, as used in this application, the term circuitry also covers an implementation of merely a hardware circuit or processor (or multiple processors) or portion of a hardware circuit or processor and its (or their) accompanying software and / or firmware. The term circuitry also covers, for example and if applicable to the particular claim element, a baseband integrated circuit or processor integrated circuit for a mobile device or a similar integrated circuit in a server, a cellular network device, or other computing or network device.

[0140] The term "non-transitory", as used herein, is a limitation of the medium itself (i.e., tangible, not a signal) as opposed to a limitation on data storage persistency (e.g., RAM vs. ROM).

[0141] It is noted that, as used herein, "at least one of the following: " and "at least one of " and similar wording, where the list of two or more elements are joined by "and" or "or", mean at least any one of the elements, or at least any two or more of the elements, or at least all the elements. It is to be understood that the various example embodiments of the subject disclosure are illustrative and non-limiting and are not intended to be construed as limiting. Various modifications and applications may be apparent to those skilled in the art without departing from the spirit and scope of the various example embodiments of the subject disclosure.

[0142] Among others, the following Items are covered by the above disclosure:

[0143] Item 1. An apparatus, comprising at least one processor, and at least one memory storing instructions that, when executed by the at least one processor, cause the apparatus at least to determine a set of phase ramp values for transmission of a payload via a Zadoff Chu sequence; determine a set of root indexes based on a size of the set of phase ramp values and a size of the payload to be transmitted; generate the Zadoff Chu sequence based the determined set of root indexes; determine a phase ramp based on the determined set of phase ramp values; and transmit the generated Zadoff Chu sequence with the determined phase ramp.

[0144] Item 2. The apparatus according to item 1, wherein the instructions stored by the at least one memory further cause the apparatus, when executed by the at least one processor, at least to: determine the phase ramp by selecting a phase ramp value of the determined set of phase ramp values based on at least a part of the payload, select at least one root index from the determined set of the root indexes based on at least a part of the payload, and transmit the generated Zadoff Chu sequence based on the selected a least one root index with the phase ramp based on the selected phase ramp value. Item 3. The apparatus according to item 1 or 2, wherein the instructions stored by the at least one memory further cause the apparatus, when executed by the at least one processor, at least to: set a length of the Zadoff Chu sequence such that the length is the smallest prime number larger than a number of allocated resources.

[0145] Item 4. The apparatus according to item 1 or 2, wherein the instructions stored by the at least one memory further cause the apparatus, when executed by the at least one processor, at least to: set a length of the Zadoff Chu sequence such that a size of the determined set of root indexes is at least equal to 2k, wherein k is the size of the payload to be transmitted.

[0146] Item 5. The apparatus according to item 1 or 2, wherein the instructions stored by the at least one memory further cause the apparatus, when executed by the at least one processor, at least to: set the length of the Zadoff Chu sequence such that a size of the determined set of root indexes is the smallest prime number larger than 2k / N, wherein N is a size of the set of phase ramp values.

[0147] Item 6. The apparatus according to item 1 or 5, wherein the set of phase ramp values, which can be determined, is limited by the number of allocated resources, or the set of phase ramp values, which can be determined, is limited by a network configuration.

[0148] Item 7. The apparatus according to item 2, wherein the instructions stored by the at least one memory further cause the apparatus, when executed by the at least one processor, at least to: subdivide the allocated resources into multiple resource subsets of Ni resources, determine a length of the Zadoff Chu sequence based on the Ni resources in each resource subset, and transmit the generated Zadoff Chu sequence with the determined phase ramp in each of the resource subsets allocated for payload transmission.

[0149] Item 8. The apparatus according to item 7, wherein the number of different phase ramps is limited by the number Ni of resources within a resources subset.

[0150] Item 9. The apparatus according to any one of the item 1 to 8, wherein the instructions stored by the at least one memory further cause the apparatus, when executed by the at least one processor, at least to: determine a root index of the Zadoff Chu sequence among the determined set of root indexes based on all of the payload to transmit or based on a part of the payload to transmit.

[0151] Item 10. The apparatus according to item 1, wherein the instructions stored by the at least one memory further cause the apparatus, when executed by the at least one processor, at least to: determine a root index of the set of root indexes of the Zadoff Chu sequence based on a part of the payload to transmit, and determine the set of root indexes further based on a standard specification or a network configuration.

[0152] Item 11. The apparatus according to any one of the items 1 to 10, wherein the instructions stored by the at least one memory further cause the apparatus, when executed by the at least one processor, at least to: select a root index and a phase ramp value for Zadoff Chu sequence generation based on a mapping between payload bits and the sets of root indexes and phase ramp values.

[0153] Item 12. The apparatus according to item 11, wherein the instructions stored by the at least one memory further cause the apparatus, when executed by the at least one processor, at least to: split the payload bits into two parts, map one of the two parts to a phase ramp value, and map the other one of the two parts to a root index.

[0154] Item 13. The apparatus according to item 12, wherein the two parts are consecutive.

[0155] Item 14. The apparatus according to item 12, wherein the instructions stored by the at least one memory further cause the apparatus, when executed by the at least one processor, at least to: determine a size of each part of the payload bits based on the number of available phase ramp values.

[0156] Item 15. The apparatus according to item 12, wherein the instructions stored by the at least one memory further cause the apparatus, when executed by the at least one processor, at least to: map the payload bits in a specific ordering to a phase ramp value and to a root index.

[0157] Item 16. The apparatus according to any one of the items 1 to 15, wherein the instructions stored by the at least one memory further cause the apparatus, when executed by the at least one processor, at least to: split the generated Zadoff Chu sequence with the selected phase ramp into a number of sets, and perform discrete Fourier transformation spreading for each set.

[0158] Item 17. The apparatus according to item 16, wherein the number of sets is equal to the number of orthogonal frequency division multiplexing symbols allocated for transmission.

[0159] Item 18. The apparatus according to item 1, wherein the number of allocated resources is given by the number of allocated subcarriers multiplied by the number of orthogonal frequency division multiplexing symbols allocated for transmission.

[0160] Item 19. An apparatus, comprising at least one processor, and at least one memory storing instructions that, when executed by the at least one processor, cause the apparatus at least to receive a sequence, perform a cross correlation with a Zadoff Chu sequence for each value of a root index of a set of root indexes, perform a fast Fourier transformation for detecting a value of a root index and a value of a phase ramp value based on peak detection, and determine the payload based on the detected value of the root index and the detected value of the phase ramp value, wherein the set of root indexes is based on a size of a set of phase ramp values and a size of the transmitted payload.

[0161] Item 20. The apparatus according to item 19, wherein the set of root indexes is defined based on a maximum sequence length of the Zadoff Chu sequence.

[0162] Item 21. The apparatus according to item 19 or 20, wherein the instructions stored by the at least one memory further cause the apparatus, when executed by the at least one processor, at least to: determine the payload based on a mapping between payload bits and root indexes and phase ramp values.

[0163] Item 22. The apparatus according to item 21, wherein the mapping between payload bits and root indexes and phase ramp values is such that a first part of payload bits is mapped to a phase ramp value and a second part of the payload bits is mapped to a root index.

[0164] Item 23. The apparatus according to item 22, wherein the two parts are consecutive.

[0165] Item 24. The apparatus according to item 21, wherein the mapping between payload bits and root indexes and phase ramp values is such that the payload bits are mapped in a specific ordering to a phase ramp value and to a root index.

[0166] Item 25. A method comprising: determining a set of phase ramp values for transmission of a payload via a Zadoff Chu sequence; determining a set of root indexes based on a size of the set of phase ramp values and a size of the payload to be transmitted; generating the Zadoff Chu sequence based the determined set of root indexes; determining a phase ramp based on the determined set of phase ramp values; and transmitting the generated Zadoff Chu sequence with the determined phase ramp.

[0167] Item 26. The method according to item 25, further comprising: determining the phase ramp by selecting a phase ramp value of the determined set of phase ramp values based on at least a part of the payload, selecting at least one root index from the determined set of the root indexes based on at least a part of the payload, and transmitting the generated Zadoff Chu sequence based on the selected a least one root index with the phase ramp based on the selected phase ramp value.

[0168] Item 27. The method according to item 25 or 26, further comprising: setting a length of the Zadoff Chu sequence such that the length is the smallest prime number larger than a number of allocated resources.

[0169] Item 28. The method according to item 25 or 26, further comprising: setting a length of the Zadoff Chu sequence such that a size of the determined set of root indexes is at least equal to 2k, wherein k is the size of the payload to be transmitted.

[0170] Item 29. The method according to item 25 or 26, further comprising: setting the length of the Zadoff Chu sequence such that a size of the determined set of root indexes is the smallest prime number larger than 2k / N, wherein N is a size of the set of phase ramp values.

[0171] Item 30. The method according to item 25 or 29, wherein the set of phase ramp values, which can be determined, is limited by the number of allocated resources, or the set of phase ramp values, which can be determined, is limited by a network configuration.

[0172] Item 31. The method according to item 26, further comprising: subdividing the allocated resources into multiple resource subsets of Ni resources, determining a length of the Zadoff Chu sequence based on the Ni resources in each resource subset, and transmitting the generated Zadoff Chu sequence with the determined phase ramp in each of the resource subsets allocated for payload transmission.

[0173] Item 32. The method according to item 31, wherein the number of different phase ramps is limited by the number Ni of resources within a resources subset.

[0174] Item 33. The method according to any one of the item 25 to 32, further comprising: determining a root index of the Zadoff Chu sequence among the determined set of root indexes based on all of the payload to transmit or based on a part of the payload to transmit.

[0175] Item 34. The method according to item 25, further comprising: determining a root index of the set of root indexes of the Zadoff Chu sequence based on a part of the payload to transmit, and determining the set of root indexes further based on a standard specification or a network configuration.

[0176] Item 35. The method according to any one of the items 25 to 34, further comprising: selecting a root index and a phase ramp value for Zadoff Chu sequence generation based on a mapping between payload bits and the sets of root indexes and phase ramp values. Item 36. The method according to item 35, further comprising: splitting the payload bits into two parts, mapping one of the two parts to a phase ramp value, and mapping the other one of the two parts to a root index.

[0177] Item 37. The method according to item 36, wherein the two parts are consecutive.

[0178] Item 38. The method according to item 36, further comprising: determining a size of each part of the payload bits based on the number of available phase ramp values.

[0179] Item 39. The method according to item 35, further comprising: mapping the payload bits in a specific ordering to a phase ramp value and to a root index.

[0180] Item 40. The method according to any one of the items 25 to 39, further comprising: splitting the generated Zadoff Chu sequence with the selected phase ramp into a number of sets, and performing discrete Fourier transformation spreading for each set.

[0181] Item 41. The method according to item 40, wherein the number of sets is equal to the number of orthogonal frequency division multiplexing symbols allocated for transmission.

[0182] Item 42. The method according to item 25, wherein the number of allocated resources is given by the number of allocated subcarriers multiplied by the number of orthogonal frequency division multiplexing symbols allocated for transmission.

[0183] Item 43. A method, comprising receiving a sequence, performing a cross correlation with a Zadoff Chu sequence for each value of a root index of a set of root indexes, performing a fast Fourier transformation for detecting a value of a root index and a value of a phase ramp value based on peak detection, and determining the payload based on the detected value of the root index and the detected value of the phase ramp value, wherein the set of root indexes is based on a size of a set of phase ramp values and a size of the transmitted payload.

[0184] Item 44. The method according to item 43, wherein the set of root indexes is defined based on a maximum sequence length of the Zadoff Chu sequence.

[0185] Item 45. The method according to item 43 or 44, further comprising: determining the payload based on a mapping between payload bits and root indexes and phase ramp values.

[0186] Item 46. The method according to item 45, wherein the mapping between payload bits and root indexes and phase ramp values is such that a first part of payload bits is mapped to a phase ramp value and a second part of the payload bits is mapped to a root index.

[0187] Item 47. The method according to item 46, wherein the two parts are consecutive.

[0188] Item 48. The method according to item 45, wherein the mapping between payload bits and root indexes and phase ramp values is such that the payload bits are mapped in a specific ordering to a phase ramp value and to a root index.

[0189] Item 49. A computer program product comprising code means for performing a method according to any one of the items 25 to 48 when run on a processing means or module.

[0190] Item 50. The computer program product according to item 49, wherein the computer program product is embodied on a computer-readable medium, and / or the computer program product is directly loadable into the internal memory of the computer and / or transmittable via a network by means of at least one of upload, download and push procedures.

[0191] Item 51. An apparatus comprising: means for determining a set of phase ramp values for transmission of a payload via a Zadoff Chu sequence; means for determining a set of root indexes based on a size of the set of phase ramp values and a size of the payload to be transmitted; means for generating the Zadoff Chu sequence based the determined set of root indexes; means for determining a phase ramp based on the determined set of phase ramp values; and means for transmitting the generated Zadoff Chu sequence with the determined phase ramp.

[0192] Item 52. The apparatus according to item 51, further comprising: means for determining the phase ramp by selecting a phase ramp value of the determined set of phase ramp values based on at least a part of the payload, means for selecting at least one root index from the determined set of the root indexes based on at least a part of the payload, and means for transmitting the generated Zadoff Chu sequence based on the selected a least one root index with the phase ramp based on the selected phase ramp value.

[0193] Item 53. The apparatus according to item 51 or 52, further comprising: means for setting a length of the Zadoff Chu sequence such that the length is the smallest prime number larger than a number of allocated resources.

[0194] Item 54. The apparatus according to item 51 or 52, further comprising: means for setting a length of the Zadoff Chu sequence such that a size of the determined set of root indexes is at least equal to 2k, wherein k is the size of the payload to be transmitted. Item 55. The apparatus according to item 51 or 52, further comprising: means for setting the length of the Zadoff Chu sequence such that a size of the determined set of root indexes is the smallest prime number larger than 2k / N, wherein N is a size of the set of phase ramp values.

[0195] Item 56. The apparatus according to item 51 or 55, wherein the set of phase ramp values, which can be determined, is limited by the number of allocated resources, or the set of phase ramp values, which can be determined, is limited by a network configuration.

[0196] Item 57. The apparatus according to item 52, further comprising: means for subdividing the allocated resources into multiple resource subsets of Ni resources, means for determining a length of the Zadoff Chu sequence based on the Ni resources in each resource subset, and means for transmitting the generated Zadoff Chu sequence with the determined phase ramp in each of the resource subsets allocated for payload transmission.

[0197] Item 58. The apparatus according to item 57, wherein the number of different phase ramps is limited by the number Ni of resources within a resources subset.

[0198] Item 59. The apparatus according to any one of the item 51 to 58, further comprising: means for determining a root index of the Zadoff Chu sequence among the determined set of root indexes based on all of the payload to transmit or based on a part of the payload to transmit.

[0199] Item 60. The apparatus according to item 51, further comprising: means for determining a root index of the set of root indexes of the Zadoff Chu sequence based on a part of the payload to transmit, and means for determining the set of root indexes further based on a standard specification or a network configuration.

[0200] Item 61. The apparatus according to any one of the items 51 to 60, further comprising: means for selecting a root index and a phase ramp value for Zadoff Chu sequence generation based on a mapping between payload bits and the sets of root indexes and phase ramp values.

[0201] Item 62. The apparatus according to item 61, further comprising: means for splitting the payload bits into two parts, means for mapping one of the two parts to a phase ramp value, and means for mapping the other one of the two parts to a root index.

[0202] Item 63. The apparatus according to item 62, wherein the two parts are consecutive.

[0203] Item 64. The apparatus according to item 62, further comprising: means for determining a size of each part of the payload bits based on the number of available phase ramp values.

[0204] Item 65. The apparatus according to item 61, further comprising: means for mapping the payload bits in a specific ordering to a phase ramp value and to a root index.

[0205] Item 66. The apparatus according to any one of the items 51 to 65, further comprising: means for splitting the generated Zadoff Chu sequence with the selected phase ramp into a number of sets, and means for performing discrete Fourier transformation spreading for each set. Item 67. The apparatus according to item 66, wherein the number of sets is equal to the number of orthogonal frequency division multiplexing symbols allocated for transmission.

[0206] Item 68. The apparatus according to item 51, wherein the number of allocated resources is given by the number of allocated subcarriers multiplied by the number of orthogonal frequency division multiplexing symbols allocated for transmission.

[0207] Item 69. An apparatus, comprising means for receiving a sequence, means for performing a cross correlation with a Zadoff Chu sequence for each value of a root index of a set of root indexes, means for performing a fast Fourier transformation for detecting a value of a root index and a value of a phase ramp value based on peak detection, and means for determining the payload based on the detected value of the root index and the detected value of the phase ramp value, wherein the set of root indexes is based on a size of a set of phase ramp values and a size of the transmitted payload.

[0208] Item 70. The apparatus according to item 69, wherein the set of root indexes is defined based on a maximum sequence length of the Zadoff Chu sequence.

[0209] Item 71. The apparatus according to item 69 or 70, further comprising: means for determining the payload based on a mapping between payload bits and root indexes and phase ramp values.

[0210] Item 72. The apparatus according to item 71, wherein the mapping between payload bits and root indexes and phase ramp values is such that a first part of payload bits is mapped to a phase ramp value and a second part of the payload bits is mapped to a root index.

[0211] Item 73. The apparatus according to item 72, wherein the two parts are consecutive. Item 74. The apparatus according to item 71, wherein the mapping between payload bits and root indexes and phase ramp values is such that the payload bits are mapped in a specific ordering to a phase ramp value and to a root index.

[0212] Item 75. An apparatus, comprising at least one processor, and at least one memory storing instructions that, when executed by the at least one processor, cause the apparatus at least to determine a set of phase ramp values for transmission of a payload via an m-sequence; generate an m-sequence for transmission of a payload based on at least one of a number of allocated resources and the payload to be transmitted, determine a phase ramp based on the determined set of phase ramp values, transmit the generated m-sequence with the determined phase ramp.

[0213] Item 76. The apparatus according to item 75, wherein the instructions stored by the at least one memory further cause the apparatus, when executed by the at least one processor, at least to: use a shift register of a size m for generating (2m- 1) m-sequences, m being a natural number, and truncate or extend the m-sequences to fit the allocated resources.

[0214] Item 77. The apparatus according to item 1 or 2, wherein the set of phase ramp values, which can be determined, has a size equal to the number of allocated resources, or the set of phase ramp values, which can be determined, has a size indicated by a network configuration.

[0215] Item 78. The apparatus according to item 75, wherein the instructions stored by the at least one memory further cause the apparatus, when executed by the at least one processor, at least to: determine the phase ramp by selecting a phase ramp value of the determined set of phase ramp values based on at least a part of the payload, and generate the m-sequence by selecting at least one shift register initialization value based on at least a part of the payload.

[0216] Item 79. The apparatus according to item 78, wherein the instructions stored by the at least one memory further cause the apparatus, when executed by the at least one processor, at least to: select the at least one shift register initialization value and the phase ramp value based on a mapping between payload bits and shift register initialization values and phase ramp values.

[0217] Item 80. The apparatus according to item 79, wherein the instructions stored by the at least one memory further cause the apparatus, when executed by the at least one processor, at least to: select the at least one shift register initialization value based on a first part of the bits of the payload and determine the phase ramp value based on the remaining part of the bits of the payload.

[0218] Item 81. The apparatus according to any one of the items 75 to 80, wherein the instructions stored by the at least one memory further cause the apparatus, when executed by the at least one processor, at least to: split the generated m-sequence with the determined phase ramp into a number of sets, and perform discrete Fourier transformation spreading for each set.

[0219] Item 82. The apparatus according to item 81, wherein the number of sets is equal to the number of orthogonal frequency division multiplexing symbols allocated for transmission.

[0220] Item 83. The apparatus according to item 75, wherein the number of allocated resources is given by the number of allocated subcarriers multiplied by the number of orthogonal frequency division multiplexing symbols allocated for transmission.

[0221] Item 84. An apparatus, comprising at least one processor, and at least one memory storing instructions that, when executed by the at least one processor, cause the apparatus at least to receive a sequence, perform a cross correlation with all possible m-sequences, perform a fast Fourier transformation for detecting at least one shift register initialization value and a value of a phase ramp value based on peak detection, and determine the payload based on the value of the at least one shift register initialization value and the value of the phase ramp value.

[0222] Item 85. The apparatus according to item 84, wherein the instructions stored by the at least one memory further cause the apparatus, when executed by the at least one processor, at least to: determine the payload based on a mapping between payload bits and at least one shift register initialization value and phase ramp values.

[0223] Item 86. A method, comprising determining a set of phase ramp values for transmission of a payload via an m-sequence; generating an m-sequence for transmission of a payload based on at least one of a number of allocated resources and the payload to be transmitted, determining a phase ramp based on the determined set of phase ramp values, transmitting the generated m-sequence with the determined phase ramp.

[0224] Item 87. The method according to item 86, further comprising: using a shift register of a size m for generating (2m-l) m-sequences, m being a natural number, and truncating or extending the m-sequences to fit the allocated resources.

[0225] Item 88. The method according to item 86 or 87, wherein the set of phase ramp values, which can be determined, has a size equal to the number of allocated resources, or the set of phase ramp values, which can be determined, has a size indicated by a network configuration.

[0226] Item 89. The method according to item 86, further comprising: determining the phase ramp by selecting a phase ramp value of the determined set of phase ramp values based on at least a part of the payload, and generating the m-sequence by selecting at least one shift register initialization value based on at least a part of the payload.

[0227] Item 90. The method according to item 89, further comprising: selecting the at least one shift register initialization value and the phase ramp value based on a mapping between payload bits and shift register initialization values and phase ramp values.

[0228] Item 91. The method according to item 90, further comprising: selecting the at least one shift register initialization value based on a first part of the bits of the payload and determining the phase ramp value based on the remaining part of the bits of the payload.

[0229] Item 92. The method according to any one of the items 86 to 91, further comprising: splitting the generated m-sequence with the determined phase ramp into a number of sets, and performing discrete Fourier transformation spreading for each set.

[0230] Item 93. The method according to item 92, wherein the number of sets is equal to the number of orthogonal frequency division multiplexing symbols allocated for transmission.

[0231] Item 94. The method according to item 86, wherein the number of allocated resources is given by the number of allocated subcarriers multiplied by the number of orthogonal frequency division multiplexing symbols allocated for transmission. Item 95. A method, comprising receiving a sequence, performing a cross correlation with all possible m-sequences, performing a fast Fourier transformation for detecting at least one shift register initialization value and a value of a phase ramp value based on peak detection, and determining the payload based on the value of the at least one shift register initialization value and the value of the phase ramp value.

[0232] Item 96. The method according to item 95, further comprising: determining the payload based on a mapping between payload bits and at least one shift register initialization value and phase ramp values.

[0233] Item 97. A computer program product comprising code means for performing a method according to any one of the items 86 to 96 when run on a processing means or module.

[0234] Item 98. The computer program product according to item 97, wherein the computer program product is embodied on a computer-readable medium, and / or the computer program product is directly loadable into the internal memory of the computer and / or transmittable via a network by means of at least one of upload, download and push procedures.

[0235] Item 99. An apparatus comprising: means for determining a set of phase ramp values for transmission of a payload via an m-sequence; means for generating an m-sequence for transmission of a payload based on at least one of a number of allocated resources and the payload to be transmitted, means for determining a phase ramp based on the determined set of phase ramp values, transmitting the generated m-sequence with the determined phase ramp.

[0236] Item 100. The apparatus according to item 99, further comprising: means for using a shift register of a size m for generating (2m-l) m- sequences, m being a natural number, and means for truncating or extending the m-sequences to fit the allocated resources.

[0237] Item 101. The apparatus according to item 99 or 100, wherein the set of phase ramp values, which can be determined, has a size equal to the number of allocated resources, or the set of phase ramp values, which can be determined, has a size indicated by a network configuration.

[0238] Item 102. The apparatus according to item 99, further comprising: means for determining the phase ramp by selecting a phase ramp value of the determined set of phase ramp values based on at least a part of the payload, and means for generating the m-sequence by selecting at least one shift register initialization value based on at least a part of the payload.

[0239] Item 103. The apparatus according to item 102, further comprising: means for selecting the at least one shift register initialization value and the phase ramp value based on a mapping between payload bits and shift register initialization values and phase ramp values.

[0240] Item 104. The apparatus according to item 103, further comprising: means for selecting the at least one shift register initialization value based on a first part of the bits of the payload and means for determining the phase ramp value based on the remaining part of the bits of the pay load.

[0241] Item 105. The apparatus according to any one of the items 99 to 104, further comprising: splitting the generated m-sequence with the determined phase ramp into a number of sets, and performing discrete Fourier transformation spreading for each set. Item 106. The apparatus according to item 105, wherein the number of sets is equal to the number of orthogonal frequency division multiplexing symbols allocated for transmission.

[0242] Item 107. The apparatus according to item 99, wherein the number of allocated resources is given by the number of allocated subcarriers multiplied by the number of orthogonal frequency division multiplexing symbols allocated for transmission.

[0243] Item 108. A apparatus, comprising means for receiving a sequence, means for performing a cross correlation with all possible m-sequences, means for performing a fast Fourier transformation for detecting at least one shift register initialization value and a value of a phase ramp value based on peak detection, and means for determining the payload based on the value of the at least one shift register initialization value and the value of the phase ramp value.

[0244] Item 109. The apparatus according to item 108, further comprising: means for determining the payload based on a mapping between payload bits and at least one shift register initialization value and phase ramp values.

Claims

CLAIMS1. An apparatus, comprising at least one processor, and at least one memory storing instructions that, when executed by the at least one processor, cause the apparatus at least to determine a set of phase ramp values for transmission of a payload via a Zadoff Chu sequence; determine a set of root indexes based on a size of the set of phase ramp values and a size of the payload to be transmitted; generate the Zadoff Chu sequence based the determined set of root indexes; determine a phase ramp based on the determined set of phase ramp values; and transmit the generated Zadoff Chu sequence with the determined phase ramp.

2. The apparatus according to claim 1, wherein the instructions stored by the at least one memory further cause the apparatus, when executed by the at least one processor, at least to: determine the phase ramp by selecting a phase ramp value of the determined set of phase ramp values based on at least a part of the payload, select at least one root index from the determined set of the root indexes based on at least a part of the payload, and transmit the generated Zadoff Chu sequence based on the selected a least one root index with the phase ramp based on the selected phase ramp value.

3. The apparatus according to claim 1 or 2, wherein the instructions stored by the at least one memory further cause the apparatus, when executed by the at least one processor, at least to: set a length of the Zadoff Chu sequence such that the length is the smallest prime number larger than a number of allocated resources.

4. The apparatus according to claim 1 or 2, wherein the instructions stored by the at least one memory further cause the apparatus, when executed by the at least one processor, at least to: set a length of the Zadoff Chu sequence such that a size of the determined set of root indexes is at least equal to 2k, wherein k is the size of the payload to be transmitted.

5. The apparatus according to claim 1 or 2, wherein the instructions stored by the at least one memory further cause the apparatus, when executed by the at least one processor, at least to: set the length of the Zadoff Chu sequence such that a size of the determined set of root indexes is the smallest prime number larger than 2k / N, wherein N is a size of the set of phase ramp values.

6. The apparatus according to claim 1 or 5, wherein the set of phase ramp values, which can be determined, is limited by the number of allocated resources, or the set of phase ramp values, which can be determined, is limited by a network configuration.

7. The apparatus according to claim 2, wherein the instructions stored by the at least one memory further cause the apparatus, when executed by the at least one processor, at least to: subdivide the allocated resources into multiple resource subsets of Ni resources, determine a length of the Zadoff Chu sequence based on the Ni resources in each resource subset, and transmit the generated Zadoff Chu sequence with the determined phase ramp in each of the resource subsets allocated for payload transmission.

8. The apparatus according to claim 7, wherein the number of different phase ramps is limited by the number Ni of resources within a resources subset.

9. The apparatus according to any one of the claims 1 to 8, wherein the instructions stored by the at least one memory further cause the apparatus, when executed by the at least one processor, at least to: determine a root index of the Zadoff Chu sequence among the determined set of root indexes based on all of the payload to transmit or based on a part of the payload to transmit.

10. The apparatus according to claim 1, wherein the instructions stored by the at least one memory further cause the apparatus, when executed by the at least one processor, at least to: determine a root index of the set of root indexes of the Zadoff Chu sequence based on a part of the payload to transmit, and determine the set of root indexes further based on a standard specification or a network configuration.

11. The apparatus according to any one of the claims 1 to 10, wherein the instructions stored by the at least one memory further cause the apparatus, when executed by the at least one processor, at least to: select a root index and a phase ramp value for Zadoff Chu sequence generation based on a mapping between payload bits and the sets of root indexes and phase ramp values.

12. The apparatus according to claim 11, wherein the instructions stored by the at least one memory further cause the apparatus, when executed by the at least one processor, at least to: split the payload bits into two parts, map one of the two parts to a phase ramp value, and map the other one of the two parts to a root index.

13. The apparatus according to claim 12, wherein the two parts are consecutive.

14. The apparatus according to claim 12, wherein the instructions stored by the at least one memory further cause the apparatus, when executed by the at least one processor, at least to:determine a size of each part of the payload bits based on the number of available phase ramp values.

15. The apparatus according to claim 12, wherein the instructions stored by the at least one memory further cause the apparatus, when executed by the at least one processor, at least to: map the payload bits in a specific ordering to a phase ramp value and to a root index.

16. The apparatus according to any one of the claims 1 to 15, wherein the instructions stored by the at least one memory further cause the apparatus, when executed by the at least one processor, at least to: split the generated Zadoff Chu sequence with the selected phase ramp into a number of sets, and perform discrete Fourier transformation spreading for each set.

17. The apparatus according to claim 16, wherein the number of sets is equal to the number of orthogonal frequency division multiplexing symbols allocated for transmission.

18. An apparatus, comprising at least one processor, and at least one memory storing instructions that, when executed by the at least one processor, cause the apparatus at least to receive a sequence, perform a cross correlation with a Zadoff Chu sequence for each value of a root index of a set of root indexes, perform a fast Fourier transformation for detecting a value of a root index and a value of a phase ramp value based on peak detection, and determine the payload based on the detected value of the root index and the detected value of the phase ramp value, wherein the set of root indexes is based on a size of a set of phase ramp values and a size of the transmitted payload.

19. The apparatus according to claim 18, wherein the set of root indexes is defined based on a maximum sequence length of the Zadoff Chu sequence.

20. The apparatus according to claim 18 or 19, wherein the instructions stored by the at least one memory further cause the apparatus, when executed by the at least one processor, at least to: determine the payload based on a mapping between payload bits and root indexes and phase ramp values.

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