Shift register, driving circuit, driving method, and display device

Abstract

The present disclosure relates to the technical field of display, and provides a shift register, a driving circuit, a driving method, and a display device. The shift register comprises an input shift circuit, configured to use a first clock signal from a first clock end, a second clock signal from a second clock end, a first input signal from a first input end, and a reset signal from a reset end to control the potential of a first node; and use a third clock signal from a third clock end, a fourth clock signal from a fourth clock end, and the potential of the first node to control the potential of a second node; a first control circuit, configured to use the potential of the second node and a first control signal from a first control end to control the potential of a third node; and an output circuit, configured to use the potential of the first node and the potential of the third node to control to provide a first power supply voltage of a first power supply or a second power supply voltage of a second power supply to an output end as an output signal.

Description

Shift register, driving circuit, driving method and display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a shift register, a driving circuit, a driving method and a display device. BACKGROUND

[0002] Gate driver on array (GOA) technology is a technology of integrating a driving circuit on a display panel, which can facilitate the narrow frame design of the display panel. The driving circuit can provide a scanning signal, a light emitting control signal and a reset signal and the like to a pixel circuit in the display panel to drive the pixel circuit.

[0003] For a conventional complementary metal oxide semiconductor (CMOS) GOA circuit, a P-type MOS transistor and an N-type MOS transistor are controlled by the same signal, which makes the P-type MOS transistor and the N-type MOS transistor possibly turn on at the same time when the signal is in an intermediate state. In this case, a leakage phenomenon occurs between the power supplies connected to the P-type MOS transistor and the N-type MOS transistor, thereby increasing the power consumption of the GOA and reducing the driving capability on the pixel circuit.

[0004] SUMMARY

[0005] To solve the above problems, the present disclosure provides a shift register, a driving circuit, a driving method and a display device.

[0006] According to a first aspect, the present disclosure provides a shift register, comprising: an input shift circuit configured to control a potential of a first node by using a first clock signal from a first clock terminal, a second clock signal from a second clock terminal, a first input signal from a first input terminal and a reset signal from a reset terminal; and control a potential of a second node by using a third clock signal from a third clock terminal, a fourth clock signal from a fourth clock terminal and the potential of the first node; a first control circuit configured to control a potential of a third node by using the potential of the second node and a first control signal from a first control terminal; and an output circuit configured to control providing a first power supply voltage of a first power supply or a second power supply voltage of a second power supply to an output terminal as an output signal by using the potential of the first node and the potential of the third node.

[0007] According to a second aspect, the present disclosure provides a driving circuit, comprising M shift registers of the present disclosure embodiments connected in cascade, wherein a first input terminal of an mth shift register is electrically connected to a second node of an (m-1)th shift register, 2

[0008] According to a third aspect, the present disclosure provides a display device comprising the driving circuit according to any one of the embodiments of the present disclosure.

[0009] According to a fourth aspect, the present disclosure provides a driving method applied to the shift register according to any one of the embodiments of the present disclosure, comprising: in a first time period, the first input signal is at a first level, the reset signal is at the first level, and the first control signal is at the first level; in a second time period, the first input signal is at the first level, the reset signal is at the first level, and the first control signal is at a second level; in a third time period, the first input signal is at a second level, the reset signal is at the first level, and the first control signal is at the first level; in a fourth time period, the first input signal is at the second level, the reset signal is at the first level, and the first control signal is at the second level. BRIEF DESCRIPTION OF DRAWINGS

[0010] FIG. 1A is a structural schematic diagram of an example pixel circuit;

[0011] FIG. 1B is a signal timing diagram of the pixel circuit shown in FIG. 1A;

[0012] FIG. 2 is a structural schematic diagram of a shift register according to an embodiment of the present disclosure;

[0013] FIG. 3 is a structural schematic diagram of a shift register according to another embodiment of the present disclosure;

[0014] FIG. 4 is a structural schematic diagram of a shift register according to another embodiment of the present disclosure;

[0015] FIG. 5 is a structural schematic diagram of a shift register according to another embodiment of the present disclosure;

[0016] FIG. 6 is a structural schematic diagram of a shift register according to another embodiment of the present disclosure;

[0017] FIG. 7 is a structural schematic diagram of a shift register according to another embodiment of the present disclosure;

[0018] FIG. 8A is a structural schematic diagram of a shift register according to another embodiment of the present disclosure;

[0019] FIG. 8B is a signal timing diagram of the shift register according to an embodiment of the present disclosure;

[0020] FIG. 9 is a structural schematic diagram of a shift register according to another embodiment of the present disclosure;

[0021] FIG. 10A is a structural schematic diagram of a shift register according to another embodiment of the present disclosure;

[0022] FIG. 10B is a signal timing diagram of the shift register according to an embodiment of the present disclosure;

[0023] FIG. 11 is a structural schematic diagram of a shift register according to another embodiment of the present disclosure;

[0024] FIG. 12A is a structural schematic diagram of a shift register according to another embodiment of the present disclosure;

[0025] FIG. 12B is a signal timing diagram of a shift register according to another embodiment of the present disclosure;

[0026] FIG. 12C is a signal timing diagram of a shift register according to another embodiment of the present disclosure;

[0027] FIG. 13 is a structural schematic diagram of a shift register according to another embodiment of the present disclosure;

[0028] FIG. 14 is a structural schematic diagram of a shift register according to another embodiment of the present disclosure;

[0029] FIG. 15 is a structural schematic diagram of a shift register according to another embodiment of the present disclosure;

[0030] FIG. 16 is a signal timing diagram of a shift register according to another embodiment of the present disclosure;

[0031] FIGS. 17A and 17B are current schematic diagrams of a shift register according to an example;

[0032] FIGS. 18A and 18B are current schematic diagrams of a shift register according to an embodiment of the present disclosure;

[0033] FIG. 19 is a structural schematic diagram of a driving circuit according to an embodiment of the present disclosure;

[0034] FIG. 20 is a structural schematic diagram of a driving circuit according to another embodiment of the present disclosure;

[0035] FIG. 21 is a structural schematic diagram of a display device according to an embodiment of the present disclosure; and

[0036] FIG. 22 is a flowchart of a driving method according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0037] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the following will be combined with the accompanying drawings to make a clear and complete description of the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the scope of protection of the present disclosure. It should be noted that throughout the drawings, the same elements are denoted by the same or similar reference numerals. In the following description, some specific embodiments are only for the purpose of description, and should not be understood as any limitation on the present disclosure, but only as examples of the embodiments of the present disclosure. When it is possible to cause confusion to the understanding of the present disclosure, the conventional structures or configurations will be omitted. It should be noted that the shapes and sizes of the components in the drawings do not reflect the true size and ratio, but only illustrate the content of the embodiments of the present disclosure.

[0038] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should be understood as the general meaning understood by a person of ordinary skill in the art. The "first", "second" and similar words used in the embodiments of the present disclosure do not represent any order, number or importance, but are only used to distinguish different components.

[0039] In addition, in the description of the embodiments of the present disclosure, the term "connected" or "connected to" can mean that two components are directly connected, or that two components are connected via one or more other components. In addition, the two components can be connected or coupled by wired or wireless means.

[0040] The source and drain of the switching transistor used in the embodiments of the present disclosure are symmetrical, so the source and drain can be interchangeable. In the embodiments of the present disclosure, according to its function, the gate can be called the control electrode, one of the source and drain can be called the first electrode, and the other of the source and drain can be called the second electrode.

[0041] In addition, in the description of the embodiments of the present disclosure, the terms "first power supply voltage" and "second power supply voltage" are only used to distinguish the amplitudes of the two power supply voltages. For example, the following is described by taking "first power supply voltage" as a relatively high voltage, and "second power supply voltage" and "third power supply voltage" as relatively low voltages. Those skilled in the art can understand that the present disclosure is not limited thereto.

[0042] It should be noted that in the description of the embodiments of the present disclosure, INPUT1 can represent both a first input signal terminal and a first input signal provided by a first input terminal. Similarly, CB can represent both a first clock terminal and a first clock signal provided by the first clock terminal, OUT can represent both a first output terminal and a first output signal output by the first output terminal, and VGH1 and VGL1 can represent both a power supply terminal and a power supply voltage provided by the power supply terminal. For example, the power supply VGH1 can provide a high-level voltage, and the power supply VGL1 can provide a low-level voltage. The following embodiments are the same as this, and will not be described again.

[0043] FIG. 1A is a structural schematic diagram of an example pixel circuit, and FIG. 1B is a signal timing diagram of the pixel circuit shown in FIG. 1A.

[0044] FIG. 1A shows an OLED pixel circuit 100, which is a 9T1C circuit. The pixel circuit 100 includes transistors M1 to M9 and a capacitor Cst. The transistor M4 and the transistor M9 in the pixel circuit 100 share a scan signal Pgate.

[0045] As shown in FIG. 1B, when the pixel circuit 100 is charged, the light-emitting control signals EM1 and EM2 are high, the transistors M5 and M6 are turned off, and the light-emitting element OLED is turned off.

[0046] In the D1 stage, the reset signals Reset_p1 and Reset_p2 are low, the transistors M7 and M8 are turned on, the initialization signal Vinit2 is written to the node A4, and the initialization signal Vinit3 is written to the node A2.

[0047] In the D2 stage, the reset signals Reset_p1 and Reset_p2 are high, the transistors M7 and M8 are turned off, the reset signal Reset_n is high, and the scan signal Pgate is low, so that the transistors M1, M9, M3, and M4 are turned on, the initialization signal Vinit1 is written to the node A1, and the data signal Data is written to the nodes A2 and A3.

[0048] In the D3 stage, the scan signal Ngate is high, the transistors M9 and M4 are turned off, the scan signal Ngate is high, and the reset signal Reset_n is still high, so that the transistors M1 and M2 are turned on, and the initialization signal Vinit1 is written to the node A3.

[0049] In the D4 stage, the scan signal Ngate keeps high, the reset signal Reset_n becomes low, and the scan signal Pgate becomes low. Then the transistor M2, the transistor M4 and the transistor M9 are turned on, and the data signal Data is written into the node A2, the node A3, the node A5 and the node A1. After the completion of the energization of the capacitor Cst, the potentials of the node A3 and the node A1 are Vdata+Vth_Td. Vdata is the voltage of the data signal Data, and Vth_Td is the threshold voltage of the transistor M3.

[0050] In the D5 stage, the scan signal Ngate is low, the scan signal Pgate is high, the transistor M2, the transistor M4 and the transistor M9 are turned off. The reset signals Reset_p1 and Reset_p2 are low, and the transistor M7 and the transistor M8 are turned on. Then the initialization signal Vinit2 is written into the node A4. The initialization signal Vinit3 is written into the node A2. If Vinit3>Vdata, the potential of the node A3 is Vinit3+Vth_Td, otherwise the potential of the node A3 is unchanged.

[0051] In the D6 stage, the reset signals Reset_p1 and Reset_p2 are high, the transistor M7 and the transistor M8 are turned off, the light emission control EM1 is low, and the transistor M5 is turned on. If the pull-up power voltage VDD>Vdata, the potential of the node A3 is VDD+Vth_Td, otherwise the potential of the node A3 is unchanged.

[0052] In the D7 stage, the light emission control EM2 is low, the transistor M6 is turned on, and the light emitting element OLED emits light. The light emission current is determined by the voltages of the node A1 and the node A2. The potential of the node A1 is Vdata+Vth_Td, and the potential of the node A2 is VDD. Then the light emission current Id=K(Vdata-VDD) 2 wherein K is determined by the characteristics of the TFT, such as W / L, Cox, mu, etc.

[0053] The scan signals Ngate and Pgate, the reset signals Reset_p1, Reset_p2 and Reset_n, and the light emission control signals EM1 and EM2 can be provided by the GOA circuit. When the leakage phenomenon occurs in the GOA circuit, the driving capability of the GOA circuit to the pixel circuit 100 is reduced, and the light emission effect of the light emitting element OLED is affected.

[0054] The present disclosure provides a shift register. A plurality of shift registers connected in cascade can provide a scanning signal, a reset signal and a light emitting control signal for pixel circuits of a plurality of pixel rows in a display panel, respectively. In the shift register provided by the present disclosure, by controlling the turn-on time node and the turn-off time node of the PMOS and the NMOS in the output circuit, the PMOS and the NMOS are prevented from being turned on at the same time, so that a large instantaneous current between the high and low power supply connected to the PMOS and the NMOS is avoided, thereby reducing the power consumption of the GOA circuit and enhancing the driving capability of the pixel circuit.

[0055] FIG. 2 is a structural schematic diagram of a shift register according to an embodiment of the present disclosure.

[0056] As shown in FIG. 2, the shift register 200 includes an input shift circuit 210, a first control circuit 220 and an output circuit 230.

[0057] In the embodiment of the present disclosure, the input shift circuit 210 is electrically connected with a first input end INPUT1, a first clock end CB, a second clock end CKn, a third clock end CK, a fourth clock end CBn and a reset end Trst.

[0058] The input shift circuit 210 controls the potential of the first node N1 by using a first clock signal CB from the first clock end CB, a second clock signal CKn from the second clock end CKn, a first input signal INPUT1 from the first input end INPUT1 and a reset signal Trst from the reset end Trst. The input shift circuit 210 also controls the potential of the second node N2 by using a third clock signal CK from the third clock end CK, a fourth clock signal CBn from the fourth clock end CBn and the potential of the first node N1.

[0059] For example, under the control of the first clock signal CB and the second clock signal CKn, the input shift circuit 210 controls the potential of the first node N1 by using the level of the reset signal Trst and the first input signal INPUT1. When the first clock signal CB and the second clock signal CKn control the input shift circuit 210 to be in a conductive state, the first input signal INPUT1 is written into the input shift circuit 210. Based on the level of the reset signal Trst and the first input signal INPUT1, the input shift circuit 210 controls the potential of the first node N1. For example, when at least one of the reset signal Trst and the first input signal INPUT1 is at a high level, the input shift circuit 210 controls the potential of the first node N1 to be at a low level. When both the reset signal Trst and the first input signal INPUT1 are at a low level, the input shift circuit 210 controls the potential of the first node N1 to be at a high level.

[0060] For example, the first clock signal CB, the second clock signal CKn, the third clock signal CK and the fourth clock signal CBn can jointly control the communication state and the cutoff state between the first input terminal INPUT1 and the second node N2. When the first clock signal CB, the second clock signal CKn, the third clock signal CK and the fourth clock signal CBn control the cutoff state between the first input terminal INPUT1 and the second node N2, the input shift circuit 210 controls the potential of the second node N2 based on the potential of the first node N1. For example, the input shift circuit 210 can control the potential of the second node N2 to be opposite to the potential of the first node N1. When the potential of the first node N1 is high, the input shift circuit 210 can control the potential of the second node N2 to be low. When the potential of the first node N1 is low, the input shift circuit 210 can control the potential of the second node N2 to be high.

[0061] In the embodiments of the present disclosure, the second node N2 can be a shift node, used to provide a shift signal. The shift signal provided by the second node N2 is provided to the first input terminal of the next stage shift register in the cascade to provide the first input signal for the next stage shift register.

[0062] In the embodiments of the present disclosure, the first control circuit 220 is electrically connected with the first node N1, the third node N3 and the first control terminal CKo1.

[0063] The first control circuit 220 controls the potential of the third node N3 by using the potential of the second node N2 and the first control signal CKo1 from the first control terminal CKo1. The first control circuit 220 controls the potential of the third node N3 by using the potential of the second node N2 and the level of the first control signal CKo1. For example, when at least one of the potential of the second node N2 and the level of the first control signal CKo1 is high, the first control circuit 220 controls the potential of the third node N3 to be low. When the potential of the second node N2 and the level of the first control signal CKo1 are both low, the first control circuit 220 controls the potential of the third node N3 to be high.

[0064] In the embodiments of the present disclosure, the output circuit 230 is electrically connected with the first node N1, the third node N3, the first power supply VGH1, the second power supply VGL1 and the output terminal OUT. The output circuit 230 controls the first power supply voltage VGH1 of the first power supply VGH1 or the second power supply voltage VGL1 of the second power supply VGL1 to be provided to the output terminal OUT as an output signal OUT by using the potential of the first node N1 and the potential of the third node N3. The output signal OUT can be a scanning signal, a reset signal, a light-emitting control signal and the like provided to a pixel circuit.

[0065] The first node N1 is a pull-up node, and the third node N3 is a pull-down node. For example, the potential of the first node N1 can control the first power supply VGH1 and the output terminal OUT to be in a communication state or a cutoff state. When the first power supply VGH1 and the output terminal OUT are in the communication state, the output circuit 230 provides the first power supply voltage VGH1 to the output terminal OUT, the first power supply voltage VGH1 pulls up the potential of the output terminal OUT, and a high-level signal is output. The potential of the third node N3 can control the second power supply VGL1 and the output terminal OUT to be in a communication state or a cutoff state. When the second power supply VGL1 and the output terminal OUT are in the communication state, the output circuit 230 provides the second power supply voltage VGL1 to the output terminal OUT, the second power supply voltage VGL1 pulls down the potential of the output terminal OUT, and a low-level signal is output.

[0066] In the embodiments of the present disclosure, the communication and cutoff states of the first power supply VGH1 and the second power supply VGL1 with the output terminal OUT are controlled by the potentials of the first node N1 and the third node N3, respectively, so that the first power supply VGH1 and the second power supply VGL1 are prevented from being in the communication state with the output terminal OUT at the same time, thereby avoiding the occurrence of a transient large current between the first power supply VGH1 and the second power supply VGL1.

[0067] The potential of the first node N1 is controlled by the level changes of the first input signal INPUT1, the first clock signal CB, the second clock signal CKn, and the reset signal Trst. In the power-on / power-off or blanking phase of the shift register, the reset signal Trst can be set to a high level, so as to reset the output terminal OUT and control the potential of the output terminal OUT to be a high level. In the normal display phase, the reset signal Trst can be stably maintained at a low level. In this case, the potential of the first node N1 is affected by the potential of the written first input signal INPUT1, and the first clock signal CB and the second clock signal CKn can control the time node of writing the first input signal 1NPUT1 to the input shift circuit 210, thereby controlling the time node of the potential change of the first node N1.

[0068] The potential of the third node N3 is controlled by the potential of the second node N2 and the level change of the first control signal CKo. The potential of the second node N2 is determined based on the potential of the first node N1, and in the case where the potential of the first node N1 has been determined, the potential of the third node N3 is controlled by controlling the level change of the first control signal CKo1. Therefore, by controlling the time node of the level change of the first control signal CKo1, the time node of the potential change of the third node N3 can be controlled.

[0069] In the embodiments of the present disclosure, the first node N1 and the third node N3 control the pull-up node and the pull-down node respectively, so that the first power supply VGH1 and the second power supply VGL1 can be controlled to be in the communication state and the cut-off state with the output terminal OUT respectively. The time node of the potential change of the first node N1 and the third node N3 can be controlled by the level change of the first clock signal CB, the second clock signal CKn and the first control signal CKo1. For example, the first control signal CKo1 is controlled to be out of synchronization with the level change of the first clock signal CB or the second clock signal CKn, so that the potential of the first node N1 and the third node N3 will not change synchronously, thereby avoiding the simultaneous communication of the first power supply VGH1 and the second power supply VGL1 with the output terminal OUT.

[0070] For example, when the second power supply VGL1 is in the cut-off state with the output terminal OUT, the first power supply VGH1 is controlled to be in the communication state with the output terminal OUT by the potential of the first node N1, so that the output terminal OUT can stably output the high-level output signal OUT. After the first power supply VGH1 is controlled to be in the cut-off state with the output terminal OUT by the potential of the first node N1, the second power supply VGL1 is controlled to be in the communication state with the output terminal OUT by the potential of the third node N3, so that the output terminal OUT can stably output the low-level output signal OUT. After the second power supply VGL1 is switched from the communication state to the cut-off state with the output terminal OUT, the first power supply VGH1 is controlled to be in the communication state with the output terminal OUT by the potential of the first node N1 again. In this case, by controlling the time node of the potential change of the first node N1 and the third node N3, the instantaneous large current between the first power supply VGH1 and the second power supply VGL1 can be avoided, the power consumption of the shift register 100 is reduced, and the driving capability is enhanced.

[0071] FIG. 3 is a structural schematic diagram of a shift register according to another embodiment of the present disclosure.

[0072] As shown in FIG. 3, the shift register 300 includes an input shift circuit 310, a first control circuit 320, an output circuit 330 and a second control circuit 340.

[0073] The input shift circuit 310, the first control circuit 320 and the output circuit 330 are similar to the input shift circuit 210, the first control circuit 220 and the output circuit 230 described above respectively, and will not be described again for simplicity.

[0074] In the embodiments of the present disclosure, the second control circuit 340 is electrically connected with the fourth node N4, the first node N1 and the second control terminal CKo2, or the second control circuit 340 is electrically connected with the fourth node N4, the first node N1 and the second clock terminal CKn. The second control circuit 340 controls the potential of the first node N1 by using the potential of the fourth node N4 and the second control signal CKo2 from the second control terminal CKo2, or controls the potential of the first node N1 by using the second clock signal CKn and the potential of the fourth node N4.

[0075] The input shift circuit 310 is electrically connected to the fourth node N4, and controls the potential of the fourth node N4 by using the first clock signal CB, the second clock signal CKn, the first input signal INPUT1 and the reset signal Trst.

[0076] In the embodiments of the present disclosure, the second control circuit 340 is also electrically connected to the second node N2. The second control circuit 340 controls the potential of the second node N2 by using the potential of the fourth node N4. For example, the second control circuit 340 can control the potential of the second node N2 to be opposite to the potential of the fourth node N4. When the potential of the fourth node N4 is high, the second control circuit 340 can control the potential of the second node N2 to be low. When the potential of the fourth node N4 is low, the second control circuit 340 can control the potential of the second node N2 to be high.

[0077] The time node of the potential change of the first node N1 is controlled by the second control signal CKo2 and the potential of the second node N2, or is controlled by the second clock signal CKn and the potential of the second node N2. In the case that the potential of the second node N2 is determined based on the potential of the first node N1, by controlling the time node of the level change of the second control signal CKo2 or the second clock signal CKn, the time node of the potential change of the first node N1 can be controlled, so that the time node of the first power supply VGH1 and the output terminal OUT being in the off state or the connected state can be controlled.

[0078] The time node of the potential change of the third node N3 is controlled by the first control signal CKo1 and the potential of the second node N2. In the case that the potential of the second node N2 is determined based on the potential of the first node N1, by controlling the time node of the level change of the first control signal CKo1, the time node of the potential change of the third node N3 can be controlled, so that the time node of the second power supply VGL1 and the output terminal OUT being in the off state or the connected state can be controlled.

[0079] In the embodiment of the present disclosure, the level of the second control signal CKo2 or the second clock signal CKn can be changed, and the level of the first control signal CKo1 can be changed at the same time. When the first input signal INPUT1 is a multi-pulse signal, the output terminal OUT can output an output signal OUT with multiple pulses.

[0080] FIG. 4 is a structural schematic diagram of a shift register according to another embodiment of the present disclosure.

[0081] As shown in FIG. 4, the shift register 400 includes an input shift circuit 410, a first control circuit 420, an output circuit 430, and a third control circuit 450.

[0082] The input shift circuit 410, the first control circuit 420, and the output circuit 430 are similar to the input shift circuit 210, the first control circuit 220, and the output circuit 230 described above, respectively, and will not be described again for simplicity.

[0083] In the embodiment of the present disclosure, the third control circuit 450 is electrically connected to the enable terminal GEN, the first node N1, and the second node N2. The third control circuit 450 controls the potential of the fifth node N5 by using the potential of the first node N1, the potential of the second node N2, and the enable signal GEN from the enable terminal GEN. The first control circuit 420 is electrically connected to the fifth node N5, and the first control circuit 420 controls the potential of the third node N3 by using the potential of the fifth node N5, the potential of the second node N2, and the first control signal CKo1.

[0084] In the embodiment of the present disclosure, the enable signal GEN can control the output signal OUT output by the output terminal OUT to locally refresh the pixel circuit. For example, the output signal OUT can be a scanning signal used to drive a P-type transistor in the pixel circuit. For example, when the level of the input signal OUT is low, the P-type transistor is turned on, and a data signal can be written, thereby realizing picture refresh. When the level of the output signal OUT is high, the P-type transistor is turned off, and the data signal cannot be written, thereby realizing picture non-refresh and keeping unchanged.

[0085] In the embodiment of the present disclosure, the enable signal GEN controls the potential of the fifth node N5, thereby controlling the potential of the third node N3. Based on the potential of the third node N3, the output terminal OUT can output a high-level signal or a low-level signal, thereby controlling whether a transistor in the pixel circuit is turned on or not, and realizing picture refresh or picture keeping.

[0086] In the embodiment of the present disclosure, the potential of the first node N1 and the potential of the second node N2 can control the enable terminal GEN and the fifth node N5 to be in a communication state or a cutoff state. When the potential of the first node N1 and the potential of the second node N2 control the enable terminal GEN and the fifth node N5 to be in the communication state, the third control circuit 450 writes the enable signal GEN to the fifth node N5.

[0087] In the embodiment of the present disclosure, the first control circuit 420 can control the potential of the third node N3 based on the levels of three signals shown in FIG. 4. For example, when at least one of the potential of the second node N2, the potential of the fifth node N5 and the level of the first control signal CKo1 is high, the first control circuit 420 controls the potential of the third node N3 to be low. When the potential of the second node N2, the potential of the fifth node N5 and the level of the first control signal CKo1 are all low, the first control circuit 420 controls the potential of the third node N3 to be high. For example, in this case, the corresponding pixel circuit is refreshed when the timing of the enable signal GEN changes to low. The corresponding pixel circuit is not refreshed when the timing of the enable signal GEN remains high.

[0088] In the embodiment of the present disclosure, the first control circuit 420 can also control the potential of the third node N3 based on the levels of only two signals. For example, when at least one of the potential of the second node N2 and the potential of the fifth node N5 is high, the first control circuit 420 controls the potential of the third node N3 to be low. When the potential of the second node N2 and the potential of the fifth node N5 are both low, the first control circuit 420 controls the potential of the third node N3 to be high. For example, in this case, the corresponding pixel circuit is refreshed when the timing of the enable signal GEN changes at the same time as the timing of the first control signal CKo1. The corresponding pixel circuit is not refreshed when the timing of the enable signal GEN remains high.

[0089] FIG. 5 is a structural schematic diagram of a shift register according to another embodiment of the present disclosure.

[0090] As shown in FIG. 5, the shift register 500 includes an input shift circuit 510, a first control circuit 520, an output circuit 530 and a fourth control circuit 560.

[0091] The input shift circuit 510, the first control circuit 520 and the output circuit 530 are similar to the input shift circuit 210, the first control circuit 220 and the output circuit 230 described above respectively, and will not be described again for simplicity.

[0092] In the embodiment of the present disclosure, the fourth control circuit 560 is electrically connected with the first node N1, the reset terminal Trst, the enable terminal GEN, and the fifth node N5. The fourth control circuit 560 controls the potential of the fifth node N5 by using the potential of the first node N1, the reset signal Trst, and the enable signal GEN from the enable terminal GEN.

[0093] In the embodiment of the present disclosure, the potential of the first node N1 and the level of the reset signal Trst can control the enable terminal GEN and the fifth node N5 to be in a communication state or a cutoff state. When the potential of the first node N1 and the level of the reset signal Trst control the enable terminal GEN and the fifth node N5 to be in the communication state, the fourth control circuit 560 writes the enable signal GEN to the fifth node N5. The enable signal GEN controls the potential of the fifth node N5, thereby achieving the control of the potential of the third node N3. Based on the potential of the third node N3, the output terminal OUT can output a high-level signal or a low-level signal, thereby controlling whether the transistor in the pixel circuit is turned on, achieving the picture refresh or picture retention.

[0094] In the embodiment of the present disclosure, by changing the potential of the first node N1 and the level of the reset signal Trst, the time node of the level change of the fifth node N5 is controlled, and the time node of the potential change of the third node N3 is controlled in combination with the level change of the first control signal CKo1 and the potential change of the second node N2, thereby when the first input signal INPUT1 is a multi-pulse signal, the output terminal OUT can output an output signal OUT with multiple pulses, and the display panel is locally refreshed by using the multi-pulse signal.

[0095] FIG. 6 is a structural schematic diagram of a shift register according to another embodiment of the present disclosure.

[0096] As shown in FIG. 6, the shift register 600 includes an input shift circuit 610, a first control circuit 620, an output circuit 630, and a fifth control circuit 670.

[0097] The input shift circuit 610, the first control circuit 620, and the output circuit 630 are similar to the input shift circuit 210, the first control circuit 220, and the output circuit 230 described above, respectively, and will not be described again for simplicity.

[0098] In the embodiment of the present disclosure, the fifth control circuit 670 is electrically connected with the first node N1, the second node N2, the enable terminal GEN, the fifth node N5, the first input terminal INPUT1 and the second input terminal INPUT2. The fifth control circuit 670 controls the potential of the fifth node N5 by using the potential of the first node N1, the potential of the second node N2, the first input signal INPUT1, the second input signal INPUT2 from the second input terminal INPUT2 and the enable signal GEN from the enable terminal GEN.

[0099] In the embodiment of the present disclosure, the second input terminal INPUT2 is electrically connected with the first node of the upper stage shift register in the cascade. The potential of the first node N1, the potential of the second node N2, the first input signal INPUT1, the second input signal INPUT2 can control the enable terminal GEN and the fifth node N5 to be in the communication state or the cutoff state. When the potential of the first node N1, the potential of the second node N2, the first input signal INPUT1, the second input signal INPUT2 control the enable terminal GEN and the fifth node N5 to be in the communication state, the fifth control circuit 670 writes the enable signal GEN to the fifth node N5. The enable signal GEN controls the potential of the fifth node N5, thereby realizing the control of the potential of the third node N3. Based on the potential of the third node N3, the output terminal OUT can be controlled to output the high level signal or the low level signal, thereby controlling whether the transistor in the pixel circuit is turned on, realizing the picture refresh or the picture retention.

[0100] In the embodiment of the present disclosure, the first control circuit 520 can be used to control the potential of the third node N3 based on the levels of three signals as shown in FIG. 5. The first control circuit 520 can also be used to control the potential of the third node N3 based on the levels of only two signals. The control process of the first control circuit 520 on the potential of the third node N3 can refer to the control process of the first control circuit 420, which will not be described here for simplicity.

[0101] In the embodiment of the present disclosure, by changing the levels of the potential of the first node N1, the potential of the second node N2, the first input signal INPUT1 and the second input signal INPUT2, the time node of the level change of the fifth node N5 is controlled, and the time node of the potential change of the third node N3 is controlled in combination with the level change of the first control signal CKo1 and the potential change of the second node N2, thereby when the first input signal INPUT1 is a multi-pulse-width single pulse signal, the output terminal OUT can be controlled to output an output signal with multi-pulse-width single pulse, and the display panel is locally refreshed by using the multi-pulse-width single pulse. The duration of the effective level of the output signal with multi-pulse-width single pulse is greater than the duration of the effective level of the output signal with single-pulse-width single pulse, and the duration of the effective level of the output signal with single-pulse-width single pulse can be affected by the pulse width of the clock signal.

[0102] FIG. 7 is a structural schematic diagram of a shift register according to another embodiment of the present disclosure. FIG. 7 shows a logic circuit diagram of the shift register of FIG. 2.

[0103] As shown in FIG. 7, the shift register 700 includes an input shift circuit 710, a first control circuit 720, and an output circuit 730.

[0104] In the embodiment of the present disclosure, the input shift circuit 710 includes a fifth transmission gate Tg5, a sixth transmission gate Tg6, a fifth NOR gate NOR5, and a second inverter INV2.

[0105] The first control terminal of the fifth transmission gate Tg5 is electrically connected to the first clock end CB, the second control terminal of the fifth transmission gate Tg5 is electrically connected to the second clock end CKn, the input terminal of the fifth transmission gate Tg5 is electrically connected to the first input end INPUT1, and the output terminal of the fifth transmission gate Tg5 is electrically connected to the ninth node N9. The first control terminal CKo1 of the sixth transmission gate Tg6 is electrically connected to the third clock end CK, the second control terminal of the sixth transmission gate Tg6 is electrically connected to the fourth clock end CBn, the input terminal of the sixth transmission gate Tg6 is electrically connected to the ninth node N9, and the output terminal of the sixth transmission gate Tg6 is electrically connected to the second node N2. The first input terminal of the fifth NOR gate NOR5 is electrically connected to the reset end Trst, the second input terminal of the fifth NOR gate NOR5 is electrically connected to the ninth node N9, and the output terminal of the fifth NOR gate NOR5 is electrically connected to the first node N1. The input terminal of the second inverter INV2 is electrically connected to the first node N1, and the output terminal of the second inverter INV2 is electrically connected to the second node N2.

[0106] In the embodiment of the present disclosure, the first clock signal CB and the second clock signal CKn control the fifth transmission gate Tg5 to be in a conductive state or a non-conductive state. When the fifth transmission gate Tg5 is in the conductive state, the first input signal INPUT1 is written to the ninth node N9. When the fifth transmission gate Tg5 is in the non-conductive state, the potential of the ninth node N9 remains the potential of the previous stage.

[0107] In the embodiment of the present disclosure, the fifth NOR gate NOR5 performs a NOR operation on the potential of the ninth node N9 and the level of the reset signal Trst. For example, a high potential can be represented as a digital signal “1”, and a low potential can be represented as a digital signal “0”. When at least one of the potential of the ninth node N9 and the reset signal Trst is high, the fifth NOR gate NOR5 controls the potential of the first node N1 to be low. When both the potential of the ninth node N9 and the reset signal Trst are low, the fifth NOR gate NOR5 controls the potential of the first node N1 to be high.

[0108] In the embodiment of the present disclosure, the second NOT gate INV2 performs a NOT operation on the potential of the first node N1. When the first node N1 is at a high level, the second NOT gate INV2 controls the potential of the second node N2 to be at a low level. When the first node N1 is at a low level, the second NOT gate INV2 controls the potential of the second node N2 to be at a high level.

[0109] In the embodiment of the present disclosure, the third clock signal CK and the fourth clock signal CBn control the sixth transmission gate Tg6 to be in a conductive or non-conductive state. When the sixth transmission gate Tg6 is in the conductive state, the second node N2 is written to the ninth node N9.

[0110] The signal is transmitted by using the transmission gate, and the voltage drop can be prevented based on the low on-resistance of the transmission gate, so that the stability in voltage transmission is maintained.

[0111] In the embodiment of the present disclosure, the first control circuit 720 includes a first NOR gate NOR1. The first input end of the first NOR gate NOR1 is electrically connected to the second node N2, the second input end of the first NOR gate NOR1 is electrically connected to the first control end CKo1, and the output end of the first NOR gate NOR1 is electrically connected to the third node N3.

[0112] In the embodiment of the present disclosure, the first NOR gate NOR1 performs a NOR operation on the potential of the second node N2 and the level of the first control signal CKo1. When at least one of the potential of the second node N2 and the level of the first control signal CKo1 is at a high level, the first NOR gate NOR1 controls the potential of the third node N3 to be at a low level. When the potential of the second node N2 and the level of the first control signal CKo1 are both at a low level, the first NOR gate NOR1 controls the potential of the third node N3 to be at a high level.

[0113] In the embodiment of the present disclosure, the output circuit 730 includes a first transistor T1 and a second transistor T2. The first transistor T1 is a PMOS transistor and the second transistor T2 is an NMOS transistor. When the potential of the first node N1 is at a low level, the first transistor T1 is turned on, and the first power supply voltage VGH1 is provided to the output end OUT. When the potential of the third node N3 is at a high level, the second transistor T2 is turned on, and the second power supply voltage VGL1 is provided to the output end OUT.

[0114] In the embodiment of the present disclosure, by changing the potentials of the first node N1 and the third node N3, the first transistor T1 can be turned off first and then the second transistor T2 can be turned on, and the second transistor T2 can be turned off first and then the first transistor T1 can be turned on, which avoids the first transistor T1 and the second transistor T2 in the output circuit 730 being turned on at the same time, and avoids the occurrence of a transient large current between the first power supply voltage VGH1 and the second power supply voltage VGL1.

[0115] FIG. 8A is a structural schematic diagram of a shift register according to another embodiment of the present disclosure. FIG. 8A is a circuit structure diagram of the shift register shown in FIG. 7.

[0116] As shown in FIG. 8A, the shift register 800 includes an input shift circuit 810, a first control circuit 820, and an output circuit 830.

[0117] In the embodiment of the present disclosure, the input shift circuit 810 includes the third transistor T3 to the twelfth transistor T12, the first control circuit 820 includes the thirteenth transistor T13 to the sixteenth transistor T16, and the output circuit 830 includes the first transistor T1 and the second transistor T2.

[0118] The control electrode of the first transistor T1 is electrically connected to the first node N1, the first electrode of the first transistor T1 is electrically connected to the first power supply voltage VGH1, and the second electrode of the first transistor T1 is electrically connected to the output terminal OUT.

[0119] The control electrode of the second transistor T2 is electrically connected to the third node N3, the first electrode of the second transistor T2 is electrically connected to the output terminal OUT, and the second electrode of the second transistor T2 is electrically connected to the second power supply voltage VGL1.

[0120] The control electrode of the third transistor T3 is electrically connected to the first clock terminal CB, the first electrode of the third transistor T3 is electrically connected to the first input terminal INPUT1, and the second electrode of the third transistor T3 is electrically connected to the ninth node N9.

[0121] The control electrode of the fourth transistor T4 is electrically connected to the first clock terminal CKn, the first electrode of the fourth transistor T4 is electrically connected to the first input terminal INPUT1, and the second electrode of the fourth transistor T4 is electrically connected to the ninth node N9.

[0122] The control electrode of the fifth transistor T5 is electrically connected to the reset terminal Trst, the first electrode of the fifth transistor T5 is electrically connected to the power supply VGH2, and the second electrode of the fifth transistor T5 is electrically connected to the first electrode of the sixth transistor T6.

[0123] The control electrode of the sixth transistor T6 is electrically connected to the ninth node N9, and the second electrode of the sixth transistor T6 is electrically connected to the first node N1.

[0124] The control electrode of the seventh transistor T7 is electrically connected to the ninth node N9, the first electrode of the seventh transistor T7 is electrically connected to the first node N1, and the second electrode of the seventh transistor T7 is electrically connected to the power supply VGL2.

[0125] The control electrode of the eighth transistor T8 is electrically connected to the reset terminal Trst, the first electrode of the eighth transistor T8 is electrically connected to the first node N1, and the second electrode of the eighth transistor T8 is electrically connected to the power supply VGL2.

[0126] The control electrode of the ninth transistor T9 is electrically connected to the third clock terminal CK, the first electrode of the ninth transistor T9 is electrically connected to the ninth node N9, and the second electrode of the ninth transistor T9 is electrically connected to the second node N2.

[0127] The control electrode of the tenth transistor T10 is electrically connected to the fourth clock terminal CBn, the first electrode of the tenth transistor T10 is electrically connected to the ninth node N9, and the second electrode of the tenth transistor T10 is electrically connected to the second node N2.

[0128] The control electrode of the eleventh transistor T11 is electrically connected to the first node N1, the first electrode of the eleventh transistor T11 is electrically connected to the power supply VGH2, and the second electrode of the eleventh transistor T11 is electrically connected to the second node N2.

[0129] The control electrode of the twelfth transistor T12 is electrically connected to the first node N1, the first electrode of the twelfth transistor T12 is electrically connected to the second node N2, and the second electrode of the twelfth transistor T12 is electrically connected to the power supply VGL2.

[0130] The control electrode of the thirteenth transistor T13 is electrically connected to the first control terminal CKo1, the first electrode of the thirteenth transistor T13 is electrically connected to the power supply VGH2, and the second electrode of the thirteenth transistor T13 is electrically connected to the first electrode of the fourteenth transistor T14.

[0131] The control electrode of the fourteenth transistor T14 is electrically connected to the second node N2, and the second electrode of the fourteenth transistor T14 is electrically connected to the third node N3.

[0132] The control electrode of the fifteenth transistor T15 is electrically connected to the second node N2, the first electrode of the fifteenth transistor T15 is electrically connected to the third node N3, and the second electrode of the fifteenth transistor T15 is electrically connected to the power supply VGL2.

[0133] The control electrode of the sixteenth transistor T16 is electrically connected to the first control terminal CKo1, the first electrode of the thirteenth transistor T13 is electrically connected to the third node N3, and the second electrode of the thirteenth transistor T13 is electrically connected to the power supply VGL2.

[0134] In the embodiments of the present disclosure, the first transistor T1, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the ninth transistor T9, the eleventh transistor T11, the thirteenth transistor T13 and the fifteenth transistor T15 are P-type TFT transistors. For example, the active layer is a low-temperature polysilicon (LTPS) thin film transistor. The second transistor T2, the fourth transistor T4, the seventh transistor T7, the eighth transistor T8, the tenth transistor T10, the twelfth transistor T113, the fourteenth transistor T14 and the sixteenth transistor T16 are N-type TFT transistors. For example, the active layer is an indium gallium zinc oxide (IGZO) thin film transistor. Those skilled in the art can understand that, in the present disclosure, the first transistor T1, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the ninth transistor T9, the eleventh transistor T11, the thirteenth transistor T13 and the fifteenth transistor T15 are N-type TFT transistors, and the second transistor T2, the fourth transistor T4, the seventh transistor T7, the eighth transistor T8, the tenth transistor T10, the twelfth transistor T113, the fourteenth transistor T14 and the sixteenth transistor T16 are P-type TFT transistors, and the levels of the gate drive signals of the respective transistors can be changed accordingly.

[0135] In the description of the embodiments of the present disclosure, the first node N1 to the ninth node N9 do not represent actual components, but represent the convergence points of the connection of the relevant circuits in the circuit diagram.

[0136] FIG. 8B is a signal timing diagram of a shift register according to an embodiment of the present disclosure.

[0137] The working process of the shift register 800 provided by the embodiments of the present disclosure will be described below by taking the structure of the shift register 800 shown in FIG. 8A as an example and in combination with the signal timing diagram shown in FIG. 8B. The working process of the shift register 800 is divided into four periods. The first control signal CKo1 is provided to the shift register 800, and the signal CBo1 is provided to the first control signal end of the next stage shift register connected in cascade with the shift register 800.

[0138] In the first period P1, the first clock signal CB is at a high level, the second clock signal CKn is at a low level, the third clock signal CK is at a low level, and the fourth clock signal CBn is at a high level. The reset signal Trst is at a low level, the first control signal CKo1 is at a low level, and the first input signal INPUT1 is at a low level.

[0139] The third transistor T3 and the fourth transistor T4 are turned off, the ninth transistor T9 and the tenth transistor T10 are turned on, and the potential of the ninth node N9 remains the high level of the previous stage. The fifth transistor T5 and the seventh transistor T7 are turned on, the sixth transistor T6 and the eighth transistor T8 are turned off, and the power supply voltage VGL2 is written into the first node N1, and the potential of the first node N1 is the low level.

[0140] The eleventh transistor T11 is turned on, the twelfth transistor T12 is turned off, the power supply voltage VGH2 is written into the second node N2, and the potential of the second node N2 is the high level. The thirteenth transistor T13 and the fifteenth transistor T15 are turned on, the fourteenth transistor T14 and the sixteenth transistor T16 are turned off, the power supply voltage VGL2 is written into the third node N3, and the potential of the third node N3 is the low level.

[0141] The first transistor T1 is turned on, the second transistor T2 is turned off, the first power supply voltage VGH1 is provided to the output terminal OUT through the first transistor T1, and the output signal OUT output by the output terminal OUT is the high level.

[0142] In the second period P2, the first clock signal CB is the low level, the second clock signal CKn is the high level, the third clock signal CK is the high level, and the fourth clock signal CBn is the low level. The reset signal Trst is the low level, the first control signal CKo1 is the high level, and the first input signal INPUT1 is the low level.

[0143] The third transistor T3 and the fourth transistor T4 are turned on, the ninth transistor T9 and the tenth transistor T10 are turned off, and the first input signal INOUT1 is written into the ninth node N9, and the potential of the ninth node N9 is pulled down to the low level. The fifth transistor T5 and the sixth transistor T6 are turned on, the seventh transistor T7 and the eighth transistor T8 are turned off, the power supply voltage VGH2 is written into the first node N1, and the potential of the first node N1 is the high level.

[0144] The eleventh transistor T11 is turned off, the twelfth transistor T12 is turned on, the power supply voltage VGL2 is written into the second node N2, and the potential of the second node N2 is the low level. The thirteenth transistor T13 and the fifteenth transistor T15 are turned off, the fourteenth transistor T14 and the sixteenth transistor T16 are turned on, the power supply voltage VGL2 is written into the third node N3, and the potential of the third node N3 is the low level.

[0145] The first transistor T1 and the second transistor T2 are turned off, and the output signal OUT output by the output terminal OUT is maintained as the high level.

[0146] In the third period P3, the first clock signal CB is at high level, the second clock signal CKn is at low level, the third clock signal CK is at low level, and the fourth clock signal CBn is at high level. The reset signal Trst is at low level, the first control signal CKo1 is at low level, and the first input signal INPUT1 is at high level.

[0147] The third transistor T3 and the fourth transistor T4 are turned off, the ninth transistor T9 and the tenth transistor T10 are turned on, and the potential of the ninth node N9 remains at low level of the previous stage. The fifth transistor T5 and the sixth transistor T6 are turned on, the seventh transistor T7 and the eighth transistor T8 are turned off, and the power supply voltage VGH2 is written into the first node N1, and the potential of the first node N1 is at high level.

[0148] The eleventh transistor T11 is turned off, the twelfth transistor T12 is turned on, the power supply voltage VGL2 is written into the second node N2, and the potential of the second node N2 is at low level. The thirteenth transistor T13 and the fourteenth transistor T14 are turned on, the fifteenth transistor T15 and the sixteenth transistor T16 are turned on, the power supply voltage VGH2 is written into the third node N3, and the potential of the third node N3 is at high level.

[0149] The first transistor T1 is turned off, the second transistor T2 is turned on, the second power supply voltage VGL1 is provided to the output terminal OUT through the second transistor T2, and the output signal OUT output by the output terminal OUT is at low level.

[0150] In the fourth period P4, the first clock signal CB is at low level, the second clock signal CKn is at high level, the third clock signal CK is at high level, and the fourth clock signal CBn is at low level. The reset signal Trst is at low level, the first control signal CKo1 is at high level, and the first input signal INPUT1 is at high level.

[0151] The third transistor T3 and the fourth transistor T4 are turned on, the ninth transistor T9 and the tenth transistor T10 are turned off, the first input signal INOUT1 is written into the ninth node N9, and the potential of the ninth node N9 is at high level. The fifth transistor T5 and the seventh transistor T7 are turned on, the sixth transistor T6 and the eighth transistor T8 are turned off, the power supply voltage VGL2 is written into the first node N1, and the potential of the first node N1 is at low level.

[0152] The eleventh transistor T11 is turned on, the twelfth transistor T12 is turned off, the power supply voltage VGH2 is written into the second node N2, and the potential of the second node N2 is at high level. The thirteenth transistor T13 and the fifteenth transistor T15 are turned on, the fourteenth transistor T14 and the sixteenth transistor T16 are turned off, the power supply voltage VGL2 is written into the third node N3, and the potential of the third node N3 is at low level.

[0153] The first transistor T1 is turned on, the second transistor T2 is turned off, the first power voltage VGH1 is provided to the output terminal OUT through the first transistor T1, and the output signal OUT output by the output terminal OUT is at a high level.

[0154] In the embodiment of the present disclosure, the output signal OUT output by the output terminal OUT can be used to drive the PMOS tube in the pixel circuit.

[0155] In the embodiment of the present disclosure, before the first time period P1, the reset signal Trst is at a high level. The first input signal INPUT1 is written to the ninth node N9, and the potential of the ninth node N9 is at a high level. The fifth transistor T5 and the sixth transistor T6 are turned off, the seventh transistor T7 and the eighth transistor T8 are turned on, the power voltage VGL2 is written to the first node N1, and the potential of the first node N1 is at a low level. The first transistor T1 is turned on, the first power voltage VGH1 is provided to the output terminal OUT through the first transistor T1, the potential of the output terminal OUT is reset, and the potential of the output terminal OUT is set to be high. In the embodiment of the present disclosure, in the second time period P2, when the first clock signal CB jumps from a high level to a low level and the second clock signal CKn jumps from a low level to a high level, the third transistor T3 and the fourth transistor T4 are turned on, and the first input signal INPUT1 is written to the ninth node N9. Since the potential of the reset signal Trst remains at a low level, when the potential of the ninth node N9 jumps to a low level, the potential of the first node N1 jumps to a high level at the same time, and the first transistor T1 is switched from a turned-on state to a turned-off state, the potential of the third node N3 remains at a low level, and the second transistor T2 is turned off.

[0156] In the third time period P3, when the first control signal CKo1 jumps from a high level to a low level, the thirteenth transistor T13 is turned on, and the sixteenth transistor T16 is turned off. Since the potential of the second node N2 remains at a low level, when the first control signal CKo1 jumps from a high level to a low level, the power voltage VGH1 is written to the third node N3 through the thirteenth transistor T13 and the fourteenth transistor T14, and the potential of the third node N3 jumps to a high level at the same time, and the second transistor T2 is switched from a turned-off state to a turned-on state. Since in the second time period P2, the first clock signal CB jumps from a low level to a high level and remains at a low level in the third time period P3, the level jump of the first input signal INPUT1 does not affect the potential change of the first node N1, and the first transistor T1 remains in a turned-off state.

[0157] In the third period P3, when the first control signal CKo1 jumps from low to high, the thirteenth transistor T13 is turned off and the sixteenth transistor T16 is turned on. Since the potential of the second node N2 remains low, when the first control signal CKo1 jumps from low to high, the power voltage VGL1 is written into the third node N3 through the sixteenth transistor T16, and the potential of the third node N3 jumps to low synchronously, at this time, the second transistor T2 is switched from the on state to the off state.

[0158] In the fourth period P4, when the first clock signal CB jumps from high to low and the second clock signal CKn jumps from low to high, at this time, the third transistor T3 and the fourth transistor T4 are turned on, and the first input signal INPUT1 is written into the ninth node N9. Since the potential of the reset signal Trst remains low, when the potential of the ninth node N9 jumps to high, the potential of the first node N1 jumps to low synchronously, at this time, the first transistor T1 is switched from the off state to the on state, the potential of the third node N3 remains low, and the second transistor T2 is turned off.

[0159] In the embodiments of the present disclosure, in the second period P2 and the third period P3, based on the level jump time of the first clock signal CB and the second clock signal CKn, the first transistor T1 is controlled to be switched from the on state to the off state and remain in the off state. In the third period P3, based on the level jump time of the first control signal CKo1, the second transistor T2 is controlled to be switched from the off state to the on state and then from the on state to the off state, and remain in the off state value to the fourth period P4. In the fourth period P4, based on the level jump time of the first clock signal CB and the second clock signal CKn, the first transistor T1 is controlled to be switched from the off state to the on state.

[0160] Through the level jump time of the first control signal CKo1, the first clock signal CB and the second clock signal CKn, when the second transistor T2 is in the off state, the first transistor T1 is first controlled to be in the off state, and then the second transistor T2 is controlled to be switched to the on state. After the output end OUT outputs the low level signal, the second transistor T2 is controlled to be switched to the off state, and then the first transistor T1 is controlled to be switched to the on state through the level jump time of the first control signal CKo1, the first clock signal CB and the second clock signal CKn. This makes the first transistor T1 and the second transistor T2 not in the on state at the same time, thereby avoiding the occurrence of instantaneous large current between the first power supply VGH1 and the second power supply VGL1, and avoiding the occurrence of leakage in the circuit.

[0161] The node separating the turn-on and turn-off states of the first transistor T1 and the second transistor T2 is separated into the first node N1 and the third node N3, and the potential changes of the first node N1 and the third node N3 are controlled by the first control signal CKo1, the first clock signal CB and the second clock signal CKn respectively, so that the first transistor T1 and the second transistor T2 are controlled respectively. The level jump time of the first control signal CKo1, the first clock signal CB and the second clock signal CKn controls the time when the first transistor T1 and the second transistor T2 are turned on and turned off, so that the first transistor T1 and the second transistor T2 are prevented from being in the turn-on state at the same time, thereby avoiding the leakage phenomenon in the circuit, reducing the power consumption of the circuit and enhancing the driving capability.

[0162] In the embodiments of the present disclosure, the fourth clock signal CBn and the first clock signal CB can have the same timing change, and the third clock signal CK and the second clock signal CKn can also have the same timing change. For example, the timing change of the fourth clock signal CBn can refer to the timing change of the first clock signal CB in FIG. 8B, and the timing change of the third clock signal CK can refer to the timing change of the second clock signal CKn in FIG. 8B. For example, the control electrode of the ninth transistor T9 can be electrically connected with the second clock terminal CKn, and the control electrode of the tenth transistor T10 can be electrically connected with the first clock terminal CB. This can also prevent the first transistor T1 and the second transistor T2 from being in the turn-on state at the same time, thereby avoiding the leakage phenomenon in the circuit, reducing the power consumption of the circuit and enhancing the driving capability. In addition, the number of signal lines in the circuit can be reduced, which is conducive to the narrowing of the display device.

[0163] In the embodiments of the present disclosure, the first power supply VGH1 can provide the same first power supply voltage VGH1 as the power supply VGH2, and the second power supply VGL1 can provide the same second power supply voltage VGL1 as the power supply VGL2. For example, the first electrode of the fifth transistor T5, the first electrode of the eleventh transistor T11, the first electrode of the thirteenth transistor T13 and the first electrode of the first transistor T1 can all be electrically connected with the first power supply VGH1. The second electrode of the seventh transistor T7, the second electrode of the eighth transistor T8, the second electrode of the twelfth transistor T12, the second electrode of the fifteenth transistor T15, the second electrode of the sixteenth transistor T16 and the second electrode of the second transistor T2 can all be electrically connected with the second power supply VGL1. By simplifying the power supply structure in the circuit, the number of power supply lines in the circuit can be reduced, which is conducive to the narrowing of the display device.

[0164] FIG. 9 is a structural schematic diagram of a shift register according to another embodiment of the present disclosure. FIG. 9 shows a logic circuit diagram of the shift register of FIG. 3.

[0165] As shown in FIG. 9, the shift register 900 includes an input shift circuit 910, a first control circuit 920, an output circuit 930, and a second control circuit 940.

[0166] In the embodiments of the present disclosure, the input shift circuit 910, the first control circuit 920, and the output circuit 930 are similar to the structures of the input shift circuit 710, the first control circuit 720, and the output circuit 730 described above, and are not described again for simplicity.

[0167] It should be noted that the potential change of the second node N2 shown in FIG. 9 is consistent with the potential change of the second node N2 shown in FIG. 7. The second node N2 shown in FIG. 9 can also be the output terminal of the second NOT gate INV2.

[0168] In the embodiments of the present disclosure, the second control circuit 940 includes a first NOT gate INV1 and a second NOR gate NOR2. The input terminal of the first NOT gate INV1 is electrically connected to the fourth node N4, and the output terminal of the first NOT gate INV1 is electrically connected to the second node N2.

[0169] The first input terminal of the second NOR gate NOR2 is electrically connected to the second control terminal CKo2 or the second clock terminal CKn, the second input terminal of the second NOR gate NOR2 is electrically connected to the second node N2, and the output terminal of the second NOR gate NOR2 is electrically connected to the first node N1.

[0170] In the embodiments of the present disclosure, the fifth NOR gate NOR5 performs NOR operation on the level of the reset signal Trst and the ninth node N9 to control the potential of the fourth node N4.

[0171] In the embodiments of the present disclosure, the first NOT gate INV1 performs NOT operation on the potential of the fourth node N4. When the fourth node N4 is at a high level, the first NOT gate INV1 controls the potential of the second node N2 to be at a low level. When the fourth node N4 is at a low level, the first NOT gate INV1 controls the potential of the second node N2 to be at a high level.

[0172] In the embodiments of the present disclosure, the second NOR gate NOR2 performs NOR operation on the potential of the second node N2 and the level of the second control signal CKo2. When at least one of the potential of the second node N2 and the level of the second control signal CKo2 is at a high level, the second NOR gate NOR2 controls the potential of the first node N1 to be at a low level. When the potential of the second node N2 and the level of the second control signal CKo2 are both at a low level, the second NOR gate NOR2 controls the potential of the first node N1 to be at a high level.

[0173] In the embodiments of the present disclosure, the second NOR gate NOR2 can also perform an NOR operation on the potential of the second node N2 and the level of the second clock signal CKn. When at least one of the potential of the second node N2 and the level of the second clock signal CKn is high, the second NOR gate NOR2 controls the potential of the first node N1 to be low. When both the potential of the second node N2 and the level of the second clock signal CKn are low, the second NOR gate NOR2 controls the potential of the first node N1 to be high.

[0174] In the embodiments of the present disclosure, the potential of the first node N1 is jointly controlled by the second control signal CKo2 or the second clock signal CKn and the second node N2, so that the output terminal OUT can output a multi-pulse output signal OUT when the first input signal INPUT1 is a multi-pulse signal, so as to drive the transistor in the pixel circuit by the multi-pulse signal. By multiplexing the second clock signal CKn, the number of signal lines in the circuit can be reduced, which is beneficial to narrow the frame of the display device and reduce the power consumption of the shift register.

[0175] FIG. 10A is a structural schematic diagram of a shift register according to another embodiment of the present disclosure. FIG. 10A is a circuit structural diagram of the shift register shown in FIG. 9.

[0176] As shown in FIG. 10A, the shift register 1000 includes an input shift circuit 1010, a first control circuit 1020, an output circuit 1030, and a second control circuit 1040.

[0177] In the embodiments of the present disclosure, the input shift circuit 810 includes the third transistor T3 to the twelfth transistor T12, the first control circuit 820 includes the thirteenth transistor T13 to the sixteenth transistor T16, the output circuit 830 includes the first transistor T1 and the second transistor T2, and the second control circuit 1040 includes the seventeenth transistor T17 to the twenty-second transistor T22.

[0178] The control electrode of the seventeenth transistor T17 is electrically connected to the second control terminal CKo2 or the second clock terminal CKn, the first electrode of the seventeenth transistor T17 is electrically connected to the power supply VGH2, and the second electrode of the seventeenth transistor T17 is electrically connected to the first electrode of the eighteenth transistor T18.

[0179] The control electrode of the eighteenth transistor T18 is electrically connected to the second node N2, and the second electrode of the eighteenth transistor T18 is electrically connected to the first node N1.

[0180] The control electrode of the nineteenth transistor T19 is electrically connected to the second node N2, the first electrode of the nineteenth transistor T19 is electrically connected to the first node N1, and the second electrode of the nineteenth transistor T19 is electrically connected to the power supply VGL2.

[0181] The control electrode of the twentieth transistor T20 is electrically connected to the second control end CKo2 or the second clock end CKn, the first electrode of the twentieth transistor T20 is electrically connected to the first node N1, and the second electrode of the twentieth transistor T20 is electrically connected to the power supply VGL2.

[0182] The control electrode of the twenty-first transistor T21 is electrically connected to the fourth node N4, the first electrode of the twenty-first transistor T21 is electrically connected to the power supply VGH2, and the second electrode of the twenty-first transistor T21 is electrically connected to the second node N2.

[0183] The control electrode of the twenty-second transistor T22 is electrically connected to the fourth node N4, the first electrode of the twenty-second transistor T22 is electrically connected to the second node N2, and the second electrode of the twenty-second transistor T22 is electrically connected to the power supply VGL2.

[0184] The second electrode of the sixth transistor, the first electrode of the seventh transistor T7, the first electrode of the eighth transistor T8, the control electrode of the eleventh transistor T11, and the control electrode of the twelfth transistor T12 are electrically connected to the fourth node N4, and the second electrode of the ninth transistor T9 and the second electrode of the tenth transistor T10 are electrically connected to the second electrode of the eleventh transistor T11.

[0185] The connection relationship of the remaining transistors in the shift register 1000 can refer to the connection relationship shown in FIG. 8A, and will not be described again for the sake of simplicity.

[0186] FIG. 10B is a signal timing diagram of a shift register according to an embodiment of the present disclosure.

[0187] The working process of the shift register 1000 provided in the embodiments of the present disclosure will be described below with reference to the structure of the shift register 1000 shown in FIG. 10A and the signal timing diagram shown in FIG. 10B. The working process of the shift register 1000 is divided into four periods. The first control signal CKo1 and the second control signal CKo2 are provided to the shift register 1000, and the signal CBo1 and the signal CBo2 are provided to the first control signal end and the second control signal end of the next stage shift register connected in cascade with the shift register 1000.

[0188] In the first period P1, the first clock signal CB is high, the second clock signal CKn is low, the third clock signal CK is low, and the fourth clock signal CBn is high. The reset signal Trst is low, the first control signal CKo1 is low, the first input signal INPUT1 is low, and the second control signal CKo2 is low.

[0189] The third transistor T3 and the fourth transistor T4 are turned off, the ninth transistor T9 and the tenth transistor T10 are turned on, and the potential of the ninth node N9 remains at the high level of the previous stage. The fifth transistor T5 and the seventh transistor T7 are turned on, the sixth transistor T6 and the eighth transistor T8 are turned off, and the power supply voltage VGL2 is written into the fourth node N4, and the potential of the fourth node N4 is at a low level.

[0190] The twenty-first transistor T21 is turned on, the twenty-second transistor T22 is turned off, the power supply voltage VGH2 is written into the second node N2, and the potential of the second node N2 is at a high level. The eleventh transistor T11 is turned on, the twelfth transistor T12 is turned off, and the power supply voltage VGH2 is written into the ninth node N9 through the eleventh transistor T11, the ninth transistor T9 and the tenth transistor T10, and the potential of the ninth node N9 is stably kept at a high level.

[0191] The seventeenth transistor T17 and the nineteenth transistor T19 are turned on, the eighteenth transistor T18 and the twentieth transistor T20 are turned off, the power supply voltage VGL2 is written into the first node N1, and the potential of the first node N1 is at a low level.

[0192] The thirteenth transistor T13 and the fifteenth transistor T15 are turned on, the fourteenth transistor T14 and the sixteenth transistor T16 are turned off, the power supply voltage VGL2 is written into the third node N3, and the potential of the third node N3 is at a low level.

[0193] The first transistor T1 is turned on, the second transistor T2 is turned off, the first power supply voltage VGH1 is provided to the output terminal OUT through the first transistor T1, and the output signal OUT output by the output terminal OUT is at a high level.

[0194] In the second period P2, the first clock signal CB is at a low level, the second clock signal CKn is at a high level, the third clock signal CK is at a high level, and the fourth clock signal CBn is at a low level. The reset signal Trst is at a low level, the first control signal CKo1 is at a high level, the first input signal INPUT1 is at a low level, and the second control signal CKo2 is at a high level.

[0195] The first input signal INOUT1 is written into the ninth node N9, and the potential of the ninth node N9 is at a low level. The power supply voltage VGH2 is written into the fourth node N4, and the potential of the fourth node N4 is at a high level.

[0196] The twenty-first transistor T21 is off, the twenty-second transistor T22 is on, the power supply voltage VGL2 is written into the second node N2, and the potential of the second node N2 is low. The eighteenth transistor T18 and the seventeenth transistor T17 are on, the nineteenth transistor T19 and the twentieth transistor T20 are off, the power supply voltage VGH2 is written into the first node N1, and the potential of the first node N1 is high.

[0197] The thirteenth transistor T13 and the fifteenth transistor T15 are off, the fourteenth transistor T14 and the sixteenth transistor T16 are on, the power supply voltage VGL2 is written into the third node N3, and the potential of the third node N3 is low.

[0198] The first transistor T1 is on, the second transistor T2 is off, the first power supply voltage VGH1 is provided to the output terminal OUT through the first transistor T1, and the output signal OUT output by the output terminal OUT is high.

[0199] In the third period P3, the first clock signal CB is high, the second clock signal CKn is low, the third clock signal CK is low, and the fourth clock signal CBn is high. The reset signal Trst is low, the first control signal CKo1 is low, the first input signal INPUT1 is low, and the second control signal CKo2 is low.

[0200] The third transistor T3 and the fourth transistor T4 are off, the ninth transistor T9 and the tenth transistor T10 are on, and the potential of the ninth node N9 remains low in the previous stage. The fifth transistor T5 and the sixth transistor T6 are on, the seventh transistor T7 and the eighth transistor T8 are off, the power supply voltage VGH2 is written into the fourth node N4, and the potential of the fourth node N4 is high.

[0201] The twenty-first transistor T21 is off, the twenty-second transistor T22 is on, the power supply voltage VGL2 is written into the second node N2, and the potential of the second node N2 is low. The eighteenth transistor T18 and the seventeenth transistor T17 are on, the nineteenth transistor T19 and the twentieth transistor T20 are off, the power supply voltage VGH2 is written into the first node N1, and the potential of the first node N1 is high.

[0202] The thirteenth transistor T13 and the fourteenth transistor T14 are on, the fifteenth transistor T15 and the sixteenth transistor T16 are off, the power supply voltage VGH2 is written into the third node N3, and the potential of the third node N3 is high.

[0203] The first transistor T1 is off, the second transistor T2 is on, the second power supply voltage VGH2 is provided to the output terminal OUT through the second transistor T2, and the output signal OUT output by the output terminal OUT is low.

[0204] In the fourth period P4, the potential change of each node and the output OUT output by the output terminal OUT can refer to the description of the fourth period P4 in FIG. 8B, which will not be repeated here for brevity.

[0205] In the embodiments of the present disclosure, if the control electrode of the seventeenth transistor T17 is electrically connected to the second control end CKo2. In the third period P3, since the potential of the second node N2 remains at the low level, when the second control signal CKo2 jumps from the high level to the low level, the potential of the first node N1 jumps from the low level to the high level synchronously.

[0206] In the embodiments of the present disclosure, if the control electrode of the seventeenth transistor T17 is electrically connected to the second clock end CKn. In the second period P2, since the potential of the second node N2 remains at the low level, when the second clock signal CKn jumps from the high level to the low level, the potential of the first node N1 jumps from the low level to the high level synchronously.

[0207] When the potential of the first node N1 jumps from the low level to the high level, the potential of the third node N3 remains at the low level. At this time, when the second transistor T2 remains in the off state, the first transistor T1 switches from the on state to the off state.

[0208] In the third period P3, since the potential of the second node N2 remains at the low level, when the first control signal CKo1 jumps from the high level to the low level, the potential of the third node N3 jumps to the high level synchronously, and at this time the second transistor T2 switches from the off state to the on state. When the first control signal CKo1 jumps from the low level to the high level, the potential of the third node N3 jumps to the low level synchronously, and at this time the second transistor T2 switches from the on state to the off state. Since the potential of the second node N2 remains at the low level, when the second control signal CKo2 jumps from the low level to the high level, the potential of the first node N1 jumps from the high level to the low level synchronously.

[0209] If the control electrode of the seventeenth transistor T17 is electrically connected to the second control terminal CKo2, in the third period P3, the first control signal CKo1 first jumps from high level to low level, and the second control signal CKo2 then jumps from high level to low level. Subsequently, the first control signal CKo1 first jumps from low level to high level, and the second control signal CKo2 then jumps from low level to high level. This makes the first transistor T1 first switch from the conducting state to the cut-off state based on the level jump time of the second control signal CKo2, and then the second transistor T2 switches from the cut-off state to the conducting state based on the level jump time of the first control signal CKo1 in the third period P3. Subsequently, the second transistor T2 switches from the conducting state to the cut-off state based on the level jump time of the first control signal CKo1, and then the first transistor T1 first switches from the cut-off state to the conducting state based on the level jump time of the second control signal CKo2.

[0210] If the control electrode of the seventeenth transistor T17 is electrically connected to the second clock terminal CKn, in the second period P2, the first transistor T1 first switches from the conducting state to the cut-off state based on the level jump time of the second clock signal CKn, and then the second transistor T2 switches from the cut-off state to the conducting state based on the level jump time of the first control signal CKo1 in the third period P3. And the second transistor T2 switches from the conducting state to the cut-off state based on the level jump time of the first control signal CKo1. Subsequently, in the fourth period P4, the first transistor T1 first switches from the cut-off state to the conducting state based on the level jump time of the second clock signal CKn.

[0211] Through the level jump time of the first control signal CKo1 and the second control signal CKo2, or through the level jump time of the first control signal CKo1 and the second clock signal CKn, when the second transistor T2 is in the cut-off state, the first transistor T1 is first controlled to be in the cut-off state, and then the second transistor T2 is controlled to switch to the conducting state. After the output terminal OUT outputs a low level signal, the second transistor T2 is first controlled to switch to the cut-off state based on the level jump time of the first control signal CKo1 and the second control signal CKo2, or based on the level jump time of the first control signal CKo1 and the second clock signal CKn, and then the first transistor T1 is controlled to switch to the conducting state. This makes the first transistor T1 and the second transistor T2 not in the conducting state at the same time, thereby avoiding the occurrence of instantaneous large current between the first power supply VGH1 and the second power supply VGL1, and avoiding the occurrence of leakage in the circuit.

[0212] In the embodiments of the present disclosure, when the first input signal INPUT1 is a multi-pulse signal, the second control signal CKo2 or the second clock signal CKn can control the output terminal OUT to output an output signal OUT with multiple pulses.

[0213] Fig. 11 is a structural schematic diagram of a shift register according to another embodiment of the present disclosure. Fig. 11 shows a logic circuit diagram of the shift register of Fig. 4.

[0214] As shown in Fig. 11, the shift register 1100 includes an input shift circuit 1110, a first control circuit 1120, an output circuit 1130, and a third control circuit 1150.

[0215] In the embodiment of the present disclosure, the input shift circuit 1110, the first control circuit 1120, and the output circuit 1130 are similar in structure to the input shift circuit 710, the first control circuit 720, and the output circuit 730 described above, and will not be described again for simplicity.

[0216] In the embodiment of the present disclosure, the third control circuit 1150 includes a first transmission gate Tg1. The first control end of the first transmission gate Tg1 is electrically connected to the first node N1, the second control end of the first transmission gate Tg1 is electrically connected to the second node N2, the input end of the first transmission gate Tg1 is electrically connected to the enable end GEN, and the output end of the first transmission gate Tg1 is electrically connected to the fifth node N5.

[0217] In the embodiment of the present disclosure, the potentials of the first node N1 and the second node N2 control the first transmission gate Tg1 to be in a conductive state or a non-conductive state. When the first transmission gate Tg1 is in the conductive state, the enable signal GEN is written to the fifth node N5. When the first transmission gate Tg1 is in the non-conductive state, the potential of the fifth node N5 remains the potential of the previous stage.

[0218] In the embodiment of the present disclosure, the first NOR gate NOR1 can be a two-input NOR gate or a three-input NOR gate.

[0219] For the two-input NOR gate, the first input end of the first NOR gate NOR1 is electrically connected to the second node N2, and the second input end of the first NOR gate NOR1 is electrically connected to the fifth node N5.

[0220] In the embodiment of the present disclosure, the first NOR gate NOR1 performs a NOR operation on the potential of the second node N2 and the potential of the fifth node N5. When at least one of the potential of the second node N2 and the potential of the fifth node N5 is high, the first NOR gate NOR1 controls the potential of the first node N1 to be low. When the potential of the second node N2 and the potential of the fifth node N5 are both low, the first NOR gate NOR1 controls the potential of the first node N1 to be high.

[0221] For the three-input NOR gate, the first input terminal of the first NOR gate NOR1 is electrically connected to the second node N2, the second input terminal of the first NOR gate NOR1 is electrically connected to the first control terminal CKo1, the third input terminal of the first NOR gate NOR1 is electrically connected to the fifth node N5, and the output terminal of the first NOR gate is electrically connected to the third node N3 (see the connection relationship shown in FIG. 4).

[0222] In the embodiment of the present disclosure, the first NOR gate NOR1 performs NOR operation on the potential of the second node N2, the potential of the fifth node N5, and the level of the first control signal CKo1. When at least one of the potential of the second node N2, the potential of the fifth node N5, and the level of the first control signal CKo1 is high, the first NOR gate NOR1 controls the potential of the first node N1 to be low. When the potential of the second node N2, the potential of the fifth node N5, and the level of the first control signal CKo1 are all low, the first NOR gate NOR1 controls the potential of the first node N1 to be high.

[0223] For example, the output signal OUT output by the output terminal OUT is used to drive the PMOS transistor in the pixel circuit. The potential of the fifth node N5 is controlled by the enable signal GEN, thereby controlling the potential of the third node N3. By controlling the potential of the third node N3, whether the output terminal OUT outputs a low-level signal can be controlled, thereby whether the PMOS transistor is turned on can be controlled, and whether the pixel circuit is refreshed can be controlled.

[0224] For example, when the enable signal GEN is low, the output signal OUT output by the output terminal OUT can refresh the corresponding pixel row in the display panel at a first frequency. When the enable signal is high, the output signal OUT output by the output terminal OUT can refresh the corresponding pixel row in the display panel at a second frequency. When the enable signal GEN switches between low and high, the output signal OUT output by the output terminal OUT can refresh the corresponding pixel row in the display panel at a third frequency. The first frequency is greater than the third frequency, and the third frequency is greater than the second frequency.

[0225] For example, the first frequency can be a high refresh frequency, and the third frequency can be a low refresh frequency.

[0226] For example, the first frequency can be 120 Hz, and the second frequency can be 0 Hz. When the enable signal GEN is always kept low, the display picture of the display panel can be refreshed 120 times in 1 second. When the enable signal GEN is always kept high, the display picture of the display panel is not refreshed, and a static picture is displayed.

[0227] For example, the enable signal GEN is switched between high and low levels, and the display panel can be refreshed at a low refresh frequency. For example, the enable signal GEN is kept at a low level in one refresh period, and kept at a high level in the subsequent refresh period. In this case, the display panel is refreshed once every two refresh periods, and the display panel can be refreshed 60 times in 1 second, and the third frequency is 60 Hz. For another example, the enable signal GEN is kept at a low level in one refresh period, and kept at a high level in the subsequent three refresh periods. In this case, the display panel is refreshed once every four refresh periods, and the display panel can be refreshed 30 times in 1 second, and the third frequency is 30 Hz.

[0228] FIG. 12A is a structural schematic diagram of a shift register according to another embodiment of the present disclosure. FIG. 12A is a circuit structure diagram of the shift register shown in FIG. 11.

[0229] As shown in FIG. 12A, the shift register 1200 includes an input shift circuit 1210, a first control circuit 1220, an output circuit 1230, and a third control circuit 1250.

[0230] In the embodiment of the present disclosure, the input shift circuit 1210 includes the third transistor T3 to the twelfth transistor T12, the first control circuit 1220 includes the thirteenth transistor T13 to the sixteenth transistor T16, the twenty-fifth transistor T25, the twenty-sixth transistor T26, and the capacitor C, the output circuit 1230 includes the first transistor T1 and the second transistor T2, and the third control circuit 1250 includes the twenty-third transistor T23 and the twenty-fourth transistor T24.

[0231] In the embodiment of the present disclosure, the first NOR gate NOR1 is a three-input NOR gate.

[0232] The control electrode of the twenty-third transistor T23 is electrically connected to the first node N1, the first electrode of the twenty-third transistor T23 is electrically connected to the enable end GEN, and the second electrode of the twenty-third transistor T23 is electrically connected to the fifth node N5.

[0233] The control electrode of the twenty-fourth transistor T24 is electrically connected to the second node N2, the first electrode of the twenty-fourth transistor T24 is electrically connected to the enable end GEN, and the second electrode of the twenty-fourth transistor T24 is electrically connected to the fifth node N5.

[0234] The control electrode of the twenty-fifth transistor T25 is electrically connected to the fifth node N5, the first electrode of the twenty-fourth transistor T24 is electrically connected to the second electrode of the thirteenth transistor T13, and the second electrode of the twenty-fourth transistor T24 is electrically connected to the first electrode of the fourteenth transistor T14.

[0235] The control electrode of the twenty-sixth transistor T26 is electrically connected to the fifth node N5, the first electrode of the twenty-sixth transistor T26 is electrically connected to the third node N3, and the second electrode of the twenty-sixth transistor T26 is electrically connected to the power supply VGL2.

[0236] The first end of the capacitor is electrically connected to the power supply VGL2, and the second end of the capacitor is electrically connected to the fifth node N5.

[0237] The connection relationship of the remaining transistors in the shift register 1200 can refer to the connection relationship shown in FIG. 8A, and will not be described again for the sake of simplicity.

[0238] In addition, those skilled in the art can understand that the capacitor can be realized as a single capacitor or a plurality of parallel or series capacitor units, as long as it can realize its corresponding function.

[0239] FIGS. 12B and 12C are signal timing diagrams of a shift register according to an embodiment of the present disclosure.

[0240] Next, the working process of the shift register 1200 provided by the present disclosure will be described with reference to the structure of the shift register 1200 shown in FIG. 12A and the signal timing diagrams shown in FIGS. 12B and 12C. The working process of the shift register 1200 is divided into four periods. The first control signal CKo1 is provided to the shift register 1200, and the signal CBo1 is provided to the first control signal end of the next stage shift register cascaded with the shift register 1200.

[0241] FIG. 12B shows that the output signal OUT output by the shift register 1200 can control the corresponding pixel row to be refreshed, and FIG. 12C shows that the output signal OUT output by the shift register 1200 can control the corresponding pixel row not to be refreshed.

[0242] As shown in FIG. 12B, the enable signal GEN remains at a low level.

[0243] In the first period P1, the first clock signal CB is at a high level, the second clock signal CKn is at a low level, the third clock signal CK is at a low level, and the fourth clock signal CBn is at a high level. The reset signal Trst is at a low level, the first control signal CKo1 is at a low level, and the first input signal INPUT1 is at a low level.

[0244] The potential of the first node N1 is at a low level, and the potential of the second node N2 is at a high level. The twenty-third transistor T23 and the twenty-fourth transistor T24 are cut off, the fifteenth transistor T15 is turned on, and the potential of the third node N3 is at a low level.

[0245] The first transistor T1 is turned on, the second transistor T2 is turned off, the first power voltage VGH1 is supplied to the output terminal OUT through the first transistor T1, and the output signal OUT output from the output terminal OUT is at a high level.

[0246] In the second period P2, the first clock signal CB is at a low level, the second clock signal CKn is at a high level, the third clock signal CK is at a high level, and the fourth clock signal CBn is at a low level. The reset signal Trst is at a low level, the first control signal CKo1 is at a high level, and the first input signal INPUT1 is at a low level.

[0247] The potential of the first node N1 is at a high level, and the potential of the second node N2 is at a low level. The twenty-third transistor T23 and the twenty-fourth transistor T24 are turned on, the enable signal GEN is written into the fifth node N5, the capacitor C is charged, and the fifth node N5 is kept at a low level.

[0248] The fourteenth transistor T14, the sixteenth transistor T16, and the twenty-fifth transistor T25 are turned on, and the fifteenth transistor T15, the thirteenth transistor T13, and the twenty-sixth transistor T26 are turned off. The power voltage VGL2 is written into the third node N3, and the potential of the third node N3 is at a low level.

[0249] The first transistor T1 and the second transistor T2 are turned off, and the output signal OUT output from the output terminal OUT is maintained at a high level.

[0250] In the third period P3, the first clock signal CB is at a high level, the second clock signal CKn is at a low level, the third clock signal CK is at a low level, and the fourth clock signal CBn is at a high level. The reset signal Trst is at a low level, the first control signal CKo1 is at a low level, and the first input signal INPUT1 is at a high level.

[0251] The potential of the first node N1 is at a high level, and the potential of the second node N2 is at a low level. The twenty-third transistor T23 and the twenty-fourth transistor T24 are turned on, and the fifth node N5 is kept at a low level.

[0252] The thirteenth transistor T13, the fourteenth transistor T14, and the twenty-fifth transistor T25 are turned on, and the fifteenth transistor T15, the sixteenth transistor T16, and the twenty-sixth transistor T26 are turned off. The power voltage VGH2 is written into the third node N3, and the potential of the third node N3 is at a high level.

[0253] The first transistor T1 is turned off, the second transistor T2 is turned on, the second power voltage VGL1 is supplied to the output terminal OUT through the second transistor T2, and the output signal OUT output from the output terminal OUT is at a low level.

[0254] In the fourth period P4, the first clock signal CB is at low level, the second clock signal CKn is at high level, the third clock signal CK is at high level, and the fourth clock signal CBn is at low level. The reset signal Trst is at low level, the first control signal CKo1 is at high level, and the first input signal INPUT1 is at high level.

[0255] The first transistor T1 is turned on, the second transistor T2 is turned off, the first power voltage VGH1 is provided to the output terminal OUT through the first transistor T1, and the output signal OUT output by the output terminal OUT is at high level.

[0256] In the embodiments of the present disclosure, the level jump of the first node N1 and the third node N3 can refer to the level jump of the first node N1 and the third node N3 described with reference to FIG. 8B, and will not be described again for simplicity.

[0257] As shown in FIG. 12C, the enable signal GEN remains at high level.

[0258] The potential changes of the nodes in the first period P1 and the change of the output signal OUT can refer to FIG. 12A.

[0259] In the second period P2, the enable signal GEN is written to the fifth node N5, and the capacitor C is charged, so that the fifth node N5 remains at high level. The fourteenth transistor T14, the sixteenth transistor T16 and the twenty-sixth transistor T26 are turned on, and the fifteenth transistor T15, the thirteenth transistor T13 and the twenty-fifth transistor T25 are turned off. The power voltage VGL2 is written to the third node N3, and the potential of the third node N3 is at low level.

[0260] The first transistor T1 and the second transistor T2 are turned off, and the output signal OUT output by the output terminal OUT remains at high level.

[0261] In the third period P3, the fifth node N5 remains at high level. The thirteenth transistor T13, the fourteenth transistor T14 and the twenty-sixth transistor T26 are turned on, and the fifteenth transistor T15, the sixteenth transistor T16 and the twenty-fifth transistor T25 are turned off. The power voltage VGL2 is written to the third node N3, and the potential of the third node N3 is at low level.

[0262] The first transistor T1 and the second transistor T2 are turned off, and the output signal OUT output by the output terminal OUT remains at high level.

[0263] The potential changes of the nodes in the fourth period P4 and the change of the output signal OUT can refer to FIG. 12A.

[0264] In the embodiment of the present disclosure, when the enable signal GEN keeps high level, the potential of the third node N3 always keeps low level, so that the second transistor T2 always keeps in the off state, and the output end OUT always keeps outputting the high level of the previous period, at this time, the pixel row electrically connected with the output end OUT is not refreshed.

[0265] FIG. 13 is a structural schematic diagram of a shift register according to another embodiment of the present disclosure. FIG. 13 shows a logic circuit diagram of the shift register of FIG. 5.

[0266] As shown in FIG. 13, the shift register 1300 includes an input shift circuit 1310, a first control circuit 1320, an output circuit 1330, and a fourth control circuit 1360.

[0267] In the embodiment of the present disclosure, the input shift circuit 1310, the first control circuit 1320, and the output circuit 1330 are similar in structure to the input shift circuit 710, the first control circuit 720, and the output circuit 730 described above, and will not be described again for simplicity.

[0268] In the embodiment of the present disclosure, the fourth control circuit 1360 includes a second transmission gate Tg2, a third NOR gate NOR3, and a fourth NOR gate NOR4.

[0269] The first control end of the second transmission gate Tg2 is electrically connected to the sixth node N6, the second control end of the second transmission gate Tg2 is electrically connected to the seventh node N7, the input end of the second transmission gate Tg2 is electrically connected to the enable end GEN, and the output end of the second transmission gate Tg2 is electrically connected to the fifth node N5.

[0270] The first input end of the third NOR gate NOR3 is electrically connected to the first node N1, the second input end of the third NOR gate NOR3 is electrically connected to the seventh node N7, and the output end of the third NOR gate NOR3 is electrically connected to the sixth node N6.

[0271] The first input end of the fourth NOR gate NOR4 is electrically connected to the sixth node N6, the second input end of the fourth NOR gate NOR4 is electrically connected to the reset end Trst, and the output end of the fourth NOR gate NOR4 is electrically connected to the seventh node N7.

[0272] In the embodiment of the present disclosure, the third NOR gate NOR3 performs NOR operation on the potential of the first node N1 and the potential of the seventh node N7. When at least one of the potential of the first node N1 and the potential of the seventh node N7 is high level, the third NOR gate NOR3 controls the potential of the sixth node N6 to be low level. When the potential of the first node N1 and the potential of the seventh node N7 are both low level, the third NOR gate NOR3 controls the potential of the sixth node N6 to be high level.

[0273] In the embodiment of the present disclosure, the fourth NOR gate NOR4 performs NOR operation on the level of the reset signal Trst and the potential of the sixth node N6. When at least one of the level of the reset signal Trst and the potential of the sixth node N6 is high, the fourth NOR gate NOR4 controls the potential of the seventh node N7 to be low. When both the level of the reset signal Trst and the potential of the sixth node N6 are low, the fourth NOR gate NOR4 controls the potential of the seventh node N7 to be high.

[0274] In the embodiment of the present disclosure, the potentials of the sixth node N6 and the seventh node N7 control the second transmission gate Tg2 to be in a conductive state or a non-conductive state. When the second transmission gate Tg2 is in the conductive state, the enable signal GEN is written into the fifth node N5. When the second transmission gate Tg2 is in the non-conductive state, the potential of the fifth node N5 remains the potential of the previous stage.

[0275] For example, the output signal OUT output by the output terminal OUT is used to drive a PMOS transistor in a pixel circuit. The potential of the fifth node N5 is controlled by the enable signal GEN, thereby controlling the potential of the third node N3. The potential of the third node N3 is controlled to control whether the output terminal OUT outputs a low-level signal, thereby controlling whether the PMOS transistor is turned on, thereby controlling whether the pixel circuit is refreshed.

[0276] In the embodiment of the present disclosure, in the case that the first input signal INPUT1 is a multi-pulse signal, the low level of the enable signal GEN can control the output terminal OUT to output an output signal OUT with multiple pulses, thereby realizing refreshing of the pixel circuit.

[0277] FIG. 14 is a structural schematic diagram of a shift register according to another embodiment of the present disclosure. FIG. 14 shows a logic circuit diagram of the shift register of FIG. 6.

[0278] As shown in FIG. 14, the shift register 1400 includes an input shift circuit 1410, a first control circuit 1420, an output circuit 1430, and a fifth control circuit 1470.

[0279] In the embodiment of the present disclosure, the input shift circuit 1410, the first control circuit 1420, and the output circuit 1430 are similar in structure to the input shift circuit 710, the first control circuit 720, and the output circuit 730 described above, and will not be described again for simplicity.

[0280] In the embodiment of the present disclosure, the fifth control circuit 1470 includes a third transmission gate Tg3 and a fourth transmission gate Tg4.

[0281] A first control terminal of the third transmission gate Tg3 is electrically connected to the first input terminal INPUT1, a second control terminal of the third transmission gate Tg3 is electrically connected to the second input terminal INPUT2, an input terminal of the third transmission gate Tg3 is electrically connected to the enable terminal GEN, and an output terminal of the third transmission gate Tg3 is electrically connected to the eighth node N8.

[0282] A first control terminal of the fourth transmission gate Tg4 is electrically connected to the first node N1, a second control terminal of the fourth transmission gate Tg4 is electrically connected to the second node N2, an input terminal of the fourth transmission gate Tg4 is electrically connected to the eighth node N8, and an output terminal of the fourth transmission gate Tg4 is electrically connected to the fifth node N5.

[0283] In the embodiment of the present disclosure, the levels of the first input signal INPUT1 and the second input signal INPUT2 control the third transmission gate Tg3 to be in a conductive state or a non-conductive state. When the third transmission gate Tg3 is in the conductive state, the enable signal GEN is written to the eighth node N8. When the third transmission gate Tg3 is in the non-conductive state, the potential of the eighth node N8 remains the potential of the previous stage.

[0284] In the embodiment of the present disclosure, the potentials of the first node N1 and the second node N2 control the fourth transmission gate Tg4 to be in a conductive state or a non-conductive state. When the fourth transmission gate Tg4 is in the conductive state, the eighth node N8 is written to the fifth node N5. When the fourth transmission gate Tg4 is in the non-conductive state, the potential of the fifth node N5 remains the potential of the previous stage.

[0285] For example, the output signal OUT output by the output terminal OUT is used to drive a PMOS transistor in a pixel circuit. The potential of the fifth node N5 is controlled by the enable signal GEN, thereby controlling the potential of the third node N3. By controlling the potential of the third node N3, whether the output terminal OUT outputs a low-level signal can be controlled, thereby controlling whether the PMOS transistor is turned on, and thereby controlling whether the pixel circuit is refreshed.

[0286] In the embodiment of the present disclosure, in the case where the first input signal INPUT1 is a multi-width single pulse signal, the low level of the enable signal GEN can control the output terminal OUT to output the output signal OUT of the multi-width single pulse signal, thereby achieving refresh of the pixel circuit.

[0287] FIG. 15 is a structural schematic diagram of a shift register according to another embodiment of the present disclosure.

[0288] As shown in FIG. 15, the shift register 1500 includes an input shift circuit 1510, a first control circuit 1520, and an output circuit 1530.

[0289] In the embodiment of the present disclosure, the output signal output by the shift register 1500 is used to drive an NMOS transistor in a pixel circuit.

[0290] The input shift circuit 1510 includes a fifth transmission gate Tg5, a sixth transmission gate Tg6, a second NOT gate INV2, and a NAND gate NAND.

[0291] The first control terminal of the fifth transmission gate Tg5 is electrically connected to the clock terminal CBp, the second control terminal of the fifth transmission gate Tg5 is electrically connected to the clock terminal CK, the input terminal of the fifth transmission gate Tg5 is electrically connected to the first input terminal INPUT1, and the output terminal of the fifth transmission gate Tg5 is electrically connected to the ninth node N9.

[0292] The first control terminal of the sixth transmission gate Tg6 is electrically connected to the clock terminal CKp, the second control terminal of the sixth transmission gate Tg6 is electrically connected to the clock terminal CB, the input terminal of the sixth transmission gate Tg6 is electrically connected to the ninth node N9, and the output terminal of the sixth transmission gate Tg6 is electrically connected to the second node N2.

[0293] The input terminal of the second NOT gate INV2 is electrically connected to the second node N2, and the output terminal of the second NOT gate INV2 is electrically connected to the third node N3.

[0294] The first input terminal of the NAND gate NAND is electrically connected to the reset terminal Trst, and the second input terminal of the NAND gate NAND is electrically connected to the ninth node N9.

[0295] In the embodiment of the present disclosure, the NAND gate NAND performs NAND operation on the level of the reset signal Trst and the potential of the ninth node N9. When at least one of the level of the reset signal Trst and the potential of the ninth node N9 is low, the NAND gate NAND controls the potential of the third node N3 to be high. When the level of the reset signal Trst and the potential of the ninth node N9 are both high, the NAND gate NAND controls the potential of the third node N3 to be low.

[0296] FIG. 16 is a signal timing diagram of a shift register according to another embodiment of the present disclosure.

[0297] FIG. 16 shows the timing changes of the signals and the potential changes of the nodes in FIG. 15. The working process of the shift register 1500 in each time period shown in FIG. 15 can refer to the working process of the shift register 800 in each time period shown in FIG. 8B, and will not be described again for simplicity.

[0298] FIGS. 17A and 17B are current diagrams of an example of a shift register. FIGS. 17A and 17B show the current values of the drain currents in PMOS transistors and NMOS transistors when an output terminal outputs a high-level signal.

[0299] FIG. 17A shows the currents in the PMOS transistors and the NMOS transistors when the output terminal outputs a high-level signal in the prior art.

[0300] As shown in FIG. 17A, the dashed line shows the current in the PMOS transistor when the output end outputs a high-level signal, and the solid line shows the current in the NMOS transistor when the output end outputs a high-level signal. Since the NMOS transistor is turned off when the output end outputs a high-level signal, the current in the NMOS transistor is a leakage current, and the current value of the leakage current is 78.87 μA.

[0301] FIG. 17B shows the current in the PMOS transistor and the NMOS transistor when the output end outputs a low-level signal in the prior art.

[0302] As shown in FIG. 17B, the dashed line shows the current in the PMOS transistor when the output end outputs a low-level signal, and the solid line shows the current in the NMOS transistor when the output end outputs a high-level signal. Since the PMOS transistor is turned off when the output end outputs a low high-level signal, the current in the PMOS transistor is a leakage current, and the current value of the leakage current is 34.67 μA.

[0303] FIGS. 18A and 18B are current diagrams of a shift register according to an embodiment of the present disclosure. FIGS. 18A and 18B show the current values of leakage currents in the PMOS transistor and the NMOS transistor in the shift register provided by the embodiment of the present disclosure when the output end outputs an output signal.

[0304] FIG. 18A shows the current in the PMOS transistor and the NMOS transistor when the output end outputs a high-level signal in the embodiment of the present disclosure.

[0305] As shown in FIG. 18A, the dashed line shows the current in the PMOS transistor when the output end outputs a high-level signal, and the solid line shows the current in the NMOS transistor when the output end outputs a high-level signal. Since the NMOS transistor is turned off when the output end outputs a high-level signal, the current in the NMOS transistor is a leakage current, and the current value of the leakage current is 9.555 nA.

[0306] FIG. 18B shows the current in the PMOS transistor and the NMOS transistor when the output end outputs a low-level signal in the embodiment of the present disclosure.

[0307] As shown in FIG. 18B, the dashed line shows the current in the PMOS transistor when the output end outputs a low-level signal, and the solid line shows the current in the NMOS transistor when the output end outputs a high-level signal. Since the PMOS transistor is turned off when the output end outputs a low high-level signal, the current in the PMOS transistor is a leakage current, and the current value of the leakage current is 2 μA.

[0308] With the shift register provided by the embodiment of the present disclosure, the current value of the leakage current in the circuit is reduced when the output end OUT outputs an output signal OUT, the power consumption of the circuit is reduced, and the driving capability of the circuit is enhanced.

[0309] FIG. 19 is a structural schematic diagram of a driving circuit according to an embodiment of the present disclosure.

[0310] FIG. 19 is a structural schematic diagram of a driving circuit according to an embodiment of the present disclosure.

[0311] As shown in FIG. 19, the driving circuit 1900 includes M cascaded shift registers, where M is a positive integer greater than 1. The M shift registers include a first-stage shift register ST1, an mth-stage shift register STm, and an Mth-stage shift register STM.

[0312] In an embodiment of the present disclosure, the shift register ST1 can be any one of the shift registers 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200, 1300, 1400, and 1500 described above.

[0313] For example, the M shift registers are all the shift register 300. For example, the M shift registers are all the shift register 700. Details are not described herein.

[0314] In an embodiment of the present disclosure, in the M cascaded shift registers, the input signal INPUT1 of the first input terminal INPUT1 of the first-stage shift register ST1 is a start signal STV. The first input terminal INPUT1 of the mth-stage shift register STm is electrically connected to the second node of the (m-1)th-stage shift register.

[0315] FIG. 20 is a structural schematic diagram of a driving circuit according to another embodiment of the present disclosure.

[0316] In an embodiment of the present disclosure, the driving circuit 2000 includes M cascaded shift registers.

[0317] In an embodiment of the present disclosure, the first input terminal INPUT1 of the mth-stage shift register STm is electrically connected to the second node N2 of the (m-1)th-stage shift register STm-1, and the second node N2 of the mth-stage shift register STm is electrically connected to the first input terminal INPUT1 of the (m+1)th-stage shift register STm+1, where 2

[0318] In an embodiment of the present disclosure, the driving circuit 2000 further includes a first clock signal line cb, a second clock signal line ckn, a third clock signal line ck, and a fourth clock signal line cbn.

[0319] In the embodiments of the present disclosure, the first clock terminal CB of the mth-stage shift register STm is electrically connected to the first clock signal line cb, the second clock terminal CKn of the mth-stage shift register STm is electrically connected to the second clock signal line ckn, the third clock terminal CK of the mth-stage shift register STm is electrically connected to the second clock signal line ckn, and the fourth clock terminal CBn of the mth-stage shift register STm is electrically connected to the first clock signal line cb.

[0320] The first clock terminal CB of the (m+1)th-stage shift register STm+1 is electrically connected to the second clock signal line ckn, the second clock terminal CKn of the (m+1)th-stage shift register STm+1 is electrically connected to the first clock signal line cb, the third clock terminal CK of the (m+1)th-stage shift register STm+1 is electrically connected to the first clock signal line cb, and the fourth clock terminal CBn of the (m+1)th-stage shift register STm+1 is electrically connected to the second clock signal line ckn.

[0321] In the embodiments of the present disclosure, the driving circuit 2000 can further include only the first clock signal line cb and the second clock signal line ckn.

[0322] In the embodiments of the present disclosure, the first clock terminal CB of the mth-stage shift register STm is electrically connected to the first clock signal line cb, the second clock terminal CKn of the mth-stage shift register STm is electrically connected to the second clock signal line ckn, the third clock terminal CK of the mth-stage shift register STm is electrically connected to the second clock signal line ckn, and the fourth clock terminal CBn of the mth-stage shift register STm is electrically connected to the first clock signal line cb.

[0323] The first clock terminal CB of the (m+1)th-stage shift register STm+1 is electrically connected to the second clock signal line ckn, the second clock terminal CKn of the (m+1)th-stage shift register STm+1 is electrically connected to the first clock signal line cb, the third clock terminal CK of the (m+1)th-stage shift register STm+1 is electrically connected to the first clock signal line cb, and the fourth clock terminal CBn of the (m+1)th-stage shift register STm+1 is electrically connected to the second clock signal line ckn.

[0324] FIG. 21 is a structural schematic diagram of a display device according to an embodiment of the present disclosure.

[0325] As shown in FIG. 21, the display device 2100 can include a driving circuit 2110.

[0326] In the embodiments of the present disclosure, the driving circuit 2110 can be at least one of the driving circuit 1900 and the driving circuit 2000 described above, and details are not repeated here.

[0327] FIG. 22 is a flowchart of a driving method according to an embodiment of the present disclosure.

[0328] As shown in FIG. 22, the driving method can include operation S2210 to operation S2240.

[0329] In operation S2210, in a first period, the first input signal is at a first level, the reset signal is at the first level, and the first control signal is at a first level.

[0330] In operation S2220, in a second period, the first input signal is at the first level, the reset signal is at the first level, and the first control signal is at a second level.

[0331] In operation S2230, in a third period, the first input signal is at a second level, the reset signal is at the first level, and the first control signal is at the first level.

[0332] In operation S2240, in a fourth period, the first input signal is at the second level, the reset signal is at the first level, and the first control signal is at the second level.

[0333] In the embodiments of the present disclosure, operation S2210 to operation S2240 are similar to the operations performed by the shift register 800 described above, and thus are not described again here.

[0334] In the embodiments of the present disclosure, the first level is a low level, and the second level is a high level. Alternatively, the first level can be a high level, and the second level can be a low level according to the types of the transistors in the shift register.

[0335] In the embodiments of the present disclosure, in the third period, the second clock signal is at the first level, the first control signal changes from the second level to the first level, and then changes from the first level to the second level.

[0336] In the embodiments of the present disclosure, the first period is similar to the operation of the first period P1 shown in FIG. 8B, the second period is similar to the operation of the second period P2 shown in FIG. 8B, the third period is similar to the operation of the third period P3 shown in FIG. 8B, and the fourth period is similar to the operation of the fourth period P4 shown in FIG. 8B. For the sake of simplicity, the same parts are not described again here.

[0337] In the embodiments of the present disclosure, in the case of refreshing the pixel circuit in the display panel at a first frequency, the enable signal is at the first level; in the case of refreshing the pixel circuit in the display panel at a second frequency, the enable signal is at the second level; and in the case of refreshing the pixel circuit in the display panel at a third frequency, the enable signal is switched between the first level and the second level; wherein the first frequency is greater than the third frequency, and the third frequency is greater than the second frequency.

[0338] The process of refreshing the pixel circuit in the display panel at the first frequency is similar to the operations of the first period P1 to the fourth period P4 shown in FIG. 12B, and the process of refreshing the pixel circuit in the display panel at the second frequency is similar to the operations of the first period P1 to the fourth period P4 shown in FIG. 12C. For the sake of brevity, the same parts of the present disclosure will not be repeated here.

[0339] The flow diagrams and the block diagrams in the drawings are illustrations of possible architectures, functions, and operations of systems, methods, and computer program products in accordance with various embodiments of the present disclosure. In this regard, each block in the flow diagrams or block diagrams can represent a module, a segment, or a portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions noted in the block can occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and / or flow diagrams, and combinations thereof, can be implemented by special purpose hardware-based systems that perform the specified functions or operations, or combinations of special purpose hardware and computer instructions.

[0340] Those skilled in the art will understand that features of the various embodiments and / or claims of the present disclosure can be combined and / or integrated with one another, even though such combinations or integrations are not expressly disclosed in the present disclosure. In particular, features of the various embodiments and / or claims of the present disclosure can be combined and / or integrated with one another without departing from the spirit and teachings of the present disclosure. All such combinations and / or integrations are within the scope of the present disclosure.

[0341] The above describes embodiments of the present disclosure. However, these embodiments are merely for illustrative purposes, and are not intended to limit the scope of the present disclosure. Although each embodiment is described above separately, this does not mean that the measures in each embodiment cannot be used advantageously in combination. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, and all such substitutions and modifications shall fall within the scope of the present disclosure.

Claims

1. A shift register comprising: an input shift circuit configured to control a potential of a first node with a first clock signal from a first clock terminal, a second clock signal from a second clock terminal, a first input signal from a first input terminal, and a reset signal from a reset terminal; and to control a potential of a second node with a third clock signal from a third clock terminal, a fourth clock signal from a fourth clock terminal, and the potential of the first node; a first control circuit configured to control a potential of a third node with the potential of the second node and a first control signal from a first control terminal; and an output circuit configured to control to provide a first power supply voltage of a first power supply or a second power supply voltage of a second power supply to an output terminal as an output signal with the potential of the first node and the potential of the third node. The first control circuit comprises: a first NOR gate, a first input terminal of the first NOR gate is electrically connected to the second node, a second input terminal of the first NOR gate is electrically connected to the first control terminal, and an output terminal of the first NOR gate is electrically connected to the third node.

2. The shift register of claim 1, wherein, The shift register further comprises: a second control circuit electrically connected to a fourth node, the first node, and a second control terminal or electrically connected to the fourth node, the first node, and the second clock terminal, the second control circuit configured to control the potential of the first node with a potential of the fourth node and a second control signal from the second control terminal or to control the potential of the first node with the second clock signal and the potential of the fourth node; 3. The shift register of claim 1, wherein, wherein the input shift circuit is electrically connected to the fourth node, and the input shift circuit is further configured to control the potential of the fourth node with the first clock signal, the second clock signal, the first input signal, and the reset signal. The second control circuit is further electrically connected to the second node, and the second control circuit is further configured to control the potential of the second node with the potential of the fourth node. The second control circuit comprises:

4. The shift register of claim 3, wherein, a first NAND gate, an input terminal of the first NAND gate is electrically connected to the fourth node, and an output terminal of the first NAND gate is electrically connected to the second node; and 5. The shift register of claim 3 or 4, wherein, a second NOR gate, a first input terminal of the second NOR gate is electrically connected to the second control terminal or the second clock terminal, a second input terminal of the second NOR gate is electrically connected to the second node, and an output terminal of the second NOR gate is electrically connected to the first node. The shift register further comprises: a third control circuit electrically connected to an enable terminal, the first node, and the second node, the third control circuit configured to control a potential of a fifth node with the potential of the first node, the potential of the second node, and an enable signal from the enable terminal; 6. The shift register of claim 1, wherein, wherein the first control circuit is electrically connected to the fifth node, and the first control circuit is configured to control the potential of the third node with the potential of the fifth node and the potential of the second node. The third control circuit comprises: ​ 7. The shift register of claim 6, wherein, ​ A first transmission gate, a first control terminal of the first transmission gate is electrically connected to the first node, a second control terminal of the first transmission gate is electrically connected to the second node, an input terminal of the first transmission gate is electrically connected to the enable terminal, and an output terminal of the first transmission gate is electrically connected to the fifth node.

8. The shift register of claim 7, wherein, The first control circuit includes a first NAND gate, a first input terminal of the first NAND gate is electrically connected to the second node, a second input terminal of the first NAND gate is electrically connected to the first control terminal, a third input terminal of the first NAND gate is electrically connected to the fifth node, and an output terminal of the first NAND gate is electrically connected to the third node.

9. The shift register of claim 1, wherein, The shift register further includes: A fourth control circuit electrically connected to the first node, the reset terminal, the enable terminal, and the fifth node, the fourth control circuit configured to control a potential of the fifth node using a potential of the first node, the reset signal, and an enable signal from the enable terminal.

10. The shift register of claim 9, wherein, The fourth control circuit includes: A second transmission gate, a first control terminal of the second transmission gate is electrically connected to a sixth node, a second control terminal of the second transmission gate is electrically connected to a seventh node, an input terminal of the second transmission gate is electrically connected to the enable terminal, and an output terminal of the second transmission gate is electrically connected to the fifth node; A third NAND gate, a first input terminal of the third NAND gate is electrically connected to the second node, a second input terminal of the third NAND gate is electrically connected to the seventh node, and an output terminal of the third NAND gate is electrically connected to the sixth node; and A fourth NAND gate, a first input terminal of the fourth NAND gate is electrically connected to the sixth node, a second input terminal of the fourth NAND gate is electrically connected to the reset terminal, and an output terminal of the fourth NAND gate is electrically connected to the seventh node.

11. The shift register of claim 1, wherein, The shift register further includes: A fifth control circuit electrically connected to the first node, the second node, the enable terminal, the fifth node, the first input terminal, and the second input terminal, the fifth control circuit configured to control a potential of the fifth node using a potential of the first node, a potential of the second node, the first input signal, a second input signal from the second input terminal, and an enable signal from the enable terminal.

12. The shift register of claim 11, wherein, The fifth control circuit includes: A third transmission gate, a first control terminal of the third transmission gate is electrically connected to the first input terminal, a second control terminal of the third transmission gate is electrically connected to the second input terminal, an input terminal of the third transmission gate is electrically connected to the enable terminal, and an output terminal of the third transmission gate is electrically connected to an eighth node; and A fourth transmission gate, a first control terminal of the fourth transmission gate is electrically connected to the first node, a second control terminal of the fourth transmission gate is electrically connected to the second node, an input terminal of the fourth transmission gate is electrically connected to the eighth node, and an output terminal of the fourth transmission gate is electrically connected to the fifth node.

13. The shift register of claim 1, wherein, The input shift circuit includes: a fifth transmission gate, a first control terminal of the fifth transmission gate is electrically connected to the first clock terminal, a second control terminal of the fifth transmission gate is electrically connected to the second clock terminal, an input terminal of the fifth transmission gate is electrically connected to the first input terminal, and an output terminal of the fifth transmission gate is electrically connected to a ninth node; a sixth transmission gate, a first control terminal of the sixth transmission gate is electrically connected to the third clock terminal, a second control terminal of the sixth transmission gate is electrically connected to the fourth clock terminal, an input terminal of the sixth transmission gate is electrically connected to the ninth node, and an output terminal of the sixth transmission gate is electrically connected to the second node; a fifth NOR gate, a first input terminal of the fifth NOR gate is electrically connected to the reset terminal, a second input terminal of the fifth NOR gate is electrically connected to the ninth node, and an output terminal of the fifth NOR gate is electrically connected to the first node; and a second NOT gate, an input terminal of the second NOT gate is electrically connected to the first node, and an output terminal of the second NOT gate is electrically connected to the second node.

14. A driving circuit comprising M shift registers as claimed in any one of claims 1-13 connected in cascade, wherein a first input terminal of an mth shift register is electrically connected to a second node of an (m-1)th shift register, 2 a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line; 15. The drive circuit of claim 14, further comprising: wherein a first clock terminal of the mth shift register is electrically connected to the first clock signal line, a second clock terminal of the mth shift register is electrically connected to the second clock signal line, a third clock terminal of the mth shift register is electrically connected to the third clock signal line, and a fourth clock terminal of the mth shift register is electrically connected to the fourth clock signal line; a first clock terminal of the (m+1)th shift register is electrically connected to the third clock signal line, a second clock terminal of the (m+1)th shift register is electrically connected to the fourth clock signal line, a third clock terminal of the (m+1)th shift register is electrically connected to the first clock signal line, and a fourth clock terminal of the (m+1)th shift register is electrically connected to the second clock signal line.

16. A display device comprising: the driving circuit as claimed in claim 14 or 15.

17. A driving method applied to the shift register as claimed in any one of claims 1-13, comprising: in a first time period, the first input signal is at a first level, the reset signal is at the first level, and the first control signal is at a first level; in a second time period, the first input signal is at the first level, the reset signal is at the first level, and the first control signal is at a second level; in a third time period, the first input signal is at a second level, the reset signal is at the first level, and the first control signal is at the first level; in a fourth time period, the first input signal is at the second level, the reset signal is at the first level, and the first control signal is at the second level.

18. The driving method as claimed in claim 17, wherein ​ In the third period, the second clock signal is the first level, the first control signal is changed from the second level to the first level, and then from the first level to the second level.

19. The driving method of claim 17, wherein, in a case where the pixel circuit in the display panel is refreshed at a first frequency, the enable signal is the first level; in a case where the pixel circuit in the display panel is refreshed at a second frequency, the enable signal is the second level; and in a case where the pixel circuit in the display panel is refreshed at a third frequency, the enable signal is switched between the first level and the second level; wherein the first frequency is greater than the third frequency, and the third frequency is greater than the second frequency.

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