Chip, preparation method, and electronic device

Abstract

The present application discloses a chip, a preparation method, and an electronic device. The chip comprises VFETs. Each VFET comprises a vertical channel, a stack structure, a groove structure, and a first electrode. The vertical channel extends in a direction perpendicular to a substrate. The stack structure comprises a gate structure and a first isolating dielectric layer, and the first isolating dielectric layer is provided on the side of the gate structure facing away from the substrate. The groove structure is provided on the side of the stack structure facing away from the substrate. The formed first electrode completely fills the bottom of the groove structure. A polycrystalline area is formed at the edges and corners on the side of the first electrode facing the substrate, so as to fill air gaps in the prior art with the part of the first electrode where the polycrystalline area is formed, thereby reducing the presence of air gaps; and the part of the first electrode where the polycrystalline area is formed is used as a support, thereby improving the stability and reliability of the structure of the corresponding VFET. In addition, the use of the first electrode having a regular shape as a mask is conducive to a subsequent process of using a self-alignment process to form a gate structure, thereby improving the accuracy of a subsequent self-alignment process.

Description

A chip, a fabrication method, and an electronic device

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411031192.2, filed on July 30, 2024, entitled "A Chip, Preparation Method and Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of semiconductor technology, and in particular to a chip, a fabrication method, and an electronic device. Background Technology

[0004] The continuous miniaturization of transistors and the increase in integration density to achieve better PPAC (power consumption, performance, area / cost) are the goals and driving forces behind the development of integrated circuit technology. As the basic unit in a chip, field-effect transistors (FETs) are currently predominantly horizontally configured, where charge carriers flow horizontally from the source to the drain, such as FinFETs. With the evolution of Moore's Law, further reductions in the critical dimension (CD) of horizontally configured FETs, such as gate length and contacted gate pitch (CGP), will lead to a significant increase in parasitic capacitance and consequently, chip power consumption. To address this, the industry has proposed vertical field-effect transistors (VFETs). Typically, a VFET has a vertical channel, a bottom source / drain, a top source / drain, and a gate. Based on this, in response to gate control, charge carriers can be transported along the vertical channel between the bottom and top source / drain electrodes, decoupling the CGP from the gate length and the source / drain-to-gate spacing. This significantly reduces the parasitic capacitance and chip power consumption of transistor devices while reducing reliance on advanced lithography technology.

[0005] During the fabrication of a VFET, if the top source and drain are formed in the groove at the top of the vertical channel using epitaxy (Epi), the limitations of this process mean that the top source and drain cannot completely fill the trench, resulting in an air gap at the corner of the groove bottom. The presence of this air gap introduces instability into the VFET structure, reducing its overall reliability, and also limits subsequent self-aligned processes that use the top source and drain as a mask. Summary of the Invention

[0006] This application provides a chip, a fabrication method, and an electronic device to reduce the presence of air gaps, improve the stability and reliability of the VFET structure, and facilitate subsequent self-aligned processes.

[0007] In a first aspect, embodiments of this application provide a chip, which may include a substrate and a plurality of VFETs disposed on the substrate. Each VFET may include: a vertical channel, a stacked structure, a protective dielectric layer, a trench structure, and a first electrode. The vertical channel extends in a direction perpendicular to the substrate, and the stacked structure is disposed at least on both sides of the vertical channel. The stacked structure may include a gate structure and a first isolation dielectric layer stacked in a direction perpendicular to the substrate, with the first isolation dielectric layer disposed on the side of the gate structure facing away from the substrate. Furthermore, by providing trench structures of approximately the same size, each trench structure is filled with heavily doped and crystalline semiconductor material to form a first electrode filling the trench structure, and the formed first electrode has both polycrystalline and single-crystal regions. This allows the formed first electrode to completely fill the bottom of the trench structure, and the corner of the first electrode facing the substrate forms a polycrystalline region. This allows the first electrode in the polycrystalline region to fill the air gaps in the prior art, reducing the presence of air gaps, and using the first electrode in the polycrystalline region as a support improves the stability and reliability of the VFET structure.

[0008] Furthermore, since the first electrode is formed in the groove structure, the size of the first electrode corresponding to different VFETs can be basically the same. Therefore, using the regularly shaped first electrode as a mask is beneficial to the subsequent process of forming the gate structure using a self-aligned process, thereby improving the accuracy of the subsequent self-aligned process.

[0009] Furthermore, in the embodiments of this application, the polycrystalline region is formed at the corner of the first electrode facing the substrate, while the current in the shortest path of the first electrode is all in the single-crystal region. Therefore, even if there is a polycrystalline region in the formed first electrode, its impact on the performance of the device is small and can be ignored.

[0010] Furthermore, if the shape of the first electrode is irregular, it can cause differences in parasitic resistance between different VFET devices. Therefore, in this embodiment, by forming first electrodes of substantially the same size, the size difference between the first electrodes of different VFETs can be reduced, the difference in parasitic resistance can be reduced, and thus the electrical differences between devices can be reduced.

[0011] In some embodiments, the semiconductor material of the first electrode has the same lattice constant as the semiconductor material of the vertical channel. For example, if the material of the vertical channel is silicon, the heavily doped amorphous semiconductor material layer can be heavily doped amorphous silicon (aSi) or heavily doped amorphous silicon germanium (aSiGe), etc. Furthermore, the doped impurities include, but are not limited to, boron, indium, or phosphorus, arsenic, or combinations thereof. The doping concentration of the impurities is greater than or equal to 1e⁻¹. 20 cm -3 .

[0012] Furthermore, since current typically flows along the shortest path, in some embodiments, the single-crystal region can be extended from the surface of the vertical channel facing away from the substrate to the surface of the first electrode facing away from the substrate, thereby making the current flow path as close to the single-crystal region as possible and improving the current flow.

[0013] Since polycrystalline regions are not conducive to current flow, in order to avoid the influence of polycrystalline regions on current flow, in some embodiments, the orthographic projection of the polycrystalline region on the substrate and the orthographic projection of the vertical channel on the substrate can be made not to overlap, so that there are no polycrystalline regions in the shortest current flow path.

[0014] In some embodiments, for the corner of the first electrode facing away from the substrate, crystal growth at this corner is relatively slow during the solid-state epitaxial process, resulting in incomplete growth. The subsequent high-temperature activation step with doped ions will form a polycrystalline structure, thus creating a polycrystalline region at this corner. Furthermore, in this embodiment, the polycrystalline region is formed at the corner of the first electrode facing away from the substrate, while the current in the shortest path of the first electrode is entirely within a single-crystal region. Therefore, even if a polycrystalline region exists in the formed first electrode, its impact on device performance is small and negligible.

[0015] In some embodiments, the interface between the polycrystalline region and the single-crystal region is a high-index crystal plane of the semiconductor material in the first electrode. For example, if the semiconductor material in the first electrode is silicon, then the interface between the polycrystalline region and the single-crystal region is a high-index crystal plane of silicon, such as the {111} crystal plane, the {311} crystal plane, etc.

[0016] In some embodiments, the groove structure may include a first region and a second region, the first region being located between the second region and the substrate, wherein the first electrode fills the first region. To prevent damage to the first electrode by subsequent processes (e.g., etching processes), the VFET may further include an etch barrier layer, which fills the second region and covers at least a portion of the surface of the first electrode facing away from the substrate, thereby protecting the subsequently formed first electrode from damage by subsequent etching processes.

[0017] In some embodiments, in order to protect the first electrode, a protective dielectric layer can be provided on the side of the stacked structure facing away from the substrate. The groove structure penetrates the protective dielectric layer, thereby surrounding the first electrode with the protective dielectric layer and preventing damage to the first electrode from other processes (such as etching processes).

[0018] In some embodiments, the groove structure is used to expose at least a portion of the surface of the vertical channel on the side opposite to the substrate, thereby enabling the first electrode to contact the vertical channel exposed by the groove structure and achieving an electrical connection between the first electrode and the vertical trench.

[0019] In some embodiments, the groove structure is used to expose the entire area of ​​the surface of the vertical trench facing away from the substrate, thereby increasing the contact area between the first electrode and the vertical trench and improving current flow.

[0020] In some embodiments, the orthogonal projection of the first electrode onto the substrate has a first orthogonal projection region, a second orthogonal projection region, and a third orthogonal projection region. The first orthogonal projection region coincides with the orthogonal projection of the vertical channel onto the substrate, and the second and third orthogonal projection regions are located on either side of the first orthogonal projection region and are symmetrical about the first orthogonal projection region. This arrangement allows the orthogonal projection of the first electrode onto the substrate to be symmetrical about the orthogonal projection of the vertical channel onto the substrate, thereby improving the reliability of the device.

[0021] In some embodiments, the first isolation dielectric layer covers the sidewall of the vertical channel through the gate oxide layer. The surface of the vertical channel facing away from the substrate is lower than the surface of the first isolation dielectric layer facing away from the substrate, and the surface of the vertical channel facing away from the substrate is higher than the surface of the gate structure facing away from the substrate, so that the gate oxide layer and the vertical channel enclose to form a recessed structure. The first electrode also fills the recessed structure, which can reduce the high-resistivity region, increase the on-state current, and improve the device performance.

[0022] In some embodiments, the gate structure and the first isolation dielectric layer are symmetrical about the vertical channel, thereby improving the reliability of the device.

[0023] In some embodiments, the stacked structure further includes a second electrode and a second isolation dielectric layer, the second electrode being disposed between the substrate and the second isolation dielectric layer, and the gate structure being disposed on the side of the second isolation dielectric layer facing away from the substrate. This configuration allows charge carriers to transport along a vertical channel between the first and second electrodes, and the second isolation dielectric layer insulates the gate structure from the second electrode, while the first isolation dielectric layer insulates the gate structure from the first electrode.

[0024] In some embodiments, the second electrode and the second isolation dielectric layer can be made symmetrical about the vertical channel, thereby making the formed VFET symmetrical about its central axis and improving the reliability of the device.

[0025] Secondly, embodiments of this application also provide a method for fabricating a chip, the method comprising: forming a vertical channel and a stacked structure disposed on at least two sides of the vertical channel on a substrate, the vertical channel extending in a direction perpendicular to the substrate, the stacked structure including a gate structure and a first isolation dielectric layer stacked in a direction perpendicular to the substrate, the first isolation dielectric layer being disposed on the side of the gate structure facing away from the substrate; and forming a groove structure on the side of the stacked structure facing away from the substrate, such that the dimensions of different groove structures are approximately or the same; and forming a first electrode in the groove structure using a solid-state epitaxy process, wherein the material of the first electrode is a heavily doped and crystalline semiconductor material, and the first electrode has a polycrystalline region and a single-crystal region, and a polycrystalline region is formed at the corner of the first electrode facing the substrate. Since the amorphous semiconductor material layer is crystallized using a solid-state epitaxy process, the amorphous semiconductor material layer can be converted into a crystalline semiconductor material layer, thereby forming a first electrode with a polycrystalline region and a single-crystal region in the groove structure. Furthermore, due to the solid-phase epitaxy process, there will be no special shape and size changes as in vapor phase epitaxy. This allows the formed first electrode to completely fill the bottom of the groove structure. As a result, the first electrode in the polycrystalline region can be used to fill the air gaps in the prior art, reducing the presence of air gaps. Using the first electrode in the polycrystalline region as a support improves the stability and reliability of the VFET structure.

[0026] Furthermore, since the first electrode is formed in the groove structure, the size of the first electrode corresponding to different VFETs can be basically the same. Therefore, using the regularly shaped first electrode as a mask is beneficial to the subsequent process of forming the gate structure using a self-aligned process, thereby improving the accuracy of the subsequent self-aligned process.

[0027] Furthermore, in the embodiments of this application, the polycrystalline region is formed at the corner of the first electrode facing the substrate, while the current in the shortest path of the first electrode is all in the single-crystal region. Therefore, even if there is a polycrystalline region in the formed first electrode, its impact on the performance of the device is small and can be ignored.

[0028] Furthermore, if the shape of the first electrode is irregular, it can cause differences in parasitic resistance between different VFET devices. Therefore, in this embodiment, by forming first electrodes of substantially the same size, the size difference between the first electrodes of different VFETs can be reduced, the difference in parasitic resistance can be reduced, and thus the electrical differences between devices can be reduced.

[0029] Furthermore, the temperature of vapor phase epitaxy (VPE) in existing mass production processes is higher than that of solid-state epitaxy (SPE), which can adversely affect other layers or structures in the VFET (e.g., the gate structure), impacting device reliability. In contrast, this embodiment employs a relatively lower-temperature SPE process and forms the first electrode before fabricating the gate structure, avoiding any impact on the gate structure and improving device reliability. Moreover, compared to VPE, SPE requires a lower thermal budget, which is beneficial for controlling impurity diffusion in the second electrode and other doped regions (e.g., Wells).

[0030] Furthermore, vapor phase epitaxy is a single-wafer operation, resulting in a long processing time for batch chip fabrication. In contrast, the solid phase epitaxy process in this embodiment allows for multi-wafer operations, such as processing 150 wafers at a time, increasing throughput and reducing costs. Additionally, the first electrode in this configuration facilitates the subsequent formation of the self-aligned gate conductive layer, simplifying process steps and improving manufacturability.

[0031] Furthermore, by first preparing a dummy gate for subsequent preparation of the first electrode, the process of preparing the first electrode can be performed first, and then the dummy gate can be removed to prepare the gate structure, thus avoiding the limitation of the gate structure on the preparation of the first electrode.

[0032] In some embodiments, forming a first electrode in a trench structure, wherein the first electrode is made of a heavily doped and crystalline semiconductor material, and the first electrode has polycrystalline and monocrystalline regions, may include the following process: using a deposition process to fill the trench structure with a heavily doped amorphous semiconductor material layer; and using a thermal annealing solid-state epitaxy process to crystallize the amorphous semiconductor material layer to form the first electrode having polycrystalline and monocrystalline regions.

[0033] To protect the first electrode, after filling the trench structure with a heavily doped amorphous semiconductor material layer, and before crystallizing the amorphous semiconductor material layer using a thermal annealing solid-state epitaxy process, the following steps are included: etching the amorphous semiconductor material layer so that the surface of the amorphous semiconductor material layer facing away from the substrate is lower than the surface of the sacrificial dielectric layer facing away from the substrate, and the surface of the amorphous semiconductor material layer facing away from the substrate is higher than the surface of the first isolation dielectric layer facing away from the substrate. Then, a dielectric material is filled into the trench structure facing away from the substrate of the amorphous semiconductor material layer to form an etch barrier layer.

[0034] In some embodiments, a hard mask layer is formed on the side of the vertical trench facing away from the substrate, and a groove structure is formed on the side of the stacked structure facing away from the substrate. This can include the following process: forming mask sidewalls and a sacrificial dielectric layer on both sides of the hard mask layer; and etching away at least a portion of the hard mask layer and mask sidewalls to form the groove structure in the sacrificial dielectric layer. Thus, groove structures of approximately or identical dimensions can be formed.

[0035] In some embodiments, after forming the first electrode, the process further includes etching away the sacrificial dielectric layer and forming a protective dielectric layer on both sides of the first electrode. Thus, the protective dielectric layer protects the first electrode from damage.

[0036] In some embodiments, forming a vertical channel on a substrate and a stacked structure at least on both sides of the vertical channel may include the following process: forming a plurality of vertical channels on the substrate, and sequentially stacking a second electrode, a second isolation dielectric layer, a dummy gate, and a first isolation dielectric layer on at least both sides of each vertical channel, wherein the vertical channel has a hard mask layer on the side facing away from the substrate. After forming the protective dielectric layer, the process further includes etching away the dummy gate to expose the area of ​​the vertical channel covered by the dummy gate. Subsequently, a gate structure is formed that at least covers the sidewalls on both sides of the channel region of the vertical channel, thereby realizing the replacement metal gate (RMG) process.

[0037] In some embodiments, the process of forming mask sidewalls and sacrificial dielectric layers on both sides of the hard mask layer may include, but is not limited to, the following processes:

[0038] A mask sidewall film is conformally grown on the surface of the substrate on the side with the hard mask layer;

[0039] Anisotropic etching is performed on the mask sidewall film layer, the mask sidewall film layers on both sides of the hard mask layer are retained, and the mask sidewall film layers on the surface of the hard mask layer facing away from the substrate and the surface of the first isolation dielectric layer between the hard masks facing away from the substrate are removed to form the mask sidewall.

[0040] A sacrificial dielectric layer is deposited on a substrate with mask sidewalls to cover the hard mask layer and the mask sidewalls.

[0041] The sacrificial medium layer is planarized to expose the hard mask layer and mask sidewalls;

[0042] The hard mask layer, mask sidewalls, and sacrificial dielectric layer are further planarized, and a portion of the hard mask layer, mask sidewalls, and sacrificial dielectric layer on the side facing away from the substrate is removed.

[0043] In some embodiments, the entire area of ​​the hard mask layer and mask sidewalls can be etched away to form a groove structure in the sacrificial dielectric layer, and the groove structure can expose the entire area of ​​the surface of the vertical channel facing away from the substrate so that the subsequently formed first electrode can contact the entire area of ​​the surface of the vertical channel facing away from the substrate.

[0044] In some embodiments, a gate oxide layer is further formed between the dummy gate and the sidewalls of the first isolation dielectric layer and the vertical channel. Furthermore, after forming the recess structure in the sacrificial dielectric layer and before filling the recess structure with a heavily doped amorphous semiconductor material layer, the method further includes: etching the vertical channel at a second predetermined distance in a direction from the first isolation dielectric layer to the second isolation dielectric layer, so that the gate oxide layer and the vertical channel enclose to form a recess structure. Moreover, the heavily doped amorphous semiconductor material layer fills the recess structure, thereby reducing high-resistivity regions, increasing on-state current, and improving device performance.

[0045] In some embodiments, the process of etching away the dummy gate to expose the area of ​​the vertical channel covered by the dummy gate may include, but is not limited to, the following process: using a protective dielectric layer and an etch barrier layer as an etch mask, etching away the first isolation dielectric layer exposed by the etch mask. Then, etching away the dummy gate exposed by the first isolation dielectric layer and the gate oxide layer between the dummy gate and the vertical channel, exposing the area of ​​the vertical channel covered by the dummy gate.

[0046] In some embodiments, after forming the gate structure that at least covers the sidewalls on both sides of the channel region of the vertical channel, the following process may also be included:

[0047] A protective dielectric layer and an etch barrier layer are used as etch masks to etch away the gate structure, the second isolation dielectric layer, and the second electrode in the area exposed by the etch mask;

[0048] In the direction from the first isolation dielectric layer to the second isolation dielectric layer, the substrate is etched at a third predetermined distance to form isolation trenches in the substrate, thereby forming a plurality of vertical field-effect transistors that are spaced apart from each other.

[0049] A dielectric material is deposited on a substrate to form an interlayer dielectric layer covering multiple vertical field-effect transistors, so that different vertical field-effect transistors are isolated by the interlayer dielectric layer.

[0050] Thirdly, embodiments of this application also provide an electronic device, which includes a circuit board and a chip, with the chip disposed on the circuit board. The chip is the chip described in the first aspect or in various embodiments of the first aspect. Furthermore, the electronic device includes, but is not limited to, terminal devices and communication devices. Terminal devices include, but are not limited to, mobile phones, computers, televisions, set-top boxes, watches, personal computers (PCs), wearable devices, workstations, etc. Communication devices include, but are not limited to, wireless network devices, fixed network devices, servers, smart broadband devices, etc.

[0051] In addition, the technical effects of the corresponding solutions in the third aspect can be referred to the technical effects that can be obtained by the corresponding solutions in the first and second aspects, and the repetitions will not be detailed. Attached Figure Description

[0052] Figure 1 is a schematic diagram of the structure of an electronic device according to an embodiment of this application;

[0053] Figure 2 is a schematic diagram of a chip structure in an embodiment of this application;

[0054] Figures 3A to 3W are cross-sectional views of the chip fabrication process in the embodiments of this application.

[0055] Reference numerals: 100-Housing; 200-Circuit board; 300-Chip; 310-Substrate; 400-VFET; 401-Vertical channel; 402-Stacked structure; 410-Gate structure; 420-First isolation dielectric layer; 430-Second electrode; 440-Second isolation dielectric layer; 450-First electrode; 460-Protective dielectric layer; 470-Etch barrier layer; 501-Interlayer dielectric layer; 502-First conductive contact; 510-Hard mask layer; 511-Pad oxide layer; 512-Mask dielectric layer ; 521 - Gate oxide layer; 522 - Virtual gate; 530 - Mask sidewall; 540 - Sacrificial dielectric layer; 550 - Amorphous semiconductor material layer; F0 - Vertical direction; AC - Groove structure; AX - Recessed structure; S0 / S1 / S2 / S3 / S4 - Surface; BQ1 - First region; BQ2 - Second region; h1 - First set distance; h2 - Second set distance; h3 - Third set distance; Db1 - First orthographic projection region; Db2 - Second orthographic projection region; Db3 - Third orthographic projection region. Detailed Implementation

[0056] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The specific operational methods in the method embodiments can also be applied to the device embodiments or system embodiments. It should be noted that in the description of this application, "multiple" can be understood as "at least two". Furthermore, it should be understood that in the description of this application, terms such as "first" and "second" are used only for distinguishing purposes and should not be construed as indicating or implying relative importance, nor as indicating or implying order.

[0057] It should be noted that the same reference numerals in the accompanying drawings of this application denote the same or similar structures, and therefore repeated descriptions of them will be omitted. Terms expressing position and direction described in this application are illustrative based on the accompanying drawings, but may be modified as needed, and all modifications are included within the scope of protection of this application. The accompanying drawings of this application are for illustrating relative positional relationships only and do not represent actual scale.

[0058] The chip, fabrication method, and electronic device provided in the embodiments of this application are described below with reference to the accompanying drawings.

[0059] Figure 1 is a schematic diagram of an electronic device according to an embodiment of this application. Referring to Figure 1, the electronic device includes: a housing 100, a circuit board 200 disposed within the housing 100, and a chip 300 fixed on the circuit board 200. The chip 300 and the circuit board 200 can be connected by bonding, splicing, or other methods to achieve an electrical connection between the chip 300 and the circuit board 200, thereby enabling signal transmission between them. Exemplarily, the circuit board 200 includes, but is not limited to, a printed circuit board (PCB). The electronic device includes, but is not limited to, terminal devices and communication devices. Terminal devices include, but are not limited to, mobile phones, computers, televisions, set-top boxes, watches, personal computers (PCs), wearable devices, workstations, etc. Communication devices include, but are not limited to, wireless network devices, fixed network devices, servers, smart broadband devices, etc. It is understood that the specific implementation of the electronic device can be determined according to the actual application scenario and is not limited here. Furthermore, the chip includes, but is not limited to, device modules, storage circuits, logic circuits, power devices, etc., which are not listed here.

[0060] Figure 2 is a schematic diagram of a chip structure in an embodiment of this application. Referring to Figure 2, the chip 300 in this embodiment may include a substrate 310. Exemplarily, the material of the substrate 310 includes, but is not limited to, silicon (Si), germanium (Ge), silicon-germanium (SiGe), silicon carbide (SiC), III-V compound semiconductors, or II-VI compound semiconductors.

[0061] Chips typically employ FETs to implement their functions. However, further reductions in the critical dimension (CD) of horizontally configured FETs, such as gate length and CGP, lead to a significant increase in parasitic capacitance and consequently, chip power consumption. Therefore, in the chip of this embodiment, multiple VFETs 400 can be disposed on the substrate 310 to implement their functions. Specifically, each VFET 400 may include a vertical channel 401, a stacked structure 402, and a first electrode 450. The vertical channel 401 extends along a vertical direction F0 (which is perpendicular to the substrate 310), forming a vertical channel 401 extending perpendicular to the substrate 310. Furthermore, each vertical channel 401 can be configured as a fin vertical channel, meaning each vertical channel 401 can extend along a first direction. Alternatively, the vertical channel 401 can also be configured as a cylindrical (e.g., cylindrical, elliptical cylindrical, etc.) vertical channel. Furthermore, each vertical channel 401 can also be arranged along a first direction and a second direction, wherein the first direction is parallel to the substrate and the first direction and the second direction are perpendicular to each other.

[0062] The stacked structure 402 can be disposed around the vertical channel 401 to form a gate-all-around (GAA) VFET. Exemplarily, the stacked structure 402 includes a second electrode 430, a second isolation dielectric layer 440, a gate structure 410, and a first isolation dielectric layer 420 stacked along the vertical direction F0, i.e., the second electrode 430, the second isolation dielectric layer 440, the gate structure 410, and the first isolation dielectric layer 420 are sequentially disposed along the vertical direction F0 and surround the vertical channel 401. Furthermore, the second electrode 430 is disposed between the second isolation dielectric layer 440 and the substrate 310, the gate structure 410 is disposed on the side of the second isolation dielectric layer 440 facing away from the substrate 310, and the first isolation dielectric layer 420 is disposed on the side of the gate structure 410 facing away from the substrate 310. Alternatively, in other embodiments of this application, the stacked structure 402 may be disposed on both sides of the vertical channel 401 (e.g., on opposite sides of the fin-type vertical channel in the second direction), in which case the second electrode 430, the second isolation dielectric layer 440, the gate structure 410 and the first isolation dielectric layer 420 are sequentially disposed along the vertical direction F0 and respectively disposed on both sides of the vertical channel 401.

[0063] The first electrode 450 is disposed on the side of the stacked structure 402 facing away from the substrate 310 and is electrically connected to the vertical channel 401. The second electrode 430 is also electrically connected to the vertical channel 401, so that charge carriers can be transported between the second electrode 430 and the first electrode 450 along the vertical channel 401. The second electrode 430 can be the bottom source / drain of the VFET 400, and the first electrode 450 can be the top source / drain of the VFET 400.

[0064] In the fabrication process of related technologies, the first electrode is typically formed using vapor phase epitaxy (Epi) after the gate structure is formed. However, due to limitations in the gate structure material and the trade-offs between factors such as the uniformity of the first electrode size, selective growth degree, and activation rate, the process temperature during vapor phase epitaxy cannot be too high. This results in irregular shapes of the formed first electrode, leading to differences in the size of the first electrode of different VFET devices, and consequently, differences in parasitic resistance between different VFET devices. To address this, in the chip provided in this application embodiment, referring to FIG2, before forming the first electrode 450 of each VFET, a groove structure AC of the same size corresponding to each VFET can be formed by etching. Then, a deposition process is used to fill each groove structure AC with a heavily doped amorphous semiconductor material layer, forming an amorphous semiconductor material layer related to the size of the groove structure AC. Subsequently, a solid-phase epitaxy (SPE) process is used to crystallize the amorphous semiconductor material layer, transforming it into a crystalline semiconductor material layer. This forms the first electrode 450, which fills the trench structure AC. The first electrode 450 is made of heavily doped and crystalline semiconductor material, completely filling the bottom of the trench structure AC. Furthermore, the SPE process involves epitaxial recrystallization of the amorphous layer on a semiconductor single crystal at a temperature below the melting point or eutectic point of the material. During the crystallization of the amorphous semiconductor material layer using the SPE process, the channel sidewall material and the bottom material result in the first electrode 450 not being a perfect single-crystal structure, but rather having both polycrystalline and single-crystal regions. Since the corner of the first electrode 450 facing the substrate 310 forms a polycrystalline region, the first electrode 450 in the polycrystalline region can be used to fill the air gaps in the prior art, reducing the presence of air gaps. Using the first electrode 450 in the polycrystalline region as a support improves the stability and reliability of the VFET structure.

[0065] Furthermore, since the first electrode 450 is formed in the recessed structure AC, the size of the first electrode 450 corresponding to different VFETs can be basically the same. Therefore, using the regularly shaped first electrode 450 as a mask is beneficial to the subsequent process of forming the gate structure 410 by self-alignment, thereby improving the accuracy of the subsequent self-alignment process.

[0066] Furthermore, in the embodiments of this application, the polycrystalline region is formed at the corner of the first electrode facing the substrate, while the current in the shortest path of the first electrode 450 is all in the single-crystal region. Therefore, even if there is a polycrystalline region in the first electrode 450, its impact on the performance of the device is small and can be ignored.

[0067] Furthermore, if the shape of the first electrode 450 is irregular, it can cause differences in the parasitic resistance of different VFET devices. Therefore, in this embodiment, by forming first electrodes of essentially the same size, and compared to first electrodes formed by vapor phase epitaxy, by setting a groove structure AC of the same size, the dimensions of the first electrodes corresponding to different VFETs can be made the same, thereby reducing the size difference between the first electrodes of different VFETs, reducing the difference in parasitic resistance, and further reducing the electrical differences between devices.

[0068] In order to protect the first electrode 450, a protective dielectric layer 460 can be provided on the side of the stacked structure 402 facing away from the substrate 310. The aforementioned groove structure AC penetrates the protective dielectric layer 460, thereby surrounding the first electrode 450 with the protective dielectric layer 460 and preventing other processes (such as etching processes) from damaging the first electrode 450.

[0069] It is worth mentioning that, due to limitations in process conditions or other factors, there may be some deviations or errors in the actual process, which may cause the "sameness" described above to be not entirely accurate. For example, the "sameness" described above may refer to the sameness that is allowed within the allowable range of error. Of course, "sameness" can also be understood as "substantially the same" or "completely the same". Therefore, as long as the "sameness" relationship described above roughly meets the above conditions, it falls within the protection scope of this application.

[0070] In some embodiments, the first electrode can be the drain and the second electrode can be the source, or the second electrode can be the drain and the first electrode can be the source, without limitation.

[0071] The following describes the fabrication process of a VFET with a stacked structure surrounding a vertical channel as an example, with reference to the accompanying drawings. For VFETs with a stacked structure on both sides of the vertical channel, the fabrication process can be referred to the following procedure; repeated details will not be discussed.

[0072] Figures 3A to 3W are cross-sectional views of the chip fabrication process in the embodiments of this application.

[0073] Referring to FIG3A, a substrate 310 is provided, which may be a Si substrate (e.g., a wafer). A hard mask layer 510 is formed by sequentially depositing a pad oxide layer 511 and a mask dielectric layer 512 on the substrate 310 using at least one deposition process, such as Chemical Vapor Deposition (CVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), and Plasma Enhanced Atomic Layer Deposition (PEALD), using a dielectric material. Exemplarily, the material of the pad oxide layer 511 includes, but is not limited to, a dielectric material such as silicon dioxide (SiO2), and the material of the mask dielectric layer includes, but is not limited to, a dielectric material such as silicon nitride (SiN). Furthermore, by providing the pad oxide layer 511, the stress between the subsequently grown silicon nitride and the substrate 310 can be relieved, reducing the risk of substrate 310 cracking.

[0074] Referring to FIG3B, the hard mask layer 510 is patterned so that the area of ​​the substrate 310 corresponding to the formation of the vertical channel 401 is covered by the hard mask layer 510, while exposing other areas of the substrate 310. Then, multiple vertical channels 401 are formed on the substrate 310 by wet etching or dry etching.

[0075] Referring to FIG3C, a semiconductor material layer is epitaxially grown (e.g., vapor phase epitaxy) on a substrate 310, and impurities are doped into the semiconductor material layer to form a second electrode 430. Exemplarily, the second electrode 430 may surround the bottom source / drain regions of each vertical channel 401. Furthermore, the material forming the second electrode 430 may be heavily doped silicon or heavily doped silicon-germanium, etc. And the doped impurities may include, but are not limited to, boron, or may be phosphorus, arsenic, indium, or combinations thereof.

[0076] Referring to Figure 3D, a dielectric material is filled using at least one deposition process such as CVD, PECVD, PVD, ALD, and PEALD. Planarization can then be performed using a process such as Chemical-Mechanical Planarization (CMP). A second isolation dielectric layer 440 is then formed by etching back, depositing the second isolation dielectric layer 440 on the surface of the second electrode 430 between each vertical channel 401 on the side facing away from the substrate 310. This allows the second electrode 430 to be insulated from adjacent elements (such as a gate structure formed later) by the second isolation dielectric layer 440. The second isolation dielectric layer 440 may surround a second spacer region of each vertical channel 401. Exemplarily, the material of the second isolation dielectric layer 440 may include a low-k (dielectric constant) dielectric material, including, but not limited to, silicon dioxide (SiO2), silicon oxycarbide (SiCO), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon carbonitride (SiOCN), or combinations thereof.

[0077] Referring to FIG3E, a gate oxide layer 521 is formed on the sidewall of each vertical channel 401 on the side of the second isolation dielectric layer 440 facing away from the substrate 310. Exemplarily, the gate oxide layer 521 can be made of SiO2, its thickness can be 2nm to 3nm, and it can be grown using a thermal oxidation process.

[0078] Referring to Figure 3F, at least one of the deposition processes such as CVD, PECVD, PVD, ALD, and PEALD is used to fill amorphous silicon material. Then, the filled amorphous silicon material film is planarized using a process such as CMP. Afterward, a dummy gate 522 is formed on the amorphous silicon material film by etching back. The dummy gate 522 is deposited on the surface of the second isolation dielectric layer 440 between each vertical channel 401 on the side facing away from the substrate 310. The dummy gate 522 surrounds the channel region of the vertical channel 401 through the gate oxide layer 521, thereby completing the fabrication process of the dummy gate of the VFET. Then, the subsequent fabrication process of the first electrode 450 can be performed based on the dummy gate. Thus, the fabrication process of the first electrode 450 can be performed first, and then the fabrication process of the gate structure can be performed, avoiding the limitation of the fabrication process of the first electrode 450 by the gate structure.

[0079] Referring to Figure 3G, a dielectric material is filled using at least one deposition process, such as CVD, PECVD, PVD, ALD, or PEALD. The filled dielectric material film can then be planarized using a process such as CMP. Afterward, the dielectric material film is etched back to form a first isolation dielectric layer 420. This first isolation dielectric layer 420 is deposited on the surface of the virtual gate 522 between each vertical channel 401, facing away from the substrate 310. Thus, the first isolation dielectric layer 420 can insulate adjacent elements (such as the gate structure 410 and the first electrode 450, which are formed later) from each other. The first isolation dielectric layer 420 also surrounds a first spacing region of the vertical channel 401 via a gate oxide layer 521. Exemplarily, the material of the first isolation dielectric layer 420 can include low-k dielectric materials, such as, but not limited to, silicon dioxide (SiO2), silicon oxycarbide (SiCO), silicon nitride (Si3N4), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon carbonitride (SiOCN), or combinations thereof.

[0080] Referring to FIG3H, a dielectric material is grown along the morphology of the surface of the substrate 310 having a hard mask layer using at least one deposition process such as CVD, PECVD, PVD, ALD, and PEALD. This results in the conformal growth of mask sidewall layers on the sidewalls of each hard mask layer 510, the surface of each hard mask layer 510 facing away from the substrate 310, and the surface of the first isolation dielectric layer 420 between each hard mask layer 510 facing away from the substrate 310. Subsequently, anisotropic etching is performed on the mask sidewall layers, retaining the mask sidewall layers on both sides of the hard mask layer 510, and removing the mask sidewall layers on the surface of each hard mask layer 510 facing away from the substrate 310 and the surface of the first isolation dielectric layer 420 between each hard mask layer 510 facing away from the substrate 310. This forms mask sidewalls 530 on the sidewalls of the hard mask layer 510, enabling a self-aligned formation of the mask sidewalls 530. For example, the material of the mask sidewalls includes, but is not limited to, dielectric materials such as silicon nitride (SiN). Furthermore, the materials of the hard mask and the mask sidewalls may be the same or different.

[0081] Referring to FIG3I, a filling dielectric material is deposited on a substrate 310 having mask sidewalls 530 using at least one deposition process, such as CVD, PECVD, PVD, ALD, or PEALD, to form a sacrificial dielectric layer 540, and the sacrificial dielectric layer 540 covers the hard mask and the mask sidewalls. Exemplarily, the material of the sacrificial dielectric layer may include, but is not limited to, silicon dioxide (SiO2), silicon oxycarbide (SiCO), silicon nitride (Si3N4), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon carbonitride (SiOCN), or combinations thereof. It is worth noting that, to achieve etching selectivity, the sacrificial dielectric layer, the hard mask, and the mask sidewalls are set to different materials, with the material having higher etching selectivity.

[0082] Referring to Figure 3J, the sacrificial dielectric layer 540 is planarized using CMP or similar processes, exposing the hard mask layer 510 and the mask sidewall 530. Furthermore, due to process factors, the edges of the formed mask sidewall 530 may have chamfered structures (e.g., rounded edges). Therefore, during the planarization of the sacrificial dielectric layer 540, the hard mask layer 510, mask sidewall 530, and sacrificial dielectric layer 540 can be further planarized, removing a portion of the hard mask layer 510, mask sidewall 530, and sacrificial dielectric layer 540 on the side facing away from the substrate 310. This allows for more polishing to remove the chamfered structure of the mask sidewall 530, resulting in smoother edges (e.g., approximately right angles). Of course, if the edges and corners of the formed mask sidewall 530 are relatively flat, the planarization process can be stopped when the hard mask layer 510 and the mask sidewall 530 are exposed.

[0083] Referring to Figure 3K, wet or dry etching is used to remove the entire area of ​​the hard mask layer 510 and the mask sidewalls 530, forming a regularly shaped groove structure AC in the sacrificial dielectric layer 540. This exposes the entire area of ​​the surface of the vertical channel 401 facing away from the substrate 310, allowing the subsequently formed first electrode to contact the entire area of ​​the surface of the vertical channel 401 facing away from the substrate 310. Alternatively, a portion of the hard mask layer 510 and the mask sidewalls 530 can be removed to form the groove structure AC, exposing a portion of the surface of the vertical channel 401 facing away from the substrate 310. This also allows the subsequently formed first electrode to contact a portion of the surface of the vertical channel 401 facing away from the substrate 310.

[0084] Referring to Figure 3L, in the direction from the first isolation dielectric layer 420 to the second isolation dielectric layer 440, a second predetermined distance h2 is etched into the vertical channel 401, such that the surface S0 of the vertical channel 401 facing away from the substrate 310 is lower than the surface S1 of the first isolation dielectric layer 420 facing away from the substrate 310, and the surface S0 of the vertical channel 401 facing away from the substrate 310 is higher than the surface S2 of the virtual gate 522 facing away from the substrate 310, so that the gate oxide layer 521 and the vertical channel 401 enclose and form a recessed structure AX. Based on this, the subsequently formed first electrode can also fill the recessed structure AX, thereby reducing the high-resistivity region, increasing the on-state current, and improving device performance. The specific value of the second predetermined distance h2 can be determined according to the needs of the actual application scenario and is not limited here. It is understood that in some other embodiments, the steps shown in Figure 3L can be omitted, and the steps shown in Figure 3M can be performed directly, in which case the surfaces S0 and S1 can be approximately flush.

[0085] Referring to Figure 3M, at least one deposition process, such as CVD, PECVD, PVD, ALD, and PEALD, is used to fill the recessed structure AC and the recessed structure AX with a heavily doped amorphous semiconductor material layer 550. The semiconductor material of the amorphous semiconductor material layer 550 can have the same or approximately the same lattice constant as the semiconductor material of the vertical channel 401. For example, if the material of the vertical channel 401 is silicon, then the heavily doped amorphous semiconductor material layer 550 can be heavily doped amorphous silicon (aSi) or heavily doped amorphous silicon germanium (aSiGe). Furthermore, the doped impurities include, but are not limited to, boron, indium, or phosphorus, arsenic, or combinations thereof. The doping concentration of the impurities is greater than or equal to 1e 20 cm -3 The amorphous semiconductor material layer 550 can then be planarized using CMP to expose the sacrificial dielectric layer 540.

[0086] Referring to Figure 3N, dry etching is used to etch the amorphous semiconductor material layer 550 at a first predetermined distance h1 in the direction from the first isolation dielectric layer 420 to the second isolation dielectric layer 440. This results in the surface S3 of the amorphous semiconductor material layer 550 facing away from the substrate 310 being lower than the surface S4 of the sacrificial dielectric layer 540 facing away from the substrate 310, and the surface S3 of the amorphous semiconductor material layer 550 facing away from the substrate 310 being higher than the surface S1 of the first isolation dielectric layer 420 facing away from the substrate 310. This embeds the amorphous semiconductor material layer 550 into the groove structure AC to a certain depth. Based on this, the formed groove structure AC can include a first region BQ1 and a second region BQ2, with the first region BQ1 located between the second region BQ2 and the substrate 310, and the amorphous semiconductor material layer 550 filling the first region BQ1. Based on this, the subsequently formed first electrode can fill the first region BQ1. Furthermore, the specific value of the first predetermined distance h1 can be determined according to the needs of the actual application scenario and is not limited here.

[0087] Referring to Figure 3O, at least one of the deposition processes, such as CVD, PECVD, PVD, ALD, and PEALD, is used to fill a dielectric material layer in the groove structure AC on the side of the amorphous semiconductor material layer 550 facing away from the substrate 310. Then, a process such as CMP is used to planarize the dielectric material layer, exposing the sacrificial dielectric layer 540. This forms an etch stop layer 470 in the second region BQ2 of the groove structure AC, covering the entire surface of the first electrode 450 on the side facing away from the substrate 310. This configuration protects the subsequently formed first electrode 450 from damage caused by subsequent etching processes. Exemplarily, the material of the etch stop layer 470 includes, but is not limited to, dielectric materials such as silicon nitride (SiN).

[0088] Subsequently, the filled amorphous semiconductor material layer 550 undergoes solid-state epitaxy through low-temperature annealing (e.g., 500–650°C) in a furnace tube. The dopant ions in the amorphous semiconductor material layer 550 are then activated using processes such as spike annealing or laser spike annealing (LSA), thereby crystallizing the amorphous semiconductor material layer 550 to form a first electrode 450 with heavily doped and crystalline semiconductor material. The first electrode 450 directly contacts the vertical channel 401 exposed by the recessed structure AC, achieving electrical connection between them. Furthermore, since heavily doped amorphous semiconductor material layers are filled in both the recessed structure AC and the recessed structure AX, the formed first electrode 450 fills not only the first region BQ1 of the recessed structure AC but also the recessed structure AX, thereby reducing high-resistivity regions, increasing on-state current, and improving device performance. Of course, if the recessed structure AX is not formed, the first electrode 450 can fill the first region BQ1 and also make contact with the vertical channel 401 to achieve electrical connection between them.

[0089] Based on this, in this embodiment, a deposition process is first used to fill the groove structure with material for forming the first electrode. This process has strong filling capability and a regular shape, avoiding the special shape and size variations seen in vapor phase epitaxy. This results in a regular shape and consistent size for the first source / drain formed in this embodiment, which helps reduce the size differences between the first electrodes of different VFETs, lowers parasitic resistance differences, and consequently reduces electrical differences between devices. Furthermore, the temperature of vapor phase epitaxy in existing mass production processes is higher than that of solid phase epitaxy, which can have adverse effects on other layers or structures in the VFET (e.g., the gate structure), affecting device reliability. In contrast, this embodiment uses a relatively lower-temperature solid phase epitaxy process and forms the first electrode before fabricating the gate structure, avoiding any impact on the gate structure and improving device reliability. Moreover, compared to vapor phase epitaxy, solid phase epitaxy requires a lower thermal budget, which is beneficial for controlling impurity diffusion in the second electrode and other doped regions (e.g., Wells).

[0090] Furthermore, vapor phase epitaxy is a single-wafer process, resulting in a long processing time for batch chip fabrication. In contrast, the solid phase epitaxy process used in this application allows for multi-wafer processing, for example, processing 150 wafers at a time, which increases production capacity and helps reduce costs.

[0091] Furthermore, the first electrode and etch barrier layer of this rule can help form the subsequent self-aligned gate conductive layer, simplifying the process steps and improving manufacturability.

[0092] Since the lattice constants of the middle and bottom of the amorphous semiconductor material layer 550 are the same as those of the vertical channel 401, they are epitaxial, resulting in faster crystal growth. However, crystal growth is slow at certain locations in the amorphous semiconductor material layer 550, and may not be complete. The subsequent high-temperature activation step involving doped ions can lead to the formation of a polycrystalline structure, resulting in the first electrode 450 not being a perfect single-crystal structure, but rather a structure with both polycrystalline and single-crystal regions. For example, the interface between the polycrystalline and single-crystal regions is a high-index crystal plane of the semiconductor material in the first electrode 450. For instance, if the semiconductor material in the first electrode 450 is silicon, the interface between the polycrystalline and single-crystal regions is a high-index crystal plane of silicon, such as the {111} plane or the {311} plane.

[0093] Since current typically flows along the shortest path, the single-crystal region can be extended from the surface S0 of the vertical channel 401 on the side opposite to the substrate 310 to the surface S3 of the first electrode 450 on the side opposite to the substrate 310. This allows the current flow path to be as close to the single-crystal region as possible, thereby improving the current flow.

[0094] Since polycrystalline regions are not conducive to current flow, in order to avoid the influence of polycrystalline regions on current flow, the orthographic projection of the polycrystalline region on the substrate 310 and the orthographic projection of the vertical channel 401 on the substrate 310 can be made to not overlap, so that there are no polycrystalline regions in the shortest current flow path.

[0095] Furthermore, for the corner BJ1 of the first electrode 450 facing away from the substrate 310, since the corner BJ1 is in contact with the sacrificial dielectric layer 540 and the etch barrier layer 470, the crystal growth of the amorphous semiconductor material layer 550 at the corner BJ1 is relatively slow, resulting in incomplete growth. The high temperature of the subsequent activation step of doped ions will form a polycrystalline structure, thereby forming a polycrystalline region at the corner BJ1.

[0096] For the corner BJ2 of the first electrode 450 facing the substrate 310, since the corner BJ2 is in contact with the sacrificial dielectric layer 540 and the first isolation dielectric layer 420, the crystal growth of the amorphous semiconductor material layer 550 at the corner BJ2 is relatively slow, resulting in incomplete growth. The high temperature of the subsequent activation step of doped ions will form a polycrystalline structure, thereby forming a polycrystalline region at the corner BJ2.

[0097] It is worth mentioning that in the embodiments of this application, the polycrystalline regions are formed at the corners BJ1 to BJ2 of the first electrode 450, while the current in the shortest path of the first electrode 450 is all in the single-crystalline region. Therefore, even if there are polycrystalline regions in the first electrode 450, their impact on the performance of the device is relatively small.

[0098] Furthermore, since the recessed structure AC is formed based on the etching of the hard mask layer 510 and the mask sidewall 530, and the hard mask layer 510 is used to etch and form the vertical channel 401, the first electrode 450 is formed in the recessed structure AC such that the first electrode 450 is formed by self-alignment of the hard mask layer 510 (or the vertical channel 401). Therefore, the first electrode 450 of different VFETs can be made to have the same size and regular shape, and the orthogonal projection of the first electrode 450 on the substrate 310 can be symmetrically arranged with respect to the orthogonal projection of the vertical channel 401 on the substrate 310, thereby improving the reliability of the device. Specifically, the orthogonal projection of the first electrode 450 onto the substrate 310 has a first orthogonal projection region Db1, a second orthogonal projection region Db2, and a third orthogonal projection region Db3. The first orthogonal projection region Db1 coincides with the orthogonal projection of the vertical channel 401 onto the substrate 310. The second orthogonal projection region Db2 and the third orthogonal projection region Db3 are located on both sides of the first orthogonal projection region Db1 and are symmetrical about the first orthogonal projection region Db1.

[0099] Referring to Figure 3P, dry etching or wet etching is used to remove the sacrificial dielectric layer 540, exposing the sidewall of the first electrode 450.

[0100] Referring to FIG3Q, a dielectric material is grown on the surface of the substrate 310 having the first electrode 450 using at least one of deposition processes such as CVD, PECVD, PVD, ALD, and PEALD. This results in the conformal growth of a protective dielectric layer 460 on the sidewalls of each etch barrier layer 470, the surface of each etch barrier layer 470 facing away from the substrate 310, the sidewalls of each first electrode 450, and the surface of the first isolation dielectric layer 420 between each first electrode 450 facing away from the substrate 310. Subsequently, anisotropic etching is performed on the protective dielectric layer 460, retaining the protective dielectric layer 460 on the sidewalls of each etch stop layer 470 and each first electrode 450, and removing the protective dielectric layer 460 on the surface of each etch stop layer 470 facing away from the substrate 310 and the surface of the first isolation dielectric layer 420 between each first electrode 450 facing away from the substrate 310. This forms a protective dielectric layer on both sides of the first electrode 450 and the etch stop layer 470, protecting the sidewalls of the first electrode 450 from damage by subsequent etching processes. Based on this, the groove structure AC effectively penetrates the protective dielectric layer 460. Exemplarily, the material of the protective dielectric layer 460 includes, but is not limited to, dielectric materials such as silicon nitride (SiN). Furthermore, the materials of the protective dielectric layer 460 and the etch stop layer 470 can be the same or different.

[0101] Referring to Figure 3R, a protective dielectric layer 460 and an etch barrier layer 470 are used as an etch mask. Dry etching or wet etching is employed, and self-aligned etching removes the first isolation dielectric layer 420 exposed by the etch mask, thereby exposing the virtual gate 522 in the area not covered by the etch mask. It is worth noting that the first isolation dielectric layer 420 is formed based on self-alignment of the etch mask; therefore, the formed first isolation dielectric layer 420 is symmetrically arranged about the vertical channel, that is, the first isolation dielectric layer 420 is completely symmetrical along the central axis of the VFET, thereby improving device reliability.

[0102] Referring to FIG3S, wet etching is used to etch away the virtual gate 522 exposed by the first isolation dielectric layer 420, and further etch away the gate oxide layer 521 between the virtual gate 522 and the vertical channel 401 to expose the area of ​​the vertical channel 401 covered by the virtual gate 522.

[0103] Referring to Figure 3T, a gate dielectric layer 412 is grown on the sidewall of the exposed vertical channel 401. Then, a metal material is filled to form a gate conductive layer 411, thereby forming a gate structure 410. Afterwards, planarization can be performed using processes such as CMP to expose a protective dielectric layer 460 and an etch barrier layer 470. Furthermore, a high-k dielectric material layer can be formed before forming the gate conductive layer 411, thus making the formed gate structure 410 a high-k metal gate (HKMG). The material of the high-k dielectric material layer includes, but is not limited to, HfO2. The high-k dielectric material layer is not shown in Figure 3T.

[0104] Referring to Figure 3U, the protective dielectric layer 460 and the etch barrier layer 470 are used as etching masks. Dry etching or wet etching is employed to remove the gate structure 410, the second isolation dielectric layer 440, and the second electrode 430 exposed by the etching mask through self-aligned etching. This self-aligned etching cuts off the gate conductive layer 411, the second isolation dielectric layer 440, and the second electrode 430 of different VFETs, thereby realizing the replacement metal gate (RMG) process. Subsequently, in the direction from the first isolation dielectric layer 420 to the second isolation dielectric layer 440, the substrate 310 is etched at a third predetermined distance h3 to form isolation trenches in the substrate 310, thereby forming multiple VFETs spaced apart from each other and isolating the different VFETs using the isolation trenches. It is understood that the substrate 310 can also be etched to form isolation trenches during the etching of the gate structure 410, the second isolation dielectric layer 440, and the second electrode 430. Alternatively, since the etching barrier layer 470 may also be damaged during the etching of the gate structure 410, the second isolation dielectric layer 440 and the second electrode 430, and considering that the thickness of the etching barrier layer may not be sufficient to support the etching isolation trench, a photolithography step can be added after etching the gate structure 410, the second isolation dielectric layer 440 and the second electrode 430 to form photoresist on the protective dielectric layer 460 and the etching barrier layer 470, and then the substrate 310 is etched to form the isolation trench, thereby realizing the semi-self-aligned etching isolation trench between the devices.

[0105] It is worth mentioning that the second isolation dielectric layer 440 and the second electrode 430 are formed based on self-alignment of the etching mask. Therefore, the formed second isolation dielectric layer 440 and second electrode 430 are symmetrically arranged about the vertical channel, that is, the second isolation dielectric layer 440 and the second electrode 430 are completely symmetrical along the central axis of the VFET, thereby improving the reliability of the device. Thus, each formed VFET is completely symmetrical along its central axis, further improving the reliability of the device. Furthermore, using self-alignment to form the VFET reduces the complexity of the process and eliminates errors in the photolithography process, further enhancing the reliability of the device.

[0106] Referring to FIG3V, a dielectric material is deposited on substrate 310 using at least one deposition process, such as CVD, PECVD, PVD, ALD, PEALD, etc., to form an interlayer dielectric layer 501 covering multiple VFETs. The interlayer dielectric layer 501 also fills the regions between different VFETs. By filling isolation trenches with the interlayer dielectric layer 501, a trench isolation structure (e.g., a shallow trench isolation (STI) structure) can be formed to isolate different VFETs using the interlayer dielectric layer 501. Exemplarily, the material of the interlayer dielectric layer 501 may include, but is not limited to: silicon dioxide (SiO2), silicon oxycarbide (SiCO), silicon nitride (Si3N4), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon carbonitride (SiOCN), or combinations thereof.

[0107] Afterwards, subsequent metal interconnection processes can be performed to complete the chip fabrication process. For example, referring to Figure 3W, dry etching or wet etching is used to form through-hole contact holes in the etch barrier layer 470 and the interlayer dielectric layer 501, exposing a portion of the first electrode 450 through the contact holes, so that the etch barrier layer does not completely cover the first electrode 450. Then, at least one of the deposition processes such as CVD, PECVD, PVD, ALD, and PEALD is used to deposit conductive material (e.g., metal material) in the contact holes to form a first conductive contact portion 502 connected to the first electrode 450. Then, electrically connected signal traces can be formed on the first conductive contact portion 502 to transmit signals to the first electrode 450 through the signal traces. Similarly, a second conductive contact portion connected to the second electrode 430 and its electrically connected signal traces can be formed, as well as a third conductive contact portion connected to the gate conductive layer and its electrically connected signal traces can be formed to realize signal transmission to the second electrode 430 and the gate conductive layer 411.

[0108] The above description is only a specific implementation of this application, but the protection scope of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the protection scope of this application.

Claims

1. A chip, characterized in that, include: A substrate and a plurality of vertical field-effect transistors (VFETs) disposed on the substrate; Each of the VFETs includes: Vertical channels extend in a direction perpendicular to the substrate; A stacked structure is disposed at least on both sides of the vertical channel. The stacked structure includes a gate structure and a first isolation dielectric layer stacked along a direction perpendicular to the substrate. The first isolation dielectric layer is disposed on the side of the gate structure facing away from the substrate. A groove structure is provided on the side of the stacked structure facing away from the substrate; A first electrode is filled in the groove structure. The material of the first electrode is a heavily doped and crystalline semiconductor material. The first electrode has a polycrystalline region and a single-crystal region, and the polycrystalline region is formed at the corner of the first electrode facing the substrate.

2. The chip as described in claim 1, characterized in that, The groove structure includes a first region and a second region, the first region being located between the second region and the substrate, and the first electrode filling the first region; The VFET further includes an etch barrier layer that fills the second region and covers at least a portion of the surface of the first electrode facing away from the substrate.

3. The chip as described in claim 1 or 2, characterized in that, It also includes a protective dielectric layer disposed on the side of the stacked structure facing away from the substrate, and the groove structure penetrates the protective dielectric layer.

4. The chip according to any one of claims 1-3, characterized in that, The semiconductor material of the first electrode has the same lattice constant as the semiconductor material of the vertical channel; The single-crystal region extends from the surface of the vertical channel on the side opposite to the substrate to the surface of the first electrode on the side opposite to the substrate.

5. The chip as described in claim 4, characterized in that, The orthographic projection of the polycrystalline region onto the substrate does not overlap with the orthographic projection of the vertical channel onto the substrate.

6. The chip as described in claim 4 or 5, characterized in that, The polycrystalline region is formed on the corner of the first electrode facing away from the substrate.

7. The chip according to any one of claims 1-6, characterized in that, The interface between the polycrystalline region and the single-crystal region is a high-index crystal plane of the semiconductor material in the first electrode.

8. The chip according to any one of claims 1-7, characterized in that, The groove structure is used to expose at least a portion of the surface of the vertical channel on the side opposite to the substrate, and the first electrode contacts the vertical channel exposed by the groove structure.

9. The chip as described in claim 8, characterized in that, The groove structure is used to expose the entire area of ​​the surface of the vertical channel facing away from the substrate.

10. The chip as described in claim 9, characterized in that, The first electrode has a first projection region, a second projection region, and a third projection region in its orthogonal projection onto the substrate. The first projection region coincides with the orthogonal projection of the vertical channel onto the substrate. The second and third projection regions are located on either side of the first projection region and are symmetrical about the first projection region.

11. The chip as described in claim 9 or 10, characterized in that, The first isolation dielectric layer covers the sidewall of the vertical channel through the gate oxide layer. The surface of the vertical channel facing away from the substrate is lower than the surface of the first isolation dielectric layer facing away from the substrate, and the surface of the vertical channel facing away from the substrate is higher than the surface of the gate structure facing away from the substrate, so that the gate oxide layer and the vertical channel enclose and form a recessed structure. The first electrode also fills the recessed structure.

12. The chip according to any one of claims 1-11, characterized in that, The gate structure and the first isolation dielectric layer are symmetrical about the vertical channel.

13. The chip according to any one of claims 1-12, characterized in that, The stacked structure further includes a second electrode and a second isolation dielectric layer, the second electrode being disposed between the substrate and the second isolation dielectric layer, and the gate structure being disposed on the side of the second isolation dielectric layer facing away from the substrate.

14. The chip as described in claim 13, characterized in that, The second electrode and the second insulating dielectric layer are symmetrical about the vertical channel.

15. A method for fabricating a chip, characterized in that, The method includes: A vertical channel and a stacked structure at least on both sides of the vertical channel are formed on a substrate. The vertical channel extends in a direction perpendicular to the substrate. The stacked structure includes a gate structure and a first isolation dielectric layer stacked in a direction perpendicular to the substrate. The first isolation dielectric layer is disposed on the side of the gate structure facing away from the substrate. A groove structure is formed on the side of the stacked structure facing away from the substrate; A first electrode is formed in the groove structure using a solid-state epitaxial process, and the material of the first electrode is a heavily doped and crystalline semiconductor material. The first electrode has a polycrystalline region and a single-crystal region, and the polycrystalline region is formed at the corner of the first electrode facing the substrate.

16. The preparation method according to claim 15, characterized in that, The first electrode is formed in the groove structure, and the material of the first electrode is a heavily doped and crystalline semiconductor material, and the first electrode has a polycrystalline region and a single-crystal region, including: A deposition process is used to fill the groove structure with a layer of heavily doped amorphous semiconductor material; A thermal annealing solid-state epitaxial process is used to crystallize the amorphous semiconductor material layer, forming a first electrode with polycrystalline and monocrystalline regions.

17. The preparation method according to claim 16, characterized in that, After filling the groove structure with a heavily doped amorphous semiconductor material layer, and before crystallizing the amorphous semiconductor material layer using a thermal annealing solid-state epitaxy process, the method further includes: The amorphous semiconductor material layer is etched such that the surface of the amorphous semiconductor material layer facing away from the substrate is lower than the surface of the sacrificial dielectric layer facing away from the substrate, and the surface of the amorphous semiconductor material layer facing away from the substrate is higher than the surface of the first isolation dielectric layer facing away from the substrate. A dielectric material is filled in the groove structure on the side of the amorphous semiconductor material layer facing away from the substrate to form an etch barrier layer.

18. The preparation method according to any one of claims 15-17, characterized in that, A hard mask layer is formed on the side of the vertical channel facing away from the substrate, and a groove structure is formed on the side of the stacked structure facing away from the substrate, including: Mask sidewalls and sacrificial dielectric layers are formed on both sides of the hard mask layer; Etching removes at least a portion of the hard mask layer and the mask sidewalls, forming a groove structure in the sacrificial dielectric layer.

19. The preparation method according to claim 18, characterized in that, After forming the first electrode, the process further includes: Etching removes the sacrificial dielectric layer; A protective dielectric layer is formed on both sides of the first electrode.

20. An electronic device, characterized in that, include: The circuit board and the chip as described in any one of claims 1-14, wherein the chip is disposed on the circuit board.

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