Micro light-emitting diode driving substrate, preparation method and display apparatus

Abstract

The present application belongs to the field of display. Disclosed are a micro light-emitting diode driving substrate, a preparation method and a display apparatus. In each pixel region of the micro light-emitting diode driving substrate, a first analog domain circuit and a first digital domain circuit of each pixel driving circuit are stacked in the vertical direction, and there is spatial position overlap between the two. The first digital domain circuit is used for generating a first control signal, and the first control signal is used for controlling the on / off state and on-duration of a switch element in the first analog domain circuit. The technical solution of the present application can use the structure of devices to separate analog domain circuits from digital domain circuits, thereby avoiding the problem of crosstalk of signals of devices in different voltage domains; moreover, the arrangement in the vertical direction can reduce the area occupied by driving circuits on a base substrate, thus effectively reducing the area of pixel regions, and facilitating improvement of the pixel density of display apparatuses.

Description

Micro light emitting diode driving substrate, preparation method and display device

[0001] Priority information

[0002] The present application claims priority to and the benefit of the filing date of the patent application with the China National Intellectual Property Office, with the patent application number of “202411060523.5” submitted on August 2, 2024, and incorporates it herein by reference in its entirety. TECHNICAL FIELD

[0003] The present application belongs to the field of display technology, and particularly relates to a micro light emitting diode driving substrate, a preparation method and a display device. BACKGROUND

[0004] In a micro light emitting diode display device, the pixel driving circuit on the driving substrate usually adopts a digital-analog hybrid method to drive the micro light emitting diode, that is, digital domain circuit and analog domain circuit are arranged in the same pixel driving circuit. Since the digital domain circuit usually uses a large number of digital gate circuit elements, it will consume a large area. In addition, the digital domain circuit usually adopts low-voltage domain devices, while the analog domain circuit usually adopts medium-voltage domain devices to match the opening voltage of the micro light emitting diode. In the prior art micro light emitting diode driving substrate, in order to avoid the signal crosstalk problem of different voltage domain devices, the distance between the analog domain circuit and the digital domain circuit on the substrate needs to meet the corresponding design rules, and a certain width gap can be used, which results in the waste of part of the area on the substrate and makes the area of a single pixel driving circuit too large, which reduces the pixel density of the display device. SUMMARY

[0005] The present application provides a micro light emitting diode driving substrate, a preparation method of the micro light emitting diode driving substrate and a micro light emitting diode display device, which aims to avoid the signal crosstalk problem of different voltage domain devices on the micro light emitting diode driving substrate, reduce the occupied area of the pixel driving circuit on the substrate, and improve the pixel density of the display device. At the same time, the occupied area of the peripheral driving circuit on the substrate can also be reduced, and the cost can be saved.

[0006] In a first aspect, the present application provides a micro light emitting diode driving substrate, comprising:

[0007] a substrate, a display area is formed on the substrate, and a plurality of pixel regions are arranged in the display area;

[0008] The pixel driving circuit is located in each pixel region, and each pixel driving circuit comprises a first digital domain circuit and a first analog domain circuit, wherein the first analog domain circuit and the first digital domain circuit are vertically stacked and overlap in space.

[0009] In some embodiments, the substrate substrate is further formed with a peripheral driving circuit in the peripheral region, the peripheral driving circuit comprising a second digital domain circuit and a second analog domain circuit, the second analog domain circuit and the second digital domain circuit being vertically stacked and overlapping in space.

[0010] In some embodiments, the first control signal is a mixed modulation signal mixed with first analog information and first digital information, the first analog information being used to control the on-off state of the switching element in the first analog domain circuit, and the first digital information being used to control the on duration of the switched-on switching element.

[0011] In some embodiments, the first digital domain circuit comprises a control signal generation module, which is used to generate the first control signal and output from the control signal output end of the control signal generation module.

[0012] In some embodiments, the second digital domain circuit comprises a clock module, which is used to generate a clock signal, and the clock signal is input to the control signal generation module so that the control signal generation module generates the first control signal according to the clock signal.

[0013] In some embodiments, the control signal generation module is also used to receive a pixel data signal, and the control signal generation module is used to generate the first control signal according to the pixel data signal and the clock signal.

[0014] In some embodiments, the pixel data signal is a mixed signal mixed with second analog information and second digital information, and the second analog information and the second digital information are obtained after the mixed signal is analyzed; or the pixel data signal comprises a second analog information and a second digital information.

[0015] In some embodiments, the control signal generation module comprises a counter, a comparator and a logic operation gate circuit.

[0016] The counter is used to receive the clock signal and count the number of pulses of the clock signal and output. The comparator is used to generate digital pulse width modulation information according to the count value output by the counter and the second digital information in the pixel data signal, and output the digital pulse width modulation information to the logic operation gate circuit. The logic operation gate circuit is used to generate the first control signal according to the second analog information in the pixel data signal and the digital pulse width modulation information.

[0017] In some embodiments, the level of the digital pulse width modulation information is the first level when the count value output by the counter is less than or equal to a set value, and the level of the digital pulse width modulation information is the second level when the count value output by the counter is greater than the set value. The set value is determined according to the second digital information in the pixel data signal.

[0018] In some embodiments, the output end of the logic operation gate circuit outputs the first control signal when the level of the digital pulse width modulation information is the first level and the level of the second analog information is the first level, and controls the switch element in the first analog domain circuit to be turned on, otherwise, controls the switch element in the first analog domain circuit to be turned off. Alternatively, the output end of the logic operation gate circuit outputs the first control signal when the level of the digital pulse width modulation information is the first level and the level of the second analog information is the first level, and controls the switch element in the first analog domain circuit to be turned off, otherwise, controls the switch element in the first analog domain circuit to be turned on.

[0019] In some embodiments, the second analog information of the pixel data signal is directly input to the logic operation gate circuit, and the second digital information of the pixel data signal is directly input to the comparator. Alternatively, the first digital domain circuit further comprises a storage module for storing at least one of the second analog information and the second digital information of the pixel data signal, and at least one of the second analog information and the second digital information of the pixel data signal is input to the logic operation gate circuit from the storage module.

[0020] In some embodiments, the second digital domain circuit further comprises a digital processing module for outputting the pixel data signal.

[0021] In some embodiments, the first analog domain circuit comprises at least two groups of current mirror branches, each group of current mirror branches comprising a first transistor and a second transistor, the drain electrode of the first transistor being electrically connected to the source electrode of the second transistor, the gate electrodes of the first transistors in the at least two groups of current mirror branches being electrically connected to each other, the drain electrodes of the second transistors in the at least two groups of current mirror branches being connected to each other and serving as a driving signal output end of the pixel driving circuit for outputting a current signal.

[0022] The control signal output end of the control signal generation module is electrically connected to the gate electrodes of the second transistors in the at least two groups of current mirror branches, for controlling the on-off state and the on duration of the second transistors in the at least two groups of current mirror branches.

[0023] The second analog domain circuit comprises a group of current mirror reference circuits, each current mirror reference circuit comprising a third transistor and a fourth transistor, the drain electrode of the third transistor being electrically connected to the source electrode of the fourth transistor, the drain electrode and the gate electrode of the third transistor being electrically connected to the gate electrodes of the first transistors, for providing reference currents for the at least two groups of current mirror branches in the first analog domain circuit.

[0024] In some embodiments, the first transistor and the third transistor are the same type of device, the second transistor and the fourth transistor are the same type of device, and the width-length ratio of the at least two first transistors and the width-length ratio of the third transistor have a preset proportional relationship.

[0025] In some embodiments, the first analog domain circuit further comprises a first level converter module for converting a level range of the first control signal.

[0026] In some embodiments, the second digital domain circuit further comprises a digital decoder for outputting a voltage level adjustment signal. The second analog domain circuit further comprises a second level conversion circuit, an output terminal of the second level conversion circuit being electrically connected to the gate of the fourth transistor, for outputting driving voltages of different levels according to the voltage level adjustment signal.

[0027] In the above embodiments, by stacking the first analog domain circuit and the first digital domain circuit in the pixel driving circuit in the vertical direction, the first digital domain circuit and the first analog domain circuit of the pixel driving circuit no longer lay on the substrate, but adopt a layout mode of stacking up and down, and the digital signal and the analog signal are pulled apart in the vertical direction by the structure of the device itself, so that the crosstalk between the signals is reduced, and the occupied area of the pixel driving circuit on the substrate is reduced, so that the occupied area of each pixel region is reduced, and the pixel density of the display device is further improved. Similarly, the second analog domain circuit and the second digital domain circuit of the peripheral driving circuit can also be stacked in the vertical direction, and the second analog domain circuit and the second digital domain circuit of the peripheral driving circuit exist in spatial position overlap, so as to further reduce the occupied area of the peripheral driving circuit on the substrate and save costs.

[0028] In the above embodiments, the first digital domain circuit is configured to generate a first control signal, and the first control signal is configured to control the on-off state and the conduction time length of the switching element in the first analog domain circuit. The on-off state of the switching element corresponds to the final output current size of the output terminal of the first analog domain circuit, and the conduction time length corresponds to the light-emitting time length of the related micro light-emitting diode. Compared with the related art in which the related analog domain circuit regulates the current size and the related digital domain circuit adjusts the light-emitting time length, the control of the present application is more concise and has higher integration.

[0029] On the other hand, the present application also provides a preparation method of a micro light-emitting diode driving substrate, comprising:

[0030] providing a substrate, and arranging a plurality of pixel regions in a display area of the substrate;

[0031] The first analog domain circuit and the first digital domain circuit are formed in each pixel region of the substrate, wherein the first analog domain circuit and the first digital domain circuit are vertically stacked and have spatial position overlap. The first digital domain circuit is configured to generate a first control signal, and the first control signal is configured to control the on-off state and the conduction duration of a switching element in the first analog domain circuit.

[0032] In some embodiments, the preparation method further comprises: forming a second analog domain circuit and a second digital domain circuit in a peripheral region of the substrate, wherein the second analog domain circuit and the second digital domain circuit are vertically stacked and have spatial position overlap.

[0033] In some embodiments, the step of forming the first digital domain circuit and the first analog domain circuit in each pixel region of the substrate further comprises:

[0034] The first digital domain circuit is formed on the substrate and comprises a control signal generation module;

[0035] The first digital domain circuit is formed on the substrate and comprises a control signal generation module;

[0036] The first analog domain circuit is formed on the first passivation layer, and the first analog domain circuit comprises at least two groups of current mirror branches. Each group of current mirror branches comprises a first transistor and a second transistor. The drain of the first transistor is electrically connected to the source of the second transistor. The gates of the first transistors in the at least two groups of current mirror branches are electrically connected to each other. The drains of the second transistors in the at least two groups of current mirror branches are connected to each other and serve as a driving signal output end of a pixel driving circuit. The control signal output end of the control signal generation module is electrically connected to the gates of the second transistors in the at least two groups of current mirror branches.

[0037] In some embodiments, the step of forming the first analog domain circuit on the first passivation layer further comprises:

[0038] The gates of the first transistor and the second transistor are formed on the first passivation layer. The gate of the second transistor is electrically connected to the control signal output end of the first digital domain circuit through the first via hole.

[0039] The first active layer of the first transistor and the second active layer of the second transistor are formed on the first gate metal layer.

[0040] The source and the drain of the first transistor are formed above the first active layer, and the source and the drain of the second transistor are formed above the second active layer. Each first transistor in the at least two groups of current mirror branches has a preset width-length ratio.

[0041] The micro light emitting diode driving substrate prepared by the preparation method has the same technical effects as the micro light emitting diode driving substrate of the first aspect, and details are not repeated here.

[0042] In another aspect, the application provides a micro light emitting diode display device, which comprises any of the micro light emitting diode driving substrates of the first aspect, and a light emitting diode in each pixel region, the light emitting diode being electrically connected to the driving signal output end of the first analog domain circuit.

[0043] The micro light emitting diode display device has the same technical effects as the micro light emitting diode driving substrate of the first aspect, and details are not repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0044] The above and / or additional aspects and advantages of the application will become apparent and more readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings, in which:

[0045] FIG. 1 is a basic architecture diagram of a peripheral driving circuit of a related micro light emitting diode display device;

[0046] FIG. 2 is a layout plan view of a related micro light emitting diode pixel driving circuit;

[0047] FIG. 3 is a device cross-sectional view of a related micro light emitting diode pixel driving circuit;

[0048] FIG. 4 is a structure schematic diagram of a micro light emitting diode driving substrate provided by an embodiment of the application;

[0049] FIG. 5 is a structure schematic diagram of another micro light emitting diode driving substrate provided by an embodiment of the application;

[0050] FIG. 6 is a display device driving circuit architecture diagram of a digital-analog hybrid modulation method based on a current mirror structure provided by an embodiment of the application;

[0051] FIG. 7 is a control signal generation module circuit architecture diagram provided by an embodiment of the application;

[0052] FIG. 8 is a driving circuit timing diagram provided by an embodiment of the application;

[0053] FIG. 9 is a partial circuit architecture diagram of a peripheral driving circuit provided by an embodiment of the application;

[0054] FIG. 10 is a flowchart of a preparation method of a micro light emitting diode driving substrate provided by an embodiment of the application;

[0055] FIG. 11 is a device cross-sectional view of a driving substrate prepared by a preparation method provided by an embodiment of the application;

[0056] FIG. 12 is a structural schematic diagram of a micro-LED display device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0057] The technical solutions in some embodiments of the present application will be clearly and completely described below with reference to the drawings. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by a person of ordinary skill in the art belong to the scope of protection of the present application.

[0058] Unless otherwise required by the context, throughout the specification and claims, the term "comprising" is to be interpreted as open, inclusive, meaning "including, but not limited to".

[0059] Hereinafter, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first" and "second" can explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, unless otherwise stated, the meaning of "a plurality of" is two or more.

[0060] In describing some embodiments, the term "connected" and its derivatives can be used. The term "connected" should be interpreted broadly, for example, "connected" can be fixedly connected, or detachably connected, or integrated; can be directly connected, or indirectly connected through an intermediate medium. For example, in describing some embodiments, the term "connected" can be used to indicate that two or more components have direct physical or electrical contact with each other.

[0061] In addition, the use of "based on" means open and inclusive, because the process, step, calculation or other action "based on" one or more stated conditions or values can be based on additional conditions or values beyond those stated in practice.

[0062] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can be that the layer or element is directly on the other layer or substrate, or there can be an intermediate layer between the layer or element and the other layer or substrate.

[0063] Exemplary embodiments are described herein with reference to cross-sectional illustrations that are idealized exemplary illustrations. In the drawings, the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the drawings are schematic in nature and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

[0064] Examples of the embodiments are illustrated in the accompanying drawings, wherein like or similar elements are designated with the same or similar reference numerals throughout the several views. The embodiments described below by reference to the drawings are exemplary only, and are merely intended to explain the present application, and are not to be construed as limiting the present application.

[0065] The light emitting intensity and light wave peak of micro light emitting diode device are greatly affected by current density, and the brightness and color coordinates under different current values will change, so in a micro light emitting diode display device, a digital-analog hybrid driving mode is usually used: in the same bias voltage, the gate voltage in the analog circuit driving the light emitting diode does not change, and the digital modulation mode is set on the light emitting path to realize the on-off of the light emitting path, so as to adjust the light emitting time in a frame. Under the same driving current, the light emitting intensity of the micro light emitting diode device is a function of the light emitting time, and the digital modulation mode can realize the adjustment of the brightness by controlling the on-off time of the light emitting path. Therefore, to realize the adjustment of different brightness of the micro light emitting diode under the same current, it is necessary to set the digital domain circuit and the analog domain circuit in the pixel area of the same light emitting diode at the same time.

[0066] In addition to the pixel driving circuit in the pixel area, a peripheral driving circuit is also formed on the substrate, and the peripheral driving circuit is also divided into a digital domain circuit and an analog domain circuit. FIG. 1 is a basic architecture diagram of the peripheral driving circuit of the related micro light emitting diode display device, wherein the solid line range is the analog domain circuit, and the dotted line range is the digital domain circuit. The diagram is only schematic, and the specific structure can be designed according to the needs of the micro light emitting diode display device.

[0067] Since the turn-on voltage of the micro light emitting diode is relatively large, the related devices in the analog domain circuit of the pixel driving circuit need to be matched with it, that is, the voltage difference of each terminal of the device needs to be less than the voltage that the device can withstand, so the analog domain circuit usually uses medium voltage domain devices, and the medium voltage domain devices have relatively large sizes; and the main function of the digital domain circuit is logic control, and a large number of digital gate circuits need to be used to realize digital control, which will consume a large area, and usually small size devices in low voltage domain are used. Moreover, they are usually CMOS devices.

[0068] In the related art, in order to avoid the crosstalk problem of different voltage domain device signals in the pixel driving circuit, the analog domain circuit and the digital domain circuit are usually placed in different deep N-wells (DNW), and the distance between the deep N-wells also needs to meet certain design rules, that is, a gap meeting certain requirements is set, and the analog domain circuit and the digital domain circuit are tiled on the substrate with a certain distance, which causes the area of a single pixel region to be too large, part of the area on the substrate is wasted, and thus the pixel density of the display device is reduced.

[0069] FIGS. 2 and 3 are schematic diagrams of the layout plane and the device cross section of the related micro light emitting diode pixel driving circuit. As shown in FIG. 2, it is a partial plane view of 9 pixel regions, the size of a single pixel is about 2-5 um, and a pixel driving circuit 10 is arranged in each pixel region. Specifically, the pixel driving circuit 10 includes a first analog domain circuit 11 and a first digital domain circuit 12. FIG. 3 is a schematic diagram of the device structure of the partial cross section of a certain pixel region. In the diagram, only the device structure is shown in the dotted line frame, and the specific device and its connection mode are configured according to the specific circuit design. The first analog domain circuit 11 and the first digital domain circuit 12 are placed in different deep N-wells (DNW), and the distance between the deep N-wells also needs to meet certain design rules, that is, a gap meeting certain requirements is set. In the related art, the pixel driving circuit causes part of the area of a single pixel region to be wasted, and thus the pixel density of the display device is reduced.

[0070] In order to solve the contradiction between the signal crosstalk and the pixel region area, the present application provides a micro light emitting diode driving substrate. FIG. 4 is a schematic diagram of the structure of a micro light emitting diode driving substrate in an embodiment of the present application. As shown in FIG. 4, a display area is formed on a substrate M0 of the micro light emitting diode driving substrate, and a plurality of pixel regions are arranged in the display area. A pixel driving circuit 10 is arranged in each pixel region. The pixel driving circuit 10 includes a first analog domain circuit 11 and a first digital domain circuit 12. The first analog domain circuit 11 and the first digital domain circuit 12 are arranged in a vertical direction and overlap in space.

[0071] It should be noted that FIG. 4 shows the case where the first analog domain circuit 11 is arranged above the first digital domain circuit 12 in the vertical direction. It can be predicted that there is also a case where the first digital domain circuit 12 is arranged above the first analog domain circuit 11. In this case, the circuit composition and the corresponding functions of the first analog domain circuit 11 and the first digital domain circuit 12 do not change, and thus will not be described here.

[0072] In the pixel driving circuit 10, the first analog domain circuit 11 and the first digital domain circuit 12 are arranged in a vertical direction, and the first analog domain circuit 11 and the first digital domain circuit 12 are separated by the structure of the device itself, so that the devices in different voltage domains are kept at a certain distance, signal crosstalk is avoided, the area of the pixel driving circuit 10 on the substrate M0 is reduced, the area of the substrate M0 is not wasted, the area of a single pixel region is reduced, and the pixel density of the display device is further improved.

[0073] In some embodiments, in addition to arranging the first analog domain circuit 11 and the first digital domain circuit 12 in the pixel driving circuit 10 in a vertical direction in the pixel region, the peripheral driving circuit 20 arranged on the peripheral region of the substrate M0 can also be arranged in a vertical direction.

[0074] Specifically, as shown in FIG. 5, FIG. 5 is a structure diagram of another micro-LED driving substrate provided by an embodiment of the present application. The peripheral driving circuit 20 includes a second analog domain circuit 21 and a second digital domain circuit 22. The second analog domain circuit 21 and the second digital domain circuit 22 are arranged in a vertical direction and overlap in space. It should be noted that FIG. 5 shows that the first analog domain circuit 11 is arranged above the first digital domain circuit 12 in the vertical direction, and the second analog domain circuit 21 is arranged above the second digital domain circuit 22 in the vertical direction. Other predictable structures formed by adjusting the arrangement and combination are within the protection scope of the present application, and will not be enumerated here.

[0075] In the present embodiment, the second analog domain circuit 21 and the second digital domain circuit 22 are not tiled on the substrate, but are arranged in a vertical direction, and the second analog domain circuit 21 and the second digital domain circuit 22 are separated by the structure of the device itself, so that the devices in different voltage domains are kept at a certain distance, signal crosstalk is avoided, the area of the peripheral driving circuit 20 on the substrate M0 is reduced, the area of the peripheral driving circuit 20 on the substrate M0 is reduced, the cost is saved, and the usable area of the pixel region is further expanded, which is beneficial to further improve the pixel density.

[0076] FIG. 6 is a display device driving circuit architecture diagram of a digital-analog hybrid modulation method based on a current mirror structure provided by an embodiment of the present application. It should be noted that the present figure includes circuit architectures related to various embodiments, and each specific embodiment can be combined with circuit design and selected according to actual needs.

[0077] In some embodiments, as shown in FIG. 6, the first control signal is a mixed modulation signal mixing the first analog information and the first digital information, wherein the first analog information is used to control the on-off state of the switching element in the first analog domain circuit 11, and the first digital information is used to control the on duration of the switched-on switching element.

[0078] In this embodiment, the first analog information for controlling the on-off state of the element and further controlling the current size, and the first digital information for controlling the on duration of the element and further controlling the light-emitting duration of the micro light-emitting diode element, are both contained in the first control signal, that is, both are generated by the first digital domain circuit 12. Compared with the related art, the control is more concise and the integration is higher.

[0079] In some embodiments, as shown in FIG. 6, the first digital domain circuit 12 includes a control signal generation module 1201, which is used to generate the first control signal and output from the control signal output end of the control signal generation module 1201.

[0080] In some embodiments, the first analog domain circuit 11 includes at least two groups of current mirror branches 110, and each group of current mirror branches 110 includes a first transistor 1101 and a second transistor 1102, as shown in FIG. 6, which lists the number <0>~number <m-1>The drain of the first transistor 1101 is electrically connected with the source of the second transistor 1102, the gates of the first transistors 1101 in at least two groups of current mirror branches 110 are electrically connected with each other, the drains of the second transistors 1102 in at least two groups of current mirror branches 110 are connected with each other and serve as a driving signal output end of the pixel driving circuit 10, for outputting a current signal.

[0081] The control signal output end of the control signal generation module 1201 is electrically connected with the gate of the second transistor 1102 in at least two groups of current mirror branches 110, for controlling the on-off state and conduction time of the second transistor 1102 in at least two groups of current mirror branches 110.

[0082] In some embodiments, as shown in FIG. 6, the second digital domain circuit 22 includes a clock module 2201, which is used to generate a clock signal, and the clock signal is input to the control signal generation module 1201, so that the control signal generation module 1201 generates the first control signal according to the clock signal.

[0083] The clock signal can be a period with equal width, or a period with unequal width according to requirements; it can be one way or multiple ways.

[0084] In some embodiments, the second analog domain circuit 21 includes a group of current mirror reference circuits 210, and the current mirror reference circuit 210 includes a third transistor 2101 and a fourth transistor 2102, the drain of the third transistor 2101 is electrically connected with the source of the fourth transistor 2102, and the drain and the gate of the third transistor 2101 are electrically connected with the gate of each first transistor 1101, to provide a reference current I ref for at least two groups of current mirror branches 110 in the first analog domain circuit 11.

[0085] The second analog domain circuit 21 mainly functions to realize voltage-to-current conversion and provide a reference current source I ref for the current mirror, which is conducive to realizing sharing of circuit modules and reducing circuit complexity, and can make full use of the original bandgap reference circuit module and provide a reference current I ref for the current mirror.

[0086] This embodiment is a driving circuit design based on the current mirror structure, and according to the circuit design, each group of current mirror branches 110 can copy the reference circuit current I ref in a certain proportion, as shown in FIG. 6, number <0>~number <m-1>The M groups of current mirror branches 110 are sequentially labeled as the 1st group, the 2nd group, …, and the Mth group, and the copy ratios of each group are sequentially labeled as K(1), K(2), …, and K(M). The branch current provided by the ith group of current mirror branches 110 is K(i)*I ref where i is any integer value in 1 to M.

[0087] The M groups of current mirror branches 110 can provide M groups of branch currents. The control signal generation module 1201 is configured to control the on-off state of the second transistor 1102 and the on duration of the turned-on transistor. The branch currents provided by the current mirror branches 110 are superimposed according to the on-off state of the second transistor 1102, forming an output current signal of the first analog domain circuit 11. Finally, the driving current output by the first analog domain circuit 11 controls the light emission of the micro light emitting diode, which can be used to adjust the display effect of the display device.

[0088] In some embodiments, as shown in FIG. 6, the control signal generation module 1201 is also configured to receive a pixel data signal. The control signal generation module 1201 generates the first control signal according to the pixel data signal and the clock signal.

[0089] In some embodiments, the pixel data signal is a mixed signal mixed with the second analog information and the second digital information. The second analog information and the second digital information are obtained after the mixed signal is analyzed. Alternatively, unlike the above-mentioned mixed modulation method, the pixel data signal includes one piece of second analog information and one piece of second digital information.

[0090] The control signal generation module 1201 can also be called a pulse width modulation (PWM) controller and an analog modulation module. The input signal of the module is the received pixel data signal, which contains the second analog information (Analog Bits) and the second digital information (Digital Bits). The second analog information (Analog Bits) and the second digital information (Digital Bits) can be mixed together to jointly determine the relevant modulation information, i.e., a mixed signal (Analog&Digital mixed signal). Alternatively, the second analog information (Analog Bits) and the second digital information (Digital Bits) can occupy a certain number of bits, i.e., they can be divided into one piece of second analog information (Analog Bits) and one piece of second digital information (Digital Bits).

[0091] The corresponding mixed signal, or the second analog information and the second digital information each occupying a certain number of bits, can be matched to the corresponding modulation signal through the information table with a certain corresponding relationship pre-configured, through the look-up table matching manner. For example, the mixed signal is set to 0001 corresponding to the second analog information being 1 and the second digital information being 0, 0010 corresponding to the second analog information being 1 and the second digital information being 1, 0011 corresponding to the second analog information being 1 and the second digital information being 2, and so on. This way is relatively random, but the corresponding way can be defined flexibly in advance, so that the data input mode is more flexible and adjustable.

[0092] In some embodiments, the control signal generation module 1201 includes a counter 1211, a comparator 1212 and a logic operation gate circuit 1213.

[0093] As shown in FIG. 7, FIG. 7 is a control signal generation module circuit architecture diagram provided by an embodiment of the present application. The counter 1211 is configured to receive a clock signal and count the number of pulses of the clock signal and output. The comparator 1212 is configured to generate digital pulse width modulation information according to the count value output by the counter 1211 and the second digital information in the pixel data signal, and output the digital pulse width modulation information to the logic operation gate circuit 1213. The logic operation gate circuit 1213 is configured to generate a first control signal according to the second analog information in the pixel data signal and the digital pulse width modulation information.

[0094] As shown in FIGS. 6-7, the number EM<0> output port in FIG. 7 outputs the corresponding first control signal to the switching element of the first analog domain circuit 11 in FIG. 6, that is, the second transistor 1102 numbered N<0>. The number EM <m-1>The output port, the corresponding first control signal output to the switch element of the first analog domain circuit 11 in Figure 6, that is, the number N <m-1>The second transistor 1102, and so on.

[0095] In the control signal generation module 1201, i.e., the pulse width modulation (PWM) controller and the analog modulation module, the comparator 1212 performs PWM modulation according to the input second digital information and the clock signal, to control the light-emitting time and the off time of the micro light-emitting diode. The analog modulation adjusts the on or off state of the second transistor 1102 in the M groups of current mirror branches 110 in the first analog domain circuit 11 according to the input second analog information, to select the current of different current mirror branches 110, and thus determine the size of the final output driving current. Finally, the analog modulation selects the working state of the corresponding current mirror branch according to the input second analog information, and the PWM signal controls the light-emitting time length of the turned-on branch, and the two together determine the light-emitting brightness of the micro light-emitting diode.

[0096] Regarding the process of generating digital pulse width modulation information by the comparator 1212, specifically, in some embodiments, when the count value output by the counter 1211 is less than or equal to a set value m, the level of the digital pulse width modulation information is a first level, and when the count value output by the counter is greater than the set value m, the level of the digital pulse width modulation information is a second level. The set value m is determined according to the second digital information in the pixel data signal.

[0097] In some embodiments, when the level of the digital pulse width modulation information is the first level and the level of the second analog information is the first level, the output end of the logic operation gate circuit 1213 outputs a first control signal to control the second transistor 1102 in the first analog domain circuit 11 to be turned on, otherwise, the second transistor 1102 is controlled to be turned off. That is, the logic operation gate circuit 1213 adopts an "AND gate".

[0098] Alternatively, when the level of the digital pulse width modulation information is the first level and the level of the second analog information is the first level, the output end of the logic operation gate circuit 1213 outputs a first control signal to control the second transistor 1102 in the first analog domain circuit 11 to be turned off, otherwise, the second transistor 1102 is controlled to be turned on. That is, the logic operation gate circuit 1213 adopts an "AND NOT gate".

[0099] For example, as shown in FIG. 8, which is a driving circuit timing diagram provided by an embodiment of the present application, in combination with FIGS. 6-8, taking the second digital information as 8 bits, the second analog information as 4 bits, the number of current mirror branches 110 as 4 groups, and the set value m of the counter 1211 as 3, and taking the 4-bit second analog information from high (MSB) to low (LSB) as 0111 as an example, when the count value output by the counter 1211 is less than or equal to the set value 3, the level of the digital pulse width modulation information is high.

[0100] When the logic operation gate circuit 1213 is an "AND gate", that is, when the level of the digital pulse width modulation information is high and the level of the second analog information is high, the output end of the logic operation gate circuit 1213 outputs the first control signal to control the second transistor 1102 to be turned on.

[0101] At this time, the timing diagram of the current signal output by the pixel driving circuit is shown in FIG. 8, where the low level of the Reset signal indicates reset, and the high level of the Reset signal corresponds to one frame. When the count value output by the counter 1211 is less than or equal to the set value 3, the level of the digital pulse width modulation information is high, and at this time, the first bit of the second analog information (Analog Bits 1) is high. Therefore, after passing through the "AND gate", the output EM<0> is high, that is, the second transistor 1102 numbered N<0> is turned on, and the current mirror branch 110 can provide a branch current K(1)*I ref .

[0102] Similarly, the second transistor 1102 numbered N<1> is turned on, and the current mirror branch 110 can provide a branch current K(2)*I ref , the second transistor 1102 numbered N<2> is turned on, and the current mirror branch 110 can provide a branch current K(3)*I ref , the second transistor 1102 numbered N<3> is turned off, and no branch current is provided. Finally, the pixel driving circuit outputs a current I = K(1)*I ref + K(2)*I ref + K(3)*I ref .

[0103] In some embodiments, as shown in FIG. 6, the second analog information of the pixel data signal is directly input to the logic operation gate circuit 1213, and the second digital information of the pixel data signal is directly input to the comparator 1212.

[0104] Alternatively, the first digital domain circuit 12 further includes a storage module 1202, the storage module 1202 being configured to store at least one of the second analog information and the second digital information of the pixel data signal, and the at least one of the second analog information and the second digital information of the pixel data signal being input from the storage module 1202 to the comparator 1212.

[0105] The second analog information can be a global signal (Global), which is directly input to the logic operation gate circuit 1213, thereby controlling the on or off state of the switching element, i.e., the second transistor 1102, in all first analog domain circuits 11 connected to the logic operation gate circuit 1213; or the second analog information can be a local signal (Local Level), which is input to the logic operation gate circuit 1213 from the storage module 1202, in which case only one or several second analog information can be input, thereby controlling the on or off state of the switching element, i.e., the corresponding second transistor 1102, in one or several first analog domain circuits 11. The analog modulation adjusts the on or off state of the corresponding second transistor 1102 in the M groups of current mirror branches according to the input second analog information, thereby realizing the selection of different current values and determining the size of the pixel driving circuit output current.

[0106] For example, as shown in FIG. 7, the second analog information of the pixel data signal is input to the logic operation gate circuit 1213 from the storage module 1202, and the second digital information of the pixel data signal is input to the comparator 1212 from the storage module 1202. Alternatively, the second analog information of the pixel data signal can be directly input to the logic operation gate circuit 1213, and the second digital information of the pixel data signal can be input to the comparator 1212 from the storage module 1202. Alternatively, the second analog information of the pixel data signal can be input to the logic operation gate circuit 1213 from the storage module 1202, and the second digital information of the pixel data signal can be directly input to the comparator 1212.

[0107] The second analog information and the second digital information of the pixel data signal can be stored in the storage module 1202 or not. The storage mode is relatively flexible. The storage module 1202 is a multi-bit storage module, which can be pre-configured with a certain correspondence relationship for controlling the digital and analog modulation signals to realize the analog and digital modulation. The correspondence relationship can be flexibly defined or matched as needed. The analog and digital signal modes can be allocated a certain number of bits to the digital end for PWM modulation, a certain number of bits to the analog end for analog modulation, or a direct analog and digital hybrid form. The input second analog information and second digital information can be stored or not, which can selectively store according to the needs, save certain resources, and flexibly realize multi-mode storage in various application scenarios.

[0108] In some embodiments, as shown in FIGS. 6 and 7, the second digital domain circuit 22 further includes a digital processing module 2202 for outputting the pixel data signal.

[0109] The digital processing module 2202 is mainly used to ensure the continuity of luminance in the analog modulation process. When there are both digital modulation and analog modulation in the same gray scale, the analog modulation will have luminance discontinuity due to the current mirror mismatch in the switching process. At this time, the digital processing module 2202 can be used for related digital compensation. The module has a digital IP module, which can determine the calculation and distribution of analog and digital signals. When the luminance discontinuity occurs in the analog modulation process, the compensation adjustment can be made through the number of digital bits or the dynamic adjustment can be realized by adjusting the gray scale length, so as to ensure the continuity of luminance in the analog modulation process.

[0110] In some embodiments, the first transistor 1101 and the third transistor 2101 are the same type of device, the second transistor 1102 and the fourth transistor 2102 are the same type of device, and the width-length ratio of at least two first transistors 1101 and the width-length ratio of the third transistor 2101 have a preset proportional relationship.

[0111] As shown in FIG. 6, the first transistor 1101 and the third transistor 2101 can be PMOS transistors, and the second transistor 1102 and the fourth transistor 2102 can be NMOS transistors.

[0112] In the driving mode based on the current mirror structure provided in the embodiments of the present application, the current mirror reference circuit 210 and the current mirror branch 110 form a current mirror structure. The smaller the device mismatch on both sides of the current mirror, the more accurate the current copying. Therefore, the same type of device is selected. According to the proportional relationship between the width-length ratio of the first transistor 1101 and the width-length ratio of the third transistor 2101, the current flowing through each current mirror branch 110 copies the reference current according to the corresponding proportional relationship. By controlling the on-off state and the conduction time of the second transistor 1102, the currents flowing through the current mirror branches 110 are superimposed according to the on-off effect, and finally the driving current signal of the pixel driving circuit 10 is output.

[0113] In the embodiments of the present application, the current mirror reference circuit 210 realizes the conversion from voltage to current, and provides the reference current I ref for the current mirror branch 110. As shown in FIG. 6, the width-length ratio of the third transistor 2101 is (W / L), and the width-length ratio of the first transistor 1101 in the i-th group of current mirror branches is K(i)*(W / L). Therefore, the current size of the i-th group of current mirror branches 110 is K(i)*I ref , where i is any integer value in 1-M. The on or off state of each second transistor 1102 is controlled by the first control signal. The M groups of current mirror branches and the M groups of second transistors are combined in the on or off state, and 2 M -1 kinds of current values (no current output when all are off) are generated. M -1 kind of current value is output as the driving signal of the pixel driving circuit 10, which can be used for the micro light emitting diode device to emit light and adjust the brightness.2 M -1 kind of current value combined with the gray scale modulation of the digital circuit pulse width modulation can make the adjustable brightness range of the micro light emitting diode more extensive, and can be applied to more application scenarios.

[0114] In some embodiments, the first analog domain circuit 11 further includes a first level converter module 1103 for converting the level range of the first control signal.

[0115] The first level converter module 1103 is configured to better realize the driving of the low-voltage domain signal of the digital domain circuit to the medium-voltage domain device of the analog domain circuit. For example, the turn-on voltage range of the general micro light emitting diode is between 2V-3V, combined with the conduction voltage drop of the transistor, the voltage range of the first analog domain circuit 11 is higher than 3V, and the voltage of the first digital domain circuit 12 is lower than that of the first analog domain circuit 11. At this time, the first level converter module 1103 can be configured to realize the driving of the first digital domain circuit 12 to the first analog domain circuit 11.

[0116] It should be understood that without the first level converter module 1103, the first control signal can still realize the conduction or turn-off of the related second transistor 1102 in the first analog domain circuit 11. When the first level converter module 1103 is set, the control effect is better.

[0117] Therefore, in different application scenarios, the resource demand can be combined, when the pixel driving circuit area is limited, it can also be set in the peripheral driving circuit, or when there is no level conversion demand, the module can also not be set.

[0118] In some embodiments, as shown in FIG. 9, FIG. 9 is a partial circuit architecture diagram of a peripheral driving circuit provided by an embodiment of the present application. The second digital domain circuit 22 further includes a digital decoder 2203 for outputting a voltage level adjustment signal. The second analog domain circuit 21 further includes a second level conversion circuit 2103, and the output end of the second level conversion circuit 2103 is electrically connected with the gate of the fourth transistor 2102, for outputting driving voltages of different levels according to the voltage level adjustment signal.

[0119] The driving voltage output by the second level conversion circuit 2103 has multiple levels, so that the reference current provided by the current mirror reference circuit has multiple levels, thereby making the pixel driving circuit have a larger adjustment range. As shown in FIG. 9, in this embodiment, the digital decoder 2203 converts the input digital signal into an analog signal output, and also can convert the low-voltage domain signal into a medium-voltage domain signal through a level conversion module, which is more conducive to the analog signal control of the on-off of the switch string.

[0120] Taking the switch string shown in FIG. 9 as an example, the original input voltage is divided by passing through 8 identical resistors in the resistor string, the on-off of the corresponding switches in the switch string is controlled by the analog signal, and the positive input end of the amplifier can have 8 different voltage inputs. After passing through the amplifier, 8 voltage output signals of the same length can be converted, and the corresponding reference current of 8 different sizes can be generated by adjusting the reference current circuit of the current mirror.

[0121] In some embodiments, the devices used in the first digital domain circuit 12 and the second digital domain circuit 22 are low-voltage domain devices, and the devices used in the first analog domain circuit 11 and the second analog domain circuit 21 are medium-voltage domain devices.

[0122] A large number of gate circuits in the first digital domain circuit 12 and the second digital domain circuit 22 use low-voltage domain devices, which can reduce the area occupied on the substrate. The first analog domain circuit 11 and the second analog domain circuit 21 use medium-voltage domain devices, which can better match the micro light-emitting diode elements and drive the micro light-emitting diode elements to emit light.

[0123] At the same time, the first analog domain circuit 11 and the first digital domain circuit 12 are separated by the structure of the devices themselves in the pixel driving circuit 10, and the second analog domain circuit 21 and the second digital domain circuit 22 are separated by the structure of the devices themselves in the peripheral driving circuit 20, so that the devices in different voltage domains maintain a certain distance, avoiding signal crosstalk, while reducing the area occupied by the pixel driving circuit 10 or the peripheral driving circuit 20 on the substrate, avoiding the waste of the area of the substrate, saving costs, and also improving the pixel density of the display device.

[0124] The application also provides a preparation method of a micro light-emitting diode driving substrate. Specifically, in the preparation process of the driving substrate, the first analog domain circuit 11 and the first digital domain circuit 12 are formed in each pixel region of the substrate M0, wherein the first analog domain circuit and the first digital domain circuit are vertically stacked, and there is an overlap in the spatial position, instead of being tiled on the substrate with a certain design rule and maintaining a certain gap, thereby saving the area occupied by the pixel driving circuit on the substrate. The first digital domain circuit is used to generate a first control signal, and the first control signal is used to control the on-off state and the conduction time of the switching elements in the first analog domain circuit. Compared with related technologies, the control is simple and the integration is high. The driving substrate finally obtained by the above preparation method separates the circuits in different voltage domains by using the device structure, reduces the signal crosstalk problem, reduces the area of the pixel region, and can improve the pixel density of the display device. FIG. 10 is a flowchart of a preparation method of a micro light-emitting diode driving substrate in an embodiment of the application. The preparation method includes the following steps S11-S12:

[0125] S11: providing a substrate, a plurality of pixel regions are arranged in a display area of the substrate;

[0126] S12: forming a first analog domain circuit 11 and a first digital domain circuit 12 in each pixel region of the substrate, wherein the first analog domain circuit 11 and the first digital domain circuit 12 are arranged in a vertical direction and overlap in space. The first digital domain circuit 12 is configured to generate a first control signal, and the first control signal is configured to control the on-off state and the conduction time of a switching element in the first analog domain circuit 11.

[0127] The driving substrate produced by the preparation method is arranged in a vertical direction, and the first analog domain circuit 11 and the first digital domain circuit 12 of the pixel driving circuit 10 are separated by the structure of the device itself. The devices in different voltage domains are kept at a certain distance, avoiding signal crosstalk, reducing the area occupied by the pixel driving circuit 10 on the substrate M0, thereby reducing the area of each pixel region, and improving the pixel density of the display device.

[0128] In some embodiments, the preparation method of the peripheral driving circuit 20 is similar to the above process, that is, a second analog domain circuit 21 and a second digital domain circuit 22 are formed in the peripheral region of the substrate M0, and the second analog domain circuit 21 and the second digital domain circuit 22 are arranged in a vertical direction and overlap in space.

[0129] Similarly, the second analog domain circuit 21 and the second digital domain circuit 22 of the peripheral driving circuit 20 are separated by the structure of the device itself, so that the devices in different voltage domains are kept at a certain distance, avoiding signal crosstalk, reducing the area occupied by the peripheral region on the substrate M0, reducing the area occupied by the peripheral driving circuit 20 on the substrate M0, saving cost, and expanding the usable area of the pixel region, which is beneficial to further improve the pixel density of the display device.

[0130] For example, as shown in FIG. 11, FIG. 11 is a device cross-sectional view of a driving substrate prepared by a preparation method provided by an embodiment of the present application.

[0131] For the case that the first digital domain circuit 12 is arranged above the first analog domain circuit 11 and the second analog domain circuit 21 is arranged above the second digital domain circuit 22 as shown in FIG. 11, in step S12, the specific preparation method further includes steps S121-S123:

[0132] S121: forming a first digital domain circuit 12 on the substrate, the first digital domain circuit 12 including a control signal generation module 1201;

[0133] S122: a first passivation layer L1 is formed on the first digital domain circuit 12, and a first via V1 is formed on the first passivation layer L1, the first via V1 exposes a control signal output end C1 of the first digital domain circuit 12;

[0134] S123: a first analog domain circuit 11 is formed on the first passivation layer L1, the first analog domain circuit 11 includes at least two groups of current mirror branches 110, each group of current mirror branches 110 includes a first transistor 1101 and a second transistor 1102, the drain of the first transistor 1101 is electrically connected with the source of the second transistor 1102, the gates of the first transistors 1101 in the at least two groups of current mirror branches 110 are electrically connected with each other, the drains of the second transistors 1102 in the at least two groups of current mirror branches 110 are connected with each other and serve as a driving signal output end C2 of the pixel driving circuit 10, and the control signal output end C1 of the control signal generation module 1201 is electrically connected with the gates of the second transistors 1102 in each group of current mirror branches 110.

[0135] The second digital domain circuit 22 of the peripheral driving circuit 20 and the first digital domain circuit 12 of the pixel driving circuit 10 can be prepared by using an N-well CMOS process, and after the CMOS process is completed, the output end of the digital circuit and the gates of the related transistors of the analog domain circuit to be controlled are connected through the first via V1.

[0136] In step S123 of the embodiment of the present application, the specific preparation method further includes steps S1231-S1233:

[0137] S1231: the gates of the first transistor 1101 and the second transistor 1102 are formed on the first passivation layer L1, and the gate of the second transistor 1102 is electrically connected with the control signal output end C1 of the first digital domain circuit 12 through the first via V1;

[0138] S1232: the first active layer L2 of the first transistor 1101 and the second active layer L3 of the second transistor 1102 are formed on the gates;

[0139] S1233: the source and the drain of the first transistor 1101 are formed above the first active layer L2, and the source and the drain of the second transistor 1102 are formed above the second active layer L3, and each first transistor 1101 in the at least two groups of current mirror branches 110 has a preset width-length ratio.

[0140] As shown in Fig. 11, the above preparation method aims to generate digital domain circuit by front-end process (FOEL process), because the first digital domain circuit 12 and the second digital domain circuit 22 both adopt low-voltage domain devices, the first digital domain circuit 12 and the second digital domain circuit 22 can share a DNW, and the design rules between different voltage domain devices, i.e. the distance gap limitation on the plane, do not need to be considered. After the gate metal is deposited by PVD technology and the gate is formed by processes such as coating, photoetching, developing, dry etching and stripping, the gate insulating layer is deposited, and the front-end process is completed. In the embodiment of the application, the devices of the analog domain circuit adopt a bottom gate structure.

[0141] Then, the analog domain circuit is generated by back-end process (BOEL process), because the first active layer L2 is used to form the first transistor 1101, and the second active layer L3 is used to form the second transistor 1102, so the two active layers need to be distinguished according to the functions of the transistors. In the process, the second active layer L3 can be deposited first, and then covered by a passivation layer, and then the first active layer L2 is formed, and then covered by a passivation layer, and it is noted that the projection areas of the first active layer L2 and the second active layer L3 on the substrate do not overlap, and then a via hole is formed on the first active layer L2 and the second active layer L3 respectively by processes such as coating, photoetching, developing, dry etching and stripping. In this process, the covalent bond of the active layer medium is broken, and the ions of the etching gas are implanted, so that the source and drain of the medium are conductive, and then the source and drain electrode layer is deposited to form the required transistor, and finally the inorganic layer is deposited to prevent oxidation.

[0142] In the embodiment of the application, the current mirror reference circuit 210 in the second analog domain circuit 21 and the current mirror branch 110 in the first analog domain circuit 11 form a current mirror structure. The smaller the device mismatch on both sides of the current mirror, the more accurate the current copying, so the same type of device needs to be selected on both sides. According to the proportional relationship between the width-length ratio of the first transistor 1101 and the width-length ratio of the third transistor 2101, the current flowing through each current mirror branch 110 copies the reference current according to the corresponding proportional relationship. By controlling the open-circuit state and conduction time of the second transistor 1102, the current flowing through each current mirror branch 110 is superimposed according to the open-circuit effect of the second transistor 1102, and finally the driving current signal of the pixel driving circuit 10 is output. Since the analog domain circuit and the digital domain circuit coincide in the vertical direction, they do not occupy additional substrate area, and the preparation method can produce a driving substrate with smaller pixel area.

[0143] In the embodiment of the application, the first transistor 1101 formed by the first active layer L2 can be a MoS2 device, and the second transistor 1102 formed by the second active layer L3 can be an IGZO device. In addition, the active layer is not limited to IGZO, MoS2, but can also be an active material such as TMD.

[0144] Taking the first active layer L2 as MoS2 and the second active layer L3 as IGZO as an example, in step S1232, the PVD process can be used to first form the IGZO active layer, then deposit a passivation layer to cover the active layer, then form the MoS2 active layer, and deposit a passivation layer, and then in the process of etching the passivation layer, the covalent bonds in IGZO and MoS2 are broken, and ions of the etching gas are injected, so that the source and drain electrodes of IGZO and MoS2 are conductorized.

[0145] In a specific embodiment, by sequentially forming the first digital domain circuit 12 and the first analog domain circuit 11 in the vertical direction of the pixel region, and sequentially forming the second digital domain circuit 22 and the second analog domain circuit 21 in the vertical direction of the peripheral region, the area of a single pixel region can be reduced from 4.5*4.5um to 3.14*3.14um, and the pixel density of the display device can be increased from 5644 to 8089, without changing the basic circuit architecture. At the same time, due to the physical separation of the digital circuit and the analog circuit, the crosstalk problem between signals is reduced, and the display effect is improved.

[0146] In a third aspect, the application also provides a micro light emitting diode display device. FIG. 12 is a structural schematic diagram of a micro light emitting diode display device according to an embodiment of the application. As shown in FIG. 12, the device includes the micro light emitting diode driving substrate B1 according to any of the embodiments of the first aspect, and a light emitting diode Q1 located in each pixel region A1. The light emitting diode Q1 is electrically connected to the driving signal output end of the first analog domain circuit of the pixel driving circuit of the micro light emitting diode driving substrate B1, and controls the luminance and color step of the light emitting diode Q1. Specifically, as shown in FIG. 12, the micro light emitting diode driving substrate B1 is divided into a plurality of pixel regions A1, and one micro light emitting diode Q1 is arranged in each pixel region A1. The micro light emitting diode driving substrate B1 has the technical features and effects described in the above embodiments, which will not be repeated here.

[0147] The above merely describes specific embodiments of the application, but the protection scope of the application is not limited thereto. Any person skilled in the art can make changes or replacements within the technical scope disclosed in the application, which should be covered by the protection scope of the application. Therefore, the protection scope of the application should be subject to the protection scope of the claims.

Claims

1. A micro light emitting diode driving substrate, wherein, The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method.

2. The drive substrate according to claim 1, wherein The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method.

3. The drive substrate according to claim 2, wherein The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method.

4. The drive substrate according to claim 3, wherein The application relates to a display substrate and a display substrate driving method.

5. The drive substrate according to claim 4, wherein The application relates to a display substrate and a display substrate driving method.

6. The drive substrate according to claim 5, wherein The application relates to a display substrate and a display substrate driving method.

7. The drive substrate according to claim 6, wherein The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method.

8. The drive substrate according to claim 7, wherein The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method.

9. The drive substrate according to claim 8, wherein The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to a display substrate and a display substrate driving method. The application relates to 10. The drive substrate according to claim 9, wherein, When the level of the digital pulse width modulation information is the first level and the level of the second analog information is the first level, the output end of the logic operation gate circuit outputs the first control signal to control the switch element in the first analog domain circuit to be turned on, otherwise, the switch element in the first analog domain circuit is controlled to be turned off. Or, when the level of the digital pulse width modulation information is the first level and the level of the second analog information is the first level, the output end of the logic operation gate circuit outputs the first control signal to control the switch element in the first analog domain circuit to be turned off, otherwise, the switch element in the first analog domain circuit is controlled to be turned on.

11. The drive substrate according to claim 8, wherein The second analog information of the pixel data signal is directly input to the logic operation gate circuit, and the second digital information of the pixel data signal is directly input to the comparator. Or, the first digital domain circuit further comprises a storage module, the storage module is used for storing at least one of the second analog information and the second digital information of the pixel data signal, and the at least one of the second analog information and the second digital information of the pixel data signal is input to the logic operation gate circuit from the storage module.

12. The drive substrate according to claim 7, wherein, The second digital domain circuit further comprises a digital processing module, which is used for outputting the pixel data signal.

13. The drive substrate according to claim 4, wherein, The first analog domain circuit comprises at least two groups of current mirror branches, each group of current mirror branches comprises a first transistor and a second transistor, the drain electrode of the first transistor is electrically connected with the source electrode of the second transistor, the gate electrodes of the first transistors in the at least two groups of current mirror branches are electrically connected with each other, the drain electrodes of the second transistors in the at least two groups of current mirror branches are connected with each other and serve as a driving signal output end of the pixel driving circuit, and are used for outputting a current signal. The control signal output end of the control signal generation module is electrically connected with the gate electrodes of the second transistors in the at least two groups of current mirror branches, and is used for controlling the on-off state and the on duration of the second transistors in the at least two groups of current mirror branches. The second analog domain circuit comprises a group of current mirror reference circuits, the current mirror reference circuit comprises a third transistor and a fourth transistor, the drain electrode of the third transistor is electrically connected with the source electrode of the fourth transistor, and the drain electrode and the gate electrode of the third transistor are electrically connected with the gate electrodes of the first transistors, so as to provide reference current for the at least two groups of current mirror branches in the first analog domain circuit.

14. The drive substrate according to claim 13, wherein, The first transistor and the third transistor are the same type of devices, and the second transistor and the fourth transistor are the same type of devices. The width-length ratio of the at least two first transistors has a preset proportional relationship with the width-length ratio of the third transistor.

15. The drive substrate according to claim 13, wherein, The first analog domain circuit further comprises a first level converter module, which is used for converting the level range of the first control signal.

16. The drive substrate of claim 13, wherein, The second digital domain circuit further comprises a digital decoder, which is used for outputting a voltage level adjustment signal. The second analog domain circuit further comprises a second level conversion circuit, the output end of the second level conversion circuit is electrically connected with the gate electrode of the fourth transistor, and is used for outputting driving voltages of different levels according to the voltage level adjustment signal.

17. A method of fabricating a micro-LED driving substrate, comprising: Comprise: A substrate substrate is provided with a plurality of pixel regions in a display area of the substrate substrate; A first analog domain circuit and a first digital domain circuit are formed in each pixel region of the substrate substrate, the first analog domain circuit and the first digital domain circuit are vertically stacked and have spatial position overlap, the first digital domain circuit is used to generate a first control signal used to control the on-off state and conduction time of a switching element in the first analog domain circuit.

18. The method of making according to claim 17, wherein, Further comprising: A second analog domain circuit and a second digital domain circuit are formed in a peripheral region of the substrate substrate, the second analog domain circuit and the second digital domain circuit are vertically stacked and have spatial position overlap, and the second digital domain circuit and the second analog domain circuit constitute a peripheral driving circuit.

19. The method of manufacturing according to claim 17 or 18, wherein, A first digital domain circuit and a first analog domain circuit are formed in each pixel region of the substrate substrate, including: A first digital domain circuit is formed on the substrate substrate, and the first digital domain circuit includes a control signal generation module; A first passivation layer is formed on the first digital domain circuit, and a first via is formed through the first passivation layer, which exposes a control signal output end of the first digital domain circuit; The first analog domain circuit is formed on the first passivation layer, and the first analog domain circuit includes at least two groups of current mirror branches, each group of current mirror branches includes a first transistor and a second transistor, the drain of the first transistor is electrically connected with the source of the second transistor, the gates of the first transistors in the at least two groups of current mirror branches are electrically connected with each other, the drains of the second transistors in the at least two groups of current mirror branches are connected with each other and serve as a driving signal output end of the pixel driving circuit, and the control signal output end of the control signal generation module is electrically connected with the gates of the second transistors in the at least two groups of current mirror branches.

20. The method of making according to claim 19, wherein, The first analog domain circuit is formed on the first passivation layer, including: The gates of the first transistor and the second transistor are formed on the first passivation layer, and the gate of the second transistor is electrically connected with the control signal output end of the first digital domain circuit through the first via; A first active layer of the first transistor and a second active layer of the second transistor are formed on the gate; The source and drain of the first transistor are formed above the first active layer, and the source and drain of the second transistor are formed above the second active layer, and each first transistor in the at least two groups of current mirror branches has a preset width-length ratio.

21. A micro-LED display device, wherein, Including: The micro light emitting diode driving substrate according to any one of claims 1-16, and a light emitting diode in each pixel region, the light emitting diode is electrically connected with the driving signal output end of the first analog domain circuit of the pixel driving circuit in the micro light emitting diode driving substrate.

Images