Display panel and display device

Abstract

Provided in the present application are a display panel and a display device. The display panel comprising: a first substrate; data lines, which are arranged on the first substrate; metal oxide semiconductor layers, which are arranged on the surface of the data lines away from the first substrate, the metal oxide semiconductor layers being electrically connected to the data lines through first via holes; and drain electrodes, which are arranged on the surface of the metal oxide semiconductor layers away from the first substrate, the drain electrodes being electrically connected to the metal oxide semiconductor layers through second via holes. The metal oxide semiconductor layers are parallel to the data lines and at least partially overlap the data lines. The display panel provided in the present application can improve pixels per inch.

Description

Display panel and display device Technical Field

[0001] This application relates to the field of display technology, specifically to a display panel and display device. Background Technology

[0002] Virtual reality (VR) products have extremely high requirements for display panel resolution. In order to eliminate the screen-door effect and provide a more immersive visual experience, the pixel density (PPI, pixels per inch) of the display panel of virtual reality products needs to reach 1000 or more.

[0003] To meet the aforementioned high pixel density requirements, existing liquid crystal display panels use indium gallium zinc oxide (IGZO) to fabricate thin-film transistors (TFTs). IGZO TFTs have higher electron mobility, which can significantly reduce the size of TFTs, thereby increasing pixel density.

[0004] However, current indium gallium zinc oxide thin-film transistors typically have a planar structure, requiring the indium gallium zinc oxide layer to be laid at an angle, which is not conducive to further increasing pixel density and therefore cannot meet the requirements of virtual reality products for display panels with higher resolution.

[0005] Therefore, a new technical solution is urgently needed to further improve pixel density. Invention Overview

[0006] Embodiments of this application provide a display panel and display device aimed at further improving pixel density.

[0007] An embodiment of this application provides a display panel, the display panel including a display area, the display panel including: a first substrate; multiple data lines located within the display area, the film layer containing the data lines being disposed on the first substrate; multiple metal oxide semiconductor layers disposed on a surface of the data lines away from the first substrate and located within the display area, the metal oxide semiconductor layers being electrically connected to the data lines through a first via; and multiple drains disposed on a surface of the metal oxide semiconductor layers away from the first substrate and located within the display area, the drains being electrically connected to the metal oxide semiconductor layers through a second via; wherein, the metal oxide semiconductor layers are disposed parallel to the data lines, and in a top view of the display panel, the metal oxide semiconductor layers and the data lines at least partially overlap.

[0008] Embodiments of this application also provide a display device, the display device including a display panel, a timing controller, and a source driving circuit. The display panel includes a display area and a non-display area, and the display panel further includes a gate driving circuit disposed in the non-display area. The timing controller is electrically connected to the source driving circuit and the gate driving circuit. The display panel includes: a first substrate; multiple data lines located within the display area, the film layer containing the data lines being disposed on the first substrate; multiple metal oxide semiconductor layers disposed on a surface of the data lines away from the first substrate and located within the display area, the metal oxide semiconductor layers being electrically connected to the data lines through a first via; and multiple drains disposed on a surface of the metal oxide semiconductor layers away from the first substrate and located within the display area, the drains being electrically connected to the metal oxide semiconductor layers through a second via; wherein the metal oxide semiconductor layers are disposed parallel to the data lines, and in a top view of the display panel, the metal oxide semiconductor layers and the data lines at least partially overlap. Beneficial effects

[0009] The thin-film transistors (TFTs) in the display area of ​​the display panel proposed in this application have a vertical structure. In this TFT, the source and drain are arranged in layers, located below and above the metal-oxide-semiconductor (MOS) layer, respectively. The data line is located on the lower layer of the MOS layer and electrically connected through a first via. The drain is located on the upper layer of the MOS layer and electrically connected through a second via. The MOS layer is parallel to the data line and directly above it, with their projected portions overlapping. Compared to traditional planar TFT structures where a portion of the MOS layer is tilted (offset) relative to the data line, resulting in increased line spacing, the MOS layer of the TFT in this application's display panel does not have tilted traces. This significantly increases pixel density and reduces the TFT's footprint, freeing up more space for further pixel density increases. Since the entire MOS layer is parallel to and directly above the data line, with at least partial overlap, the length of the MOS layer can be shortened, reducing its resistance and thus power consumption. Since the source and drain metal layers of the thin-film transistors in the peripheral area of ​​the display panel share the same metal layer as the data lines and gate lines in the display area of ​​the display panel, the number of photomasks in the manufacturing process is reduced, thereby reducing production costs. Attached Figure Description

[0010] Figure 1 is a schematic diagram of a display device provided in an embodiment of this application.

[0011] Figure 2 is a cross-sectional view of a first embodiment of the display panel provided in the present application.

[0012] Figure 3 is a cross-sectional view of a second embodiment of the display panel provided in the embodiments of this application.

[0013] Figure 4 is a top view of the display panel shown in Figures 2 and 3. Embodiments of the present invention

[0014] To make the embodiments of this application clearer, the technical solutions in the embodiments of this application will be described below with reference to the accompanying drawings.

[0015] The terms “first,” “second,” and similar words do not indicate any order, quantity, or importance, but are merely used to distinguish different technical features. The terms “multiple,” and similar words mean two or more, unless otherwise expressly specified.

[0016] The term "parallel" includes absolute parallelism and approximate parallelism. Absolute parallelism refers to the case where the angle between the lines corresponding to A and B is equal to 0 degrees, while approximate parallelism refers to the case where the angle between the lines corresponding to A and B is greater than 0 degrees and less than or equal to 3 degrees.

[0017] Traditional virtual reality (VR) products use planar thin-film transistors (TFTs) in their display panels. The metal-oxide-semiconductor (MOS) layer in these planar TFTs is divided into three parts: the first part is parallel to the data lines and largely overlaps with them; the second part bends (skews) into the opening area and forms an angle with the data lines; and the third part is parallel to the data lines but does not overlap. Because traditional VR display panels typically have high pixel density—meaning each pixel occupies a small area—the spacing at the skewed traces must be designed to be even smaller. However, this significantly increases the risk of short circuits, preventing further increases in pixel density.

[0018] Therefore, embodiments of this application provide a display device and display panel that can overcome the aforementioned technical problem that pixel density cannot be further increased.

[0019] The display devices provided in the embodiments of this application include LCD display devices, OLED display devices, etc., as shown in FIG1. ​​The display device includes a display panel, a timing controller TCON, a source driving circuit DD, and a power management chip (not shown in the figure). The power management chip can be integrated with the timing controller TCON into the same chip. The display panel includes multiple pixels P, multiple scan lines (GL1~GLn), multiple data lines (DL1~DLm), a gate driving circuit GOA, etc. The multiple pixels P are arranged in rows and columns. The gate driving circuit GOA is electrically connected to the multiple scan lines (GL1~GLn). The source driving circuit DD is electrically connected to the multiple data lines (DL1~DLm). The scan lines (GL1~GLn) and data lines (DL1~DLm) are electrically connected to the pixels P. The timing controller TCON is electrically connected to the gate driving circuit GOA and the source driving circuit DD.

[0020] When the display panel is an LCD display panel, the display panel includes a thin-film transistor array substrate, an opposing substrate, and liquid crystal material disposed between the thin-film transistor array substrate and the opposing substrate. The thin-film transistor array substrate includes a substrate, a gate driving circuit GOA, a pixel P, scan lines (GL1~GLn), data lines (DL1~DLm), color resist, etc. The pixel P includes a thin-film transistor, a pixel electrode, etc. The thin-film transistor is electrically connected to the pixel electrode, the scan lines (GL1~GLn), and the data lines (DL1~DLm).

[0021] When the display panel is an OLED display panel, the display panel includes a substrate, a pixel P, a gate driving circuit GOA, an organic light-emitting device, an encapsulation layer, a polarizer, a color filter, etc. The substrate may be, for example, a glass substrate, a flexible substrate (e.g., a polyimide substrate), etc. The pixel P includes an organic light-emitting device (OLED) and a driving circuit. The driving circuit includes multiple thin-film transistors. The organic light-emitting device is electrically connected to the driving circuit. The organic light-emitting device includes an emissive layer, an electron transport layer, a hole transport layer, a cathode, and an anode, etc. The encapsulation layer includes a multilayer structure of alternating organic and inorganic materials.

[0022] The gate drive circuit GOA includes cascaded multi-stage gate drive units, each of which is electrically connected to a row of pixels P. The gate drive units are used to provide scan signals to pixels P.

[0023] The source drive circuit DD is used to provide data signals to pixel P.

[0024] The timing controller TCON is used to receive externally input image data and control the gate drive circuit GOA to output scan signals, as well as control the source drive circuit DD to output data signals.

[0025] Power management chips are used to provide the necessary operating voltages to various parts of a display device.

[0026] As shown in Figures 2, 3, and 4, embodiments of this application provide a COA (Color-filter On Array) type LCD display panel, that is, the color filters R and G in the display panel provided by the embodiments of this application are fabricated on a thin-film transistor array substrate. The display panel includes a thin-film transistor array substrate, a counter substrate, liquid crystal material disposed between the thin-film transistor array substrate and the counter substrate, and a polarizer.

[0027] The thin-film transistor array substrate includes a first substrate S1 made of a transparent material such as glass or plastic, and thin-film transistors, data lines SE, gate lines (GE1, GE2, GE3), pixel electrodes, color filters (R, G), etc. disposed on the first substrate S1.

[0028] The opposing substrate includes a second substrate S2 made of a transparent material such as glass or plastic, and a common electrode is disposed on the second substrate S2.

[0029] A polarizer is disposed on the outer side of the thin-film transistor array substrate and the opposing substrate to adjust the polarization state of light.

[0030] The display panel provided in the embodiments of this application may further include a backlight module disposed on the side of the thin-film transistor array substrate facing away from the opposing substrate.

[0031] The display panel provided in the embodiments of this application includes multiple pixel units, each pixel unit typically comprising three sub-pixels: red, green, and blue. Each sub-pixel consists of a thin-film transistor and a pixel electrode. A color filter is applied over the corresponding color sub-pixel to filter out light of other colors.

[0032] To achieve high pixel density (PPI), the size of pixel units needs to be reduced, which requires thin-film transistors (TFTs) to occupy a smaller area. Therefore, embodiments of this application provide a display panel including a display area AA. The portion of the display panel located in the display area AA includes multiple metal-oxide-semiconductor (IGZO) thin-film transistors. These IGZO TFTs have a vertical structure, thus reducing the area occupied by the thin-film transistors. The display panel provided by embodiments of this application is suitable for VR products with extremely high PPI.

[0033] Specifically, the portion of the display panel located in the display area AA includes multiple data lines SE, multiple metal-oxide-semiconductor layers OS, and multiple drain electrodes DE. The data lines SE are located within the display area AA, and the film layer containing the data lines SE is disposed on the first substrate S1. The material of the metal-oxide-semiconductor layer OS can be indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), etc. The material of the drain electrodes DE is a transparent conductive material, such as indium tin oxide (ITO).

[0034] A metal-oxide-semiconductor layer OS is disposed on a surface of the data line SE away from the first substrate S1 and located within the display area AA. The metal-oxide-semiconductor layer OS is electrically connected to the data line SE through a first via H1. The metal-oxide-semiconductor layer OS is arranged parallel to the data line SE, and in a top view of the display panel, as shown in Figure 4, the metal-oxide-semiconductor layer OS and the data line SE at least partially overlap. This technical solution can maximize the use of a limited area, thereby improving the aperture ratio.

[0035] The drain DE is positioned above the metal oxide semiconductor layer OS, and the drain DE is electrically connected to the metal oxide semiconductor layer OS through the second via H2.

[0036] The metal-oxide-semiconductor layer OS includes a first part and a second part. The first part is electrically connected to the data line SE, and the second part is electrically connected to the drain DE. The first part and the second part are located at different heights in a direction perpendicular to the plane of the display panel, thereby forming a vertical thin-film transistor.

[0037] In the display area AA, the metal-oxide-semiconductor layer OS has a vertical structure. Specifically, the source (SE) and drain (DE) of the metal-oxide-semiconductor thin-film transistor are respectively disposed on the upper and lower layers of the metal-oxide-semiconductor layer OS. In the embodiments of this application, the source, i.e., the data line SE, is disposed on the lower layer of the metal-oxide-semiconductor layer OS and is electrically connected to the metal-oxide-semiconductor layer OS through a first via H1. The drain (DE) is disposed on the upper layer of the metal-oxide-semiconductor layer OS and is electrically connected to the metal-oxide-semiconductor layer OS through a second via H2.

[0038] This vertical thin-film transistor (TFT) structure allows the metal-oxide-semiconductor (MOS) layer (OS) to be completely parallel to and overlap with the data line (SE). Compared to planar TFTs, the vertical structure avoids bypass branches (diagonal areas) in the MOS layer, thus reducing the risk of short circuits in the display panel with high PPI and improving reliability. Furthermore, the vertical structure completely shields the MOS layer below the data line (SE), significantly increasing the aperture ratio.

[0039] To achieve the aforementioned vertical structure, the two parts (the first part and the second part) of the metal-oxide-semiconductor layer OS are connected by a ramp. The first part is connected to the data line SE, and from the data line SE, it ramps over the first gate insulating layer GI2 to connect with the second part. In other words, the metal-oxide-semiconductor layer OS has a vertical structure with a ramp crossing in the vertical direction, and is no longer on the same plane. The second part is electrically connected to the drain DE.

[0040] This vertical structure (layered ramp design) allows the metal-oxide-semiconductor (OS) layer to be arranged in straight lines in a planar layout, eliminating the need for diagonal arrangements and avoiding bypass branches (diagonal areas in a planar structure). This makes it suitable for designs with extremely high pixel densities, allowing for further reduction in linewidth and spacing to achieve ultra-high resolutions such as 2000+ PPI. Simultaneously, the height difference between the first and second parts in the vertical direction reduces the occupied area of ​​the OS layer (increasing the effective display area), further improving the aperture ratio and reducing power consumption. Furthermore, the parallel arrangement of the OS layer and the data lines (SE) increases their overlap area, further enhancing the aperture ratio.

[0041] The first portion of the metal-oxide-semiconductor layer OS is located at a lower height and is electrically connected to the data line SE through a first via H1. The second portion is located at a higher height and is electrically connected to the drain DE through a second via H2. The first and second portions are connected by a step-up structure (a transition structure in the direction perpendicular to the plane of the display panel), that is, the first and second portions of the metal-oxide-semiconductor layer OS are stepped in the vertical direction.

[0042] As an improvement, a metal oxide semiconductor layer (OS) has a metal oxide thin film with different band structures on its upper and lower surfaces. This multilayer structure can improve the carrier mobility of the OS, thereby improving the switching characteristics and driving capability of the thin-film transistor. Simultaneously, it can also improve device stability and reduce performance degradation during long-term operation.

[0043] Furthermore, in the top view of the display panel, as shown in Figure 4, the width of the metal oxide semiconductor layer OS is greater than the width of the data line SE, and the width of the drain DE is greater than the width of the data line SE, but less than or equal to the width of the metal oxide semiconductor layer OS.

[0044] The display panel also includes a first gate line GE2, an interlayer insulating layer IL, a first gate insulating layer GI2, a second gate line GE3, and a second gate insulating layer GI3.

[0045] The first gate line GE2 is disposed below the second part of the metal-oxide-semiconductor layer OS and is used to control the conductivity state of the second part.

[0046] An interlayer insulating layer IL is disposed between the first gate line GE2 and the data line SE to isolate the first gate line GE2 from the data line SE.

[0047] The first gate insulating layer GI2 is disposed between the first gate line GE2 and the second part of the metal oxide semiconductor layer OS, and is used to insulate the first gate line GE2 and the metal oxide semiconductor layer OS.

[0048] The second gate line GE3 is disposed above the second part of the metal-oxide-semiconductor layer OS, and together with the first gate line GE2, controls the conductivity state of the second part.

[0049] The second gate insulating layer GI3 is disposed between the second gate line GE3 and the metal oxide semiconductor layer OS, and is used to insulate the second gate line GE3 and the metal oxide semiconductor layer OS.

[0050] The film layer containing the first gate line GE2 is located above the film layer containing the data line SE.

[0051] In the top view of the display panel, as shown in Figure 4, the length direction of the metal oxide semiconductor layer OS is consistent with the length direction of the data line SE, and the metal oxide semiconductor layer OS spans the first gate line GE2 and the second gate line GE3.

[0052] The metal-oxide-semiconductor layer OS includes an active region located at the intersection of the first gate line GE2, the second gate line GE3, and the data line SE. Electric fields are applied to the first gate line GE2 and the second gate line GE3 at their corresponding positions within the active region to control the conductivity state of the metal-oxide-semiconductor layer OS, thereby achieving pixel switching control.

[0053] In the top view of the display panel, as shown in Figure 4, the first gate line GE2 and the second gate line GE3 are both located between the first via H1 and the second via H2. Therefore, the second part of the metal oxide semiconductor layer OS is completely within the control range of the first gate line GE2 and the second gate line GE3, thereby optimizing the switching characteristics of the pixel.

[0054] The first gate line GE2 and the second gate line GE3 are arranged in parallel. The first gate line GE2 intersects with the data line SE. In the top view of the display panel, as shown in Figure 4, the portion of the first gate line GE2 overlapping with the metal-oxide-semiconductor layer OS and the data line SE is at least partially overlapped, and the portion of the second gate line GE3 overlapping with the metal-oxide-semiconductor layer OS and the data line SE is also at least partially overlapped. The first gate line GE2 and the second gate line GE3 are electrically connected in the peripheral region PA of the display panel.

[0055] The first gate line GE2 and the second gate line GE3 can have different driving voltages or the same driving voltage.

[0056] The first gate line GE2 and the second gate line GE3 can be driven synchronously or asynchronously.

[0057] The first via H1 penetrates the interlayer insulating layer IL and the first gate insulating layer GI2, and the second via H2 penetrates the second gate insulating layer GI3.

[0058] Specifically, in the manufacturing process, an interlayer insulating layer IL and a first gate insulating layer GI2 are deposited on the data line SE. Before forming the metal-oxide-semiconductor layer OS, a first via H1 is formed in the interlayer insulating layer IL and the first gate insulating layer GI2 so that the first portion of the subsequently formed metal-oxide-semiconductor layer OS is electrically connected to the data line SE. Then, a second gate insulating layer GI3 is formed above the metal-oxide-semiconductor layer OS, and a second via H2 is formed in the second gate insulating layer GI3 so that the second portion of the metal-oxide-semiconductor layer OS is electrically connected to the drain DE.

[0059] The first via H1 and the second via H2 can have different shapes and sizes. For example, the first via H1 has a larger size than the second via H2 to increase the contact area between the metal oxide semiconductor layer OS and the data line SE, and the second via H2 has a smaller size than the first via H1.

[0060] In the top view of the display panel, the line connecting the first via H1 and the second via H2, located at both ends of the same metal oxide layer OS, is parallel to the data line SE.

[0061] To ensure good insulation of the inner wall of the first via H1 and prevent leakage or short circuit between the metal oxide semiconductor layer OS and the data line SE, one improvement is to fabricate an insulating layer, such as an oxide insulating layer, on the inner wall of the first via H1. Another improvement is to passivate the first via H1 to eliminate sharp corners, that is, to form obtuse angles or rounded corners on adjacent sides of the bottom edge or opening edge of the first via H1.

[0062] The display panel also includes a peripheral area PA. The portion of the display panel located in the peripheral area PA includes a gate driving circuit. The gate driving circuit includes a low-temperature polycrystalline silicon thin-film transistor. The first source-drain metal layer SD1 of the low-temperature polycrystalline silicon thin-film transistor and the data line SE are disposed on the same layer. The film layer where the first source-drain metal layer SD1 is located is located on the film layer where the third gate GE1 of the low-temperature polycrystalline silicon thin-film transistor is located.

[0063] The aforementioned metal-oxide-slim thin-film transistor is disposed in the display area AA, while a low-temperature polysilicon thin-film transistor is disposed in the peripheral area PA to drive the first gate line GE2 and the second gate line GE3 of the display area AA. The first source-drain metal layer SD1 of the low-temperature polysilicon thin-film transistor and the data line SE are disposed on the same layer, so that they can be formed together in the same process step, simplifying the manufacturing process.

[0064] The low-temperature polycrystalline silicon thin-film transistor also includes a second source-drain metal layer SD2, which is located on top of the first source-drain metal layer SD1. The second source-drain metal layer SD2 is electrically connected to the first source-drain metal layer SD1. The second source-drain metal layer SD2 and the first gate line GE2 are disposed on the same layer, as shown in Figure 3, or the second source-drain metal layer SD2 and the second gate line GE3 are disposed on the same layer, as shown in Figure 4.

[0065] If the second source-drain metal layer SD2 and the first gate line GE2 are disposed on the same layer, then the second source-drain metal layer SD2 can be formed together with the first gate line GE2 metal layer in the same process step. If the second source-drain metal layer SD2 and the second gate line GE3 are disposed on the same layer, then the second source-drain metal layer SD2 can be formed together with the second gate line GE3 metal layer in the same process step.

[0066] The display panel also includes a third via, which penetrates the interlayer insulating layer IL, the first gate insulating layer GI2, and the second gate insulating layer GI3. The second source-drain metal layer SD2 is electrically connected to the first source-drain metal layer SD1 through the third via.

[0067] Specifically, in the manufacturing process, a data line SE, an interlayer insulating layer IL, a first gate line GE2, a first gate insulating layer GI2, a metal-oxide-semiconductor layer OS, and a second gate insulating layer GI3 are first sequentially formed on the substrate. Then, a third via is formed in the interlayer insulating layer IL, the first gate insulating layer GI2, and the second gate insulating layer GI3, so that the third via penetrates the interlayer insulating layer IL, the first gate insulating layer GI2, and the second gate insulating layer GI3. Next, a second source-drain metal layer SD2 is formed above the second gate insulating layer GI3, and the second source-drain metal layer SD2 is electrically connected to the first source-drain metal layer SD1 through the third via.

[0068] The third via can be a special shape such as a cone or a step to ensure the electrical connection quality between the second source-drain metal layer SD2 and the first source-drain metal layer SD1.

[0069] The third via has a different diameter at different depths, which ensures good step coverage and electrical connection.

[0070] There is a certain height difference between the second source-drain metal layer SD2 and the first source-drain metal layer SD1, so the two are electrically connected through a third via.

[0071] The thin-film transistors (TFTs) located in the display area AA of the display panel proposed in this application have a vertical structure. In this TFT, the source and drain electrodes DE are arranged in layers and are located below and above the metal-oxide-semiconductor (MOS) layer OS, respectively. That is, the data line SE is located on the lower layer of the MOS layer OS, and the two are electrically connected through a first via H1. The drain electrode DE is located on the upper layer of the MOS layer OS, and the two are electrically connected through a second via H2. The MOS layer OS is parallel to the data line SE and is located directly above the data line SE, with their projected portions overlapping. Compared with the conventional planar structure of TFTs, where a portion of the MOS layer OS needs to be tilted (offset) relative to the data line SE, resulting in increased line spacing, the MOS layer OS of the TFTs in the display panel of this application does not have tilted traces, which can significantly improve pixel density and reduce the occupied area of ​​the TFT, freeing up more space for increasing pixel density. Since the MOS layer OS is entirely parallel to the data line SE and located directly above the data line SE, and the two overlap at least partially, the length of the MOS layer OS can be shortened, its resistance reduced, and power consumption reduced. Since the source and drain metal layers of the thin-film transistors in the peripheral area PA of the display panel share the same metal layer as the data lines SE and gate lines in the display area AA of the display panel, the number of photomasks in the manufacturing process is reduced, thereby reducing production costs.

[0072] This application provides a vertical LTPO design scheme. In this design, the portion of the display panel located in the display area AA employs a vertically structured metal-oxide-semiconductor thin-film transistor (MTPT). The data line SE is positioned below the MTPT layer OS, and the two are electrically connected through a first via H1. The drain DE is positioned above the MTPT layer OS, and the two are electrically connected through a second via H2. The entire MTPT layer OS is parallel to the data line SE and positioned directly above the data line SE, with their orthographic projections overlapping. In this design, the MTPT layer OS does not need to bend (tilt the trace) into the aperture area, the occupied area of ​​the thin-film transistor can be further reduced, the size of the pixel unit can be further reduced, thereby achieving a higher pixel density and significantly improving the aperture ratio.

[0073] In addition, the peripheral area PA of the display panel uses low-temperature polycrystalline silicon thin-film transistors. Its source and drain metal layers share the same metal layer as the data lines SE and gate lines of the display area AA, which reduces the number of photomasks, lowers production costs, and improves yield.

[0074] This solution proposes two implementation methods:

[0075] Example 1:

[0076] The metal-oxide-semiconductor (MOS) thin-film transistors (TFTs) in the display area AA of the display panel adopt a vertical architecture. The data line SE is located below the MOS layer OS, and the drain DE is located above the MOS layer OS. The MOS layer OS is divided into two parts: the first part is connected to the data line SE, and the second part is connected to the drain DE. The two parts are located at different heights in the vertical direction. This architecture allows the MOS layer OS to have only straight lines, which is suitable for ultra-high pixel density designs, such as 2000+ pixel density designs. The first source-drain metal layer SD1 of the low-temperature polysilicon (LTPS) in the peripheral area PA of the display panel is located on the same layer as the data line SE in the display area AA. The second source-drain metal layer SD2 is located on the same layer as the second gate line GE3 of the MOSPS, sharing the same metal layer, saving the number of photomasks, reducing production costs, and improving yield.

[0077] Example 2:

[0078] Based on Embodiment 1, the second source-drain metal layer SD2 of the low-temperature polysilicon thin-film transistor in the peripheral region PA of the display panel is disposed on the same layer as the first gate line GE2 of the metal oxide thin-film transistor. This design reduces the height difference between the second source-drain metal layer SD2 and the first source-drain metal layer SD1, separated only by an interlayer insulating layer IL. The height difference is reduced from 0.6~1μm to 0.2~0.5μm, significantly reducing the process difficulty and further improving the yield.

[0079] This solution proposes a novel LTPO COA architecture for display panels with extremely high pixel density. This solution can significantly increase pixel density (e.g., to over 2000 pixels), increase aperture ratio, reduce power consumption, and improve color shift. Furthermore, in this solution, the source and drain metal layers of the low-temperature polysilicon thin-film transistors in the peripheral area PA of the display panel share the same metal layer as the data lines SE and gate lines in the display area AA, which can reduce the number of photomasks, lower costs, and improve yield.

[0080] The embodiments of this application have been described in detail above. The content of this specification should not be construed as limiting the scope of protection of this application.

Claims

1. A display panel, wherein, The display panel includes a display area, and the display panel includes: First substrate; Multiple data lines are located within the display area, and the film layer containing the data lines is disposed on the first substrate. Multiple metal-oxide-semiconductor layers are disposed on a surface of the data line away from the first substrate and located within the display area; the metal-oxide-semiconductor layers are electrically connected to the data line through a first via; and Multiple drains are disposed on a surface of the metal oxide semiconductor layer away from the first substrate and located within the display area. The drains are electrically connected to the metal oxide semiconductor layer through a second via. The metal oxide semiconductor layer is arranged parallel to the data line, and in the top view of the display panel, the metal oxide semiconductor layer and the data line at least partially overlap.

2. The display panel according to claim 1, wherein, The metal oxide semiconductor layer includes a first part and a second part. The first part is electrically connected to the data line, and the second part is electrically connected to the drain. The first part and the second part are located at different heights in a direction perpendicular to the plane of the display panel.

3. The display panel according to claim 2, wherein, The display panel also includes: A first gate line is disposed below the second portion of the metal oxide semiconductor layer; An interlayer insulating layer is disposed between the first gate line and the data line; A first gate insulating layer is disposed between the first gate line and the second portion of the metal oxide semiconductor layer; A second gate line is disposed above the second portion of the metal-oxide-semiconductor layer; and A second gate insulating layer is disposed between the second gate line and the metal oxide semiconductor layer.

4. The display panel according to claim 3, wherein, The first gate line is arranged parallel to the second gate line, and the first gate line is arranged intersecting the data line. In the top view of the display panel, the portion of the first gate line overlapping the metal oxide semiconductor layer and the data line at least partially overlaps, and the portion of the second gate line overlapping the metal oxide semiconductor layer and the data line at least partially overlaps.

5. The display panel according to claim 3, wherein, The film layer containing the first gate line is located above the film layer containing the data line.

6. The display panel according to claim 3, wherein, In a top view of the display panel, both the first gate line and the second gate line are located between the first via and the second via.

7. The display panel according to claim 3, wherein, The first via penetrates the interlayer insulating layer and the first gate insulating layer, and the second via penetrates the second gate insulating layer.

8. The display panel according to claim 3, wherein, The display panel further includes a peripheral area, and the portion of the display panel located in the peripheral area includes: A gate driving circuit, the gate driving circuit including a low-temperature polycrystalline silicon thin-film transistor, wherein the first source-drain metal layer of the low-temperature polycrystalline silicon thin-film transistor is disposed on the same layer as the data line.

9. The display panel according to claim 8, wherein, The low-temperature polycrystalline silicon thin-film transistor further includes a second source-drain metal layer, which is electrically connected to the first source-drain metal layer. The second source-drain metal layer is disposed on the same layer as the first gate line, or the second source-drain metal layer is disposed on the same layer as the second gate line.

10. The display panel according to claim 9, wherein, The display panel further includes a third via, which penetrates the interlayer insulating layer, the first gate insulating layer and the second gate insulating layer, and the second source-drain metal layer is electrically connected to the first source-drain metal layer through the third via.

11. The display panel according to claim 1, wherein, In the top view of the display panel, the width of the metal oxide semiconductor layer is greater than the width of the data line, and the width of the drain is greater than the width of the data line, but less than or equal to the width of the metal oxide semiconductor layer.

12. The display panel according to claim 1, wherein, In the top view of the display panel, the line connecting the first via and the second via, located at both ends of the same metal oxide layer, is parallel to the data line.

13. A display device, wherein, The display device includes a display panel, a timing controller, and a source driving circuit. The display panel includes a display area and a non-display area. The display panel also includes a gate driving circuit disposed in the non-display area. The timing controller is electrically connected to the source driving circuit and the gate driving circuit. The display panel includes: First substrate; Multiple data lines are located within the display area, and the film layer containing the data lines is disposed on the first substrate. Multiple metal-oxide-semiconductor layers are disposed on a surface of the data line away from the first substrate and located within the display area; the metal-oxide-semiconductor layers are electrically connected to the data line through a first via; and Multiple drains are disposed on a surface of the metal oxide semiconductor layer away from the first substrate and located within the display area. The drains are electrically connected to the metal oxide semiconductor layer through a second via. The metal oxide semiconductor layer is arranged parallel to the data line, and in the top view of the display panel, the metal oxide semiconductor layer and the data line at least partially overlap.

14. The display device according to claim 13, wherein, The metal oxide semiconductor layer includes a first part and a second part. The first part is electrically connected to the data line, and the second part is electrically connected to the drain. The first part and the second part are located at different heights in a direction perpendicular to the plane of the display panel.

15. The display device according to claim 14, wherein, The display panel also includes: A first gate line is disposed below the second portion of the metal oxide semiconductor layer; An interlayer insulating layer is disposed between the first gate line and the data line; A first gate insulating layer is disposed between the first gate line and the second portion of the metal oxide semiconductor layer; A second gate line is disposed above the second portion of the metal-oxide-semiconductor layer; and A second gate insulating layer is disposed between the second gate line and the metal oxide semiconductor layer.

16. The display device according to claim 15, wherein, The first gate line is arranged parallel to the second gate line, and the first gate line is arranged intersecting the data line. In the top view of the display panel, the portion of the first gate line overlapping the metal oxide semiconductor layer and the data line at least partially overlaps, and the portion of the second gate line overlapping the metal oxide semiconductor layer and the data line at least partially overlaps.

17. The display device according to claim 15, wherein, The film layer containing the first gate line is located above the film layer containing the data line.

18. The display device according to claim 15, wherein, In a top view of the display panel, both the first gate line and the second gate line are located between the first via and the second via.

19. The display device according to claim 15, wherein, The first via penetrates the interlayer insulating layer and the first gate insulating layer, and the second via penetrates the second gate insulating layer.

20. The display device according to claim 15, wherein, The display panel further includes a peripheral area, and the portion of the display panel located in the peripheral area includes: A gate driving circuit, the gate driving circuit including a low-temperature polycrystalline silicon thin film transistor, wherein the first source-drain metal layer of the low-temperature polycrystalline silicon thin film transistor is disposed on the same layer as the data line, the second source-drain metal layer of the low-temperature polycrystalline silicon thin film transistor is electrically connected to the first source-drain metal layer, and the second source-drain metal layer is disposed on the same layer as the first gate line or the second gate line.

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