Pixel structure, display chip, display device and preparation method of display chip

Abstract

The invention relates to a pixel structure, a display chip, a display device and a preparation method of the display chip. The pixel structure comprises a first substrate, a pixel unit, a first conductive structure and a plurality of second conductive structures. The pixel unit comprises a plurality of light-emitting units which are sequentially stacked on the first substrate, and each light-emitting unit comprises a first semiconductor layer and a second semiconductor layer. The first conductive structure at least penetrates from the first substrate to the first semiconductor layer of the light-emitting unit farthest from the first substrate, and is electrically connected with the first semiconductor layer of each light-emitting unit. The number of the second conductive structures is the same as that of the light-emitting units, the second conductive structures and the light-emitting units are arranged in a one-to-one correspondence mode, and each second conductive structure at least penetrates to the second semiconductor layer of the corresponding light-emitting unit from the first substrate and is electrically connected with the corresponding second semiconductor layer. The pixel density can be effectively improved.

Description

Pixel structure, display chip, display device, and method for fabricating display chip Technical Field

[0001] This application relates to the field of Micro-LED display technology, and in particular to a pixel structure, a display chip, a display device, and a method for fabricating the display chip. Background Technology

[0002] Display devices are an indispensable part of our daily consumer electronics. Mainstream commercial display chips include TFT, OLED, and MiniLED, while emerging display chips include QLED and Micro-LED. As a new type of self-emissive display technology, Micro-LED chips are known for their high luminous efficiency, low energy consumption, and wide color gamut, making them a current investment hotspot in the capital market.

[0003] Currently, Micro-LED employs laser lift-off and laser mass transfer technologies to directly peel off the red, green, and blue epitaxial layers and chips from the substrate and transfer them to the driver circuit substrate for packaging. This allows for chip size reduction to below 100μm, and individual pixels to be as small as 200-300μm. However, due to the highly precise and expensive equipment used in laser lift-off and laser mass transfer, the extremely high yield requirements (≥99.999%) for Micro-LED chip laser mass transfer in full-color large-screen displays, and the difficulty in repairing and salvaging screen defects, the adoption rate of home appliances equipped with Micro-LED display devices remains low.

[0004] Patent application CN118281125A discloses a vertically stacked full-color Micro-LED device based on through-hole electrodes and its fabrication method. This patent draws inspiration from design concepts in multi-segment GaAs-based solar cells and multi-segment VCSEL high-power laser chips. Specifically, it uses highly doped thin-layer quantum tunneling junctions to connect sequentially connected PIN junctions in the epitaxial layer (e.g., PIN-PIN-PIN, where current flows forward from the P-type layer through the quantum well to the N-type layer; however, when passing between two sequentially connected PIN junctions, there is a reverse-connected NP junction that blocks the current flow). This allows the reverse-flowing current to tunnel directly through the quantum effect without overcoming the potential barrier.

[0005] The use of quantum tunneling junctions to connect red, green, and blue multi-segment epitaxial layers is more suitable for growing all epitaxial structures on a substrate wafer in a single operation using MOCVD equipment. In fact, GaAs-based multi-segment solar cells and GaAs-based multi-segment VCSEL high-power laser chips are grown using this approach. However, as is well known, GaN-based LED chips used for lighting and displays are generally grown on wafers made of non-GaN materials, such as silicon or sapphire wafers. Both silicon and sapphire wafers have a significant lattice mismatch (13%–17%) with GaN materials. Even for monochromatic LED epitaxial layer structures, a low-temperature GaN or AlN layer thicker than 2µm is needed as a buffer layer, or a strained superlattice structure to reduce the stress effect on the light-emitting layer. Growing the epitaxial layers of red, green, and blue LEDs sequentially on a non-GaN substrate in a single operation poses a significant challenge to the MOCVD material growth process.

[0006] Meanwhile, the solution for implementing a full-color MicroLED microdisplay chip in this patent application places the P-type electrode and the N-type electrode on the front and back of the chip, respectively. This means that when connecting to the driver chip, one side uses micro-bumps for connection, while the other side requires gold wire bonding, resulting in a less compact structure. Summary of the Invention

[0007] Based on this, this application provides a pixel structure, a display chip, a display device, and a method for fabricating a display chip that can improve pixel density.

[0008] A pixel structure, comprising:

[0009] First substrate;

[0010] A pixel unit includes a plurality of light-emitting units stacked sequentially on a first substrate, each of the light-emitting units including a first semiconductor layer and a second semiconductor layer;

[0011] A first conductive structure extends from the first substrate to at least the first semiconductor layer of the light-emitting unit furthest from the first substrate, and is electrically connected to the first semiconductor layer of each light-emitting unit;

[0012] Multiple second conductive structures are provided, the number of which is the same as the number of light-emitting units, and they are arranged in a one-to-one correspondence. Each second conductive structure extends from the first substrate to at least the second semiconductor layer of the corresponding light-emitting unit and is electrically connected to the corresponding second semiconductor layer.

[0013] In one embodiment, the pixel unit further includes a plurality of connection units, each connection unit being configured in a one-to-one correspondence with the light-emitting unit, and each connection unit comprising:

[0014] The first connection structure includes a first connection electrode and a first connection trace. Within the same light-emitting unit, the first connection electrode is connected to the first semiconductor layer, and the first connection trace connects the first connection electrode to the first conductive structure.

[0015] The second connection structure is insulated from the first connection structure and includes a second connection electrode and a second connection trace. Within the same light-emitting unit, the second connection electrode is connected to the second semiconductor layer, and the second connection trace connects the second connection electrode to the corresponding second conductive structure.

[0016] In one embodiment, the first connecting electrode and / or the second connecting electrode are ring-shaped structures.

[0017] In one embodiment, the pixel structure further includes a first insulating layer disposed between adjacent light-emitting units;

[0018] The first connection trace and the second connection trace are located within the first insulating layer;

[0019] The first connecting electrode extends from inside the first insulating layer toward the corresponding light-emitting unit through the first insulating layer and connects to the corresponding first semiconductor layer;

[0020] The second connection electrode passes through the first insulating layer from within the first insulating layer toward the corresponding light-emitting unit and is connected to the corresponding second semiconductor layer.

[0021] In one embodiment, the pixel structure further includes:

[0022] A second insulating layer is disposed on the side of the first substrate away from the light-emitting unit, and the first conductive structure and the plurality of second conductive structures penetrate the second insulating layer and are exposed from the second insulating layer.

[0023] In one embodiment, the plurality of light-emitting units include a first light-emitting unit, a second light-emitting unit, and a third light-emitting unit that are stacked sequentially on a first substrate.

[0024] In one embodiment, the pixel structure further includes:

[0025] The second substrate is located between the second light-emitting unit and the third light-emitting unit.

[0026] In one embodiment, the pixel structure further includes:

[0027] A third substrate is located on the side of the third light-emitting unit that is away from the first substrate.

[0028] In one embodiment, the pixel structure further includes:

[0029] The microlens structure is located on the side of the third substrate away from the third light-emitting unit.

[0030] A display chip includes the aforementioned plurality of pixel structures.

[0031] In one embodiment, the display chip further includes:

[0032] A shallow trench isolation structure is located between each pixel unit.

[0033] A display device, comprising:

[0034] The aforementioned display chip;

[0035] The driver chip is located on one side of the display chip and is electrically connected to the display chip through the first conductive structure and the plurality of second conductive structures.

[0036] In one embodiment, the display device further includes:

[0037] The adapter board is located on the side of the driver chip away from the display chip and is electrically connected to the driver chip.

[0038] In the aforementioned pixel structure, display chip, and display device, the pixel structure includes a first substrate and pixel units. Each pixel unit comprises multiple light-emitting units stacked sequentially on the first substrate, thereby facilitating an increase in pixel area or pixel density. The pixel structure also includes one first conductive structure and multiple second conductive structures. The number of second conductive structures is the same as the number of light-emitting units, and they are arranged in a one-to-one correspondence. In this case, electrical connections to the N-type and P-type semiconductor layers of each light-emitting unit can be achieved using fewer conductive structures, further enabling a more compact pixel structure. Simultaneously, during the packaging of the pixel structure, the bottom of both the first and second conductive structures can be vertically connected to the driver chip, further improving the compactness of the pixel structure.

[0039] A method for fabricating a display chip, comprising:

[0040] A plurality of different light-emitting wafers are provided, each light-emitting wafer comprising a substrate and an epitaxial layer grown on the substrate;

[0041] Light-emitting units are defined in the epitaxial layer of each of the light-emitting wafers;

[0042] In each of the light-emitting units of each of the light-emitting wafers, a first via and a predetermined number of second vias are formed, and both the first via and the second via penetrate at least the epitaxial layer;

[0043] Conductive material is filled into the first and second through holes of each of the light-emitting wafers;

[0044] Each light-emitting wafer is stacked and bonded in sequence, and the conductive materials in the corresponding first through-hole and the conductive materials in the second through-hole are vertically interconnected to form the first conductive structure and the second conductive structure, respectively.

[0045] The set number of the second through holes is determined by the number m of the stacked light-emitting wafers. In the vertical direction from bottom to top, the set number of the second through holes in each of the stacked light-emitting wafers decreases sequentially from m to 1, where m≥2.

[0046] In one embodiment, defining the light-emitting unit in the epitaxial layer of each of the light-emitting wafers includes:

[0047] At least the epitaxial layer of each of the light-emitting wafers is etched to form shallow trenches, which isolate the epitaxial layer into a plurality of light-emitting units;

[0048] An insulating material is filled into the shallow trenches of each of the light-emitting wafers to form a shallow trench isolation structure.

[0049] In one embodiment, before sequentially stacking and bonding the light-emitting wafers, the method further includes:

[0050] A first insulating layer is formed on the side of the epitaxial layer of each light-emitting wafer away from the substrate, and a first connection structure and a second connection structure are formed in the first insulating layer. The first connection structure connects the conductive material in the first via and the first semiconductor layer, and the second connection structure connects the conductive material in the second via and the second semiconductor layer.

[0051] In one embodiment, the first connection structure includes a first connection electrode and a first connection trace, the first connection electrode being connected to the first semiconductor layer, and the first connection trace being connected to the first connection electrode and a conductive material in the first via; the second connection structure includes a second connection electrode and a second connection trace, the second connection electrode being connected to the second semiconductor layer, and the second connection trace being connected to the second connection electrode and a conductive material in the corresponding second via.

[0052] The method for forming the first connection structure and / or the second connection structure includes:

[0053] An electrode window is formed, wherein the electrode window of the first connection structure extends to the first semiconductor layer, and the electrode window of the second connection structure extends to the second semiconductor layer.

[0054] The electrode window is filled with conductive material to form the connecting electrode;

[0055] The connection trace connecting the connection electrode is formed.

[0056] In one embodiment, filling the electrode window with conductive material to form a connecting electrode includes:

[0057] An ohmic contact material is formed at the bottom of the electrode window;

[0058] Electrode material is formed in the remaining space of the electrode window.

[0059] In one embodiment, the first connecting electrode and / or the second connecting electrode are ring-shaped structures.

[0060] In one embodiment, after sequentially stacking and bonding the light-emitting wafers, the method further includes:

[0061] The substrate of the bottom light-emitting wafer is thinned so that the first conductive structure and the second conductive structure are exposed and protrude relative to the substrate of the bottom light-emitting wafer.

[0062] A second insulating layer is formed on the substrate surface, the first conductive structure surface, and the second conductive structure surface of the thinned bottom light-emitting wafer;

[0063] The second insulating layer is etched to expose the first conductive structure and the second conductive structure.

[0064] The aforementioned display chip fabrication method involves individually forming multiple different light-emitting wafers, and then forming a first via and a second via within each light-emitting unit of each light-emitting wafer. The number of second vias formed within different light-emitting wafers varies. The light-emitting wafers are then sequentially stacked via bonding, with the conductive materials within the first vias of different light-emitting wafers vertically interconnected, and the conductive materials within the relatively opposite second vias of different light-emitting wafers vertically interconnected. This allows for the formation of one first conductive structure and m second conductive structures for each pixel unit, where m is the number of stacked light-emitting wafers. At this point, the via interconnection method simultaneously enables vertical stacking of the light-emitting wafers and upward signal transmission. The stacking of light-emitting units within the same pixel effectively reduces pixel area or increases pixel density. Furthermore, the m+1 conductive structures (one first conductive structure and m second conductive structures) provide electrical connections to the N-type and P-type semiconductor layers of each light-emitting unit, further enabling a more compact pixel structure. Meanwhile, during subsequent packaging, the bottom of each of the m+1 conductive structures can be vertically connected to the driver chip, thereby further improving the compactness of the pixel structure. Attached Figure Description

[0065] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0066] Figure 1 is a flowchart of a method for fabricating a display chip provided in one embodiment;

[0067] Figure 2 is a cross-sectional schematic diagram of several different light-emitting wafers provided in one embodiment;

[0068] Figure 3 is a top view schematic diagram of the light-emitting unit defined in the epitaxial layer of each light-emitting wafer in one embodiment;

[0069] Figure 4a is a top view of a first light-emitting wafer after a first connecting electrode has been formed on it, according to one embodiment.

[0070] Figures 4b to 4g are cross-sectional schematic diagrams of the structure formed in different steps during the processing of the first light-emitting wafer before the individual light-emitting wafers are stacked and bonded in sequence in one embodiment; the cross-sectional directions in Figures 4b to 4g correspond to the corresponding cross-sectional directions in Figure 4a.

[0071] Figure 5a is a top view of a second light-emitting wafer after a first connecting electrode has been formed on it, according to one embodiment.

[0072] Figures 5b to 5g are cross-sectional schematic diagrams of the structure formed in different steps during the processing of the second light-emitting wafer before the individual light-emitting wafers are stacked and bonded in sequence in one embodiment; the cross-sectional directions in Figures 5b to 5g correspond to the corresponding cross-sectional directions in Figure 5a;

[0073] Figure 6a is a top view of a third light-emitting wafer after a first connecting electrode has been formed on it, according to one embodiment.

[0074] Figures 6b to 6g are cross-sectional schematic diagrams of the structure formed in different steps during the processing of the third light-emitting wafer before the individual light-emitting wafers are stacked and bonded in sequence in one embodiment; the cross-sectional directions in Figures 6b to 6g correspond to the corresponding cross-sectional directions in Figure 6a.

[0075] Figure 7 is a cross-sectional schematic diagram of a pixel structure formed by sequentially stacking and bonding the light-emitting wafers in one embodiment;

[0076] Figures (a), (b), (c), and (d) in Figure 8 show the distribution design of the light-emitting units in different embodiments;

[0077] Figure 9 is a cross-sectional schematic diagram of a display device provided in one embodiment;

[0078] Figure 10 is a cross-sectional schematic diagram of a pixel structure provided in one embodiment;

[0079] Figure 11 is a cross-sectional schematic diagram of a display chip provided in one embodiment.

[0080] Explanation of reference numerals in the attached figures:

[0081] 110 - First substrate, 120 - Second substrate, 130 - Third substrate, 200 - Epitaxial layer, 200a - Light-emitting unit, a1 - First light-emitting unit, a2 - Second light-emitting unit, a3 - Third light-emitting unit, 210 - First semiconductor layer, 220 - Multiple quantum well layer, 221 - Quantum well, 222 - Quantum barrier, 230 - Second semiconductor layer, 240 - Stress buffer layer, 250 - Electron blocking layer, 310 - First conductive structure, 320 - Second conductive structure, 400 - Shallow trench isolation structure, 510-first connection structure, 511-first connection electrode, 512-first connection trace, 520-second connection structure, 521-second connection electrode, 522-second connection trace, 600-first insulating layer, 610-first sub-insulating layer, 620-second sub-insulating layer, 630-third sub-insulating layer, 700-second insulating layer, 1-display chip, 2-driver chip, 3-adapter board, 4-molding layer, H1-first through hole, H2-second through hole. Detailed Implementation

[0082] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0083] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0084] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion.

[0085] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0086] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0087] In one embodiment, referring to Figure 1, a method for fabricating a display chip is provided, including the following steps:

[0088] Step S100, please refer to Figure 2, provide multiple different light-emitting wafers, each light-emitting wafer including a substrate and an epitaxial layer 200 grown on the substrate;

[0089] Step S200, please refer to Figure 3, define the light-emitting unit 200a in the epitaxial layer 200 of each light-emitting wafer;

[0090] In step S300, please refer to Figures 4b, 5b and 6b. In each light-emitting unit 200a of each light-emitting wafer, a first via H1 and a set number of second vias H2 are formed. The first via H1 and the second via H2 both penetrate the epitaxial layer 200 at least.

[0091] Step S400, please continue to refer to Figures 4b, 5b and 6b, fill the first through hole H1 and the second through hole H2 of each light-emitting wafer with conductive material;

[0092] In step S500, please refer to Figure 7, the light-emitting wafers are stacked and bonded in sequence, and the conductive materials in the corresponding first through-hole H1 and the conductive materials in the second through-hole H2 are vertically interconnected to form the first conductive structure 310 and the second conductive structure 320 respectively.

[0093] The number of second vias H2 is determined by the number m of stacked light-emitting wafers. In the vertical direction from bottom to top, the number of second vias H2 in each stacked layer of light-emitting wafers decreases from m to 1, where m≥2.

[0094] In step S100, referring to Figure 2, each light-emitting wafer may include a substrate and an epitaxial layer 200 grown on the substrate. The epitaxial layer 200 on different light-emitting wafers is used to emit light of different colors.

[0095] The epitaxial layer 200 may include a first semiconductor layer 210, a multiple quantum well layer 220, and a second semiconductor layer 230. One of the first semiconductor layer 210 and the second semiconductor layer 230 is a P-type semiconductor layer, and the other is an N-type semiconductor layer. In addition, the epitaxial layer 200 may also include a stress buffer layer 240, a superlattice layer, an electron blocking layer 250, etc.

[0096] The epitaxial layer 200 structures of different light-emitting wafers can be the same, but are not limited to being the same. That is, the epitaxial layer 200 structures of different light-emitting wafers can also be different. For example, the epitaxial layer 200 of each light-emitting wafer can all include a first semiconductor layer 210, a multi-quantum well layer 220, and a second semiconductor layer 230 sequentially stacked in a direction away from the substrate. Alternatively, the epitaxial layer 200 of each light-emitting wafer can include a second semiconductor layer 230, a multi-quantum well layer 220, and a first semiconductor layer 210 sequentially stacked in a direction away from the substrate. Furthermore, the epitaxial layer 200 of some light-emitting wafers can all include a first semiconductor layer 210, a multi-quantum well layer 220, and a second semiconductor layer 230 sequentially stacked in a direction away from the substrate, while the epitaxial layer 200 of other light-emitting wafers can include a second semiconductor layer 230, a multi-quantum well layer 220, and a first semiconductor layer 210 sequentially stacked in a direction away from the substrate.

[0097] For example, a plurality of different light-emitting wafers include a first light-emitting wafer, a second light-emitting wafer, and a third light-emitting wafer.

[0098] Please refer to Figure 2(a). The substrate of the first light-emitting wafer is the first substrate 110, and the epitaxial layer 200 of the first light-emitting wafer is the first epitaxial layer 200. The first epitaxial layer 200 may include a stress buffer layer 240, a first semiconductor layer 210, a multiple quantum well layer 220, an electron blocking layer 250, and a second semiconductor layer 230 sequentially formed on the first substrate 110.

[0099] Please refer to Figures (b) and (c) in Figure 2. The substrate of the second light-emitting wafer can be the second substrate 120, and the epitaxial layer 200 of the second light-emitting wafer is the second epitaxial layer 200. The substrate of the third light-emitting wafer can be the third substrate 130, and the epitaxial layer 200 of the third light-emitting wafer is the third epitaxial layer 200.

[0100] The growth order of the first semiconductor layer 210 and the second semiconductor layer 230 in both the second epitaxial layer 200 and the third epitaxial layer 200 can be, for example, the reverse of the growth order of the first semiconductor layer 210 and the second semiconductor layer 230 in the first epitaxial layer 200.

[0101] Specifically, referring to Figure 2(b), the second epitaxial layer 200 may include a stress buffer layer 240, a second semiconductor layer 230, an electron blocking layer 250, a multiple quantum well layer 220, and a first semiconductor layer 210 sequentially formed on the second substrate 120. Referring to Figure 2(c), the third epitaxial layer 200 may include a stress buffer layer 240, a second semiconductor layer 230, an electron blocking layer 250, a multiple quantum well layer 220, and a first semiconductor layer 210 sequentially formed on the third substrate 130.

[0102] At this time, after the light-emitting wafers are stacked and bonded in sequence in step S500, the alignment of the first semiconductor layer 210, the multiple quantum well layer 220 and the second semiconductor layer 230 can be kept consistent in the vertical direction.

[0103] Furthermore, exemplarily, the first light-emitting wafer can be a red light-emitting wafer, the second light-emitting wafer can be a green light-emitting wafer, and the third light-emitting wafer can be a blue light-emitting wafer.

[0104] For example, the first substrate 110 may be a silicon substrate. The second substrate 120 and the third substrate 130 may both be sapphire substrates.

[0105] For example, the first epitaxial layer 200, the second epitaxial layer 200, and the third epitaxial layer 200 can all be gallium nitride-based epitaxial layers 200. The first semiconductor layer 210 can include an N-type GaN layer. The second semiconductor layer 230 can include a P-type GaN layer. Furthermore, the second semiconductor layer 230 may also include a heavily doped P-type GaN capping layer located on the side of the P-type GaN layer away from the multi-quantum-well layer 220. The stress buffer layer 240 can be made of gallium nitride (GaN) or aluminum nitride (AlN), etc. The electron blocking layer 250 can be made of aluminum gallium nitride (AlGaN).

[0106] Meanwhile, the multi-quantum-well layer 220 may include alternating stacked quantum barriers 222 and quantum wells 221.

[0107] Furthermore, in the first epitaxial layer 200, the material of the quantum barrier 222 may include aluminum indium gallium nitride (AlInGaN), and the material of the quantum well 221 may include indium gallium nitride (InGaN). In the quantum well (InGaN layer), the proportion of In can be between 35% and 45%. The thickness of the quantum well can be between 2 nm and 3 nm. In the quantum barrier 222 (AlInGaN layer), the proportion of Al can be approximately 5% to 15% (e.g., 10%), and the proportion of In can be approximately 3%. The thickness of the quantum barrier 222 can be approximately 8 nm to 12 nm (e.g., 10 nm).

[0108] In the second and third epitaxial layers 200, the quantum barrier 222 may be made of gallium nitride (GaN), and the quantum well may be made of indium gallium nitride (InGaN). The emission wavelength can be determined by the proportion of In in the quantum well (InGaN layer) and the thickness of the quantum well in the multi-quantum-well layer 220. For example, in the second epitaxial layer 200, the proportion of In in the quantum well (InGaN layer) is between 25% and 35%, and the thickness of the quantum well is between 3 nm and 4 nm. In the third epitaxial layer 200, the proportion of In in the quantum well (InGaN layer) is between 15% and 20%, and the thickness of the quantum well is between 2 nm and 3 nm.

[0109] In the above example, the epitaxial layer 200 of each light-emitting wafer is made of a wide-bandgap GaN-based compound semiconductor material. In this case, the material systems of the epitaxial layers 200 of each light-emitting wafer are matched, making subsequent vertical bonding integration easier. Of course, the arrangement of each light-emitting wafer can also be different. For example, the first epitaxial layer 200 of the first light-emitting wafer (red light-emitting wafer) can also be made of a narrow-bandgap gallium arsenide (GaAs)-based material. The multi-quantum well layer 220 of the first epitaxial layer 200 can also include alternating stacks of indium gallium arsenide phosphide (InGaAsP) and gallium arsenide (GaAs).

[0110] In step S200, referring to Figure 3, multiple light-emitting units 200a can be defined in the epitaxial layer 200 of each light-emitting wafer. The light-emitting units 200a of each light-emitting wafer can be arranged relative to each other and can have the same arrangement.

[0111] For example, the light-emitting units 200a of each light-emitting wafer can be arranged in a four-corner arrangement or a hexagonal arrangement, etc.

[0112] For example, the light-emitting units 200a of each light-emitting wafer can have the same shape, such as square, circular, polygonal, etc.

[0113] In step S300, referring to Figures 4b, 5b and 6b, each light-emitting wafer can be etched to form a first through-hole H1 and a set number of second through-holes H2 in each light-emitting unit 200a of each light-emitting wafer.

[0114] For example, when etching each light-emitting wafer, the epitaxial layer 200 can be etched through, and a portion of the substrate can also be etched, so that both the first via H1 and the second via H2 penetrate the epitaxial layer 200 and extend into the substrate. The depth to which the first via H1 and the second via H2 can penetrate into the substrate can be set according to actual needs, for example, it can be set to 5μm to 15μm (e.g., 10μm).

[0115] Of course, when etching individual or partial light-emitting wafers, etching of the substrate can be stopped after penetrating the epitaxial layer 200. In this case, the first via H1 and the second via H2 penetrate the epitaxial layer 200 but do not extend into the substrate. The specific settings can be configured according to actual requirements.

[0116] Meanwhile, the “set number” of the second via H2 can be determined by the number m of the subsequently stacked light-emitting wafers. In the vertical direction from bottom to top, the set number of the second via H2 in each of the sequentially stacked light-emitting wafers decreases from m to 1, where m≥2.

[0117] For example, the light-emitting wafers subsequently stacked sequentially include a first light-emitting wafer, a second light-emitting wafer, and a third light-emitting wafer. The first light-emitting wafer, the second light-emitting wafer, and the third light-emitting wafer are stacked sequentially from bottom to top in the vertical direction.

[0118] At this point, the value of m is 3. In each light-emitting unit 200a of the first light-emitting wafer, the preset number of second vias H2 is 3. In each light-emitting unit 200a of the second light-emitting wafer, the preset number of second vias H2 is 2. In each light-emitting unit 200a of the third light-emitting wafer, the preset number of second vias H2 is 1.

[0119] In step S400, for each light-emitting wafer, an insulating layer can first be formed on the sidewalls and bottom of the first via H1 and the second via H2. Then, a conductive material is formed on the surface of the insulating layer to fill the first via H1 and the second via H2.

[0120] Conductive materials can include metallic materials, such as copper.

[0121] In step S500, as shown in Figure 7, the light-emitting wafers can be stacked and bonded sequentially from bottom to top in the vertical direction.

[0122] Specifically, when sequentially bonding a light-emitting wafer to the underlying light-emitting wafer, the first light-emitting wafer can be flipped, and then the side of the light-emitting wafer furthest from the substrate can be bonded and stacked with the underlying light-emitting wafer. Afterwards, the substrate of the light-emitting wafer can be thinned or removed to facilitate the bonding of subsequent light-emitting wafers. After the last light-emitting wafer is bonded, it can be thinned, retaining a portion of the substrate as a protective layer for the display chip.

[0123] For example, the first light-emitting wafer, the second light-emitting wafer, and the third light-emitting wafer can be stacked and bonded sequentially from bottom to top in the vertical direction.

[0124] For example, the first light-emitting wafer can be placed face up first. Then, the second light-emitting wafer is flipped, thereby bonding the sides of the two light-emitting wafers away from the substrate. Next, the second substrate 120 of the bonded second light-emitting wafer is thinned to expose the first via H1 and the second via H2 extending into the second substrate 120, thereby exposing the conductive material within the first via H1 and the conductive material within the second via H2. Then, the third light-emitting wafer is flipped, thereby bonding the side of the third light-emitting wafer away from the substrate to the thinned second light-emitting wafer. Afterwards, the third substrate 130 of the bonded third light-emitting wafer can be thinned, while still covering the first via H1 and the second via H2 of the third light-emitting wafer, thereby providing passivation protection for the display chip.

[0125] Furthermore, after thinning the third substrate 130, a microlens structure can be formed on the side of the third substrate 130 away from the first substrate 110. This allows for the control of light emission from the display chip through the microlens structure, thereby improving display performance. Of course, the microlens structure can also be omitted, depending on actual needs.

[0126] For example, after flipping the second light-emitting wafer and bonding it to the first light-emitting wafer, the second substrate 120 of the second light-emitting wafer can also be removed. The removed second substrate 120 can be reused. For example, before reusing the second substrate 120, it can also be subjected to surface polishing, cleaning, or other treatments.

[0127] Similarly, after flipping and bonding the third light-emitting wafer, the third substrate 130 of the third light-emitting wafer can also be removed. The removed third substrate 130 can be reused. In addition to removing the third substrate 130, a protective layer can be formed to passivate and protect the display chip.

[0128] After stacking, the light-emitting units 200a within each light-emitting wafer can form a multilayer light-emitting unit 200a. Multiple light-emitting units 200a located in different layers of light-emitting units 200a and stacked vertically opposite each other can form a pixel unit. The same pixel unit can correspond to one first conductive structure 310 and multiple second conductive structures 320. Furthermore, the number of second conductive structures 320 corresponding to the same pixel unit can be the same as the number of light-emitting units 200a stacked vertically within it, which is the number of sequentially stacked light-emitting wafers, m.

[0129] Specifically, for the same pixel unit, the conductive materials in the first through-hole H1 within each light-emitting wafer are sequentially and vertically interconnected, thereby forming a first conductive structure 310 through conductive connection. Furthermore, within the same pixel unit, the first conductive structure 310 can electrically connect to the first semiconductor layer 210 of each light-emitting unit 200a within that pixel unit, thereby supplying power to the first semiconductor layer 210 of each light-emitting unit 200a.

[0130] Simultaneously, for the same pixel unit, the conductive material within the second via H2 of all light-emitting wafers except the bottommost light-emitting wafer can be vertically interconnected with the conductive material within the second via H2 of the light-emitting wafer located below it, thereby forming m-1 second conductive structures 320. m is the number of light-emitting wafers stacked sequentially. Also, one second conductive structure 320 can be formed based on the conductive material within the second via H2 of the bottommost light-emitting wafer. Thus, for the same pixel unit, m second conductive structures 320 can be formed. Furthermore, within the same pixel unit, each second conductive structure 320 can correspond to the topmost light-emitting unit 200a it passes through, thereby electrically connecting to the second semiconductor layer 230 of that light-emitting unit 200a, thus supplying power only to that second semiconductor layer 230. Therefore, the second semiconductor layers 230 of different light-emitting units 200a are powered through different second conductive structures 320.

[0131] For example, a first light-emitting wafer, a second light-emitting wafer, and a third light-emitting wafer can be stacked and bonded sequentially from bottom to top in a vertical direction. The light-emitting unit 200a of the first light-emitting wafer is denoted as first light-emitting unit a1, the light-emitting unit 200a of the second light-emitting wafer is denoted as second light-emitting unit a2, and the light-emitting unit 200a of the third light-emitting wafer is denoted as third light-emitting unit a3.

[0132] After stacking, for the same pixel unit, the conductive materials in the first through-hole H1 of the first light-emitting wafer, the conductive materials in the first through-hole H1 of the second light-emitting wafer, and the conductive materials in the first through-hole H1 of the third light-emitting wafer are vertically interconnected in sequence, thereby forming a first conductive structure 310 through conductive connection.

[0133] Simultaneously, for the same pixel unit, the conductive material within the second through-hole H2 of the third light-emitting wafer can be vertically interconnected with the conductive material within the second through-hole H2 of the second light-emitting wafer located below it and the conductive material within the second through-hole H2 of the first light-emitting wafer, thereby forming a second conductive structure 320 corresponding to the third light-emitting unit a3. The conductive material within another second through-hole H2 of the second light-emitting wafer can be vertically interconnected with the conductive material within the second through-hole H2 of the first light-emitting wafer located below it, thereby forming another second conductive structure 320 corresponding to the second light-emitting unit a2. Furthermore, based on the conductive material within the remaining second through-hole H2 of the first light-emitting wafer, yet another second conductive structure 320 corresponding to the first light-emitting unit a1 can be formed. Thus, three second conductive structures 320 can be formed.

[0134] For example, the size of the light-emitting units 200a in each light-emitting wafer can be the same. In this case, after the light-emitting wafers are stacked and bonded in sequence, the light-emitting units 200a in the same pixel unit can share the same light-emitting surface, thereby facilitating the reduction of pixel area or the increase of pixel density.

[0135] In this embodiment, multiple different light-emitting wafers are individually formed, and a first via H1 and a second via H2 are formed in each light-emitting unit 200a of each light-emitting wafer. The number of second vias H2 formed in different light-emitting wafers is different. Then, the light-emitting wafers are sequentially stacked by bonding, and the conductive materials in the first vias H1 of different light-emitting wafers are vertically interconnected, as are the conductive materials in the oppositely positioned second vias H2 of different light-emitting wafers. This allows for the formation of one first conductive structure 310 and m second conductive structures 320 for each pixel unit, where m is the number of stacked light-emitting wafers. At this time, through via interconnection, the vertical stacking of the light-emitting wafers and the upward transmission of signals can be simultaneously achieved. The stacked arrangement of light-emitting units 200a within the same pixel can effectively reduce the pixel area or increase the pixel density. Meanwhile, at this point, electrical connections with the N-type and P-type semiconductor layers of each light-emitting unit 200a can be achieved through m+1 conductive structures (one first conductive structure 310 and m second conductive structures 320), thereby enabling a more compact pixel structure. Furthermore, during subsequent packaging, the bottom of each of the m+1 conductive structures can be vertically connected to the driver chip 2, further enhancing the compactness of the pixel structure.

[0136] In one embodiment, referring to Figure 3, step S200 includes:

[0137] Step S210: At least the epitaxial layer 200 of each light-emitting wafer is etched to form shallow trenches, which isolate the epitaxial layer 200 into multiple light-emitting units 200a.

[0138] In step S220, insulating material is filled into the shallow trenches of each light-emitting wafer to form a shallow trench isolation structure 400.

[0139] In step S210, shallow trenches can be etched first for each light-emitting wafer. The shallow trenches can isolate the epitaxial layer 200 into multiple light-emitting units 200a, thereby defining the light-emitting units 200a in the epitaxial layer 200. The shape and size of the light-emitting units 200a can be set according to requirements.

[0140] For example, the size of the light-emitting unit 200a can be approximately 30 μm to 100 μm.

[0141] For example, the spacing (i.e. pixel spacing) between the individual light-emitting units 200a on the same light-emitting wafer can be approximately 2μm to 5μm, that is, the width of the shallow trench can be between 2μm and 5μm.

[0142] For example, the depth of the shallow trench can be between approximately 2 μm and 3 μm.

[0143] For example, the depth of the shallow trench formed in each light-emitting wafer can be slightly greater than the thickness of its epitaxial layer 200, so that the shallow trench can extend from the epitaxial layer 200 into the substrate, thereby providing good insulation and isolation.

[0144] For example, shallow trenches can be formed by etching the light-emitting wafer using a dry etching method.

[0145] For example, dry etching may specifically include inductively coupled plasma-reactive ion etching (ICP RIE).

[0146] For example, the reaction gas used for etching shallow trenches can be boron trichloride (BCl3) and chlorine (Cl2), and can be supplemented with a certain amount of nitrogen (N2) or argon (Ar) as an atmosphere gas.

[0147] For example, the flow rate ratio of the reactive gases BCl3 and Cl2 used for etching shallow trenches can be approximately 1:1, and the gas pressure can be approximately 10 mTorr. The ICP power can be set between 250W and 400W, and the RF power can be set between 50W and 200W.

[0148] In step S220, insulating material can be formed on the entire surface of the structure after the shallow trench is formed, and then the insulating material outside the shallow trench can be removed to form the shallow trench isolation structure 400.

[0149] For example, when forming an insulating material over the entire surface of a structure after forming a shallow trench, a passivation material may be formed first. The passivation material can passivate and protect the epitaxial layer 200 located on the sidewalls of the passivated shallow trench. Then, a filler material is formed on the surface of the passivation material.

[0150] For example, when forming a passivation material, a thin aluminum oxide (Al2O3) or silicon oxide (SiO2) film can be deposited by atomic layer deposition (ALD) process to cover the P-type semiconductor layer, multiple quantum well layer 220 and N-type semiconductor layer located on the sidewall of the shallow trench.

[0151] For example, when depositing passivation materials via the ALD process, an Al2O3 film can be generated by reacting trimethylaluminum (TMA) with water (H2O) (or oxygen (O2)). The growth temperature of the Al2O3 film can be set between 200°C and 350°C.

[0152] For example, when depositing passivation materials via the ALD process, an ultrathin SiO2 film can also be prepared by reacting aminosilane (BDEAS) with water (H2O) to serve as a passivation material. The growth temperature of the SiO2 film can be set between 200°C and 400°C.

[0153] For example, distributed Bragg reflector (DBR) materials can also be formed using an ALD process, such as by forming alternating stacked Al2O3 and SiO2 films. Then, the distributed Bragg reflector material outside the shallow trenches is removed by an etching process, thereby forming a DBR structure on the sidewalls of the shallow trenches.

[0154] When the shallow trench width is sufficient (e.g., greater than or equal to 5 μm), a DBR structure can be set for a specific emission wavelength, thereby reducing sidewall light leakage and increasing front light emission.

[0155] For example, when forming the filling material, a plasma-enhanced chemical vapor deposition (PECVD) process using tetraethoxysilane (TEOS) is used to deposit SiO2 material to fill the shallow trenches. The deposition of the SiO2 filling medium can be carried out at a low temperature range of 300°C to 400°C. The reaction gases can be TEOS and O2. The RF power can be approximately between 100W and 300W. Simultaneously, appropriately matching the flow rates of TEOS and O2 allows the reaction to proceed at a slower or suitable rate, enabling gradual filling of the STI and thus avoiding voids in the shallow trenches.

[0156] For example, when removing the insulating material outside the shallow trench to form a shallow trench isolation structure 400 within the shallow trench, the insulating material can be planarized using a chemical mechanical polishing (CMP) process. After planarization, the surface roughness of the light-emitting wafer can be maintained at a root mean square (RMS) value ≤ 1 nm. Atomic force microscopy (AFM) can be used to inspect the surface roughness and adjust and optimize the CMP process parameters. For example, when using AFM for surface inspection, 49 test points throughout the entire wafer can be tested.

[0157] In this embodiment, a plurality of light-emitting units 200a are defined in the epitaxial layer 200 of each light-emitting wafer by a shallow trench isolation structure 400, thereby isolating each pixel unit in the subsequently stacked display chip. At this time, the pixel pitch is the width of the shallow trench isolation structure 400 between the light-emitting units, rather than the traditional pitch between different independent Micro-LEDs, thereby further reducing the pixel pitch of the display chip and further increasing the pixel density.

[0158] In one embodiment, referring to Figures 4a to 4g, 5a to 5g, and 6a to 6g, before step S500, the method further includes:

[0159] In step S10, a first insulating layer 600 is formed on the side of the epitaxial layer 200 of each light-emitting wafer away from the substrate, and a first connection structure 510 and a second connection structure 520 are formed in the first insulating layer 600. The first connection structure 510 connects the conductive material in the first via H1 and the first semiconductor layer 210, and the second connection structure 520 connects the conductive material in the second via H2 and the second semiconductor layer 230.

[0160] The first insulating layer 600 can be a multi-layer structure, which may include multiple insulating film layers. The materials of the first connecting structure 510 and the second connecting structure 520 are conductive materials, thereby enabling conductive connection. The specific structural forms of the first connecting structure 510 and the second connecting structure 520 can be set according to actual needs.

[0161] In one embodiment, the first connection structure 510 includes a first connection electrode 511 and a first connection trace 512. The first connection electrode 511 is connected to the first semiconductor layer 210, and the first connection trace 512 is connected to the first connection electrode 511 and the conductive material in the first via H1. The second connection structure 520 includes a second connection electrode 521 and a second connection trace 522. The second connection electrode 521 is connected to the second semiconductor layer 230, and the second connection trace 522 is connected to the second connection electrode 521 and the conductive material in the corresponding second via H2.

[0162] Furthermore, the method of forming the first connection structure 510 and / or the second connection structure 520 includes:

[0163] Step S11: Forming electrode windows, wherein the electrode window of the first connection structure 510 extends to the first semiconductor layer 210, and the electrode window of the second connection structure 520 extends to the second semiconductor layer 230.

[0164] Step S12: Fill the electrode window with conductive material to form a connecting electrode;

[0165] Step S13: Form the connection traces connecting the connecting electrodes.

[0166] For example, the shape of the electrode window can be annular, so that the first connecting electrode 511 and / or the second connecting electrode 521 are annular structures.

[0167] For example, both the first connecting electrode 511 and the second connecting electrode 521 are annular structures, and the second connecting electrode 521 can surround the first connecting electrode 511. The area enclosed by the ring of the first connecting electrode 511 can be the light-emitting area of ​​the light-emitting unit 200a. After stacking, the light-emitting areas of the light-emitting units 200a on different light-emitting wafers can be arranged relative to each other.

[0168] The distribution design of the first connecting electrode 511, the second connecting electrode 521, the first through hole H1, and the second through hole H2 on the light-emitting unit 200a can be set according to actual needs. Figures (a), (b), (c), and (d) in Figure 8 show four different distribution designs of the light-emitting unit 200a. It can be understood that the distribution design of the light-emitting unit 200a is not limited to the four forms presented in Figures 4a to 4d.

[0169] For example, the width of the electrode window can be approximately 2 μm to 3 μm, so that the width of the first connecting electrode 511 and / or the second connecting electrode 521 can be approximately 2 μm to 3 μm.

[0170] For example, step S12 may include:

[0171] Step S121: An ohmic contact material is formed at the bottom of the electrode window;

[0172] Step S122: Form electrode material in the remaining space of the electrode window.

[0173] In step S121, when the bottom of the electrode window is a P-type semiconductor layer, the ohmic contact material may include Pt / Au / Ni / Cu. When the bottom of the electrode window is an N-type semiconductor layer, the ohmic contact material may include Ti / Al / Ti / Cu. The total thickness of the ohmic contact material can be controlled within 500 nm.

[0174] Optionally, ohmic contact material can be deposited both inside and outside the electrode window using a PVD sputtering process. Then, the ohmic contact material outside the electrode window can be etched away, leaving only the ohmic contact material inside the electrode window. The ohmic contact material can then be annealed.

[0175] In step S122, the electrode material can fill the remaining space of the electrode window. Optionally, the electrode material (such as copper) can be formed within the electrode window by an electroplating process.

[0176] In one embodiment, the first connecting structure 510 and the second connecting structure 520 can be fabricated separately, with one of them being fabricated after the other has been fabricated. In this case, both the first connecting structure 510 and the second connecting structure 520 can independently perform steps S11 to S13.

[0177] For example, the second connection structure 520 can be formed first, and then the first connection structure 510 can be formed.

[0178] When forming the second connection structure 520, please refer to Figures 4c, 5c and 6c. Before step S11, after filling the first through hole H1 and the second through hole H2 of each light-emitting wafer with conductive material in step S400, the first sub-insulating layer 610 is first deposited.

[0179] Optionally, the material of the first sub-insulating layer 610 may include SiO2, Si x N y or Si x C1- x N yMaterials such as the first insulating layer 610. The thickness of the first insulating layer 610 can be approximately 2 μm to 3 μm.

[0180] Optionally, after depositing the first sub-insulating layer 610, the first sub-insulating layer 610 can be subjected to CMP treatment to planarize its surface. The RMS of the planarized first sub-insulating layer 610 can be less than or equal to 1 nm, and the thickness can be from 1.5 μm to 2 μm.

[0181] Then, in step S11, referring to Figures 4c, 5c, and 6c, an electrode window can be formed that penetrates the first sub-insulating layer 610 and extends to the second semiconductor layer 230. This electrode window is referred to as the second electrode window. Optionally, the second semiconductor layer 230 includes a heavily p-type doped layer. The second electrode window can then extend to the surface of the heavily p-type doped layer.

[0182] Then, in step S12, if the second electrode window (such as the second electrode window on the first light-emitting wafer, see Figure 4c) only penetrates the first sub-insulating layer 610, conductive material can be directly filled into the second electrode window to form a connection electrode in the second electrode window. This connection electrode is the second connection electrode 521.

[0183] If the second electrode window (such as the second electrode window on the second and third light-emitting wafers, see Figures 5c and 6c) extends both through the first sub-insulating layer 610 and into a portion of the epitaxial layer 200, a sidewall passivation layer can be formed first on the sidewall of the second electrode window, and then a conductive material can be filled into the second electrode window to form a connection electrode. This connection electrode is the second connection electrode 521.

[0184] Then, in step S13, referring to Figures 4d, 5d, and 6d, a connection trace connecting the second connection electrode 521 is formed. This connection trace is designated as the second connection trace 522. The second connection trace 522 connects the second connection electrode 521 to the conductive material within the corresponding second via H2.

[0185] Specifically, since the upper surface of the second connecting electrode 521 and the upper surface of the conductive material in the second through hole H2 are not on the same plane, an opening can be formed in the first sub-insulating layer 610 to expose the conductive material in the corresponding second through hole H2 before forming the second connecting trace 522. Then, the conductive material is filled into the opening.

[0186] For example, Cu can be electroplated into the opening at a slower rate until the opening within the first sub-insulating layer 610 is completely filled. Subsequently, the electroplated Cu and the first sub-insulating layer 610 can be CMP-plated to planarize the surface after CMP. The RMS of the planarized surface can be less than or equal to 1 nm. The thickness of the planarized first sub-insulating layer 610 can be within 1 μm to 1.5 μm.

[0187] Subsequently, the second connection trace 522 can be formed through processes such as physical vapor deposition (PVD) sputtering, photolithography, and etching. The second connection trace 522 covers the conductive material (such as electroplated Cu) in the opening above the first connection electrode 511 embedded in the first sub-insulating layer 610, part of the first sub-insulating layer 610, and the corresponding second through hole H2, thereby electrically connecting the second connection electrode 521 to the conductive material in the corresponding second through hole H2.

[0188] For example, the second connection line 522 includes a Ti / Cu metal thin film. The thickness of the second connection line 522 can be in the range of approximately 500 nm to 1 μm. The width of the second connection line 522 can be approximately 1 μm to 1.5 μm.

[0189] Referring to Figures 4e, 5e, and 6e, after forming the second connection trace 522, a second sub-insulating layer 620 can be formed covering the first sub-insulating layer 610, the second connection electrode 521, and the second connection trace 522. Exemplarily, a SiO2 thin film can be deposited using a PECVD TEOS process to form the second sub-insulating layer 620. The thickness of the PECVD-deposited second sub-insulating layer 620 can be approximately 1.5 μm to 2.5 μm (e.g., 2 μm). Subsequently, the second sub-insulating layer 620 can be subjected to CMP treatment to planarize its surface. The RMS of the planarized second sub-insulating layer 620 can be less than or equal to 1 nm, and its thickness can be 1 μm to 1.5 μm.

[0190] Then, the first connecting structure 510 can be prepared.

[0191] When forming the first connection structure 510, in step S11, an electrode window can be formed that penetrates the second sub-insulating layer 620 and the first sub-insulating layer 610 and extends to the first semiconductor layer 210. This electrode window is referred to as the first electrode window. Optionally, the first semiconductor layer 210 includes an N-type heavily doped layer. Then the first electrode window can extend to the surface of the N-type heavily doped layer. Both the first electrode window and the second electrode window are annular, and the first electrode window can be distributed within the area surrounded by the second electrode window. The spacing between the first electrode window and the second electrode window can be approximately 1 μm to 2 μm.

[0192] Then, in step S12, if the first electrode window (such as the first electrode window on the second light-emitting wafer and the third light-emitting wafer, see Figures 5e and 6e) only penetrates the second sub-insulating layer 620 and the first sub-insulating layer 610, conductive material can be directly filled into the first electrode window to form a connection electrode in the second electrode window. This connection electrode is the first connection electrode 511.

[0193] If the first electrode window (such as the first electrode window on the first light-emitting wafer, see Figure 4e) penetrates both the second sub-insulating layer 620 and the first sub-insulating layer 610, and extends into part of the epitaxial layer 200, a sidewall passivation layer can be formed first on the sidewall of the first electrode window, and then a conductive material can be filled into the first electrode window to form a connection electrode. This connection electrode is the first connection electrode 511.

[0194] Then, in step S13, a connection trace connecting the first connection electrode 511 is formed. This connection trace is designated as the first connection trace 512. The first connection trace 512 connects the first connection electrode 511 to the conductive material within the first through hole H1.

[0195] Specifically, since the upper surface of the first connecting electrode 511 and the upper surface of the conductive material in the first through hole H1 are not on the same plane, an opening can be formed to expose the conductive material in the first through hole H1 before forming the first connecting trace 512, penetrating the second sub-insulating layer 620 and the first sub-insulating layer 610. Then, the conductive material is filled into the opening.

[0196] For example, Cu can be electroplated into the opening at a slower rate until the opening is completely filled. Afterwards, the electroplated Cu and the second sub-insulating layer 620 can be CMP-plated to planarize the surface after CMP. The RMS of the planarized surface can be less than or equal to 1 nm. The thickness of the planarized second sub-insulating layer 620 can be within 1 μm to 1.5 μm.

[0197] Subsequently, the first connection trace 512 can be formed through physical vapor deposition (PVD) sputtering, photolithography, etching, and other processes. The first connection trace 512 covers the first connection electrode 511, part of the second sub-insulating layer 620, and the conductive material (such as electroplated Cu) in the opening above the first through hole H1, thereby electrically connecting the first connection electrode 511 to the conductive material in the first through hole H1.

[0198] For example, the first connection trace 512 includes a Ti / Cu metal thin film. The thickness of the first connection trace 512 can be in the range of approximately 500 nm to 1 μm. The width of the first connection trace 512 can be approximately 1 μm to 1.5 μm.

[0199] In this embodiment, the first connection structure 510 and the second connection structure 520 are fabricated separately for ease of design. Of course, in other embodiments, the fabrication of the first connection structure 510 and the second connection structure 520 can also involve overlapping steps. For example, the first connection electrode 511 of the first connection structure 510 and the second connection electrode 521 of the second connection structure 520 can be fabricated simultaneously. Then, the first connection trace 512 of the first connection structure 510 and the second connection trace 522 of the second connection structure 520 are fabricated separately. It is understood that an insulating layer exists between the first connection trace 512 and the second connection trace 522. Furthermore, before the later-formed connection trace (the first connection trace 512 or the second connection trace 522) is formed, an opening can be etched and filled with conductive material, thereby enabling the connection trace to connect to the corresponding connection electrode and the conductive material within the through-hole (the first through-hole H1 or the second through-hole H2).

[0200] In one embodiment, referring to Figures 4f, 5f, and 6f, after forming the first connection trace 512, a third sub-insulating layer 630 can be formed covering the second sub-insulating layer 620, the first connection electrode 511, and the first connection trace 512. Exemplarily, a SiO2 thin film can be deposited using a PECVD TEOS process to form the third sub-insulating layer 630. The third sub-insulating layer 630, the second sub-insulating layer 620, and the first sub-insulating layer 610 form the first insulating layer 600.

[0201] Next, referring to Figures 4g, 5g, and 6g, the first insulating layer 600 can be etched to form a first lead-out hole opposite to the first through-hole H1 and a second lead-out hole opposite to the second through-hole H2. Then, conductive material can be filled into the first lead-out hole and the second lead-out hole by processes such as copper electroplating to bring out the conductive material in the first through-hole H1 and the second through-hole H2.

[0202] The first lead-out hole can penetrate the third sub-insulating layer 630 to expose the first connection trace 512. Different light-emitting wafers can form different numbers and different forms of second lead-out holes depending on their stacked layers.

[0203] For example, the multiple different light-emitting wafers provided in step S100 include a first light-emitting wafer, a second light-emitting wafer, and a third light-emitting wafer. In step S500, the first light-emitting wafer, the second light-emitting wafer, and the third light-emitting wafer are stacked and bonded sequentially from bottom to top in the vertical direction.

[0204] Referring again to Figure 4g, two second lead-out holes can be formed in the first light-emitting wafer. The two second lead-out holes penetrate the third sub-insulating layer 630, the second sub-insulating layer 620 and the first sub-insulating layer 610, and respectively expose the second through hole H2 of the corresponding second light-emitting wafer and the second through hole H2 of the corresponding third light-emitting wafer.

[0205] Referring to Figure 5g, two second vias can be formed in the second light-emitting wafer. One of the second vias penetrates the third sub-insulating layer 630 and the second sub-insulating layer 620, and exposes the second connection trace 522 formed on the second light-emitting wafer. The other second via penetrates the third sub-insulating layer 630, the second sub-insulating layer 620, and the first sub-insulating layer 610, and exposes the corresponding second via H2 of the third light-emitting wafer.

[0206] Referring to Figure 6g, a second via can be formed in the third light-emitting wafer. This second via penetrates the third sub-insulating layer 630 and the second sub-insulating layer 620, and exposes the second connection trace 522 formed on the third light-emitting wafer.

[0207] After the conductive filling material is formed on each light-emitting wafer, CMP planarization can be performed on the conductive filling material and the surface of the first insulating layer 600 (i.e., the surface of the third sub-insulating layer 630). After CMP planarization, the RMS of the planarized surface can be less than or equal to 1 nm. The thickness of the planarized third sub-insulating layer 630 can be within 1 μm to 1.5 μm.

[0208] Next, in step S500, referring to Figure 7, the second light-emitting wafer can be flipped, and then, based on the first insulating layer 600 and the conductive material (such as copper) in the first and second leads, the second light-emitting wafer and the first light-emitting wafer are mixed-bonded. At this time, no underfill (UFM) is needed between the second and first light-emitting wafers, making the connection between them more compact and reliable. Furthermore, the second light-emitting wafer can be effectively stacked on top of the first light-emitting wafer, simultaneously achieving vertical interconnection of the conductive materials in the first through-holes H1 of the two light-emitting wafers, and vertical interconnection of the conductive materials in the corresponding second through-holes H2 of the second light-emitting wafer and the corresponding second through-hole H2 of the third light-emitting wafer.

[0209] After the second light-emitting wafer is mixed and bonded with the first light-emitting wafer, an annealing process can be performed to eliminate the dish effect that may exist at the bonding metal interface of the two light-emitting wafers, thereby ensuring a seamless connection of the interface layer of the two light-emitting wafers.

[0210] Subsequently, the second substrate 120 of the second light-emitting wafer can be thinned using a CMP process to expose the conductive material within the first via H1 and the second via H2 of the second light-emitting wafer.

[0211] For example, during the thinning process of the second substrate 120, chemical mechanical polishing (CMP) can be used first to coarsely polish the second substrate 120 at a relatively fast speed, reducing its thickness to about 30 μm. Then, the second substrate 120 is finely polished at a slower rate with a finer abrasive particle size, reducing its thickness to about 10 μm. Afterward, a more refined CMP technique is used to polish the second substrate 120, planarizing its surface and exposing the conductive material within the first via H1 and the second via H2 of the second light-emitting wafer. At this point, the thickness of the second substrate 120 can be reduced to within approximately 5 μm to 10 μm.

[0212] Next, the third light-emitting wafer can be flipped, and then the conductive material (such as copper) within the first insulating layer 600 of the third light-emitting wafer (specifically within the first and second lead-out holes) is bonded to the conductive material (such as copper) within the second substrate 120 of the second light-emitting wafer (specifically within the first via H1 and second via H2), thereby stacking and bonding the third light-emitting wafer to the thinned second light-emitting wafer. At this point, no underfill (UFM) is needed between the third and second light-emitting wafers, making the connection between them more compact and reliable.

[0213] Optionally, the bonding temperature environment can be a low-temperature environment of 200℃ to 400℃. After bonding, annealing can be performed in a nitrogen or vacuum atmosphere for about 30 minutes to eliminate any possible dishing phenomenon at the interface between the conductive material (such as copper) in the first insulating layer 600 of the third light-emitting wafer (specifically in the first and second lead-out holes) and the conductive material (such as copper) in the second substrate 120 of the second light-emitting wafer (specifically in the first via H1 and the second via H2), thereby ensuring a seamless connection of the interface layers of the two light-emitting wafers.

[0214] In one embodiment, referring to Figure 7, after step S500, the following is also included:

[0215] In step S600, the substrate of the bottom light-emitting wafer is thinned so that the first conductive structure 310 and the second conductive structure 320 are exposed and protrude relative to the substrate of the bottom light-emitting wafer.

[0216] In step S700, a second insulating layer 700 is formed on the substrate surface, the surface of the first conductive structure 310, and the surface of the second conductive structure 320 of the thinned bottom light-emitting wafer.

[0217] In step S800, the second insulating layer 700 is etched to expose the first conductive structure 310 and the second conductive structure 320.

[0218] The following explanation will take step S500, in which the first light-emitting wafer, the second light-emitting wafer, and the third light-emitting wafer are stacked and bonded sequentially from bottom to top in the vertical direction.

[0219] At this time, in step S600, the first substrate 110 of the first light-emitting wafer can be thinned.

[0220] For example, chemical mechanical polishing can be used to thin the first substrate 110, which can be divided into two steps: coarse polishing and fine polishing. After coarse polishing, the thickness of the first substrate 110 can be reduced to about 15 μm. Then, fine polishing is used to planarize the surface of the first substrate 110, so that the thickness of the first substrate 110 is reduced to about 10 μm, thereby exposing the conductive material in the first via H1, and exposing the conductive material (such as copper) in the three second vias H2 corresponding to different light-emitting wafers (first light-emitting wafer, second light-emitting wafer and third light-emitting wafer), that is, exposing the first conductive structure 310 and multiple second conductive structures 320.

[0221] Following this, a wet etching method can be used to lightly and gently etch the surface of the first substrate 110 to further thin the first substrate 110, thereby making the exposed first conductive structure 310 and multiple second conductive structures 320 slightly protrude relative to the first substrate 110. Optionally, the protrusion height can be approximately 500 nm to 1 μm.

[0222] In step S700, a SiO2 thin film can be deposited on the surface of the thinned first substrate 110 and on the surfaces of the first conductive structure 310 and the plurality of second conductive structures 320, which are slightly protruding relative to the first substrate 110, to serve as a second insulating layer 700. The thickness of the second insulating layer 700 can be approximately 0.5 μm to 1 μm.

[0223] In step S800, the second insulating layer 700 can be etched by dry or wet BOE etching to expose the first conductive structure 310 and the second conductive structure 320.

[0224] For example, after etching the second insulating layer 700, the first conductive structure 310 and the second conductive structure 320 can protrude relative to the second insulating layer 700 to form microbumps, which facilitates subsequent microbump thermo-bonding with the driver chip.

[0225] For example, after etching the second insulating layer 700, the bottom of the first conductive structure 310, the bottom of the second conductive structure 320, and the bottom of the second insulating layer 700 can be made flush, so that the portions of the first conductive structure 310 and the second conductive structure 320 embedded in the second insulating layer 700 form micro copper pillars, which facilitates subsequent hybrid bonding with the driver chip.

[0226] At this point, the fabrication of the display chip is complete. Next, referring to Figure 9, the display chip 1 is packaged to form a display device.

[0227] Specifically, the display chip 1 and the driver chip 2 can be electrically connected through the first conductive structure 310 and a plurality of second conductive structures 320.

[0228] For example, the first conductive structure 310 and the second conductive structure 320 derived from the back side of the first substrate 110 of the first light-emitting wafer can be connected to the silicon-based addressable active driver chip 2.

[0229] For example, the display chip 1 installed on the driver chip 2 includes a first light-emitting unit a1, a second light-emitting unit a2 and a third light-emitting unit a3, wherein the first light-emitting unit a1 is a red light-emitting unit, the second light-emitting unit a2 is a green light-emitting unit and the third light-emitting unit a3 is a blue light-emitting unit.

[0230] At this point, the traditional method of transferring separate red, green, and blue Micro-LED chips and laying them flat on the driving circuit can be abandoned. Instead, metal interconnect technology within the display chip can be used to insulate the three vertically stacked light-emitting units (red, green, and blue) horizontally and vertically, respectively, and connect them to corresponding vertical conductive vias (including the first and second vias). Then, the conductive vias of the display chip are brought out and vertically interconnected with the CMOS active driver chip via either micro-bump thermoforming bonding or hybrid bonding using micro-copper pillars embedded in the second insulating layer 700. Because the red, green, and blue micro-light-emitting layers are stacked sequentially in the vertical direction and share the same light-emitting surface, the area of ​​a single pixel unit can be further reduced.

[0231] For example, the side of the driver chip 2 furthest from the display chip 1 can be further electrically connected to the adapter board 3.

[0232] For example, micro-copper pillars and micro-bumps can be provided on the side of the driver chip 2 facing away from the display chip 1. Through-silicon vias and redistribution layers can be distributed on the adapter board 3. Further interconnection between the driver chip 2 and the adapter board 3 can be achieved through the micro-copper pillars and micro-bumps.

[0233] For example, after connecting the driver chip 2 to the adapter board 3, a molding compound 4 covering the driver chip 2 and the display chip 1 can be formed on the adapter board 3. The material of the molding compound 4 may include, but is not limited to, epoxy molding compound (EMC).

[0234] It should be understood that although the steps in the flowchart of Figure 1 are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some of the steps in Figure 1 may include multiple steps or multiple stages, which are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps.

[0235] In one embodiment, referring to FIG10, a pixel structure is provided, which includes a first substrate 110, a pixel unit, a first conductive structure 310, and a plurality of second conductive structures 320. Here, "a plurality of" can mean two or more.

[0236] The first substrate 110 may be, but is not limited to, a silicon substrate or a sapphire substrate.

[0237] The pixel unit includes multiple light-emitting units 200a. The multiple light-emitting units 200a are stacked sequentially on the first substrate 110. Different light-emitting units 200a are used to emit light of different colors.

[0238] Each light-emitting unit 200a includes a first semiconductor layer 210 and a second semiconductor layer 230. Specifically, each light-emitting unit 200a may include a first semiconductor layer 210, a multiple quantum well layer 220, and a second semiconductor layer 230. One of the first semiconductor layer 210 and the second semiconductor layer 230 is a P-type semiconductor layer, and the other is an N-type semiconductor layer. In addition, each light-emitting unit 200a may also include a stress buffer layer 240, a superlattice layer, an electron blocking layer 250, etc.

[0239] The film structure of different light-emitting units 200a can be the same, but is not limited to being the same. That is, the film structure of different light-emitting units 200a can also be different. For example, each light-emitting unit 200a may include a first semiconductor layer 210, a multi-quantum well layer 220, and a second semiconductor layer 230 sequentially stacked along a direction away from the first substrate 110. Alternatively, each light-emitting unit 200a may include a second semiconductor layer 230, a multi-quantum well layer 220, and a first semiconductor layer 210 sequentially stacked along a direction away from the first substrate 110. Furthermore, some light-emitting units 200a may include a first semiconductor layer 210, a multi-quantum well layer 220, and a second semiconductor layer 230 sequentially stacked along a direction away from the substrate, while other light-emitting units 200a may include a second semiconductor layer 230, a multi-quantum well layer 220, and a first semiconductor layer 210 sequentially stacked along a direction away from the substrate.

[0240] For example, the plurality of light-emitting units 200a include a first light-emitting unit a1, a second light-emitting unit a2 and a third light-emitting unit a3 stacked sequentially on a first substrate 110.

[0241] For example, the first light-emitting unit a1 may include a stress buffer layer 240, a first semiconductor layer 210, a multiple quantum well layer 220, an electron blocking layer 250 and a second semiconductor layer 230 disposed sequentially along a direction away from the first substrate 110.

[0242] The second light-emitting unit a2 may include a stress buffer layer 240, a second semiconductor layer 230, an electron blocking layer 250, a multiple quantum well layer 220 and a first semiconductor layer 210 arranged sequentially along the direction close to the first substrate 110.

[0243] The third light-emitting unit a3 may include a stress buffer layer 240, a second semiconductor layer 230, an electron blocking layer 250, a multiple quantum well layer 220 and a first semiconductor layer 210 arranged sequentially along the direction close to the first substrate 110.

[0244] At this time, the arrangement orientation of the first semiconductor layer 210, the multi-quantum well layer 220 and the second semiconductor layer 230 of all light-emitting units 200a (first light-emitting unit a1, second light-emitting unit a2 and third light-emitting unit a3) can be kept consistent in the vertical direction.

[0245] Further, by way of example, the first light-emitting unit a1 can be a red light-emitting unit 200a, the second light-emitting unit a2 can be a green light-emitting unit 200a, and the third light-emitting unit a3 can be a blue light-emitting unit 200a.

[0246] For example, the first light-emitting unit a1, the second light-emitting unit a2, and the third light-emitting unit a3 can all be gallium nitride-based light-emitting units 200a. The first semiconductor layer 210 can include an N-type GaN layer. The second semiconductor layer 230 can include a P-type GaN layer. Furthermore, the second semiconductor layer 230 may also include a heavily doped P-type GaN capping layer located on the side of the P-type GaN layer away from the multi-quantum-well layer 220. The stress buffer layer 240 can be made of gallium nitride (GaN) or aluminum nitride (AlN), etc. The electron blocking layer 250 can be made of aluminum gallium nitride (AlGaN).

[0247] Meanwhile, the multi-quantum-well layer 220 may include alternating stacked quantum barriers 222 and quantum wells 221.

[0248] In the first light-emitting unit a1, the quantum barrier 222 may be made of aluminum indium gallium nitride (AlInGaN), and the quantum well 221 may be made of indium gallium nitride (InGaN). Alternatively, the first light-emitting unit a1 may also be made of a narrow-bandgap gallium arsenide (GaAs) based material. The multi-quantum-well layer 220 of the first light-emitting unit a1 may also include alternating stacks of indium gallium arsenide phosphide (InGaAsP / ) and gallium arsenide (GaAs).

[0249] In the second light-emitting unit a2 and the third light-emitting unit a3, the material of the quantum barrier 222 may include gallium nitride (GaN), and the material of the quantum well may include indium gallium nitride (InGaN).

[0250] For example, each light-emitting unit 200a may have the same shape, such as square, circle, polygon, etc.

[0251] The first conductive structure 310 extends from the first substrate 110 to at least the first semiconductor layer 210 of the light-emitting unit 200a furthest from the first substrate 110. That is, the first conductive structure 310 can extend from the first substrate 110 to the first semiconductor layer 210 of the light-emitting unit 200a furthest from the first substrate 110, or it can extend from the first substrate 110 to above the first semiconductor layer 210 of the light-emitting unit 200a furthest from the first substrate 110, depending on actual needs.

[0252] Furthermore, the first conductive structure 310 is electrically connected to the first semiconductor layer 210 of each light-emitting unit 200a, thereby supplying power to the first semiconductor layer 210 of each light-emitting unit 200a.

[0253] The number of second conductive structures 320 is the same as that of light-emitting units 200a, and they are arranged in a one-to-one correspondence. At this time, for each light-emitting unit 200a, there is a corresponding second conductive structure 320.

[0254] Each second conductive structure 320 extends from the first substrate 110 to at least the second semiconductor layer 230 of the corresponding light-emitting unit 200a. That is, for each second conductive structure 320, it can extend from the first substrate 110 to the second semiconductor layer 230 of the corresponding light-emitting unit 200a, or it can extend from the first substrate 110 to above the second semiconductor layer 230 of the corresponding light-emitting unit 200a, which can be set according to actual needs.

[0255] Meanwhile, each second conductive structure 320 is electrically connected to the second semiconductor layer 230 of the corresponding light-emitting unit 200a, thereby supplying power only to the second semiconductor layer 230 of the corresponding light-emitting unit 200a. Therefore, the second semiconductor layer 230 of different light-emitting units 200a is powered through different second conductive structures 320.

[0256] For example, the plurality of light-emitting units 200a of the pixel unit includes a first light-emitting unit a1, a second light-emitting unit a2, and a third light-emitting unit a3 stacked sequentially on the first substrate 110. Then, the same pixel structure can be provided with one first conductive structure 310 and three second conductive structures 320. The three second conductive structures 320 supply power to the second semiconductor layer 230 of the first light-emitting unit a1, the second light-emitting unit a2, and the third light-emitting unit a3, respectively.

[0257] For example, the size of each light-emitting unit 200a within a pixel unit can be the same. In this case, each light-emitting unit 200a within the same pixel unit can share the same light-emitting surface, thereby facilitating a reduction in pixel area or an increase in pixel density.

[0258] In this embodiment, the pixel structure includes a first substrate 110 and pixel units. Each pixel unit includes a plurality of light-emitting units 200a stacked sequentially on the first substrate 110, thereby facilitating a reduction in pixel area or an increase in pixel density. The pixel structure also includes one first conductive structure 310 and a plurality of second conductive structures 320. The number of second conductive structures 320 is the same as the number of light-emitting units 200a, and they are arranged in a one-to-one correspondence. In this case, fewer conductive structures can be used to achieve electrical connections with the N-type and P-type semiconductor layers of each light-emitting unit 200a, further enabling a more compact pixel structure. Simultaneously, during the packaging of the pixel structure, the bottom of both the first conductive structure 310 and the second conductive structures 320 can be vertically connected to the driver chip 2, further improving the compactness of the pixel structure.

[0259] In one embodiment, the pixel unit further includes multiple connection units. Each connection unit corresponds one-to-one with a light-emitting unit 200a. That is, one connection unit corresponds to one light-emitting unit 200a.

[0260] Please refer to Figure 4a. Each connection unit includes a first connection structure 510 and a second connection structure 520.

[0261] The first connection structure 510 includes a first connection electrode 511 and a first connection trace 512. Referring to FIG4f, within the same light-emitting unit 200a, the first connection electrode 511 is connected to the first semiconductor layer 210, and the first connection trace 512 connects the first connection electrode 511 and the first conductive structure 310.

[0262] The second connection structure 520 is insulated from the first connection structure 510 by a distance. The second connection structure 520 includes a second connection electrode 521 and a second connection trace 522. Referring to FIG4d, within the same light-emitting unit 200a, the second connection electrode 521 is connected to the second semiconductor layer 230, and the second connection trace 522 connects the second connection electrode 521 to the corresponding second conductive structure 320.

[0263] The second connecting electrode 521 and the first connecting electrode 511 can be located on the same side of the corresponding light-emitting unit 200a. The second connecting electrode 521 can extend vertically to the second semiconductor layer 230, and the first connecting electrode 511 can extend vertically to the first semiconductor layer 210. The second connecting electrode 521 and the first connecting electrode 511 can be spaced apart.

[0264] Meanwhile, in the vertical direction, there is an insulating layer between the first connection trace 512 and the second connection trace 522. The surface of the first connection electrode 511 near the first connection trace 512 and the surface of the second connection electrode 521 near the second connection trace 522 are not on the same plane.

[0265] For example, the second connection trace 522 can be located on the side of the first connection trace 512 closer to the first substrate 110. Alternatively, the second connection trace 522 can be located on the side of the first connection trace 512 away from the first substrate 110. The specific configuration can be determined according to actual needs.

[0266] For example, the first connecting electrode 511 has a ring structure.

[0267] For example, the second connecting electrode 521 has a ring structure.

[0268] For example, referring to Figure 4a, both the first connecting electrode 511 and the second connecting electrode 521 are annular structures. One of the first connecting electrode 511 and the second connecting electrode 521 surrounds the other, and the area enclosed by the one located in the inner ring can be the light-emitting area of ​​the light-emitting unit 200a. For example, the second connecting electrode 521 can surround the first connecting electrode 511. In this case, the area enclosed by the ring of the first connecting electrode 511 can be the light-emitting area of ​​the light-emitting unit 200a.

[0269] For example, the light-emitting areas of the stacked light-emitting units 200a can be arranged relative to each other, and the orthographic projections of each light-emitting unit 200a on the first substrate 110 can overlap.

[0270] In one embodiment, referring to FIG7, the pixel structure further includes a first insulating layer 600. The first insulating layer 600 is disposed between adjacent light-emitting units 200a. The first insulating layer 600 can be a multilayer structure, which may include multiple insulating film layers.

[0271] The first connecting trace 512 and the second connecting trace 522 are located within the first insulating layer 600, and thus can be wrapped by the first insulating layer 600.

[0272] The first connecting electrode 511 passes through the first insulating layer 600 from within the first insulating layer 600 toward the corresponding light-emitting unit 200a, thereby connecting with the corresponding first semiconductor layer 210.

[0273] The second connecting electrode 521 passes through the first insulating layer 600 from within the first insulating layer 600 toward the corresponding light-emitting unit 200a, thereby connecting with the corresponding second semiconductor layer 230.

[0274] For example, the plurality of light-emitting units 200a of the pixel unit includes a first light-emitting unit a1, a second light-emitting unit a2, and a third light-emitting unit a3 sequentially stacked on the first substrate 110. The first insulating layer 600 includes a first sub-insulating layer 610, a second sub-insulating layer 620, and a third sub-insulating layer 630.

[0275] Two first insulating layers 600 symmetrically arranged in the vertical direction can be provided between the first light-emitting unit a1 and the second light-emitting unit a2. The connecting unit corresponding to the first light-emitting unit a1 and the connecting unit corresponding to the second light-emitting unit a2 can both be located between the two. A first insulating layer 600 can be provided between the second light-emitting unit a2 and the third light-emitting unit a3, and the connecting unit corresponding to the third light-emitting unit a3 can be provided between the second light-emitting unit a2 and the third light-emitting unit a3.

[0276] In one embodiment, as shown in Figure 7, the pixel structure further includes a second insulating layer 700.

[0277] The second insulating layer 700 is disposed on the side of the first substrate 110 away from the light-emitting unit 200a. The first conductive structure 310 and the plurality of second conductive structures 320 penetrate the second insulating layer 700 and are exposed from the second insulating layer 700.

[0278] For example, the first conductive structure 310 and the plurality of second conductive structures 320 protrude relative to the second insulating layer 700.

[0279] For example, the thickness of the second insulating layer 700 can be approximately 0.5 μm to 1 μm.

[0280] In one embodiment, referring to FIG7, the plurality of light-emitting units 200a of the pixel unit include a first light-emitting unit a1, a second light-emitting unit a2 and a third light-emitting unit a3 stacked sequentially on the first substrate 110.

[0281] For example, the pixel structure further includes a second substrate 120. The second substrate 120 is located between the second light-emitting unit a2 and the third light-emitting unit a3. The first conductive structure 310 and a portion of the second conductive structure 320 may penetrate the second substrate 120.

[0282] Exemplarily, the pixel structure also includes a third substrate 130. The third substrate 130 is located on the side of the third light-emitting unit a3 away from the first substrate 110. Optionally, the first conductive structure 310 and the second conductive structure 320 corresponding to the third light-emitting unit a3 may extend into a portion of the third substrate 130. Of course, the first conductive structure 310 and the second conductive structure 320 corresponding to the third light-emitting unit a3 may not extend into the third substrate 130. The third substrate 130 can provide passivation protection for the pixel structure.

[0283] For example, the pixel structure also includes a microlens structure. The microlens structure is located on the side of the third substrate 130 away from the third light-emitting unit a3. The microlens structure can regulate the light emission of the display chip 1 to improve display performance.

[0284] In one embodiment, referring to FIG11, a display chip 1 is provided. The display chip 1 can be formed by, but is not limited to, the manufacturing method of the display chip 1 in any of the above embodiments.

[0285] Display chip 1 includes a plurality of pixel structures as described in any of the above embodiments. The first substrate 110 of each pixel structure can be the same substrate.

[0286] In one embodiment, referring to FIG11, the display chip 1 further includes a shallow trench isolation structure 400. The shallow trench isolation structure is located between the pixel units, thereby isolating the pixel units.

[0287] Specifically, the display chip 1 may include multiple layers of light-emitting units 200a, and each light-emitting unit 200a in each layer of light-emitting units 200a may be provided with a shallow trench isolation structure 400.

[0288] For example, the width of the shallow trench isolation structure 400 can be between 2 μm and 5 μm.

[0289] For example, the depth of the shallow trench isolation structure 400 can be between approximately 2 μm and 3 μm.

[0290] For example, the display chip 1 includes a first light-emitting unit a1, a second light-emitting unit a2, and a third light-emitting unit a3 sequentially stacked on a first substrate 110. Each pixel structure of the display chip 1 also includes a second substrate 120 and a third substrate 130. Furthermore, the second substrate 120 of each pixel structure can be the same substrate, and the third substrate 130 of each pixel structure can be the same substrate.

[0291] At this time, the depth of the shallow trench isolation structure 400 between each of the first light-emitting units a1 can be slightly greater than the thickness of the first light-emitting unit a1, so that the shallow trench isolation structure 400 can extend from the first light-emitting unit a1 into the first substrate 110, thereby achieving good insulation and isolation. And / or, the depth of the shallow trench isolation structure 400 between each of the second light-emitting units a2 can be slightly greater than the thickness of the second light-emitting unit a2, so that the shallow trench isolation structure 400 can extend from the second light-emitting unit a2 into the second substrate 120, thereby achieving good insulation and isolation. And / or, the depth of the shallow trench isolation structure 400 between each of the third light-emitting units a3 can be slightly greater than the thickness of the third light-emitting unit a3, so that the shallow trench isolation structure 400 can extend from the third light-emitting unit a3 into the third substrate 130, thereby achieving good insulation and isolation.

[0292] In one embodiment, referring to FIG9, a display device is provided. The display device includes the display chip 1 in any of the above embodiments, and includes a driver chip 2.

[0293] The driver chip 2 is located on one side of the display chip 1 and is electrically connected to the display chip 1 through a first conductive structure 310 and a plurality of second conductive structures 320.

[0294] For example, the driver chip 2 may include a silicon-based addressable active driver chip 2.

[0295] In one embodiment, the display device further includes an adapter board 3. The adapter board 3 is located on the side of the driver chip 2 away from the display chip 1 and is electrically connected to the driver chip 2.

[0296] For example, micro-copper pillars and micro-bumps can be provided on the side of the driver chip 2 facing away from the display chip 1. Through-silicon vias and redistribution layers can be distributed on the adapter board 3. The driver chip 2 can achieve further communication with the adapter board 3 through the micro-copper pillars and micro-bumps.

[0297] Exemplarily, the display device also includes a molding compound 4. The molding compound 4 may be located on the adapter board 3 and cover the driver chip 2 and the display chip 1. The material of the molding compound 4 may include, but is not limited to, epoxy molding compound (EMC).

[0298] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0299] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0300] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A pixel structure, characterized in that, include: First substrate; A pixel unit includes a plurality of light-emitting units stacked sequentially on a first substrate, each of the light-emitting units including a first semiconductor layer and a second semiconductor layer; A first conductive structure extends from the first substrate to at least the first semiconductor layer of the light-emitting unit furthest from the first substrate, and is electrically connected to the first semiconductor layer of each light-emitting unit; a plurality of second conductive structures are provided in the same number as the light-emitting units, and are arranged in a one-to-one correspondence, each second conductive structure extending from the first substrate to at least the second semiconductor layer of the corresponding light-emitting unit, and is electrically connected to the corresponding second semiconductor layer.

2. The pixel structure according to claim 1, characterized in that, The pixel unit further includes multiple connection units, each of which is configured in a one-to-one correspondence with the light-emitting unit. Each connection unit includes: a first connection structure, including a first connection electrode and a first connection trace, wherein within the same light-emitting unit, the first connection electrode is connected to the first semiconductor layer, and the first connection trace connects the first connection electrode to the first conductive structure; and a second connection structure, which is insulated from the first connection structure and includes a second connection electrode and a second connection trace, wherein within the same light-emitting unit, the second connection electrode is connected to the second semiconductor layer, and the second connection trace connects the second connection electrode to the corresponding second conductive structure.

3. The pixel structure according to claim 2, characterized in that, The first connecting electrode and / or the second connecting electrode are ring-shaped structures.

4. The pixel structure according to claim 2, characterized in that, The pixel structure further includes a first insulating layer, which is disposed between adjacent light-emitting units; the first connection trace and the second connection trace are located within the first insulating layer; the first connection electrode passes through the first insulating layer from within the first insulating layer toward the corresponding light-emitting unit and is connected to the corresponding first semiconductor layer; The second connection electrode passes through the first insulating layer from within the first insulating layer toward the corresponding light-emitting unit and is connected to the corresponding second semiconductor layer.

5. The pixel structure according to claim 1, characterized in that, The pixel structure further includes: a second insulating layer disposed on the side of the first substrate away from the light-emitting unit, wherein the first conductive structure and the plurality of second conductive structures penetrate the second insulating layer and are exposed from the second insulating layer.

6. The pixel structure according to any one of claims 1-5, characterized in that, The plurality of light-emitting units include a first light-emitting unit, a second light-emitting unit, and a third light-emitting unit that are stacked sequentially on a first substrate.

7. The pixel structure according to claim 6, characterized in that, The pixel structure further includes a second substrate, which is located between the second light-emitting unit and the third light-emitting unit.

8. The pixel structure according to claim 6, characterized in that, The pixel structure further includes a third substrate, which is located on the side of the third light-emitting unit away from the first substrate.

9. The pixel structure according to claim 8, characterized in that, The pixel structure further includes a microlens structure located on the side of the third substrate away from the third light-emitting unit.

10. A display chip, characterized in that, Includes the plurality of pixel structures as described in any one of claims 1-9.

11. The display chip according to claim 10, characterized in that, The display chip further includes a shallow trench isolation structure, which is located between each pixel unit.

12. A display device, characterized in that, include: The display chip according to any one of claims 10-11; a driver chip, located on one side of the display chip, and electrically connected to the display chip through the first conductive structure and the plurality of second conductive structures.

13. The display device according to claim 12, characterized in that, The display device further includes an adapter board located on the side of the driver chip away from the display chip and electrically connected to the driver chip.

14. A method for fabricating a display chip, characterized in that, A method for fabricating a display chip according to any one of claims 10-11 includes: providing a plurality of different light-emitting wafers, each light-emitting wafer including a substrate and an epitaxial layer grown on the substrate; defining light-emitting units in the epitaxial layer of each light-emitting wafer; forming a first via and a predetermined number of second vias in each light-emitting unit of each light-emitting wafer, wherein the first via and the second vias at least penetrate the epitaxial layer; filling the first via and the second via of each light-emitting wafer with conductive material; sequentially stacking and bonding the light-emitting wafers, wherein the conductive materials in the corresponding first vias and the conductive materials in the corresponding second vias are vertically interconnected and respectively form the first conductive structure and the second conductive structure; wherein the predetermined number of second vias is determined by the number m of the stacked light-emitting wafers, and in the vertical direction from bottom to top, the predetermined number of second vias in the sequentially stacked light-emitting wafers decreases sequentially from m to 1, where m≥2.

15. The method for fabricating a display chip according to claim 14, characterized in that, Defining light-emitting units in the epitaxial layer of each of the light-emitting wafers includes: etching at least the epitaxial layer of each of the light-emitting wafers to form shallow trenches, the shallow trenches isolating the epitaxial layer into a plurality of light-emitting units; and filling the shallow trenches of each of the light-emitting wafers with insulating material to form a shallow trench isolation structure.

16. The method for fabricating a display chip according to claim 14, characterized in that, Before sequentially stacking and bonding the light-emitting wafers, the method further includes: forming a first insulating layer on the side of the epitaxial layer of each light-emitting wafer away from the substrate, and forming a first connection structure and a second connection structure within the first insulating layer, wherein the first connection structure connects the conductive material in the first via and the first semiconductor layer, and the second connection structure connects the conductive material in the second via and the second semiconductor layer.

17. The method for fabricating a display chip according to claim 16, characterized in that, The first connection structure includes a first connection electrode and a first connection trace. The first connection electrode is connected to the first semiconductor layer, and the first connection trace is connected to the first connection electrode and the conductive material in the first through hole. The second connection structure includes a second connection electrode and a second connection trace. The second connection electrode is connected to the second semiconductor layer, and the second connection trace is connected to the conductive material in the corresponding second via. A method for forming the first connection structure and / or the second connection structure includes: forming an electrode window, wherein the electrode window of the first connection structure extends to the first semiconductor layer and the electrode window of the second connection structure extends to the second semiconductor layer; filling the electrode window with a conductive material to form the connection electrode; and forming the connection trace connecting the connection electrode.

18. The method for fabricating a display chip according to claim 17, characterized in that, The step of filling the electrode window with conductive material to form a connecting electrode includes: forming an ohmic contact material at the bottom of the electrode window; and forming an electrode material in the remaining space of the electrode window.

19. The method for fabricating a display chip according to claim 17, characterized in that, The first connecting electrode and / or the second connecting electrode are ring-shaped structures.

20. The method for fabricating a display chip according to claim 14, characterized in that, After stacking and bonding the light-emitting wafers in sequence, the method further includes: thinning the substrate of the bottom light-emitting wafer so that the first conductive structure and the second conductive structure are exposed and protrude relative to the substrate of the bottom light-emitting wafer; forming a second insulating layer on the substrate surface, the surface of the first conductive structure and the surface of the second conductive structure of the thinned bottom light-emitting wafer; and etching the second insulating layer to expose the first conductive structure and the second conductive structure.

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