Thin film device having high pixel density, photosensitive apparatus, and display apparatus

Abstract

Disclosed are a thin film device having high pixel density, a photosensitive apparatus, and a display apparatus. The thin film device comprises: a bottom metal electrode array formed on a backplane; a dense and pinhole-free metal compound thin film layer passivated on a free surface of a bottom metal electrode to completely cover the bottom metal electrode; a metal compound thin film layer located on an upper surface of the bottom metal electrode, which is a P-type or N-type semiconductor, and forms ohmic contact with the upper surface of the bottom metal electrode; and a continuous / non-patterned active layer, a continuous / non-patterned upper charge transport layer, a continuous / non-patterned top metal electrode, and a continuous / non-patterned transparent encapsulation layer which are sequentially formed on the metal compound thin film layer from bottom to top. According to the present invention, by passivating a metal compound thin film layer wrapping the bottom metal electrode, the problem of current leakage between adjacent pixels caused by an excessively small spacing between two adjacent patterned bottom metal electrodes is avoided, thereby improving image clarity.

Description

A thin-film device, photosensitive device, and display device with high pixel density. Technical Field

[0001] This invention relates to the field of optoelectronic device technology, and more specifically, to a thin-film device, a photosensitive device, and a display device with high pixel density. Background Technology

[0002] Infrared photodetectors and imaging arrays hold immense application potential in artificial intelligence, machine vision, 3D integrated circuit chip fabrication and online inspection, health monitoring, and biometric detection. However, existing infrared photodetectors made from inorganic semiconductor crystal materials (such as Ge and InGaAs) suffer from high dark current and low detectivity at room temperature. Photodetectors and imaging arrays based on these materials require active cooling to reduce thermal noise, especially for applications with low light intensity. However, the size and power consumption of currently used thermoelectric coolers prevent their use in battery-powered portable applications.

[0003] The photoelectric imaging arrays used in infrared cameras require high-purity, large-size semiconductor crystals with low defect density, fabricated into PIN structures. Then, image elements are photolithographically formed to create a sensor array. Pixel formation involves deep trench etching of the PIN structure at the pixel scale, post-surface treatment, encapsulation passivation, and bonding to a CMOS-based readout circuit integrated array on a silicon wafer. These processes limit pixel size, total pixel count, and manufacturing yield, thus limiting system cost. Furthermore, imperfections in the etching process and post-passivation can lead to charge trapping in the semiconductor bandgap, further limiting device performance and manufacturing yield.

[0004] In contrast, thin-film photodetectors based on organic semiconductors offer new opportunities for wearable electronics and image sensing due to their excellent mechanical flexibility, tunable bandgap, and direct integration onto CMOS integrated circuit wafers. Furthermore, organic semiconductors possess high light absorption coefficients (typically >10). 5 cm 2 With moderate carrier mobility and low charge trap density in the bandgap, these characteristics enable low-cost, large-area, high-pixel-count thin-film optical displays or thin-film optical detection image arrays without the need for patterning of the active layer (G. Yu et al., “Large-area full-color image sensors made of semiconductor polymers”, Adv. Materials 10, 1431 (1998)).

[0005] Whether this simple array structure with an unpatterned active layer can be used in image arrays with small pixel pitch and photosensitive (or light-emitting) arrays in PIN structures remains to be investigated. This is because the unpatterned lower charge transport layer between the active layer and the patterned bottom metal electrode can cause current leakage between adjacent pixels. This leakage can lead to image blurring and reduced image contrast when the pixel pitch is too small.

[0006] Therefore, it is necessary to pattern the lower charge transport layer on a patterned bottom metal electrode. However, when the pixel pitch is reduced to the micrometer or submicrometer level, aligning this patterned lower charge transport layer pattern with the bottom metal electrode pattern becomes challenging, especially in image arrays with a total number of pixels exceeding one million (often referred to as megapixel focal plane arrays). Summary of the Invention

[0007] In order to solve the problem of current leakage between adjacent pixels caused by the unpatterned lower charge transport layer between the active layer and the patterned bottom metal electrode in the prior art, the present invention provides a thin film device, photosensitive device and display device with high pixel density.

[0008] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0009] A thin-film device with high pixel density, the thin-film device comprising:

[0010] A bottom metal electrode array is formed on the back plate;

[0011] A dense, pinhole-free metal compound thin film is passivated on the free surface of the bottom metal electrode in the bottom metal electrode array to completely cover the bottom metal electrode;

[0012] The metal compound thin film layer located on the upper surface of the bottom metal electrode is a P-type or N-type semiconductor and forms an ohmic contact with the upper surface of the bottom metal electrode.

[0013] A continuous / unpatterned active layer, a continuous / unpatterned upper charge transport layer, a continuous / unpatterned top metal electrode, and a continuous / unpatterned transparent encapsulation layer are formed sequentially from bottom to top on a metal compound thin film layer.

[0014] Preferably, a dense, pinhole-free metal compound thin film layer is passivated on the free surface of the bottom metal electrode in the bottom metal electrode array, including: forming a dense, pinhole-free metal compound thin film layer by performing a surface chemical reaction on the free surface of the bottom metal electrode using a self-aligned process.

[0015] Furthermore, the surface chemical reaction includes one or more combinations of anodic oxidation, oxygen plasma oxidation, high-temperature thermal oxidation, chemical oxidation, and sulfidation.

[0016] Furthermore, the specific process steps of the anodizing are as follows:

[0017] After fabricating a bottom metal electrode array for multiple thin-film devices on a wafer,

[0018] Clean the free surface of the bottom metal electrode;

[0019] The bottom metal electrode array on the wafer is immersed in a non-strong acid anodic oxidation solution;

[0020] First, a metal compound thin film layer is formed under a constant current until the thickness of the metal compound thin film layer reaches the voltage corresponding to the target thickness;

[0021] Then maintain the voltage corresponding to the target thickness, and continue at a constant voltage until the oxidation current decreases to a certain threshold of the constant current, thus ending the anodizing process.

[0022] Preferably, when the bottom metal electrode is a metal layer, the metal compound thin film layer passivated on the upper surface and sidewalls of the metal layer is a P-type or N-type semiconductor;

[0023] When the bottom metal electrode consists of two or more metal layers, the metal compound thin film layer passivated on the upper surface of the top metal layer is a P-type or N-type semiconductor; the metal compound thin film layer passivated on the sidewalls of the remaining metal layers is an insulating layer, or a P-type semiconductor, or an N-type semiconductor.

[0024] Preferably, the thickness of the metal compound thin film layer is 5 nm to 100 nm.

[0025] Furthermore, the thickness of the metal compound thin film layer is 10 nm - 50 nm.

[0026] Preferably, the average surface roughness of the metal compound thin film layer is less than 5 nm.

[0027] Furthermore, the average surface roughness of the metal compound thin film layer is less than 3 nm.

[0028] Preferably, the carrier concentration of the metal compound thin film layer is in the range of 10. 15 cm -3 -10 20 cm -3 .

[0029] Furthermore, the carrier concentration range of the metal compound thin film layer is 10. 16 cm -3 -10 19 cm -3 .

[0030] Preferably, the bandgap of the metal compound thin film layer is larger than the bandgap of the active layer.

[0031] Preferably, when the metal compound thin film layer is P-type, the material of the metal compound thin film layer includes oxides or sulfides of Cu, Cr, Ni, V, Ga, W, Zr or Mo, or oxides or sulfides of their metal alloys.

[0032] Preferably, when the metal compound thin film layer is N-type, the material of the metal compound thin film layer includes oxides of Ti, Ta, Zn, In, Sn, Mg, Hf, Nd, or Nb, or oxides of their metal alloys.

[0033] Preferably, it further includes adding a surface-promoting material between the metal compound thin film layer and the active layer to improve adhesion and reduce surface defects at the interface.

[0034] Preferably, the active layer comprises an organic semiconductor in the form of a single-phase film or a D / A bulk heterojunction blend film, an inorganic semiconductor or compound semiconductor in the form of single-phase or quantum dot nanoparticles, or a combination thereof in a mixed form or a thin film stack; wherein, D represents an organic molecule of electron donor; and A represents an organic molecule of electron acceptor;

[0035] The inorganic semiconductors include Si, Ge, SiGe, and CuInS in crystalline or polycrystalline forms. x Se 2-x Nanoscale quantum dots or nanoscale quantum films, or single-phase films of CuInGa(S,Se), PbS, PbI2, PBI3, and InGaAs (0≤x≤2);

[0036] The organic semiconductor comprises an organic blend of one or more organic molecules that serve as electron donors (D) and one or more organic molecules that serve as electron acceptors (A), forming an organic blend of D / A.

[0037] A photosensitive device includes a backplate with multiple pixel readout circuits integrated inside, and a thin-film device with high pixel density disposed on the backplate.

[0038] The active layer serves as a photosensitive layer, used to detect light incident on the photosensitive device;

[0039] Each of the pixel readout circuits is connected to a corresponding bottom metal electrode via a metal post.

[0040] A display device includes a backplate with multiple pixel driving circuits integrated inside, and a thin-film device with high pixel density disposed on the backplate.

[0041] The active layer serves as a light-emitting layer, used to generate light for luminescence display;

[0042] Each of the pixel driving circuits is connected to a corresponding bottom metal electrode via a metal post.

[0043] Compared with the prior art, the beneficial effects of the present invention are:

[0044] This invention passivates the free surface of each bottom metal electrode in the bottom metal electrode array with a dense, pinhole-free metal compound thin film to completely cover the bottom metal electrode; and the metal compound thin film layer forms an ohmic contact with the bottom metal electrode. Because the bottom metal electrode is wrapped by the passivated metal compound thin film layer, the problem of current leakage between adjacent pixels caused by excessively small spacing between two patterned adjacent bottom metal electrodes is avoided, thereby improving sharpness and achieving low pixel signal crosstalk. Attached Figure Description

[0045] Figure 1 is a schematic diagram of the passivation of a metal compound thin film layer on the bottom metal electrode according to the present invention.

[0046] Figure 2 is a schematic diagram of the structure of the device provided by the present invention.

[0047] Figure 3 is a schematic diagram of the bottom metal electrode with two metal layers in this invention.

[0048] Figure 4 is a schematic diagram of the structure of the metal compound thin film layer formed by passivation of the bottom metal electrode in Figure 3.

[0049] Figure 5 shows a typical pixel readout circuit for passive detection pixels (PPS).

[0050] Figure 6 shows a typical pixel readout circuit for active detection pixels (APS).

[0051] Figure 7 is a schematic diagram of the driver reset line integrated circuit provided by the present invention.

[0052] Figure 8 is a schematic diagram of the driver reset line integrated circuit provided by the present invention.

[0053] Figure 9 is a schematic diagram of the silicon wafer provided by the present invention.

[0054] Figure 10 shows a typical pixel driving circuit of the display device of the present invention.

[0055] Figure 11 is a schematic diagram of the circuit density changing with time under constant voltage according to the present invention.

[0056] Figure 12 is a structural schematic diagram of a vehicle provided by the present invention.

[0057] Figure 13 is a structural schematic diagram of another vehicle provided by the present invention.

[0058] Figure 14 is an image without pixel signal crosstalk provided by the present invention.

[0059] Figure 15 is an image with pixel signal crosstalk provided by the present invention.

[0060] In the diagram, 100-backplane, 1001-substrate, 1002-pixel readout circuit, 1003-planarization layer, 1004-metal post, 200-bottom metal electrode, 2001-first electrode layer, 2002-second electrode layer, 300-metal compound thin film layer, 400-active layer, 500-upper charge transport layer, 600-top metal electrode, 700-encapsulation layer, 800-silicon wafer, 801-contact pad, 900-thin film device, 110-carrier, 120-stainless steel, 130-slot. Detailed Implementation

[0061] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0062] It should be understood that, when used in this specification, the terms “comprising” and “including” indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0063] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to include the plural forms.

[0064] It should also be further understood that the term "and / or" as used in this specification refers to any combination of one or more of the associated listed items, as well as all possible combinations, and includes such combinations.

[0065] The term "bulk heterojunction structure" in this invention refers to an interpenetrating network structure with nanoscale phase separation formed by blending donor and acceptor materials.

[0066] In this invention, the term "donor material" refers to a P-type semiconductor material.

[0067] In this invention, the term "receptor material" refers to an N-type semiconductor material.

[0068] In this invention, the term "I-semiconductor material" refers to an undoped intrinsic semiconductor material. The term "bandgap" in this invention refers to the optical bandgap of a semiconductor material, the value of which (in electron volts) can be obtained by dividing 1240 by the cutoff wavelength (in nanometers) of the semiconductor material's absorption edge.

[0069] In this invention, the term "active layer" refers to a thin film layer in a device structure that has photoelectric or electro-optic activity.

[0070] In this invention, the term "photosensitive layer" refers to a thin film layer in a device structure that is responsible for absorbing photons and generating free electrons and holes.

[0071] In this invention, the term "light-emitting layer" refers to a thin film layer in the device structure that converts injected free electrons and holes into photons.

[0072] In this invention, the term "AFM" refers to atomic force microscope.

[0073] Generally, in metal-semiconductor-metal (MSM) thin-film devices, only the bottom metal electrode is patterned, and a continuous active layer and top metal electrode layer are used. The pixel size and pixel pitch of such thin-film devices can be defined by the bottom metal electrode. However, whether this thin-film device structure with an unpatterned active layer can be used in imaging devices with small pixel pitch and photosensitive (or light-emitting) devices with PIN structures remains to be investigated. The unpatterned doped metal compound thin film layer between the active layer and the patterned bottom metal electrode can cause current leakage between adjacent pixels. This leakage can lead to image blurring and reduced image contrast when the pixel pitch is too small.

[0074] Therefore, patterning of a metal compound thin film layer is performed on top of a patterned bottom metal electrode, especially for image array devices with small pixel pitch and narrow spaces between adjacent pixels. When the pixel pitch decreases to the micrometer or sub-micrometer level, aligning the pattern of the metal compound thin film layer with the bottom metal electrode pattern becomes a challenge, particularly in large-size image array devices with more than one million pixels (commonly referred to as megapixel focal plane array devices). Furthermore, the metal compound thin film layer is needed to encapsulate the entire free surface (top surface and sidewalls) of the bottom metal electrode to eliminate current leakage between adjacent pixels caused by adjacent bottom metal electrodes.

[0075] Therefore, as shown in Figures 1 and 2, the present invention provides a thin-film device with high pixel density, the thin-film device comprising:

[0076] A bottom metal electrode array is formed on the back plate 100;

[0077] A dense, pinhole-free metal compound thin film layer 300 is passivated on the free surface of the bottom metal electrode 200 in the bottom metal electrode array to completely cover the bottom metal electrode 200.

[0078] The metal compound thin film layer 300 located on the upper surface of the bottom metal electrode 200 is a P-type or N-type semiconductor and forms an ohmic contact with the upper surface of the bottom metal electrode 200.

[0079] A continuous / unpatterned active layer 400, a continuous / unpatterned upper charge transport layer 500, a continuous / unpatterned top metal electrode 600, and a continuous / unpatterned transparent encapsulation layer 700 are formed sequentially from bottom to top on the metal compound thin film layer 300.

[0080] This invention provides a thin-film device with a high pixel density and small pixel pitch, featuring a PIN pixel structure. The bottom metal compound thin film layer (P-type or N-type) is encapsulated on the free surface of a bottom metal electrode 200 using a self-patterning fabrication process. The free surface of the bottom metal electrode 200 includes an exposed upper surface and sidewalls. This patterned metal compound thin film layer 300 is formed by a surface chemical reaction (e.g., surface oxidation) on the exposed free surface of the bottom metal electrode 200. The upper surface and surrounding sidewalls of the bottom metal electrode 200 are encapsulated by the metal compound thin film layer 300, which acts as a pixel isolation structure, separating adjacent pixels and effectively suppressing signal crosstalk between adjacent pixels, thereby significantly improving pixel density. Therefore, leakage caused by defects in traditional thin-film device pixels and current leakage between adjacent pixels are greatly suppressed. This invention achieves large-size thin-film devices with high pixel density, millions of pixels, and PIN sensing elements through a single photolithography step on the bottom metal electrode. This eliminates the alignment problems introduced by multi-layer photolithography for large-area array fabrication, thus resulting in a very high manufacturing yield. In addition to serving as a photosensitive layer, when the active layer uses a light-emitting material, the thin-film device becomes a display device.

[0081] Example 1

[0082] This embodiment uses a photosensitive device as an example for detailed description. As shown in Figures 1 and 2, a photosensitive device with high pixel density includes:

[0083] Backplane 100 with multiple pixel readout circuits integrated internally;

[0084] A thin-film device with high pixel density disposed on a backplate 100, the thin-film device specifically comprising: forming a bottom metal electrode array consisting of a plurality of bottom metal electrodes 200 on the backplate;

[0085] A dense, pinhole-free metal compound thin film layer 300 is passivated on the free surface of the bottom metal electrode 200 in the bottom metal electrode array to completely cover the bottom metal electrode 200.

[0086] The metal compound thin film layer 300 located on the upper surface of the bottom metal electrode 200 is a P-type or N-type semiconductor and forms an ohmic contact with the upper surface of the bottom metal electrode 200.

[0087] A continuous / unpatterned photosensitive layer, a continuous / unpatterned upper charge transport layer 500, a continuous / unpatterned top metal electrode 600, and a continuous / unpatterned transparent encapsulation layer 700 are formed sequentially from bottom to top on the metal compound thin film layer 300.

[0088] Each of the pixel readout circuits 1002 is connected to a corresponding bottom metal electrode 200 via a metal post 1004.

[0089] In this embodiment, the photosensitive layer is used to detect light incident on the photosensitive device. The metal compound thin film layer located on the upper surface of the bottom metal electrode 200 serves as the lower charge transport layer, forming a PIN junction or a NIP junction with the photosensitive layer and the upper charge transport layer, respectively.

[0090] Figure 2 shows a cross-sectional view of the entire photosensitive device. The backplane 100 can be made of various insulating materials or high-resistivity semiconductor materials, and can have either a flat surface or a curved surface of a specific shape. Besides inorganic semiconductor wafer materials, the backplane 100 can also be glass, ceramic, or plastic. For photosensitive devices used for image sensing, multiple pixel readout circuits 1002 are integrated on the backplane 100. For high-pixel-density photosensitive devices, the pixel readout circuits 1002 are typically fabricated on the upper surface of a single-crystal silicon wafer using CMOS technology. For medium- and low-photosensitive pixel-density photosensitive devices, the backplane 100 can integrate CMOS field-effect transistor or thin-film transistor (TFT) pixel readout circuits 1002. For ultra-large-scale and high-photosensitive pixel-density image arrays, the pixel readout circuits 1002 on the backplane 100 can be fabricated using CMOS field-effect transistors (MOSFETs, or FETs). For the pixel readout circuit 1002 fabricated on a single-crystal silicon wafer using CMOS integrated circuit technology, it can be connected to a corresponding bottom metal electrode 200 via a metal post 1004. The metal post 1004 and the planarization layer 1003 can be fabricated using conventional silicon wafer back-end fabrication materials and processes. Besides using silicon wafer back-end fabrication processes, the metal post 1004 and the planarization layer 1003 can also be fabricated using corresponding processes in thin-film transistor (TFT) backplane fabrication. Specifically, above the pixel readout circuit 1002 of a CMOS field-effect transistor or thin-film transistor (TFT), the planarization layer 1003 can be formed using inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride via vapor deposition. The planarization layer 1003 can also be made using photolithographically patternable organic insulating materials (such as photolithographically patternable polyimide films or photolithographically patternable polyacrylate films). The planarization layer 1003 can also be achieved by stacking the aforementioned inorganic and organic insulating materials. When using this preparation method, the metal post 1004 does not need to be prepared separately and can be achieved simultaneously when preparing the bottom metal electrode.

[0091] The device structure shown in Figure 2 in this embodiment allows the photosensitive pixels (200-600 stacked structure) to be vertically superimposed with the pixel readout circuit 1002 below, which is commonly referred to as a three-dimensional circuit. This design can effectively reduce the pixel size, thereby increasing the pixel density.

[0092] In this embodiment, the upper surface of the backplate 100 is a metal thin film array, commonly referred to as a bottom metal electrode array, which includes multiple bottom metal electrodes 200. Its thickness can be selected in the range of 50 nm to 500 nm according to the reflectivity requirements of the photosensitive layer. Commonly used metal materials for the bottom metal electrodes include, but are not limited to, Ta, Ti, Ni, Cr, Cu, Al, Mg, V, Ga, Zr, Zn, Sn, Hf, Nb, W, or Mo, or their metal alloys.

[0093] Below each bottom metal electrode 200, a metal plug 1004 connects it to the pixel readout circuit 1002. This structure allows the photosensitive pixel (also called a photosensitive pixel) to be vertically superimposed on the pixel readout circuit 1002 below, which is commonly referred to as a three-dimensional circuit. This design can effectively reduce the pixel size, thereby increasing the pixel density.

[0094] In this embodiment, the bottom metal electrode 200 has a smooth surface. In AFM testing, the surface roughness of the bottom metal electrode 200 is typically less than 5 nm. Achieving such a smooth top surface requires appropriate deposition methods and process conditions. Commonly used deposition methods include DC, RF, or pulsed sputtering deposition, electron beam deposition, ion beam-assisted deposition, or thermal deposition. However, compared to process conditions used for high conductivity applications (high deposition rates at high temperatures), the high smoothness surface of the bottom metal electrode 200 in this embodiment can be achieved on a low-temperature backplane 100 and at medium or low deposition power. If necessary, the deposition rate can also be varied from high to low during deposition to optimize the surface smoothness of the bottom metal electrode 200. Since the total thickness of the bottom metal electrode 200 is in the nanometer (nm) range, the fabrication method of the bottom metal electrode 200 provided by this invention meets the capacity requirements and manufacturability needed for mass production. Within the operating spectral band, the thickness of the bottom metal electrode 200 provides sufficient optical reflectivity.

[0095] Generally, for photosensitive devices with large size or large pixel pitch, such as a bottom metal electrode array with a spacing greater than 20 μm between two bottom metal electrodes 200, a shadow mask can be placed in front of the backplate 100 during the deposition process. Then, a patterned metal layer is formed using photolithography, a process well-known in the field of thin film device fabrication, to form a bottom metal electrode array consisting of several bottom metal electrodes 200.

[0096] Commonly used photolithography processes, such as wet etching or dry etching, are typically used to form the desired electrode patterns. For example, dry etching is commonly used to pattern Ta, Ti, or Ni thin films. Wet etching is commonly used to pattern Cr, Cu, Al, V, W, or Mo thin films. For metal layers that can be patterned using either wet or dry etching, dry etching is typically used to achieve better dimensional control, especially at the sub-micron level. For large-area megapixel imagers or microdisplay arrays with micron or sub-micron gaps between adjacent pixels, dry etching can achieve pixel pitches of less than 1 micrometer.

[0097] In one specific embodiment, a dense, pinhole-free metal compound thin film layer 300 is passivated on the free surface of the bottom metal electrode 200 in the bottom metal electrode array, including: forming a dense, pinhole-free metal compound thin film layer 300 by performing a surface chemical reaction on the free surface of the bottom metal electrode 200 using a self-aligned process.

[0098] In this embodiment, a dense, pinhole-free metal compound thin film layer is formed on the free surface of the high-density, small-sized pixel bottom metal electrode 200, as shown in Figure 1. The metal compound thin film layer 300 is grown on the free surface of each bottom metal electrode 200. The free surface of the bottom metal electrode array 200 refers to all surfaces (including the top surface and sidewalls) of each bottom metal electrode 200 exposed to air after the patterned metal layer is formed.

[0099] In this embodiment, the surface chemical reaction includes one or more combinations of anodic oxidation, oxygen plasma oxidation, high-temperature thermal oxidation, chemical oxidation, and sulfidation.

[0100] Compared to the various defects easily formed during photolithography patterning, the metal compound thin film layer 300 formed by surface chemical processing is dense and free of pinhole defects. Furthermore, the pattern of this surface chemical reaction-generated metal compound thin film layer is automatically aligned with the underlying bottom metal electrode pattern, eliminating the need for the mask alignment process in traditional photolithography; that is, the pattern of the metal compound thin film layer 300 and the pattern of the bottom metal electrode array 200 are self-aligned. This method of forming the metal compound thin film layer 300 on the bottom metal electrode 200 through surface chemical reaction can effectively fabricate photosensitive devices with small pixel pitch and high pixel density.

[0101] In this embodiment, the thickness of the metal compound thin film layer 300 can be controlled by the process parameters used in the surface chemical reaction. For array devices containing PIN sensing elements, the thickness of the metal compound thin film layer 300 is typically set to 5 nm-100 nm. Preferably, the thickness of the metal compound thin film layer 300 is 10-50 nm. If the average surface roughness of the metal compound thin film layer 300 is relatively large, it will cause pinholes, shorten the device, and form bright pixel defects in the photosensitive layer 400 formed on the metal compound thin film layer 300, thus hindering the formation of a high-quality photosensitive layer 400. Therefore, the average surface roughness of the metal compound thin film layer 300 is less than 5 nm, preferably less than 3 nm. This invention enables photosensitive devices with millions of pixels through its dense, pinhole-free characteristics and high uniformity over a large device area. This invention has the advantages of high process yield and no pixel short circuits.

[0102] In this embodiment, the surface chemical reaction specifically includes anodic oxidation, oxygen plasma surface treatment at room temperature or high temperature, chemical oxidation in air and oxygen-rich environments, humid air at room temperature or high temperature, and chemical oxidation using oxidants (such as H2O2, hot water at 85°C-100°C), or a combination of the above processes. In addition to oxidation on the free surface of each bottom metal electrode 200, sulfidation (e.g., treatment with H2S) can also be performed on the free surface of each bottom metal electrode 200. Therefore, a metal sulfide or metal sulfate thin film layer can also be formed by reacting the bottom metal electrode with a corresponding reactant.

[0103] In a specific embodiment, when the bottom metal electrode 200 is a metal layer, the metal compound thin film layer passivated on the upper surface and sidewalls of the metal layer is a P-type or N-type semiconductor.

[0104] In this embodiment, when the bottom metal electrode is a single metal layer, the metal compound thin film layer passivated on the bottom metal electrode is an oxide or sulfide of the corresponding metal. In this case, the metal compound thin film layer can be a P-type or N-type semiconductor, serving as the lower charge transport layer and forming a PIN or NIP structure with the photosensitive layer and the upper charge transport layer. It should be noted that Al cannot be used as the bottom metal electrode in this case because the aluminum oxide formed after Al oxidation is an insulator, not a semiconductor. Since the encapsulated metal compound thin film layer is a semiconductor, its conductivity is much lower than that of the bottom metal electrode, thus effectively suppressing current leakage between adjacent pixels and avoiding pixel signal crosstalk.

[0105] When the bottom metal electrode consists of two or more metal layers, the metal compound thin film layer passivated on the upper surface of the top metal layer is a P-type or N-type semiconductor; the metal compound thin film layer passivated on the sidewalls of the remaining metal layers is an insulating layer, or a P-type semiconductor, or an N-type semiconductor.

[0106] It should be noted that, except for the topmost metal layer which cannot be made of Al, all other metal layers can be made of Al. The advantage of using Al for the other metal layers is that the aluminum oxide or aluminum sulfide formed by oxidizing or sulfiding Al is an insulator, which can completely suppress current leakage between adjacent pixels and avoid crosstalk between adjacent pixel signals.

[0107] In this embodiment, the metal compound thin film layer 300 can be fabricated as P-type or N-type. When the metal compound thin film layer 300 is a P-type semiconductor layer, the material of the metal compound thin film layer 300 includes oxides or sulfides of Cu, Cr, Ni, V, Ga, W, Zr, or Mo, or oxides or sulfides of their metal alloys. When the metal compound thin film layer is an N-type semiconductor layer, the material of the metal compound thin film layer includes oxides of Ti, Ta, Zn, In, Sn, Mg, Hf, Nd, or Nb, or oxides of their metal alloys.

[0108] In a specific embodiment, a patterned bottom metal electrode and a metal compound thin film layer (shown as 200 and 300 in Figure 1) with strong light reflection within the operating spectral range are preferred. Generally, this can be achieved by controlling the thickness of the appropriate metal material or metal compound thin film layer. For example, titanium (Ti) exhibits strong reflectivity over a wide spectral range of visible and infrared light. A TiO2-x layer is formed on the bottom metal electrode prepared using titanium (Ti) through a surface chemical reaction. Due to the strong optical resonant cavity effect formed on the upper and lower surfaces of the TiO2-x layer, the Ti / TiO2-x bilayer film can exhibit maximum reflectivity in certain spectral ranges, which can be used to optimize the photosensitivity of the photosensitive device at a specific operating wavelength. In addition to titanium (Ti), metals with high optical reflectivity in the ultraviolet, visible, and infrared spectral ranges include aluminum, magnesium, and copper.

[0109] In this embodiment, Ta2O 5-x TiO 2-x These are N-type metal compound semiconductor thin films with a Fermi level of approximately -4 eV. Their Fermi level can be tuned by doping with magnesium, aluminum, zinc, tin, or copper to form an alloy compound thin film layer. In this metal oxide thin film layer, interstitial metals and oxygen vacancies provide additional electrons, which act as the primary charge carriers. The carrier concentration can be controlled by surface chemical reaction conditions or by annealing the generated (bottom metal electrode 200 / metal compound thin film layer 300) array under different partial pressures of O2 and H2O in N2 or air. The concentration of the doped metal compound component determines the carrier concentration. The carrier concentration range of the metal compound thin film layer 300 can be within 10 eV. 15 cm -3 -10 20 cm -3 Internal regulation; preferably, when the metal compound thin film layer is an N-type semiconductor layer, its carrier concentration is preferably 10. 16 cm -3 -10 19 cm -3The carrier concentration can be adjusted within a certain range. Besides Ti and Ta, metal compound thin films of N-type semiconductors can also be formed by surface reactions of metals including Zn, Mg, Hf, or Nb, or metal alloys thereof. The carrier concentration of metal compound thin films of P-type semiconductors is typically in the range of 10. 16 cm -3 -10 19 cm -3 Within the range.

[0110] In this embodiment, the optical and electrical properties of the bottom metal electrode and the metal compound thin film layer can be further optimized by designing a stacked metal structure with two or more bottom metal electrodes. As shown in Figure 3, the bottom metal electrode 200 includes a first electrode layer 2001 and a second electrode layer 2002, which are made of Al and Ti thin films, respectively. The patterned bottom metal electrode 200, including the first electrode layer 2001 and the second electrode layer 2002, can be achieved by one-step photolithography. The double-layer bottom metal electrode is subjected to a surface oxidation process to form a patterned metal compound thin film layer 300, the cross-section of which is shown in Figure 4.

[0111] In this embodiment, the metal compound thin film layer 300 formed by the surface oxidation process comprises two parts: (1) a TiO2-x thin film layer 3002 located on the top and sidewalls of the Ti electrode layer; and (2) an Al2O3 thin film layer 3001 surrounding the sidewalls of the Al electrode layer, wherein the Al2O3 is insulating. This double-layer bottom metal electrode design not only optimizes the optical reflection of the upper photosensitive layer, thereby optimizing the sensing spectrum range of the PIN sensing element, but also provides highly insulating Al2O3 encapsulation (sometimes referred to as a passivation layer) for the sidewalls of the bottom metal electrode, thereby eliminating leakage current (commonly referred to as crosstalk) between adjacent pixels. It should be noted that this innovative structural design and molding process disclosed in this invention is applicable to active functional elements of electronic arrays with vertical PIN structures, whose pixel size can be as small as micrometers and the gap between adjacent pixels can be as small as submicrometers; that is, close to the optical wavelength of light detection or emission.

[0112] In this embodiment, one characteristic of the inorganic metal oxide formed by the surface reaction is that the Fermi level of the inorganic metal oxide is close to that of its corresponding pure metal. This invention achieves optimized Fermi level for obtaining a metal compound thin film layer 300 by anolyzing a bottom metal electrode structure composed of two or more electrode layers with different work functions.

[0113] For example, the Fermi level of TiO2-x is approximately -4.1 eV, while that of Al is approximately -3.7 eV. For Ti and Al electrode layer structures, a target Fermi level between -3.7 eV and -4.1 eV can be achieved through appropriate stacking design. For instance, an oxide Ti-Al-O alloy can be realized by anodizing a Ti (x nm) / Al (y nm) / Ti (100 nm) bottom metal electrode structure. When anodizing enters or passes through the Al electrode layer and into the next Ti electrode layer, the target alloy oxide can be achieved by adjusting the thickness of Ti (x nm) / Al (y nm) and the anodizing depth in the next Ti layer. Similarly, alloy metal oxides with a Fermi level of -3.5 eV (using Ti-Mg or Ta-Al structures) or a Fermi level in the range of -4.1 to -4.4 eV (using Ti-Sn, Ti-Ni, or Ti-Cu structures) can also be achieved.

[0114] In one specific embodiment, the bandgap of the metal compound thin film layer is greater than the bandgap of the active layer.

[0115] Taking TiO2-x as an example, TiO2-x is an N-type semiconductor with a bandgap of approximately 3.1 eV (light absorption begins at 400 nm). The Fermi level of TiO2-x is ~4.1 eV, close to the bottom of the conduction band on the surface of pure titanium. This wide-gap N-type oxide semiconductor can effectively pull photogenerated electrons out of the active layer, but it blocks photogenerated holes at the TiO2-x / I layer interface.

[0116] For dark current, under low reverse bias or zero bias, the blocking holes in the I layer at the NI interface and the blocking electrons at the IP interface further reduce the dark current.

[0117] The metal compound thin film obtained by the surface oxidation process provided by this invention is very thin (typically in the range of 5-100 nm), dense, and free of pinhole defects. It should be particularly noted that the anodizing process provided by this invention differs from the anodizing process used in the metal corrosion protection industry. In the metal corrosion protection industry, high-power-density, strong electrolyte, and high-temperature reaction conditions under heating or self-heating are typically employed; however, the metal oxide layer formed by this method has a porous structure, high surface roughness, and an oxidation thickness typically of 10-100 micrometers, with a surface roughness exceeding micrometers.

[0118] Specifically, the specific steps of the anodizing process provided by this invention are as follows:

[0119] After fabricating a bottom metal electrode array for multiple thin-film devices on a wafer,

[0120] First, clean the free surface of the bottom metal electrode;

[0121] The bottom metal electrode array on the silicon wafer is immersed in a non-strong acid anodizing solution (usually using mild electrolytes such as organic acids or salts) and anodized at low temperature. Specifically:

[0122] First, a metal compound thin film layer is formed under a constant current until the thickness of the metal compound thin film layer reaches the voltage corresponding to the target thickness; this process is called film formation.

[0123] Then maintain the voltage corresponding to the target thickness at a constant voltage until the oxidation current decreases to a certain threshold (e.g., 1%) of the constant current; this process is the sealing process; the anodizing process ends.

[0124] In this embodiment, the anodizing process can be maintained at a low temperature (0-25°C) by circulating the anodizing solution and controlling the temperature. The anodizing solution is also an electrolyte solution.

[0125] The rate of anodizing can be adjusted by changing the electrolyte solution concentration and the current density of a constant current.

[0126] In addition to sealing with a constant voltage (the current density of anodizing drops by 2-3 orders of magnitude from the initial constant current used in the film formation process), other oxidation processes can be combined, such as surface O2 plasma treatment, thermal annealing, and surface oxidation with oxidants, to further improve sealing performance and the quality of the oxide film.

[0127] This invention achieves self-aligned formation of a metal compound thin film layer on the bottom metal electrode through the aforementioned oxidation process. As shown in Figures 1 and 2, the bottom metal electrode array 200 is constructed on top of the pixel readout circuit 1002. Figure 5 shows a typical pixel readout circuit for passive detection pixels (PPS). Figure 6 shows a typical pixel readout circuit for active detection pixels (APS). The positions marked with "*" are the bottom metal electrodes of each pixel in the photosensitive device, which are blocked by the channel of the CMOS field-effect transistor T1 in the pixel readout circuit, and therefore cannot be directly connected from the edge of the device.

[0128] This invention uses existing pixel readout circuits and applies an anode voltage to the bottom metal electrode (*) of each pixel by appropriately connecting the corresponding CMOS field-effect transistors to achieve anodizing of the bottom metal electrode of each pixel, thereby forming a self-patterned metal compound thin film layer.

[0129] This embodiment uses a CMOS pixel readout circuit on a silicon wafer as an example (the same applies to pixel readout circuits composed of thin-film field-effect transistors (TFTs) on glass or plastic substrates) to explain in detail the wiring method for connecting each photosensitive device to the edge of the silicon wafer.

[0130] As shown in Figures 5 and 6, the power lines “Vdd” and “Vss” reach the edge check / test point of each photosensitive element. Furthermore, the signal lines “Select”, “Vdata”, and “Reset” for each pixel are also accessible near the boundary of each photosensitive element. With these lines fully integrated with the external drive circuitry or signal acquisition circuitry of the photosensitive element, a simple “MUX” circuit can be integrated at the outer edge of the device for anodizing process purposes, as shown in Figures 7 and 8. Figure 7 shows the connection circuitry for a passive detection pixel (PPS) array. Figure 8 shows the connection circuitry for an active detection pixel (APS) array. When contacts “A”, “B”, “A”, and “B” in Figure 7 are connected together to the positive electrode of the anodizing power supply, all field-effect transistors in the MUX circuit and the field-effect transistors in the readout circuit of each PPS pixel are turned on. The bottom metal electrode "*" of each pixel is connected to the high potential (i.e., the anodic potential) of the anodic oxidation power supply. In the anodic oxidation tank, these bottom metal electrodes "*", the anodic oxidation solution and the counter electrode plate connected to the low potential (cathode potential) of the anodic oxidation power supply form an anodic oxidation circuit loop, thereby anodicizing all the bottom metal electrodes.

[0131] Similarly, as shown in Figure 8, for a photosensitive device with active detection pixels (APS), each row of select lines can be turned on by a "MUX" circuit incorporated at the edge of the device. Specifically, the "A", "B", and "Vdd" contacts located outside the array in Figure 8 are connected to the positive electrode of the anodizing power supply. In the MUX circuit, all field-effect transistors (FETs) and the FETs (T1) used as selection switches in the readout circuit of each APS pixel are turned on. The bottom metal electrode "*" of each pixel is connected to the high potential (i.e., the anode potential) of the anodizing power supply. In the anodizing tank, these bottom metal electrodes "*", the anodizing solution, and the counter electrode plate connected to the low potential (cathode potential) of the anodizing power supply form an anodizing circuit loop, thereby anodizing all the bottom metal electrode arrays.

[0132] It should be noted that the "MUX" circuit in Figure 7 does not need to be removed. After forming a metal compound thin film layer on the surface of the bottom metal electrode array through anodizing, the high potential of anodizing can be disconnected. During manufacturing, multiple photosensitive devices can be arranged in the longitudinal and transverse directions on the silicon wafer 800, as shown in Figure 9. The interconnects for fabricating the self-aligned, patterned metal compound thin film layer 300 can be connected horizontally or vertically at the edge of the photosensitive device 900 and connected to the contact point 801 on the wafer edge for the anodizing process. After the thin film device is fabricated, these interconnects can be automatically disconnected when the silicon wafer is diced into individual photosensitive devices, without the need for additional dicing or etching processes.

[0133] In this embodiment, Figures 5 and 6 show the basic structures of the PPS and APS pixel readout circuits. Any pixel readout circuit that includes corresponding transistors for similar functions has similar unit circuits, as long as they are connected in accordance with the same principles disclosed in this invention and a self-aligned metal compound thin film layer 300 is formed by anodizing to completely encapsulate the bottom metal electrode. These circuits are all within the scope of this invention and will not be described in detail here.

[0134] The transistors shown in Figures 5 and 6 can be used to create pixel readout circuits made of N-type or P-type transistors, and connected in a similar manner to implement the anodizing process.

[0135] The photosensitive layer described in this embodiment comprises an organic semiconductor in the form of a single-phase film or a D / A bulk heterojunction blend film, an inorganic semiconductor or compound semiconductor in the form of single-phase or quantum dot nanoparticles, or a combination thereof in a mixed form or a stacked thin film form. Here, D represents an organic molecule that is an electron donor; A represents an organic molecule that is an electron acceptor.

[0136] The inorganic semiconductors include Si, Ge, SiGe, and CuInS in crystalline or polycrystalline forms. x Se 2-x Nanoscale quantum dots, nanoscale quantum films, or single-phase films of CuInGa(S,Se), PbS, PbI2, PBI3, and InGaAs (0≤x≤2).

[0137] The organic semiconductor comprises an organic blend of one or more organic molecules that serve as electron donors (D) and one or more organic molecules that serve as electron acceptors (A), forming an organic blend of D / A.

[0138] In this embodiment, the photosensitive layer may have at least one molecular component with a band gap of less than 1.7 eV (wavelength greater than 700 nm), that is, the photosensitive device in this embodiment is an infrared photodetector.

[0139] In this embodiment, the photosensitive layer can be a single-molecule type organic semiconductor thin film, or a hybrid film containing at least one donor molecule (D) and one acceptor molecule (A) (commonly referred to as a D / A bulk heterojunction film). Donor (acceptor) molecules are often referred to as P-type (N-type) in the traditional inorganic semiconductor device industry. The photosensitive layer 400 can also be fabricated together with other thin-film semiconductor layers. Examples include perovskite semiconductor thin films (such as PbI2 and / or PbI3), PbS, CuInSe2, CuInSSe, CuInGaSe, and CuInGaSSe.

[0140] The absorption coefficients of the organic and inorganic semiconductor compounds listed above are in the range of 10. 4 -10 5 cm -1 Within this range, when the photosensitive layer has a thin film thickness of 100nm-1µm, it can achieve a light absorption rate of 90%-99% within the operating range. This contrasts sharply with the active layer in silicon CMOS image arrays, where the active layer typically needs a thickness of 10-500µm to achieve over 90% light absorption in the near-infrared region (700nm-1000nm).

[0141] The photosensitive layer can also be made of a thin film composed of the various semiconductor materials listed above to achieve the desired spectral response or performance improvement. Furthermore, the photosensitive layer can also be made of a composite thin film containing the aforementioned semiconductor materials. As mentioned above, the photosensitive layer can be made of organic molecules in the form of a D / A bulk heterojunction. The photosensitive layer can also be made of a phase comprising an organic semiconductor and another phase comprising inorganic semiconductor nanoparticles (or quantum dots). By utilizing the unique mechanical and electronic properties of organic semiconductors, this hybrid photosensitive layer can be fabricated with low-trapped states in the semiconductor bandgap, thereby improving device performance.

[0142] It is worth mentioning that, due to the thin-film nature of the photosensitive layer, photosensitive layers with pixel sizes as small as micrometers can be fabricated without patterning the photosensitive layer, as shown in Figure 2. Image dispersion caused by optical and / or current crosstalk becomes a negligible factor. In the photosensitive array shown in Figure 2, the continuous / unpatterned top metal electrode 600 is shared by all pixels of the photosensitive device. Due to the design of the "common" top metal electrode, the upper charge transport layer 500 between the photosensitive layer and the top metal electrode layer 600 can also be made in the form of a continuous thin film.

[0143] In this embodiment, the upper charge transport layer 500 typically has a charge opposite to that of the semiconductor metal compound thin film layer 300. The metal compound thin film layer 300, the photosensitive layer, and the upper charge transport layer 500 located on the upper surface of the bottom metal electrode can be stacked to form a PIN (or NIP) structure. Besides PIN or NIP junctions, various other structures such as PIP, NIN, NIPIN, and PINIP can also be stacked to form them.

[0144] This embodiment also includes adding a surface-promoting material (commonly referred to as a self-assembled monolayer, SAM) between the semiconductor metal compound thin film layer 300 and the photosensitive layer to improve adhesion and reduce surface defects at the interface. When the metal compound thin film layer 300 is an N-type semiconductor, examples of SAM materials used for the formed NI contact interface include SAM-C60, C60-COOH-SAM, and SAM-PBD. When the metal compound thin film layer 300 is a P-type semiconductor, suitable SAM materials for the formed PI contact interface include 2PACz, x-4PACz (where x = H, Cl, F, Ph), and PPAOMe. Their molecular structures are shown below.

[0145]

[0146] In this embodiment, depending on the organic molecular material used in the photosensitive layer, the wavelengths of light that can be detected are ultraviolet (200-400nm), visible light (400-700nm), near-infrared light (700-1000nm), short-wave infrared light (1000-2500nm), mid-infrared light (2.5-25um), or a combination of multiple wavelengths.

[0147] When necessary, an encapsulation layer 700 is added above the top metal electrode 600 to ensure stable operation of the photosensitive array under various operating environments and throughout its target lifespan. The encapsulation layer should be transparent in the operating wavelength range and have an optical transmittance of over 50%.

[0148] The encapsulation layer 700 can be formed using various vacuum deposition methods, such as thermal evaporation, molecular beam deposition, plasma sputtering, or atomic layer deposition. It can also be prepared using liquid deposition methods, such as drop coating, dip coating, spin coating, and various printing methods. Besides using a single material, the encapsulation layer can also be formed using alternating multilayer films. In addition to improving the performance of the encapsulation layer, this multilayer film structure can also be used to optimize the optical resonant cavity structure of thin-film photodiodes in the operating wavelength range, thereby optimizing their photosensitiveness and specific detectivity.

[0149] The encapsulation layer 700 commonly uses inorganic materials including silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, zirconium oxide, magnesium oxide, zirconium oxide and magnesium fluoride; and commonly uses organic materials including polymethyl methacrylate, polyethylene oxide, polystyrene, polyvinylpyrrolidone, polycarbonate, polyacrylic acid, epoxy resin, parylene, and polysiloxane.

[0150] In this embodiment, examples of materials constituting the continuous / unpatterned top metal electrode 600 include any elemental titanium (Ti), tungsten (W), titanium nitride (TiN), platinum (Pt), gold (Au), silver (Ag), germanium (Ge), nickel (Ni), tin (Sn), and aluminum (Al), or alloys containing at least one of these. In particular, indium titanium oxide (InTiO) has high transmittance relative to the infrared region and is desirable as a constitutive material for the continuous / unpatterned top metal electrode. In addition to the materials mentioned above, examples of materials for the top metal electrode include indium tin oxide (ITO), tin oxide (SnO2), indium tungsten oxide (InWO), indium zinc oxide (InZnO), aluminum-doped zinc oxide (AlZnO), gallium-doped zinc oxide (GaZnO), magnesium- and aluminum-doped zinc oxide (AlMgZnO), indium gallium oxide (InGaO), InGaZnO4 (IGZO), fluorine-doped indium oxide (FIO), antimony-doped tin oxide (ATO), fluorine-doped tin oxide (FTO), zinc oxide (ZnO), boron-doped ZnO (BZnO), and indium tin oxide (InSnZnO).

[0151] The material of the upper charge transport layer 500, which serves as the electron transport layer, is selected from organic compound 1, inorganic compound 1, or a combination thereof;

[0152] Wherein, the organic compound 1 is selected from fullerenes and their derivatives, 4,7-diphenyl-1,10-phenanthroline, polyethyleneimine, polyethoxyethyleneimine, 2,9-dimethyl-4,7-biphenyl-1,10-o-diazaphenanthroline, [9,9-dioctylfluorene-9,9-bis(N,N-dimethylaminopropyl)fluorene], bromo-[9,9-dioctylfluorene-9,9-bis(N,N-dimethylaminopropyl)fluorene], 8-hydroxyquinoline lithium, 1,3,5-tris(1-phenyl-1H-benzimidazol-2-yl)benzene, bis(2-methyl-8-quinoline)-4-(phenylphenol)aluminum, 1,3,5-tris[(3-pyridyl)-phenyl-3-yl]benzene, or mixtures or complexes of the above materials;

[0153] The inorganic compound 1 is selected from zinc oxide, tin oxide, aluminum-doped zinc oxide, magnesium-doped zinc oxide, gallium-doped zinc oxide, tin-doped zinc oxide, titanium oxide, tantalum oxide, zinc sulfide, chromium sulfide, or a mixture or composite of the above materials.

[0154] The material of the upper charge transport layer 500, which serves as the hole transport layer, is selected from organic compound 2, inorganic compound 2, or a combination thereof;

[0155] Wherein, the organic compound 2 is selected from 4,4'-cyclohexylbis[N,N'-di(4-methylphenyl)aniline], N,N'-bis(naphthyl-1-yl)-N,N'-bis(phenyl)-benzidine, N,N'-bis(naphthyl-1-yl)-N,N'-bis(phenyl)-2,7-diamino9,9-spirodifluorene, 2,2',7,7'-tetra[N,N-di(4-methoxyphenyl)amino]-9,9'-spirodifluorene, 4,4',4"-tris(carbazole-9-yl)triphenylamine, poly(4-butyltriphenylamine), polyvinylcarbazole, polystyrene-N,N'-diphenyl-N,N'-bis-(3-methylphenyl)-(1,1)-biphenyl-4,4 One or more of '-diamine perfluorocyclobutane, poly3,4-ethylenedioxythiophene mixed polystyrene sulfonate;

[0156] The inorganic compound 2 is selected from tungsten oxide, molybdenum oxide, vanadium oxide, chromium oxide, nickel oxide, copper oxide, cuprous oxide, cuprous thiocyanate, copper sulfide, copper iodide, or a mixture or compound of the above materials.

[0157] This embodiment also provides a method for fabricating a high pixel density thin-film device, including the following steps:

[0158] Patterning bottom metal electrodes on the backplate forms a bottom metal electrode array;

[0159] A dense, pinhole-free metal compound thin film layer is formed by surface chemical reaction on the free surface of the bottom metal electrode using a self-aligned process.

[0160] Preparation of continuous / unpatterned photosensitive layers;

[0161] Fabrication of continuous / unpatterned charge transport layers;

[0162] Fabrication of continuous / unpatterned top metal electrode layers;

[0163] Fabricate continuous / unpatterned encapsulation layers.

[0164] The photosensitive layer is prepared by solution film formation or vacuum thermal evaporation deposition.

[0165] The preparation of the charge transport layer is independently selected from one or more of the following methods: solution film formation, sol-gel film formation, vacuum thermal evaporation, atomic layer deposition, chemical vapor deposition, electrodeposition, and anodic oxidation.

[0166] The preparation of the top metal electrode layer and the bottom metal electrode layer are each independently selected from one or more of the following methods: vacuum thermal evaporation, electron beam evaporation, molecular beam evaporation or plasma sputtering, atomic layer deposition or liquid film formation followed by reduction and conversion, electroplating or electrodeposition.

[0167] Example 2

[0168] This embodiment provides a display device, as shown in Figures 1 and 2.

[0169] The display device includes a backplate with multiple pixel driving circuits integrated inside, and a thin-film device with high pixel density disposed on the backplate.

[0170] Each of the pixel driving circuits is connected to a corresponding bottom metal electrode via a metal post.

[0171] The thin-film device includes:

[0172] A bottom metal electrode array is formed on the back plate 100;

[0173] A dense, pinhole-free metal compound thin film layer 300 is passivated on the free surface of the bottom metal electrode 200 in the bottom metal electrode array to completely cover the bottom metal electrode 200.

[0174] The metal compound thin film layer 300 located on the upper surface of the bottom metal electrode 200 is a P-type or N-type semiconductor and forms an ohmic contact with the upper surface of the bottom metal electrode 200.

[0175] A continuous / unpatterned active layer 400, a continuous / unpatterned upper charge transport layer 500, a continuous / unpatterned top metal electrode 600, and a continuous / unpatterned transparent encapsulation layer 700 are formed sequentially from bottom to top on the metal compound thin film layer 300.

[0176] The display device described herein has a basically the same structure and manufacturing process as the photosensitive device in Example 1, with the specific differences as follows:

[0177] The photosensitive layer is replaced with a light-emitting layer to generate light for display.

[0178] In this embodiment, the undoped active layer 400 can be used as the light-emitting layer, which includes one or more light-emitting materials and can be in a multilayer or single-layer structure. The luminous efficiency can be optimized by adjusting the mixing ratio and film thickness in the form of a donor / guest mixture.

[0179] Depending on the material used in the light-emitting layer, it can achieve a combination of multiple wavelengths, including UV (200-400nm), visible light (400-700nm), near-infrared (700-1000nm), short-wavelength infrared (1000-2500nm), mid-wavelength infrared (2.5-25um), and more.

[0180] The material of the light-emitting layer includes p-type organic semiconductor materials and n-type organic semiconductor materials. Among them, the p-type organic semiconductor can be a compound that acts as an electron donor to supply electrons.

[0181] For example, the p-type organic semiconductor can be boron subphthalocyanine chloride (SubPc), copper(II) phthalocyanine (CuPc), tetraphenyldibenzoperiflanthene (DBP), or any combination thereof, but is not limited thereto. The n-type organic semiconductor can be a compound that acts as an electron acceptor, accommodating electrons. For example, the n-type organic semiconductor can be N2200, C60 fullerene, C70 fullerene, or any combination thereof, but is not limited thereto.

[0182] The molecular structure of N2200 is shown below:

[0183]

[0184] When the upper charge transport layer serves as an electron transport layer, it may include 2,9-dimethyl-4,7-diphenyl-1,10-phenanthroline (BCP: 2,9-Dimethyl-4,7-diphenyl-1,10-phenanthroline), 4,7-diphenyl-1,10-phenanthroline (Bphen: 4,7-Diphenyl-1,10-phenanthroline), Alq3, BAlq, TAZ, NTAZ, or any combination thereof.

[0185] In addition to the materials mentioned above, the electron transport layer may also include metallic substances.

[0186] The metal-containing substance may include alkali metal complexes, alkaline earth metal complexes, or any combination thereof. The metal ion of the alkali metal complex may be Li, Na, K, Rb, or Cs ions, and the metal ion of the alkaline earth metal complex may be Be, Mg, Ca, Sr, or Ba ions. The ligands coordinated to the metal ions of the alkali metal and alkaline earth metal complexes may independently include hydroxyquinoline, hydroxyisoquinoline, hydroxybenzoquinoline, hydroxyacridine, hydroxyphenanthridine, hydroxyphenyloxazole, hydroxyphenylthiazole, hydroxyphenyloxadiazole, hydroxyphenylthiadiazole, hydroxyphenylpyridine, hydroxyphenylbenzimidazole, hydroxyphenylbenzothiazole, bipyridine, phenanthrene, cyclopentadiene, or any combination thereof.

[0187] When the upper charge transport layer serves as a hole transport layer, it may include the following: m-MTDATA, TDATA, 2-TNATA, NPB (NPD), β-NPB, TPD, spiro-TPD (Spiro-TPD), spiro-NPB (Spiro-NPB), methylated -NPB, TAPC, HMTPD, 4,4',4"-tris(N-carbazolyl)triphenylamine (TCTA: 4,4',4"-tris(N-carbazolyl)triphenylamine), polyaniline / dodecylbenzenesulfonic acid (PANI / DBSA: Polyaniline / Dodecylbenzenesulfonic acid), poly(3,4-ethylenedioxythiophene) / poly(4-styrenesulfonate) (PEDOT / PSS: Poly(3,4-ethylenedioxythiophene) / Poly(4-styrenesulfonate)), polyaniline / camphorsulfonic acid (PANI / CSA: Polyaniline / Camphor sulfonic acid). (acid), polyaniline / poly(4-styrenesulfonate) (PANI / PSS: Polyaniline / Poly(4-styrenesulfonate)) or any combination thereof.

[0188] Figure 10 shows a typical pixel driving circuit in a display device (organic or inorganic components), illustrating a typical pixel driving circuit for an active matrix display array. When the "Vdata" and "Vdd" lines are connected via lines "A" and "B" in Figure 6, respectively, to the high potential of the anodizing power supply, and each "VSeset" line is connected to a line driver integrated into the silicon wafer, if transistors T1 and T2 in Figure 10 are turned on, the bottom metal electrode is connected to the high potential of the anodizing power supply. This allows the formation of a metal compound thin film layer through the anodizing process, after which the high potential of the anodizing power supply can be disconnected. After anodizing is complete, when the silicon wafer is diced into each display device, all connection lines in the pixel readout circuit of the display device that are connected to the silicon wafer are automatically cut along the dicing lines between adjacent display devices, without the need for additional dicing or etching processes.

[0189] Example 3

[0190] Generally, the thin-film device (photosensitive device or display device) is fabricated on a silicon wafer. In this embodiment, a backplane is first fabricated on the silicon wafer, and a tantalum (Ta) metal thin film layer is sputtered on the backplane using a DC sputtering device. The thickness of the Ta metal thin film layer ranges from about 170 to about 500 nm. The Ta metal thin film layer is then patterned using a photolithography process to form a bottom metal electrode array.

[0191] In this embodiment, a dense, pinhole-free Ta2O5 thin film layer is formed on the free surface of the corresponding bottom metal electrode. The specific steps are as follows:

[0192] S1. First, clean the free surface of the bottom metal electrode using IPA and DIW rinsing; air-blade drying; UV-Ozone treatment (365-385nm, 533mW / cm²). 2 ), 10-15 minutes.

[0193] S2. Connect the power clip of the anode to the contact pad near the edge of the silicon wafer.

[0194] S3. Immerse the silicon wafer in a container containing anodizing solution until the liquid surface reaches the specified line; immerse a stainless steel plate as the counter electrode (i.e., cathode) of the anode in the container containing anodizing solution, with a distance of 4 cm between the stainless steel plate and the silicon wafer; connect the stainless steel plate to the power clamp of the negative electrode.

[0195] The anodizing solution includes aqueous solutions of organic acids, weak acids, or weak bases and weak acid salts, and is also a solution containing an organic polar solvent.

[0196] The organic polar solvents include formamide, acetonitrile, methanol, ethanol, propanol, acetone, dioxane, tetrahydrofuran, methyl ethyl ketone, n-butanol, ethyl acetate, diethyl ether, isopropyl ether, dichloromethane, chloroform, bromoethane, benzene, chloropropane, toluene, carbon tetrachloride, carbon disulfide, cyclohexane, hexane, and heptane.

[0197] The organic acids include tartaric acid, oxalic acid, malic acid, citric acid, benzoic acid, salicylic acid, caffeic acid, and citric acid.

[0198] The weakly acidic salt aqueous solution includes carbonic acid (H2CO3), acetic acid (CH3COOH), silica (H2SiO3), nitrous acid (HNO2), hydrogen sulfide (H2S), hydrofluoric acid (HF), hypochlorous acid (HClO), hydrogen cyanide (HCN), sulfurous acid (H2SO3), and phosphoric acid (H3PO4).

[0199] The aqueous solutions of weak bases and weak acid salts include ammonium carbonate, ammonium acetate, and copper sulfide.

[0200] S4. In a 0.01 M citric acid solution at 0.2 mA / cm 2 (Typically, the current density can be 0.1-1 mA / cm) 2 A constant current (adjustable within a certain range) is used to anodize the metal surface until the voltage corresponding to the target thickness of Ta2O5 is reached (Ta2O5 growth rate = 0.46 V / nm). It should be noted that a 0.01 M citric acid solution is used as the anodizing solution.

[0201] S5. After reaching a voltage of 17.5 V (corresponding to the formation of a ~30 nm thin film), stop the constant current and switch the power supply to constant voltage mode. In constant voltage mode, the anodizing current will begin to decrease over time, as shown in Figure 11.

[0202] S6. When the current density drops to less than 1% of the constant current used in step S4, turn off the power supply.

[0203] S7. Remove the silicon wafer from the container containing the anodizing solution.

[0204] S8. Air dry; if watermarks are present on the oxide surface, perform ultrasonic deionized water cleaning.

[0205] In this embodiment, the rate of anodizing can be adjusted according to the current density used in the constant current phase. It can also be adjusted by the temperature of the anodizing solution; generally, the temperature of the anodizing solution is between 2°C and 25°C.

[0206] The anodizing process disclosed in this invention differs significantly from the anodizing process used in the metal corrosion protection industry. The former employs a low-current-density DC power supply, resulting in no significant temperature rise in the anodizing solution. A dense oxide film is formed during the constant-current phase, free of large crystalline particles and cracks. Furthermore, during the constant-voltage phase, the oxide film is further sealed. When anodizing is complete, the current drops to a negligible level, resulting in a dense, smooth, pinhole-free metal oxide film layer with a thickness selectable from a few nanometers to several hundred nanometers. In contrast, the metal surface passivation process used in the metal corrosion protection industry employs pulsed voltage and relatively high current, along with a relatively strong electrolyte. The resulting oxide coating has a thickness of 10-100 micrometers, and its porous surface includes numerous submicron-diameter pores.

[0207] Example 4

[0208] For the bottom metal electrode, this embodiment can also use O2 plasma to form a dense, pinhole-free metal compound thin film layer on the free surface of the bottom metal electrode.

[0209] The process conditions and equipment are the same as for O2 plasma. Evacuate to 300 mtorr, then turn on the plasma source, setting the power to 300W, and continue for 15 minutes. The backplate temperature can be set to 25°C. o C to 100 o Within the range of C. If necessary, the above process can be repeated, thereby producing a dense, pinhole-free metal compound thin film layer on the surface of the bottom metal electrode, which can be verified by impedance testing and photodiode testing.

[0210] Example 5

[0211] For the oxidation of the bottom metal electrode, annealing in high-temperature air at 100-300°C can also be used to form a dense metal compound thin film layer on the bottom metal electrode.

[0212] Specifically, after patterning and fabricating the bottom metal electrode (material tantalum) on a silicon wafer, the silicon wafer is ultrasonically cleaned in acetone for 5 minutes, followed by ultrasonic treatment in isopropanol for 5 minutes. The silicon wafer is then annealed at approximately 120°C for 20 minutes, allowing a semiconductor metal oxide thin film layer to form on the free surface of the bottom metal electrode. The resulting tantalum oxide is used as a wide-bandgap semiconductor layer with a Fermi energy of approximately -4.1 eV. It is important to note that if a metal compound thin film layer is formed solely through high-temperature oxidation, it is not necessary to place it on the silicon wafer.

[0213] Example 6

[0214] For the bottom metal electrode, this embodiment can use chemical oxidation treatment (H2O2 or 85°C hot water) to form a dense metal compound thin film layer on the bottom metal electrode.

[0215] Example 7

[0216] A dense semiconductor metal compound thin film layer was formed on the bottom metal electrode by using any combination of oxidation methods from Examples 3 to 6.

[0217] Alternatively, after Example 3, the oxidation process of Examples 4 to 6 can be used to continuously seal pinholes, thereby forming a higher quality, pinhole-free, dense metal compound thin film layer on the bottom metal electrode.

[0218] Example 8

[0219] This embodiment also provides a carrier 110 for anodizing processes on the surface of large-size silicon wafers (up to 16-inch silicon wafers).

[0220] The carrier 110 can be made of plastic sheet or anodized aluminum sheet; anodized aluminum sheet generally has better wear resistance and corrosion resistance. The carrier 110 can accommodate 2 silicon wafers 800 (as shown in Figure 12), 8 or 16 (as shown in Figure 13), or 24 silicon wafer 800 slots 130, which can be designed according to actual needs. Corresponding slots 130 are provided on the inner wall of the carrier 110, as shown in Figure 12, and a stainless steel plate 120 is placed between two silicon wafers 800.

[0221] Silicon wafers 800 and stainless steel 120 are inserted into slots 130 of carrier 110, respectively. The contact pads 801 of each silicon wafer 800 are connected to the anode clamp of the anodizing power supply, and the stainless steel is connected to the cathode of the anodizing power supply. Then, the entire carrier 110 is transferred into the oxidation tank. The level of the anodizing solution is controlled to be higher than that of the carrier. The anodizing power supply is turned on. Oxidation can be carried out according to Example 3. After the reaction is complete, the carrier is lifted, the wiring of the anodizing power supply is disconnected, and the carrier is moved into a cleaning tank for cleaning.

[0222] For example, the anodizing process time for Ta in Example 3 is approximately 60-120 minutes. Taking 120 minutes as an example, when a container is filled with 24 silicon wafers, the equivalent time for each silicon wafer is 5 minutes. The corresponding production capacity is 8,600 silicon wafers per month (annual production capacity greater than 100,000 wafers). This example demonstrates that the self-aligned, patterned semiconductor forming process disclosed in this invention can meet the requirements of high-volume, large-scale production.

[0223] Example 9

[0224] This embodiment provides a photosensitive device, which is prepared by the following method:

[0225] In 5×10 -7 Under the vacuum conditions of Torr, a 100 nm thick Ta metal film was thermally vaporized and deposited on the back plate at a rate of 0.1 Å / s.

[0226] The Ta-based metal electrode array on the backplane was anodized using the method described in Example 3 above to form a 30 nm Ta2O5 metal compound thin film layer.

[0227] The lead sulfide quantum dot solution coated with oleic acid ligands was spin-coated onto the above-mentioned Ta2O5 metal compound thin film. Then, a solid ligand exchange was performed using a methanol solution of tetrabutylammonium iodide as a short-chain ligand. Finally, the film was washed twice with methanol solvent to obtain a passivated lead sulfide quantum dot film. The above steps were repeated four times to obtain a lead sulfide quantum dot layer of a specified thickness.

[0228] The polymer donor JD40 and the non-fullerene acceptor Y6 were blended at a mass ratio of 1:1 and added to chloroform solvent. The dissolved solution was then spin-coated onto the lead sulfide quantum dot layer to prepare an organic semiconductor layer of a specified thickness. Finally, the layer was annealed at 80°C for 5 minutes.

[0229] The above structure was transferred to a thermal evaporation equipment, at 5×10 -7 Under the vacuum conditions of torr, a molybdenum oxide thin film of a specified thickness is thermally vaporized and deposited on the aforementioned photosensitive layer at a rate of 0.1 Å / s.

[0230] In 5×10 -7 Under the vacuum conditions of torr, a 30nm thick silver film is thermally deposited on a molybdenum oxide thin film layer as an anode, thereby obtaining a photosensitive device with a specific high pixel density.

[0231] A Ta2O5 thin film layer, serving as the electron transport layer, a photosensitive layer, and molybdenum oxide, serving as the hole transport layer, form an NIP junction.

[0232] In this embodiment, the photosensitive layer can be formed using binary organic materials (BHJ). The photosensitive layer can also be prepared using ternary or higher-order materials, as detailed in patent publication number CN113823744A, publication date: December 21, 2021, entitled "A High-Sensitivity Organic Photodiode and its Array, and a Method for Preparing the Organic Photodiode." The photosensitive layer can also be a hybrid of organic and inorganic semiconductor materials, as detailed in patent publication number CN 114284436 A, publication date: April 5, 2022, entitled "An Organic-Inorganic Hybrid Shortwave Infrared Photodetector and its Array, and a Related Preparation Method."

[0233] The photosensitive device prepared in this embodiment was used to capture and display an image, as shown in Figure 14. Figure 15 shows an image captured by a photosensitive device where the distance between adjacent bottom metal electrodes is too close, resulting in current leakage. As shown in Figure 15, due to current leakage between adjacent bottom metal electrodes, pixel signal crosstalk occurs, causing the image to be blurry. However, the photosensitive device described in this invention can improve image resolution, resulting in a clearer image.

[0234] Example 10

[0235] The display device provided in this embodiment has a similar structure to the photosensitive device, except that the semiconductor material used in the light-emitting layer is different from that used in the photosensitive layer of the photosensitive device, and their working principles are opposite. As a light-emitting display array, an array with ITIC as the host molecule and Y6-4F or IEICO-4F as the guest molecule, at a concentration of 0.5-10%, is used. A metal oxide thin film layer can be formed on the bottom metal electrode using the anodic oxidation method described in Example 3.

[0236] Within the scope of protection of this invention, the technical solutions and / or implementation methods can be modified and varied in various ways. For example, by using a bottom metal electrode (such as ITO, AlZnO, CuOx) that is transparent in the short-wave infrared region to replace the opaque metal electrode, the photosensitive device shown in Figure 2 can detect incident images simultaneously from above and below. For images incident from the top, it can detect image information across a wide band from ultraviolet, visible, and near-infrared to short-wave infrared; for images incident from the bottom, this device is only sensitive to image information in the short-wave infrared region (wavelength greater than 1 micrometer). This image sensing device can replace multiple cameras in portable devices such as mobile phones and helmets.

[0237] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the implementation of the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the claims of the present invention.

Claims

1. A thin film device having a high pixel density, characterized by: The thin film device comprises: forming a bottom metal electrode array on a backplane; passivating a free surface of a bottom metal electrode in the bottom metal electrode array with a dense, pinhole-free metal compound thin film layer to completely cover the bottom metal electrode; wherein the metal compound thin film layer on the upper surface of the bottom metal electrode is a P-type or N-type semiconductor and forms an ohmic contact with the upper surface of the bottom metal electrode; forming, in sequence from bottom to top on the metal compound thin film layer, a continuous / non-patterned active layer, a continuous / non-patterned upper charge transport layer, a continuous / non-patterned top metal electrode, and a continuous / non-patterned transparent encapsulation layer.

2. The thin film device having high pixel density according to claim 1, wherein: passivating a free surface of a bottom metal electrode in the bottom metal electrode array with a dense, pinhole-free metal compound thin film layer, comprising: forming a dense, pinhole-free metal compound thin film layer on the free surface of the bottom metal electrode by surface chemical reaction using a self-alignment process.

3. The thin film device with high pixel density of claim 2, wherein: The surface chemical reaction comprises one or more of anodic oxidation, oxygen plasma oxidation, high-temperature thermal oxidation, chemical oxidation, and sulfidation.

4. The thin film device with high pixel density of claim 3, wherein: The anodic oxidation has the following specific process steps: after preparing a bottom metal electrode array of a plurality of thin film devices on a wafer; cleaning the free surface of the bottom metal electrode; immersing the bottom metal electrode array on the wafer in an anodic oxidation solution of a non-strong acid; first forming the metal compound thin film layer at a constant current until the thickness of the metal compound thin film layer reaches a voltage corresponding to the target thickness; then maintaining the voltage corresponding to the target thickness and ending the anodic oxidation at a constant voltage until the oxidation current decreases below a certain threshold of the constant current.

5. The thin film device with high pixel density of claim 1, wherein: When the bottom metal electrode is a metal layer, the metal compound thin film layer passivated on the upper surface and sidewalls of the metal layer is a P-type or N-type semiconductor. When the bottom metal electrode is two or more metal layers, the metal compound thin film layer passivated on the upper surface of the topmost metal layer is a P-type or N-type semiconductor, and the metal compound thin film layer passivated on the sidewalls of the remaining metal layers is an insulating layer, or a P-type semiconductor, or an N-type semiconductor.

6. The thin film device with high pixel density of claim 1, wherein: The thickness of the metal compound thin film layer is 5 nm - 100 nm.

7. The thin film device having high pixel density of claim 1, wherein: The average surface roughness of the metal compound thin film layer is less than 5 nm.

8. The thin film device having high pixel density of claim 1, wherein: The carrier concentration of the metal compound thin film layer ranges from 10 15 cm -3 -10 20 cm -3 .

9. The thin film device having high pixel density of claim 1, wherein: The energy gap of the metal compound thin film layer is greater than that of the active layer.

10. The thin film device having high pixel density of claim 1, wherein: When the metal compound thin film layer is P-type, the material of the metal compound thin film layer comprises oxides or sulfides of Cu, Cr, Ni, V, Ga, W, Zr, or Mo, or oxides or sulfides of metal alloys thereof.

11. The thin film device having high pixel density of claim 1, wherein: When the metal compound thin film layer is N-type, the material of the metal compound thin film layer comprises oxides of Ti, Ta, Zn, In, Sn, Mg, Hf, Nd, or Nb, or oxides of metal alloys thereof.

12. The thin film device having high pixel density of claim 1, wherein: Further comprising: adding a surface-promoting material between the metal compound thin film layer and the active layer to improve adhesion and reduce surface defects at the interface.

13. The thin film device having high pixel density of claim 1, wherein: The active layer comprises an organic semiconductor in the form of a single-phase film or a D / A bulk heterojunction blend film, an inorganic semiconductor in the form of a single-phase or quantum dot nanoparticle, or a compound semiconductor, or a combination in a mixed form or a thin film stack; wherein D represents an electron donor organic molecule; A represents an electron acceptor organic molecule; wherein the inorganic semiconductor comprises Si, Ge, SiGe, CuInS x Se 2-x (0≤x≤2), CuInGa(S,Se), PbS, PbI2, PBI3, nanometer quantum dots, nanometer quantum film or single-phase film of InGaAs The organic semiconductor comprises one or more organic molecules serving as electron donors (D), one or more organic molecules serving as electron acceptors (A) to form a D / A organic blend.

14. A photosensitive device, characterized by: The backplane has a plurality of pixel readout circuits integrated therein, and the thin film device with high pixel density is arranged on the backplane. The active layer serves as a photosensitive layer for detecting light incident on the photosensitive device. Each pixel readout circuit is connected to a corresponding bottom metal electrode through a metal pillar.

15. A display device, characterized by comprising: The backplane has a plurality of pixel driving circuits integrated therein, and the thin film device with high pixel density is arranged on the backplane. The active layer serves as a light-emitting layer for generating light for light-emitting display. Each pixel driving circuit is connected to a corresponding bottom metal electrode through a metal pillar.

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