Decoding of variable-length prefix code data of an image data stream
An acceleration table for decoding variable-length prefix codes allows simultaneous lookup of multiple bits, addressing inefficiencies in modern CPUs by reducing power consumption and latency, thereby enhancing decoding performance for video compression.
Patent Information
- Application Number
- PCT/GB2025/050266
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2024-07-29
- Filing Date
- 2025-02-12
- Publication Date
- 2026-02-05
AI Technical Summary
Decoding variable-length prefix code data streams is inefficient for modern CPUs due to the need to process bits sequentially, leading to high power consumption, latency, and large device size, especially in applications like video compression where frequent small memory transactions and unpredictable branch operations occur.
Utilizing an acceleration table that maps fixed-length bit combinations to decoded symbols, allowing simultaneous access and lookup of multiple bits to decode the majority of symbols without sequential processing, reducing memory transactions and branch operations.
This approach significantly improves decoding performance by 3 to 10 times with minimal increase in power consumption or device size, making it more efficient for high-demand applications like video compression.