Communication method and apparatus

Abstract

The present application discloses a communication method and apparatus. The method comprises: a network device sends a low power synchronization signal to a terminal device, and the terminal device processes the low power synchronization signal on the basis of a first sequence. The first sequence is related to one or more of the following: the number of time units occupied by the first sequence, the number M of bits carried in each time unit, a subcarrier spacing, or a CP type. By means of the method, good synchronization detection performance of a low power synchronization signal generated on the basis of a first sequence can be ensured as much as possible.

Description

Communication method and apparatus

[0001] Cross-reference to Related Applications

[0002] This application claims priority to the Chinese Patent Application No. 202411091364.5, filed on August 8, 2024, and entitled “A Communication Method and Apparatus”, the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present application relates to the field of communication technology, and in particular, to a communication method and apparatus. BACKGROUND

[0004] In a wireless communication system, a network device sends a synchronization signal (SS) generated based on a specific sequence to a terminal device; the terminal device receives the synchronization signal and detects the specific sequence to achieve time synchronization and frequency synchronization between the terminal device and the network device. In order to reduce the power consumption of the terminal device, a lower power (LP) feature is introduced, and accordingly, a lower power synchronization signal (LP-SS) is also proposed.

[0005] The sequences commonly used to generate the SS include m-sequences and gold sequences. At present, it is proposed that m-sequences and gold sequences can also be used as sequences to generate the LP-SS. However, due to the difference in the generation process of the LP-SS and the SS, if any m-sequence or gold sequence used to generate the SS is followed for the LP-SS, it may result in lower synchronization detection performance (e.g., timing estimation performance) of the LP-SS. SUMMARY

[0006] Embodiments of the present application provide a communication method and apparatus for reducing the power consumption of a terminal device and trying to ensure better synchronization detection performance.

[0007] To achieve the above-mentioned purpose, the embodiments of the present application adopt the following technical solutions:

[0008] In a first aspect, a communication method is provided. The method can be applied to a network side, for example, the method is applied to a network device, a component (e.g., a circuit, a chip, or a chip system, etc.) in the network device; or the method is applied to a module or unit that completes part or all functions of the network device, for example, a central unit (CU), a distributed unit (DU), or a radio unit (RU). For convenience of description, the method is taken as an example applied to a network device in the following.

[0009] The communication method includes: a network device sending a low-power synchronization signal, wherein a sequence used to generate the low-power synchronization signal is a first sequence. Alternatively, the communication method includes: a network device generating a low-power synchronization signal based on a first sequence; and the network device sending the low-power synchronization signal. The first sequence is related to one or more of the following: a number of time units occupied by the first sequence, a number of bits M carried by each time unit, a subcarrier spacing, or a type of cyclic prefix (CP).

[0010] Correspondingly, in a second aspect, a communication method is provided. The method can be applied to a terminal side, for example, the method is applied to a terminal device, or the method is applied to a module or unit that completes part of the function of the terminal device, for example, a circuit or a chip / chip system (e.g., a modem chip, also known as a baseband chip, or a system on chip (SoC) chip or a system in package (SIP) chip containing a modem core) or other functional modules in the terminal device. For convenience of description, the method is taken as an example applied to a terminal device in the following. In the various aspects of the application described below, the terminal device supports a low-power feature.

[0011] The communication method includes: a terminal device receiving a low-power synchronization signal and processing the low-power synchronization signal based on a first sequence. Alternatively, the communication method includes: a terminal device receiving a low-power synchronization signal, wherein a sequence used to generate the low-power synchronization signal is a first sequence. The first sequence is related to one or more of the following: a number of time units occupied by the first sequence, a number of bits M carried by each time unit, a subcarrier spacing, or a type of CP.

[0012] In the solution of the first aspect or the second aspect, the first sequence is a sequence used to generate the LP-SS. The number of time units occupied by the first sequence, the number of bits M carried by each time unit, the subcarrier spacing, the type of CP, and the like can affect the autocorrelation of the sequence, and further affect the synchronization detection performance (e.g., timing estimation performance) of the LP-SS. The first sequence can be determined based on one or more of the above factors. In this way, the synchronization detection performance of the LP-SS generated based on the first sequence can be guaranteed to be relatively good.

[0013] In an implementation, the first sequence can be generated based on other sequences. For example, the first sequence is a gold sequence, and the first sequence can be generated based on two m-sequences.

[0014] As an example, the first sequence LP_SS satisfies: LP_SS = (x0 + x1) mod 2, where x0 is a second sequence, x1 is a third sequence, and mod is a modulo operation. The lengths of the second sequence and the third sequence are N, and N = 2 k -1, and k is a positive integer. The second sequence and the third sequence can be used to generate the first sequence. The first sequence is related to the number of time units occupied, the number of bits M carried by each time unit, the subcarrier spacing, or the type of CP. It can also be understood that the second sequence and the third sequence are each related to one or more of the following: the number of time units occupied, the number of bits M carried by each time unit, the subcarrier spacing, or the type of CP.

[0015] As another example, the first sequence LP_SS(n) satisfies: LP_SS(n) = [x0(n) + x1((n + m0) mod N)] mod 2, where x0(n) is a second sequence, x1(n) is a third sequence, m0 is a cyclic shift, n is an integer greater than or equal to 0 and less than N, N is the length of the second sequence and the third sequence, and N = 2 k -1, k is a positive integer, and mod is a modulo operation.

[0016] In this implementation, the terminal device or the network device can store the first sequence and generate the LP-SS based on the first sequence. Alternatively, the terminal device or the network device can also store the second sequence and the third sequence, generate the first sequence based on the second sequence and the third sequence, and then generate the LP-SS based on the first sequence. Alternatively, the terminal device or the network device can also generate the second sequence and the third sequence, generate the first sequence based on the second sequence and the third sequence, and then generate the LP-SS based on the first sequence.

[0017] In another implementation, the first sequence is associated with one or more of: a number of time units occupied by the first sequence, a number of bits M carried by each time unit, a subcarrier spacing, or a type of CP, and the initial value of the first sequence is associated with one or more of: the number of time units occupied by the first sequence, the number of bits M carried by each time unit, the subcarrier spacing, or the type of CP.

[0018] The initial value can also be understood as a base sequence (also referred to as an initial sequence) from which the first sequence is generated. For example, the first sequence is obtained by processing the initial value. In this scheme, the initial value of the first sequence can be determined based on one or more of: a number of time units occupied by the first sequence, a number of bits M carried by each time unit, a subcarrier spacing, or a type of CP, so that the autocorrelation of the first sequence can be guaranteed to be better. In addition, different initial values / different first sequences can be selected for adjacent cells to reduce interference between adjacent cells and improve the synchronization detection performance of the LP-SS.

[0019] In this implementation, the first sequence can be an m-sequence. The terminal device or the network device can store an initial value of the first sequence, generate the first sequence based on the initial value of the first sequence, and then generate the LP-SS based on the first sequence. Alternatively, the terminal device or the network device can store the first sequence obtained based on the initial value, and generate the LP-SS based on the stored first sequence.

[0020] In the implementation of the first aspect or the second aspect, when the first sequence is generated based on the second sequence and the third sequence, the second sequence and the third sequence are different according to different values of k, N, and M. The range of values of m0 is also different according to different combinations of the second sequence and the third sequence. Further, the second sequence and the third sequence, and the range of values of m0 are also different according to whether the Manchester coding is used in the process of generating the low-power synchronization signal. In the following, possible second sequences and third sequences, and the range of values of m0 are listed with specific examples. In any of the following examples, the taps of the second sequence and the third sequence are fewer, which can reduce the processing complexity. In any of the following examples, the range of values of m0 can guarantee better synchronization detection performance, for example, better timing estimation performance.

[0021] (1) k = 7, N = 127, M = 8.

[0022] The element x0(i+7) in the second sequence can satisfy: x0(i+7) = (x0(i+1) + x0(i)) mod 2, and the element x1(i+7) in the third sequence can satisfy: x1(i+7) = (x1(i+3) + x1(i)) mod 2. Alternatively, the element x0(i+7) in the second sequence can satisfy: x0(i+7) = (x0(i+1) + x0(i)) mod 2, and the element x1(i+7) in the third sequence can satisfy: x1(i+7) = (x1(i+4) + x1(i)) mod 2.

[0023] When the element x0(i+7) in the second sequence satisfies: x0(i+7) = (x0(i+1) + x0(i)) mod 2, and the element x1(i+7) in the third sequence satisfies: x1(i+7) = (x1(i+3) + x1(i)) mod 2, m0 belongs to a first set, which includes one or more cyclic shifts as follows: 3, 912, 15, 19, 31, 35, 46, 48, 57, 60, 61, 62, 64, 65, 71, 82, 87, 92, 94, 99, 101, 107, 108, 113, 114, 117, 120, 121, 122, 123, 124.

[0024] When the element x0(i+7) in the second sequence satisfies: x0(i+7) = (x0(i+1) + x0(i)) mod 2, and the element x1(i+7) in the third sequence satisfies: x1(i+7) = (x1(i+4) + x1(i)) mod 2, m0 belongs to a second set, which includes one or more cyclic shifts as follows: 24, 29, 34, 36, 39, 46, 47, 50, 53, 58, 61, 62, 65, 66, 78, 82, 84, 85, 86, 96, 100, 105, 106, 109, 111, 112, 116, 117, 120, 123, 125, 126.

[0025] (2) k = 6, N = 63, M = 8 or M = 4.

[0026] The element x0(i+6) in the second sequence satisfies: x0(i+6) = (x0(i+1) + x0(i)) mod 2, and the element x1(i+6) in the third sequence satisfies: x1(i+6) = (x1(i+5) + x1(i)) mod 2.

[0027] When M=8, m0 belongs to a third set comprising one or more cyclic shifts of: 2, 4, 5, 8, 9, 10, 11, 12, 13, 14, 16, 18, 19, 21, 22, 23, 27, 28, 33, 39, 40, 43, 45, 49, 50, 51, 52, 55, 57, 58, 60, 61.

[0028] When M=4, m0 belongs to a fourth set comprising one or more cyclic shifts of: 2, 4, 5, 9, 13, 14, 16, 18, 19, 22, 23, 25, 27, 28, 30, 31, 33, 34, 39, 40, 41, 43, 45, 49, 50, 51, 52, 53, 55, 57, 58, 60.

[0029] Optionally, when generating the low power consumption synchronization procedure, a Maltsev encoding operation is performed on the first sequence, i.e. element 0 in the first sequence is mapped to [0, 1] and element 1 in the first sequence is mapped to [1, 0] or element 1 in the first sequence is mapped to [0, 1] and element 0 in the first sequence is mapped to [1, 0]; and when M=8, m0 belongs to a fifth set comprising one or more cyclic shifts of: 1, 3, 6, 7, 8, 10, 12, 13, 15, 20, 21, 24, 26, 31, 32, 35, 36, 37, 41, 42, 43, 44, 47, 50, 53, 54, 56, 57, 59, 61, 62, 63.

[0030] (3) k = 5, N = 31, M = 8, M = 4 or M = 2.

[0031] The element x0(i+5) in the second sequence satisfies: x0(i+5) = (x0(i+2) + x0(i)) mod 2, and the element x1(i+5) in the third sequence satisfies: x1(i+5) = (x1(i+3) + x1(i+2) + x1(i+1) + x1(i)) mod 2. Alternatively, the element x0(i+5) in the second sequence satisfies: x0(i+5) = (x0(i+2) + x0(i)) mod 2, and the element x1(i+5) in the third sequence satisfies: x1(i+5) = (x1(i+4) + x1(i+2) + x1(i+1) + x1(i)) mod 2.

[0032] wherein, when the element x0(i+5) in the second sequence satisfies: x0(i+5) = (x0(i+2) + x0(i)) mod 2, and the element x1(i+5) in the third sequence satisfies: x1(i+5) = (x1(i+3) + x1(i+2) + x1(i+1) + x1(i)) mod 2, m0 belongs to a sixth set, the sixth set including one or more cyclic shifts of: 2, 4, 5, 7, 9, 10, 12, 13, 16, 20, 21, 23, 24, 25, 26, 27; or, 2, 5, 7, 9, 10, 12, 13, 16, 21, 23, 24, 25, 26, 27, 29, 30, 31.

[0033] Optionally, when the first sequence is subjected to a Manchester encoding operation in generating the low power consumption synchronization process, and when M = 4, m0 belongs to a seventh set, the seventh set including one or more cyclic shifts of: 1, 2, 3, 8, 10, 11, 13, 14, 15, 18, 19, 22, 27, 28, 29, 31.

[0034] Optionally, when the first sequence is subjected to a Manchester encoding operation in generating the low power consumption synchronization process, and when M = 4, m0 belongs to an eighth set, the eighth set including one or more cyclic shifts of: 1, 2, 3, 4, 6, 8, 11, 13, 14, 15, 18, 19, 22, 28, 29, 31.

[0035] wherein, when the element x0(i+5) in the second sequence satisfies: x0(i+5) = (x0(i+2) + x0(i)) mod 2, and the element x1(i+5) in the third sequence satisfies: x1(i+5) = (x1(i+4) + x1(i+2) + x1(i+1) + x1(i)) mod 2, m0 belongs to a ninth set, the ninth set including one or more cyclic shifts of: 1, 2, 3, 5, 6, 8, 9, 11, 12, 15, 16, 20, 21, 23, 28, 31; or, the ninth set including one or more cyclic shifts of: 1, 2, 3, 5, 6, 8, 9, 11, 12, 13, 15, 16, 20, 21, 23, 28.

[0036] Optionally, when the first sequence is subjected to a Manchester encoding operation in generating the low power consumption synchronization process, and when M = 8, m0 belongs to a tenth set, the tenth set including one or more cyclic shifts of: 4, 7, 10, 11, 13, 14, 18, 19, 20, 22, 24, 25, 27, 29, 30, 31.

[0037] Optionally, when the first sequence is subjected to the M-ary Manchester coding operation in the process of generating the low-power synchronization signal, and when M=4, m0 belongs to an eleventh set, the eleventh set including one or more cyclic shifts of 2, 4, 7, 8, 10, 14, 18, 19, 20, 22, 24, 25, 27, 29, 30, and 31.

[0038] (4) k = 4, N = 15, M = 4 or M = 2.

[0039] The element x0(i+4) in the second sequence satisfies x0(i+4) = (x0(i+1) + x0(i)) mod 2, and the element x1(i+4) in the third sequence satisfies x1(i+4) = (x1(i+3) + x1(i)) mod 2.

[0040] In the above, m0 belongs to a twelfth set, the twelfth set including one or more cyclic shifts of 2, 5, 7, 8, 9, 11, and 12.

[0041] Optionally, when the first sequence is subjected to the M-ary Manchester coding operation in the process of generating the low-power synchronization signal, m0 belongs to a thirteenth set, the thirteenth set including one or more cyclic shifts of 1, 3, 4, 6, 8, 12, 14, and 15.

[0042] The above m0 is related to a cell identifier, for example, m0 is determined according to a first cell identifier. Different m0 can carry different cell identifiers (IDs), and adjacent cells use different m0, so as to ensure the orthogonality of the LP-SS between adjacent cells as much as possible, and reduce the interference between adjacent cells.

[0043] In the implementation manner of the first aspect or the second aspect, when the initial value of the first sequence is related to the number of time units occupied by the first sequence, the number of bits M carried by each time unit, the subcarrier spacing, or the type of CP, etc., the initial value of the first sequence is different according to different values of k, N, and M. And according to whether the Manchester coding is used in the process of generating the low-power synchronization signal, the initial value of the first sequence is also different. The following lists the possible initial values of the first sequence with specific examples. The initial value in any of the following examples can ensure the optimal autocorrelation of the first sequence, so as to ensure the optimal synchronization detection performance as much as possible, for example, to ensure the optimal timing estimation performance.

[0044] (1) k = 7, N = 127, M = 8.

[0045] When the element x(i+7) in the first sequence satisfies: x(i+7) = (x(i+1) + x(i)) mod 2, the initial value is one of the initial values as follows: [0, 0, 0, 0, 0, 0, 1], [0, 0, 0, 0, 0, 1, 1], [0, 0, 1, 0, 0, 0, 0], [0, 0, 1, 1, 1, 1, 1], [0, 1, 0, 0, 0, 0, 0], [0, 1, 1, 0, 0, 1, 1], [0, 1, 1, 0, 1, 1, 0], [0, 1, 1, 1, 0, 1, 1], [0, 1, 1, 1, 1, 1, 1], [1, 0, 1, 0, 1, 0, 1], [1, 1, 0, 0, 1, 0, 0], [1, 1, 0, 1, 0, 1, 1], [1, 1, 0, 1, 1, 1, 1], [1, 1, 1, 0, 1, 1, 0], [1, 1, 1, 1, 1, 0, 1], [1, 1, 1, 1, 1, 1, 1].

[0046] When the element x(i+7) in the first sequence satisfies: x(i+7) = (x(i+1) + x(i)) mod 2, the initial value is one of the initial values as follows: [0, 0, 0, 0, 0, 0, 1], [0, 0, 0, 0, 0, 1, 0], [0, 0, 0, 0, 1, 1, 1], [0, 0, 0, 1, 0, 1, 1], [0, 0, 0, 1, 1, 0, 0], [0, 0, 1, 0, 0, 0, 0], [0, 1, 0, 0, 0, 1, 0], [0, 1, 0, 0, 1, 1, 0], [0, 1, 0, 1, 1, 0, 1], [0, 1, 0, 1, 1, 1, 0], [0, 1, 1, 0, 1, 1, 0], [1, 0, 0, 1, 0, 0, 1], [1, 1, 0, 0, 0, 0, 0].

[0047] (2) k = 6, N = 63, M = 8.

[0048] When the element x(i+7) in the first sequence satisfies: x(i+7) = (x(i+1) + x(i)) mod 2, the initial value is one of the initial values as follows: [0, 0, 0, 0, 1, 0], [0, 0, 0, 0, 1, 1], [0, 0, 1, 0, 0, 0], [0, 0, 1, 1, 1, 1], [0, 1, 0, 1, 0, 1], [0, 1, 1, 0, 0, 1], [0, 1, 1, 0, 1, 1], [1, 0, 0, 0, 0, 0], [1, 0, 0, 1, 1, 0], [1, 0, 1, 1, 1, 0], [1, 0, 1, 1, 1, 1], [1, 1, 0, 0, 1, 1], [1, 1, 0, 1, 0, 0], [1, 1, 1, 0, 1, 1], [1, 1, 1, 1, 0, 1], [1, 1, 1, 1, 1, 1].

[0049] Optionally, when generating the low-power consumption synchronization process, the first sequence is subjected to a Manteuffel coding operation, i.e., element 0 in the first sequence is mapped to [0, 1], and element 1 in the first sequence is mapped to [1, 0]; or element 1 in the first sequence is mapped to [0, 1], and element 0 in the first sequence is mapped to [1, 0]; and element x(i+6) in the first sequence satisfies: x(i+6) = (x(i+1) + x(i)) mod 2, the initial value is one of the following initial values: [0, 0, 0, 0, 1, 0], [0, 0, 0, 1, 0, 1], [0, 0, 1, 0, 0, 1], [0, 0, 1, 1, 0, 0], [0, 0, 1, 1, 1, 1], [0, 1, 0, 1, 0, 1], [0, 1, 1, 0, 0, 1], [0, 1, 1, 0, 1, 1], [0, 1, 1, 1, 0, 0], [1, 0, 0, 0, 0, 0], [1, 0, 0, 1, 0, 1], [1, 0, 1, 1, 0, 1], [1, 1, 0, 0, 0, 0], [1, 1, 0, 0, 1, 0], [1, 1, 0, 1, 1, 1].

[0050] When element x(i+6) in the first sequence satisfies: x(i+6) = (x(i+5) + x(i)) mod 2, the initial value is one of the following initial values: [0, 0, 0, 1, 0, 0], [0, 0, 0, 1, 1, 0], [0, 0, 0, 1, 1, 0], [0, 0, 1, 0, 0, 1], [0, 0, 1, 1, 0, 1], [0, 1, 0, 0, 0, 1], [0, 1, 0, 1, 1, 1], [0, 1, 1, 0, 0, 1], [0, 1, 1, 0, 1, 1], [1, 0, 0, 0, 0, 0], [1, 0, 0, 0, 0, 1], [1, 0, 0, 0, 1, 1], [1, 0, 1, 1, 0, 1], [1, 1, 0, 0, 0, 0], [1, 1, 0, 0, 1, 0], [1, 1, 0, 1, 1, 1].

[0051] (3) k = 6, N = 63, M = 4.

[0052] When the element x(i+6) in the first sequence satisfies: x(i+6) = (x(i+1) + x(i)) mod 2, the initial value is one of the initial values as follows: [0, 0, 0, 0, 1, 0], [0, 0, 0, 0, 1, 1], [0, 0, 1, 0, 0, 0], [0, 0, 1, 1, 1, 1], [0, 1, 0, 1, 0, 1], [0, 1, 1, 0, 0, 1], [0, 1, 1, 0, 1, 1], [1, 0, 0, 0, 0, 0], [1, 0, 0, 1, 1, 0], [1, 1, 0, 0, 0, 0], [1, 1, 0, 0, 1, 1], [1, 1, 0, 1, 0, 1], [1, 1, 0, 1, 1, 1], [1, 1, 1, 1, 0, 1], [1, 1, 1, 1, 0, 1], [1, 1, 1, 1, 1, 1].

[0053] Alternatively, when a Duffing sequence is generated in a low-power synchronization process, the first sequence is subjected to a Duffing encoding operation, and when the element x(i+6) in the first sequence satisfies: x(i+6) = (x(i+1) + x(i)) mod 2, the initial value is one of the initial values as follows: [0, 0, 0, 1, 0, 1], [0, 0, 0, 1, 1, 1], [0, 0, 1, 0, 0, 1], [0, 0, 1, 0, 1, 0], [0, 0, 1, 1, 1, 0], [0, 1, 0, 0, 0, 0], [0, 1, 0, 0, 0, 1], [0, 1, 0, 1, 1, 1], [0, 1, 1, 0, 0, 0], [0, 1, 1, 0, 1, 1], [0, 1, 1, 1, 1, 1], [1, 0, 0, 0, 0, 0], [1, 0, 0, 0, 0, 1], [1, 0, 0, 0, 1, 1], [1, 0, 1, 1, 0, 1], [1, 1, 1, 1, 0, 1].

[0054] When the element x(i+6) in the first sequence satisfies: x(i+6) = (x(i+5) + x(i)) mod 2, the initial value is one of the initial values as follows: [0, 0, 0, 0, 1, 0], [0, 0, 0, 0, 1, 1], [0, 0, 0, 1, 0, 0], [0, 0, 0, 1, 1, 0], [0, 0, 0, 1, 1, 1], [0, 0, 1, 0, 0, 0], [0, 0, 1, 1, 0, 1], [0, 1, 0, 0, 0, 1], [0, 1, 1, 0, 0, 1], [0, 1, 1, 0, 1, 1], [0, 1, 1, 1, 0, 0], [1, 0, 0, 0, 0, 0], [1, 0, 0, 0, 0, 1], [1, 0, 0, 0, 1, 1], [1, 1, 0, 1, 1, 0], [1, 1, 1, 0, 0, 0].

[0055] (4) k = 5, N = 31, M = 4.

[0056] When the element x(i+5) in the first sequence satisfies: x(i+5) = (x(i+2) + x(i)) mod 2, the initial value is one of the initial values as follows: [0, 0, 0, 0, 1], [0, 0, 0, 1, 1], [0, 0, 1, 1, 1], [0, 1, 0, 0, 0], [0, 1, 0, 1, 1], [0, 1, 1, 0, 0], [0, 1, 1, 0, 1], [0, 1, 1, 1, 1], [1, 0, 0, 1, 1], [1, 0, 1, 0, 0], [1, 1, 0, 0, 0], [1, 1, 0, 0, 1], [1, 1, 1, 0, 0], [1, 1, 1, 1, 0], [1, 1, 1, 1, 1]

[0057] Optionally, when the first sequence is subjected to a Manchester encoding operation in generating the low-power consumption synchronization process, and the element x(i+5) in the first sequence satisfies: x(i+5) = (x(i+2) + x(i)) mod 2, the initial value is one of the initial values as follows: [0, 0, 0, 0, 1], [0, 0, 0, 1, 1], [0, 0, 1, 0, 1], [0, 1, 0, 0, 0], [0, 1, 0, 0, 1], [0, 1, 1, 0, 0], [0, 1, 1, 0, 1], [0, 1, 1, 1, 1], [1, 0, 0, 1, 0], [1, 0, 0, 1, 1], [1, 0, 1, 0, 0], [1, 0, 1, 1, 1], [1, 1, 0, 0, 0], [1, 1, 0, 1, 1], [1, 1, 1, 0, 0], [1, 1, 1, 1, 1].

[0058] (5) k = 5, N = 31, M = 2.

[0059] When the element x(i+5) in the first sequence satisfies: x(i+5) = (x(i+2) + x(i)) mod 2, the initial value is one of the initial values as follows: [0, 0, 0, 1, 1], [0, 0, 1, 0, 0], [0, 0, 1, 1, 0], [0, 0, 1, 1, 1], [0, 1, 0, 0, 1], [0, 1, 1, 0, 1], [0, 1, 1, 1, 1], [1, 0, 0, 0, 1], [1, 0, 0, 1, 0], [1, 0, 1, 0, 0], [1, 1, 0, 0, 1], [1, 1, 0, 1, 1], [1, 1, 1, 0, 0], [1, 1, 1, 1, 0].

[0060] (6) k = 5, N = 31, M = 8.

[0061] When the first sequence is subjected to a Manchester encoding operation in generating the low-power consumption synchronization process, and the element x(i+5) in the first sequence satisfies: x(i+5) = (x(i+2) + x(i)) mod 2, the initial value is one of the initial values as follows: [0, 0, 0, 0, 1], [0, 0, 1, 0, 0], [0, 0, 1, 0, 1], [0, 0, 1, 1, 1], [0, 1, 0, 0, 0], [0, 1, 0, 1, 0], [0, 1, 1, 0, 0], [0, 1, 1, 0, 1], [0, 1, 1, 1, 0], [1, 0, 0, 1, 0], [1, 0, 0, 1, 1], [1, 0, 1, 0, 0], [1, 0, 1, 1, 1], [1, 1, 0, 1, 1], [1, 1, 1, 0, 0], [1, 1, 1, 1, 1].

[0062] (7) k = 4, N = 15, M = 2.

[0063] When the element x(i+4) in the first sequence satisfies: x(i+4) = (x(i+1) + x(i)) mod 2, the initial value is one of the initial values as follows: [0, 0, 1, 1], [0, 1, 0, 1], [0, 1, 1, 1], [1, 0, 1, 0], [1, 0, 1, 1], [1, 1, 0, 1], [1, 1, 1, 0], [1, 1, 1, 1].

[0064] Optionally, when the first sequence is subjected to a Manchester encoding operation in generating the low-power consumption synchronization process, and the element x(i+4) in the first sequence satisfies: x(i+4) = (x(i+1) + x(i)) mod 2, the initial value is one of the initial values as follows: [0, 0, 0, 1], [0, 0, 1, 0], [0, 1, 0, 0], [0, 1, 1, 0], [1, 0, 0, 1], [1, 0, 1, 1], [1, 1, 0, 1], [1, 1, 1, 1].

[0065] When the element x(i+4) in the first sequence satisfies: x(i+4) = (x(i+3) + x(i)) mod 2, the initial value is one of the initial values as follows: [0, 0, 0, 1], [0, 0, 1, 1], [0, 1, 0, 1], [1, 1, 1, 1], [1, 0, 0, 0], [1, 0, 1, 1], [1, 1, 1, 0], [1, 1, 1, 1].

[0066] Optionally, when the first sequence is subjected to a Manchester coding operation in the generation of the low-power synchronization process, and the element x(i+4) in the first sequence satisfies x(i+4)=(x(i+3)+x(i))mod 2, the initial value is one of the following initial values: [0, 0, 0, 1], [0, 0, 1, 0], [0, 0, 1, 1], [0, 1, 0, 0], [1, 1, 0, 0], [1, 1, 0, 1], [1, 1, 1, 0], [1, 1, 1, 1].

[0067] (8) k = 4, N = 15, M = 4.

[0068] When the element x(i+4) in the first sequence satisfies x(i+4)=(x(i+1)+x(i))mod 2, and the first sequence is subjected to a Manchester coding operation in the generation of the low-power synchronization process, the initial value is one of the following initial values: [0, 0, 1, 1], [0, 1, 0, 1], [1, 0, 0, 0], [1, 0, 0, 1], [1, 0, 1, 1], [1, 1, 0, 0], [1, 1, 0, 1], [1, 1, 1, 1].

[0069] When the element x(i+4) in the first sequence satisfies x(i+4)=(x(i+3)+x(i))mod 2, and the first sequence is subjected to a Manchester coding operation in the generation of the low-power synchronization process, the initial value is one of the following initial values: [0, 0, 0, 1], [0, 0, 1, 0], [0, 0, 1, 1], [0, 1, 0, 0], [1, 0, 0, 0], [1, 1, 0, 0], [1, 1, 0, 1], [1, 1, 1, 1].

[0070] When the initial value of the first sequence is related to the number of time units occupied by the first sequence, the number of bits M carried by each time unit, the subcarrier spacing, or the type of CP, etc., the first sequence is related to the first cell identifier, and / or the cyclic shift of the first sequence is related to the first cell identifier.

[0071] The generation formula and the initial value of the first sequence can be determined according to the cell identifier. Different generation formulas and initial values can be selected for adjacent cells, so as to ensure the orthogonality of the LP-SS between adjacent cells, and to reduce the interference between adjacent cells as much as possible.

[0072] In a third aspect, an embodiment of the present application provides a communication apparatus, which has the function of implementing the behaviors in the method examples of the first aspect or the second aspect, and the beneficial effects can be referred to the related description of the first aspect or the second aspect, which will not be repeated here. For example, the communication apparatus can be the network device in the first aspect, or the communication apparatus can be an apparatus capable of supporting the functions required for the network device to implement the method provided by the first aspect, for example, the communication apparatus can be a chip or a chip system in the network device. For another example, the communication apparatus can be the terminal device in the second aspect, or the communication apparatus can be an apparatus capable of supporting the functions required for the terminal device to implement the method provided by the second aspect, for example, the communication apparatus can be a chip or a chip system in the terminal device.

[0073] In a possible design, the communication apparatus includes a baseband apparatus and a radio frequency apparatus.

[0074] In a possible design, the communication apparatus includes corresponding means or modules or units for performing the method of the first aspect or the second aspect. The modules or units or means can be implemented by software, or by hardware, or by a combination of software and hardware. For example, the communication apparatus includes a processing unit (sometimes also referred to as a processing module or a processor) and / or a transceiver unit (sometimes also referred to as a transceiver module or a transceiver). The transceiver unit is capable of implementing the sending function and the receiving function. When the transceiver unit implements the sending function, it can be referred to as a sending unit (sometimes also referred to as a sending module). When the transceiver unit implements the receiving function, it can be referred to as a receiving unit (sometimes also referred to as a receiving module). The sending unit and the receiving unit can be the same functional unit, which is referred to as a transceiver unit, and is capable of implementing the sending function and the receiving function. Alternatively, the sending unit and the receiving unit can be different functional units, and the transceiver unit refers to these functional units in general. These units (modules) can perform the corresponding functions in the method examples of the first aspect or the second aspect, and the details can be referred to the detailed description in the method examples, which will not be repeated here.

[0075] For example, the communication apparatus is used to implement the corresponding functions in the method examples of the first aspect, and the processing module is used to generate the low-power-consumption synchronization signal. The sequence used to generate the low-power-consumption synchronization signal is the first sequence. The first sequence is related to one or more of the following: the number of time units occupied by the first sequence, the number of bits M carried by each time unit, the subcarrier spacing, or the type of CP. The transceiver module is used to send the low-power-consumption synchronization signal.

[0076] For example, the communication apparatus is configured to implement the corresponding functions in the method examples of the second aspect, and the transceiver is configured to receive the low-power synchronization signal. The processor is configured to process the low-power synchronization signal based on the first sequence. The first sequence is related to one or more of the following: the number of time units occupied by the first sequence, the number of bits M carried by each time unit, the subcarrier spacing, or the type of CP.

[0077] In a fourth aspect, the embodiments of the present application provide a communication apparatus, which comprises a processor configured to enable the communication apparatus to perform the method in the first aspect or the second aspect or any implementation manner thereof. Optionally, the communication apparatus further comprises a communication interface. Optionally, the communication apparatus further comprises a memory configured to store a computer program (which can also be referred to as code or instruction), data, etc. The processor is coupled with the memory and the communication interface. When the processor reads the computer program, data, etc. from the memory, the communication apparatus is enabled to perform the method in the first aspect or the second aspect or any implementation manner thereof.

[0078] In a fifth aspect, the embodiments of the present application provide a communication apparatus, which comprises an input / output interface and a logic circuit. The input / output interface is configured to input and / or output information. The input / output interface can be an interface circuit, an output circuit, an input circuit, a pin or related circuit, etc. The logic circuit is configured to perform the method in the first aspect or the second aspect.

[0079] In the fourth aspect and the fifth aspect, the communication apparatus can be the network device in the first aspect. Alternatively, the communication apparatus can be an apparatus capable of supporting the functions required for the network device to implement the method provided in the first aspect, for example, the communication apparatus can be a chip or a chip system in the network device. Alternatively, the communication apparatus can be the terminal device in the second aspect. Alternatively, the communication apparatus can be an apparatus capable of supporting the functions required for the terminal device to implement the method provided in the second aspect, for example, the communication apparatus can be a chip or a chip system in the terminal device. The chip can be a baseband chip and / or a radio frequency chip, and the chip system can be composed of the chip or can contain the chip and other discrete devices.

[0080] In an implementation manner of the fifth aspect, when the communication apparatus is the terminal device, the interface circuit can be a radio frequency processing chip in the terminal device, and the processing circuit can be a baseband processing chip in the terminal device. When the communication apparatus is the network device, the interface circuit can be a radio frequency processing chip in the network device, and the processing circuit can be a baseband processing chip in the network device.

[0081] In an implementation process of the fifth aspect, when the communication apparatus is a chip or a chip system, the input circuit can be an input pin, the output circuit can be an output pin, and the logic circuit can be a transistor, a gate circuit, a flip-flop, various logic circuits, etc. The input signal received by the input circuit can be received and input by, for example but not limited to, a receiver, the output signal output by the output circuit can be output to and transmitted by, for example but not limited to, a transmitter, and the input circuit and the output circuit can be the same circuit which is used as the input circuit and the output circuit at different times. The specific implementation of the input / output interface and the logic circuit is not limited in the present application.

[0082] In a sixth aspect, an embodiment of the present application provides a communication system, comprising a terminal device and a network device, wherein the network device is configured to implement the functions of the method in the first aspect, and the terminal device is configured to implement the functions of the method in the second aspect.

[0083] In a seventh aspect, an embodiment of the present application provides a computer readable storage medium configured to store a computer program or instructions, which when executed, cause the method in the first aspect or the second aspect or any implementation manner thereof to be implemented.

[0084] In an eighth aspect, an embodiment of the present application further provides a computer program product comprising instructions which, when executed on a computer, cause the method in the first aspect or the second aspect or any implementation manner thereof to be implemented.

[0085] The beneficial effects of the third aspect to the eighth aspect and the implementation manners thereof can refer to the beneficial effects of the first aspect to the second aspect and any implementation manner thereof. BRIEF DESCRIPTION OF DRAWINGS

[0086] FIG. 1 is a schematic diagram of an architecture of a communication system according to an embodiment of the present application;

[0087] FIG. 2 is a schematic diagram of a generation process of an OOK-4 waveform;

[0088] FIG. 3 is a schematic diagram of a code sequence generator composed of a k-stage shift register;

[0089] FIG. 4 is a schematic diagram of the influence of CP on the autocorrelation of different sequences;

[0090] FIG. 5 is another schematic diagram of the influence of CP on the autocorrelation of different sequences;

[0091] FIG. 6 is a schematic diagram of the first wave trough in FIG. 5;

[0092] FIG. 7 is a schematic diagram of the influence of Manchester coding on the autocorrelation of a gold sequence;

[0093] FIG. 8 is a flow diagram of a communication method according to an embodiment of the present application;

[0094] FIG. 9 is a schematic diagram of a structure of a communication apparatus according to an embodiment of the present application;

[0095] FIG. 10 is a schematic diagram of another structure of a communication apparatus according to an embodiment of the present application. DETAILED DESCRIPTION

[0096] The technical solutions provided by the embodiments of the present application can be applied to various communication systems, for example, a long term evolution (LTE) communication system, a 5th generation (5G) mobile communication system / new radio (NR) communication system, or can also be applied to a future mobile communication system or other similar communication systems. Other similar communication systems can include wireless fidelity (WIFI), vehicle to everything (V2X), internet of things (IoT) system, etc.

[0097] [According to Rule 91 Correction 16.10.2025] Please refer to FIG. 1, which shows a communication system to which the embodiments of the present application are applicable. The communication system includes a radio access network 100 and a core network 200. Optionally, the communication system can also include the Internet 300 (as an example in FIG. 1).

[0098] The radio access network 100 can include at least one network device and at least one terminal device. For example, the radio access network 100 includes two network devices 110a and 110b and terminal devices 120a to 120j. The network architecture shown in FIG. 1 is only schematic, and the number of terminal devices and / or network devices can be less or more. The communication system described in the embodiments of the present application is for more clearly illustrating the technical solutions of the embodiments of the present application, and does not constitute a limitation on the communication system to which the embodiments of the present application are applicable. For example, the communication system can also include other devices, such as wireless relay devices and wireless backhaul devices, etc., which are not shown in FIG. 1. Those skilled in the art can know that, as the network architecture evolves, the technical solutions provided by the embodiments of the present application are also applicable to similar technical problems. When applying the technical solutions of the embodiments of the present application to other communication systems, the devices, components, modules, etc. in the embodiments can be replaced by corresponding devices, components, modules in other communication systems, without limitation.

[0099] In embodiments of the present application, the network device refers to a (wireless) access network ((radio) access network, (R)AN) device / RAN node. In embodiments of the present application, the (R)AN and the RAN are replaceable. The RAN can be a third generation partnership project (3GPP) related cellular system, for example, a 5G / NR mobile communication system, or a future-oriented evolved system. The RAN can also be an open RAN (O-RAN or ORAN), a cloud radio access network (CRAN), or a virtualized RAN (vRAN), a non-terrestrial network (NTN), etc. The RAN can also be a communication system in which two or more of the above systems are fused. The RAN device can also be referred to as a RAN node, a RAN entity, or an access node, etc.

[0100] In a possible scenario, the RAN node can be a base station, an evolved NodeB (eNodeB), an access point (AP), a transmission reception point (TRP), a next generation NodeB (gNB), a base station in a future mobile communication system, etc. The RAN node can be a macro base station, a micro base station, an indoor station, a relay node, a donor node / host node, or a radio controller, etc. The RAN node can also be a server, a wearable device, a vehicle or a vehicle-mounted device, etc. For example, the RAN node in the V2X technology can be a road side unit (RSU).

[0101] In another possible scenario, a RAN node can be a module or unit that completes part of the function of a base station; or multiple RAN nodes cooperate to assist a terminal device to implement wireless access, and different RAN nodes respectively implement part of the function of a base station. For example, a RAN node can be a CU, a DU, or a RU, etc. The function of the CU can be implemented by one entity, or also can be implemented by different entities. For example, the function of the CU can be further divided, that is, the control plane and the user plane are separated and implemented by different entities, respectively, as a control plane CU entity (that is, a CU-control plane (CP) entity) and a user plane CU entity (that is, a CU-user plane (UP) entity). The CU-CP entity and the CU-UP entity can be coupled with the DU to jointly complete the function of the RAN node. The CU and the DU can be separately arranged, or also can be included in the same network element, for example, in a baseband unit (BBU). Any one of the CU (or the CU-CP, the CU-UP), the DU, and the RU in this application can be implemented by a software module, a hardware module, or a combination of a software module and a hardware module.

[0102] In different systems, the CU (or the CU-CP and the CU-UP), the DU, or the RU can also have different names, but those skilled in the art can understand their meanings. For example, in an ORAN system, the CU can also be referred to as an O-CU (open CU), the DU can also be referred to as an O-DU, the CU-CP can also be referred to as an O-CU-CP, the CU-UP can also be referred to as an O-CU-UP, and the RU can also be referred to as an O-RU. For the convenience of description, the CU, the CU-CP, the CU-UP, the DU, and the RU are taken as examples for description in this application.

[0103] The CU and the DU can be configured according to the protocol layer function of the wireless network they implement: for example, the CU is configured to implement the function of the packet data convergence protocol (PDCP) layer and the protocol layer above (such as the radio resource control (RRC) layer and / or the service data adaptation protocol (SDAP) layer, etc.); and the DU is configured to implement the function of the protocol layer below the PDCP layer (such as the radio link control (RLC), the media access control (MAC) layer, and / or the physical (PHY) layer, etc.). For specific description of the above-mentioned various protocol layers, reference can be made to the relevant technical specifications of 3GPP or the technical specifications of other applicable communication protocols.

[0104] The above-mentioned processing functions of the CU and the DU are merely examples according to the protocol layer division, and the division can be performed in other manners, which is not limited in the present application. For example, in one design, the CU or the DU can also be divided into partial processing functions with protocol layers. In one design, partial functions of the RLC layer and functions of the protocol layers above the RLC layer are arranged in the CU, and the remaining functions of the RLC layer and functions of the protocol layers below the RLC layer are arranged in the DU.

[0105] In another possible design, the functions of the PHY layer are jointly implemented by the DU and the RU, or described as moving part of the PHY layer functions of the DU to the RU. One DU can be connected with one or more RUs. The functions of the DU and the RU can be configured in multiple manners according to the design. For example, the DU is configured to implement baseband functions, and the RU is configured to implement intermediate frequency functions. For another example, the DU is configured to implement high-layer functions in the PHY layer, and the RU is configured to implement low-layer functions in the PHY layer or implement the low-layer functions and the intermediate frequency functions. The high-layer functions in the PHY layer can include part of the functions of the PHY layer, which are closer to the MAC layer, and the low-layer functions in the PHY layer can include another part of the functions of the PHY layer, which are closer to the intermediate frequency side. The present application does not limit the specific functions of the DU and the RU. The interface between the DU and the RU can be referred to as a front-haul interface. In one design, the CU can have no PDCP layer, for example, the CU only includes the RRC layer. The CU-CP has no PDCP-C. The CU-UP can have no PDCP-U, or have no CU-UP. In one design, the DU can have no RLC layer, for example, the DU only has the MAC and the higher PHY layer.

[0106] When the RAN is an O-RAN, it can also have an artificial intelligence (AI) function, for example, the O-RAN includes an intelligent controller. The intelligent controller can be a non-real time RAN intelligent controller (non-real time RIC / non-RT RIC / NRT RIC), or a near-real time RAN intelligent controller (near-real time RIC / near-RT RIC / nRT RIC). The non-real time RIC can be used to implement non-real time intelligent management of the RAN function, can implement a workflow including model training and model updating, and guide applications / functions in the nRT RIC based on a policy. The near-real time RIC can be used to implement near-real time intelligent management of the RAN. Through data collection and related operations on the E2 interface, near-real time control and optimization of modules and resources of the O-RAN are implemented.

[0107] In the embodiments of the present application, all devices capable of communicating data with the base station can be regarded as terminal devices. The terminal device is also referred to as a terminal, a terminal apparatus, a user equipment (UE), a user device, a mobile station, or a mobile terminal, etc. The terminal device can be widely applied to various scenarios, for example, the terminal device can be a mobile phone, a computer, a mobile internet device (MID), a wearable device, a virtual reality (VR) device, an augmented reality (AR) device, a station (STA), a mechanical arm, a camera, a robot, a vehicle, a drone, a helicopter, an airplane, a ship, or a smart home device (such as a television, an air conditioner, a sweeping machine, a sound box, a set-top box), a relay, a customer premise equipment (CPE), etc.

[0108] In addition, in the embodiments of the present application, the terminal device can also be a terminal device in an IoT system, for example, a water meter, an electricity meter, etc. IoT is an important part of the future information technology development, and its main technical feature is to connect objects through communication technology and network, so as to realize the intelligent network of man-machine interconnection and object-object interconnection.

[0109] The terminal device can also be referred to as a V2X device when applied to V2X, for example, a smart car, an unmanned car, a road site unit (RSU), etc. As introduced above, various terminal devices can be considered as vehicle-mounted terminal devices if they are located on a vehicle (for example, placed / installed in the vehicle). The vehicle-mounted terminal device can be built-in as one or more components or units in a vehicle-mounted module, a vehicle-mounted module group, a vehicle-mounted component, a vehicle-mounted chip, or a vehicle-mounted unit. The vehicle can implement the method of the present application through the built-in vehicle-mounted module, vehicle-mounted module group, vehicle-mounted component, vehicle-mounted chip, or vehicle-mounted unit. The vehicle-mounted terminal device can be a whole vehicle device, a vehicle-mounted module, a vehicle, an on-board unit (OBU), an RSU, a telematics box (T-box), a chip, or an SoC, etc. The above-mentioned chip or SoC can be installed in a vehicle, OBU, RSU, or T-box.

[0110] Taking a network device as a base station and a terminal device as a UE as an example, the base station and the UE can be in a fixed position or movable. The base station and the UE can be deployed on land, including indoors or outdoors, handheld or vehicle-mounted; can also be deployed on the water surface; and can also be deployed on an airplane, a balloon, and a man-made satellite. Embodiments of the present application do not limit the application scenarios of the base station and the UE.

[0111] The roles of the base station and the UE can be relative, for example, the helicopter or the unmanned aerial vehicle 120i in FIG. 1 can be configured as a mobile base station. For the UE 120j accessing to the wireless access network 100 through 120i, the UE 120i is a base station; but for the base station 110a, 120i is a UE, that is, 110a and 120i communicate through a wireless air interface protocol. Of course, 110a and 120i can also communicate through a base station-to-base station interface protocol, at this time, relative to 110a, 120i is also a base station. Therefore, the base station and the UE can be collectively referred to as a communication device. 110a and 110b in FIG. 1 can be referred to as a communication device with a base station function, and 120a-120j in FIG. 1 can be referred to as a communication device with a UE function.

[0112] As introduced above, the communication system to which the embodiments of the present application are applicable is described, and for the convenience of understanding the technical solutions provided by the embodiments of the present application, the related technical terms involved in the embodiments of the present application are first explained below. It should be noted that these explanations are for the convenience of the embodiments of the present application being more easily understood, and should not be regarded as limiting the scope of protection claimed by the present application.

[0113] (1) LP-SS

[0114] The synchronization signal received through the LP interface can be referred to as LP-SS. The LP interface can be understood as being set for reducing power consumption, for example, the LP interface is implemented through a simple structure circuit or chip, and has low power consumption. The specific form of the LP interface is not limited by the embodiments of the present application. For example, the LP interface can be implemented through a wake up receiver (WUR), a low power wake up receiver (LP-WUR), a low-power radio (LR), a wake up module or a wake up circuit. The WUR in this paper can be a wake up radio, a wake up receiver. The WUR in this paper can be replaced by the LP-WUR, the LR, the wake up module or the wake up circuit.

[0115] (2) Generation process of OOK-4 waveform

[0116] It should be understood that on off keying (OOK) modulation utilizes the presence or absence of a signal to represent digital information, and the bit information corresponding to the signal is mapped to at least one time unit through OOK modulation. The bit information of the signal is determined by detecting whether there is a signal on the time unit. The presence of a signal on a time unit means that the signal amplitude on the time unit is not zero, such time unit is also called ON time unit, or the time unit is in ON mode; correspondingly, the presence of a signal on a time unit means that the signal amplitude on the time unit is zero, such time unit is also called OFF time unit, or the time unit is in OFF mode. Generally, if a sequence is transmitted on a time unit, the time unit has a signal; if no sequence is transmitted on a time unit, the time unit has no signal. For a time unit, the time unit is an ON time unit or the time unit is in ON mode, which can be decoded as 1; correspondingly, the time unit is an OFF time unit or the time unit is in OFF mode, which can be decoded as 0. In OOK, the time unit is a symbol, and correspondingly, the ON time unit is an ON symbol, and the OFF time unit is an OFF symbol.

[0117] OOK-4 refers to an OOK modulation mode in which the total number of ON symbols and / or OFF symbols carried on one OFDM symbol is M, that is, each OFDM symbol can carry M bits through ON / OFF symbols. For example, M = 2, 4 or 8.

[0118] In the embodiments of the present application, the LP-SS supports the OOK-4 waveform, or the data corresponding to the LP-SS is transmitted through the OOK-4 waveform, or the LP-SS supports the OOK-4 modulation mode.

[0119] [According to Rule 91 correction 16.10.2025] Please refer to FIG. 2, which is a schematic diagram of the generation process of the OOK-4 waveform. FIG. 2 takes M = 4 as an example, as shown in FIG. 2, the generation of the OOK-4 waveform includes steps ①-⑥, wherein step ③ is optional, that is, it is not a mandatory step. The symbols in FIG. 2 refer to OFDM symbols unless otherwise specified.

[0120] Step ①: Obtain a sequence used to generate the LP-SS, for example, sequence X.

[0121] Step ②: Map all bits included in the sequence X to at least one OFDM symbol, for example, M = 4, and each OFDM symbol can carry 4 bits.

[0122] Step ③: Map bit 0 included in the sequence X to [0, 1], and map bit 1 included in the sequence X to [1, 0]; or map bit 0 included in the sequence X to [1, 0], and map bit 1 included in the sequence X to [0, 1]. That is, perform a Manchester encoding operation on the sequence X.

[0123] Step ④: In the time domain position of bit 0, a sequence of all 0s is used; in the time domain position of bit 1, a complex sequence is used.

[0124] Step ⑤: Perform discrete Fourier transform (DFT) on the time domain signal to obtain a frequency domain signal, and then map the frequency domain signal to the RE positions (for example, RE0-RE N-1) of the LP-SS.

[0125] Step ⑥: Perform inverse fast Fourier transform (IFFT) on the sequence obtained in step ⑤, and add a CP to the sequence obtained through the IFFT, to obtain an OFDM symbol of the LP-SS.

[0126] (3) gold sequence

[0127] The gold sequence is obtained by modulo 2 addition of two m-sequences, i.e., m-sequence 1 and m-sequence 2. Alternatively, the gold sequence can be regarded as a sequence obtained by performing element-wise XOR of two m-sequences with different primitive polynomials. The primitive polynomials will be described below.

[0128] wherein the m-sequence is a short form of the longest linear shift register, and the m-sequence is the longest code sequence generated by a multi-stage shift register or a delay element thereof through linear feedback. In a binary shift register, if k is the number of stages of the shift register, the k-stage shift register has 2 k -1 states, except for the all-zero state, leaving 2 k -1 states. Therefore, the maximum length of the sequence generated by the k-stage linear feedback shift register is 2 k -1, that is, the longest period of the k-stage linear feedback shift register is equal to 2 k -1.

[0129] For example, referring to FIG. 3, there is shown a schematic diagram of a code sequence generator composed of a k-stage shift register. In FIG. 3, x0-x k-1 are k shift registers, and C0, C1,..., Ck are feedback coefficients. It should be understood that the m-sequence is generated by a cyclic sequence generator, and therefore, C0and Cnare 1, indicating that they participate in feedback. C1, C2,..., Ck-1, if 1, indicate that they participate in feedback, and if 0, indicate that they do not participate in feedback, i.e., the feedback link is disconnected. The state of the register is determined by the input information ("0" or "1") under the control of the clock, for example, the state of the ith-stage shift register is determined by the state of the (i-1)th-stage shift register after the previous clock pulse.

[0130] According to FIG. 3, we have: mod is a modulo operation. The formula can be equivalent to: Correspondingly, the characteristic polynomial F(x) of the k-stage shift register satisfies: C i ∈{0,1}, the length of the m-sequence is N=2 k -1. Wherein the power of x represents the position of the element included in the sequence.

[0131] When F(x) satisfies the following three conditions, the m-sequence can be generated: (1) F(x) is irreducible, i.e., F(x) is a polynomial that cannot be further decomposed; (2) F(x) is divisible by x p +1, p=2 n -1; (3) F(x) is not divisible by x q +1, q<p. The characteristic polynomial satisfying the above three conditions is also called a primitive polynomial.

[0132] Taking k=5 as an example, the primitive polynomial of the m-sequence is: F(x)=x 5 +x 2 +1; F(x)=x 5 +x 3 +1; F(x)=x 5 +x 3 +x 2 +x+1; F(x)=x 5 +x 4 +x 2 +x+1; F(x)=x 5 +x 4 +x 3 +x+1; F(x)=x 5 +x 4 +x 3 +x 2 +1. Accordingly, the element x(i+5) in the m-sequence with length 31 when k=5 satisfies any one of the following, and it can also be considered that the m-sequence with length 31 has the following six generating modes M5_1-M5_6.

[0133] M5_1: x(i+5)=(x(i+2)+x(i))mod 2;

[0134] M5_2: x(i+5)=(x(i+3)+x(i))mod 2;

[0135] M5_3: x(i+5)=(x(i+3)+x(i+2)+x(i+1)+x(i))mod 2;

[0136] M5_4: x(i+5)=(x(i+4)+x(i+2)+x(i+1)+x(i))mod 2;

[0137] M5_5: x(i+5)=(x(i+4)+x(i+3)+x(i+1)+x(i))mod 2;

[0138] M5_6: x(i+5)=(x(i+4)+x(i+3)+x(i+2)+x(i))mod 2.

[0139] Similarly, k=7, the element x(i+7) in the m-sequence with length 127 satisfies any one of the following, and it can also be considered that the m-sequence with length 127 has the following 18 generating modes M7_1-M7_18.

[0140] M7_1: x(i+7)=(x(i+1)+x(i))mod 2;

[0141] M7_2: x(i+7) = (x(i+3) + x(i)) mod 2;

[0142] M7_3: x(i+7) = (x(i+3) + x(i+2) + x(i+1) + x(i)) mod 2;

[0143] M7_4: x(i+7) = (x(i+4) + x(i)) mod 2;

[0144] M7_5: x(i+7) = (x(i+4) + x(i+3) + x(i+2) + x(i)) mod 2;

[0145] M7_6: x(i+7) = (x(i+5) + x(i+2) + x(i+1) + x(i)) mod 2;

[0146] M7_7: x(i+7) = (x(i+5) + x(i+3) + x(i+1) + x(i)) mod 2;

[0147] M7_8: x(i+7) = (x(i+5) + x(i+4) + x(i+3) + x(i)) mod 2;

[0148] M7_9: x(i+7) = (x(i+5) + x(i+4) + x(i+3) + x(i+2) + x(i+1) + x(i)) mod 2;

[0149] M7_10: x(i+7) = (x(i+6) + x(i)) mod 2;

[0150] M7_11: x(i+7) = (x(i+6) + x(i+3) + x(i+1) + x(i)) mod 2;

[0151] M7_12: x(i+7) = (x(i+6) + x(i+4) + x(i+1) + x(i)) mod 2;

[0152] M7_13: x(i+7) = (x(i+6) + x(i+4) + x(i+2) + x(i)) mod 2;

[0153] M7_14: x(i+7) = (x(i+6) + x(i+5) + x(i+2) + x(i)) mod 2;

[0154] M7_15: x(i+7) = (x(i+6) + x(i+5) + x(i+3) + x(i+2) + x(i+1) + x(i)) mod 2;

[0155] M7_16: x(i+7) = (x(i+6) + x(i+5) + x(i+4) + x(i)) mod 2;

[0156] M7_17: x(i+7) = (x(i+6) + x(i+5) + x(i+4) + x(i+2) + x(i+1) + x(i)) mod 2;

[0157] M7_18: x(i+7) = (x(i+6) + x(i+5) + x(i+4) + x(i+3) + x(i+2) + x(i)) mod 2.

[0158] Similarly, k = 6, the element x(i+6) in the m-sequence of length 63 satisfies any of the following, it can also be considered that the m-sequence of length 63 has the following M6_1~M6_6 six generating ways.

[0159] M6_1: x1(i+6) = (x1(i+1) + x1(i)) mod 2;

[0160] M6_2: x1(i+6) = (x1(i+5) + x1(i)) mod 2;

[0161] M6_3: x1(i+6) = (x1(i+4) + x1(i+3) + x1(i+1) + x1(i)) mod 2;

[0162] M6_4: x1(i+6) = (x1(i+4) + x1(i+3) + x1(i+1) + x1(i)) mod 2;

[0163] M6_5: x1(i+6) = (x1(i+5) + x1(i+2) + x1(i+1) + x1(i)) mod 2;

[0164] M6_6: x1(i+6) = (x1(i+5) + x1(i+4) + x1(i+1) + x1(i)) mod 2.

[0165] Similarly, k = 4, the element x(i+4) in the m-sequence of length 14 satisfies any of the following, it can also be considered that the m-sequence of length 63 has the following M4_1~M4_2 two generating ways.

[0166] M4_1: x(i+4) = (x(i+1) + x(i)) mod 2

[0167] M4_2: x(i+4) = (x(i+3) + x(i)) mod 2

[0168] Two m-sequences (also referred to as an m-sequence pair) satisfying certain conditions can be selected from a plurality of m-sequences and added modulo 2 to obtain a gold sequence. For example, the cross-correlation |R ab (τ)| between the two selected m-sequences satisfies:

[0169] Using the above example, two m-sequences satisfying the above conditions are shown in Table 1. In Table 1, one row represents two m-sequences satisfying the above conditions, which can be used to construct a gold sequence.

[0170] Table 1

[0171] It can be understood that the complexity of generating a gold sequence by an m-sequence pair with fewer taps is lower. In a shift register, data is moved out from the output end and new data is moved in from the input end in a shift operation. A tap is a specific position from which data is taken out from the shift register. Accordingly, the number of taps refers to the number of specific positions from which data is taken out from the shift register.

[0172] (4) Time unit

[0173] A time unit refers to a unit of time. The time unit can be a radio frame, a subframe, a slot, a mini-slot, an OFDM symbol, a millisecond (ms), or a fractional millisecond (e.g., 1 / 32 ms). Alternatively, the time unit is a plurality of slots, a plurality of subframes, a plurality of mini-slots, a plurality of OFDM symbols, a plurality of milliseconds (ms), or a plurality of fractional milliseconds. In this case, one radio frame can include a plurality of subframes, one subframe can include one or more slots, and one slot can include at least one symbol. Alternatively, one radio frame can include a plurality of slots, and one slot can include at least one symbol.

[0174] (5) Cyclic prefix / CP

[0175] A cyclic prefix / CP is a signal copied from the tail of an OFDM symbol to the head. The CP can be classified into various types according to the length thereof. For example, one type of CP is a normal cyclic prefix (NCP) having a length of 4.7 microseconds (us), and another type of CP is an extended cyclic prefix (ECP) having a length of 16.67 us.

[0176] (6) In the embodiments of the present application, "transmit" includes "send" and / or "receive". Wherein, "send" and "receive" represent the direction of signal transmission. For example, "send information to XX" can be understood as that the destination of the information is XX, which can include direct sending through the air interface, and also includes indirect sending through the air interface by other units or modules. "Receive information from YY" can be understood as that the source of the information is YY, which can include direct receiving from YY through the air interface, and also includes indirect receiving from YY through the air interface by other units or modules. "Send" can also be understood as "output" of the chip interface, and "receive" can also be understood as "input" of the chip interface. In other words, sending and receiving can be carried out between devices, for example, between an access network device and a terminal device, or can be carried out within a device, for example, between components, between modules, between chips, between software modules or hardware modules in the device through a bus, a wire or an interface.

[0177] In the embodiments of the present application, the number of nouns represents "singular noun or plural noun", that is, "one or more" unless otherwise specified. "At least one" means one or more, and "multiple" means two or more. "And / or" describes the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B can represent the following three cases: A exists alone, A and B exist together, and B exists alone, wherein A / B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects. For example, A / B means A or B. "At least one of the following" or the like means any combination of these items, including any combination of single item or multiple items. For example, at least one of a, b and / or c means the following combinations: a exists alone, b exists alone, c exists alone, a and b exist together, a and c exist together, b and c exist together, or a, b and c exist together, wherein a, b and c can be single or multiple.

[0178] In the embodiments of the present application, "when", "if" and "whether" all mean that the device will make corresponding processing under certain objective circumstances, and are not limited to time, and do not require the device to have a judgment action when it is implemented, nor mean that there are other limitations. Unless otherwise specified, "if" and "if" can be replaced, and "when" and "in the case of" can be replaced. "When" and "if" / "if" can be replaced.

[0179] In the embodiments of the present application, the word "exemplary" or "for example" is used to mean serving as an example, instance, or illustration, and not necessarily to imply any preference or superiority. In fact, an "exemplary" or "for example" embodiment or design scheme is presented in a concrete manner only for the sake of clarity and illustration, and not necessarily for any other purpose.

[0180] The ordinal numbers "first", "second", etc. mentioned in the embodiments of the present application are used to distinguish different objects, and are not used to limit the size, content, order, timing, priority or importance of the objects. For example, the first sequence and the second sequence refer to two different sequences, and do not mean that the priority or importance of the two sequences is different.

[0181] In the embodiments of the present application, the schemes in the embodiments can be reasonably combined, and the explanation or description of each term appearing in the embodiments, similar operations, or steps can be mutually referenced or explained in each embodiment, and this is not limited.

[0182] Before data transmission, the network device and the terminal device perform time synchronization and frequency synchronization. For example, the network device sends SS generated based on a specific sequence, and the terminal device detects the SS based on the specific sequence to achieve time synchronization and frequency synchronization between the terminal device and the network device. In order to reduce the power consumption of the terminal device, LP-SS is introduced, the network device sends LP-SS to the terminal device, and the terminal device checks the LP-SS to achieve time synchronization and frequency synchronization between the terminal device and the network device.

[0183] The specific sequence used to generate the SS includes an m-sequence and a gold sequence. At present, it is proposed that the m-sequence and the gold sequence can also be used as a sequence for generating the LP-SS. However, due to the difference between the generation processes of the LP-SS and the SS, if any m-sequence or gold sequence used to generate the SS is followed for the LP-SS, the synchronization detection performance (for example, timing estimation performance) of the LP-SS may be relatively low. For the convenience of understanding, the following is explained and described in combination with the drawings.

[0184] Generally, in order to improve the timing estimation performance of the SS, a CP is added in the generation of the SS. In order to reduce the processing complexity of the network device, a CP can also be added in the generation of the LP-SS. In this way, for the SS and the LP-SS, the network device can generate the synchronization signal based on a set of generation mechanisms, and the processing complexity is relatively low. However, the LP-SS is transmitted based on the OOK-4 waveform, and the addition of the CP will affect the timing estimation performance of the LP-SS. As can be seen from the foregoing generation process of the OOK-4 waveform, the OOK-4 waveform is converted from a time domain signal to a frequency domain signal through DFT, and then a CP is added after IFFT is performed on the sequence in the frequency domain. The sequence (for example, an m sequence / gold sequence) used to generate the LP-SS is binary, and the CP is also binary. If the CP is reserved for correlation detection, the CP will affect the autocorrelation of the sequence, and the synchronization detection performance will be affected.

[0185] For example, referring to FIG. 4, an illustration of the influence of the CP on the autocorrelation of the gold sequence is shown. In FIG. 4, the horizontal axis represents the index of the gold sequence, and the vertical axis represents the signal to noise ratio (SNR) corresponding to the proportion of the timing estimation error greater than 1us being 1%, that is, the SNR working point. The lower the SNR working point, the better the timing estimation performance. As can be seen from FIG. 4, different gold sequences correspond to different SNR working points, and the timing estimation performance is different.

[0186] Referring to FIG. 5, an illustration of the influence of the CP on the autocorrelation of different sequences is shown. In FIG. 5, the horizontal axis represents the autocorrelation time, and the vertical axis represents the autocorrelation peak value. As can be seen from FIG. 5, the decline speed of the autocorrelation peak value of different gold sequences is different. Accordingly, referring to FIG. 6, the first trough in FIG. 5 is shown. In FIG. 6, the horizontal axis represents the sequence index, and the vertical axis represents the value of the first trough. As can be seen from FIG. 6, the timing estimation performance of different gold sequences is strongly related to the value of the first trough, and the lower the value of the first trough, the better the timing estimation performance.

[0187] In addition, Manchester coding is performed on the gold sequence, which can also improve the autocorrelation of the gold sequence and improve the timing estimation performance. For example, referring to FIG. 7, an illustration of the influence of Manchester coding on the autocorrelation of the gold sequence is shown. In FIG. 7, the horizontal axis represents the autocorrelation time, and the vertical axis represents the normalized autocorrelation value. As can be seen from FIG. 7, after Manchester coding is performed, the main lobe width of the autocorrelation function is narrowed, which is beneficial to timing estimation.

[0188] As can be seen from FIG. 4 to FIG. 6, the addition of the CP will affect the autocorrelation of the sequence. In addition, a sequence can obtain a new sequence after cyclic shift m0, and different m0 will result in different autocorrelation of the sequence, and further result in different synchronization detection performance of the LP-SS. Therefore, for the LP-SS, if an arbitrary m sequence or gold sequence used for generating the SS is followed, the synchronization detection performance of the LP-SS cannot be guaranteed.

[0189] In view of this, the scheme of the embodiments of the present application is provided. The embodiments of the present application determine a suitable m sequence / gold sequence according to the factors affecting the synchronization detection performance of the LP-SS, so as to guarantee that the determined m sequence / gold sequence can guarantee the synchronization detection performance of the LP-SS. As mentioned above, the factors affecting the synchronization detection performance of the LP-SS include the waveform parameter of the LP-SS, the type of the CP, and whether the Manchester coding is used. The waveform parameter of the LP-SS includes, for example, the number of time units occupied by the sequence, the number of bits M carried by each time unit, the subcarrier spacing, and the like. If not otherwise specified, the time unit occupied by the sequence refers to the OFDM symbol (hereinafter taken as an example).

[0190] For example, if the gold sequence is taken as the sequence for generating the LP-SS, a suitable gold sequence (or m sequence pair) can be selected based on one or more of the following factors, so as to improve the synchronization detection performance of the LP-SS as much as possible. The m sequence pair refers to two m sequences used for generating the gold sequence. Further, an m sequence pair with a smaller number of taps can be selected, so as to reduce the complexity of generating the gold sequence. In addition, a sequence can obtain a new sequence after cyclic shift m0, and different m0 will result in different autocorrelation of the sequence. Therefore, a suitable part of the values of m0 can be selected from all candidate values of m0, so as to guarantee the optimal synchronization detection performance as much as possible.

[0191] For another example, if the m sequence is taken as the sequence for generating the LP-SS, considering that the autocorrelation characteristics of the m sequence caused by different initial values of the m sequence are different, a suitable initial value of the m sequence can be determined based on one or more of the following factors, so as to improve the synchronization detection performance of the LP-SS as much as possible. Further, considering the interference between adjacent intervals, different initial values and generation modes of m0 are used in adjacent cells, so as to guarantee the orthogonality of the LP-SS between adjacent cells, and reduce the interference between cells as much as possible.

[0192] The scheme provided by the embodiments of the present application will be described below in combination with the drawings and specific embodiments. In the following description, the sequence used for generating the LP-SS is referred to as the first sequence. The first sequence can be a gold sequence or an m sequence.

[0193] Embodiment one: the first sequence is a gold sequence.

[0194] The LP-SS can be obtained based on the first sequence, that is, the sequence used to generate the LP-SS is the first sequence. The network device can generate the LP-SS based on the first sequence before transmitting the LP-SS to the terminal device. Wherein, the generation of the LP-SS and the transmission of the LP-SS can be implemented by different functional entities constituting the network device. For example, the LP-SS can be generated by the DU and transmitted by the RU. Of course, the generation of the LP-SS and the transmission of the LP-SS can also be implemented by the same functional entity constituting the network device, for example, the LP-SS is generated by the RU and transmitted by the RU.

[0195] It can be understood that if the first sequence is a gold sequence, the first sequence can be generated by two m-sequences (for example, the second sequence and the third sequence). For example, the first sequence LP_SS satisfies: LP_SS = (x0+x1) mod 2, wherein x0 is the second sequence, x1 is the third sequence, and mod is a modulo operation. For another example, the first sequence LP_SS(n) satisfies: LP_SS(n) = [x0(n)+x1((n+m0) mod N)] mod 2; wherein x0(n) is the second sequence, x1(n) is the third sequence, m0 is a cyclic shift, n is an integer greater than or equal to 0 and less than N, N is the length of the second sequence and the third sequence, N = 2 k -1, k is a positive integer, and mod is a modulo operation.

[0196] For the SS, the available m-sequences are defined. As described above, due to the influence of the CP on the autocorrelation of the sequence, the LP-SS cannot guarantee a better synchronization detection performance if the m-sequences suitable for the SS are followed. Therefore, in the embodiments of the present application, the m-sequences suitable for the LP-SS can be selected from the existing m-sequences, and then the first sequence is generated based on the selected m-sequences, so as to generate the LP-SS based on the first sequence.

[0197] As described above, the factors affecting the synchronization detection performance of the LP-SS include the number of OFDMs occupied by the sequence, the number of bits M carried by each OFDM, the subcarrier spacing, or the type of CP. Therefore, one or more of these factors can be used to determine a suitable first sequence, so as to guarantee that the synchronization detection performance of the LP-SS generated based on the first sequence is better. In other words, the first sequence is related to one or more of the following: the number of OFDMs occupied by the first sequence, the number of bits M carried by each OFDM, the subcarrier spacing, or the type of CP.

[0198] Since the first sequence is generated from the second sequence and the third sequence, the second sequence is also related to one or more of the following: the number of OFDMs occupied by the second sequence, the number of bits M carried by each OFDM, the subcarrier spacing, or the type of CP; the third sequence is also related to one or more of the following: the number of OFDMs occupied by the third sequence, the number of bits M carried by each OFDM, the subcarrier spacing, or the type of CP. The second sequence and the third sequence can be determined based on one or more of the above factors, and then the first sequence is determined according to the second sequence and the third sequence.

[0199] Wherein, determining the second sequence and the third sequence based on one or more of the above factors means: selecting appropriate second sequence and third sequence from the available m sequence set based on one or more of the above factors. Here, the available m sequence can be an m sequence that has been defined, for example, an m sequence that has been defined in NR.

[0200] In possible implementation manners, the network device can store the second sequence and the third sequence. When the network device needs to send the LP-SS to the terminal device, the network device can generate the first sequence according to the stored second sequence and the third sequence, and then generate the LP-SS according to the first sequence. Alternatively, the network device can store the first sequence obtained based on the second sequence and the third sequence. When the network device needs to send the LP-SS to the terminal device, the network device generates the LP-SS according to the stored first sequence.

[0201] A plurality of lengths of m sequences can be defined, and there are a plurality of m sequences for each length. For any length of m sequence, a plurality of m sequence pairs can be determined based on one or more of the above factors, wherein each m sequence pair includes two m sequences, and the two m sequences can generate a first sequence. According to the difference of the length N of the m sequence (i.e., the second sequence and the third sequence), the number of bits M carried on each OFDM symbol, and the degree k of the primitive polynomial used to generate the m sequence, the second sequence and the third sequence (or the first sequence) are also different. In addition, as mentioned above, the cyclic shift m0 also affects the autocorrelation of the sequence, and under different generation modes of the m sequence, a suitable m0 can be selected to improve the synchronization detection performance of the LP-SS. The following specific examples list possible second sequences and third sequences, and the value range of m0.

[0202] It should be noted that each row in each of the following Tables 2-7 corresponds to an m sequence pair (i.e., a second sequence and a third sequence), and each m sequence corresponds to a value range of m0. Any m sequence in Tables 2-7 can ensure relatively optimal synchronization detection performance of the LP-SS. Further, the value range of m0 corresponding to each m sequence can also improve the relatively optimal synchronization detection performance as much as possible.

[0203] Tables 2-7 can be pre-defined or (pre-)configured by a protocol. For any table, the network device and the terminal device can store the table, or can store part of the rows in the table. Which rows in the table are stored will be introduced later, and is not introduced here. Alternatively, the network device and the terminal device can store the gold sequences generated by the m-sequence pairs in each row in the table and the value range of m0 corresponding to the m-sequence pair. Alternatively, the network device and the terminal device can store the gold sequences generated by the m-sequence pairs in part of the rows in the table and the value range of m0 corresponding to the m-sequence pair.

[0204] Alternatively, the network device and the terminal device can only store the m-sequence pairs in the table, and not store the value range of m0 therein. Alternatively, the network device and the terminal device can only store the gold sequences generated by the m-sequence pairs in the table, and not store the value range of m0 therein. In this case, the value range of m0 corresponding to each m-sequence pair can be 0-126.

[0205] Example 1-1: k=7, N=127, M=8.

[0206] In example 1-1, the first sequence LP_SS(n) can satisfy: LP_SS(n)=[x0(n)+x1((n+m0)mod 127)]mod 2. The initial values of the second sequence x0(n) and the third sequence x1(n) are not limited. For example, the initial value of x0(n) can be [0, 0, 0, 0, 0, 0, 1], and the initial value of x1(n) can be [0, 0, 0, 0, 0, 0, 1]. In this case, the value range of the second sequence and the third sequence and m0 is shown in Table 2.

[0207] Table 2

[0208] Alternatively, an m-sequence pair with fewer taps can be selected to reduce the complexity of generating a gold sequence, thereby reducing the complexity of generating an LP-SS. For example, the m-sequence pair with fewer taps can be (M7_1, M7_2), (M7_1, M7_4), (M7_2, M7_10), or (M7_4, M7_10), etc. Correspondingly, the network device and the terminal device can store the row corresponding to the m-sequence pair with fewer taps in Table 1, or the network device and the terminal device can store a table (for example, referred to as Table 2-1) formed by the row corresponding to the m-sequence pair with fewer taps in Table 2. Alternatively, the network device and the terminal device can only store the m-sequence pairs in Table 2-1, or only store the gold sequences generated by the m-sequence pairs in Table 2-1.

[0209] Example 1-2: k = 6, N = 63, M = 8.

[0210] In Example 1-2, the first sequence LP SS(n) can satisfy: LP SS(n) = [x0(n) + x1((n + m0) mod 63)] mod 2. The initial values of the second sequence x0(n) and the third sequence x1(n) are not limited. For example, the initial value of x0(n) can be [0, 0, 0, 0, 0, 1], and the initial value of x1(n) can be [0, 0, 0, 0, 0, 1]. In this case, the value ranges of the second sequence and the third sequence and m0 are shown in Table 3.

[0211] Table 3

[0212] Alternatively, a less-tap m-sequence pair can be selected to reduce the complexity of generating a gold sequence, thereby reducing the complexity of generating an LP-SS. For example, the less-tap m-sequence pair can include (M6_1, M6_2), etc. Accordingly, the network device and the terminal device can store the rows corresponding to the less-tap m-sequence pair(s) in Table 3, or the network device and the terminal device can store a table (for example, referred to as Table 3-1) formed by the rows corresponding to the less-tap m-sequence pair(s) in Table 3. Alternatively, the network device and the terminal device can only store the m-sequence pairs in Table 3-1, or only store the gold sequences generated by the m-sequence pairs in Table 3-1.

[0213] Example 1-3: k = 6, N = 63, M = 4.

[0214] In Example 1-3, the first sequence LP SS(n) can satisfy: LP SS(n) = [x0(n) + x1((n + m0) mod 63)] mod 2. The initial values of the second sequence x0(n) and the third sequence x1(n) are not limited. For example, the initial value of x0(n) can be [0, 0, 0, 0, 0, 1], and the initial value of x1(n) can be [0, 0, 0, 0, 0, 1]. In this case, the value ranges of the second sequence and the third sequence and m0 are shown in Table 4.

[0215] Table 4

[0216] Optionally, m-sequence pairs with less taps can be selected to reduce the complexity of generating gold sequences, and thus reduce the complexity of generating LP-SS. For example, m-sequence pairs with less taps can include (M6_1, M6_2), and the like. Accordingly, the network device and the terminal device can store the rows corresponding to one or more m-sequence pairs with less taps in Table 4, or the network device and the terminal device can store a table (e.g., referred to as Table 4-1) formed by the rows corresponding to one or more m-sequence pairs with less taps in Table 4. Alternatively, the network device and the terminal device can only store the m-sequence pairs in Table 4-1, or only store the gold sequences generated by the respective m-sequence pairs in Table 4-1.

[0217] Example 1-4: k = 5, N = 31, M = 4.

[0218] In Example 1-4, the first sequence LP_SS(n) can satisfy: LP SS(n) = [x0(n) + x1((n + m0) mod 31)] mod 2. The initial values of the second sequence x0(n) and the third sequence x1(n) are not limited. For example, the initial value of x0(n) can be [0, 0, 0, 0, 1], and the initial value of x1(n) can be [0, 0, 0, 0, 1]. In this case, the value ranges of the second sequence and the third sequence and m0 are shown in Table 5.

[0219] Table 5

[0220] Optionally, m-sequence pairs with less taps can be selected to reduce the complexity of generating gold sequences, and thus reduce the complexity of generating LP-SS. For example, m-sequence pairs with less taps can include (M5_1, M5_2), (M5_1, M5_4), (M5_1, M5_5), (M5_1, M5_6), (M5_2, M5_3), (M5_2, M5_4), (M5_2, M5_5), (M5_2, M5_6), and the like. Accordingly, the network device and the terminal device can store the rows corresponding to one or more m-sequence pairs with less taps in Table 5, or the network device and the terminal device can store a table (e.g., referred to as Table 5-1) formed by the rows corresponding to one or more m-sequence pairs with less taps in Table 5. Alternatively, the network device and the terminal device can only store the m-sequence pairs in Table 5-1, or only store the gold sequences generated by the respective m-sequence pairs in Table 5-1.

[0221] Example 1-5: k = 5, N = 31, M = 2.

[0222] In Example 1-5, the first sequence LP_SS(n) can satisfy: LP SS(n)= [x0(n) + x1((n + m0) mod 31)] mod 2. The initial values of the second sequence x0(n) and the third sequence x1(n) are not limited. For example, the initial value of x0(n) can be [0, 0, 0, 0, 0, 1], and the initial value of x1(n) can be [0, 0, 0, 0, 0, 1]. In this case, the second sequence and the third sequence and the value range of m0 are shown in Table 6.

[0223] Table 6

[0224] Alternatively, a pair of m-sequences with fewer taps can be selected to reduce the complexity of generating a gold sequence, and thus reduce the complexity of generating an LP-SS. For example, a pair of m-sequences with fewer taps can include (M5_1, M5_2), (M5_1, M5_4), (M5_1, M5_5), (M5_1, M5_6), (M5_2, M5_3), (M5_2, M5_4), (M5_2, M5_5), (M5_2, M5_6), and the like. Accordingly, the network device and the terminal device can store the rows corresponding to the one or more pairs of m-sequences with fewer taps in Table 6, or the network device and the terminal device can store a table (for example, referred to as Table 6-1) formed by the rows corresponding to the one or more pairs of m-sequences with fewer taps in Table 6. Alternatively, the network device and the terminal device can only store the pairs of m-sequences in Table 6-1, or only store the gold sequences generated by the pairs of m-sequences in Table 6-1.

[0225] Example 1-6: k = 4, N = 15, M = 2.

[0226] In Example 1-6, the first sequence LP_SS(n) can satisfy: LP SS(n) = [x0(n) + x1((n + m0) mod 15)] mod 2. The initial values of the second sequence x0(n) and the third sequence x1(n) are not limited. For example, the initial value of x0(n) can be [0, 0, 0, 1], and the initial value of x1(n) can be [0, 0, 0, 1]. In this case, the second sequence and the third sequence and the value range of m0 are shown in Table 7.

[0227] Table 7

[0228] In possible implementations, the first sequence can be Manchester coded in the generation of the LP-SS, to further improve the synchronization detection performance. In this case, the second sequence and the third sequence (or the first sequence) are different, and the applicable value range of m0 is also different, according to the length N of the m-sequence (i.e., the second sequence and the third sequence), the number of bits M carried on each OFDM symbol, and the order k of the primitive polynomial used to generate the m-sequence. The following lists possible second sequences and third sequences, and the value range of m0, with specific examples.

[0229] It should be noted that each row in each of the following Tables 8-12 corresponds to an m-sequence pair (i.e., the second sequence and the third sequence), and each m-sequence corresponds to a value range of m0. Any m-sequence in Tables 8-12 can guarantee the optimal synchronization detection performance of the LP-SS. Further, the value range of m0 corresponding to each m-sequence can also improve the optimal synchronization detection performance as much as possible.

[0230] Tables 8-12 can be protocol predefined or (pre)configured. For any table, the network device and the terminal device can store the table, or can store part of the rows in the table. It is not introduced here which rows of the table are stored specifically, and will be introduced later. Alternatively, the network device and the terminal device can store the gold sequence generated by the m-sequence pair in each row of the table and the value range of m0 corresponding to the m-sequence pair. Alternatively, the network device and the terminal device can store the gold sequence generated by the m-sequence pair in part of the rows in the table and the value range of m0 corresponding to the m-sequence pair.

[0231] Alternatively, the network device and the terminal device can only store the m-sequence pair in the table, without storing the value range of m0 therein. Alternatively, the network device and the terminal device can only store the gold sequence generated by the m-sequence pair in the table, without storing the value range of m0 therein. In this case, the value range of m0 corresponding to each m-sequence pair can be 0-126.

[0232] Example 2-1: k = 6, N = 63, M = 8.

[0233] In Example 2-1, the first sequence LP_SS(n) can satisfy: LP_SS(n) = [x0(n) + x1((n + m0) mod 63)] mod 2. The initial values of the second sequence x0(n) and the third sequence x1(n) are not limited. For example, the initial value of x0(n) can be [0, 0, 0, 0, 0, 1], and the initial value of x1(n) can be [0, 0, 0, 0, 0, 1]. In this case, the second sequence and the third sequence and the value range of m0 are shown in Table 8.

[0234] Table 8

[0235] Alternatively, m-sequence pairs with fewer taps can be selected to reduce the complexity of generating gold sequences, and thus the complexity of generating LP-SSs. For example, m-sequence pairs with fewer taps can include (M6_1, M6_2), and the like. Accordingly, the network device and the terminal device can store the rows corresponding to the one or more m-sequence pairs with fewer taps in Table 8, or the network device and the terminal device can store a table (e.g., referred to as Table 8-1) formed by the rows corresponding to the one or more m-sequence pairs with fewer taps in Table 8. Alternatively, the network device and the terminal device can store only the m-sequence pairs in Table 8-1, or only the gold sequences generated by the respective m-sequence pairs in Table 8-1.

[0236] Example 2-2: k = 5, N = 31, M = 8.

[0237] In Example 2-2, the first sequence LP_SS(n) can satisfy: LP_SS(n) = [x0(n) + x1((n + m0) mod 31)] mod 2. The initial values of the second sequence x0(n) and the third sequence x1(n) are not limited. For example, the initial value of x0(n) can be [0, 0, 0, 0, 1], and the initial value of x1(n) can be [0, 0, 0, 0, 1]. In this case, the second sequence and the third sequence and the value range of m0 are shown in Table 9.

[0238] Table 9

[0239] Alternatively, m-sequence pairs with fewer taps can be selected to reduce the complexity of generating gold sequences, and thus the complexity of generating LP-SSs. For example, m-sequence pairs with fewer taps can include (M5_1, M5_3), (M5_1, M5_4), and the like. Accordingly, the network device and the terminal device can store the rows corresponding to the one or more m-sequence pairs with fewer taps in Table 9, or the network device and the terminal device can store a table (e.g., referred to as Table 9-1) formed by the rows corresponding to the one or more m-sequence pairs with fewer taps in Table 9. Alternatively, the network device and the terminal device can store only the m-sequence pairs in Table 9-1, or only the gold sequences generated by the respective m-sequence pairs in Table 9-1.

[0240] Example 2-3: k = 5, N = 31, M = 4.

[0241] In Example 2-3, the first sequence LP SS(n) can satisfy: LP SS(n) = [x0(n) + x1((n + m0) mod 31)] mod 2. The initial values of the second sequence x0(n) and the third sequence x1(n) are not limited. For example, the initial value of x0(n) can be [0, 0, 0, 0, 0, 1], and the initial value of x1(n) can be [0, 0, 0, 0, 0, 1]. In this case, the second sequence and the third sequence and the value range of m0 are shown in Table 10.

[0242] Table 10

[0243] Alternatively, a less-tap m-sequence pair can be selected to reduce the complexity of generating a gold sequence, and thus reduce the complexity of generating an LP-SS. For example, the less-tap m-sequence pair can include (M5_1, M5_3), (M5_1, M5_4), and the like. Accordingly, the network device and the terminal device can store the rows corresponding to the one or more less-tap m-sequence pairs in Table 10, or the network device and the terminal device can store a table (for example, referred to as Table 10-1) formed by the rows corresponding to the one or more less-tap m-sequence pairs in Table 10. Alternatively, the network device and the terminal device can only store the m-sequence pairs in Table 10-1, or only store the gold sequences generated by the respective m-sequence pairs in Table 10-1.

[0244] Example 2-4: k = 4, N = 15, M = 4.

[0245] In Example 2-4, the first sequence LP SS(n) can satisfy: LP SS(n) = [x0(n) + x1((n + m0) mod 15)] mod 2. The initial values of the second sequence x0(n) and the third sequence x1(n) are not limited. For example, the initial value of x0(n) can be [0, 0, 0, 0, 1], and the initial value of x1(n) can be [0, 0, 0, 0, 1]. In this case, the second sequence and the third sequence and the value range of m0 are shown in Table 11.

[0246] Table 11

[0247] Example 2-5: k = 4, N = 15, M = 2.

[0248] In example 2-5, the first sequence LP_SS(n) can satisfy: LP_SS(n) = [x0(n) + x1((n + m0) mod 31)] mod 2. The initial values of the second sequence x0(n) and the third sequence x1(n) are not limited. For example, the initial value of x0(n) can be [0, 0, 0, 0, 1], and the initial value of x1(n) can be [0, 0, 0, 0, 1]. In this case, the second sequence and the third sequence and the value range of m0 are shown in Table 12.

[0249] Table 12

[0250] Each row of m sequence pairs in Tables 2-7 and Tables 8-12 can generate a gold sequence, and the network device can generate the LP-SS based on the gold sequence and send it to the terminal device. If the network device uses Manchester encoding, the network device can generate the LP-SS based on the gold sequence corresponding to any row of m sequence pairs in Tables 8-12 and send it to the terminal device. Since the m sequence pairs shown in each row of Tables 2-7 and Tables 8-12 are determined according to factors affecting the synchronization detection performance of the LP-SS (for example, the number of OFDM symbols occupied by the gold sequence, the number of bits M carried by each OFDM, the subcarrier spacing, the CP type, etc.). It can be considered that the gold sequence generated by the m sequence pair shown in each row of Tables 2-12 can guarantee the synchronization detection performance of the LP-SS. Further, based on the m sequence pair with fewer taps in Tables 2-7 and Tables 8-12, the complexity of generating the LP-SS can be reduced, and the synchronization detection efficiency can be improved. Further, for any m sequence pair in the table, selecting a suitable m0 from the value range of m0 corresponding to the m sequence pair when generating the LP-SS can further improve the synchronization detection performance.

[0251] Embodiment two: the first sequence is an m sequence.

[0252] It is considered that the autocorrelation characteristics of different m sequences caused by the initial values of the m sequences are also different, which further affects the synchronization detection performance of the LP-SS generated based on the m sequence. The factors affecting the autocorrelation characteristics of the m sequence, in the embodiments of the present application, can determine the appropriate initial value of the m sequence based on one or more of the following factors to improve the synchronization detection performance of the LP-SS as much as possible.

[0253] As mentioned above, factors affecting the synchronization detection performance of the LP-SS include the number of OFDMs occupied by the sequence, the number of bits M carried by each OFDM, the subcarrier spacing, or the type of CP. Therefore, the initial value of the first sequence can be determined based on one or more of these factors to ensure that the synchronization detection performance of the LP-SS generated based on the first sequence is optimal. In other words, the initial value of the first sequence is related to one or more of the following: the number of OFDMs occupied by the first sequence, the number of bits M carried by each OFDM, the subcarrier spacing, or the type of CP.

[0254] As mentioned above, there are m sequences of various lengths, and there are various ways to generate m sequences under each length. According to the difference in the length N of the m sequence, the number of bits M carried on each OFDM symbol, and the difference in the degree k of the primitive polynomial used to generate the m sequence, the initial value of the first sequence is also different. In the following, with specific examples, the possible initial values of the first sequence under various generation methods of the first sequence are listed.

[0255] It should be noted that each row in each of Tables 13-18 corresponds to a generation method of the first sequence, and a plurality of candidate values of the initial value corresponding to the generation method. Among them, the initial value of the first sequence is selected from the plurality of candidate values, or the initial value of the first sequence is one of the plurality of candidate values. The initial value and the generation method shown in any row in Tables 13-18 can ensure optimal synchronization detection performance of the LP-SS. For the plurality of initial values shown in each row in any table in Tables 13-18, one initial value can be retained to form a new table. Table 13 retains one initial value to form Table 13-1, and so on. Table 18 retains one initial value to form Table 18-1. Then the new tables formed by Tables 13-18 are Tables 13-1-18-1. The network device and the terminal device can store any table in Tables 13-1-18-1.

[0256] Example 3-1: k = 7, N = 127, M = 8.

[0257] In Example 3-1, the correspondence between the generation method of the first sequence and the initial value of the first sequence is shown in Table 13. Each row in Table 13 corresponds to a generation method of the first sequence and a candidate value of the initial value of the first sequence under the generation method.

[0258] Table 13

[0259] Example 3-2: k = 6, N = 63, M = 8.

[0260] In Example 3-2, the correspondence between the generation manner of the first sequence and the initial value of the first sequence is shown in Table 14. Each row in Table 14 corresponds to a generation manner of the first sequence and the candidate value of the initial value of the first sequence under the generation manner.

[0261] Table 14

[0262] Example 3-3: k = 6, N = 63, M = 4.

[0263] In Example 3-3, the correspondence between the generation manner of the first sequence and the initial value of the first sequence is shown in Table 15. Each row in Table 15 corresponds to a generation manner of the first sequence and the candidate value of the initial value of the first sequence under the generation manner.

[0264] Table 15

[0265] Example 3-4: k = 5, N = 31, M = 4.

[0266] In Example 3-4, the correspondence between the generation manner of the first sequence and the initial value of the first sequence is shown in Table 16. Each row in Table 16 corresponds to a generation manner of the first sequence and the candidate value of the initial value of the first sequence under the generation manner.

[0267] Table 16

[0268] Example 3-5: k = 5, N = 31, M = 2.

[0269] In Example 3-5, the correspondence between the generation manner of the first sequence and the initial value of the first sequence is shown in Table 17. Each row in Table 17 corresponds to a generation manner of the first sequence and the candidate value of the initial value of the first sequence under the generation manner.

[0270] Table 17

[0271] Example 3-6: k = 4, N = 15, M = 2.

[0272] In Example 3-6, the correspondence between the generation manner of the first sequence and the initial value of the first sequence is shown in Table 18. Each row in Table 18 corresponds to a generation manner of the first sequence and the candidate value of the initial value of the first sequence under the generation manner.

[0273] Table 18

[0274] In a possible implementation, in the generation of the LP-SS, the first sequence can be Manchester coded to further improve the synchronization detection performance. In this case, according to the length N of the m sequence, the number of bits M carried on each OFDM symbol, and the degree k of the primitive polynomial used to generate the m sequence, the initial value of the first sequence is also different. In the following, with specific examples, the possible initial values of the first sequence in various generation modes of the first sequence are listed.

[0275] It should be noted that each row in each of the following Tables 19-23 corresponds to a generation mode of the first sequence and a plurality of candidate values of the initial value corresponding to the generation mode. Among them, the initial value of the first sequence is selected from the plurality of candidate values, or the initial value of the first sequence is one of the plurality of candidate values. The initial value and the generation mode shown in any row in Tables 19-23 can guarantee the optimal synchronization detection performance of the LP-SS. For the plurality of initial values shown in each row in any of Tables 19-23, one initial value can be reserved to form a new table. Table 19 reserves one initial value to form Table 19-1, and so on. Table 23 reserves one initial value to form Table 23-1. Then, the new tables formed by Tables 19-23 are Tables 19-1-23-1. The network device and the terminal device can store any of Tables 19-1-23-1.

[0276] Example 4-1: k = 6, N = 63, M = 8.

[0277] In Example 4-1, the correspondence between the generation mode of the first sequence and the initial value of the first sequence is shown in Table 19. Each row in Table 19 corresponds to a generation mode of the first sequence and a candidate value of the initial value of the first sequence in the generation mode.

[0278] Table 19

[0279] Example 4-2: k = 5, N = 31, M = 8.

[0280] In Example 4-2, the correspondence between the generation mode of the first sequence and the initial value of the first sequence is shown in Table 20. Each row in the table corresponds to a generation mode of the first sequence and a candidate value of the initial value of the first sequence in the generation mode.

[0281] Table 20

[0282] Example 4-3: k = 5, N = 31, M = 4.

[0283] In Example 4-3, the correspondence between the generation manner of the first sequence and the initial value of the first sequence is shown in Table 21. Each row in Table 21 corresponds to a generation manner of the first sequence and the candidate value of the initial value of the first sequence in the generation manner.

[0284] Table 21

[0285] Example 4-4: k = 4, N = 15, M = 4.

[0286] In Example 4-4, the correspondence between the generation manner of the first sequence and the initial value of the first sequence is shown in Table 22. Each row in Table 22 corresponds to a generation manner of the first sequence and the candidate value of the initial value of the first sequence in the generation manner.

[0287] Table 22

[0288] Example 4-5: k = 4, N = 15, M = 2.

[0289] In Example 4-5, the correspondence between the generation manner of the first sequence and the initial value of the first sequence is shown in Table 23. Each row in Table 23 corresponds to a generation manner of the first sequence and the candidate value of the initial value of the first sequence in the generation manner.

[0290] Table 23

[0291] It should be noted that the above Tables 2-23 are applicable to the scenario of NCP. According to the different types of CP, the value range of the second sequence, the third sequence or m0may be the same or different. For example, when the type of CP is ECP, k = 6, N = 63, M = 4, the value range of the second sequence, the third sequence and m0is shown in Table 24.

[0292] Table 24

[0293] The network device can generate the LP-SS based on the generation manner and the initial value shown in any row of any of the above Tables 13-23 and send the LP-SS to the terminal device. If the network device uses Manchester coding, the network device can generate the LP-SS based on the generation manner and the initial value shown in any row of any of the above Tables 19-23 and send the LP-SS to the terminal device. The initial value shown in each row of the above Tables 13-23 is determined according to factors affecting the synchronization detection performance of the LP-SS (e.g., the number of OFDM symbols occupied by the first sequence, the number of bits M carried by each OFDM, the subcarrier spacing, the CP type, etc.). It can be considered that the m sequence obtained based on the generation manner and the initial value shown in each row of the above Tables 13-23 can guarantee the optimal synchronization detection performance of the LP-SS. Further, adjacent cells select different generation manners and initial values to reduce interference between adjacent cells.

[0294] The communication method provided by the embodiments of the present application is described below.

[0295] In the following description, the communication method provided by the embodiments of the present application is applied to the network architecture shown in FIG. 1, and the communication method provided by the embodiments of the present application can be executed by the network device and the terminal device. The steps executed by the network device can be implemented by the RAN device itself, or by a component (such as a baseband chip, or other processing unit or processor, etc.) in the RAN device, or by a component (such as a CU, DU, or RU) that completes part or all of the functions of the RAN device. The steps executed by the terminal device can be implemented by the terminal device itself, or by a component (such as a baseband chip, or other processing unit or processor, etc.) in the terminal device. The specific forms of the network device and the terminal device are not limited, for example, the network device can be a chip, and the terminal device can be a device; or both the network device and the terminal device are chips or devices. In possible scenarios, the network device can be the terminal device 120a shown in FIG. 1, or can also be a chip (system) in the terminal device 120a in FIG. 1; the terminal device can be the network device 110a in FIG. 1, or can also be a chip (system) in the network device 110a in FIG. 1. In possible scenarios, the network device can be the terminal device 120b shown in FIG. 1, or can also be a chip (system) in the terminal device 120b in FIG. 1; the terminal device can be the terminal device 120a in FIG. 1, or can also be a chip (system) in the terminal device 120a in FIG. 1.

[0296] In embodiments of the present application, the terminal device supports LP-SS, or the terminal device supports low-power characteristics, or the terminal device has LP capability / WUR capability. Having WUR capability is equivalent to any of the following descriptions: having the capability to receive a low-power signal, or having the capability to receive LP-SS, or being configured with WUR or LP-SS function, or having WUR or LP-SS function enabled, or supporting receiving an LP signal through an LP receiver / link / interface, or being configured to receive an LP signal through an LP receiver / link / interface, or being allowed / activated to receive an LP signal through an LP receiver / link / interface.

[0297] Please refer to FIG. 8, which is a flowchart of a communication method provided by embodiments of the present application. FIG. 8 introduces the method from the perspective of interaction between a network device and a terminal device, wherein the terminal device supports low-power characteristics or supports LP-SS. It should be understood that the communication method can also be implemented by other devices, such as a chip or a communication device with communication function. In addition, the processing performed by a single execution subject can also be divided into processing performed by multiple execution subjects, which can be logically and / or physically separated. For example, the processing performed by the network device can be divided into processing performed by at least one of a CU, a DU, a RU, etc. As shown in FIG. 8, the flow of the communication method includes the following steps.

[0298] S801, the network device generates a low-power synchronization signal based on a first sequence. S801 is an optional step, that is, a step that does not have to be performed. In FIG. 8, it is shown in a dashed line.

[0299] S802, the network device sends the low-power synchronization signal to the terminal device, and correspondingly, the terminal device receives the low-power synchronization signal from the network device.

[0300] For a terminal device that supports a low-power synchronization signal / LP-SS, in the synchronization process between the network device and the terminal device, in order to reduce the power consumption of the terminal device, the network device can send an LP-SS to the terminal device. The LP-SS can be obtained based on a first sequence, that is, the sequence used to generate the LP-SS is the first sequence. The generation of the LP-SS and the sending of the LP-SS can be implemented by different functional entities that make up the network device. For example, the DU can generate the LP-SS, and the RU can send the LP-SS. Of course, the generation of the LP-SS and the sending of the LP-SS can also be implemented by the same functional entity that makes up the network device, for example, the RU can generate the LP-SS, and the RU can send the LP-SS.

[0301] Depending on the implementation form of the first sequence, the specific implementation of the network device generating the LP-SS is different, which is introduced below.

[0302] Case 1: the first sequence is a gold sequence.

[0303] In case 1, the network device can generate the LP-SS based on any table in table 2-7. For example, the network device can generate the LP-SS based on the gold sequence generated by the m-sequence pair and the value range of m0 in any row of table 1. The network device generating the LP-SS includes but is not limited to the following implementation manners.

[0304] Implementation manner 1

[0305] The network device can store all or part of the tables in table 2-7. The network device can select a suitable table (for example, referred to as a target table) from the stored tables according to N and M, and generate the LP-SS based on the target table. For example, the network device can generate the gold sequence based on the m-sequence pair and m0 corresponding to the row in any row of the target table, and generate the LP-SS based on the gold sequence.

[0306] For example, the m-sequence pair is x0(n) and x1(n), and the gold sequence LP_SS(n) = [x0(n) + x1((n+m0)mod N)]mod 2. The specific value of m0 can be determined according to the cell ID. It can be understood that the cell ID can be used to identify the cell at the physical layer. The terminal device can determine the cell identity through the network identifier one (network identity 1, NID1) and the network identifier two (network identity 2, NID2). The cell ID is carried in the LP-SS. In the embodiment of the present application, m0 can be determined according to NID1. For example, For NID1, P is the number of available first sequences, and seqlist[] represents the value range of m0.

[0307] Implementation manner 2

[0308] The network device can store all or part of the tables in table 2-7 generated by the m-sequence pair and the value range of m0 corresponding to the gold sequence. For example, the network device can store all or part of table 2-1-7-1. The network device can select a target table from the stored tables according to N and M, and generate the LP-SS based on the target table. For example, the network device can generate the LP-SS based on the gold sequence and m0 corresponding to the row in any row of the target table. The specific value of m0 can be referred to the related description above.

[0309] Optionally, the table stored by the network device can only include the m-sequence pair or the gold sequence, and not include the value range of m0. In this case, the value range of m0 can be predefined by a protocol, for example, the value range of m0 can be [0, N-1].

[0310] Optionally, Tables 2 to 7 can be predefined by a protocol, and the network device does not need to store them. Similarly, Tables 2-1 to 7-1 can be predefined by a protocol, and the network device does not need to store them.

[0311] It can be understood that if the network device uses Manchester coding, the network device can generate the LP-SS based on any table in Tables 8 to 12. For example, the network device can generate the LP-SS based on the gold sequence corresponding to the m-sequence pair shown in any row in Table 8 and the value range of m0. The network device generates the LP-SS in the following implementation manners, but is not limited to them.

[0312] Implementation manner 3

[0313] The network device can store all or part of the tables in Tables 8 to 12. The network device can select a suitable table (for example, referred to as a target table) from the stored tables according to N and M, and generate the LP-SS based on the target table. For example, the network device can generate the gold sequence based on the m-sequence pair shown in any row in the target table and m0 corresponding to the row, and generate the LP-SS based on the gold sequence. The specific value of m0 can be referred to the related description above.

[0314] Implementation manner 4

[0315] The network device can store all or part of the tables in Tables 8 to 12, the gold sequence generated by the m-sequence pair, and the value range of m0 corresponding to the m-sequence pair. For example, the network device can store all or part of Tables 8-1 to 12-1. The network device can select a target table from the stored tables according to N and M, and generate the LP-SS based on the target table. For example, the network device can generate the LP-SS based on the gold sequence shown in any row in the target table and m0 corresponding to the row. Adjacent cells use different m0, so as to ensure that the LP-SS of adjacent cells are orthogonal as much as possible, and reduce the interference between adjacent cells. The specific value of m0 can be referred to the related description above.

[0316] Optionally, the table stored by the network device can only include the m-sequence pair or the gold sequence, and not include the value range of m0. In this case, the value range of m0 can be predefined by a protocol, for example, the value range of m0 can be [0, N-1].

[0317] Optionally, Tables 8-12 can be pre-defined by the protocol and need not be stored by the network device. Similarly, Tables 8-1-12-1 can be pre-defined by the protocol and need not be stored by the network device.

[0318] Optionally, for Tables 2-12, the network device can also generate the pair of m-sequences in Tables 2-12 when generating the LP-SS, generate the gold sequence based on the pair of m-sequences, and generate the LP-SS based on the gold sequence. In this case, the network device can also not store Tables 2-12. Similarly, the network device can also not store Tables 2-1-12-1, and the network device can also generate the pair of m-sequences in Tables 2-1-12-1 when generating the LP-SS, generate the gold sequence based on the pair of m-sequences, and generate the LP-SS based on the gold sequence. For example, the network device stores the initial value for generating a row in Table 2, and based on the initial value and the generation method of the m-sequence, the network device can generate two m-sequences, and generate the LP-SS based on the two m-sequences.

[0319] Case 2: The first sequence is an m-sequence.

[0320] In Case 2, the network device can generate the LP-SS based on the m-sequence obtained from any of Tables 13-18. For example, the network device can generate the LP-SS based on the m-sequence obtained from any row in Table 13 and one of the initial values shown in the row. The network device can generate the LP-SS in the following implementation manners, but not limited to the following implementation manners.

[0321] Implementation Manner 1

[0322] The network device can store all or part of Tables 13-1-18-1. The network device can select a suitable table (e.g., referred to as a target table) from the stored tables according to N and M, and generate the LP-SS based on the target table. For example, the network device can generate the m-sequence based on the generation method shown in any row in the target table and one of the initial values shown in the row, and generate the LP-SS based on the m-sequence.

[0323] Implementation Manner 2

[0324] The network device can store all or part of the m-sequences obtained from the initial values and the corresponding generation methods in Tables 13-1-18-1. The network device can select one m-sequence from the stored m-sequences according to N and M, and generate the LP-SS based on the m-sequence.

[0325] Optionally, Tables 13-1-18-1 can be pre-defined by the protocol and need not be stored by the network device.

[0326] It can be understood that if the network device uses Manchester coding, the network device can generate the LP-SS based on any table in Tables 19-23. For example, the network device can generate the LP-SS based on the generation method shown in any row in Table 19 and an m sequence obtained by using one initial value in the row. The network device can generate the LP-SS in the following implementation manners.

[0327] Implementation manner 3

[0328] The network device can store all or part of the tables in Tables 19-1-23-1. The network device can select a suitable table (for example, referred to as a target table) from the stored tables according to N and M, and generate the LP-SS based on the target table. For example, the network device can generate the LP-SS based on a generation method shown in any row in the target table and an m sequence obtained by using one initial value in the row.

[0329] Implementation manner 4

[0330] The network device can store all or part of the tables in Tables 19-1-23-1, and m sequences obtained by using initial values and corresponding generation methods. The network device can select an m sequence from the stored m sequences according to N and M, and generate the LP-SS.

[0331] Optionally, Tables 19-1-23-1 can be predefined by a protocol, and the network device does not need to store the tables.

[0332] In case 2, the specific value of m0 is also determined according to the cell ID. Adjacent cells use different m0 and generation methods, so as to ensure the orthogonality of the LP-SS between adjacent cells and reduce the interference between adjacent cells. For details, refer to the foregoing description, which will not be repeated here.

[0333] S803, the terminal device performs correlation processing on the low-power synchronization signal based on the first sequence. S803 is an optional step, that is, not necessarily executed, which is shown in FIG. 8 in a dashed line.

[0334] After the terminal device receives the low-power synchronization signal / LP-SS from the network device, the terminal device can perform correlation processing on the LP-SS based on the first sequence to detect the synchronization signal. The process in which the terminal device performs correlation processing on the LP-SS based on the first sequence is also the process in which the terminal device detects the LP-SS. In the process in which the terminal device detects the LP-SS, the terminal device actually performs a sliding correlation calculation on the received sequence and a specific sequence, and takes the position of the correlation peak as the timing estimation position. The specific sequence can be stored in the terminal device in advance or generated by the terminal device. The terminal device can store a plurality of specific sequences, and when detecting the synchronization signal, performs autocorrelation calculation on the received sequence and a specified specific sequence, and takes the position of the maximum autocorrelation value as the timing estimation position.

[0335] In the embodiments of the present application, the specific sequence has various implementation manners, and the detection manner of the synchronization signal is also different according to the implementation manner of the specific sequence, including but not limited to the following four manners.

[0336] Manner 1: The specific sequence is a gold sequence, and the received signal can be processed based on the gold sequence to detect the LP-SS.

[0337] The terminal device can store at least one gold sequence, and when detecting the synchronization signal, a first sequence can be obtained from the at least one stored gold sequence. Alternatively, an m-sequence pair and a corresponding m0 obtained according to any row in Tables 2 to 7 can be stored locally, and when detecting the synchronization signal, one m-sequence pair (for example, x0(n) and x1(n)) is selected from the stored m-sequence pairs, one m0 is selected from the value range of m0, and a first sequence is generated based on x0(n) and x1(n) and m0. For example, the first sequence LP_SS(n) = [x0(n)+x1((n+m0)mod N)]mod 2.

[0338] The terminal device processes the received signal according to the first sequence, including: for the obtained first sequence, the terminal device performs correlation processing on the received signal using the first sequence, and obtains a correlation peak position. The correlation processing includes correlation calculation, and the correlation peak position is the timing estimation position.

[0339] Manner 2: The specific sequence is an m-sequence, and the received signal can be processed based on the m-sequence to detect the LP-SS.

[0340] The terminal device can store at least one m-sequence, and when detecting the synchronization signal, a first sequence can be obtained from the at least one stored m-sequence. Alternatively, initial values in any row in Tables 13 to 23 can be stored locally, and when detecting the synchronization signal, a first sequence is generated based on the initial values and m0.

[0341] The terminal device processes the received signal according to the first sequence, including: for the obtained first sequence, the terminal device uses the first sequence to perform correlation processing on the received signal to obtain a correlation peak position. The correlation processing includes correlation calculation, and the correlation peak position is a timing estimation position.

[0342] The above embodiments of the present application are introduced by taking the terminal device and the network device as examples. In the present application, each embodiment can be independently implemented or implemented based on certain internal relations; different implementation manners in each embodiment can be combined or independently implemented. In order to realize the functions in the above method provided by the embodiments of the present application, the steps performed by the terminal device can be realized by the terminal device itself, or can be realized by a functional entity including the terminal device, or can be realized by different functional entities constituting the terminal device. The steps performed by the network device can be realized by the network device itself, or can be realized by different functional entities constituting the network device, or can be realized by a functional entity including the network device. For example, the network device is an access network device, which can be a CU-DU-RU architecture, the DU can generate the LP-SS, and the RU can send the LP-SS. In order to realize the functions in the above method provided by the embodiments of the present application, the terminal device and the network device can include hardware structures and / or software modules, and the above functions can be realized in the form of hardware structures, software modules, or hardware structures plus software modules. Whether a certain function in the above functions is executed in the form of hardware structure, software module, or hardware structure plus software module depends on the specific application and design constraints of the technical solution.

[0343] Based on the same inventive concept as the method embodiments, the embodiments of the present application provide a communication device. The communication device used to implement the above method in the embodiments of the present application is introduced below in conjunction with the drawings. The above contents can be used in the subsequent embodiments, and the repeated contents will not be described again.

[0344] FIG. 9 is a schematic block diagram of a communication apparatus 900 provided by the embodiments of the present application. The communication apparatus 900 can correspond to implement the functions or steps implemented by the terminal device in each of the above method embodiments. For example, the communication apparatus 900 can be the terminal device in FIG. 1; or the communication apparatus 900 is a chip (system) in the terminal device; or the communication apparatus 900 is a software module of the terminal device. Alternatively, the communication apparatus 900 can correspond to implement the functions or steps implemented by the network device in each of the above method embodiments. For example, the communication apparatus 900 can be the network device in FIG. 1; or the communication apparatus 900 is a chip (system) in the network device; or the communication apparatus 900 is a software module of the network device. The communication apparatus 900 can include a processing module 910 and a transceiver module 920. Optionally, it can also include a storage module, which can be used to store instructions (codes or programs) and / or data. The storage module can be, for example, a memory. The processing module 910 and the transceiver module 920 can be coupled with the storage module. For example, the processing module 910 can read the instructions (codes or programs) and / or data in the storage module to implement the corresponding method. When the communication apparatus 900 is a chip in the terminal device, the storage module can be a storage module in the chip, such as a register, a cache, etc. For example, the storage module can also be a storage module outside the chip in the terminal device, such as a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, a random access memory (RAM), etc. The above various units can be independently arranged, or partially or entirely integrated.

[0345] The processing module 910 can be a processor or a controller, for example, can be a general central processing unit (CPU), a general processor, a digital signal processing (DSP), an application specific integrated circuits (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof. It can implement or execute various exemplary logical blocks, modules and circuits described in combination with the disclosure. The processor can also be a combination of computing functions, such as including one or more microprocessor combinations, combinations of DSP and microprocessor, etc. The transceiver module 920 is a transceiver, interface circuit, bus, pin or other possible communication interface for receiving signals from other devices. For example, when the device is implemented in the form of a chip, the transceiver module 920 is an interface circuit of the chip for receiving signals from other chips or devices, or is an interface circuit of the chip for transmitting signals to other chips or devices.

[0346] In an implementation manner, the communication apparatus 900 can correspondingly implement the behaviors and functions of the network device in the above method embodiments. The communication apparatus 900 can be a network device, or a component (for example, a chip or a circuit) in the network device, or a part of a chip or a chip set in the network device for executing the functions of the related method, or a software module in the network device capable of implementing the above communication method, without limitation. For details, reference can be made to the related contents of the foregoing method embodiments, which will not be described here.

[0347] For example, the processing module 910 is configured to generate a low-power consumption synchronization signal. The sequence used to generate the low-power consumption synchronization signal is a first sequence. The first sequence is related to one or more of the following: the number of time units occupied by the first sequence, the number of bits M carried by each time unit, the subcarrier spacing, or the type of CP. The transceiver module 920 is configured to transmit the low-power consumption synchronization signal.

[0348] In an implementation manner, the communication apparatus 900 can correspondingly implement the behaviors and functions of the terminal device in the above method embodiments. The communication apparatus 900 can be a terminal device, or a component (for example, a chip or a circuit) in the terminal device, or a part of a chip or a chip set in the terminal device for executing the functions of the related method, or a software module in the terminal device capable of implementing the above communication method, without limitation. For details, reference can be made to the related contents of the foregoing method embodiments, which will not be described here.

[0349] For example, the transceiver module 920 is configured to receive the low power consumption synchronization signal. The processing module 910 is configured to process the low power consumption synchronization signal based on a first sequence. The first sequence is related to one or more of the following: a number of time units occupied by the first sequence, a number of bits M carried by each time unit, a subcarrier spacing, or a type of CP.

[0350] When the communication apparatus 900 is a chip type apparatus or circuit, the transceiver module can be an input / output circuit and / or a communication interface; and the processing module can be an integrated processor or microprocessor or integrated circuit.

[0351] FIG. 10 is a schematic block diagram of a communication apparatus 1000 according to an embodiment of the present application. The communication apparatus 1000 can be a terminal device or a network device in the embodiments described above. For example, the communication apparatus 1000 can be a terminal device or a chip (system) in a terminal device in FIG. 1. For another example, the communication apparatus 1000 can be a network device or a chip (system) in a network device in FIG. 1. In embodiments of the present application, the chip system can be composed of a chip, or can include a chip and other discrete devices. For specific functions, refer to the description in the method embodiments described above.

[0352] The communication apparatus 1000 includes one or more processors 1001 configured to implement or support implementation of the functions of the terminal device or the network device in the methods provided in the embodiments of the present application. For specific descriptions, refer to the detailed description in the method embodiments, which will not be repeated here. The processor 1001 can also be referred to as a processing unit or a processing module, and can implement certain control functions. The processor 1001 can be a general purpose processor or a special purpose processor. For example, it includes a baseband processor, a central processing unit, an application processor, a modem processor, a graphics processor, an image signal processor, a digital signal processor, a video coding and decoding processor, a controller, a memory, and / or a neural network processor, etc. The baseband processor can be configured to process communication protocols and communication data. The central processing unit can be configured to control the communication apparatus 1000 (e.g., a terminal device or a network device), execute software programs, and / or process data. Different processors can be independent devices, or can be integrated into one or more processors, for example, integrated into one or more application specific integrated circuits.

[0353] In an example design, the processor 1001 can include a program 1003 (which can also be referred to as code or instructions) that can be run on the processor 1001 to cause the communication device 1000 to perform the methods described in the following embodiments. In another example design, the communication device 1000 includes circuitry (not shown in FIG. 10) to implement the functions of a terminal device or a network device in the above-described embodiments.

[0354] In an example design, the communication device 1000 can include one or more memories 1002 having a program 1004 (which can also be referred to as code or instructions) stored thereon that can be run on the processor 1001 to cause the communication device 1000 to perform the methods described in the above-described method embodiments.

[0355] In an example design, the processor 1001 and / or the memory 1002 can include an artificial intelligence (AI) module 1007, which can be used to implement AI-related functions. The AI module can be implemented in software, hardware, or a combination of both. For example, the AI module can include a RAN intelligent controller (RIC) module. The AI module can be a near-real-time RIC or a non-real-time RIC.

[0356] In an example design, the processor 1001 and / or the memory 1002 can also store data. The processor and the memory can be separately arranged or integrated together.

[0357] In an example design, the communication device 1000 can also include a transceiver 1005 and / or an antenna 1006. The processor 1001 can also be referred to as a processing unit, which controls the communication device 1000. The transceiver 1005 can also be referred to as a transceiving unit, a transceiver, a transceiving circuit, or a transceiver, which can be used to implement the transceiving functions of the communication device 1000 through the antenna 1006.

[0358] In a possible design, the communication apparatus 1000 can further include one or more of the following components: a wireless communication module, an audio module, an external storage interface, an internal storage, a universal serial bus (USB) interface, a power management module, an antenna, a speaker, a microphone, an input / output (I / O) module, a sensor module, a motor, a camera, or a display screen, etc. It can be understood that, in some embodiments, the communication apparatus 1000 can include more or less components, or some components can be integrated, or some components can be split into a plurality of components. These components can be implemented by hardware, software, or a combination of hardware and software.

[0359] The communication apparatus in the above embodiments can be a terminal device, can be a circuit, or can be a chip applied to a terminal device or other combination device, component, etc. having the terminal device. When the communication apparatus is a terminal device, the transceiver module can be a transceiver, can include an antenna and a radio frequency circuit, etc., and the processing module can be a processor, for example, a CPU. When the communication apparatus is a chip system, the communication apparatus can be an FPGA, can be a special ASIC, can be a SoC, can be a CPU, can be a network processor (NP), can be a DSP, can be a micro controller unit (MCU), can be a programmable logic device (PLD), or can be another integrated chip. The processing module can be a processor of the chip system. The transceiver module or the communication interface can be an input / output interface or an interface circuit of the chip system. For example, the interface circuit can be a code / data read / write interface circuit. The interface circuit can be used to receive code instructions (the code instructions are stored in a memory, can be directly read from the memory, or can be read from the memory through another device) and transmit the code instructions to the processor. The processor can be used to run the code instructions to perform the methods in the above method embodiments. For another example, the interface circuit can also be a signal transmission interface circuit between a communication processor and a transceiver.

[0360] The embodiments of the present application further provide a communication system, including at least one terminal device and at least one network device, and the terminal device is a terminal device used to implement the functions related to the above communication method.

[0361] The embodiments of the present application further provide a computer readable storage medium, including instructions, when the instructions are run on a computer, causing the computer to execute the method performed by the terminal device or the network device in the above communication method.

[0362] The embodiment of the present application further provides a computer program product, including computer program codes, which, when executed, cause a computer to execute the method performed by the terminal device or the network device in the communication method.

[0363] The embodiment of the present application provides a chip system, which includes a processor and can further include a memory, and is used for implementing the functions of the terminal device or the network device in the foregoing communication method. The chip system can be composed of a chip or can include the chip and other discrete devices.

[0364] In order to implement the functions of the communication device in FIG. 9 and FIG. 10, the embodiment of the present application further provides a chip, which includes a processor and is used for supporting the communication device to implement the functions related to the terminal device or the network device in the foregoing method embodiments. In a possible design, the chip is connected with a memory or the chip includes the memory, and the memory is used for storing the computer programs or instructions and data necessary for the communication device.

[0365] It should be understood that, in the various embodiments of the present application, the size of the serial number of each process does not mean the order of execution, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0366] Those skilled in the art can realize that the various illustrative logical blocks and steps described in conjunction with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether the functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. A person skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0367] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the system, device and unit described above can refer to the corresponding processes in the foregoing method embodiments, which will not be described here.

[0368] In several embodiments provided in the present application, it should be understood that the disclosed system, device and method can be implemented in other manners. For example, the described device embodiments are merely schematic. For example, the division of the units is only a logical function division. There can be another division manner for the actual implementation, for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections between the units can be indirect couplings or communication connections through some interfaces, devices or units, and can be in electrical, mechanical or other forms.

[0369] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, i.e., can be located in one place, or can be distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0370] If the functions are implemented in the form of software function units and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the part of the technical solutions of the present application that essentially contributes or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, and includes a number of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, ROM, RAM, magnetic disk or optical disk, and various program code storage media.

[0371] Obviously, those skilled in the art can make various modifications and variations to the present application without departing from the scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application also intends to include these modifications and variations.

Claims

A communication method characterized by comprising: Comprise: transmitting a low power synchronization signal, wherein a sequence used for generating the low power synchronization signal is a first sequence, the first sequence being related to one or more of: a number of time units occupied by the first sequence, a number of bits M carried by each time unit, a subcarrier spacing, or a type of cyclic prefix CP. The method of claim 1, wherein The first sequence LP_SS satisfies: LP_SS = (x0+x1) mod 2, wherein x0 is a second sequence, x1 is a third sequence, mod is a modulo operation, lengths of the second sequence and the third sequence are N, N = 2 k -1, k is a positive integer; and the second sequence is related to one or more of: a number of time units occupied by the second sequence, a number of bits M carried by each time unit, a subcarrier spacing, or a type of CP; The third sequence is related to one or more of: a number of time units occupied by the third sequence, a number of bits M carried by each time unit, a subcarrier spacing, or a type of CP. The method of claim 1, wherein The first sequence LP_SS(n) satisfies: LP_SS(n) = [x0(n)+x1((n+m0)mod N)] mod 2 wherein x0(n) is a second sequence, x1(n) is a third sequence, m0 is a cyclic shift, n is an integer greater than or equal to 0 and less than N, N is a length of the second sequence and the third sequence, N=2 k -1, k is a positive integer, and mod is a modulo operation. The method of claim 1, wherein The first sequence is related to one or more of: a number of time units occupied by the first sequence, a number of bits M carried by each time unit, a subcarrier spacing, or a type of CP, comprising: An initial value of the first sequence is related to one or more of: a number of time units occupied by the first sequence, a number of bits M carried by each time unit, a subcarrier spacing, or a type of CP. The method as claimed in claim 2 or 3, characterized in that k = 7, N = 127, M = 8; The element x0(i+7) in the second sequence satisfies: x0(i+7) = (x0(i+1)+x0(i)) mod 2, and the element x1(i+7) in the third sequence satisfies: x1(i+7) = (x1(i+3)+x1(i)) mod 2; or, The element x0(i+7) in the second sequence satisfies: x0(i+7) = (x0(i+1)+x0(i)) mod 2, and the element x1(i+7) in the third sequence satisfies: x1(i+7) = (x1(i+4)+x1(i)) mod 2. The method of claim 5, wherein When the element x0(i+7) in the second sequence satisfies: x0(i+7) = (x0(i+1)+x0(i)) mod 2, and the element x1(i+7) in the third sequence satisfies: x1(i+7) = (x1(i+3)+x1(i)) mod 2, the m0 belongs to a first set, the first set comprising one or more of the following cyclic shifts: 3, 912, 15, 19, 31, 35, 46, 48, 57, 60, 61, 62, 64, 65, 71, 82, 87, 92, 94, 99, 101, 107, 108, 113, 114, 117, 120, 121, 122, 123, 124. The method of claim 6, wherein when the element x0(i+7) in the second sequence satisfies: x0(i+7)=(x0(i+1)+x0(i))mod 2, and the element x1(i+7) in the third sequence satisfies: x1(i+7)=(x1(i+4)+x1(i))mod 2, the m0 belongs to a second set, and the second set comprises one or more cyclic shifts as follows: 24, 29, 34, 36, 39, 46, 47, 50, 53, 58, 61, 62, 65, 66, 78, 82, 84, 85, 86, 96, 100, 105, 106, 109, 111, 112, 116, 117, 120, 123, 125, 126. The method as claimed in claim 2 or 3, characterized in that k=6, N=63, M=8 or M=4; when the element x0(i+6) in the second sequence satisfies: x0(i+6)=(x0(i+1)+x0(i))mod 2, and the element x1(i+6) in the third sequence satisfies: x1(i+6)=(x1(i+5)+x1(i))mod 2. The method of claim 8, wherein when M=8, the m0 belongs to a third set, and the third set comprises one or more cyclic shifts as follows: 2, 4, 5, 8, 9, 10, 11, 12, 13, 14, 16, 18, 19, 21, 22, 23, 27, 28, 33, 39, 40, 43, 45, 49, 50, 51, 52, 55, 57, 58, 60, 61. The method of claim 8, wherein when M=4, the m0 belongs to a fourth set, and the fourth set comprises one or more cyclic shifts as follows: 2, 4, 5, 9, 13, 14, 16, 18, 19, 22, 23, 25, 27, 28, 30, 31, 33, 34, 39, 40, 41, 43, 45, 49, 50, 51, 52, 53, 55, 57, 58, 60. The method of claim 8, wherein The method further comprises: mapping the element 0 in the first sequence as [0, 1], and mapping the element 1 in the first sequence as [1, 0]; or mapping the element 1 in the first sequence as [0, 1], and mapping the element 0 in the first sequence as [1, 0]; wherein, when M=8, the m0 belongs to a fifth set, and the fifth set comprises one or more cyclic shifts as follows: 1, 3, 6, 7, 8, 10, 12, 13, 15, 20, 21, 24, 26, 31, 32, 35, 36, 37, 41, 42, 43, 44, 47, 50, 53, 54, 56, 57, 59, 61, 62, 63. The method as claimed in claim 2 or 3, characterized in that k=5, N=31, M=8, M=4 or M=2; when the element x0(i+5) in the second sequence satisfies: x0(i+5)=(x0(i+2)+x0(i))mod 2, and the element x1(i+5) in the third sequence satisfies: x1(i+5)=(x1(i+3)+x1(i+2)+x1(i+1)+x1(i))mod 2; or The element x0(i+5) in the second sequence satisfies: x0(i+5)=(x0(i+2)+x0(i))mod2, and the element x1(i+5) in the third sequence satisfies: x1(i+5)=(x1(i+4)+x1(i+2)+x1(i+1)+x1(i))mod2. The method of claim 12, wherein When the element x0(i+5) in the second sequence satisfies: x0(i+5)=(x0(i+2)+x0(i))mod2, and the element x1(i+5) in the third sequence satisfies: x1(i+5)=(x1(i+3)+x1(i+2)+x1(i+1)+x1(i))mod2, the m0 belongs to a sixth set, and the sixth set includes one or more cyclic shifts as follows: 2, 4, 5, 7, 9, 10, 12, 13, 16, 20, 21, 23, 24, 25, 26, 27; or 2, 5, 7, 9, 10, 12, 13, 16, 21, 23, 24, 25, 26, 27, 29, 30, 31. The method of claim 12, wherein The method further includes: mapping the element 0 in the first sequence as [0, 1], and mapping the element 1 in the first sequence as [1, 0]; or mapping the element 1 in the first sequence as [0, 1], and mapping the element 0 in the first sequence as [1, 0]; When M=8, the m0 belongs to a seventh set, and the seventh set includes one or more cyclic shifts as follows: 1, 2, 3, 8, 10, 11, 13, 14, 15, 18, 19, 22, 27, 28, 29, 31; or, When M=4, the m0 belongs to an eighth set, and the eighth set includes one or more cyclic shifts as follows: 1, 2, 3, 4, 6, 8, 11, 13, 14, 15, 18, 19, 22, 28, 29, 31. The method of claim 12, wherein When the element x0(i+5) in the second sequence satisfies: x0(i+5)=(x0(i+2)+x0(i))mod2, and the element x1(i+5) in the third sequence satisfies: x1(i+5)=(x1(i+4)+x1(i+2)+x1(i+1)+x1(i))mod2, the m0 belongs to a ninth set, and the ninth set includes one or more cyclic shifts as follows: 1, 2, 3, 5, 6, 8, 9, 11, 12, 15, 16, 20, 21, 23, 28, 31; or 1, 2, 3, 5, 6, 8, 9, 11, 12, 13, 15, 16, 20, 21, 23, 28. The method of claim 12, wherein The method further includes: mapping the element 0 in the first sequence as [0, 1], and mapping the element 1 in the first sequence as [1, 0]; or mapping the element 1 in the first sequence as [0, 1], and mapping the element 0 in the first sequence as [1, 0]; When M=8, the m0 belongs to a tenth set, the tenth set comprising one or more cyclic shifts of: 4, 7, 10, 11, 13, 14, 18, 19, 20, 22, 24, 25, 27, 29, 30, 31; or When M=4, the m0 belongs to an eleventh set, the eleventh set comprising one or more cyclic shifts of: 2, 4, 7, 8, 10, 14, 18, 19, 20, 22, 24, 25, 27, 29, 30, 31. The method as claimed in claim 2 or 3, characterized in that k=4, N=15, M=4 or M=2; The element x0(i+4) in the second sequence satisfies: x0(i+4)=(x0(i+1)+x0(i))mod 2, and the element x1(i+4) in the third sequence satisfies: x1(i+4)=(x1(i+3)+x1(i))mod 2. The method of claim 17, wherein The m0 belongs to a twelfth set, the twelfth set comprising one or more cyclic shifts of: 2, 5, 7, 8, 9, 11, 12, 13. The method of claim 17, wherein The method further comprises: mapping element 0 in the first sequence as [0, 1], and mapping element 1 in the first sequence as [1, 0]; or mapping element 1 in the first sequence as [0, 1], and mapping element 0 in the first sequence as [1, 0]; Wherein, the m0 belongs to a thirteenth set, the thirteenth set comprising one or more cyclic shifts of: 1, 3, 4, 6, 8, 12, 14, 15. The method of any one of claims 3, 5-19, wherein The m0 is determined according to a first cell identifier. The method of claim 4, wherein k=7, N=127, M=8; When the element x(i+7) in the first sequence satisfies: x(i+7)=(x(i+1)+x(i))mod 2, the initial value is one of the following initial values: [0, 0, 0, 0, 0, 0, 1], [0, 0, 0, 0, 0, 1, 1], [0, 0, 1, 0, 0, 0, 0], [0, 0, 1, 1, 1, 1, 1], [0, 1, 0, 0, 0, 0, 0], [0, 1, 1, 0, 0, 1, 1], [0, 1, 1, 0, 1, 1, 0], [0, 1, 1, 1, 0, 1, 1], [0, 1, 1, 1, 1, 1, 1], [1, 0, 1, 0, 1, 0, 1], [1, 1, 0, 0, 1, 0, 0], [1, 1, 0, 1, 0, 1, 1], [1, 1, 0, 1, 1, 1, 1], [1, 1, 1, 0, 1, 1, 0], [1, 1, 1, 1, 1, 0, 1], [1, 1, 1, 1, 1, 1, 1]; or, When the element x(i+7) in the first sequence satisfies: x(i+7)=(x(i+4)+x(i))mod 2, the initial value is one of the initial values as follows: [0, 0, 0, 0, 0, 0, 1], [0, 0, 0, 0, 0, 1, 0], [0, 0, 0, 0, 1, 1, 1], [0, 0, 0, 1, 0, 1, 1], [0, 0, 0, 1, 1, 0, 0], [0, 0, 1, 0, 0, 0, 0], [0, 1, 0, 0, 0, 1, 0], [0, 1, 0, 0, 1, 1, 0], [0, 1, 0, 1, 1, 0, 1], [0, 1, 0, 1, 1, 1, 0], [0, 1, 1, 0, 1, 1, 0], [1, 0, 0, 1, 0, 0, 1], [1, 1, 0, 0, 0, 0, 0]. The method of claim 4, wherein The element x(i+6) in the first sequence satisfies: x(i+6)=(x(i+5)+x(i))mod 2; When k=6, N=63, and M=8, the initial value is one of the initial values as follows: [0, 0, 0, 0, 1, 0], [0, 0, 0, 0, 1, 1], [0, 0, 1, 0, 0, 0], [0, 0, 1, 1, 1, 1], [0, 1, 0, 1, 0, 1], [0, 1, 1, 0, 0, 1], [0, 1, 1, 0, 1, 1], [1, 0, 0, 0, 0, 0], [1, 0, 0, 1, 1, 0], [1, 0, 1, 1, 1, 0], [1, 0, 1, 1, 1, 1], [1, 1, 0, 0, 1, 1], [1, 1, 0, 1, 0, 0], [1, 1, 1, 0, 1, 1], [1, 1, 1, 1, 0, 1], [1, 1, 1, 1, 1, 1]; or, When k=6, N=63, and M=4, the initial value is one of the initial values as follows: [0, 0, 0, 0, 1, 0], [0, 0, 0, 0, 1, 1], [0, 0, 1, 0, 0, 0], [0, 0, 1, 1, 1, 1], [0, 1, 0, 1, 0, 1], [0, 1, 1, 0, 0, 1], [0, 1, 1, 0, 1, 1], [1, 0, 0, 0, 0, 0], [1, 0, 0, 1, 1, 0], [1, 1, 0, 0, 0, 0], [1, 1, 0, 0, 1, 1], [1, 1, 0, 1, 0, 1], [1, 1, 0, 1, 1, 1], [1, 1, 1, 1, 0, 1], [1, 1, 1, 1, 0, 1], [1, 1, 1, 1, 1, 1]. The method of claim 4, wherein The element x(i+6) in the first sequence satisfies: x(i+6)=(x(i+5)+x(i))mod 2; when k=6, N=63, M=8, the initial value is one of the initial values as follows: [0, 0, 0, 1, 0, 0], [0, 0, 0, 1, 1, 0], [0, 0, 0, 1, 1, 0], [0, 0, 1, 0, 0, 1], [0, 0, 1, 1, 0, 1], [0, 1, 0, 0, 0, 1], [0, 1, 0, 1, 1, 1], [0, 1, 1, 0, 0, 1], [0, 1, 1, 0, 1, 1], [1, 0, 0, 0, 0, 0], [1, 0, 0, 0, 0, 1], [1, 0, 0, 0, 1, 1], [1, 0, 1, 1, 0, 1], [1, 1, 0, 0, 0, 0], [1, 1, 0, 0, 1, 0], [1, 1, 0, 1, 1, 1]; or, when k=6, N=63, M=4, the initial value is one of the initial values as follows: [0, 0, 0, 0, 1, 0], [0, 0, 0, 0, 1, 1], [0, 0, 0, 1, 0, 0], [0, 0, 0, 1, 1, 0], [0, 0, 0, 1, 1, 1], [0, 0, 1, 0, 0, 0], [0, 0, 1, 1, 0, 1], [0, 1, 0, 0, 0, 1], [0, 1, 1, 0, 0, 1], [0, 1, 1, 0, 1, 1], [0, 1, 1, 1, 0, 0], [1, 0, 0, 0, 0, 0], [1, 0, 0, 0, 0, 1], [1, 0, 0, 0, 1, 1], [1, 1, 0, 1, 1, 0], [1, 1, 1, 0, 0, 0]. The method of claim 4, wherein The method further comprises: mapping element 0 in the first sequence as [0, 1], mapping element 1 in the first sequence as [1, 0]; or, mapping element 1 in the first sequence as [0, 1], mapping element 0 in the first sequence as [1, 0]; and, element x(i+6) in the first sequence satisfies: x(i+6)=(x(i+1)+x(i))mod2. when k=6, N=63, M=8, the initial value is one of the initial values as follows: [0, 0, 0, 0, 1, 0], [0, 0, 0, 1, 0, 1], [0, 0, 1, 0, 0, 1], [0, 0, 1, 1, 0, 0], [0, 0, 1, 1, 1, 1], [0, 1, 0, 1, 0, 1], [0, 1, 1, 0, 0, 1], [0, 1, 1, 0, 1, 1], [0, 1, 1, 1, 0, 0], [1, 0, 0, 0, 0, 0], [1, 0, 0, 1, 0, 1], [1, 0, 1, 1, 0, 1], [1, 1, 0, 1, 0, 0], [1, 1, 0, 1, 0, 1], [1, 1, 1, 0, 1, 1], [1, 1, 1, 1, 0, 1]; or, When k=6, N=63, M=4, the initial value is one of the following initial values: [0, 0, 0, 1, 0, 1], [0, 0, 0, 1, 1, 1], [0, 0, 1, 0, 0, 1], [0, 0, 1, 0, 1, 0], [0, 0, 1, 1, 1, 0], [0, 1, 0, 0, 0, 0], [0, 1, 0, 0, 0, 1], [0, 1, 0, 1, 1, 1], [0, 1, 1, 0, 0, 0], [0, 1, 1, 0, 1, 1], [0, 1, 1, 1, 1, 1], [1, 0, 0, 0, 0, 0], [1, 0, 0, 0, 0, 1], [1, 0, 0, 0, 1, 1], [1, 0, 1, 1, 0, 1], [1, 1, 1, 1, 0, 1]. The method of claim 4, wherein An element x(i+5) in the first sequence satisfies: x(i+5)=(x(i+2)+x(i))mod2; When k=5, N=31, M=4, the initial value is one of the following initial values: [0, 0, 0, 0, 1], [0, 0, 0, 1, 1], [0, 0, 1, 1, 1], [0, 1, 0, 0, 0], [0, 1, 0, 1, 1], [0, 1, 1, 0, 0], [0, 1, 1, 0, 1], [0, 1, 1, 1, 1], [1, 0, 0, 1, 1], [1, 0, 1, 0, 0], [1, 1, 0, 0, 0], [1, 1, 0, 0, 1], [1, 1, 1, 0, 0], [1, 1, 1, 1, 0], [1, 1, 1, 1, 1]; or, When k=5, N=31, M=2, the initial value is one of the following initial values: [0, 0, 0, 1, 1], [0, 0, 1, 0, 0], [0, 0, 1, 1, 0], [0, 0, 1, 1, 1], [0, 1, 0, 0, 1], [0, 1, 1, 0, 1], [0, 1, 1, 1, 1], [1, 0, 0, 0, 1], [1, 0, 0, 1, 0], [1, 0, 1, 0, 0], [1, 1, 0, 0, 1], [1, 1, 0, 1, 1], [1, 1, 1, 0, 0], [1, 1, 1, 1, 0]. The method of claim 4, wherein The method further comprises: mapping element 0 in the first sequence as [0, 1], and mapping element 1 in the first sequence as [1, 0]; or mapping element 1 in the first sequence as [0, 1], and mapping element 0 in the first sequence as [1, 0]; and an element x(i+5) in the first sequence satisfies: x(i+5)=(x(i+2)+x(i))mod2. When k=5, N=31, M=8, the initial value is one of the following initial values: [0, 0, 0, 0, 1], [0, 0, 1, 0, 0], [0, 0, 1, 0, 1], [0, 0, 1, 1, 1], [0, 1, 0, 0, 0], [0, 1, 0, 1, 0], [0, 1, 1, 0, 0], [0, 1, 1, 0, 1], [0, 1, 1, 1, 0], [1, 0, 0, 1, 0], [1, 0, 0, 1, 1], [1, 0, 1, 0, 0], [1, 0, 1, 1, 1], [1, 1, 0, 1, 1], [1, 1, 1, 0, 0], [1, 1, 1, 1, 1]; or, When k=5, N=31, M=4, the initial value is one of the following initial values: [0, 0, 0, 0, 1], [0, 0, 0, 1, 1], [0, 0, 1, 0, 1], [0, 1, 0, 0, 0], [0, 1, 0, 0, 1], [0, 1, 1, 0, 0], [0, 1, 1, 0, 1], [0, 1, 1, 1, 1], [1, 0, 0, 1, 0], [1, 0, 0, 1, 1], [1, 0, 1, 0, 0], [1, 0, 1, 1, 1], [1, 1, 0, 0, 0], [1, 1, 0, 1, 1], [1, 1, 1, 0, 0], [1, 1, 1, 1, 1]. The method of claim 4, wherein The method further comprises: mapping element 0 in the first sequence as [0, 1], and mapping element 1 in the first sequence as [1, 0]; or mapping element 1 in the first sequence as [0, 1], and mapping element 0 in the first sequence as [1, 0]; and k=4, N=15, M=4; When element x(i+4) in the first sequence satisfies: x(i+4)=(x(i+1)+x(i))mod2, the initial value is one of the following initial values: [0, 0, 1, 1], [0, 1, 0, 1], [1, 0, 0, 0], [1, 0, 0, 1], [1, 0, 1, 1], [1, 1, 0, 0], [1, 1, 0, 1], [1, 1, 1, 1]; or, When element x(i+4) in the first sequence satisfies: x(i+4)=(x(i+3)+x(i))mod2, the initial value is one of the following initial values: [0, 0, 0, 1], [0, 0, 1, 0], [0, 0, 1, 1], [0, 1, 0, 0], [1, 0, 0, 0], [1, 1, 0, 0], [1, 1, 0, 1], [1, 1, 1, 1]. The method of claim 4, wherein k=4, N=15, M=2; When element x(i+4) in the first sequence satisfies: x(i+4)=(x(i+1)+x(i))mod2, the initial value is one of the following initial values: [0, 0, 1, 1], [0, 1, 0, 1], [0, 1, 1, 1], [1, 0, 1, 0], [1, 0, 1, 1], [1, 1, 0, 1], [1, 1, 1, 0], [1, 1, 1, 1]; or, The initial value is one of the following initial values: [0, 0, 0, 1], [0, 0, 1, 1], [0, 1, 0, 1], [1, 1, 1, 1], [1, 0, 0, 0], [1, 0, 1, 1], [1, 1, 1, 0], [1, 1, 1, 1] when the element x(i+4) in the first sequence satisfies: x(i+4) = (x(i+3) + x(i)) mod 2. The method of claim 4, wherein The method further comprises: mapping element 0 in the first sequence as [0, 1], and mapping element 1 in the first sequence as [1, 0]; or mapping element 1 in the first sequence as [0, 1], and mapping element 0 in the first sequence as [1, 0]; and k = 4, N = 15, M = 2. The initial value is one of the following initial values: [0, 0, 0, 1], [0, 0, 1, 0], [0, 1, 0, 0], [0, 1, 1, 0], [1, 0, 0, 1], [1, 0, 1, 1], [1, 1, 0, 1], [1, 1, 1, 1] when the element x(i+4) in the first sequence satisfies: x(i+4) = (x(i+1) + x(i)) mod 2. The initial value is one of the following initial values: [0, 0, 0, 1], [0, 0, 1, 0], [0, 0, 1, 1], [0, 1, 0, 0], [1, 1, 0, 0], [1, 1, 0, 1], [1, 1, 1, 0], [1, 1, 1, 1] when the element x(i+4) in the first sequence satisfies: x(i+4) = (x(i+3) + x(i)) mod 2. The method of any one of claims 20-29, wherein The first sequence is related to a first cell identifier, and / or a cyclic shift of the first sequence is related to a first cell identifier. A communication method characterized by comprising: Comprise: Receiving a low-power synchronization signal; Processing the low-power synchronization signal based on a first sequence, the first sequence being related to one or more of: a number of time units occupied by the first sequence, a number of bits M carried by each time unit, a subcarrier spacing, or a type of cyclic prefix (CP). The method of claim 31, wherein The first sequence LP_SS satisfies: LP_SS = (x0 + x1) mod 2, wherein x0 is a second sequence, x1 is a third sequence, mod is a modulo operation, lengths of the second sequence and the third sequence are N, N = 2 k -1, k is a positive integer; The second sequence is related to one or more of: a number of time units occupied by the second sequence, a number of bits M carried by each time unit, a subcarrier spacing, or a type of CP; The third sequence is related to one or more of: a number of time units occupied by the third sequence, a number of bits M carried by each time unit, a subcarrier spacing, or a type of CP. The method of claim 31, wherein The first sequence LP_SS(n) satisfies: LP_SS(n) = [x0(n) + x1((n + m0) mod N)] mod 2 wherein x0(n) is a second sequence, x1(n) is a third sequence, m0 is a cyclic shift, n is an integer greater than or equal to 0 and less than N, N is a length of the second sequence and the third sequence, N=2 k -1, k is a positive integer, and mod is a modulo operation. The method of claim 31, wherein The first sequence is related to one or more of: a number of time units occupied by the first sequence, a number of bits M carried by each time unit, a subcarrier spacing, or a type of CP, comprising: The initial value of the first sequence is related to one or more of the following: the number of time units occupied by the first sequence, the number of bits M carried by each time unit, the subcarrier spacing, or the type of CP. The method of claim 32 or 33, wherein k = 7, N = 127, M = 8; The element x0(i+7) in the second sequence satisfies: x0(i+7) = (x0(i+1) + x0(i)) mod 2, and the element x1(i+7) in the third sequence satisfies: x1(i+7) = (x1(i+3) + x1(i)) mod 2; or, The element x0(i+7) in the second sequence satisfies: x0(i+7) = (x0(i+1) + x0(i)) mod 2, and the element x1(i+7) in the third sequence satisfies: x1(i+7) = (x1(i+4) + x1(i)) mod 2. The method of claim 35, wherein When the element x0(i+7) in the second sequence satisfies: x0(i+7) = (x0(i+1) + x0(i)) mod 2, and the element x1(i+7) in the third sequence satisfies: x1(i+7) = (x1(i+3) + x1(i)) mod 2, the m0 belongs to a first set, and the first set includes one or more cyclic shifts as follows: 3, 912, 15, 19, 31, 35, 46, 48, 57, 60, 61, 62, 64, 65, 71, 82, 87, 92, 94, 99, 101, 107, 108, 113, 114, 117, 120, 121, 122, 123, 124. The method of claim 36, wherein When the element x0(i+7) in the second sequence satisfies: x0(i+7) = (x0(i+1) + x0(i)) mod 2, and the element x1(i+7) in the third sequence satisfies: x1(i+7) = (x1(i+4) + x1(i)) mod 2, the m0 belongs to a second set, and the second set includes one or more cyclic shifts as follows: 24, 29, 34, 36, 39, 46, 47, 50, 53, 58, 61, 62, 65, 66, 78, 82, 84, 85, 86, 96, 100, 105, 106, 109, 111, 112, 116, 117, 120, 123, 125, 126. The method of claim 32 or 33, wherein k = 6, N = 63, M = 8 or M = 4; The element x0(i+6) in the second sequence satisfies: x0(i+6) = (x0(i+1) + x0(i)) mod 2, and the element x1(i+6) in the third sequence satisfies: x1(i+6) = (x1(i+5) + x1(i)) mod 2. The method of claim 38, wherein When M=8, the m0 belongs to a third set, the third set comprising one or more cyclic shifts of: 2, 4, 5, 8, 9, 10, 11, 12, 13, 14, 16, 18, 19, 21, 22, 23, 27, 28, 33, 39, 40, 43, 45, 49, 50, 51, 52, 55, 57, 58, 60, 61. The method of claim 38, wherein When M=4, the m0 belongs to a fourth set, the fourth set comprising one or more cyclic shifts of: 2, 4, 5, 9, 13, 14, 16, 18, 19, 22, 23, 25, 27, 28, 30, 31, 33, 34, 39, 40, 41, 43, 45, 49, 50, 51, 52, 53, 55, 57, 58, 60. The method of claim 38, wherein The method further comprises: mapping element 0 in the first sequence as [0, 1], and mapping element 1 in the first sequence as [1, 0]; or mapping element 1 in the first sequence as [0, 1], and mapping element 0 in the first sequence as [1, 0]; Wherein, when M=8, the m0 belongs to a fifth set, the fifth set comprising one or more cyclic shifts of: 1, 3, 6, 7, 8, 10, 12, 13, 15, 20, 21, 24, 26, 31, 32, 35, 36, 37, 41, 42, 43, 44, 47, 50, 53, 54, 56, 57, 59, 61, 62, 63. The method of claim 32 or 33, wherein k=5, N=31, M=8, M=4 or M=2; The element x0(i+5) in the second sequence satisfies: x0(i+5)=(x0(i+2)+x0(i))mod2, and the element x1(i+5) in the third sequence satisfies: x1(i+5)=(x1(i+3)+x1(i+2)+x1(i+1)+x1(i))mod2; or, The element x0(i+5) in the second sequence satisfies: x0(i+5)=(x0(i+2)+x0(i))mod2, and the element x1(i+5) in the third sequence satisfies: x1(i+5)=(x1(i+4)+x1(i+2)+x1(i+1)+x1(i))mod2. The method of claim 42, wherein When the element x0(i+5) in the second sequence satisfies: x0(i+5)=(x0(i+2)+x0(i))mod2, and the element x1(i+5) in the third sequence satisfies: x1(i+5)=(x1(i+3)+x1(i+2)+x1(i+1)+x1(i))mod2, the m0 belongs to a sixth set, the sixth set comprising one or more cyclic shifts of: 2, 4, 5, 7, 9, 10, 12, 13, 16, 20, 21, 23, 24, 25, 26, 27; or 2, 5, 7, 9, 10, 12, 13, 16, 21, 23, 24, 25, 26, 27, 29, 30, 31. The method of claim 42, wherein The method further comprises: mapping element 0 in the first sequence as [0, 1], and mapping element 1 in the first sequence as [1, 0]; or mapping element 1 in the first sequence as [0, 1], and mapping element 0 in the first sequence as [1, 0]; When M = 8, the m0 belongs to a seventh set, and the seventh set comprises one or more cyclic shifts as follows: 1, 2, 3, 8, 10, 11, 13, 14, 15, 18, 19, 22, 27, 28, 29, 31; or, When M = 4, the m0 belongs to an eighth set, and the eighth set comprises one or more cyclic shifts as follows: 1, 2, 3, 4, 6, 8, 11, 13, 14, 15, 18, 19, 22, 28, 29, 31. The method of claim 42, wherein When the element x0(i+5) in the second sequence satisfies: x0(i+5) = (x0(i+2) + x0(i)) mod 2, and the element x1(i+5) in the third sequence satisfies: x1(i+5) = (x1(i+4) + x1(i+2) + x1(i+1) + x1(i)) mod 2, the m0 belongs to a ninth set, and the ninth set comprises one or more cyclic shifts as follows: 1, 2, 3, 5, 6, 8, 9, 11, 12, 15, 16, 20, 21, 23, 28, 31; or, 1, 2, 3, 5, 6, 8, 9, 11, 12, 13, 15, 16, 20, 21, 23, 28. The method of claim 42, wherein The method further comprises: mapping element 0 in the first sequence as [0, 1], and mapping element 1 in the first sequence as [1, 0]; or mapping element 1 in the first sequence as [0, 1], and mapping element 0 in the first sequence as [1, 0]; When M = 8, the m0 belongs to a tenth set, and the tenth set comprises one or more cyclic shifts as follows: 4, 7, 10, 11, 13, 14, 18, 19, 20, 22, 24, 25, 27, 29, 30, 31; or, When M = 4, the m0 belongs to an eleventh set, and the eleventh set comprises one or more cyclic shifts as follows: 2, 4, 7, 8, 10, 14, 18, 19, 20, 22, 24, 25, 27, 29, 30, 31. The method of claim 32 or 33, wherein k = 4, N = 15, M = 4 or M = 2; The element x0(i+4) in the second sequence satisfies: x0(i+4) = (x0(i+1) + x0(i)) mod 2, and the element x1(i+4) in the third sequence satisfies: x1(i+4) = (x1(i+3) + x1(i)) mod 2. The method of claim 47, wherein The m0 belongs to a twelfth set, and the twelfth set comprises one or more cyclic shifts as follows: 2, 5, 7, 8, 9, 11, 12, 13. The method of claim 47, wherein The method further comprises: mapping element 0 in the first sequence as [0, 1], and mapping element 1 in the first sequence as [1, 0]; or mapping element 1 in the first sequence as [0, 1], and mapping element 0 in the first sequence as [1, 0]; Wherein, the m0 belongs to a thirteenth set, and the thirteenth set comprises one or more cyclic shifts as follows: 1, 3, 4, 6, 8, 12, 14, 15. The method of any one of claims 33, 36-49, wherein The m0 is determined according to a first cell identifier. The method of claim 35, wherein k=7, N=127, M=8; When the element x(i+7) in the first sequence satisfies: x(i+7)=(x(i+1)+x(i))mod 2, the initial value is one of the initial values as follows: [0, 0, 0, 0, 0, 0, 1], [0, 0, 0, 0, 0, 1, 1], [0, 0, 1, 0, 0, 0, 0], [0, 0, 1, 1, 1, 1, 1], [0, 1, 0, 0, 0, 0, 0], [0, 1, 1, 0, 0, 1, 1], [0, 1, 1, 0, 1, 1, 0], [0, 1, 1, 1, 0, 1, 1], [0, 1, 1, 1, 1, 1, 1], [1, 0, 1, 0, 1, 0, 1], [1, 1, 0, 0, 1, 0, 0], [1, 1, 0, 1, 0, 1, 1], [1, 1, 0, 1, 1, 1, 1], [1, 1, 1, 0, 1, 1, 0], [1, 1, 1, 1, 1, 0, 1], [1, 1, 1, 1, 1, 1, 1]; or, When the element x(i+7) in the first sequence satisfies: x(i+7)=(x(i+4)+x(i))mod 2, the initial value is one of the initial values as follows: [0, 0, 0, 0, 0, 0, 1], [0, 0, 0, 0, 0, 1, 0], [0, 0, 0, 0, 1, 1, 1], [0, 0, 0, 1, 0, 1, 1], [0, 0, 0, 1, 1, 0, 0], [0, 0, 1, 0, 0, 0, 0], [0, 1, 0, 0, 0, 1, 0], [0, 1, 0, 0, 1, 1, 0], [0, 1, 0, 1, 1, 0, 1], [0, 1, 0, 1, 1, 1, 0], [0, 1, 1, 0, 1, 1, 0], [1, 0, 0, 1, 0, 0, 1], [1, 1, 0, 0, 0, 0, 0]. The method of claim 35, wherein The element x(i+6) in the first sequence satisfies: x(i+6)=(x(i+1)+x(i))mod 2; When k=6, N=63, M=8, the initial value is one of the following initial values: [0, 0, 0, 0, 1, 0], [0, 0, 0, 0, 1, 1], [0, 0, 1, 0, 0, 0], [0, 0, 1, 1, 1, 1], [0, 1, 0, 1, 0, 1], [0, 1, 1, 0, 0, 1], [0, 1, 1, 0, 1, 1], [1, 0, 0, 0, 0, 0], [1, 0, 0, 1, 1, 0], [1, 0, 1, 1, 1, 0], [1, 0, 1, 1, 1, 1], [1, 1, 0, 0, 1, 1], [1, 1, 0, 1, 0, 0], [1, 1, 1, 0, 1, 1], [1, 1, 1, 1, 0, 1], [1, 1, 1, 1, 1, 1]; or, When k=6, N=63, M=4, the initial value is one of the following initial values: [0, 0, 0, 0, 1, 0], [0, 0, 0, 0, 1, 1], [0, 0, 1, 0, 0, 0], [0, 0, 1, 1, 1, 1], [0, 1, 0, 1, 0, 1], [0, 1, 1, 0, 0, 1], [0, 1, 1, 0, 1, 1], [1, 0, 0, 0, 0, 0], [1, 0, 0, 1, 1, 0], [1, 1, 0, 0, 0, 0], [1, 1, 0, 0, 1, 1], [1, 1, 0, 1, 0, 1], [1, 1, 0, 1, 1, 1], [1, 1, 1, 1, 0, 1], [1, 1, 1, 1, 0, 1], [1, 1, 1, 1, 1, 1]. The method of claim 35, wherein The element x(i+6) in the first sequence satisfies: x(i+6)=(x(i+5)+x(i))mod2; When k=6, N=63, M=8, the initial value is one of the following initial values: [0, 0, 0, 1, 0, 0], [0, 0, 0, 1, 1, 0], [0, 0, 0, 1, 1, 0], [0, 0, 1, 0, 0, 1], [0, 0, 1, 1, 0, 1], [0, 1, 0, 0, 0, 1], [0, 1, 0, 1, 1, 1], [0, 1, 1, 0, 0, 1], [0, 1, 1, 0, 1, 1], [1, 0, 0, 0, 0, 0], [1, 0, 0, 0, 0, 1], [1, 0, 0, 0, 1, 1], [1, 0, 1, 1, 0, 1], [1, 1, 0, 0, 0, 0], [1, 1, 0, 0, 1, 0], [1, 1, 0, 1, 1, 1]; or, When k=6, N=63, M=4, the initial value is one of the following initial values: [0, 0, 0, 0, 1, 0], [0, 0, 0, 0, 1, 1], [0, 0, 0, 1, 0, 0], [0, 0, 0, 1, 1, 0], [0, 0, 0, 1, 1, 1], [0, 0, 1, 0, 0, 0], [0, 0, 1, 1, 0, 1], [0, 1, 0, 0, 0, 1], [0, 1, 1, 0, 0, 1], [0, 1, 1, 0, 1, 1], [0, 1, 1, 1, 0, 0], [1, 0, 0, 0, 0, 0], [1, 0, 0, 0, 0, 1], [1, 0, 0, 0, 1, 1], [1, 1, 0, 1, 1, 0], [1, 1, 1, 0, 0, 0]. The method of claim 35, wherein The method further comprises: mapping element 0 in the first sequence as [0, 1], mapping element 1 in the first sequence as [1, 0]; or, mapping element 1 in the first sequence as [0, 1], mapping element 0 in the first sequence as [1, 0]; and element x(i+6) in the first sequence satisfies: x(i+6)=(x(i+1)+x(i))mod2. When k=6, N=63, M=8, the initial value is one of the following initial values: [0, 0, 0, 0, 1, 0], [0, 0, 0, 1, 0, 1], [0, 0, 1, 0, 0, 1], [0, 0, 1, 1, 0, 0], [0, 0, 1, 1, 1, 1], [0, 1, 0, 1, 0, 1], [0, 1, 1, 0, 0, 1], [0, 1, 1, 0, 1, 1], [0, 1, 1, 1, 0, 0], [1, 0, 0, 0, 0, 0], [1, 0, 0, 1, 0, 1], [1, 0, 1, 1, 0, 1], [1, 1, 0, 1, 0, 0], [1, 1, 0, 1, 0, 1], [1, 1, 1, 0, 1, 1], [1, 1, 1, 1, 0, 1]; or, When k=6, N=63, M=4, the initial value is one of the following initial values: [0, 0, 0, 1, 0, 1], [0, 0, 0, 1, 1, 1], [0, 0, 1, 0, 0, 1], [0, 0, 1, 0, 1, 0], [0, 0, 1, 1, 1, 0], [0, 1, 0, 0, 0, 0], [0, 1, 0, 0, 0, 1], [0, 1, 0, 1, 1, 1], [0, 1, 1, 0, 0, 0], [0, 1, 1, 0, 1, 1], [0, 1, 1, 1, 1, 1], [1, 0, 0, 0, 0, 0], [1, 0, 0, 0, 0, 1], [1, 0, 0, 0, 1, 1], [1, 0, 1, 1, 0, 1], [1, 1, 1, 1, 0, 1]. The method of claim 35, wherein Element x(i+5) in the first sequence satisfies: x(i+5)=(x(i+2)+x(i))mod2; When k=5, N=31, M=4, the initial value is one of the following initial values: [0, 0, 0, 0, 1], [0, 0, 0, 1, 1], [0, 0, 1, 0, 1], [0, 1, 0, 0, 0], [0, 1, 0, 0, 1], [0, 1, 1, 0, 0], [0, 1, 1, 0, 1], [0, 1, 1, 1, 1], [1, 0, 0, 1, 0], [1, 0, 0, 1, 1], [1, 0, 1, 0, 0], [1, 0, 1, 1, 1], [1, 1, 0, 0, 0], [1, 1, 0, 1, 1], [1, 1, 1, 0, 0], [1, 1, 1, 1, 1]; or, When k=5, N=31, M=2, the initial value is one of the following initial values: [0, 0, 0, 1, 1], [0, 0, 1, 0, 0], [0, 0, 1, 1, 0], [0, 0, 1, 1, 1], [0, 1, 0, 0, 1], [0, 1, 1, 0, 1], [0, 1, 1, 1, 1], [1, 0, 0, 0, 1], [1, 0, 0, 1, 0], [1, 0, 1, 0, 0], [1, 1, 0, 0, 1], [1, 1, 0, 1, 1], [1, 1, 1, 0, 0], [1, 1, 1, 1, 0]. The method of claim 35, wherein The method further comprises: mapping element 0 in the first sequence as [0, 1], mapping element 1 in the first sequence as [1, 0]; or, mapping element 1 in the first sequence as [0, 1], mapping element 0 in the first sequence as [1, 0]; and, element x(i+5) in the first sequence satisfies: x(i+5)=(x(i+2)+x(i))mod2. When k=5, N=31, M=8, the initial value is one of the following initial values: [0, 0, 0, 0, 1], [0, 0, 1, 0, 0], [0, 0, 1, 0, 1], [0, 0, 1, 1, 1], [0, 1, 0, 0, 0], [0, 1, 0, 1, 0], [0, 1, 1, 0, 0], [0, 1, 1, 0, 1], [0, 1, 1, 1, 0], [1, 0, 0, 1, 0], [1, 0, 0, 1, 1], [1, 0, 1, 0, 0], [1, 0, 1, 1, 1], [1, 1, 0, 1, 1], [1, 1, 1, 0, 0], [1, 1, 1, 1, 1]; or, When k=5, N=31, M=4, the initial value is one of the following initial values: [0, 0, 0, 0, 1], [0, 0, 0, 1, 1], [0, 0, 1, 0, 1], [0, 1, 0, 0, 0], [0, 1, 0, 0, 1], [0, 1, 1, 0, 0], [0, 1, 1, 0, 1], [0, 1, 1, 1, 1], [1, 0, 0, 1, 0], [1, 0, 0, 1, 1], [1, 0, 1, 0, 0], [1, 0, 1, 1, 1], [1, 1, 0, 0, 0], [1, 1, 0, 1, 1], [1, 1, 1, 0, 0], [1, 1, 1, 1, 1]. The method of claim 35, wherein The method further comprises: mapping element 0 in the first sequence as [0, 1], and mapping element 1 in the first sequence as [1, 0]; or mapping element 1 in the first sequence as [0, 1], and mapping element 0 in the first sequence as [1, 0]; and k = 4, N = 15, and M = 4. When element x(i+4) in the first sequence satisfies: x(i+4) = (x(i+1) + x(i)) mod 2, the initial value is one of the following initial values: [0, 0, 1, 1], [0, 1, 0, 1], [1, 0, 0, 0], [1, 0, 0, 1], [1, 0, 1, 1], [1, 1, 0, 0], [1, 1, 0, 1], [1, 1, 1, 1]; or, When element x(i+4) in the first sequence satisfies: x(i+4) = (x(i+3) + x(i)) mod 2, the initial value is one of the following initial values: [0, 0, 0, 1], [0, 0, 1, 0], [0, 0, 1, 1], [0, 1, 0, 0], [1, 0, 0, 0], [1, 1, 0, 0], [1, 1, 0, 1], [1, 1, 1, 1]. The method of claim 35, wherein k = 4, N = 15, and M = 2. When element x(i+4) in the first sequence satisfies: x(i+4) = (x(i+1) + x(i)) mod 2, the initial value is one of the following initial values: [0, 0, 1, 1], [0, 1, 0, 1], [0, 1, 1, 1], [1, 0, 1, 0], [1, 0, 1, 1], [1, 1, 0, 1], [1, 1, 1, 0], [1, 1, 1, 1]; Or, When element x(i+4) in the first sequence satisfies: x(i+4) = (x(i+3) + x(i)) mod 2, the initial value is one of the following initial values: [0, 0, 0, 1], [0, 0, 1, 1], [0, 1, 0, 1], [1, 1, 1, 1], [1, 0, 0, 0], [1, 0, 1, 1], [1, 1, 1, 0], [1, 1, 1, 1]. The method of claim 35, wherein The method further comprises: mapping element 0 in the first sequence as [0, 1], and mapping element 1 in the first sequence as [1, 0]; or mapping element 1 in the first sequence as [0, 1], and mapping element 0 in the first sequence as [1, 0]; and k = 4, N = 15, and M = 2. When element x(i+4) in the first sequence satisfies: x(i+4) = (x(i+1) + x(i)) mod 2, the initial value is one of the following initial values: [0, 0, 0, 1], [0, 0, 1, 0], [0, 1, 0, 0], [0, 1, 1, 0], [1, 0, 0, 1], [1, 0, 1, 1], [1, 1, 0, 1], [1, 1, 1, 1]; or, The initial value is one of the following initial values: [0, 0, 0, 1], [0, 0, 1, 0], [0, 0, 1, 1], [0, 1, 0, 0], [1, 1, 0, 0], [1, 1, 0, 1], [1, 1, 1, 0], [1, 1, 1, 1] when the element x(i+4) in the first sequence satisfies x(i+4) = (x(i+3) + x(i)) mod 2. The method of any one of claims 51-59, wherein The first sequence is related to a first cell identifier, and / or a cyclic shift of the first sequence is related to the first cell identifier. A communication device, characterized by Comprise: A processing module, configured to determine a low-power synchronization signal, wherein a sequence used to generate the low-power synchronization signal is a first sequence, and the first sequence is related to one or more of the following: a number of time units occupied by the first sequence, a number of bits M carried by each time unit, a subcarrier spacing, or a type of cyclic prefix (CP); A transceiver module, configured to send the low-power synchronization signal. The apparatus of claim 61, wherein The first sequence LP_SS satisfies: LP_SS = (x0 + x1) mod 2, wherein x0 is a second sequence, x1 is a third sequence, mod is a modulo operation, lengths of the second sequence and the third sequence are N, N = 2 k -1, k is a positive integer; The second sequence is related to one or more of the following: a number of time units occupied by the second sequence, a number of bits M carried by each time unit, a subcarrier spacing, or a type of CP; The third sequence is related to one or more of the following: a number of time units occupied by the third sequence, a number of bits M carried by each time unit, a subcarrier spacing, or a type of CP. The apparatus of claim 61, wherein The first sequence LP_SS(n) satisfies: LP_SS(n) = [x0(n) + x1((n + m0) mod N)] mod 2 wherein x0(n) is a second sequence, x1(n) is a third sequence, m0 is a cyclic shift, n is an integer greater than or equal to 0 and less than N, N is a length of the second sequence and the third sequence, N=2 k -1, k is a positive integer, and mod is a modulo operation. The apparatus of claim 61, wherein The first sequence is related to one or more of the following: a number of time units occupied by the first sequence, a number of bits M carried by each time unit, a subcarrier spacing, or a type of CP, comprising: An initial value of the first sequence is related to one or more of the following: a number of time units occupied by the first sequence, a number of bits M carried by each time unit, a subcarrier spacing, or a type of CP. The apparatus of claim 62 or 63, wherein k = 7, N = 127, M = 8; The element x0(i+7) in the second sequence satisfies x0(i+7) = (x0(i+1) + x0(i)) mod 2, and the element x1(i+7) in the third sequence satisfies x1(i+7) = (x1(i+3) + x1(i)) mod 2; or The element x0(i+7) in the second sequence satisfies x0(i+7) = (x0(i+1) + x0(i)) mod 2, and the element x1(i+7) in the third sequence satisfies x1(i+7) = (x1(i+4) + x1(i)) mod 2. The apparatus of claim 65, wherein When the element x0(i+7) in the second sequence satisfies: x0(i+7)=(x0(i+1)+x0(i))mod 2, and the element x1(i+7) in the third sequence satisfies: x1(i+7)=(x1(i+3)+x1(i))mod 2, the m0 belongs to a first set, and the first set includes one or more cyclic shifts of: 3, 912, 15, 19, 31, 35, 46, 48, 57, 60, 61, 62, 64, 65, 71, 82, 87, 92, 94, 99, 101, 107, 108, 113, 114, 117, 120, 121, 122, 123, 124. The apparatus of claim 66, wherein When the element x0(i+7) in the second sequence satisfies: x0(i+7)=(x0(i+1)+x0(i))mod 2, and the element x1(i+7) in the third sequence satisfies: x1(i+7)=(x1(i+4)+x1(i))mod 2, the m0 belongs to a second set, and the second set includes one or more cyclic shifts of: 24, 29, 34, 36, 39, 46, 47, 50, 53, 58, 61, 62, 65, 66, 78, 82, 84, 85, 86, 96, 100, 105, 106, 109, 111, 112, 116, 117, 120, 123, 125, 126. The apparatus of claim 62 or 63, wherein k=6, N=63, M=8 or M=4; The element x0(i+6) in the second sequence satisfies: x0(i+6)=(x0(i+1)+x0(i))mod 2, and the element x1(i+6) in the third sequence satisfies: x1(i+6)=(x1(i+5)+x1(i))mod 2. The apparatus of claim 68, wherein When M=8, the m0 belongs to a third set, and the third set includes one or more cyclic shifts of: 2, 4, 5, 8, 9, 10, 11, 12, 13, 14, 16, 18, 19, 21, 22, 23, 27, 28, 33, 39, 40, 43, 45, 49, 50, 51, 52, 55, 57, 58, 60, 61. The apparatus of claim 68, wherein When M=4, the m0 belongs to a fourth set, and the fourth set includes one or more cyclic shifts of: 2, 4, 5, 9, 13, 14, 16, 18, 19, 22, 23, 25, 27, 28, 30, 31, 33, 34, 39, 40, 41, 43, 45, 49, 50, 51, 52, 53, 55, 57, 58, 60. The apparatus of claim 68, wherein The processing module is further configured to: map the element 0 in the first sequence as [0, 1], and map the element 1 in the first sequence as [1, 0]; or map the element 1 in the first sequence as [0, 1], and map the element 0 in the first sequence as [1, 0]. When M=8, the m0 belongs to a fifth set, the fifth set comprising one or more cyclic shifts of: 1, 3, 6, 7, 8, 10, 12, 13, 15, 20, 21, 24, 26, 31, 32, 35, 36, 37, 41, 42, 43, 44, 47, 50, 53, 54, 56, 57, 59, 61, 62, 63. The apparatus of claim 62 or 63, wherein k=5, N=31, M=8, M=4 or M=2; When the element x0(i+5) in the second sequence satisfies: x0(i+5)=(x0(i+2)+x0(i))mod2, and the element x1(i+5) in the third sequence satisfies: x1(i+5)=(x1(i+3)+x1(i+2)+x1(i+1)+x1(i))mod2, the m0 belongs to a sixth set, the sixth set comprising one or more cyclic shifts of: When the element x0(i+5) in the second sequence satisfies: x0(i+5)=(x0(i+2)+x0(i))mod2, and the element x1(i+5) in the third sequence satisfies: x1(i+5)=(x1(i+3)+x1(i+2)+x1(i+1)+x1(i))mod2, the m0 belongs to a sixth set, the sixth set comprising one or more cyclic shifts of: The apparatus of claim 72, wherein 2, 4, 5, 7, 9, 10, 12, 13, 16, 20, 21, 23, 24, 25, 26, 27; or 2, 5, 7, 9, 10, 12, 13, 16, 21, 23, 24, 25, 26, 27, 29, 30, 31. The processing module is further configured to: map the element 0 in the first sequence as [0, 1], and map the element 1 in the first sequence as [1, 0]; or map the element 1 in the first sequence as [0, 1], and map the element 0 in the first sequence as [1, 0]; The apparatus of claim 72, wherein When M=8, the m0 belongs to a seventh set, the seventh set comprising one or more cyclic shifts of: 1, 2, 3, 8, 10, 11, 13, 14, 15, 18, 19, 22, 27, 28, 29, 31; or When M=4, the m0 belongs to an eighth set, the eighth set comprising one or more cyclic shifts of: 1, 2, 3, 4, 6, 8, 11, 13, 14, 15, 18, 19, 22, 28, 29, 31. ​ The apparatus of claim 72, wherein when the element x0(i+5) in the second sequence satisfies: x0(i+5)=(x0(i+2)+x0(i))mod2, and the element x1(i+5) in the third sequence satisfies: x1(i+5)=(x1(i+4)+x1(i+2)+x1(i+1)+x1(i))mod2, the m0 belongs to a ninth set, and the ninth set includes one or more cyclic shifts as follows: 1, 2, 3, 5, 6, 8, 9, 11, 12, 15, 16, 20, 21, 23, 28, 31; or, 1, 2, 3, 5, 6, 8, 9, 11, 12, 13, 15, 16, 20, 21, 23, 28. The apparatus of claim 72, wherein The processing module is further configured to map element 0 in the first sequence as [0, 1] and element 1 in the first sequence as [1, 0], or map element 1 in the first sequence as [0, 1] and element 0 in the first sequence as [1, 0]; when M=8, the m0 belongs to a tenth set, and the tenth set includes one or more cyclic shifts as follows: 4, 7, 10, 11, 13, 14, 18, 19, 20, 22, 24, 25, 27, 29, 30, 31; or, when M=4, the m0 belongs to an eleventh set, and the eleventh set includes one or more cyclic shifts as follows: 2, 4, 7, 8, 10, 14, 18, 19, 20, 22, 24, 25, 27, 29, 30, 31. The apparatus of claim 62 or 63, wherein k=4, N=15, M=4 or M=2; The element x0(i+4) in the second sequence satisfies: x0(i+4)=(x0(i+1)+x0(i))mod2, and the element x1(i+4) in the third sequence satisfies: x1(i+4)=(x1(i+3)+x1(i))mod2. The apparatus of claim 77, wherein The m0 belongs to a twelfth set, and the twelfth set includes one or more cyclic shifts as follows: 2, 5, 7, 8, 9, 11, 12, 13. The apparatus of claim 77, wherein The processing module is further configured to map element 0 in the first sequence as [0, 1] and element 1 in the first sequence as [1, 0], or map element 1 in the first sequence as [0, 1] and element 0 in the first sequence as [1, 0]; wherein the m0 belongs to a thirteenth set, and the thirteenth set includes one or more cyclic shifts as follows: 1, 3, 4, 6, 8, 12, 14, 15. The apparatus of any one of claims 63, 65-79, wherein The m0 is determined according to a first cell identifier. The apparatus of claim 64, wherein k=7, N=127, M=8; When the element x(i+7) in the first sequence satisfies: x(i+7)=(x(i+1)+x(i))mod 2, the initial value is one of the initial values as follows: [0, 0, 0, 0, 0, 0, 1], [0, 0, 0, 0, 0, 1, 1], [0, 0, 1, 0, 0, 0, 0], [0, 0, 1, 1, 1, 1, 1], [0, 1, 0, 0, 0, 0, 0], [0, 1, 1, 0, 0, 1, 1], [0, 1, 1, 0, 1, 1, 0], [0, 1, 1, 1, 0, 1, 1], [0, 1, 1, 1, 1, 1, 1], [1, 0, 1, 0, 1, 0, 1], [1, 1, 0, 0, 1, 0, 0], [1, 1, 0, 1, 0, 1, 1], [1, 1, 0, 1, 1, 1, 1], [1, 1, 1, 0, 1, 1, 0], [1, 1, 1, 1, 0, 1, 1], [1, 1, 1, 1, 1, 1, 1]; or, When the element x(i+7) in the first sequence satisfies: x(i+7)=(x(i+4)+x(i))mod 2, the initial value is one of the initial values as follows: [0, 0, 0, 0, 0, 0, 1], [0, 0, 0, 0, 0, 1, 0], [0, 0, 0, 0, 1, 1, 1], [0, 0, 0, 1, 0, 1, 1], [0, 0, 0, 1, 1, 0, 0], [0, 0, 1, 0, 0, 0, 0], [0, 1, 0, 0, 0, 1, 0], [0, 1, 0, 0, 1, 1, 0], [0, 1, 0, 1, 1, 0, 1], [0, 1, 0, 1, 1, 1, 0], [0, 1, 1, 0, 1, 1, 0], [1, 0, 0, 1, 0, 0, 1], [1, 1, 0, 0, 0, 0, 0]. The apparatus of claim 64, wherein The element x(i+6) in the first sequence satisfies: x(i+6)=(x(i+1)+x(i))mod 2; When k=6, N=63, M=8, the initial value is one of the initial values as follows: [0, 0, 0, 0, 1, 0], [0, 0, 0, 0, 1, 1], [0, 0, 1, 0, 0, 0], [0, 0, 1, 1, 1, 1], [0, 1, 0, 1, 0, 1], [0, 1, 1, 0, 0, 1], [0, 1, 1, 0, 1, 1], [1, 0, 0, 0, 0, 0], [1, 0, 0, 1, 1, 0], [1, 0, 1, 1, 1, 0], [1, 0, 1, 1, 1, 1], [1, 1, 0, 0, 1, 1], [1, 1, 0, 1, 0, 0], [1, 1, 1, 0, 1, 1], [1, 1, 1, 1, 0, 1], [1, 1, 1, 1, 1, 1]; or, When k=6, N=63, and M=4, the initial value is one of the following initial values: [0, 0, 0, 0, 1, 0], [0, 0, 0, 0, 1, 1], [0, 0, 0, 1, 0, 0], [0, 0, 0, 1, 1, 0], [0, 0, 0, 1, 1, 1], [0, 0, 1, 0, 0, 0], [0, 0, 1, 1, 0, 1], [0, 1, 0, 0, 0, 1], [0, 1, 1, 0, 0, 1], [0, 1, 1, 0, 1, 1], [0, 1, 1, 1, 0, 0], [1, 0, 0, 0, 0, 0], [1, 0, 0, 0, 0, 1], [1, 0, 0, 0, 1, 1], [1, 1, 0, 1, 1, 0], [1, 1, 1, 0, 0, 0]. The apparatus of claim 64, wherein An element x(i+6) in the first sequence satisfies: x(i+6)=(x(i+5)+x(i))mod2; When k=6, N=63, and M=8, the initial value is one of the following initial values: [0, 0, 0, 1, 0, 0], [0, 0, 0, 1, 1, 0], [0, 0, 0, 1, 1, 0], [0, 0, 1, 0, 0, 1], [0, 0, 1, 1, 0, 1], [0, 1, 0, 0, 0, 1], [0, 1, 0, 1, 1, 1], [0, 1, 1, 0, 0, 1], [0, 1, 1, 0, 1, 1], [1, 0, 0, 0, 0, 0], [1, 0, 0, 0, 0, 1], [1, 0, 0, 0, 1, 1], [1, 0, 1, 1, 0, 1], [1, 1, 0, 0, 0, 0], [1, 1, 0, 0, 1, 0], [1, 1, 0, 1, 1, 1]; or, When k=6, N=63, and M=4, the initial value is one of the following initial values: [0, 0, 0, 0, 1, 0], [0, 0, 0, 0, 1, 1], [0, 0, 0, 1, 0, 0], [0, 0, 0, 1, 1, 0], [0, 0, 0, 1, 1, 1], [0, 0, 1, 0, 0, 0], [0, 0, 1, 1, 0, 1], [0, 1, 0, 0, 0, 1], [0, 1, 1, 0, 0, 1], [0, 1, 1, 0, 1, 1], [0, 1, 1, 1, 0, 0], [1, 0, 0, 0, 0, 0], [1, 0, 0, 0, 0, 1], [1, 0, 0, 0, 1, 1], [1, 1, 0, 1, 1, 0], [1, 1, 1, 0, 0, 0]. The apparatus of claim 64, wherein The processing module is further configured to: map an element 0 in the first sequence as [0, 1], and map an element 1 in the first sequence as [1, 0]; or map an element 1 in the first sequence as [0, 1], and map an element 0 in the first sequence as [1, 0]; and an element x(i+6) in the first sequence satisfies: x(i+6)=(x(i+1)+x(i))mod2. When k=6, N=63, M=8, the initial value is one of the following initial values: [0, 0, 0, 0, 1, 0], [0, 0, 0, 1, 0, 1], [0, 0, 1, 0, 0, 1], [0, 0, 1, 1, 0, 0], [0, 0, 1, 1, 1, 1], [0, 1, 0, 1, 0, 1], [0, 1, 1, 0, 0, 1], [0, 1, 1, 0, 1, 1], [0, 1, 1, 1, 0, 0], [1, 0, 0, 0, 0, 0], [1, 0, 0, 1, 0, 1], [1, 0, 1, 1, 0, 1], [1, 1, 0, 1, 0, 0], [1, 1, 0, 1, 0, 1], [1, 1, 1, 0, 1, 1], [1, 1, 1, 1, 0, 1]; or, When k=6, N=63, M=4, the initial value is one of the following initial values: [0, 0, 0, 1, 0, 1], [0, 0, 0, 1, 1, 1], [0, 0, 1, 0, 0, 1], [0, 0, 1, 0, 1, 0], [0, 0, 1, 1, 1, 0], [0, 1, 0, 0, 0, 0], [0, 1, 0, 0, 0, 1], [0, 1, 0, 1, 1, 1], [0, 1, 1, 0, 0, 0], [0, 1, 1, 0, 1, 1], [0, 1, 1, 1, 1, 1], [1, 0, 0, 0, 0, 0], [1, 0, 0, 0, 0, 1], [1, 0, 0, 0, 1, 1], [1, 0, 1, 1, 0, 1], [1, 1, 1, 1, 0, 1]. The apparatus of claim 64, wherein The element x(i+5) in the first sequence satisfies: x(i+5)=(x(i+2)+x(i))mod2; When k=5, N=31, M=4, the initial value is one of the following initial values: [0, 0, 0, 0, 1], [0, 0, 0, 1, 1], [0, 0, 1, 1, 1], [0, 1, 0, 0, 0], [0, 1, 0, 1, 1], [0, 1, 1, 0, 0], [0, 1, 1, 0, 1], [0, 1, 1, 1, 1], [1, 0, 0, 1, 1], [1, 0, 1, 0, 0], [1, 1, 0, 0, 0], [1, 1, 0, 0, 1], [1, 1, 1, 0, 0], [1, 1, 1, 1, 0], [1, 1, 1, 1, 1]; or, When k=5, N=31, M=2, the initial value is one of the following initial values: [0, 0, 0, 1, 1], [0, 0, 1, 0, 0], [0, 0, 1, 1, 0], [0, 0, 1, 1, 1], [0, 1, 0, 0, 1], [0, 1, 1, 0, 1], [0, 1, 1, 1, 1], [1, 0, 0, 0, 1], [1, 0, 0, 1, 0], [1, 0, 1, 0, 0], [1, 1, 0, 0, 1], [1, 1, 0, 1, 1], [1, 1, 1, 0, 0], [1, 1, 1, 1, 0]. The apparatus of claim 64, wherein The processing module is further configured to: map element 0 in the first sequence as [0, 1], and map element 1 in the first sequence as [1, 0]; or map element 1 in the first sequence as [0, 1], and map element 0 in the first sequence as [1, 0]; and element x(i+5) in the first sequence satisfies: x(i+5) = (x(i+2) + x(i)) mod 2. When k = 5, N = 31, and M = 8, the initial value is one of the following initial values: [0, 0, 0, 0, 1], [0, 0, 1, 0, 0], [0, 0, 1, 0, 1], [0, 0, 1, 1, 1], [0, 1, 0, 0, 0], [0, 1, 0, 1, 0], [0, 1, 1, 0, 0], [0, 1, 1, 0, 1], [0, 1, 1, 1, 0], [1, 0, 0, 1, 0], [1, 0, 0, 1, 1], [1, 0, 1, 0, 0], [1, 0, 1, 1, 1], [1, 1, 0, 1, 1], [1, 1, 1, 0, 0], [1, 1, 1, 1, 1]; or, When k = 5, N = 31, and M = 4, the initial value is one of the following initial values: [0, 0, 0, 0, 1], [0, 0, 0, 1, 1], [0, 0, 1, 0, 1], [0, 1, 0, 0, 0], [0, 1, 0, 0, 1], [0, 1, 1, 0, 0], [0, 1, 1, 0, 1], [0, 1, 1, 1, 1], [1, 0, 0, 1, 0], [1, 0, 0, 1, 1], [1, 0, 1, 0, 0], [1, 0, 1, 1, 1], [1, 1, 0, 0, 0], [1, 1, 0, 1, 1], [1, 1, 1, 0, 0], [1, 1, 1, 1, 1]. The apparatus of claim 64, wherein The processing module is further configured to: map element 0 in the first sequence as [0, 1], and map element 1 in the first sequence as [1, 0]; or map element 1 in the first sequence as [0, 1], and map element 0 in the first sequence as [1, 0]; and k = 4, N = 15, and M = 4. When element x(i+4) in the first sequence satisfies: x(i+4) = (x(i+1) + x(i)) mod 2, the initial value is one of the following initial values: [0, 0, 1, 1], [0, 1, 0, 1], [1, 0, 0, 0], [1, 0, 0, 1], [1, 0, 1, 1], [1, 1, 0, 0], [1, 1, 0, 1], [1, 1, 1, 1]; Or, When element x(i+4) in the first sequence satisfies: x(i+4) = (x(i+3) + x(i)) mod 2, the initial value is one of the following initial values: [0, 0, 0, 1], [0, 0, 1, 0], [0, 0, 1, 1], [0, 1, 0, 0], [1, 0, 0, 0], [1, 1, 0, 0], [1, 1, 0, 1], [1, 1, 1, 1]. The apparatus of claim 64, wherein k = 4, N = 15, and M = 2; when the element x(i+4) in the first sequence satisfies: x(i+4)=(x(i+1)+x(i))mod2, the initial value is one of the initial values as follows: [0, 0, 1, 1], [0, 1, 0, 1], [0, 1, 1, 1], [1, 0, 1, 0], [1, 0, 1, 1], [1, 1, 0, 1], [1, 1, 1, 0], [1, 1, 1, 1]; Or, when the element x(i+4) in the first sequence satisfies: x(i+4)=(x(i+3)+x(i))mod2, the initial value is one of the initial values as follows: [0, 0, 0, 1], [0, 0, 1, 1], [0, 1, 0, 1], [1, 1, 1, 1], [1, 0, 0, 0], [1, 0, 1, 1], [1, 1, 1, 0], [1, 1, 1, 1]. The apparatus of claim 64, wherein The processing module is further configured to: map the element 0 in the first sequence as [0, 1], and map the element 1 in the first sequence as [1, 0]; or map the element 1 in the first sequence as [0, 1], and map the element 0 in the first sequence as [1, 0]; and k=4, N=15, M=2. when the element x(i+4) in the first sequence satisfies: x(i+4)=(x(i+1)+x(i))mod2, the initial value is one of the initial values as follows: [0, 0, 0, 1], [0, 0, 1, 0], [0, 1, 0, 0], [0, 1, 1, 0], [1, 0, 0, 1], [1, 0, 1, 1], [1, 1, 0, 1], [1, 1, 1, 1]; Or, when the element x(i+4) in the first sequence satisfies: x(i+4)=(x(i+3)+x(i))mod2, the initial value is one of the initial values as follows: [0, 0, 0, 1], [0, 0, 1, 0], [0, 0, 1, 1], [0, 1, 0, 0], [1, 1, 0, 0], [1, 1, 0, 1], [1, 1, 1, 0], [1, 1, 1, 1]. The apparatus of any one of claims 80-89, wherein The first sequence is related to a first cell identifier, and / or a cyclic shift of the first sequence is related to a first cell identifier. A communication device, characterized by Comprise: a transceiver module, configured to receive a low-power synchronization signal; a processing module, configured to process the low-power synchronization signal based on a first sequence, the first sequence being related to one or more of: a number of time units occupied by the first sequence, a number of bits M carried by each time unit, a subcarrier spacing, or a type of cyclic prefix CP. The apparatus of claim 91, wherein The first sequence LP_SS satisfies: LP_SS=(x0+x1)mod 2, wherein x0 is a second sequence, x1 is a third sequence, mod is a modulo operation, lengths of the second sequence and the third sequence are N, N = 2 k -1, k is a positive integer; and the second sequence is related to one or more of: a number of time units occupied by the second sequence, a number of bits M carried by each time unit, a subcarrier spacing, or a type of CP; The third sequence is associated with one or more of: a number of time units occupied by the third sequence, a number of bits M carried per time unit, a subcarrier spacing, or a type of CP. The apparatus of claim 91, wherein The first sequence LP_SS(n) satisfies: LP_SS(n) = [x0(n) + x1((n + m0) mod N)] mod 2 wherein x0(n) is a second sequence, x1(n) is a third sequence, m0 is a cyclic shift, n is an integer greater than or equal to 0 and less than N, N is a length of the second sequence and the third sequence, N=2 k -1, k is a positive integer, and mod is a modulo operation. The apparatus of claim 91, wherein The first sequence is associated with one or more of: a number of time units occupied by the first sequence, a number of bits M carried per time unit, a subcarrier spacing, or a type of CP, including: An initial value of the first sequence is associated with one or more of: a number of time units occupied by the first sequence, a number of bits M carried per time unit, a subcarrier spacing, or a type of CP. The apparatus of claim 92 or 93, wherein k = 7, N = 127, M = 8; The element x0(i+7) in the second sequence satisfies: x0(i+7) = (x0(i+1) + x0(i)) mod 2, and the element x1(i+7) in the third sequence satisfies: x1(i+7) = (x1(i+3) + x1(i)) mod 2; or, The element x0(i+7) in the second sequence satisfies: x0(i+7) = (x0(i+1) + x0(i)) mod 2, and the element x1(i+7) in the third sequence satisfies: x1(i+7) = (x1(i+4) + x1(i)) mod 2. The apparatus of claim 95, wherein When the element x0(i+7) in the second sequence satisfies: x0(i+7) = (x0(i+1) + x0(i)) mod 2, and the element x1(i+7) in the third sequence satisfies: x1(i+7) = (x1(i+3) + x1(i)) mod 2, the m0 belongs to a first set, the first set including one or more of the following cyclic shifts: 3, 912, 15, 19, 31, 35, 46, 48, 57, 60, 61, 62, 64, 65, 71, 82, 87, 92, 94, 99, 101, 107, 108, 113, 114, 117, 120, 121, 122, 123, 124. The apparatus of claim 96, wherein When the element x0(i+7) in the second sequence satisfies: x0(i+7) = (x0(i+1) + x0(i)) mod 2, and the element x1(i+7) in the third sequence satisfies: x1(i+7) = (x1(i+4) + x1(i)) mod 2, the m0 belongs to a second set, the second set including one or more of the following cyclic shifts: 24, 29, 34, 36, 39, 46, 47, 50, 53, 58, 61, 62, 65, 66, 78, 82, 84, 85, 86, 96, 100, 105, 106, 109, 111, 112, 116, 117, 120, 123, 125, 126. The apparatus of claim 92 or 93, wherein k = 6, N = 63, M = 8 or M = 4; An element x0(i+6) in the second sequence satisfies: x0(i+6)=(x0(i+1)+x0(i))mod 2, and an element x1(i+6) in the third sequence satisfies: x1(i+6)=(x1(i+5)+x1(i))mod 2. The apparatus of claim 98, wherein When M=8, the m0 belongs to a third set, and the third set includes one or more cyclic shifts of: 2, 4, 5, 8, 9, 10, 11, 12, 13, 14, 16, 18, 19, 21, 22, 23, 27, 28, 33, 39, 40, 43, 45, 49, 50, 51, 52, 55, 57, 58, 60, 61. The apparatus of claim 98, wherein When M=4, the m0 belongs to a fourth set, and the fourth set includes one or more cyclic shifts of: 2, 4, 5, 9, 13, 14, 16, 18, 19, 22, 23, 25, 27, 28, 30, 31, 33, 34, 39, 40, 41, 43, 45, 49, 50, 51, 52, 53, 55, 57, 58, 60. The apparatus of claim 98, wherein The processing module is further configured to: map an element 0 in the first sequence as [0, 1], and map an element 1 in the first sequence as [1, 0]; or map an element 1 in the first sequence as [0, 1], and map an element 0 in the first sequence as [1, 0]; When M=8, the m0 belongs to a fifth set, and the fifth set includes one or more cyclic shifts of: 1, 3, 6, 7, 8, 10, 12, 13, 15, 20, 21, 24, 26, 31, 32, 35, 36, 37, 41, 42, 43, 44, 47, 50, 53, 54, 56, 57, 59, 61, 62, 63. The apparatus of claim 92 or 93, wherein k=5, N=31, M=8, M=4, or M=2; An element x0(i+5) in the second sequence satisfies: x0(i+5)=(x0(i+2)+x0(i))mod 2, and an element x1(i+5) in the third sequence satisfies: x1(i+5)=(x1(i+3)+x1(i+2)+x1(i+1)+x1(i))mod 2; or, An element x0(i+5) in the second sequence satisfies: x0(i+5)=(x0(i+2)+x0(i))mod 2, and an element x1(i+5) in the third sequence satisfies: x1(i+5)=(x1(i+4)+x1(i+2)+x1(i+1)+x1(i))mod 2. The apparatus of claim 102, wherein When an element x0(i+5) in the second sequence satisfies: x0(i+5)=(x0(i+2)+x0(i))mod 2, and an element x1(i+5) in the third sequence satisfies: x1(i+5)=(x1(i+3)+x1(i+2)+x1(i+1)+x1(i))mod 2, the m0 belongs to a sixth set, and the sixth set includes one or more cyclic shifts of: 2, 5, 7, 9, 10, 12, 13, 16, 21, 23, 24, 25, 26, 27, 29, 30, 31. The apparatus of claim 102, wherein The processing module is further configured to map element 0 in the first sequence as [0, 1] and element 1 in the first sequence as [1, 0], or map element 1 in the first sequence as [0, 1] and element 0 in the first sequence as [1, 0]. When M = 8, the m0 belongs to a seventh set, and the seventh set includes one or more cyclic shifts as follows: 1, 2, 3, 8, 10, 11, 13, 14, 15, 18, 19, 22, 27, 28, 29, 31; or, When M = 4, the m0 belongs to an eighth set, and the eighth set includes one or more cyclic shifts as follows: 1, 2, 3, 4, 6, 8, 11, 13, 14, 15, 18, 19, 22, 28, 29, 31. The apparatus of claim 102, wherein When the element x0(i+5) in the second sequence satisfies x0(i+5) = (x0(i+2) + x0(i)) mod 2, and the element x1(i+5) in the third sequence satisfies x1(i+5) = (x1(i+4) + x1(i+2) + x1(i+1) + x1(i)) mod 2, the m0 belongs to a ninth set, and the ninth set includes one or more cyclic shifts as follows: 1, 2, 3, 5, 6, 8, 9, 11, 12, 15, 16, 20, 21, 23, 28, 31; or, 1, 2, 3, 5, 6, 8, 9, 11, 12, 13, 15, 16, 20, 21, 23, 28. The apparatus of claim 102, wherein The processing module is further configured to map element 0 in the first sequence as [0, 1] and element 1 in the first sequence as [1, 0], or map element 1 in the first sequence as [0, 1] and element 0 in the first sequence as [1, 0]. When M = 8, the m0 belongs to a tenth set, and the tenth set includes one or more cyclic shifts as follows: 4, 7, 10, 11, 13, 14, 18, 19, 20, 22, 24, 25, 27, 29, 30, 31; or, When M = 4, the m0 belongs to an eleventh set, and the eleventh set includes one or more cyclic shifts as follows: 2, 4, 7, 8, 10, 14, 18, 19, 20, 22, 24, 25, 27, 29, 30, 31. The apparatus of claim 92 or 93, wherein k = 4, N = 15, M = 4 or M = 2; The element x0(i+4) in the second sequence satisfies x0(i+4) = (x0(i+1) + x0(i)) mod 2, and the element x1(i+4) in the third sequence satisfies x1(i+4) = (x1(i+3) + x1(i)) mod 2. The apparatus of claim 107, wherein The m0 belongs to a twelfth set, and the twelfth set includes one or more cyclic shifts as follows: 2, 5, 7, 8, 9, 11, 12, and 13. The apparatus of claim 107, wherein The processing module is further configured to map element 0 in the first sequence as [0, 1] and element 1 in the first sequence as [1, 0], or map element 1 in the first sequence as [0, 1] and element 0 in the first sequence as [1, 0]. The m0 belongs to a thirteenth set, and the thirteenth set includes one or more cyclic shifts as follows: 1, 3, 4, 6, 8, 12, 14, and 15. The apparatus of any one of claims 93, 96-109, wherein The m0 is determined according to a first cell identifier. The apparatus of claim 95, wherein k = 7, N = 127, and M = 8. When element x(i+7) in the first sequence satisfies x(i+7) = (x(i+1) + x(i)) mod 2, the initial value is one of the initial values as follows: [0, 0, 0, 0, 0, 0, 1], [0, 0, 0, 0, 0, 1, 1], [0, 0, 1, 0, 0, 0, 0], [0, 0, 1, 1, 1, 1, 1], [0, 1, 0, 0, 0, 0, 0], [0, 1, 1, 0, 0, 1, 1], [0, 1, 1, 0, 1, 1, 0], [0, 1, 1, 1, 0, 1, 1], [0, 1, 1, 1, 1, 1, 1], [1, 0, 1, 0, 1, 0, 1], [1, 1, 0, 0, 1, 0, 0], [1, 1, 0, 1, 0, 1, 1], [1, 1, 0, 1, 1, 1, 1], [1, 1, 1, 0, 1, 1, 0], [1, 1, 1, 1, 1, 0, 1], [1, 1, 1, 1, 1, 1, 1]; or, When element x(i+7) in the first sequence satisfies x(i+7) = (x(i+4) + x(i)) mod 2, the initial value is one of the initial values as follows: [0, 0, 0, 0, 0, 0, 1], [0, 0, 0, 0, 0, 1, 0], [0, 0, 0, 0, 1, 1, 1], [0, 0, 0, 1, 0, 1, 1], [0, 0, 0, 1, 1, 0, 0], [0, 0, 1, 0, 0, 0, 0], [0, 1, 0, 0, 0, 1, 0], [0, 1, 0, 0, 1, 1, 0], [0, 1, 0, 1, 1, 0, 1], [0, 1, 0, 1, 1, 1, 0], [0, 1, 1, 0, 1, 1, 0], [1, 0, 0, 1, 0, 0, 1], [1, 1, 0, 0, 0, 0, 0]. The apparatus of claim 95, wherein Element x(i+6) in the first sequence satisfies x(i+6) = (x(i+1) + x(i)) mod 2. When k=6, N=63, M=8, the initial value is one of the following initial values: [0, 0, 0, 0, 1, 0], [0, 0, 0, 0, 1, 1], [0, 0, 1, 0, 0, 0], [0, 0, 1, 1, 1, 1], [0, 1, 0, 1, 0, 1], [0, 1, 1, 0, 0, 1], [0, 1, 1, 0, 1, 1], [1, 0, 0, 0, 0, 0], [1, 0, 0, 1, 1, 0], [1, 0, 1, 1, 1, 0], [1, 0, 1, 1, 1, 1], [1, 1, 0, 0, 1, 1], [1, 1, 0, 1, 0, 0], [1, 1, 1, 0, 1, 1], [1, 1, 1, 1, 0, 1], [1, 1, 1, 1, 1, 1]; or, When k=6, N=63, M=4, the initial value is one of the following initial values: [0, 0, 0, 0, 1, 0], [0, 0, 0, 0, 1, 1], [0, 0, 1, 0, 0, 0], [0, 0, 1, 1, 1, 1], [0, 1, 0, 1, 0, 1], [0, 1, 1, 0, 0, 1], [0, 1, 1, 0, 1, 1], [1, 0, 0, 0, 0, 0], [1, 0, 0, 1, 1, 0], [1, 1, 0, 0, 0, 0], [1, 1, 0, 0, 1, 1], [1, 1, 0, 1, 0, 1], [1, 1, 0, 1, 1, 1], [1, 1, 1, 1, 0, 1], [1, 1, 1, 1, 0, 1], [1, 1, 1, 1, 1, 1]. The apparatus of claim 95, wherein The element x(i+6) in the first sequence satisfies: x(i+6)=(x(i+5)+x(i))mod2; When k=6, N=63, M=8, the initial value is one of the following initial values: [0, 0, 0, 1, 0, 0], [0, 0, 0, 1, 1, 0], [0, 0, 0, 1, 1, 0], [0, 0, 1, 0, 0, 1], [0, 0, 1, 1, 0, 1], [0, 1, 0, 0, 0, 1], [0, 1, 0, 1, 1, 1], [0, 1, 1, 0, 0, 1], [0, 1, 1, 0, 1, 1], [1, 0, 0, 0, 0, 0], [1, 0, 0, 0, 0, 1], [1, 0, 0, 0, 1, 1], [1, 0, 1, 1, 0, 1], [1, 1, 0, 0, 0, 0], [1, 1, 0, 0, 1, 0], [1, 1, 0, 1, 1, 1]; or, When k=6, N=63, and M=4, the initial value is one of the following initial values: [0, 0, 0, 0, 1, 0], [0, 0, 0, 0, 1, 1], [0, 0, 0, 1, 0, 0], [0, 0, 0, 1, 1, 0], [0, 0, 0, 1, 1, 1], [0, 0, 1, 0, 0, 0], [0, 0, 1, 1, 0, 1], [0, 1, 0, 0, 0, 1], [0, 1, 1, 0, 0, 1], [0, 1, 1, 0, 1, 1], [0, 1, 1, 1, 0, 0], [1, 0, 0, 0, 0, 0], [1, 0, 0, 0, 0, 1], [1, 0, 0, 0, 1, 1], [1, 1, 0, 1, 1, 0], [1, 1, 1, 0, 0, 0]. The apparatus of claim 95, wherein The processing module is further configured to map element 0 in the first sequence as [0, 1], and map element 1 in the first sequence as [1, 0], or map element 1 in the first sequence as [0, 1], and map element 0 in the first sequence as [1, 0], and element x(i+6) in the first sequence satisfies: x(i+6)=(x(i+1)+x(i))mod2. When k=6, N=63, and M=8, the initial value is one of the following initial values: [0, 0, 0, 0, 1, 0], [0, 0, 0, 1, 0, 1], [0, 0, 1, 0, 0, 1], [0, 0, 1, 1, 0, 0], [0, 0, 1, 1, 1, 1], [0, 1, 0, 1, 0, 1], [0, 1, 1, 0, 0, 1], [0, 1, 1, 0, 1, 1], [0, 1, 1, 1, 0, 0], [1, 0, 0, 0, 0, 0], [1, 0, 0, 1, 0, 1], [1, 0, 1, 1, 0, 1], [1, 1, 0, 1, 0, 0], [1, 1, 0, 1, 0, 1], [1, 1, 1, 0, 1, 1], [1, 1, 1, 1, 0, 1]; or, When k=6, N=63, and M=4, the initial value is one of the following initial values: [0, 0, 0, 1, 0, 1], [0, 0, 0, 1, 1, 1], [0, 0, 1, 0, 0, 1], [0, 0, 1, 0, 1, 0], [0, 0, 1, 1, 1, 0], [0, 1, 0, 0, 0, 0], [0, 1, 0, 0, 0, 1], [0, 1, 0, 1, 1, 1], [0, 1, 1, 0, 0, 0], [0, 1, 1, 0, 1, 1], [0, 1, 1, 1, 1, 1], [1, 0, 0, 0, 0, 0], [1, 0, 0, 0, 0, 1], [1, 0, 0, 0, 1, 1], [1, 0, 1, 1, 0, 1], [1, 1, 1, 1, 0, 1]. The apparatus of claim 95, wherein Element x(i+5) in the first sequence satisfies: x(i+5)=(x(i+2)+x(i))mod2. When k=5, N=31, and M=4, the initial value is one of the following initial values: [0, 0, 0, 0, 1], [0, 0, 0, 1, 1], [0, 0, 1, 1, 1], [0, 1, 0, 0, 0], [0, 1, 0, 1, 1], [0, 1, 1, 0, 0], [0, 1, 1, 0, 1], [0, 1, 1, 1, 1], [1, 0, 0, 1, 1], [1, 0, 1, 0, 0], [1, 1, 0, 0, 0], [1, 1, 0, 0, 1], [1, 1, 1, 0, 0], [1, 1, 1, 1, 0], [1, 1, 1, 1, 1]; or, When k=5, N=31, and M=2, the initial value is one of the following initial values: [0, 0, 0, 1, 1], [0, 0, 1, 0, 0], [0, 0, 1, 1, 0], [0, 0, 1, 1, 1], [0, 1, 0, 0, 1], [0, 1, 1, 0, 1], [0, 1, 1, 1, 1], [1, 0, 0, 0, 1], [1, 0, 0, 1, 0], [1, 0, 1, 0, 0], [1, 1, 0, 0, 1], [1, 1, 0, 1, 1], [1, 1, 1, 0, 0], [1, 1, 1, 1, 0]. The apparatus of claim 95, wherein The processing module is further configured to: map element 0 in the first sequence as [0, 1], and map element 1 in the first sequence as [1, 0]; or map element 1 in the first sequence as [0, 1], and map element 0 in the first sequence as [1, 0]; and element x(i+5) in the first sequence satisfies: x(i+5)=(x(i+2)+x(i))mod2. When k=5, N=31, and M=8, the initial value is one of the following initial values: [0, 0, 0, 0, 1], [0, 0, 1, 0, 0], [0, 0, 1, 0, 1], [0, 0, 1, 1, 1], [0, 1, 0, 0, 0], [0, 1, 0, 1, 0], [0, 1, 1, 0, 0], [0, 1, 1, 0, 1], [0, 1, 1, 1, 0], [1, 0, 0, 1, 0], [1, 0, 0, 1, 1], [1, 0, 1, 0, 0], [1, 0, 1, 1, 1], [1, 1, 0, 1, 1], [1, 1, 1, 0, 0], [1, 1, 1, 1, 1]; or, When k=5, N=31, M=4, the initial value is one of the following initial values: [0, 0, 0, 0, 1], [0, 0, 0, 1, 1], [0, 0, 1, 0, 1], [0, 1, 0, 0, 0], [0, 1, 0, 0, 1], [0, 1, 1, 0, 0], [0, 1, 1, 0, 1], [0, 1, 1, 1, 1], [1, 0, 0, 1, 0], [1, 0, 0, 1, 1], [1, 0, 1, 0, 0], [1, 0, 1, 1, 1], [1, 1, 0, 0, 0], [1, 1, 0, 1, 1], [1, 1, 1, 0, 0], [1, 1, 1, 1, 1]. The apparatus of claim 95, wherein The processing module is further configured to: map element 0 in the first sequence as [0, 1], and map element 1 in the first sequence as [1, 0]; or map element 1 in the first sequence as [0, 1], and map element 0 in the first sequence as [1, 0]; and k=4, N=15, M=4; When element x(i+4) in the first sequence satisfies: x(i+4)=(x(i+1)+x(i))mod2, the initial value is one of the following initial values: [0, 0, 1, 1], [0, 1, 0, 1], [1, 0, 0, 0], [1, 0, 0, 1], [1, 0, 1, 1], [1, 1, 0, 0], [1, 1, 0, 1], [1, 1, 1, 1]; Or, When element x(i+4) in the first sequence satisfies: x(i+4)=(x(i+3)+x(i))mod2, the initial value is one of the following initial values: [0, 0, 0, 1], [0, 0, 1, 1], [0, 1, 0, 1], [1, 1, 1, 1], [1, 0, 0, 0], [1, 0, 1, 1], [1, 1, 1, 0], [1, 1, 1, 1]. The apparatus of claim 95, wherein k=4, N=15, M=2; When element x(i+4) in the first sequence satisfies: x(i+4)=(x(i+1)+x(i))mod2, the initial value is one of the following initial values: [0, 0, 1, 1], [0, 1, 0, 1], [0, 1, 1, 1], [1, 0, 1, 0], [1, 0, 1, 1], [1, 1, 0, 1], [1, 1, 1, 0], [1, 1, 1, 1]; Or, When element x(i+4) in the first sequence satisfies: x(i+4)=(x(i+3)+x(i))mod2, the initial value is one of the following initial values: [0, 0, 0, 1], [0, 0, 1, 1], [0, 1, 0, 1], [1, 1, 1, 1], [1, 0, 0, 0], [1, 0, 1, 1], [1, 1, 1, 0], [1, 1, 1, 1]. The apparatus of claim 95, wherein The processing module is further configured to map element 0 in the first sequence as [0, 1], and map element 1 in the first sequence as [1, 0]; or map element 1 in the first sequence as [0, 1], and map element 0 in the first sequence as [1, 0]; and k = 4, N = 15, and M = 2. When element x(i+4) in the first sequence satisfies x(i+4) = (x(i+1) + x(i)) mod 2, the initial value is one of the following initial values: [0, 0, 0, 1], [0, 0, 1, 0], [0, 1, 0, 0], [0, 1, 1, 0], [1, 0, 0, 1], [1, 0, 1, 1], [1, 1, 0, 1], [1, 1, 1, 1]. Or, When element x(i+4) in the first sequence satisfies x(i+4) = (x(i+3) + x(i)) mod 2, the initial value is one of the following initial values: [0, 0, 0, 1], [0, 0, 1, 0], [0, 0, 1, 1], [0, 1, 0, 0], [1, 1, 0, 0], [1, 1, 0, 1], [1, 1, 1, 0], [1, 1, 1, 1]. The apparatus of any one of claims 111-119, wherein The first sequence is related to a first cell identifier, and / or a cyclic shift of the first sequence is related to a first cell identifier. A communication device, characterized by The communication device includes at least one processor configured to cause the communication device to perform the method of any one of claims 1-30, or to cause the communication device to perform the method of any one of claims 31-60. A computer-readable storage medium, characterized by, The computer-readable storage medium is configured to store a computer program that, when executed on a computer, causes the computer to perform the method of any one of claims 1-30, or causes the computer to perform the method of any one of claims 31-60. A computer program product, characterized by The computer program product includes a computer program that, when executed on a computer, causes the computer to perform the method of any one of claims 1-30, or causes the computer to perform the method of any one of claims 31-60. A chip characterized by The computer program product includes a computer program that, when executed on a computer, causes the computer to perform the method of any one of claims 1-30, or causes the computer to perform the method of any one of claims 31-60. The computer program product includes a computer program that, when executed on a computer, causes the computer to perform the method of any one of claims 1-30, or causes the computer to perform the method of any one of claims 31-60.

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