LDPC code-based communication method and communication apparatus

Abstract

A communication method and a communication apparatus. In the method, a device may perform encoding or decoding on the basis of an LDPC matrix, wherein the LDPC matrix is determined on the basis of an LDPC base matrix, Zc, a, and b; a first region of the base matrix comprises L types of elements, wherein 2≤L≤2a*b, and a and b are not both 1 at the same time; Zc, a, and b are used for lifting each element in the first region into an (a*Zc)*(b*Zc) matrix, wherein the matrix comprises (a*b)(Zc*Zc) matrices, and each Zc*Zc matrix is an all-0 matrix or a cyclic shift matrix; first sub-matrices corresponding to the L types of elements are all different; and each first sub-matrix is a matrix formed by replacing, with an identity matrix of Zc*Zc, a cyclic shift matrix within the (a*b)(Zc*Zc) matrices of the matrix lifted by a corresponding element. The method can improve the decoding performance of LDPC codes.

Description

Communication method and communication apparatus based on LDPC code

[0001] The present application claims priority to the Chinese patent application No. 202411071161.X, filed on August 5, 2024, and entitled “Communication method and communication apparatus based on LDPC code”, the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the field of coding, and more particularly, to a communication method and communication apparatus based on LDPC code. BACKGROUND

[0003] In the field of channel coding, low-density parity check (LDPC) code is one of the most mature and widely used channel coding schemes. Quasi-cyclic low density parity check (QC-LDPC) code is a structured LDPC code. Due to the unique structure of its check matrix, it can be implemented using a simple feedback shift register during encoding, which reduces the encoding complexity of LDPC code.

[0004] Currently, the decoding threshold and decoding complexity of QC-LDPC code are mainly determined by the base graph (BG) (i.e., the base matrix). The degree distribution of the LDPC code supported by the small-scale base matrix is limited, and the decoding threshold cannot reach the optimal value. The performance of new radio (NR) LDPC is severely impaired at very high code rates. The degree distribution of the LDPC code is used to indicate the column weight distribution of the check matrix. In one possible implementation, the decoding threshold can be improved by expanding the base matrix. However, the large-scale base matrix has low parallelism and complex hardware implementation without good orthogonality. SUMMARY

[0005] Embodiments of the present application provide a communication method and communication apparatus based on LDPC code, which helps to improve the decoding performance of LDPC code.

[0006] In a first aspect, a communication method based on LDPC code is provided. The method can be performed by a sending device. In the absence of special description, the “sending device” in the present application can refer to the sending device itself (e.g., a network device, a terminal device), a component (e.g., a processor, a chip, or a chip system) in the sending device, or a logic module or software capable of realizing all or part of the functions of the sending device.

[0007] The method comprises: obtaining an information bit sequence; determining an LDPC matrix, the LDPC matrix being determined based on an LDPC base matrix, a lifting value Z c , a numerical value a and a numerical value b, wherein the first region of the base matrix comprises L elements, the L elements comprising 0 elements and L-1 non-0 elements, the L-1 non-0 elements being L-1 different integers in 1 to 2 a*b -1, L being an integer greater than or equal to 2 and less than or equal to 2 a*b , a and b are both positive integers and are not simultaneously 1, the first region being part or all of the region of the base matrix, the L first sub-matrices corresponding to the L elements all being different, the first sub-matrix of each element in the L elements comprising (a*b) (Zc*Zc) matrices, the Zc*Zc matrix being a full 0 matrix or a unit matrix, Zc, a and b being used to lift each element in the first region into an (a*Zc)*(b*Zc) matrix, the (a*Zc)*(b*Zc) matrix being determined based on the first sub-matrix corresponding to each element, the (a*Zc)*(b*Zc) matrix being obtained by cyclically shifting the unit matrix in the first sub-matrix, or the (a*Zc)*(b*Zc) matrix being a full 0 matrix; encoding the information bit sequence according to the LDPC matrix to obtain a codeword sequence; and outputting the codeword sequence.

[0008] It can be understood that if each Zc*Zc matrix in the (a*b) (Zc*Zc) matrices of the first sub-matrix of element #1 in the first region is a full 0 matrix, then the (a*Zc)*(b*Zc) matrix after lifting of element #1 is a full 0 matrix. If the (a*b) (Zc*Zc) matrices of the first sub-matrix corresponding to element #1 contain at least one Zc*Zc unit matrix, then the (a*Zc)*(b*Zc) matrix after lifting of element #1 can be regarded as a matrix obtained by keeping the full 0 matrix of Zc*Zc in the first sub-matrix unchanged and cyclically shifting the unit matrix of Zc*Zc in the first sub-matrix.

[0009] For example, the LDPC matrix can be an LDPC check matrix or an LDPC generator matrix. The LDPC check matrix or the LDPC generator matrix is a matrix obtained by lifting the elements in all regions of the base matrix based on the corresponding lifting manner, and the LDPC generator matrix and the LDPC check matrix correspond to each other.

[0010] The above technical solution can make the LDPC matrix obtained after lifting support a wider degree distribution, while maintaining orthogonality, and without the need to expand the size of the base matrix on the basis of optimizing the decoding threshold, thereby reducing the hardware implementation complexity.

[0011] In a second aspect, a communication method is provided, which can be performed by a receiving end device. In the present application, the "receiving end device" can refer to the receiving end device itself (e.g., a network device, a terminal device), a component (e.g., a processor, a chip, or a chip system) in the receiving end device, or a logic module or software capable of realizing all or part of the functions of the receiving end device.

[0012] The method comprises: obtaining a symbol sequence; determining an LDPC matrix, the LDPC matrix being determined based on an LDPC base matrix, a lifting value Z c , a numerical value a, and a numerical value b, wherein the first region of the base matrix comprises L elements, the L elements comprising a 0 element and L-1 non-0 elements, the L-1 non-0 elements being L-1 different integers in 1 to 2 a*b -1, L being an integer greater than or equal to 2 and less than or equal to 2 a*b a and b both being positive integers and not being 1 at the same time, the first region being part or all of the region of the base matrix, the L first sub-matrices corresponding to the L elements all being different, the first sub-matrix of each element in the L elements comprising (a*b) Zc*Zc matrices, the Zc*Zc matrix being a full 0 matrix or a unit matrix, Zc, a, and b being used to lift each element in the first region into an (a*Zc)*(b*Zc) matrix, the (a*Zc)*(b*Zc) matrix being determined based on the first sub-matrix corresponding to each element, the (a*Zc)*(b*Zc) matrix being obtained by cyclically shifting the unit matrix in the first sub-matrix, or the (a*Zc)*(b*Zc) matrix being a full 0 matrix; and decoding the symbol sequence according to the LDPC matrix to obtain an information bit sequence.

[0013] The beneficial effects of the second aspect are described in the first aspect, which will not be repeated here.

[0014] In some implementations of the first aspect or the second aspect, the LDPC matrix is determined by: replacing each element in the first region with an a*b matrix, any element in the a*b matrix being a 0 element or a 1 element, the a*b matrices corresponding to the L elements all being different; replacing the 0 elements in the a*b matrix corresponding to each element with a full 0 matrix of Zc*Zc, and replacing the 1 elements in the a*b matrix with a cyclic shift matrix of Zc*Zc to obtain the LDPC matrix.

[0015] In the above technical solution, a possible two-stage lifting method is provided, in which each element in the first region is first lifted into a row-a column-b matrix, and then each element in the row-a column-b matrix is further lifted based on the lifting value Zc. Although this solution is lifted in multiple stages, it is simple to implement in hardware and has high parallelism, which can reduce the computational complexity.

[0016] In some implementations of the first aspect or the second aspect, the LDPC matrix is determined by replacing each element in the first region with a (a*Zc)*(b*Zc) matrix corresponding to the element.

[0017] It can be understood that the lifting manner has the same lifting result as the two-stage lifting manner described above, that is, the LDPC matrix obtained after lifting is the same. The difference is that the first lifting manner is an indirect lifting manner, and the second lifting manner is a direct lifting manner.

[0018] In some implementations of the first aspect or the second aspect, the first region is a partial region of the base matrix, and the base matrix further includes a second region, the second region being a region of the base matrix other than the first region, and the elements in the second region being 0 elements or 1 elements. The LDPC matrix is determined by lifting the 0 elements in the second region into a full 0 matrix of Zc*Zc, and lifting the 1 elements in the second region into a cyclic shift matrix of Zc*Zc.

[0019] The above technical solution gives a possible specific lifting manner of the elements in the remaining region (i.e., the second region) of the base matrix when the first region is a partial region of the base matrix.

[0020] In some implementations of the first aspect or the second aspect, the first element corresponds to a*b translation values, the first element is a non-0 element in the first region, and the a*b translation values one-to-one correspond to (a*b) (Zc*Zc) matrices of the first sub-matrix of the first element, wherein the translation value corresponding to the identity matrix of Zc*Zc in the (a*b) (Zc*Zc) matrices is a natural number, and the translation value corresponding to the full 0 matrix of Zc*Zc in the (a*b) (Zc*Zc) matrices is a first character, and the first character is not equal to the natural number.

[0021] In the above technical solution, the same number of translation values can be configured for all non-0 elements in the first region, which is simple and easy to implement, the hardware design is relatively uniform, the parallel degree resources need to be allocated are consistent, and there is no parallel degree waste.

[0022] For example, the a*b translation values corresponding to the first element one-to-one correspond to the (a*b) (Zc*Zc) matrices of the first sub-matrix of the first element in the order of row first and column second, or the a*b translation values corresponding to the first element one-to-one correspond to the (a*b) (Zc*Zc) matrices of the first sub-matrix of the first element in the order of column first and row second.

[0023] In some implementations of the first aspect or the second aspect, the first element corresponds to M translation values, the first element is a non-zero element in the first region, and the M translation values correspond one-to-one to M unit matrices of Zc*Zc in the first sub-matrix of the first element, where each of the M translation values is a natural number, M is greater than or equal to 1 and less than or equal to a*b.

[0024] In the technical solution, different numbers of translation values can be configured based on the type of the non-zero element in the first region, flexible degree distribution is supported, and coding performance is better.

[0025] In some implementations of the first aspect or the second aspect, the M translation values corresponding to the first element correspond one-to-one to the M unit matrices of Zc*Zc in the first sub-matrix of the first element in the order of row first and column second, or the M translation values corresponding to the first element correspond one-to-one to the M unit matrices of Zc*Zc in the first sub-matrix of the first element in the order of column first and row second.

[0026] In some implementations of the first aspect or the second aspect, the first element corresponds to t translation values, the first element is a non-zero element in the first region, and a translation value corresponding to a (Zc*Zc) unit matrix in the (a*b) (Zc*Zc) matrices of the first sub-matrix of the first element is determined based on the t translation values corresponding to the first element and the element type of the first element, t is an integer greater than or equal to 0 and less than Q, and Q is the number of (Zc*Zc) unit matrices contained in the (a*b) (Zc*Zc) matrices of the first sub-matrix of the first element.

[0027] In the technical solution, the translation values of the first element can be flexibly configured, hardware implementation is simple, and coding performance is good.

[0028] In some implementations of the first aspect or the second aspect, the base matrix is composed of five parts, the five parts include an A part, a B part, a C part, a D part, and an E part, and the base matrix includes X rows and Y columns, where the A part is a region composed of the 1st-x1st rows and the 1st-y1st columns of the base matrix, the B part is a region composed of the 1st-x1st rows and the y1+1st-y2nd columns of the base matrix, the matrix corresponding to the B part is a square matrix, the C part is a region composed of the 1st-x1st rows and the y2+1st-Yth columns of the base matrix, the matrix corresponding to the C part is a full zero matrix, the D part is a region composed of the x1+1st-Xth rows and the 1st-y2nd columns of the base matrix, the E part is a region composed of the x1+1st-Xth rows and the y2+1st-Yth columns of the base matrix, and the matrix corresponding to the E part is a unit matrix.

[0029] The characteristics of the regions composed of the rows and columns of the base matrix are described above, and the specific positions of the first region and the second region are specifically illustrated based on the described row and column characteristics of the base matrix. Among them, the first region uses the lifting manner proposed in the application, and the second region uses the lifting manner corresponding to the second region described above.

[0030] Example one, the first region is a region composed of the 1st to Xth rows and the 1st to y2th columns of the base matrix (i.e., the A+B+D part of the base matrix), and the second region is all the regions remaining in the base matrix except the first region (i.e., the C+E part of the base matrix).

[0031] The advantage of this example is that the E part supports hybrid automatic repeat request (HARQ) and has a lower triangular structure, and the diagonal elements are definitely non-zero. Using the lifting manner proposed in the application, the first lifting matrix corresponding to the diagonal elements is a non-all-zero and non-all-one matrix, which will cause some additional complexity, so the E part can be lifted based on the lifting manner corresponding to the second region.

[0032] Example two, the first region is a region composed of the 1st to x1th rows and the 1st to y1th columns of the base matrix and a region composed of the x1+1th to Xth rows and the 1st to y2th columns of the base matrix (i.e., the A+D part), and the second region is all the regions remaining in the base matrix except the first region (i.e., the B+C+E part of the base matrix).

[0033] The advantage of this example is that the B part can have a more flexible coding structure, simple hardware coding, and optimization of the trap set in this region, and the A+D region can completely use the lifting manner proposed in the application.

[0034] Example three, the first region is a region composed of all the rows of the base matrix and all the columns of the base matrix except at least one column in the y1+1th to y2th columns (i.e., the core check column) and the y2+1th to Yth columns (i.e., the extended check column), and the second region is all the regions remaining in the base matrix except the first region.

[0035] The advantage of this example is that it can achieve the property of easy coding with as few mixed structures as possible, and the hardware utilization rate is high.

[0036] Optionally, the at least one column in the y1+1th to y2th columns is all the columns in the y1+1th to y2th columns.

[0037] Optionally, at least one column in the y1+1~y2 columns includes the first column, wherein the first column has an odd column weight greater than 1 in a region formed by the 1~x1 rows and the y1+1~y2 columns of the base matrix (i.e., the B part of the base matrix). It is emphasized that the column weight of the first column in the B part is the number of non-zero elements in all the elements of the first column in the B part.

[0038] In some implementations of the first aspect or the second aspect, the first region is a region formed by the 1~x rows and the 1~y2 columns of the base matrix, and the first region includes a second element, wherein the first element has a first sub-matrix in which each Zc*Zc matrix is a full zero matrix, and the second element has a first sub-matrix in which each Zc*Zc matrix is an identity matrix.

[0039] In some implementations of the first aspect or the second aspect, the first region corresponds to at least one punctured column, and each punctured column of the at least one punctured column includes at least one second element. More specifically, at least one row of a region formed by the 1~x1 rows and the at least one punctured column of the base matrix includes the second element.

[0040] The advantage of the above design rule is that, since the structure of the element x is compatible with the puncturing structure (if each row contains 0 or more than one puncturing node, the LDPC cannot be decoded), at least one element x is required when the core matrix works at a code rate.

[0041] In some implementations of the first aspect or the second aspect, each row of the A part includes at most one element x.

[0042] The advantage of this design rule is that the hardware utilization rate is high, and arbitrary row weight distribution can be supported, and the decoding performance is good.

[0043] In some implementations of the first aspect or the second aspect, the A part does not include the element x.

[0044] The advantage of this design rule is that the hardware utilization rate is the highest, and the decoding architecture design is simpler.

[0045] In some implementations of the first aspect or the second aspect, the B part (the B part is an m*m matrix) includes at most m x, and each row of the B part includes at most two x.

[0046] The advantage of this design rule is that the property of easy encoding can be achieved with as few mixed structures as possible, and the hardware utilization rate is high.

[0047] In some implementations of the first aspect or the second aspect, the number of elements x included in a corresponding row in the D part decreases as the row number of the extended row increases (i.e., as the code rate decreases).

[0048] The advantage of this design rule is that the degree distribution design space is larger as the code rate decreases, thus resulting in higher hardware utilization.

[0049] In some implementations of the first aspect or the second aspect, the number of second elements included in each row in the D part is less than a corresponding threshold of each row, the corresponding threshold of each row being determined based on at least one of the following: the corresponding code rate of each row, the corresponding row weight of each row in the base matrix, the corresponding row weight of each row in the base matrix without including the puncturing column, and the connection structure of the second elements included in each row and the puncturing column of the base matrix.

[0050] In some implementations of the first aspect or the second aspect, all rows in the D part correspond to S row sets, wherein each row set in the S row sets includes at least one row, the at least one row is a row with a consecutive row number, the number of second elements included in all rows in each row set is the same, and the number of second elements included in rows in a first row set in the S row sets decreases as the row number of a first row in the first row set increases, the first row being a row with the smallest row number in the first row set, and S is an integer greater than 1.

[0051] The advantage of this design rule is that the degree distribution design space is larger, thus resulting in higher hardware utilization.

[0052] In some implementations of the first aspect or the second aspect, L = 2, and the L types of elements include a first type of element and a second type of element, wherein each Zc*Zc matrix in the first sub-matrix of the first type of element is a full zero matrix, and each Zc*Zc matrix in the first sub-matrix of the second type of element is an identity matrix.

[0053] In a third aspect, a communication apparatus is provided, which is configured to execute the method in any of the above aspects or implementations thereof. Specifically, the apparatus can include units and / or modules for performing the method in any of the above aspects or implementations thereof, such as a processing unit and / or a transceiving unit.

[0054] In an implementation, the apparatus is a transmitting device or a receiving device. When the apparatus is a transmitting device or a receiving device, the transceiving unit can be a transceiver, or an input / output interface, or a communication interface; and the processing unit can be at least one processor. Optionally, the transceiver is a transceiving circuit. Optionally, the input / output interface is an input / output circuit.

[0055] In another implementation, the apparatus is a chip, chip system or circuit for a transmitting end device or a receiving end device. When the apparatus is a chip, chip system or circuit for a transmitting end device or a receiving end device, the transceiving unit can be an input / output interface, interface circuit, output circuit, input circuit, pin or related circuit on the chip, chip system or circuit; and the processing unit can be at least one processor, processing circuit or logic circuit.

[0056] In a fourth aspect, a communication apparatus is provided, which comprises a memory configured to store a computer program or instructions; and at least one processor configured to execute the computer program or instructions stored in the memory to perform the method in any one of the aspects or the implementation manners thereof.

[0057] In an implementation, the apparatus is a transmitting end device or a receiving end device.

[0058] In another implementation, the apparatus is a chip, chip system or circuit for a transmitting end device or a receiving end device.

[0059] In a fifth aspect, a communication apparatus is provided, which comprises at least one processor and a communication interface, the at least one processor configured to acquire, through the communication interface, a computer program or instructions stored in a memory, to perform the method in any one of the aspects or the implementation manners thereof. The communication interface can be implemented by hardware or software.

[0060] In an implementation, the apparatus further comprises the memory.

[0061] In a sixth aspect, a processor is provided, which is configured to perform the method in the aspects.

[0062] For the transmitting and acquiring / receiving operations of the processor, if no special description is provided, or if it does not contradict with the actual role or inherent logic in the related description, it can be understood as the processor outputting and receiving, inputting and the like, or the transmitting and receiving operations performed by the radio frequency circuit and the antenna, which are not limited in the present application.

[0063] In a seventh aspect, a computer readable storage medium is provided, which stores program codes for execution by a device, and the program codes comprise codes for performing the method in any one of the aspects or the implementation manners thereof.

[0064] In an eighth aspect, a computer program product comprising instructions which, when the computer program product is executed on a computer, cause the computer to carry out the method in any one of the aspects or the implementation manners thereof.

[0065] In a ninth aspect, a chip is provided, which includes a processor and a communication interface. The processor reads instructions stored on a memory through the communication interface, and executes the method provided in any one of the aspects or the implementation manners thereof. The communication interface can be implemented by hardware or software.

[0066] Optionally, as an implementation manner, the chip further includes a memory, which stores a computer program or instructions. The processor is configured to execute the computer program or instructions stored on the memory, and when the computer program or instructions are executed, the processor is configured to execute the method provided in any one of the aspects or the implementation manners thereof.

[0067] When the method provided in the present application is executed by the chip, the present application does not limit the number of chips that implement the method of the present application, for example, the method can be executed by one chip, or two or more chips. When the number of chips that implement the method of the present application is two or more, the chips can be from the same manufacturer or different manufacturers.

[0068] In a tenth aspect, a computer program is provided, which, when executed on a computer, causes the method provided in any one of the aspects or the implementation manners thereof to be executed.

[0069] In an eleventh aspect, a communication system is provided, which includes at least one of the sending device or the receiving device described above. BRIEF DESCRIPTION OF DRAWINGS

[0070] FIG. 1 is a schematic diagram of a network architecture to which embodiments of the present application can be applied.

[0071] FIG. 2 is a schematic diagram of a check matrix H of an LDPC.

[0072] FIG. 3 is a Tanner graph of a check matrix H of an LDPC.

[0073] FIG. 4 is a schematic diagram of a structure of a check matrix.

[0074] FIG. 5 is a schematic diagram of an information transmission process.

[0075] FIG. 6 is a schematic flowchart of a communication method 600 based on an LDPC code provided in the present application.

[0076] FIGS. 7 to 9 are schematic diagrams of a translation value acquisition manner proposed in the present application.

[0077] FIG. 10 is a schematic block diagram of a communication apparatus 1000 provided in an embodiment of the present application.

[0078] FIG. 11 is a schematic block diagram of a communication apparatus 1100 provided in an embodiment of the present application. DETAILED DESCRIPTION

[0079] In order to facilitate the understanding of the embodiments of the present application, the following points are explained before the embodiments of the present application are introduced.

[0080] "Indicative of" or "indicate" can include both direct and indirect indication, or "indicative of" or "indicate" can explicitly and / or implicitly indicate. The first, second, etc. various numerical designations are only for the convenience of description and do not limit the scope of the embodiments of the present application, for example, to distinguish different messages, different information, etc. "Predefined" can be achieved by pre-storing corresponding codes, tables or other means for indicating relevant information in the device, and the specific implementation manner is not limited in the present application. The "protocol" referred to can refer to a standard protocol in the communication field, which can include a long term evolution (LTE) protocol, a new radio (NR) protocol and a related protocol applied in a future communication system, and the present application is not limited thereto. The words "example", "for example", "exemplary", "as an example", etc. are used to indicate an example, illustration or description. Any embodiment or design scheme described as "example" in the present application should not be interpreted as more preferred or more advantageous than other embodiments or design schemes. The terms "include", "contain", "have" and their variants mean "including but not limited to", unless otherwise specifically emphasized. "At least one" refers to one or more, and "multiple" refers to two or more. "At most one" refers to one or 0. "And / or", which describes the association relationship of the associated objects, means that there can be three kinds of relationships, for example, A and / or B can represent the following three cases: A exists alone, A and B exist together, and B exists alone, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after it. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or multiple items. For example, at least one of a, b and c can represent: a, or b, or c, or a and b, or a and c, or b and c, or a, b and c. Where a, b and c can be single or multiple. The description related to the sending of messages, information or data by network element A to network element B and the receiving of messages, information or data from network element A by network element B is intended to indicate which network element the message, information or data is intended for, and does not limit whether they are directly sent or indirectly sent via other network elements. "When", "in the case of", "if" and "if" and other descriptions all refer to the objective situation in which the device will make corresponding processing, and are not limited by time, and do not require the device to have a judgment action when implemented, nor does it mean that there are other limitations. "Corresponding to", "correspondingly" and equivalent expressions mean that the two have a corresponding relationship, which can include indirect correspondence. For example, corresponding to a certain objective situation, the device will directly or indirectly make corresponding processing, and it is not required that the corresponding processing must follow the occurrence of the objective situation.

[0081] In addition, the network architecture and service scenarios described in the embodiments of the present application are for more clearly illustrating the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application. It can be known by those skilled in the art that, with the evolution of network architecture and the appearance of new service scenarios, the technical solutions provided by the embodiments of the present application are also applicable to similar technical problems.

[0082] The communication system to which the embodiments of the present application can be applied will be described below.

[0083] The embodiments of the present application can be applied to various communication systems, including but not limited to: a 5th generation (5G) system, an LTE system, a long term evolution-advanced (LTE-A) system, an LTE frequency division duplex (FDD) system, an LTE time division duplex (TDD) system, etc. It can also be applied to future communication systems, such as a 6th generation mobile communication system. In addition, it can also be applied to device to device (D2D) communication, vehicle-to-everything (V2X) communication, machine to machine (M2M) communication, machine type communication (MTC), an internet of things (IoT) communication system, a narrow band-internet of things (NB-IoT) system, or other communication systems. In addition, it can also be extended to similar wireless communication systems, such as wireless-fidelity (WiFi), worldwide interoperability for microwave access (WIMAX), and 3rd generation partnership project (3GPP) related communication systems, etc., without limitation.

[0084] The communication system applicable to the embodiments of the present application can include one or more transmitting end devices and one or more receiving end devices. Optionally, one of the transmitting end device and the receiving end device can be a terminal device, and the other can be a network device. Optionally, the transmitting end device and the receiving end device can both be terminal devices. Optionally, the transmitting end device and the receiving end device can both be network devices.

[0085] FIG. 1 is a schematic diagram of a network architecture applicable to the embodiments of the present application. As shown in FIG. 1, the embodiments of the present application can be applicable to both uplink data transmission and downlink data transmission. In FIG. 1, only uplink data transmission or downlink data transmission between one network device and two terminal devices (e.g., terminal device 1 and terminal device 2) is taken as an example. In uplink data transmission, the transmitting end device herein is a terminal device, and the receiving end device is a network device; conversely, in downlink data transmission, the transmitting end device is a network device, and the receiving end device is a terminal device. In addition, the embodiments of the present application are not limited in their applicability to other communication scenarios, for example, they can also be applied to sidelink communication.

[0086] The terminal device of the present application can also be referred to as a user equipment (UE), an access terminal, a user unit, a user station, a mobile station, a mobile station, a mobile terminal (MT), a remote station, a remote terminal, a mobile device, a user terminal, a terminal, a drone, a wireless communication device, a user agent or a user apparatus, etc. The terminal device in the embodiments of the present application can refer to a device that provides voice and / or data connectivity to users, and can be used to connect people, things and machines, such as handheld devices with wireless connection function, vehicle-mounted devices, etc. The terminal device in the embodiments of the present application can be a mobile phone, a tablet computer, a notebook computer, a palm computer, a mobile internet device (MID), a wearable device, a virtual reality (VR) device, an augmented reality (AR) device, a wireless terminal in industrial control, a wireless terminal in self driving, a wireless terminal in remote medical surgery, a wireless terminal in smart grid, a wireless terminal in transportation safety, a wireless terminal in smart city, a wireless terminal in smart home, etc.

[0087] The network device of the present application can be a device with wireless transceiving function, which can be a device providing wireless communication function service, usually located at the network side, including but not limited to next generation base station (gNodeB, gNB) in 5G system, base station in sixth generation mobile communication system, base station in future mobile communication system, or access node in wireless fidelity (WiFi) system, evolved node B (eNB) in long term evolution (LTE) system, radio network controller (RNC), node B (NB), base station controller (BSC), home base station (such as home evolved NodeB or home Node B, HNB), base band unit (BBU), transmission reception point (TRP), transmitting point (TP), base transceiver station (BTS), satellite, unmanned aerial vehicle, etc. In one network structure, the network device can include a centralized unit (CU) node, or include a distributed unit (DU) node, or be a RAN device including CU node and DU node, or be a RAN device including control plane CU node and user plane CU node, and DU node, or the network device can also be a wireless controller in cloud radio access network (CRAN) scenario, relay station, vehicle-mounted device, wearable device, etc. In addition, the base station can be a macro base station, micro base station, relay node, donor node or combination thereof. The base station can also refer to a communication module, modem or chip for setting in the foregoing device or apparatus. The base station can also be a mobile switching center and a device assuming base station function in D2D, V2X, M2M communication, network side device in 6G network, device assuming base station function in future communication system, etc. The base station can support networks of the same or different access technologies, without limitation.

[0088] Unless otherwise defined, the apparatuses used in the embodiments of the present application to realize the functions of the terminal device or the network device can refer to the terminal device or the network device itself, or can refer to an apparatus capable of supporting the terminal device or the network device to realize the functions, such as a chip system or a chip, specifically, a system on a chip (SoC) or a Modem. The apparatus can be installed in the terminal device or the network device. In the embodiments of the present application, the chip system can be composed of a chip, or can include a chip and other discrete devices.

[0089] It should also be noted that some embodiments in the present document take the 5G system as an example to introduce specific scheme details. It can be understood that when the scheme is used in other communication systems, for example, the LTE system, or future communication systems, the messages, channels or information in the scheme can be replaced by messages, channels or information capable of realizing corresponding functions in other communication systems, and the present application does not limit this.

[0090] In addition, the embodiments of the present application can be applied to various application scenarios, such as a high throughput scenario, a high reliability scenario, a low latency scenario, a high reliability low latency scenario, or a low power consumption scenario. Among them, the high throughput scenario can be, for example, an enhanced mobile broadband (eMBB) scenario, and the like, the high reliability low latency scenario can be, for example, an ultra reliable low latency communication (URLLC) scenario, and the like, and the low power consumption scenario can be, for example, an M2M scenario, an MTC scenario, or an IoT scenario, and the like.

[0091] In order to facilitate understanding of the embodiments of the present application, several concepts or terms related to the embodiments of the present application are briefly described. The concepts or terms described below are described based on the concepts or terms defined in the protocol, but do not mean that the embodiments of the present application can only be applied to the existing system, and the concepts or terms related to the embodiments of the present application can be applied to future systems. And the specific name of the concept or term (for example, the concept or term related to the functional description) can be adjusted with the development of future systems.

[0092] 1. LDPC code

[0093] LDPC code is a kind of linear block code. Linear block code is to divide the information sequence to be coded into groups in units of q bits, and then linearly operate the q information bits by the encoder to obtain m check bits, and then combine the q information bits and the m check bits to obtain a code word with length n=q+m. The mapping relationship from the q-bit information bits to the n-bit code word is usually represented by a corresponding check matrix H. According to the check matrix H, the code word sequence can be generated to complete the coding process. After the code word sequence is transmitted through the channel, the receiving end device decodes the received signal to determine the original information bits.

[0094] The check matrix H of LDPC is a sparse matrix. The number of zero elements in the check matrix H is much larger than the number of non-zero elements, or in other words, the row weight (or column weight) of the check matrix is much smaller than the number of elements in each row (or each column) of the LDPC matrix. The LDPC code with the information bit sequence length equal to q and the code length equal to n can be uniquely determined by its check matrix H.

[0095] Tanner represented the check matrix H in the form of a graph in 1981. This graph is now called a Tanner graph, and the Tanner graph and the check matrix correspond one-to-one. The Tanner graph is composed of two types of vertices. One type of vertex represents a code word bit, which is called a variable node. The other type of vertex is a check node, which represents a check constraint relationship. Each check node represents a check constraint relationship. The following will be explained in conjunction with FIG. 2 and FIG. 3.

[0096] FIG. 2 is a schematic diagram of a check matrix H of an LDPC.

[0097] In FIG. 2, {V i} represents a set of variable nodes (VN), and {C i} represents a set of check nodes (CN). Each row of the check matrix H represents a check equation, each check equation corresponds to a check node, each column represents a code word bit, and each code word bit corresponds to a variable node. In FIG. 2, there are 8 variable nodes and 4 check nodes. If a code word bit is included in the corresponding check equation, a line is used to connect the variable node and the check node involved to obtain a Tanner graph.

[0098] FIG. 3 is a Tanner graph of a check matrix H of an LDPC.

[0099] As shown in FIG. 3, the Tanner graph represents the check matrix of the LDPC. For example, for a check matrix H of size m rows and n columns, the Tanner graph contains two types of nodes, n variable nodes and m check nodes. The n variable nodes correspond to the n columns of the check matrix H, and the m check nodes correspond to the m rows of the check matrix H. A cycle in the Tanner graph is formed by a group of vertices connected to each other, a loop is formed by a vertex in the group of vertices serving as both a start point and an end point, and each node is passed only once. The length of the loop is defined as the number of edges contained in the loop, and the girth of the graph can also be referred to as the perimeter of the graph, which is defined as the minimum cycle length in the graph. As shown in FIG. 3, the girth is 4, as indicated by the black lines. Each variable node in the Tanner graph corresponds to each column of the check matrix H, that is, each code bit of the LDPC. Each check node in the Tanner graph corresponds to each row of the check matrix H, that is, each check bit of the LDPC. The connection between the two types of nodes corresponds to the value of the element in the H matrix. If there is a connection between the i th check node and the j th variable node, it means that the value of the element (i, j) in the H matrix is 1, and if there is no connection, the corresponding element is 0. The connection between the variable node and the check node can also be referred to as an edge. The connection between the check node and the variable node can also be described as: the check node and the variable node have a connection or an edge. The edge relationship between the check node and the variable node can include the existence of an edge or the non-existence of an edge. In addition, in the Tanner graph, a cycle refers to a closed loop formed by variable nodes, check nodes, and edges connected end to end.

[0100] 2. QC-LDPC code

[0101] The QC-LDPC code is a structured LDPC code. Due to the unique structure of the check matrix, a simple feedback shift register can be used for encoding, reducing the encoding complexity of the LDPC code. The QC-LDPC code actually used is represented by a base graph (BG). The elements in the BG are 0 or 1. The 1 and 0 in the BG are expanded, and the check matrix H obtained after the expansion can be used for encoding or decoding. In the embodiments of the present application, the BG can be written in the form of a matrix, which can be referred to as a base matrix H BG in the present application. BGThe middle element is 0, indicating that there is no edge in the base graph, and is 1, indicating that there is an edge in the base graph (or indicating that the corresponding check is associated with the corresponding variable). The NR LDPC code involves multiple base graph selection, and the current standard stores two base graphs BG1 and BG2. When the information length is less than or equal to 292, or the information length is less than or equal to 3824 and the code rate is less than or equal to 2 / 3, or the code rate is less than or equal to 0.25, BG2 is used, otherwise BG1 is used. The following describes the extension process of the base matrix.

[0102] Based on the base matrix and the lifting value Z c , the base matrix can be extended to a complete check matrix for encoding or decoding. In this application, Z c may also be referred to as an extension factor, a lifting factor, an extension value, an extension coefficient, a lifting size, etc. The extension process is to lift all elements in the base matrix to a Z c × Z c matrix, wherein 0 is lifted to a Z c × Z c 0 matrix, and 1 is lifted to a unit matrix and cyclically shifted based on the shifting value (SV) corresponding to 1. The cyclic shift can be to the left or to the right, which is not limited in this application. It can be understood that each 1 in the base matrix corresponds to a shifting value. Taking a 4*4 unit matrix as an example, if the shifting values are 0, 1, and 3, the cyclic shift matrix after right cyclic shift is as shown in the following table:

[0103] (1) When the shifting value is 0 (i.e. remains unchanged), the corresponding matrix after cyclic shift is

[0104] (2) When the shifting value is 1, the corresponding matrix after cyclic shift is

[0105] (3) When the shifting value is 3, the corresponding matrix after cyclic shift is

[0106] It can also be understood that the complete check matrix H can be represented by an exponential matrix H b , and each element in H b corresponds to a Z c × Z c submatrix, and each element identifies the number of times of cyclic shift of the corresponding submatrix from the unit matrix. Thus, the storage space required by the complete check matrix H is greatly reduced. The elements in the exponential matrix H b may also be referred to as QC blocks.

[0107] For example, the exponential matrix H of the QC-LDPC code is bAs shown below:

[0108] It can be seen that the size of the exponent matrix H b is 4 rows and 24 columns, and each element i in the exponent matrix H b represents a Z c order square matrix represents a cyclic shift matrix, i represents a cyclic shift value of the cyclic shift matrix, and i is an integer. In addition, "-1" in the exponent matrix H b represents an all-zero matrix, and "0" represents an identity matrix.

[0109] For example, As shown below:

[0110] Optionally, in addition to "-1", the zero element in the exponent matrix H b may also have other forms of expression, such as using "-" or a null value to represent an all-zero matrix.

[0111] It can be understood that the matrix corresponding to changing the positions greater than and equal to 0 in the above exponent matrix H b to 1 and changing the positions of -1 to 0 is a base matrix. The 1 in the base matrix is extended to a cyclic shift matrix based on the elements in the corresponding position of the exponent matrix, and the 0 is extended to a 0 matrix of the corresponding size. After the extension is completed, the check matrix is obtained.

[0112] Then, the information bit sequence c can be encoded based on the check matrix H to obtain a codeword sequence, wherein the codeword sequence includes (N+2*Zc-K) check bits w, N is the length of the codeword sequence, K=Kb*Zc, Kb is the column number of the information column corresponding to the base graph, and Zc is the lifting value, which is described in detail in the term explanation 3. Specifically, the check bits w are determined based on the information bit sequence c and the check matrix H, wherein the check bits are w=[w0,w1,w2,…,wN+2*Zc-K-1] T , c=[c0,c1,c2,…,c K-1 ] T , and the encoding process is a process of solving the equation to obtain w.

[0113] 3. Lifting size Z c and shifting value

[0114] The storage content of the 5G LDPC code with respect to the shifting value includes: (1) a lifting size list; and (2) a shifting value list corresponding to each row of the lifting size list.

[0115] For example, the lifting size list is shown in Table 1.

[0116] Table 1

[0117] The jth row of the lifting size list includes wherein a j ∈{2,3,5,7,9,11,13,15}, max(k j )∈{7,7,6,5,5,5,4,4}; the row index of the lifting size corresponds to the column index of the shifting value, that is, each row of the lifting size list corresponds to a group of shifting values.

[0118] For example, the shifting value list is shown in Table 2.

[0119] Table 2

[0120] For a fixed lifting value index, one non-zero position of the base matrix corresponds to one shifting value. For example, the shifting value corresponding to the 0th row and the 0th column of H BG when the lifting value index is 0 is 211, the shifting value corresponding to the 1st row and the 6th column of H BG when the lifting value index is 3 is 66, and the shifting value corresponding to the 2nd row and the 9th column of H BG when the lifting value index is 7 is 206.

[0121] It can be understood that, when performing LDPC encoding, the lifting value needs to be determined first, and then the corresponding shifting value is determined based on the selected lifting value to construct the check matrix. For example, the determined lifting value is 40, and the lifting value index corresponding to 40 in Table 1 is 2, and then the check matrix can be constructed based on the shifting values in the column corresponding to the lifting value index = 2 in Table 2.

[0122] 4. Column weight and row weight

[0123] For a column of the matrix, the column weight can refer to the number of non-zero elements contained in the column. For a row of the matrix, the row weight can refer to the number of non-zero elements contained in the row. For example, the matrix can be a base matrix, a check matrix or a generator matrix.

[0124] 5. Structure of the base matrix

[0125] Figure 4 is a schematic diagram of the structure of a check matrix.

[0126] As shown in (a) of Figure 4, the check matrix can include a high rate region, an all-zero region, an incremental redundancy region, and a raptor-like region. The high rate region can include the A and B parts shown in (b) of Figure 4, where the A part corresponds to information bits (or information positions, system positions, etc.), and the B part is a square matrix and corresponds to core check bits (or core check positions), where the core check can be the check corresponding to the highest code rate, or can be the check with a degree greater than or equal to 2, or can be the check node corresponding to the row set with the largest row weight (the row weight is significantly / higher than other rows). The all-zero region can correspond to the C part of (b) of Figure 4, which is an all-zero matrix. The incremental redundancy region can correspond to the D part of (b) of Figure 4. The raptor-like region can correspond to the E part of (b) of Figure 4, which can be a unit matrix and corresponds to the check bits for low code rate extension. The B part and the E part are both check parts, the B part is defined as a core check region, and the feature can be a non-lower triangular encoding part (i.e., the values above the diagonal are non-all 0), or an encoding part with a column weight greater than 1, and the E part is defined as an extension check region, and the feature can be a lower triangular encoding part (i.e., the values above the diagonal are all 0), or a diagonal matrix.

[0127] The check matrix of the LDPC code shown in Figure 4 adopts a "raptor-like" structure, and can be gradually extended to a low code rate from a high code rate core matrix. In actual use, as shown in (a) of Figure 4, the first X rows and the first Y columns of the check matrix can be intercepted, and as the code rate gradually decreases from high to low, X and Y gradually increase, and the area of the matrix used also gradually expands.

[0128] It should be noted that the check matrix can be represented by an LDPC base matrix, and therefore the structure of the LDPC base matrix is similar to that of the check matrix, and will not be described in detail here.

[0129] 6. Information columns and check columns

[0130] The columns of the LDPC base matrix are composed of information columns and check columns.

[0131] Information columns: correspond to information bits (or information positions, system positions, etc.), and are the columns corresponding to the A part.

[0132] Check column: corresponds to a check bit (or a check bit, etc.), a column corresponding to the B part and the C part, which can include a core check column and an extended check column. Among them, the core check column is the column corresponding to the B part, and the extended check column is the column corresponding to the C part or the E part, and the extended check column can also be called a raptor-like column. Alternatively, the core check column is the check column with more than 1 in the B part (1 element above and below the diagonal line in the B part), and the extended check column is the remaining column in the check column except the core check column.

[0133] 7、Core row, core column, core matrix

[0134] Core row: the core row of the LDPC base matrix corresponds to the row of the core check bit. In other words, the core row is the row corresponding to the high code rate area, or the row corresponding to the A part, the B part or the C part.

[0135] Core column: can include all information columns and all core check columns. In other words, the core column is the column corresponding to the high code rate area, or the column corresponding to the A part + the B part.

[0136] Core matrix (Kernel Matrix): is a matrix area composed of all core rows and all core columns of the LDPC base matrix. In other words, the core matrix is the high code rate area of the LDPC base matrix, or the part composed of the A part and the B part.

[0137] 8、Information length, code length and code rate

[0138] The information length is the length (i.e. the number of bits contained) of the to-be-sent information bit sequence, which can be the length of the payload information bit or the length of the payload information bit after adding the cyclic redundancy check (CRC) bit, which is not specifically limited in the present application.

[0139] The code length refers to the length of the to-be-sent bit sequence, which can be the to-be-sent bit sequence corresponding to the modulated symbol.

[0140] The code rate refers to the ratio of the length of the to-be-sent information bit sequence to the code length.

[0141] Optionally, the above three values can be pre-configured by high layer signaling, medium access control (MAC) layer or downlink physical layer signal, and can also be obtained or calculated directly by the transceiver. For example, the code length can be determined by the coding and the frame structure, the number of layers and the modulation scheme of the to-be-sent information bit sequence; the code rate can be indicated in the above manner, or given in the modulation and coding scheme (MCS).

[0142] 9. Information transmission process

[0143] FIG. 5 is a schematic diagram of an information transmission process suitable for the present application. As shown in FIG. 5, information is transmitted from a source to a destination through source encoding, channel encoding, modulation, air interface transmission, demodulation, channel decoding, and source recovery. The upper layer processes (including source encoding, channel encoding, and modulation) are performed at the sending end device, and the lower layer processes (including demodulation, channel decoding, and source recovery) are performed at the receiving end device. Embodiments of the present application mainly relate to source encoding, channel encoding, channel decoding, and source recovery.

[0144] Based on the description in the background art, the present application proposes a communication method based on LDPC code, which can effectively solve the above technical problems. The method proposed by the present application is described in detail below.

[0145] FIG. 6 is a schematic flowchart of a communication method 600 based on LDPC code provided by the present application. The method includes the following steps.

[0146] It can be understood that the method 600 can be performed by a sending end device and a receiving end device. Unless otherwise specified, the "sending end device" or "receiving end device" can refer to the sending end device or receiving end device itself, or can refer to a device capable of supporting the sending end device or receiving end device to implement the function. For the convenience of description, the sending end device and the receiving end device are used to describe the following. The sending end device can be a terminal device or a network device, and the receiving end device can be a terminal device or a network device.

[0147] S610, the sending end device acquires an information bit sequence.

[0148] It can be understood that if the sending end device needs to communicate with the receiving end device, i.e., the sending end device needs to send a signal to the receiving end device, the sending end device needs to first acquire the information bit sequence corresponding to the signal to be sent to the receiving end device.

[0149] The sending end device acquires the information bit sequence can mean that the sending end device source encodes the source symbol to generate the information bit sequence, or the sending end device acquires the information bit sequence can also mean that the sending end device receives the information bit sequence from other communication devices. The present application does not limit the way of acquiring the information bit sequence.

[0150] S620, the sending end device determines an LDPC matrix.

[0151] Wherein, the LDPC matrix is determined based on an LDPC base matrix (hereinafter referred to as a base matrix), a lifting value Zc, a numerical value a, and a numerical value b. The characteristics of each parameter used to determine the LDPC matrix are described in detail below.

[0152] (1) Base matrix

[0153] The first area of the base matrix includes L different elements, the L elements including a 0 element and L-1 different non-0 elements, the L-1 non-0 elements being 1 to 2 a*b L-1 integers in the L-1 integers, L being an integer greater than or equal to 2 and less than or equal to 2 a*b a and b are both positive integers and not simultaneously 1.

[0154] For example, a = 1, b = 2, then the first area can include up to 4 elements, the 4 elements being 0, 1, 2, and 3 respectively, wherein 0 is a 0 element, and 1, 2, and 3 are non-0 elements. The L elements are exemplified based on this example. For example, the first area can include L = 2 elements, the 2 elements can be {0, 1} or {0, 2} or {0, 3}, if the 2 elements are {0, 2}, it means that the elements in the first area are non-0 or 2. For example, the first area can include L = 3 elements, the 3 elements can be {0, 1, 2} or {0, 2, 3} or {0, 1, 3}, if the 3 elements are {0, 1, 3}, it means that the elements in the first area are 0 or 1 or 3.

[0155] Optionally, the first area is part or all of the area of the base matrix.

[0156] For example, if the first area is part of the base matrix, the base matrix further includes a second area, the second area can be the remaining area of the base matrix except the first area, and the elements in the second area are non-0 or 1.

[0157] For example, if the first area is all of the base matrix, the positions of the non-0 elements in the base matrix can be the same as the positions of the non-0 elements of the BG1 or BG2 of the NR.

[0158] For example, all the rows of the base matrix and the associated columns of each row can be stored in a table, when there is an associated column, the element at that position in the base matrix is a non-0 element, otherwise it is a 0 element. For example, the storage method of the base matrix can be as shown in the first two rows of Table 2.

[0159] (2) Lifting value Zc, numerical value a, and numerical value b

[0160] Zc, a and b are used to promote each element in the first region into a (a*Zc)*(b*Zc) matrix (hereinafter referred to as the promoted (a*Zc)*(b*Zc) matrix), and the (a*Zc)*(b*Zc) matrix is determined based on the first sub-matrix corresponding to each element, wherein the L first sub-matrices corresponding to the L elements in the first region are all different, the first sub-matrix of each element in the L elements includes (a*b) (Zc*Zc) matrices, the Zc*Zc matrix is a full 0 matrix or an identity matrix, and the (a*Zc)*(b*Zc) matrix is obtained based on cyclic shift of the identity matrix in the first sub-matrix, or the (a*Zc)*(b*Zc) matrix is a full 0 matrix.

[0161] It can be understood that the A*B matrix described in the present application refers to a matrix with A rows and B columns.

[0162] The above description can also be replaced with "Zc, a and b are used to promote each element in the first region into a (a*Zc)*(b*Zc) matrix, and the promoted (a*Zc)*(b*Zc) matrix includes (a*b) (Zc*Zc) matrices, one of which is a full 0 matrix or a cyclic shift matrix of Zc*Zc (the row weight of all rows and the column weight of all columns of the cyclic shift matrix are both 1). Wherein the L first sub-matrices corresponding to the L elements are all different, and the first sub-matrix of each element is a matrix obtained by replacing the Zc*Zc cyclic shift matrix in the (a*b) (Zc*Zc) matrices of the (a*Zc)*(b*Zc) matrix after promotion of the corresponding element with a Zc*Zc identity matrix".

[0163] It can be understood that the first sub-matrix of each element in the L elements is also an (a*Zc)*(b*Zc) matrix (hereinafter referred to as the (a*Zc)*(b*Zc) matrix of the first sub-matrix). The (a*Zc)*(b*Zc) matrix of the first sub-matrix also includes (a*b) (Zc*Zc) matrices, one of which is a full 0 matrix or an identity matrix of Zc*Zc.

[0164] It can also be understood that if each Zc*Zc matrix in the (a*b) Zc*Zc matrices of the first sub-matrix of element #1 in the first region is a full 0 matrix, then the (a*Zc)*(b*Zc) matrix of element #1 after promotion is a full 0 matrix. If the (a*b) Zc*Zc matrices of the first sub-matrix corresponding to element #1 at least contain a unit matrix of Zc*Zc, then the (a*Zc)*(b*Zc) matrix of element #1 after promotion can be regarded as a matrix obtained by keeping the full 0 matrix of Zc*Zc in the first sub-matrix unchanged and cyclically shifting the unit matrix of Zc*Zc in the first sub-matrix.

[0165] It can also be understood that the cyclic shift matrix of Zc*Zc is obtained by cyclically shifting the unit matrix of Zc*Zc based on a shift value. The manner of obtaining the shift value will not be described here, and will be described in detail later.

[0166] For example, the L kinds of elements at least include a first kind of element and a second kind of element, wherein each Zc*Zc matrix in the first sub-matrix of the first kind of element is a full 0 matrix, and each Zc*Zc matrix in the first sub-matrix of the second kind of element is a unit matrix. Further, L=2, and the two kinds of elements include the first kind of element and the second kind of element.

[0167] For example, if the first region is a partial region of the base matrix, the promotion manner of the second region of the base matrix can be that the 0 elements in the second region are promoted to full 0 matrices of Zc*Zc, and the 1 elements are promoted to cyclic shift matrices of Zc*Zc.

[0168] It can be understood that the corresponding LDPC matrix can be obtained after promoting the elements in the base matrix based on the promotion manner described above. In this application, the LDPC matrix can also be referred to as an LDPC encoding matrix. For example, the LDPC matrix can be an LDPC check matrix, or an LDPC generator matrix. The LDPC check matrix or the LDPC generator matrix is a matrix obtained by promoting the elements in all regions of the base matrix based on the corresponding promotion manner, and the LDPC generator matrix and the LDPC check matrix correspond one by one.

[0169] The possible promotion manners of the first region are described below. For ease of description, the entire region of the base matrix is taken as an example for description.

[0170] Promotion manner one: two-stage promotion manner.

[0171] In the lifting manner, first, each element in the base matrix is lifted to an a*b sub-matrix to obtain a first lifting matrix, the elements in the a*b sub-matrix are non-zero or one, and the a*b matrices corresponding to the L elements are all different. Then, each 1 element in the first lifting matrix is lifted to a Zc*Zc cyclic shift matrix, and each 0 element is lifted to a Zc*Zc all-zero matrix, thereby obtaining the LDPC check matrix.

[0172] It can be understood that the a*b matrix includes a*b elements in total, each element is non-zero or one, and the a*b matrix corresponds to at most 2 a*b different a*b matrices. Since the a*b matrices corresponding to the L elements are all different, the L elements are at most 2 a*b elements.

[0173] It can also be understood that the L elements described above include 0 elements and L-1 non-zero elements, and the L-1 non-zero elements are L-1 integers in 1 to 2 a*b . In a possible implementation, the present application can not limit the value range of the L elements. For example, the L elements can be any different L numerical values, as long as the number of element types in the base matrix is not more than 2 a*b . For example, a=1, b=2, L can be equal to 3, and the three elements are -1, -2, and 0, and the a*b matrices after lifting of the three elements are all different.

[0174] In a possible implementation, the a*b matrices after lifting of the L elements are all different, and the value of each element can be converted into a 2-bit sequence with a length of a*b, and the a*b matrix corresponding to the element is a matrix obtained by sequentially filling the 2-bit sequence of the element into the a*b positions of the a*b matrix.

[0175] Optionally, the 2-bit sequence with a length of a*b can be sequentially filled into the a*b positions of the a*b matrix in the order of row first and column second, or in the order of column first and row second. For example, a=2, b=3, the 2-bit sequence with a length of 6 corresponding to element #1 is 101100, and the matrix obtained by filling in the order of row first and column second is shown in Table 3, and the matrix obtained by filling in the order of column first and row second is shown in Table 4.

[0176] Table 3

[0177] Table 4

[0178] The following is an example. The base matrix is shown in Table 5, a=1, b=2, the base matrix includes four elements, and the four elements are {0, 1, 2, 3}. The 1*2 sub-matrix after lifting of {0, 1, 2, 3} in the base matrix is shown in Table 6.

[0179] Table 5

[0180] Table 6

[0181] First, each element in Table 5 is promoted to a 1*2 sub-matrix, and the first promotion matrix after promotion is shown in Table 7. Then, each 0 element in Table 7 is promoted to a Zc*Zc all-0 matrix, and each non-0 element is promoted to a Zc*Zc unit matrix, and the Zc*Zc unit matrix corresponding to the non-0 element is cyclically shifted based on the shift value corresponding to the non-0 element to obtain a cyclic shift matrix corresponding to the non-0 element, thereby obtaining the LDPC check matrix shown in FIG. 8. The manner of obtaining the shift value corresponding to each non-0 element in the base matrix will not be described here, and will be described in detail later.

[0182] Table 7

[0183] Table 8

[0184] Promotion mode two: direct promotion mode.

[0185] This promotion mode can be understood as directly promoting each element of the base matrix to an (a*Zc)*(b*Zc) matrix (i.e., the (a*Zc)*(b*Zc) matrix after promotion) to obtain the LDPC check matrix.

[0186] In this promotion mode, a and b can be predefined or indicated, and each element is promoted based on a and b to obtain the (a*Zc)*(b*Zc) matrix after promotion, or the pattern of the first sub-matrix corresponding to each element can be directly defined, and each element is promoted based on the first sub-matrix corresponding to each element to obtain the (a*Zc)*(b*Zc) matrix after promotion.

[0187] It can be understood that the promotion results based on the promotion mode one and the promotion mode two are the same, that is, the LDPC check matrices after promotion are the same. The difference is that the promotion mode one is an indirect promotion mode, and the promotion mode two is a direct promotion mode.

[0188] The possible promotion modes of the first region of the base matrix are described in detail above. The manner of obtaining the shift value corresponding to each non-0 element in the first region of the base matrix is described below.

[0189] In a possible implementation, the first element corresponds to a*b translation values, the first element is a non-zero element in the first region, and the a*b translation values correspond to the (a*b) (Zc*Zc) matrices of the first submatrix of the first element one by one, where the translation value corresponding to the unit matrix of Zc*Zc in the (a*b) (Zc*Zc) matrices is a natural number, and the translation value corresponding to the all-zero matrix of Zc*Zc in the (a*b) (Zc*Zc) matrices is a first character, and the first character is not equal to the natural number.

[0190] Based on the above lifting manner one, the a*b translation values of the first element correspond to the (a*b) (Zc*Zc) matrices of the first submatrix of the first element one by one, which can also be understood as that the a*b translation values of the first element correspond to the a*b elements in the a*b matrix (the first lifting matrix of the first element) of the first element one by one, and if the 0 element in the a*b matrix of the first element corresponds to the first character, the 1 element corresponds to the natural number.

[0191] For example, the first character can be -1. For example, a=1, b=3, and Table 9 is the translation value of the non-zero element in the first region, and each non-zero element in the base matrix corresponds to 8 groups of translation values, and each group of translation values includes 3 translation values.

[0192] Table 9

[0193] For example, the a*b translation values of the first element can correspond to the a*b elements in the first lifting matrix of the first element one by one in the order of row first and column second, or can correspond to the a*b elements in the first lifting matrix of the first element one by one in the order of row first and column second.

[0194] It can also be understood that, in this implementation, the first lifting matrix (or the first submatrix) corresponding to the first element can be determined based on the a*b translation values of the first element, and since the first lifting matrix (or the first submatrix) of the L types of elements are not the same, in this implementation, the values of each element in the first region can not be stored, and the type of each element can be implicitly indicated based on the a*b translation values corresponding to each element.

[0195] In another possible implementation, the first element corresponds to M translation values, the first element is a non-zero element in the first region, and the M translation values correspond to the M unit matrices of Zc*Zc in the first submatrix of the first element one by one, where each of the M translation values is a natural number, and M is greater than or equal to 1 and less than or equal to a*b.

[0196] Based on the above lifting manner one, the M translation values correspond to the M Zc*Zc unit matrices in the first sub-matrix of the first element one by one, and can also be understood as that the M translation values correspond to the non-zero elements in the a*b elements of the first lifting matrix one by one, that is, the number of non-zero elements in the first lifting matrix of the first element is M.

[0197] For example, the M translation values of the first element can correspond to the M non-zero elements in the first lifting matrix of the first element one by one in the order of row first and column second, or can correspond to the M non-zero elements in the first lifting matrix of the first element one by one in the order of row first and column second.

[0198] For example, Table 10 is the translation values of the non-zero elements in the first region, and each non-zero element in the first region corresponds to 8 groups of translation values, and the number of translation values contained in each group of translation values of each element is the same, but the number of translation values corresponding to different non-zero elements can be different.

[0199] Table 10

[0200] In another possible implementation, the first element corresponds to t translation values, the first element is a non-zero element in the first region, and the translation values corresponding to the (Zc*Zc) unit matrices in the (a*b) (Zc*Zc) matrices of the first sub-matrix of the first element are determined based on the t translation values corresponding to the first element and the element type of the first element, t is an integer greater than or equal to 0 and less than Q, and Q is the number of Zc*Zc unit matrices contained in the (a*b) (Zc*Zc) matrices of the first sub-matrix of the first element. For example, t=0 or 1 or 2.

[0201] Based on the above lifting manner one, the translation values corresponding to the (Zc*Zc) unit matrices in the (a*b) (Zc*Zc) matrices of the first sub-matrix of the first element are determined based on the t translation values corresponding to the first element and the element type of the first element, and can also be understood as that the translation values corresponding to the non-zero elements in the a*b elements of the first lifting matrix of the first element are determined based on the t translation values corresponding to the first element and the element type of the first element, t is an integer greater than or equal to 0 and less than Q, and Q can also be understood as the number of non-zero elements in the first lifting matrix of the first element.

[0202] For example, if t is greater than 0 and less than Q, several possible ways to obtain the translation values corresponding to the first element are given.

[0203] Manner one: the translation value corresponding to the first element is determined based on the first rule and the second rule, wherein the first rule is used to indicate that the correspondence between the t translation values of the first element and the non-zero elements in the first lifting matrix of the first element is determined based on the number t of translation values, and the second rule is used to generate the translation values corresponding to the remaining non-zero elements in the first lifting matrix of the first element based on the t translation values.

[0204] As shown in FIG. 7, taking t = 1, the first element being the 1 element, and the first lifting matrix of the first element being a 1*3 all-1 matrix as an example, the first element corresponds to one translation value SV1. Based on the number of translation values of the first element, the first rule is used to determine that SV1 is the translation value corresponding to the first non-zero element in the first lifting matrix of the first element. Then, based on SV1, the second rule is used to generate the translation values SV2 and SV3 corresponding to the remaining two non-zero elements in the first lifting matrix of the first element.

[0205] Manner two: the translation value corresponding to the first element is determined based on the third rule and the second rule, wherein the third rule is used to indicate that the correspondence between the t translation values of the first element and the non-zero elements in the first lifting matrix of the first element is determined based on the number t of translation values and the element type of the first element, and the second rule is used to generate the translation values corresponding to the remaining non-zero elements in the first lifting matrix of the first element based on the t translation values.

[0206] As shown in FIG. 8, taking t = 1, the first element being the 1 element, and the first lifting matrix of the first element being a 1*3 all-1 matrix as an example, the first element corresponds to one translation value SV1. Based on the number of translation values of the first element and the element type of the first element, the third rule is used to determine that SV1 is the translation value corresponding to the first non-zero element in the first lifting matrix of the first element. Then, based on SV1, the second rule is used to generate the translation values SV2 and SV3 corresponding to the remaining two non-zero elements in the first lifting matrix of the first element.

[0207] Manner three: the translation value corresponding to the first element is determined based on the fourth rule, wherein the fourth rule is used to indicate that the translation values corresponding to all non-zero elements in the first lifting matrix of the first element are generated based on the t translation values.

[0208] As shown in FIG. 9, taking t = 1, the first element being the 1 element, and the first lifting matrix of the first element being a 1*3 all-1 matrix as an example, the first element corresponds to one translation value SV. Based on the translation value SV, the fourth rule is used to determine to generate the translation values SV1, SV2 and SV3 corresponding to all non-zero elements in the first lifting matrix of the first element.

[0209] For example, in one possible implementation, if t = 0, one shift value SV of the first element is determined based on two sequences, all elements of the first sequence in the two sequences correspond to all rows of the base matrix one by one, and all elements of the second sequence in the two sequences correspond to all columns of the base matrix one by one. Further, one SV of the first element located at the i-th row and the j-th column of the base matrix is determined based on an element R(i) in the first sequence R corresponding to the i-th row of the base matrix, an element C(j) in the second sequence C corresponding to the j-th column of the base matrix, and Zc, for example, SV = mod(R(i) * C(j), Zc). Then, the shift value corresponding to the first element can be determined based on any one of the above-described mode 1 to mode 3.

[0210] The above describes the way of obtaining the shift value of the first element. The following illustrates the range of the region that the first region can correspond to. In one possible implementation, the first region is a partial region of the base matrix, and the base matrix includes the first region and a second region, and the union of the first region and the second region is all regions of the base matrix, that is, each element in the base matrix is located in the first region or belongs to the second region, wherein the first region uses the promotion method proposed in the present application, and the second region uses the promotion method corresponding to the second region described above. The following illustrates the first region and the second region.

[0211] Before introducing the specific implementation, first, the row and column characteristics of the base matrix are described. As known from the foregoing, the base matrix is composed of five parts, the five parts of the LDPC matrix include the A part, the B part, the C part, the D part and the E part, the total number of rows of the base matrix is X rows, and the total number of columns is Y columns, wherein the following characteristics exist in the region composed of the partial rows and the partial columns of the base matrix: the LDPC matrix A part is a region composed of the 1st~x1 rows and the 1st~y1 columns of the LDPC matrix base matrix, the LDPC matrix B part is a region composed of the 1st~x1 rows and the y1+1~y2 columns of the LDPC matrix base matrix, the matrix corresponding to the LDPC matrix B part is a square matrix, the LDPC matrix C part is a region composed of the 1st~x1 rows and the y2+1~Y columns of the LDPC matrix base matrix, the matrix corresponding to the LDPC matrix C part is a full 0 matrix, the LDPC matrix D part is a region composed of the x1+1~X rows and the 1st~y2 columns of the LDPC matrix base matrix, the LDPC matrix E part is a region composed of the x1+1~X rows and the y2+1~Y columns of the LDPC matrix base matrix, and the matrix corresponding to the LDPC matrix E part is an identity matrix.

[0212] In an example, the first to x1 rows of the base matrix can be referred to as core rows, the first to y1+1 columns of the base matrix can be referred to as information columns, the y1+1 to y2 columns of the base matrix can be referred to as core check columns, the first to y2 columns of the base matrix can be referred to as core columns, and the y2+1 to Y columns can be referred to as extended check columns. The following describes specific implementation manners of possible region division based on the above row and column characteristics.

[0213] In an example one, the first region is a region composed of the first to x rows and the first to y2 columns of the base matrix (i.e., the A+B+D part of the base matrix), and the second region is all regions of the base matrix except the first region (i.e., the C+E part of the base matrix).

[0214] The example has the advantage that the E part supports hybrid automatic repeat request (HARQ) and has a lower triangular structure, and diagonal elements are necessarily non-zero. Using the lifting manner proposed in this application, the first lifting matrix corresponding to the diagonal elements is a non-all-zero and non-all-one matrix, which causes some additional complexity. Therefore, the E part can be lifted based on the lifting manner corresponding to the second region.

[0215] In an example two, the first region is a region composed of the first to x1 rows and the first to y1 columns of the base matrix and a region composed of the x1+1 to x rows and the first to y2 columns of the base matrix (i.e., the A+D part), and the second region is all regions of the base matrix except the first region (i.e., the B+C+E part of the base matrix).

[0216] The example has the advantage that the B part can have a more flexible coding structure, simple hardware coding, and optimization of the trap set of the region, and the A+D region can completely use the lifting manner proposed in this application.

[0217] In an example three, the first region is a region composed of all rows of the base matrix and all columns of the base matrix except at least one column of the y1+1 to y2 columns (i.e., the core check columns) and the y2+1 to Y columns (i.e., the extended check columns) of the base matrix, and the second region is all regions of the base matrix except the first region.

[0218] The example has the advantage that the property of easy coding can be achieved with as few mixed structures as possible, and hardware utilization is high.

[0219] Optionally, the at least one column of the y1+1 to y2 columns is all columns of the y1+1 to y2 columns.

[0220] Optionally, at least one column in the y1+1~y2-th columns includes the first column, wherein the first column has an odd column weight greater than 1 in the region composed of the 1~x1-th rows and the y1+1~y2-th columns of the base matrix (i.e., the B part of the base matrix). It is emphasized that the column weight of the first column in the B part is the number of non-zero elements in all the elements of the first column in the B part.

[0221] The above describes the regions in the base matrix using different lifting manners, and the design rule of the element x in the first region is described below.

[0222] The element x is neither the first type of element nor the second type of element, wherein the first type of element has each Zc*Zc matrix in the first sub-matrix being a full zero matrix, and the second type of element has each Zc*Zc matrix in the first sub-matrix being an identity matrix. It can be understood that, based on the first lifting manner, the first lifting matrix corresponding to the first type of element is a full zero matrix of a*b, and the first lifting matrix corresponding to the second type of element is a full one matrix of a*b. For example, as shown in Table 6, the first type of element is a 0 element, the second type of element is a 1 element, and the element x is 2 and 3.

[0223] For example, the design rule of the element x in the first region is described below by taking the region composed of the A part, the B part and the D part of the base matrix as an example.

[0224] (1) When the punch column is included, the design rule of the element x in the core array (i.e., the A+B part of the base matrix).

[0225] Optionally, the first region corresponds to at least one fixed punch column, and each punch column in the at least one fixed punch column corresponds to an element including at least one element x. More specifically, at least one row in the region composed of the 1~x1-th rows (i.e., the core rows) of the base matrix and the at least one fixed punch column includes the element x.

[0226] The advantage of this design rule is that the structure of the element x can be compatible with the punch structure (if each row contains 0 or more than one punch node, the LDPC cannot be decoded), so at least one element x is needed when the code rate corresponding to the core array works. At the same time, the element x brings greater freedom to the LDPC design; but the structure of the element x will cause waste of hardware resources, and there is a balance between performance and hardware utilization.

[0227] (2) When the punch column is not included, the design rule of the element x in the core array.

[0228] Optionally, each row in the A part includes at most one element x. The advantage of this design rule is that the hardware utilization is high, and it can support arbitrary row weight distribution, and the decoding performance is good.

[0229] Optionally, the element x is not included in the A part. The advantage of this design rule is that the hardware utilization is the highest, and the decoding architecture design is simpler.

[0230] Optionally, there are at most m x in the B part (the B part is an m*m matrix), and each row in the B part contains at most 2 x. The advantage of this design rule is that the property of easy encoding can be achieved with as few mixed structures as possible, and the hardware utilization is high.

[0231] (3) Design rule of the element x in the incremental redundancy area (i.e., the D part of the base matrix).

[0232] In an implementation, in the D part, the number of the element x located in the D part in the row decreases as the row number increases (i.e., as the code rate decreases). The advantage of this design rule is that as the code rate decreases, the degree distribution design space is larger, thus making the hardware utilization higher.

[0233] For example, the number of the element x included in each row in the D area is less than the threshold value corresponding to each row, and the threshold value corresponding to each row is determined based on the first information corresponding to each row, and the first information includes at least one of the current code rate corresponding to each row, the row weight corresponding to each row in the base matrix, the row weight corresponding to each row in the base matrix without the puncturing column, and the connection structure of the element x included in each row and the puncturing column of the base matrix. For example, the base matrix corresponds to two puncturing columns 1 and 2, and there are four cases of the connection structure of each row, which are connected to both the puncturing column 1 and the puncturing column 2, connected to one of the puncturing column 1 and the puncturing column 2, and not connected to both the puncturing column 1 and the puncturing column 2.

[0234] For example, there is a row number i' in the D area, and the rows with the row number greater than i' in the D area do not include the element x.

[0235] In another implementation, all the rows in the D area correspond to S row sets, wherein each row set in the S row sets includes at least one row, the row number of the at least one row is a row number of a consecutive row, the number of the element x included in all the rows in each row set is the same, and the larger the row number of the first row in one row set in the S row sets is, the fewer the number of the element x included in the rows in the row set is, and S is an integer greater than 1. In simple terms, all the rows in the D area are divided into S segments, wherein the number of the element x corresponding to all the rows in each segment is a fixed value, and the number of the element x corresponding to each segment decreases as the segment decreases. The advantage of this design rule is that as the code rate decreases, the degree distribution design space is larger, thus making the hardware utilization higher.

[0236] For example, there are row numbers i1, i2, i3 in the D part, and i1 < i2 < i3, all the rows with row numbers less than i1 in the D part correspond to the first segment, all the rows with row numbers greater than or equal to i1 and less than i2 correspond to the second segment, all the rows with row numbers greater than or equal to i2 and less than i3 correspond to the third segment, and all the rows with row numbers greater than or equal to i3 correspond to the fourth segment. All the rows in each segment correspond to the same number of elements x, and the number of elements x corresponding to each segment decreases with the segment. For example, the number of elements x corresponding to the first segment is 3, the number of elements x corresponding to the second segment is 2, the number of elements x corresponding to the third segment is 1, and the number of elements x corresponding to the fourth segment is 0.

[0237] Optionally, the number of elements x in the extended area is less than that in the core matrix. The advantage of this design rule is that as the code rate decreases, the degree distribution design space is larger, and the hardware utilization is higher compared to the high code rate part of the A part.

[0238] In S630, the sending end device encodes the information bit sequence according to the LDPC matrix to output a codeword sequence.

[0239] For ease of description, this step is simply described here by taking the LDPC matrix as the LDPC check matrix H as an example. The information bit sequence c is encoded based on the LDPC check matrix H to obtain a codeword sequence, where the codeword sequence includes (N+2*Zc-K) check bits w, N is the length of the codeword sequence, K=Kb*Zc, and Kb is the column number of the information column corresponding to the base graph. Specifically, the check bits w are determined based on the information bit sequence c and the check matrix H, where the check bits are w=[w0, w1, w2, …, wN+2*Zc-K-1] T , c=[c0, c1, c2, …, c K-1 ] T , and the encoding process is to solve the equation to obtain w.

[0240] In S640, the sending end device determines a symbol sequence based on the codeword sequence.

[0241] It can be understood that the symbol sequence can be a sequence after rate matching and modulation. For example, the sending end device performs rate matching on the codeword sequence, then modulates the sequence after rate matching to obtain a symbol sequence, and then maps the modulated symbol sequence to a physical resource for transmission.

[0242] In S650, the sending end device sends the symbol sequence to the receiving end device. Correspondingly, the receiving end device receives the symbol sequence from the sending end device.

[0243] It can be understood that the symbol sequence #1 sent by the sending device and the symbol sequence #2 received by the receiving device can be different due to the channel noise signal introduced in the transmission process of the symbol sequence.

[0244] At S660, the receiving device decodes the symbol sequence according to the LDPC matrix to obtain the information bit sequence.

[0245] The LDCP matrix according to which the receiving device decodes is the same as the LDPC matrix according to which the sending device encodes, and the specific manner in which the receiving device determines the LDPC matrix can refer to the description on the sending device side, which will not be described in detail here.

[0246] It can be understood that the steps in the above figures are only exemplary and are not strictly limited. In addition, the size of the serial number of the above processes does not mean the order of execution, and the execution order of the processes should be determined according to their functions and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0247] It can also be understood that some optional features in the embodiments of the present application can not depend on other features in some scenarios, or can be combined with other features in some scenarios, without limitation.

[0248] It can also be understood that the methods and operations implemented by the device (sending device or receiving device) in the above method embodiments can also be implemented by the constituent components of the device, such as chips or circuits, without limitation.

[0249] The above describes the method embodiments provided by the present application in detail in combination with FIGS. 1 to 9. The device embodiments of the present application will be described below in combination with FIGS. 10 and 11. It can be understood that, in order to realize the functions in the above embodiments, the devices in FIGS. 10 and 11 include the corresponding hardware structures and / or software modules for executing various functions. Those skilled in the art should easily realize that, in combination with the units and method steps of the examples described in the embodiments disclosed in the present application, the present application can be realized in the form of hardware or a combination of hardware and computer software. It can be understood that the technical features described in the above method embodiments are also applicable to the following device embodiments.

[0250] FIGS. 10 and 11 are structural schematic diagrams of possible devices provided by the embodiments of the present application. These devices can be used to realize the functions of the sending device or the receiving device in the above method embodiments, and thus can also realize the beneficial effects possessed by the above method embodiments.

[0251] FIG. 10 is a schematic block diagram of a communication apparatus 1000 according to an embodiment of the present application. As shown in FIG. 10, the apparatus 1000 can include a communication unit 1010 and a processing unit 1020. The communication unit 1010 can be configured to communicate with an external device, and the processing unit 1020 can be configured to perform data processing. The communication unit 1010 can also be referred to as a communication interface or a transceiver unit.

[0252] In a possible design, the apparatus 1000 can implement steps or procedures corresponding to those performed by a sending device in the above-described method embodiments. The processing unit 1020 can be configured to perform processing-related operations of the sending device in the above-described method embodiments, and the communication unit 1010 can be configured to perform transmission-related operations of the sending device in the above-described method embodiments.

[0253] In another possible design, the apparatus 1000 can implement steps or procedures corresponding to those performed by a receiving device in the above-described method embodiments. The communication unit 1010 can be configured to perform receiving-related operations of the receiving device in the above-described method embodiments, and the processing unit 1020 can be configured to perform processing-related operations of the receiving device in the above-described method embodiments.

[0254] It can be understood that the apparatus 1000 is in the form of functional units. The term “unit” can refer to an application specific integrated circuit (ASIC), an electronic circuit, a processor (shared, dedicated or group) and memory that execute one or more software or firmware programs, a combinational logic circuit, and / or other suitable components that provide the described functionality. In one possible design, the apparatus 1000 can be specifically the sending device in the above-described embodiments, and can be configured to perform the procedures and / or steps corresponding to the sending device in the above-described method embodiments. Alternatively, the apparatus 1000 can be specifically the receiving device in the above-described embodiments, and can be configured to perform the procedures and / or steps corresponding to the receiving device in the above-described method embodiments. To avoid redundancy, details are not described here again.

[0255] The apparatus 1000 of each of the above-mentioned solutions has a function of implementing the corresponding steps performed by the sending-end device in the above-mentioned methods, or the apparatus 1000 of each of the above-mentioned solutions has a function of implementing the corresponding steps performed by the receiving-end device in the above-mentioned methods. The function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above-mentioned functions; for example, the communication unit can be replaced by a transceiver (for example, the sending unit in the communication unit can be replaced by a transmitter, and the receiving unit in the communication unit can be replaced by a receiver), and other units such as the processing unit can be replaced by a processor, which respectively performs the transceiving operation and the related processing operation in each method embodiment.

[0256] In addition, the communication unit can also be a transceiving circuit (for example, can include a receiving circuit and a sending circuit), and the processing unit can be a processing circuit. In embodiments of the present application, the apparatus in FIG. 10 can be a receiving-end device or a sending-end device in the foregoing embodiments, or can be a chip or a chip system, for example, a system on chip (SoC). The communication unit can be an input / output circuit or a communication interface, and the processing unit can be a processor or a microprocessor integrated on the chip or an integrated circuit. In this regard, no limitation is made.

[0257] FIG. 11 is a schematic block diagram of a communication apparatus 1100 provided by embodiments of the present application. The apparatus 1100 includes a processor 1110 and a transceiver 1120. The processor 1110 and the transceiver 1120 communicate with each other through an internal connection path. The processor 1110 is configured to execute instructions to control the transceiver 1120 to send and / or receive signals.

[0258] Optionally, the apparatus 1100 can further include a memory 1130, which communicates with the processor 1110 and the transceiver 1120 through an internal connection path. The memory 1130 is configured to store instructions, and the processor 1110 can execute the instructions stored in the memory 1130. In a possible implementation, the apparatus 1100 is configured to implement the corresponding procedures and steps of the sending-end device in the above-mentioned method embodiments. In another possible implementation, the apparatus 1100 is configured to implement the corresponding procedures and steps of the receiving-end device in the above-mentioned method embodiments.

[0259] Optionally, the memory 1130 can be integrated in the processor 1110.

[0260] In a possible scenario, the apparatus 1100 includes at least one processor integrated with a memory and other memory in addition to the memory integrated on the processor.

[0261] It can be understood that the apparatus 1100 can be specifically a sending device or a receiving device in the above-described embodiments, or can be a chip or a chip system. Correspondingly, the transceiver 1120 can be a transceiver circuit of the chip, which is not limited here. Specifically, the apparatus 1100 can be configured to perform various steps and / or processes in the above-described method embodiments corresponding to the sending device or the receiving device.

[0262] Optionally, the memory 1130 can include read-only memory and random access memory, and provide instructions and data for the processor. The memory can include non-volatile random access memory. For example, the memory can also store device type information. The processor 1110 can be configured to execute instructions stored in the memory, and when the processor 1110 executes the instructions stored in the memory, the processor 1110 is configured to perform various steps and / or processes of the above-described method embodiments corresponding to the sending device or the receiving device.

[0263] In the implementation process, the steps of the above method can be completed by integrated logic circuits of hardware in the processor or instructions in the form of software. The steps of the method disclosed in combination with the embodiments of the present application can be directly embodied as hardware processor execution completion, or executed by a combination of hardware and software modules in the processor. The software module can be located in a random access memory, a flash memory, a read-only memory, a programmable read-only memory, an electrically erasable programmable memory, a register, or other mature storage media in the art. The storage medium is located in the memory, and the processor reads the information in the memory, and combines the hardware to complete the steps of the above method. To avoid repetition, it will not be described in detail here.

[0264] It should be noted that the processor in the embodiments of the present application can be an integrated circuit chip with a signal processing capability. In the implementation process, the steps of the method embodiments described above can be completed by the integrated logic circuit or the software form of instructions in the processor. The processor described above can be a general purpose processor, a digital signal processor (DSP), an ASIC, a field-programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. The processor in the embodiments of the present application can realize or execute the methods, steps and logic block diagrams disclosed in the embodiments of the present application. The general purpose processor can be a microprocessor or the processor can also be any conventional processor or the like. The steps of the method disclosed in conjunction with the embodiments of the present application can be directly embodied as a hardware code processor for execution, or be executed by a combination of hardware and software modules in the code processor. The software module can be located in a random access memory, a flash memory, a read only memory, a programmable read only memory or an electrically erasable programmable memory, a register or the like mature storage medium in the art. The storage medium is located in the storage, and the processor reads the information in the storage, and combines the hardware to complete the steps of the above method.

[0265] It is to be appreciated that the memory in the embodiments of the application can be a volatile memory or a nonvolatile memory, or can include both volatile and nonvolatile memory. Where the nonvolatile memory is a read-only memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), electrically EPROM (EEPROM), or flash memory. The volatile memory can be a random access memory (RAM), which is used as an external cache. By way of example, and not limitation, many forms of RAM are available, for example, static RAM (SRAM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), double-data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), and direct rambus RAM (DR RAM). Note that the system and method described herein are intended to include all such memory types and any other suitable type of memory.

[0266] Optionally, the memory (e.g., 1130) in the embodiments of the application can be integrated in the processor (e.g., 1110).

[0267] In addition, the application also provides a computer readable storage medium, the computer readable storage medium stores computer instructions, when the computer instructions run on the computer, the operations and / or processes performed by the sending end device or the receiving end device in the method embodiments of the application are executed.

[0268] The application also provides a computer program product, the computer program product includes computer program codes or instructions, when the computer program codes or instructions run on the computer, the operations and / or processes performed by the sending end device or the receiving end device in the method embodiments of the application are executed.

[0269] Further, the application provides a chip including a processor. A memory for storing a computer program is arranged independently of the chip, and the processor is configured to execute the computer program stored in the memory, so that the operations and / or processes performed by the sending device or the receiving device in any one of the method embodiments are performed.

[0270] Further, the chip can further include a communication interface. The communication interface can be an input / output interface, an interface circuit, or the like. Further, the chip can further include a memory.

[0271] Further, the application provides a communication system including the sending device and the receiving device in the embodiments of the application.

[0272] It should be further noted that the memory described herein is intended to include, but not limited to, these and any other suitable types of memory.

[0273] Those skilled in the art can appreciate that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether the functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the application. Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described system, device and unit can refer to the corresponding processes in the foregoing method embodiments, which will not be described here. In several embodiments provided in the application, it should be understood that the disclosed system, device and method can be implemented in other ways. For example, the above-described device embodiments are only schematic, for example, the division of the units is only a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interface, device or unit, which can be electrical, mechanical or other form. The units described as separate components can be or can not be physically separate, and the components shown as units can be or can not be physical units, i.e. can be located in one place, or can be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment. In addition, the functional units in each embodiment of the application can be integrated in one processing unit, or each unit can be physically present, or two or more units can be integrated in one unit.

[0274] The functions described can be implemented in software, firmware, hardware, or any combination thereof. If implemented in software and as an independent application in a computing environment, the functions described can be stored in one or more of the storage devices, which can also be a memory or database within the computing environment. The software implementing the functions described can be stored on a computer readable storage medium, which can include one or more of a floppy disk, a hard disk, an optical disk, a tape, a semiconductor memory, a memory chip, or the like. The software can also be transmitted or received as a computer data signal in a carrier wave via a communication network, including the Internet, extranet, intranet, local area network, wide area network, wireless network, wireline network, etc.

[0275] It is to be understood that the terminology “one embodiment,” “another embodiment,” “an implementation,” “an embodiment,” “some embodiments,” “one specific embodiment,” or “some implementations” used throughout this specification, indicates that the particular features, configurations, or characteristics described in connection with the embodiment or implementation can be included in, or performed by, one or more embodiments or implementations. Thus, these particular features, configurations, or characteristics are not necessarily included in all embodiments or implementations, whether or not a particular feature, configuration, or characteristic is described as being “essential,” “important,” “preferred,” or “optional” in other portions of the specification.

[0276] It is also to be understood that the transitional phrases, “when,” “if,” “as,” “while,” “where,” “whereby,” “thereby,” “therefore,” “thus,” and the like are to be interpreted flexibly and are not necessarily limited to the transitional sense provided, but are to be accorded their full breadth, consistent with the context of the description.

[0277] It is also to be understood that the transitional phrases, “when,” “if,” “as,” “while,” “where,” “whereby,” “thereby,” “therefore,” “thus,” and the like are to be interpreted flexibly and are not necessarily limited to the transitional sense provided, but are to be accorded their full breadth, consistent with the context of the description.

Claims

1. A communication method based on a low-density parity-check (LDPC) code, characterized by, The method comprises: obtaining an information bit sequence; determining an LDPC matrix, the LDPC matrix being determined based on an LDPC base matrix, a lifting value Z c , a numerical value a and a numerical value b, wherein, The first region of the base matrix includes L elements, the L elements including 0 elements and L-1 non-0 elements, the L-1 non-0 elements being 1 to 2 a*b L-1 different integers in -1, the L being greater than or equal to 2 and less than or equal to 2 a*b integer, the a and the b both being positive integers and not being 1 at the same time, the first region being part or all of the region of the base matrix, the L first sub-matrices corresponding to the L elements are all different, the first sub-matrix of each element in the L elements comprises (a*b) (Zc*Zc) matrices, the Zc*Zc matrix is a full 0 matrix or a unit matrix, the Zc, the a and the b are used for lifting each element in the first area into an (a*Zc)*(b*Zc) matrix, the (a*Zc)*(b*Zc) matrix is determined based on the first sub-matrix corresponding to the each element, the (a*Zc)*(b*Zc) matrix is obtained based on cyclic shift of the unit matrix in the first sub-matrix, or the (a*Zc)*(b*Zc) matrix is a full 0 matrix; encoding the information bit sequence according to the LDPC matrix to obtain a codeword sequence; outputting the codeword sequence.

2. A communication method based on a low-density parity-check (LDPC) code, comprising: obtaining a symbol sequence; determining an LDPC matrix, the LDPC matrix being determined based on an LDPC base matrix, a lifting value Z c , a numerical value a and a numerical value b, wherein, The first region of the base matrix includes L elements, the L elements including 0 elements and L-1 non-0 elements, the L-1 non-0 elements being 1 to 2 a*b L-1 different integers in -1, the L being greater than or equal to 2 and less than or equal to 2 a*b an integer, the a and the b both being positive integers and not being 1 at the same time, the first region being part or all of the region of the base matrix, the L first sub-matrices corresponding to the L elements are all different, the first sub-matrix of each element in the L elements comprises (a*b) (Zc*Zc) matrices, the Zc*Zc matrix is a full 0 matrix or a unit matrix, the Zc, the a and the b are used for lifting each element in the first area into an (a*Zc)*(b*Zc) matrix, the (a*Zc)*(b*Zc) matrix is determined based on the first sub-matrix corresponding to the each element, the (a*Zc)*(b*Zc) matrix is obtained based on cyclic shift of the unit matrix in the first sub-matrix, or the (a*Zc)*(b*Zc) matrix is a full 0 matrix; decoding the symbol sequence according to the LDPC matrix to obtain an information bit sequence.

3. The method according to claim 1 or 2, characterized in that, The method comprises: replacing each element in the first area with an a*b matrix, any element in the a*b matrix is a 0 element or a 1 element, and the a*b matrix corresponding to the L elements are all different; replacing the 0 element in the a*b matrix corresponding to the each element with a full 0 matrix of Zc*Zc, and replacing the 1 element in the a*b matrix with a cyclic shift matrix of Zc*Zc to obtain the LDPC matrix.

4. The method according to claim 1 or 2, characterized in that, The method comprises: replacing each element in the first area with the (a*Zc)*(b*Zc) matrix corresponding to the each element to obtain the LDPC matrix.

5. The method according to any one of claims 1 to 4, characterized in that, The first area is a partial area of the base matrix, and the base matrix further comprises a second area, the second area is a remaining area of the base matrix except the first area, and the element in the second area is a 0 element or a 1 element, The method comprises: lifting the 0 element in the second area into a full 0 matrix of Zc*Zc, and lifting the 1 element in the second area into a cyclic shift matrix of Zc*Zc.

6. The method according to any one of claims 1 to 5, comprising: The first element corresponds to a*b translation values, the first element is a non-zero element in the first region, and the a*b translation values one-to-one correspond to (a*b) (Zc*Zc) matrices of the first sub-matrix of the first element, wherein the translation value corresponding to the unit matrix of Zc*Zc in the (a*b) (Zc*Zc) matrices is a natural number, and the translation value corresponding to the all-zero matrix of Zc*Zc in the (a*b) (Zc*Zc) matrices is a first character, and the first character is not equal to the natural number.

7. The method of claim 6, wherein, the a*b translation values corresponding to the first element one-to-one correspond to (a*b) (Zc*Zc) matrices of the first sub-matrix of the first element in the order of row first and column second, or, the a*b translation values corresponding to the first element one-to-one correspond to (a*b) (Zc*Zc) matrices of the first sub-matrix of the first element in the order of column first and row second.

8. The method of any one of claims 1 to 5, wherein, the first element corresponds to M translation values, the first element is a non-zero element in the first region, and the M translation values one-to-one correspond to M unit matrices of Zc*Zc in the first sub-matrix of the first element, wherein each of the M translation values is a natural number, and M is greater than or equal to 1 and less than or equal to a*b.

9. The method of claim 8, wherein, the M translation values corresponding to the first element one-to-one correspond to the M unit matrices of Zc*Zc in the first sub-matrix of the first element in the order of row first and column second, or, the M translation values corresponding to the first element one-to-one correspond to the M unit matrices of Zc*Zc in the first sub-matrix of the first element in the order of column first and row second.

10. The method of any one of claims 1 to 5, wherein, the first element corresponds to t translation values, the first element is a non-zero element in the first region, and the translation value corresponding to the unit matrix of (Zc*Zc) in the (a*b) (Zc*Zc) matrices of the first sub-matrix of the first element is determined based on the t translation values corresponding to the first element and the element type of the first element, t is an integer greater than or equal to 0 and less than Q, and Q is the number of unit matrices of Zc*Zc contained in the (a*b) (Zc*Zc) matrices of the first sub-matrix of the first element.

11. The method according to any one of claims 1 to 10, characterized in that, the base matrix includes X rows and Y columns, the first region is a region composed of the 1st to Xth rows and the 1st to y2nd columns of the base matrix, or, the first region is a region composed of the 1st to x1st rows and the 1st to y1st columns of the base matrix and a region composed of the x1+1th to Xth rows and the 1st to y2nd columns of the base matrix, or, the first region is a region composed of all rows of the base matrix and columns of the base matrix except at least one column in the y1+1th to y2nd columns and the y2+1th to Yth columns. Wherein, 1 12. The method of claim 11, wherein, The at least one column in the y1+1~y2th column of the base matrix comprises a first column, wherein the first column corresponds to an odd number greater than 1 in the column weight in the region composed of the 1~x1th row and the y1+1~y2th column of the base matrix.

13. The method according to any one of claims 1 to 12, characterized in that, The base matrix is composed of five parts, including an A part, a B part, a C part, a D part and an E part, and the base matrix comprises X rows and Y columns, wherein, The A part is a region composed of the 1~x1th row and the 1~y1th column of the base matrix, The B part is a region composed of the 1~x1th row and the y1+1~y2th column of the base matrix, and the B part corresponds to a square matrix, The C part is a region composed of the 1~x1th row and the y2+1~Yth column of the base matrix, and the C part corresponds to an all-zero matrix, The D part is a region composed of the x1+1~Xth row and the 1~y2th column of the base matrix, The E part is a region composed of the x1+1~Xth row and the y2+1~Yth column of the base matrix, and the E part corresponds to an identity matrix.

14. The method of claim 13, wherein, The first region is a region composed of the 1~Xth row and the 1~y2th column of the base matrix, and the first region comprises a second element, wherein the second element is a type of element other than the first type of element and the second type of element in the L types of elements, wherein each Zc*Zc matrix in the first sub-matrix of the first type of element is an all-zero matrix, and each Zc*Zc matrix in the first sub-matrix of the second type of element is an identity matrix.

15. The method of claim 14, wherein, The first region corresponds to at least one puncturing column, and each puncturing column in the at least one puncturing column contains at least one second element in the corresponding element.

16. The method of claim 15, wherein, At least one row in the region composed of the 1~x1th row and the at least one puncturing column of the base matrix comprises the second element.

17. The method of claim 14, wherein, There is no puncturing column in the first region, Each row in the A part contains at most one second element, Or, The A part does not contain the second element.

18. The method of any one of claims 14 to 17, wherein, In the D part, the larger the row number, the fewer the number of second elements contained in the corresponding row.

19. The method of claim 18, wherein, The number of second elements contained in each row in the D part is less than the corresponding threshold value of each row, and the corresponding threshold value of each row is determined based on the first information corresponding to each row, and the first information comprises at least one of the code rate corresponding to each row, the row weight of each row in the base matrix, the row weight of each row in the base matrix without puncturing columns, and the connection structure of the second elements contained in each row and the puncturing columns of the base matrix.

20. The method of any one of claims 14 to 17, wherein, All rows in the D part correspond to S row sets, wherein each row set in the S row sets includes at least one row, the at least one row is a row with consecutive row numbers, all rows in each row set contain the same number of the second elements, and the larger the row number of a first row in a first row set among the S row sets, the fewer the number of the second elements contained by the rows in the first row set, the first row being a row with the smallest row number in the first row set, and the S being an integer greater than 1.

21. The method of any one of claims 1 to 20, wherein, The L is 2, and the L kinds of elements include a first kind of element and a second kind of element, wherein each Zc*Zc matrix in the first sub-matrix of the first kind of element is a full 0 matrix, and each Zc*Zc matrix in the first sub-matrix of the second kind of element is an identity matrix.

22. A communications device, characterized by The communication device comprises at least one processor and interface circuitry for receiving signals from other communication devices outside the communication device and transmitting signals to the processor or sending signals from the processor to other communication devices outside the communication device, and the processor is configured to implement the method according to any one of claims 1 to 21 by means of logic circuitry or executing code instructions.

23. The communication apparatus according to claim 22, wherein, The communication device is a chip or a chip system.

24. A computer-readable storage medium, characterized in that, The storage medium stores a computer program or instructions, and when the computer program or instructions are executed, the method according to any one of claims 1 to 21 is implemented.

25. A computer program product, characterised in that, The computer program is configured to implement the method according to any one of claims 1 to 21 when the computer program is executed.

26. A communication system, characterized by The computer program product comprises: a sending end device for executing the method according to any one of claims 1, or 3 to 21; a receiving end device for executing the method according to any one of claims 2 to 21.

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