Communication system based on spread spectrum clock

Abstract

A communication system based on a spread spectrum clock. The communication system comprises a first communication device and a second communication device, wherein the first communication device is connected to the second communication device by means of a communication link; the first communication device sends a first signal to the second communication device; the second communication device sends a second signal to the first communication device; the first signal and the second signal are transmitted in a time-division manner on the communication link; a local clock generation module in the first communication device generates a local clock of the first communication device; a clock for the first communication device to send the first signal is the local clock of the first communication device; the local clock of the first communication device is a spread spectrum clock; the first signal includes a synchronization frame; and after the first communication device sends the synchronization frame, the local clock generation module comprised in the first communication device sets the frequency of the local clock of the first communication device to a preset frequency value of the first communication device.

Description

A communication system based on spread spectrum clock TECHNICAL FIELD

[0001] The present application relates to the field of communication technology, and particularly relates to a communication system based on spread spectrum clock. BACKGROUND

[0002] Spread spectrum clock (SSC) is a technology for reducing electromagnetic interference (EMI) of electronic devices, which can prevent EMI problems caused by excessive concentration of energy at a certain frequency. SSC can be used to periodically modulate the clock (for example, triangular wave modulation) to distribute energy over a wider frequency range, thereby reducing the energy intensity at a single frequency and reducing the impact of electromagnetic interference.

[0003] Although SSC can effectively suppress the impact of EMI, it can also introduce clock jitter, thereby increasing the phase noise of the communication system and causing data reception errors. In an audio transmission system, there is often no clock line dedicated to transmitting clock signals in order to save wire. The audio transmission system often uses time-division transmission to transmit audio data, transmitting one or more audio sampling points in each time slice. The system may have intermittent data transmission between time slices, that is, the clock recovery circuit cannot rely on continuous transmission of data. In such a system, using SSC technology is more likely to cause a high bit error rate.

[0004] There is currently a lack of an audio transmission system and method that can both use SSC technology to suppress the impact of EMI and effectively improve the reliability of received data and reduce the bit error rate of received data. SUMMARY

[0005] The technical problem to be solved by the present application is how to both use SSC technology to suppress the impact of EMI and improve the reliability of received data and reduce the bit error rate of received data.

[0006] To solve the above technical problems, the technical scheme adopted by the present application is:

[0007] As a kind of master communication equipment of the present application, a kind of master communication equipment, including downstream device interface module, local clock generation module, the downstream device interface module is connected with downstream device by downlink, downstream device interface module sends first signal to downstream device by downlink, downstream device sends second signal, downstream device interface module receives second signal from downstream device by downlink, first signal and second signal are time-sharing transmission on downlink, the local clock generation module generates local clock, the clock of downstream device interface module sending first signal is local clock, local clock is spread spectrum clock, the first signal includes synchronization frame, downstream device interface module sends synchronization frame, after the downstream device interface module sends synchronization frame, local clock generation module sets the frequency of local clock as preset frequency value.

[0008] Preferably, after the downstream device interface module sends synchronization frame, local clock generation module sets the frequency of local clock as preset frequency value, then the frequency of local clock changes according to preset frequency curve.

[0009] Preferably, the master communication equipment is integrated circuit chip, the local clock generation module generates local clock according to local reference clock, and the local reference clock is generated by a crystal reference clock generation circuit on the integrated circuit chip.

[0010] Preferably, the master communication equipment further includes a host interface module, the host interface module is connected to a host, and the host interface module receives a data frame synchronization signal from the host; the synchronization frame includes data frame synchronization signal information, and the downstream device can recover the data frame synchronization signal according to the synchronization frame.

[0011] Preferably, the master communication equipment further includes a data frame synchronization signal generation module, the data frame synchronization signal generation module generates a data frame synchronization signal, and the synchronization frame includes data frame synchronization signal information, and the downstream device can recover the data frame synchronization signal according to the synchronization frame.

[0012] As a kind of slave communication equipment of the present application, a kind of slave communication equipment, including upstream device interface module, local clock generation module, the upstream device interface module is connected with upstream device by uplink, upstream device sends first signal, upstream device interface module receives first signal from upstream device by uplink, upstream device interface module sends second signal to upstream device by uplink, first signal and second signal are time-sharing transmission on uplink, the local clock generation module generates first local clock, the clock of upstream device interface module sending second signal is first local clock, and first local clock is spread spectrum clock, the first signal includes synchronization frame, and the upstream device interface module receives synchronization frame, after the upstream device interface module receives synchronization frame, local clock generation module sets the frequency of first local clock as first preset frequency value.

[0013] Preferably, after the slave communication device receives the synchronization frame, the local clock generation module sets the frequency of the first local clock to a first preset frequency value, and then the frequency of the first local clock varies according to a first preset frequency curve.

[0014] Preferably, the slave communication device is an integrated circuit chip, and the local clock generation module generates the first local clock according to a local reference clock, which is generated by a crystalless reference clock generation circuit on the integrated circuit chip.

[0015] Preferably, the slave communication device further comprises a data frame synchronization signal recovery module, the synchronization frame comprises data frame synchronization signal information, and the data frame synchronization signal recovery module recovers the data frame synchronization signal according to the received synchronization frame.

[0016] Preferably, the slave communication device further comprises a downstream device interface module, the downstream device interface module is connected to a downstream device through a downlink, the downstream device interface module sends a third signal to the downstream device through the downlink, the slave communication device sends the received synchronization frame to the downstream device through the downlink by including the synchronization frame in the third signal, and the local clock generation module further generates a second local clock, the clock of the downstream device interface module for sending the third signal is the second local clock, the second local clock is a spread spectrum clock, and after the slave communication device sends the received synchronization frame to the downstream device through the downlink by including the synchronization frame in the third signal, the local clock generation module sets the frequency of the second local clock to a second preset frequency value.

[0017] Further, after the slave communication device sends the received synchronization frame to the downstream device through the downlink by including the synchronization frame in the third signal, the local clock generation module sets the frequency of the second local clock to a second preset frequency value, and then the frequency of the second local clock varies according to a second preset frequency curve.

[0018] Further, the slave communication device is an integrated circuit chip, and the local clock generation module generates the second local clock according to a local reference clock, which is generated by a crystalless reference clock generation circuit on the integrated circuit chip.

[0019] As a slave communication device of the present application, comprising an upstream device interface module, a downstream device interface module, a local clock generation module, the upstream device interface module is connected with an upstream device through an uplink, the upstream device sends a first signal, the upstream device interface module receives the first signal from the upstream device through the uplink, the upstream device interface module sends a second signal to the upstream device through the uplink, the first signal and the second signal are transmitted in time division on the uplink, the local clock generation module generates a first local clock, the clock of the upstream device interface module sending the second signal is the first local clock, the first signal contains a synchronization frame, the upstream device interface module receives the synchronization frame, the downstream device interface module is connected with a downstream device through a downlink, the downstream device interface module sends a third signal to the downstream device through the downlink, the slave communication device sends the received synchronization frame to the downstream device through the downlink and contains it in the third signal, the local clock generation module also generates a second local clock, the clock of the downstream device interface module sending the third signal is the second local clock, the second local clock is a spread spectrum clock, after the slave communication device sends the received synchronization frame to the downstream device through the downlink and contains it in the third signal, the local clock generation module sets the frequency of the second local clock to a second preset frequency value.

[0020] Preferably, after the slave communication device sends the received synchronization frame to the downstream device through the downlink and contains it in the third signal, the local clock generation module sets the frequency of the second local clock to a second preset frequency value, and then the frequency of the second local clock changes according to a second preset frequency curve.

[0021] Preferably, the slave communication device is an integrated circuit chip, the local clock generation module generates the second local clock according to a local reference clock, and the local reference clock is generated by a crystalless reference clock generation circuit on the integrated circuit chip.

[0022] Preferably, the slave communication device further comprises a data frame synchronization signal recovery module, the synchronization frame contains data frame synchronization signal information, and the data frame synchronization signal recovery module recovers the data frame synchronization signal according to the received synchronization frame.

[0023] As a spread spectrum clock-based communication system of the present application, it comprises a first communication device and a second communication device, the first communication device is connected with the second communication device through a communication link, the first communication device comprises a downstream device interface module, which sends a first signal to the second communication device through the communication link and receives a second signal from the second communication device through the communication link, the second communication device comprises an upstream device interface module, which sends the second signal to the first communication device through the communication link and receives the first signal from the first communication device through the communication link, the first signal and the second signal are transmitted on the communication link at different times, the first communication device and the second communication device further respectively comprise a local clock generation module, the clock for sending the first signal by the first communication device is a first communication device local clock generated by the local clock generation module comprised by the first communication device, the clock for sending the second signal by the second communication device is a second communication device local clock generated by the local clock generation module comprised by the second communication device, the first communication device local clock is a spread spectrum clock, the first signal comprises a synchronization frame, the second communication device receives the synchronization frame, after the first communication device sends the synchronization frame, the local clock generation module comprised by the first communication device sets the frequency of the first communication device local clock to a first communication device preset frequency value.

[0024] Preferably, after the first communication device sends the synchronization frame, the local clock generation module comprised by the first communication device sets the frequency of the first communication device local clock to a first communication device preset frequency value, and then the frequency of the first communication device local clock changes according to a first communication device preset frequency curve.

[0025] Preferably, the second communication device local clock is a spread spectrum clock, after the second communication device receives the synchronization frame, the local clock generation module comprised by the second communication device sets the frequency of the second communication device local clock to a second communication device preset frequency value.

[0026] Further, after the second communication device receives the synchronization frame, the local clock generation module comprised by the second communication device sets the frequency of the second communication device local clock to a second communication device preset frequency value, and then the frequency of the second communication device local clock changes according to a second communication device preset frequency curve.

[0027] Preferably, the first communication device is a master communication device, and the second communication device is a slave communication device.

[0028] Preferably, the first communication device and the second communication device are both slave communication devices.

[0029] Preferably, the second communication device comprises a data frame synchronization signal recovery module, the synchronization frame comprises data frame synchronization signal information, and the data frame synchronization signal recovery module of the second communication device recovers the data frame synchronization signal according to the received synchronization frame. Attached Figure Description

[0030] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0031] Figure 1 is a schematic diagram of a communication system based on spread spectrum clock according to the present invention;

[0032] Figure 2 is a structural block diagram of a main communication device in the communication system based on spread spectrum clock of the present invention;

[0033] Figure 3 is a structural block diagram of another main communication device of the communication system based on spread spectrum clock according to the present invention;

[0034] Figure 4 is a timing diagram of the synchronization frame and the frequency curve of the spread spectrum clock in the communication system based on the spread spectrum clock of the present invention;

[0035] Figure 5 is another timing diagram of the synchronization frame and spread spectrum clock frequency curve in the communication system based on spread spectrum clock of the present invention;

[0036] Figure 6 is another timing diagram of the synchronization frame and spread spectrum clock frequency curve in the communication system based on spread spectrum clock of the present invention;

[0037] Figure 7 is a structural block diagram of a communication device in the communication system based on spread spectrum clock according to the present invention;

[0038] Figure 8 is a structural block diagram of another communication device in the communication system based on spread spectrum clock of the present invention;

[0039] Figure 9 is a schematic diagram of the first signal, the second signal, the third signal, and the fourth signal in the communication system based on spread spectrum clock of the present invention;

[0040] Figure 10 is a structural diagram of a data frame in the communication system based on spread spectrum clock according to the present invention;

[0041] Figure 11 is a master-slave structure diagram of the communication system based on spread spectrum clock of the present invention;

[0042] Figure 12 is a slave-slave structure diagram of the communication system based on spread spectrum clock of the present invention;

[0043] Figure 13 is a signal timing diagram of a method for recovering data frame synchronization signal in a communication system based on spread spectrum clock according to the present invention;

[0044] Figure 14 is a structural diagram of a synchronization frame in the communication system based on spread spectrum clock according to the present invention;

[0045] Figure 15 is a signal timing diagram of another method of recovering a data frame synchronization signal in a spread spectrum clock based communication system according to the present application;

[0046] Figure 16 is another structure of a synchronization frame in a spread spectrum clock based communication system according to the present application;

[0047] Figure 17 is a signal timing diagram of another method of recovering a data frame synchronization signal in a spread spectrum clock based communication system according to the present application;

[0048] Figure 18 is another structure of a synchronization frame in a spread spectrum clock based communication system according to the present application;

[0049] Figure 19 is a signal timing diagram of another method of recovering a data frame synchronization signal in a spread spectrum clock based communication system according to the present application.

[0050] Wherein: 10: master communication device 11: slave communication device 100: downstream device interface module in master communication device 101: local clock generation module in master communication device 102: host interface module 103: data frame synchronization signal generation module 110: upstream device interface module 111: local clock generation module in slave communication device 112: peripheral interface module 113: data frame synchronization signal recovery module 114: downstream device interface module in slave communication device DETAILED DESCRIPTION

[0051] In order to make the above and other features and advantages of the present application more comprehensible, the present application will be further described below with reference to the accompanying drawings. It should be understood that the specific embodiments given herein are intended for explanatory purposes only and are not intended to limit the present application.

[0052] As shown in Figure 1, as one spread spectrum clock based communication system according to the present application, it comprises one master communication device and one or more slave communication devices, wherein the master communication device can be optionally connected to a host computer, and the rest of the communication devices are slave communication devices. Each communication device is connected in a chain topology, wherein the master communication device is connected to the first slave communication device through a communication link, the first slave communication device is connected to the second slave communication device through a communication link, and so on, until the last slave communication device is connected to the penultimate slave communication device through a communication link.

[0053] In the present application, the slave communication devices are divided into end slave communication devices and non-end slave communication devices, wherein the last slave communication device is called an end slave communication device, and the rest of the slave communication devices are called non-end slave communication devices.

[0054] The direction from the master communication device to the slave communication device is called downstream direction, and the direction from the slave communication device to the master communication device is called upstream direction. For a specified communication device, the communication device connected through a communication link in the downstream direction is called the downstream device of the specified communication device, and the communication link is called the downstream link of the specified communication device. For a specified communication device, the communication device connected through a communication link in the upstream direction is called the upstream device of the specified communication device, and the communication link is called the upstream link of the specified communication device.

[0055] The master communication device has no upstream device and upstream link, but has downstream device and downstream link, and the downstream device is a slave communication device. The slave communication device has no downstream device and downstream link, but has upstream device and upstream link, and the upstream device can be a master communication device or a slave communication device. If there is no non-end slave communication device, the upstream device is a master communication device. If there is non-end slave communication device, the upstream device is a slave communication device. The non-end slave communication device has both upstream device and upstream link, and downstream device and downstream link, and the upstream device can be a master communication device or a slave communication device, and the downstream device is a slave communication device.

[0056] A communication link is the downstream link of the communication device connected in the upstream direction, and a communication link is the upstream link of the communication device connected in the downstream direction.

[0057] Fig. 2 is an embodiment of the master communication device 10 in the present application, which includes a downstream device interface module 100 and a local clock generation module 101. The downstream device interface module 100 is connected to the downstream device through the downstream link. The downstream device interface module 100 sends the first signal to the downstream device through the downstream link, and the downstream device sends the second signal. The downstream device interface module 100 receives the second signal from the downstream device through the downstream link. The local clock generation module 101 of the master communication device 10 generates the local clock clock0, and the clock of the first signal sent by the downstream device interface module 100 is the local clock clock0. The first signal contains the synchronization frame, and the downstream device interface module 100 sends the synchronization frame.

[0058] The host interface module 102 receives a data frame synchronization signal from the host. The synchronization frame contains the data frame synchronization signal information, and the downstream device can recover the data frame synchronization signal from the synchronization frame. The first signal can also contain first data frames. The host interface module 102 receives data from the host, and the downstream device interface module 100 sends some or all of the data in the first data frames to the downstream device. The second signal can also contain second data frames. The downstream device interface module 100 receives the second data frames, and the host interface module 102 sends some or all of the data in the second data frames to the host. The first signal and the second signal are transmitted on the downstream link of the host communication device 10 at different times.

[0059] Figure 3 is another embodiment of the master communication device 10 in the present application, which includes a downstream device interface module 100, a local clock generation module 101, a host interface module 102, and a data frame synchronization signal generation module 103. The downstream device interface module 100 is connected to a downstream device through a downstream link. The downstream device interface module 100 sends a first signal to the downstream device through the downstream link. The downstream device sends a second signal. The downstream device interface module 100 receives the second signal from the downstream device through the downstream link. The local clock generation module 101 of the master communication device 10 generates a local clock clock0. The clock for sending the first signal by the downstream device interface module 100 is the local clock clock0. The data frame synchronization signal generation module 103 generates a data frame synchronization signal. The host interface module 102 is connected to a host. The host interface module 102 sends the data frame synchronization signal to the host. The first signal includes a synchronization frame. The downstream device interface module 100 sends the synchronization frame. The synchronization frame includes the data frame synchronization signal information. The downstream device can recover the data frame synchronization signal according to the synchronization frame. The first signal can also include a first data frame. The host can select to generate data based on the data frame synchronization signal. The host interface module 102 receives the data from the host. The downstream device interface module 100 sends part or all of the data in the first data frame to the downstream device. The second signal can also include a second data frame. The downstream device interface module 100 receives the second data frame. The host interface module 102 sends part or all of the data in the second data frame to the host. The first signal and the second signal are transmitted in time division on the downstream link of the master communication device 10. In the embodiment shown in Figure 3, the master communication device 10 can also only include the downstream device interface module 100, the local clock generation module 101, and the data frame synchronization signal generation module 103, but not the host interface module 102 and the host connected thereto. The downstream device interface module 100 is connected to a downstream device through a downstream link. The downstream device interface module 100 sends a first signal to the downstream device through the downstream link. The downstream device sends a second signal. The downstream device interface module 100 receives the second signal from the downstream device through the downstream link. The local clock generation module 101 of the master communication device 10 generates a local clock clock0. The clock for sending the first signal by the downstream device interface module 100 is the local clock clock0. The data frame synchronization signal generation module 103 generates a data frame synchronization signal. The first signal includes a synchronization frame. The downstream device interface module 100 sends the synchronization frame. The synchronization frame includes the data frame synchronization signal information. The downstream device can recover the data frame synchronization signal according to the synchronization frame. The first signal can also include a first data frame. The master communication device 10 can select to generate data based on the data frame synchronization signal. The master communication device 10 sends the data it generates in the first data frame to the downstream device. The second signal can also include a second data frame. The downstream device interface module 100 receives the second data frame. The master communication device 10 can process the data included in the second data frame it receives.The first signal and the second signal are transmitted in time division on a downlink of the master communication device 10.

[0060] For the master communication device 10 in FIG. 2 and FIG. 3, the second signal can also include a synchronization response frame. After the master communication device 10 transmits the synchronization frame included in the first signal, different embodiments of the master communication device 10 can choose to transmit or not to transmit any data to the downstream device within a preset time. The master communication device 10 can determine the state of its downlink according to whether the synchronization response frame is received within the preset time after transmitting the synchronization frame included in the first signal.

[0061] For the master communication device 10 in FIG. 2 and FIG. 3, the local clock generation module 101 generates the local clock clock0 according to a local reference clock. The local reference clock generation circuit (not shown in FIG. 2 and FIG. 3) is generally based on a quartz crystal to achieve high frequency accuracy. However, when the master communication device 10 is an integrated circuit chip, the local reference clock can also be generated by a crystal-free reference clock generation circuit on the integrated circuit chip to eliminate the quartz crystal and reduce the cost and size. The present application does not limit the implementation method of the local clock generation module 101. A commonly used implementation method of the local clock generation module 101 is a phase-locked loop circuit (PLL).

[0062] In the embodiments shown in FIG. 2 and FIG. 3, the local clock clock0 is a spread spectrum clock. As shown in FIG. 4, after the downstream device interface module 100 transmits the synchronization frame, the master communication device 10 sets the frequency of the local clock clock0 to a preset frequency value f0, and then the frequency of the local clock clock0 changes according to a preset frequency curve wave0. As shown in FIG. 4, the preset frequency curve wave0 is a triangular wave, and the frequency of the triangular wave is the same as the frame frequency of the synchronization frame, that is, the frequency of the local clock clock0 reaches the preset frequency value f0 exactly after the downstream device interface module 100 transmits the synchronization frame.

[0063] In actual applications, the frequency of the triangular wave can be different from the frame frequency of the synchronization frame. In one embodiment, as shown in FIG. 5, the frequency of the triangular wave is less than the frame frequency of the synchronization frame, and the frequency of the local clock clock0 has not reached the preset frequency value f0 after the downstream device interface module 100 transmits the synchronization frame. The master communication device 10 sets the frequency of the local clock clock0 to the preset frequency value f0. In another embodiment, as shown in FIG. 6, the frequency of the triangular wave is greater than the frame frequency of the synchronization frame, and the frequency of the local clock clock0 has reached the preset frequency value f0 and continues to change according to the preset frequency curve wave0 after the downstream device interface module 100 transmits the synchronization frame. The master communication device 10 sets the frequency of the local clock clock0 to the preset frequency value f0.

[0064] With the above method, the deviation between the frequency of the triangular wave and the frame frequency of the synchronization frame does not accumulate, and after the downstream device interface module 100 sends a synchronization frame, the frequency of the local clock clock0 starts to change according to the preset frequency curve wave0 from the preset frequency value f0. After the downstream device of the main communication device 10 receives the synchronization frame, the downstream device can more accurately predict the data rate from the main communication device 10 received after the synchronization frame until the next synchronization frame is received according to the preset frequency value f0 and the preset frequency curve wave0, so as to adjust the parameters of a clock data recovery (CDR) circuit, thereby improving the reliability of received data and reducing the bit error rate. The CDR circuit can be implemented by using a phase-locked loop (PLL) based method.

[0065] The present application does not limit the preset frequency value f0 or the preset frequency curve wave0, and does not limit the implementation method of the CDR circuit. Any preset frequency value f0, any preset frequency curve wave0 or any implementation method of the CDR circuit is within the protection scope of the present application.

[0066] The present application can adjust the preset frequency curve according to the relationship between the preset frequency curve and the frame frequency of the synchronization frame. For example, in the embodiment shown in FIG. 5, the frequency of the triangular wave is less than the frame frequency of the synchronization frame, and after the downstream device interface module 100 sends a synchronization frame, the main communication device 10 sets the frequency of the local clock clock0 to the preset frequency value f0, and at the same time, the frequency of the triangular wave can be increased so that the frequency of the triangular wave is closer to the frame frequency of the synchronization frame. For another example, in the embodiment shown in FIG. 6, the frequency of the triangular wave is greater than the frame frequency of the synchronization frame, and after the downstream device interface module 100 sends a synchronization frame, the main communication device 10 sets the frequency of the local clock clock0 to the preset frequency value f0, and at the same time, the frequency of the triangular wave can be decreased so that the frequency of the triangular wave is closer to the frame frequency of the synchronization frame. In this way, after the downstream device of the main communication device 10 receives the synchronization frame, the downstream device can more accurately predict the data rate from the main communication device 10 received after the synchronization frame until the next synchronization frame is received according to the preset frequency value f0 and the preset frequency curve wave0, so as to more accurately adjust the parameters of a clock data recovery (CDR) circuit, thereby further improving the reliability of received data and reducing the bit error rate.

[0067] FIG. 7 is an embodiment of a slave communication device 11 in the present application, which is a terminal slave communication device, and includes an upstream device interface module 110 and a local clock generation module 111.

[0068] The upstream device interface module 110 is connected to the upstream device through the uplink, the upstream device sends the first signal, the upstream device interface module 110 receives the first signal from the upstream device through the uplink, and the upstream device interface module 110 sends the second signal to the upstream device through the uplink. The first local clock clock1 is generated by the local clock generation module 111 of the slave communication device 11, and the clock of the upstream device interface module 110 sending the second signal is the first local clock clock1. The first signal contains a synchronization frame, and the upstream device interface module 110 receives the synchronization frame.

[0069] In the embodiment shown in FIG. 7, the slave communication device 11 can further include a data frame synchronization signal recovery module 113 connected to the upstream device interface module 110. The synchronization frame contains data frame synchronization signal information, and the data frame synchronization signal recovery module 113 recovers the data frame synchronization signal according to the received synchronization frame.

[0070] In the embodiment shown in FIG. 7, the slave communication device 11 can further include a peripheral interface module 112 connected to an external device. The peripheral interface module 112 can select to communicate with the external device based on the data frame synchronization signal, including that the peripheral interface module 112 sends data to the external device based on the data frame synchronization signal, or receives data from the external device, or sends data to the external device and receives data from the external device. The peripheral interface module 112 communicating with the external device based on the data frame synchronization signal also includes the peripheral interface module 112 sending the data frame synchronization signal to the external device.

[0071] The first signal can further contain a first data frame, and the upstream device interface module 110 receives the first data frame. The peripheral interface module 112 sends part or all of the data in it to the external device. The second signal can further contain a second data frame, and the peripheral interface module 112 receives data from the external device. The upstream device interface module 110 sends part or all of the data in it to the upstream device in the second data frame. The first signal and the second signal are transmitted in time on the uplink of the slave communication device 11.

[0072] For the slave communication device 11 in FIG. 7, the second signal can further contain a synchronization response frame. After the upstream device interface module 110 receives the synchronization frame in the first signal, the synchronization response frame is sent to the upstream device within a predetermined time. In an embodiment, the slave communication device 11 sends the synchronization response frame to the upstream device earlier than any other data sent to the upstream device, for example, the predetermined time can be set to the slave communication device 11 sending the synchronization response frame to the upstream device immediately after receiving the synchronization frame in the first signal, which is earlier than any other data sent to the upstream device.

[0073] As shown in Fig. 7, the slave communication device 11 further comprises a local clock generating module 111. The local clock generating module 111 generates a first local clock clockl according to a local reference clock. The local reference clock generating circuit (not shown in Fig. 7) is generally based on a quartz crystal to achieve high frequency accuracy. However, when the slave communication device 11 is an integrated circuit chip, the local reference clock can also be generated by a crystalless reference clock generating circuit on the integrated circuit chip to eliminate the quartz crystal and reduce the cost and size. The present application does not limit the implementation method of the local clock generating module 111. A commonly used implementation method of the local clock generating module 111 is a phase-locked loop circuit (PLL).

[0074] Fig. 8 is another embodiment of the slave communication device 11 in the present application. The slave communication device is a non-terminal slave communication device, which comprises an upstream device interface module 110, a downstream device interface module 114, and a local clock generating module 111. The upstream device interface module 110 is connected to an upstream device through an uplink. The upstream device transmits a first signal. The upstream device interface module 110 receives the first signal from the upstream device through the uplink. The upstream device interface module 110 transmits a second signal to the upstream device through the uplink. The first signal comprises a synchronization frame. The upstream device interface module 110 receives the synchronization frame.

[0075] The downstream device interface module 114 is connected to a downstream device through a downlink. The downstream device interface module 114 transmits a third signal to the downstream device through the downlink. The downstream device interface module 114 receives a fourth signal from the downstream device through the downlink. The local clock generating module 111 of the slave communication device 11 generates a first local clock clockl and a second local clock clock2. The clock of the second signal transmitted by the upstream device interface module 110 is the first local clock clockl. The clock of the third signal transmitted by the downstream device interface module 114 is the second local clock clock2. The third signal comprises a synchronization frame. The downstream device interface module 114 transmits the synchronization frame contained in the first signal to the downstream device through the downlink as a synchronization frame contained in the third signal. The first signal and the second signal are transmitted in time division on the uplink of the slave communication device 11. The third signal and the fourth signal are transmitted in time division on the downlink of the slave communication device 11.

[0076] In the embodiment shown in Fig. 8, the slave communication device 11 can further comprise a data frame synchronization signal recovery module 113. The data frame synchronization signal recovery module 113 is connected to the upstream device interface module 110. The synchronization frame contains data frame synchronization signal information. The data frame synchronization signal recovery module 113 recovers the data frame synchronization signal according to the received synchronization frame.

[0077] In the slave communication device 11 shown in FIG. 8, the peripheral interface module 112 is connected to the external device, and the peripheral interface module 112 can selectively communicate with the external device based on the data frame synchronization signal, including that the peripheral interface module 112 transmits data to the external device based on the data frame synchronization signal, or receives data from the external device based on the data frame synchronization signal, or transmits data to the external device and receives data from the external device based on the data frame synchronization signal, and the communication between the peripheral interface module 112 and the external device based on the data frame synchronization signal also includes that the peripheral interface module 112 transmits the data frame synchronization signal to the external device. As shown in the slave communication device 11 in FIG. 8, the local clock generation module 111 generates the first local clock clock1 and the second local clock clock2 based on the local reference clock. The local reference clock generation circuit (not shown in FIG. 8) is generally based on a quartz crystal to achieve high frequency accuracy. However, when the slave communication device 11 is an integrated circuit chip, the local reference clock can also be generated by a crystalless reference clock generation circuit on the integrated circuit chip to eliminate the quartz crystal and reduce the cost and size. The present application does not limit the implementation method of the local clock generation module 111, and the commonly used implementation method of the local clock generation module 111 is a phase-locked loop circuit (PLL).

[0078] Simple variations and combinations of the embodiments shown in the present application are also within the scope of the present application. For example, in the embodiment shown in FIG. 8, clock1 and clock2 can be the same clock, that is, the upstream device interface module 110 and the downstream device interface module 114 can transmit the second signal and the third signal based on the same clock, or clock1 and clock2 can be generated by two different local clock generation modules 111, based on the same local reference clock or based on two different local reference clocks respectively.

[0079] For the slave communication device 11 in FIG. 8, the fourth signal can contain a synchronization response frame. After the slave communication device 11 transmits the synchronization frame contained in the third signal, the state of the downlink can be determined according to whether the synchronization response frame contained in the fourth signal is received within a predetermined time.

[0080] For the slave communication device 11 in FIG. 8, the second signal can contain a synchronization response frame. After the upstream device interface module 110 receives the synchronization frame in the first signal, the upstream device sends a synchronization response frame within a predetermined time. In an embodiment, the slave communication device 11 sends the synchronization response frame to the upstream device earlier than any other data sent to the upstream device, for example, the predetermined time can be set to the slave communication device 11 sending the synchronization response frame to the upstream device immediately after receiving the synchronization frame in the first signal, earlier than any other data sent to the upstream device.

[0081] In the present application, the time at which the upstream device interface module 110 sends the synchronization response frame to the upstream device is independent of whether and when the downstream device interface module 114 receives the synchronization response frame in the fourth signal, and is also independent of whether and when the downstream device interface module 114 receives any other data in the fourth signal.

[0082] In the embodiments shown in FIG. 7 and FIG. 8, the first local clock clockl can be a spread spectrum clock. When the first local clock clockl is a spread spectrum clock, as shown in FIG. 4, after the upstream device interface module 110 receives the synchronization frame, the frequency of the first local clock clockl is set to the preset frequency value fl from the communication device 11, and then the frequency of the first local clock clockl varies according to the preset frequency curve wave 1. As shown in FIG. 4, the preset frequency curve wave 1 is a triangular wave, and the frequency of the triangular wave is the same as the frame frequency of the synchronization frame, that is, after the upstream device interface module 110 receives the synchronization frame, the frequency of the first local clock clockl reaches the preset frequency value fl.

[0083] In actual applications, the frequency of the triangular wave can be different from the frame frequency of the synchronization frame. In one embodiment, as shown in FIG. 5, the frequency of the triangular wave is less than the frame frequency of the synchronization frame, and after the upstream device interface module 110 receives the synchronization frame, the frequency of the first local clock clockl has not yet reached the preset frequency value fl, and the frequency of the first local clock clockl is set to the preset frequency value fl from the communication device 11. In another embodiment, as shown in FIG. 6, the frequency of the triangular wave is greater than the frame frequency of the synchronization frame, and after the upstream device interface module 110 receives the synchronization frame, the frequency of the first local clock clockl has reached the preset frequency value fl and continues to vary according to the preset frequency curve wave 1, and the frequency of the first local clock clockl is set to the preset frequency value fl from the communication device 11.

[0084] By using the above method, the deviation between the frequency of the triangular wave and the frame frequency of the synchronization frame will not accumulate, and after the upstream device interface module 110 receives the synchronization frame each time, the frequency of the first local clock clockl starts to vary according to the preset frequency curve wave 1 from the preset frequency value fl. After the upstream device of the communication device 11 sends the synchronization frame, the data rate received from the communication device 11 after sending the synchronization frame until sending the next synchronization frame can be more accurately predicted according to the preset frequency value fl and the preset frequency curve wave 1, so that the parameters of the clock data recovery (CDR) circuit are adjusted, and the reliability of the received data is improved, and the bit error rate is reduced.

[0085] In the embodiment shown in Fig. 8, the second local clock clock2 can be a spread spectrum clock. When the second local clock clock2 is a spread spectrum clock, as shown in Fig. 4, after the downstream device interface module 114 sends a synchronization frame, the frequency of the second local clock clock2 is set to the preset frequency value f2 from the communication device 11, and then the frequency of the second local clock clock2 varies according to the preset frequency curve wave2. As shown in Fig. 4, the preset frequency curve wave2 is a triangular wave, and the frequency of the triangular wave is the same as the frame frequency of the synchronization frame, that is, after the downstream device interface module 114 sends a synchronization frame, the frequency of the second local clock clock2 reaches the preset frequency value f2.

[0086] In actual applications, the frequency of the triangular wave can be different from the frame frequency of the synchronization frame, or the frame frequency of the synchronization frame can change. In one embodiment, as shown in Fig. 5, the frequency of the triangular wave is less than the frame frequency of the synchronization frame, and after the downstream device interface module 114 sends a synchronization frame, the frequency of the second local clock clock2 has not reached the preset frequency value f2, and the frequency of the second local clock clock2 is set to the preset frequency value f2 from the communication device 11. In another embodiment, as shown in Fig. 6, the frequency of the triangular wave is greater than the frame frequency of the synchronization frame, and after the downstream device interface module 114 sends a synchronization frame, the frequency of the second local clock clock2 has reached the preset frequency value f2 and continues to vary according to the preset frequency curve wave2, and the frequency of the second local clock clock2 is set to the preset frequency value f2 from the communication device 11.

[0087] Using the above method, the deviation between the frequency of the triangular wave and the frame frequency of the synchronization frame will not accumulate, and after the downstream device interface module 114 sends a synchronization frame each time, the frequency of the second local clock clock2 starts to vary according to the preset frequency curve wave2 from the preset frequency value f2. After receiving a synchronization frame, the downstream device of the communication device 11 can accurately predict the data rate received from the communication device 11 from after receiving the synchronization frame to before receiving the next synchronization frame according to the preset frequency value f2 and the preset frequency curve wave2, so as to adjust the parameters of the clock data recovery (CDR) circuit, thereby improving the reliability of received data and reducing the bit error rate. The present application does not limit the preset frequency values f1, f2 or the preset frequency curves wave1, wave2, nor does it limit the implementation method of the CDR circuit. Using any preset frequency values f1, f2, any preset frequency curves wave1, wave2, or any implementation method of the CDR circuit is within the protection scope of the present application.

[0088] For a slave communication device 11 (as shown in FIG. 7 and FIG. 8), the first signal and the second signal are transmitted on its uplink in time division manner, the first signal contains a synchronization frame and can also contain a first data frame, the second signal can contain a synchronization response frame and can also contain a second data frame. For a slave communication device 11 when it contains a downstream device interface module 114 (as shown in FIG. 8), the third signal and the fourth signal are transmitted on its downlink in time division manner, the third signal contains a synchronization frame and can also contain a third data frame, the fourth signal can contain a synchronization response frame and can also contain a fourth data frame, as shown in FIG. 9.

[0089] The slave communication device 11 (as shown in FIG. 7 and FIG. 8) receives the first signal from its upstream device, i.e. receives the synchronization frame contained in the first signal and the first data frame, and sends the second signal to its upstream device, i.e. sends the synchronization response frame contained in the second signal and the second data frame. When a slave communication device 11 contains a downstream device interface module 114 (as shown in FIG. 8), it sends the third signal to the downstream device, i.e. sends the synchronization frame contained in the third signal and the third data frame, and receives the fourth signal from the downstream device, i.e. receives the synchronization response frame and the fourth data frame.

[0090] For a master communication device 10 (as shown in FIG. 2 and FIG. 3), the first signal and the second signal are transmitted on its downlink in time division manner, the first signal contains a synchronization frame and can also contain a first data frame, the second signal can contain a synchronization response frame and can also contain a second data frame, as shown in FIG. 9.

[0091] The master communication device 10 (as shown in FIG. 2 and FIG. 3) receives the second signal from its downstream device, i.e. receives the synchronization response frame contained in the second signal and the second data frame, and sends the first signal to its downstream device, i.e. sends the synchronization frame contained in the first signal and the first data frame.

[0092] In the present application, the slave communication device 11 as shown in FIG. 8, after receiving the synchronization frame contained in the first signal from the upstream device, forwards the received synchronization frame contained in the third signal to the downstream device, as shown in FIG. 9. In the process of forwarding, the slave communication device 11 in the present application can choose to modify the content of the synchronization frame.

[0093] Because the first signal and the second signal are transmitted on the same communication link in time division manner, in order to avoid conflict, a certain time interval should be maintained between the transmission of the first signal (i.e. the transmission of the synchronization frame and the first data frame contained in the first signal) and the transmission of the second signal (i.e. the transmission of the synchronization response frame and the second data frame contained in the second signal), such as the time interval between the synchronization frame contained in the first signal and the synchronization response frame contained in the second signal as shown in FIG. 9, or the time interval between the synchronization response frame contained in the second signal and the first data frame contained in the first signal as shown in FIG. 9.

[0094] Because the third signal and the fourth signal are transmitted in time division on the same communication link, to avoid conflict, a time interval should be kept between the transmission of the third signal (i.e. the transmission of the synchronization frame and the third data frame contained in the third signal) and the transmission of the fourth signal (i.e. the transmission of the synchronization response frame and the fourth data frame contained in the fourth signal), such as the time interval between the synchronization frame contained in the third signal and the synchronization response frame contained in the fourth signal as shown in Fig. 9, or the time interval between the synchronization response frame contained in the fourth signal and the third data frame contained in the third signal as shown in Fig. 9.

[0095] In the present application, the multiple data frames contained in the same first signal, second signal, third signal or fourth signal can be transmitted continuously or discontinuously, such as the two first data frames contained in the first signal are transmitted continuously without time interval in between, and the two third data frames contained in the third signal are transmitted discontinuously with time interval in between as shown in Fig. 9.

[0096] For a slave communication device 11 (as shown in Fig. 7 and Fig. 8), which can choose to send a synchronization response frame within a preset time after receiving the synchronization frame contained in the first signal, as shown in Fig. 9, the slave communication device 11 sends a synchronization response frame after receiving the synchronization frame contained in the first signal, and the time of sending the synchronization response frame is within the preset time and earlier than any other data sent by the slave communication device 11 to the upstream device. The time of sending the synchronization response frame by the slave communication device 11 is independent of whether and when the downstream device interface module 114 receives the synchronization response frame in the fourth signal, and is also independent of whether and when the downstream device interface module 114 receives any other data in the fourth signal.

[0097] For a master communication device 10 (as shown in Fig. 2 and Fig. 3), which can choose to send or not to send any data to the downstream device within a preset time after sending the synchronization frame contained in the first signal. As shown in Fig. 9, the master communication device 10 sends the first signal, the slave communication device 11 (as shown in Fig. 7 and Fig. 8) receives the first signal and sends the second signal, and the master communication device 10 does not send any data to the downstream device within the preset time after sending the synchronization frame contained in the first signal, i.e. does not send the first data frame contained in the first signal within the preset time, and the slave communication device 11 sends a synchronization response frame within the preset time after receiving the synchronization frame contained in the first signal, and the time of sending the synchronization response frame is earlier than the time of sending the first data frame contained in the first signal by the master communication device 10.

[0098] The first data frame, the second data frame, the third data frame and the fourth data frame are collectively referred to as data frames in the present application. The present application does not limit the structure and processing method of the data frames. As a structure and processing method of the data frames, as shown in FIG. 10, the data frame includes a data frame header and a data field. Each communication device uses the data frame header to identify the data frame. The data field includes a plurality of data slots for carrying data payloads. Each communication device can add or delete a data slot, and can initialize, replace or empty the data payload in the data slot. Each communication device can be allocated one or more data slots. When the communication device needs to send data, the data payload can be placed in the corresponding data slot in the data frame, or a data slot of the data frame can be added and the data payload can be placed in the data slot. When the communication device needs to receive data, the data payload can be read out from the corresponding data slot, or the data slot can be deleted from the data frame after the data payload is read out from the corresponding data slot. When the communication device needs to send and receive data, the data payload can be read out from the corresponding data slot, and the data payload in the data slot can be replaced.

[0099] As shown in FIGS. 7 and 8, the first data frame can be received from the communication device 11, and part or all of the data contained in the first data frame can be sent to the external device.

[0100] As shown in FIGS. 7 and 8, data can be received from the external device by the communication device 11, and part or all of the data can be contained in the second data frame and sent to the upstream device.

[0101] As shown in FIG. 8, the first data frame can be received from the communication device 11, and part or all of the data contained in the first data frame can be contained in the third data frame and sent to the downstream device.

[0102] As shown in FIG. 8, data can be received from the external device by the communication device 11, and part or all of the data can be contained in the third data frame and sent to the downstream device.

[0103] As shown in FIG. 8, the first data frame can be received from the communication device 11, and data can be received from the external device by the communication device 11. Part or all of the data contained in the first data frame and part or all of the data received from the external device by the communication device 11 can be contained in the third data frame and sent to the downstream device by the communication device 11.

[0104] As shown in FIG. 8, the fourth data frame can be received from the communication device 11, and part or all of the data contained in the fourth data frame can be sent to the external device.

[0105] As shown in FIG. 8, the fourth data frame can be received from the communication device 11, and part or all of the data contained in the fourth data frame can be contained in the second data frame and sent to the upstream device.

[0106] As shown in Fig. 8, the fourth data frame can be received from the slave communication device 11, and the slave communication device receives data from the external device, and the slave communication device sends the second data frame containing part or all of the data contained in the fourth data frame and part or all of the data received from the external device to the upstream device.

[0107] The present application does not limit the encoding method of the first signal, the second signal, the third signal and the fourth signal. In one embodiment of the present application, the first signal, the second signal, the third signal and the fourth signal can use an encoding method with clock information, such as 8b / 10b, 4b / 5b, Manchester encoding, etc.

[0108] For a slave communication device 11 (as shown in Fig. 7 and Fig. 8), the clock of the first signal sent by the upstream device is the local clock generated by the upstream device, and the clock of the second signal sent by the slave communication device 11 is the first local clock clock1 generated by the slave communication device 11. The local clock generated by the upstream device and the first local clock clock1 generated by the slave communication device 11 are not of the same source, i.e. the upstream device and the slave communication device 11 use their own local reference clock respectively, so the local clock generated by the upstream device and the first local clock clock1 generated by the slave communication device 11 are asynchronous clocks, and the first local clock clock1 generated by the slave communication device 11 is not locked to the first signal rate sent by the upstream device. For a slave communication device 11 (as shown in Fig. 8), the clock of the fourth signal sent by the downstream device is the local clock generated by the downstream device, and the clock of the third signal sent by the slave communication device 11 is the second local clock clock2 generated by the slave communication device 11. The local clock generated by the downstream device and the second local clock clock2 generated by the slave communication device 11 are not of the same source, i.e. the downstream device and the slave communication device 11 use their own local reference clock respectively, so the local clock generated by the downstream device and the second local clock clock2 generated by the slave communication device 11 are asynchronous clocks, and the second local clock clock2 generated by the slave communication device 11 is not locked to the fourth signal rate sent by the downstream device.

[0109] For a master communication device 10 (as shown in Fig. 2 and Fig. 3), the clock of the second signal sent by the downstream device is the local clock generated by the downstream device, and the clock of the first signal sent by the master communication device 10 is the local clock clock0 generated by the master communication device 10. The local clock generated by the downstream device and the local clock clock0 generated by the master communication device 10 are not of the same source, i.e. the downstream device and the master communication device 10 use their own local reference clock respectively, so the local clock generated by the downstream device and the local clock clock0 generated by the master communication device 10 are asynchronous clocks, and the local clock clock0 generated by the master communication device 10 is not locked to the second signal rate sent by the downstream device.

[0110] The clock and data recovery circuit (CDR) can be used to receive the encoded first signal or the fourth signal. The CDR circuit is a common oversampling receiving circuit. The application does not specify the selection of the CDR circuit. Any applicable CDR circuit can be used to receive the first signal or the fourth signal.

[0111] As shown in FIG. 11 and FIG. 12, the communication system is an embodiment of the application based on spread spectrum clock (master-slave structure). The communication system includes a first communication device and a second communication device. The first communication device and the second communication device are connected through a communication link. The first communication device is an upstream device of the second communication device. The second communication device is a downstream device of the first communication device. The first communication device can be a master communication device (as shown in FIG. 11) or a slave communication device (as shown in FIG. 12). The second communication device is a slave communication device. If the second communication device is a slave non-terminal communication device, the second communication device is also connected to its downstream device through a downstream link.

[0112] The first communication device sends a first signal to the second communication device through a downstream link and receives a second signal from the second communication device through the downstream link. The second communication device sends the second signal to the first communication device through an upstream link and receives the first signal from the first communication device through the upstream link. The first signal and the second signal are transmitted on the downstream link of the first communication device at different times. The first signal includes a synchronization frame and can also include a first data frame. The second signal can include a synchronization response frame and can also include a second data frame.

[0113] If the second communication device is a slave non-terminal communication device, the second communication device sends a third signal to its downstream device through a downstream link and receives a fourth signal from its downstream device through the downstream link. The third signal and the fourth signal are transmitted on the downstream link of the second communication device at different times. The third signal includes a synchronization frame and can also include a third data frame. The fourth signal can include a synchronization response frame and can also include a fourth data frame.

[0114] In the embodiment shown in FIG. 11, the first communication device is a master communication device. The master communication device shown in FIG. 11 is the same as the master communication device 10 shown in FIG. 2 and FIG. 3 and the related description above. Therefore, the description is not repeated here.

[0115] In the embodiment shown in FIG. 12, the first communication device is a slave communication device. The slave communication device shown in FIG. 12 is the same as the slave communication device 11 shown in FIG. 7 and FIG. 8 and the related description above. Therefore, the description is not repeated here.

[0116] In the present application, the slave communication device 11 receives the synchronization frame from its upstream device, and the synchronization frame can contain the data frame synchronization signal information, and the slave communication device 11 recovers the data frame synchronization signal according to the synchronization frame.

[0117] In the present application, the synchronization frame is initially sent by the master communication device 10 to its downstream device (the downstream device of the master communication device 10 is the slave communication device 11), and the slave communication device 11 receives the synchronization frame from its upstream device (the upstream device of the slave communication device 11 is the master communication device 10 or the slave communication device 11), in an embodiment of the master communication device 10 as shown in Fig. 2, the host interface module 102 is connected to the host, and the host interface module 102 receives the data frame synchronization signal as shown in Fig. 13 and Fig. 15 from the host, in another embodiment of the master communication device 10 as shown in Fig. 3, the master communication device 10 contains the data frame synchronization signal generation module 103, and the data frame synchronization signal generation module 103 generates the data frame synchronization signal as shown in Fig. 13 and Fig. 15.

[0118] In the present application, the synchronization frame is initially sent by the master communication device 10, and the slave communication device 11 receives and forwards the synchronization frame, and the synchronization frame contains the data frame synchronization signal information, including: the ratio of the frame frequency of the synchronization frame to the frequency of the data frame synchronization signal is M / N, wherein M and N are both positive integers, that is, the frame frequency of the synchronization frame is locked to the frequency of the data frame synchronization signal according to the ratio of M / N, and the data frame synchronization signal recovery module 113 (contained in the slave communication device 11) recovers the data frame synchronization signal according to the time sequence signal received by the synchronization frame. Several values of M and N are given as follows: when M=1 and N=1, the frame frequency of the synchronization frame is the same as the frequency of the data frame synchronization signal, that is, for each data frame synchronization signal pulse, one synchronization frame is sent, when M=1 and N=2, the frame frequency of the synchronization frame is half of the frequency of the data frame synchronization signal, that is, for every two data frame synchronization signal pulses, one synchronization frame is sent, when M=2 and N=1, the frame frequency of the synchronization frame is twice the frequency of the data frame synchronization signal, that is, for each data frame synchronization signal pulse, two synchronization frames are sent.

[0119] As shown in the embodiment of Fig. 13, an implementation method of recovering the data frame synchronization signal from the synchronization frame is given. The data frame synchronization signal shown in Fig. 13 is the data frame synchronization signal used by the master communication device 10 to send the synchronization frame, and the ratio of the frame frequency of the synchronization frame to the frequency of the data frame synchronization signal is M / N, in this example, M=1, N=2, i.e. the frame frequency of the synchronization frame is half of the frequency of the data frame synchronization signal. The data frame synchronization signal recovered from the communication device 11 (indicated as the data frame synchronization signal recovered from the communication device in Fig. 13) is recovered from the synchronization frame timing signal (the synchronization frame timing signal generated after the synchronization frame is received) received by the communication device 11. In one embodiment, after the synchronization frame is received by the communication device 11, the synchronization frame timing signal is generated, and the synchronization frame timing signal can be sent to a phase-locked loop circuit (included in the data frame synchronization signal recovery module 113) to generate a high frequency clock. If the frequency of the high frequency clock is K times the frequency of the synchronization frame timing signal, the high frequency clock is counted by the communication device 11, in this embodiment, the count value is 0 when the synchronization frame timing signal is high, and the count value is counted from 0 to the maximum value K-1 and loops. The communication device 11 generates a high level pulse of the data frame synchronization signal when the count value is n1 and (K / 2)+n1, thereby recovering the data frame synchronization signal (indicated as the data frame synchronization signal recovered from the communication device in Fig. 13). The frequency of the recovered data frame synchronization signal is twice the frame frequency of the synchronization frame, equal to the frequency of the data frame synchronization signal used by the master communication device 10 to send the synchronization frame. At the same time, because of the existence of the high frequency clock count value 0 to K-1, the recovered data frame synchronization signal can be selected to be output at a preset high frequency clock count value (phase) position, i.e. the delay of the recovered data frame synchronization signal relative to the synchronization frame timing signal can be selected. In other embodiments, the frequency of the recovered data frame synchronization signal can also be different from the frequency of the data frame synchronization signal used by the master communication device 10 to send the synchronization frame, for example, if the communication device 11 only generates a high level pulse of the data frame synchronization signal when the count value is n1, the frequency of the recovered data frame synchronization signal is equal to the frame frequency of the synchronization frame, which is half of the frequency of the data frame synchronization signal used by the master communication device 10 to send the synchronization frame. If the communication device 11 only generates a high level pulse of the data frame synchronization signal when the count value is n1, (K / 4)+n1, (K / 2)+n1, (3K / 4)+n1, the frequency of the recovered data frame synchronization signal is twice the frequency of the data frame synchronization signal used by the master communication device 10 to send the synchronization frame.

[0120] In the application, the synchronization frame can contain a serial number field. The synchronization frame contains data frame synchronization signal information, including: the ratio of the frame frequency of the synchronization frame to the frequency of the data frame synchronization signal is M / N, where M and N are positive integers, i.e. the frame frequency of the synchronization frame is locked to the frequency of the data frame synchronization signal at a ratio of M / N. The synchronization frame contains a serial number field, which contains the serial number of the synchronization frame. The data frame synchronization signal recovery module 113 (contained in the slave communication device 11) recovers the data frame synchronization signal according to the synchronization frame serial number field and the time sequence signal of the received synchronization frame.

[0121] As shown in the embodiment of FIG. 14, the synchronization frame contains a synchronization frame header and a serial number field. The slave communication device 11 uses the synchronization frame header to identify the synchronization frame. The serial number field contains the serial number of the synchronization frame, i.e. the count value of the synchronization frame.

[0122] As shown in the embodiment of FIG. 15, another implementation method for recovering the data frame synchronization signal according to the synchronization frame is given. The data frame synchronization signal shown in FIG. 15 is the data frame synchronization signal used by the master communication device 10 to send the synchronization frame. The ratio of the frame frequency of the synchronization frame to the frequency of the data frame synchronization signal is M / N. In this example, M=2 and N=1, i.e. the frame frequency of the synchronization frame is twice the frequency of the data frame synchronization signal, i.e. for each data frame synchronization signal pulse, two synchronization frames are sent. The serial number field contains the serial number count value of the synchronization frame, which is 0 to 3 and cycles back and forth. The slave communication device 11 recovers the data frame synchronization signal (indicated as the data frame synchronization signal recovered by the slave communication device in FIG. 15) according to the synchronization frame serial number field and the time sequence signal of the received synchronization frame (the synchronization frame time sequence signal generated after the synchronization frame is received),

[0123] In one embodiment, after receiving the synchronization frame from the communication device 11, a synchronization frame timing signal is generated, and the synchronization frame timing signal can be sent to a phase-locked loop circuit (included in the data frame synchronization signal recovery module 113) to generate a high frequency clock. If the frequency of the high frequency clock is K times the frequency of the synchronization frame timing signal, the high frequency clock is counted from the communication device 11. In this embodiment, the count value is 0 when the synchronization frame timing signal is high, and the count value is counted from 0 to the maximum value K-1 and loops. The communication device 11 generates a high level pulse of the data frame synchronization signal when the count is n1 and the synchronization frame sequence number is odd, thereby recovering the data frame synchronization signal (indicated as the recovered data frame synchronization signal from the communication device in FIG. 15). The frequency of the recovered data frame synchronization signal is half the frame frequency of the synchronization frame, which is equal to the frequency of the data frame synchronization signal used by the master communication device 10 to send the synchronization frame. At the same time, because of the existence of the high frequency clock count value 0 to K-1, the recovered data frame synchronization signal can be selected to be output at a preset high frequency clock count value (phase) position, that is, the delay of the recovered data frame synchronization signal relative to the synchronization frame timing signal can be selected. Further, because of the existence of the synchronization frame sequence number, the data frame synchronization signal can be selected to be output only at a preset synchronization frame sequence number and a preset high frequency clock count value (phase) position. In other embodiments, the communication device 11 can select to generate a high level pulse of the data frame synchronization signal at a different high frequency clock count value or a different synchronization frame sequence number than shown in FIG. 15, thereby recovering the data frame synchronization signal. For example, the communication device 11 can generate a high level pulse of the data frame synchronization signal when the count is n1 and the synchronization frame sequence number is 2 (this case is not shown in FIG. 15), and the frequency of the recovered data frame synchronization signal is one fourth of the frame frequency of the synchronization frame, which is half the frequency of the data frame synchronization signal used by the master communication device 10 to send the synchronization frame.

[0124] In the present application, the synchronization frame can include a phase field, and the phase field includes phase relationship information between the synchronization frame and the data frame synchronization signal. The data frame synchronization signal recovery module 113 (included in the communication device 11) recovers the data frame synchronization signal according to the phase field.

[0125] As shown in FIG. 16, the synchronization frame includes a synchronization frame header and a phase field. The communication device 11 uses the synchronization frame header to identify the synchronization frame, and the phase field includes phase relationship information between the synchronization frame and the data frame synchronization signal.

[0126] In the application, the synchronization frame is initially sent by the master communication device 10 to its downstream device (the downstream device of the master communication device 10 is the slave communication device 11), the slave communication device 11 receives the synchronization frame from its upstream device (the upstream device of the slave communication device 11 is the master communication device 10 or the slave communication device 11), in an embodiment of the master communication device 10 as shown in Fig. 2, the host interface module 102 is connected with the host, the host interface module 102 receives the data frame synchronization signal as shown in Fig. 17 and Fig. 19 from the host, in another embodiment of the master communication device 10 as shown in Fig. 3, the master communication device 10 comprises a data frame synchronization signal generation module 103, the data frame synchronization signal generation module 103 generates the data frame synchronization signal as shown in Fig. 17 and Fig. 19.

[0127] An implementation method of recovering the data frame synchronization signal according to the synchronization frame is given in the embodiment as shown in Fig. 17. The data frame synchronization signal as shown in Fig. 17 is the data frame synchronization signal in the master communication device 10, the data frame synchronization signal can be sent into a phase-locked loop circuit (included in the master communication device 10) to generate a high frequency clock, if the frequency of the high frequency clock is K times of the frequency of the synchronization frame timing signal, the master communication device 10 counts from 0 to K-1 for the high frequency clock and loops. The master communication device 10 sends the synchronization frame, the frame frequency of the synchronization frame can be independent of the frequency of the data frame synchronization signal, i.e. the frame frequency of the synchronization frame is not required to be locked to the frequency of the data frame synchronization signal according to a determined proportional relationship (the frame frequency of the synchronization frame is not required to be locked to the frequency of the data frame synchronization signal according to a determined proportional relationship), of course, the frame frequency of the synchronization frame can be locked to the frequency of the data frame synchronization signal according to a determined proportional relationship, the embodiment does not limit how the master communication device 10 determines the frame frequency of the synchronization frame. In the embodiment as shown in Fig. 17, the frame frequency of the synchronization frame is independent of the frequency of the data frame synchronization signal, further, the interval between two adjacent synchronization frames can be fixed or variable, in the embodiment as shown in Fig. 17, the interval between two adjacent synchronization frames is variable. When the master communication device 10 sends the synchronization frame, the phase field of the synchronization frame can be the count value of the high frequency clock of the master communication device 10 at the time of sending the synchronization frame, so that the phase field contains the phase relationship information between the synchronization frame and the data frame synchronization signal.

[0128] The data frame synchronization signal is recovered from the communication device 11 according to the phase field. In one embodiment, after receiving the synchronization frame from the communication device 11, a synchronization frame timing signal is generated and the phase field of the synchronization frame is read from the communication device 11, and the synchronization frame timing signal and the read phase field of the synchronization frame can be sent to the data frame synchronization signal recovery module 113, and the data frame synchronization signal is recovered by the data frame synchronization signal recovery module 113. The present application does not limit the implementation method of the data frame synchronization signal recovery module 113, and in one embodiment, the data frame synchronization signal recovery module 113 can include a high-frequency clock generation circuit and a high-frequency clock counter, and the counting range of the high-frequency clock counter can be 0 to K-1 and loop back and forth, as shown in FIG. 17, and the high-frequency clock counting range in the communication device 11 can be selected to be the same as the high-frequency clock counting range in the master communication device 10.

[0129] At the moment of receiving the synchronization frame, that is, when the synchronization frame timing signal is a high-level pulse, the data frame synchronization signal recovery module 113 compares the difference between the phase field read from the synchronization frame and the high-frequency clock counting value of the data frame synchronization signal recovery module 113, and this difference can be used as a phase error signal to adjust the frequency and phase of the high-frequency clock generated by the high-frequency clock generation circuit included in the data frame synchronization signal recovery module 113, so as to minimize the phase error, thereby recovering the high-frequency clock and the high-frequency clock counting value in the data frame synchronization signal recovery module 113 that are locked with the frequency and phase of the high-frequency clock in the master communication device 10.

[0130] As shown in FIG. 17, the values of the synchronization frame phase field are n1, n2, n3, and n4, and the values of the high-frequency clock counting value recovered from the communication device 11 at the moment when the synchronization frame timing signal is a high-level pulse are also n1, n2, n3, and n4, and in this example, the phase error has been reduced to 0. As shown in the embodiment of FIG. 17, the communication device 11 generates a high-level pulse of the data frame synchronization signal when counting to m, thereby recovering the data frame synchronization signal (indicated as the data frame synchronization signal recovered from the communication device in FIG. 17). The recovered data frame synchronization signal can be output at a preset high-frequency clock counting value (phase) position from the communication device 11, because the high-frequency clock counting value recovered in the data frame synchronization signal recovery module 113 is locked with the high-frequency clock counting value in the master communication device 10, so the delay of the recovered data frame synchronization signal relative to the data frame synchronization signal in the master communication device 10 can be preset.

[0131] In the present application, the synchronization frame can include a phase field and a counting field, the phase field includes the phase relationship information between the synchronization frame and the data frame synchronization signal, and the counting field includes the data frame synchronization signal counting value, and the data frame synchronization signal recovery module 113 recovers the data frame synchronization signal according to the phase field and the counting field.

[0132] As shown in Fig. 18, the synchronization frame contains a synchronization frame header, a phase field and a count field. The synchronization frame header is used by the communication device 11 to identify the synchronization frame. The phase field contains the phase relationship information between the synchronization frame and the data frame synchronization signal. The count field contains the count value of the data frame synchronization signal.

[0133] As shown in Fig. 19, an implementation method for recovering the data frame synchronization signal from the synchronization frame is given. The data frame synchronization signal shown in Fig. 19 is the data frame synchronization signal in the main communication device 10. The data frame synchronization signal can be input into a phase-locked loop circuit (included in the main communication device 10) to generate a high frequency clock. If the frequency of the high frequency clock is K times the frequency of the synchronization frame timing signal, the main communication device 10 counts from 0 to K-1 and loops, and the main communication device 10 further includes a data frame synchronization signal counter for counting the data frame synchronization signal. In the embodiment shown in Fig. 19, the count value of the data frame synchronization signal is from 0 to 3 and loops. The main communication device 10 sends the synchronization frame. The frame frequency of the synchronization frame can be independent of the frequency of the data frame synchronization signal, i.e. the frame frequency of the synchronization frame does not need to have a certain proportional relationship with the frequency of the data frame synchronization signal (i.e. the frame frequency of the synchronization frame does not need to be locked to the frequency of the data frame synchronization signal according to a certain proportional relationship). Of course, the frame frequency of the synchronization frame can have a certain proportional relationship with the frequency of the data frame synchronization signal, i.e. the frame frequency of the synchronization frame is locked to the frequency of the data frame synchronization signal according to a certain proportional relationship. This embodiment does not limit how the main communication device 10 determines the frame frequency of the synchronization frame. In the embodiment shown in Fig. 19, the frame frequency of the synchronization frame is independent of the frequency of the data frame synchronization signal, and further, the interval between two adjacent synchronization frames can be fixed or variable. In the embodiment shown in Fig. 19, the interval between two adjacent synchronization frames is variable. When the main communication device 10 sends the synchronization frame, the phase field of the synchronization frame can be the count value of the high frequency clock of the main communication device 10 at the time of sending the synchronization frame, so that the phase field contains the phase relationship information between the synchronization frame and the data frame synchronization signal. The count field of the synchronization frame can be the count value of the data frame synchronization signal of the main communication device 10 at the time of sending the synchronization frame.

[0134] The data frame synchronization signal is recovered from the communication device 11 according to the phase field and the count field. In one embodiment, after receiving the synchronization frame from the communication device 11, the synchronization frame timing signal is generated and the phase field and the count field of the synchronization frame are read from the communication device 11, and the synchronization frame timing signal and the read phase field and count field of the synchronization frame can be sent to the data frame synchronization signal recovery module 113, and the data frame synchronization signal is recovered by the data frame synchronization signal recovery module 113. The present application does not limit the implementation method of the data frame synchronization signal recovery module 113. In one embodiment, the data frame synchronization signal recovery module 113 can include a high-frequency clock generation circuit, a high-frequency clock counter and a data frame synchronization signal counter. The counting range of the high-frequency clock counter can be 0 to K-1 and loop back, and the counting range of the data frame synchronization signal counter can be 0 to 3 and loop back. When the counting value of the high-frequency clock counter jumps from K-1 to 0, the data frame synchronization signal counter is incremented by 1, as shown in FIG. 19. The high-frequency clock counting range and the data frame synchronization signal counting range in the communication device 11 can be selected to be the same as the high-frequency clock counting range and the data frame synchronization signal counting range in the master communication device 10.

[0135] At the moment of receiving the synchronization frame, that is, when the synchronization frame timing signal is a high-level pulse, the data frame synchronization signal recovery module 113 compares the difference between the phase field and the count field read from the synchronization frame and the high-frequency clock counting value and the data frame synchronization signal counting value of the data frame synchronization signal recovery module 113. This difference can be used as a phase error signal to adjust the frequency and phase of the high-frequency clock generated by the high-frequency clock generation circuit included in the data frame synchronization signal recovery module 113 to minimize the phase error, so as to recover the high-frequency clock, the high-frequency clock counting value and the data frame synchronization signal counting value in the data frame synchronization signal recovery module 113 which are locked with the high-frequency clock frequency and phase in the master communication device 10.

[0136] As shown in Fig. 19, the values of the phase field / count field of the synchronization frame are n1 / 0, n2 / 1, n3 / 2, n4 / 3, and the values of the high-frequency clock count value / data frame synchronization signal count value recovered from the communication device 11 are also n1 / 0, n2 / 1, n3 / 2, n4 / 3 at the time when the synchronization frame timing signal is a high level pulse, and in this example, the phase error has been reduced to 0. As shown in the example of Fig. 19, a high level pulse of the data frame synchronization signal is generated from the communication device 11 when the high-frequency clock count is m and the data frame synchronization signal count value is even, and thus the data frame synchronization signal is recovered (indicated as the data frame synchronization signal recovered from the communication device in Fig. 19), and in this example, the frequency of the recovered data frame synchronization signal is half of the frequency of the data frame synchronization signal in the main communication device 10. The recovered data frame synchronization signal can be outputted from the communication device 11 at a preset high-frequency clock count value (phase) and a preset data frame synchronization signal count value, because the high-frequency clock count value and the data frame synchronization signal count value recovered in the data frame synchronization signal recovery module 113 are locked to the high-frequency clock count value and the data frame synchronization signal count value in the main communication device 10, and thus the delay of the recovered data frame synchronization signal relative to the data frame synchronization signal in the main communication device 10 can be preset, and the frequency can also be different from the frequency of the data frame synchronization signal in the main communication device 10.

[0137] The above merely illustrates the preferred embodiments of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can make changes, modifications, replacements and variations to the above embodiments within the technical scope disclosed by the present application, which should be covered within the protection scope of the present application.

Claims

1. A master communication device, comprising a downstream device interface module, a local clock generation module, characterized in that: the downstream device interface module is connected with a downstream device through a downlink, the downstream device interface module sends a first signal to the downstream device through the downlink, the downstream device sends a second signal, the downstream device interface module receives the second signal from the downstream device through the downlink, the first signal and the second signal are transmitted on the downlink in time division, the local clock generation module generates a local clock, the clock of the downstream device interface module sending the first signal is the local clock, and the local clock is a spread spectrum clock, the first signal comprises a synchronization frame, and the downstream device interface module sends the synchronization frame, and after the downstream device interface module sends the synchronization frame, the local clock generation module sets the frequency of the local clock to a preset frequency value.

2. The master communication device according to claim 1, characterized in that: after the downstream device interface module sends the synchronization frame, the local clock generation module sets the frequency of the local clock to the preset frequency value, and then the frequency of the local clock changes according to a preset frequency curve.

3. The master communication device according to claim 1, characterized in that: the master communication device is an integrated circuit chip, the local clock generation module generates the local clock according to a local reference clock, and the local reference clock is generated by a crystal reference clock generation circuit on the integrated circuit chip.

4. The master communication device according to claim 1, characterized in that: the master communication device further comprises a host interface module, the host interface module is connected with a host, the host interface module receives a data frame synchronization signal from the host, the synchronization frame comprises data frame synchronization signal information, and the downstream device can recover the data frame synchronization signal according to the synchronization frame.

5. The master communication device according to claim 1, characterized in that: the master communication device further comprises a data frame synchronization signal generation module, the data frame synchronization signal generation module generates a data frame synchronization signal, the synchronization frame comprises data frame synchronization signal information, and the downstream device can recover the data frame synchronization signal according to the synchronization frame.

6. A slave communication device, comprising an upstream device interface module, a local clock generation module, characterized in that: the upstream device interface module is connected with an upstream device through an uplink, the upstream device sends a first signal, the upstream device interface module receives the first signal from the upstream device through the uplink, the upstream device interface module sends a second signal to the upstream device through the uplink, and the first signal and the second signal are transmitted on the uplink in time division, the local clock generation module generates a first local clock, the clock of the upstream device interface module sending the second signal is the first local clock, and the first local clock is a spread spectrum clock, the first signal comprises a synchronization frame, and the upstream device interface module receives the synchronization frame, and after the upstream device interface module receives the synchronization frame, the local clock generation module sets the frequency of the first local clock to a first preset frequency value.

7. The slave communication device according to claim 6, characterized in that: ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ After the upstream device interface module receives the synchronization frame, the local clock generation module sets the frequency of the first local clock to a first preset frequency value, and then the frequency of the first local clock varies according to a first preset frequency curve.

8. The slave communication device of claim 6, wherein: The slave communication device is an integrated circuit chip, and the local clock generation module generates the first local clock according to a local reference clock, which is generated by a crystalless reference clock generation circuit on the integrated circuit chip.

9. The slave communication device of claim 6, wherein: The slave communication device further comprises a data frame synchronization signal recovery module, the synchronization frame comprises data frame synchronization signal information, and the data frame synchronization signal recovery module recovers the data frame synchronization signal according to the received synchronization frame.

10. The slave communication device of claim 6, wherein: The slave communication device further comprises a downstream device interface module, The downstream device interface module is connected to a downstream device through a downlink, and the downstream device interface module sends a third signal to the downstream device through the downlink, The slave communication device sends the received synchronization frame to the downstream device through the downlink in the third signal, The local clock generation module further generates a second local clock, the clock of the downstream device interface module sending the third signal is the second local clock, and the second local clock is a spread spectrum clock, After the slave communication device sends the received synchronization frame to the downstream device through the downlink in the third signal, the local clock generation module sets the frequency of the second local clock to a second preset frequency value.

11. The slave communication device of claim 10, wherein: After the slave communication device sends the received synchronization frame to the downstream device through the downlink in the third signal, the local clock generation module sets the frequency of the second local clock to a second preset frequency value, and then the frequency of the second local clock varies according to a second preset frequency curve.

12. The slave communication device of claim 10, wherein: The slave communication device is an integrated circuit chip, and the local clock generation module generates the second local clock according to a local reference clock, which is generated by a crystalless reference clock generation circuit on the integrated circuit chip.

13. A slave communication device, comprising an upstream device interface module, a downstream device interface module, and a local clock generation module, wherein: The upstream device interface module is connected to an upstream device through an uplink, the upstream device sends a first signal, the upstream device interface module receives the first signal from the upstream device through the uplink, the upstream device interface module sends a second signal to the upstream device through the uplink, and the first signal and the second signal are transmitted in time division on the uplink, The local clock generation module generates a first local clock, and the clock of the upstream device interface module sending the second signal is the first local clock, The first signal comprises a synchronization frame, and the upstream device interface module receives the synchronization frame, The downstream device interface module is connected to a downstream device through a downlink, and the downstream device interface module sends a third signal to the downstream device through the downlink, The slave communication device sends the received synchronization frame to the downstream device through the downlink in the third signal, The local clock generation module further generates a second local clock, the clock of the downstream device interface module sending the third signal is the second local clock, and the second local clock is a spread spectrum clock, After the slave communication device sends the received synchronization frame to the downstream device through the downlink in the third signal, the local clock generation module sets the frequency of the second local clock to a second preset frequency value. the slave communication device sends the received synchronization frame to the downstream device through a downlink as a third signal, the local clock generation module further generates a second local clock, the clock for sending the third signal by the downstream device interface module is the second local clock, and the second local clock is a spread spectrum clock, after the slave communication device sends the received synchronization frame to the downstream device through a downlink as a third signal, the local clock generation module sets the frequency of the second local clock to a second preset frequency value.

14. The slave communication device according to claim 13, wherein: after the slave communication device sends the received synchronization frame to the downstream device through a downlink as a third signal, the local clock generation module sets the frequency of the second local clock to a second preset frequency value, and then the frequency of the second local clock changes according to a second preset frequency curve.

15. The slave communication device according to claim 13, wherein: the slave communication device is an integrated circuit chip, the local clock generation module generates the second local clock according to a local reference clock, and the local reference clock is generated by a crystalless reference clock generation circuit on the integrated circuit chip.

16. The slave communication device according to claim 13, wherein: the slave communication device further comprises a data frame synchronization signal recovery module, the synchronization frame comprises data frame synchronization signal information, and the data frame synchronization signal recovery module recovers the data frame synchronization signal according to the received synchronization frame.

17. A spread spectrum clock-based communication system comprising a first communication device and a second communication device, the first communication device being connected to the second communication device through a communication link, characterized in that: the first communication device comprises a downstream device interface module, which sends a first signal to the second communication device through the communication link and receives a second signal from the second communication device through the communication link, the second communication device comprises an upstream device interface module, which sends the second signal to the first communication device through the communication link and receives the first signal from the first communication device through the communication link, the first signal and the second signal are transmitted on the communication link at different times, the first communication device and the second communication device further respectively comprise a local clock generation module, the clock for sending the first signal by the first communication device is a first communication device local clock generated by the local clock generation module comprised by the first communication device, the clock for sending the second signal by the second communication device is a second communication device local clock generated by the local clock generation module comprised by the second communication device, and the first communication device local clock is a spread spectrum clock, the first signal comprises a synchronization frame, and the second communication device receives the synchronization frame, after the first communication device sends the synchronization frame, the local clock generation module comprised by the first communication device sets the frequency of the first communication device local clock to a first preset frequency value.

18. The spread spectrum clock-based communication system according to claim 17, wherein: After the first communication device sends the synchronization frame, a local clock generation module included in the first communication device sets the frequency of the local clock of the first communication device to a preset frequency value of the first communication device, and then the frequency of the local clock of the first communication device changes according to a preset frequency curve of the first communication device.

19. The spread spectrum clock-based communication system of claim 17, wherein: The local clock of the second communication device is a spread spectrum clock, and after the second communication device receives the synchronization frame, a local clock generation module included in the second communication device sets the frequency of the local clock of the second communication device to a preset frequency value of the second communication device.

20. The spread spectrum clock-based communication system of claim 19, wherein: After the second communication device receives the synchronization frame, a local clock generation module included in the second communication device sets the frequency of the local clock of the second communication device to a preset frequency value of the second communication device, and then the frequency of the local clock of the second communication device changes according to a preset frequency curve of the second communication device.

21. The spread spectrum clock-based communication system of claim 17, wherein: The first communication device is a master communication device, and the second communication device is a slave communication device.

22. The spread spectrum clock-based communication system of claim 17, wherein: The first communication device and the second communication device are both slave communication devices.

23. The spread spectrum clock-based communication system of claim 17, wherein: The second communication device includes a data frame synchronization signal recovery module, and the synchronization frame includes data frame synchronization signal information, and the data frame synchronization signal recovery module of the second communication device recovers the data frame synchronization signal according to the received synchronization frame.

Images