Video processing system, information processing device, and control method

Abstract

A video processing system (100, 200, 300) comprises a storage (3), an information processing device (1, 1'), a configuration unit (5), and an arbitration unit (6). The information processing device (1, 1') controls transmission and reception of video data to and from the storage (3) via a plurality of video channels (CH1 to CHm + n). The configuration unit (5) sets a time slot (TS). The arbitration unit (6) determines timing for permitting access to the storage (3) for each video channel. The information processing device (1, 1') performs the transmission and reception of video data to and from the storage (3) via each of the plurality of video channels (CH1 to CHm + n), within the time slot (TS), at the timing determined by the arbitration unit (6), performs the transmission and reception of the video data to and from the storage (3) via the plurality of video channels (CH1 to CHm + n), and executes interrupt processing in free time when the video data is not being transmitted and received within the time slot (TS).

Description

Video processing system, information processing device, and control method

[0001] The present disclosure relates to a video processing system, an information processing device, and a control method for recording and reading video data.

[0002] A system (called a video processing system) is known that records video data output from a video output device such as a camera in a recording device and reads the video data recorded in the recording device. A known recording device for recording video data is a recording device configured with a NAND element. This recording device is known as a solid state drive (SSD), for example.

[0003] When recording data such as video data in storage, it is known to reduce the amount of data collected if the total rate of collected data exceeds the throughput parameters of the network infrastructure (see, for example, Patent Document 1).

[0004] Special Publication No. 2020-530159

[0005] Currently, recording and playback of video data between a video input / output device and a storage device configured with a NAND element is being considered. If recording / reading of multiple pieces of video data between the video input / output device and the storage device is performed simultaneously without any control, a large amount of data will be transmitted and received between the video input / output device and the storage device, resulting in a decrease in the speed of transmitting and receiving the video data.

[0006] On the other hand, for example, when video data is not being transmitted or received between a video input / output device and a storage device, the video processing system may not perform any processing during the time when video data is not being transmitted or received. In other words, time may be wasted in the video processing system during which no processing is performed, which may reduce the efficiency of information processing in the video processing system.

[0007] The present disclosure aims to efficiently perform information processing in a system that transmits and receives video data between a video input / output device and storage, while maintaining the speed of transmitting and receiving video data.

[0008] The video processing system disclosed herein includes a storage, an information processing device, a configuration unit, and an arbitration unit. The storage has a nonvolatile memory unit that allows data to be written in page-size units and data to be erased in erase block-size units consisting of multiple pages. The information processing device controls transmission and reception of video data to and from the storage via multiple video channels connected to video input / output devices. The configuration unit sets time slots having a predetermined length of time for transmitting and receiving video data based on the page size and erase block size of the storage. The arbitration unit determines the timing at which each video channel is permitted to access the storage based on the time slot setting.

[0009] In this video processing system, the information processing device transmits and receives video data to and from the storage via a plurality of video channels by transmitting and receiving video data to and from the storage via each of a plurality of video channels within a time slot at the timing determined by the arbitration unit. The information processing device also executes interrupt processing during free time in the time slot when no video data is being transmitted or received.

[0010] In the video processing system disclosed herein, video data is transmitted and received with the storage via multiple video channels by transmitting and receiving video data with the storage via each of the multiple video channels within a time slot having a predetermined length. As a result, at a specific timing within the time slot, the communication bandwidth can be monopolized for transmitting and receiving video data with the storage via one video channel. As a result, the speed of transmitting and receiving video data with the storage via the video channels does not decrease.

[0011] Furthermore, in the above video processing system, interrupt processing is performed during the free time in a time slot when no video data is being transmitted or received, thereby preventing the video processing system from wasting time during which no processing is being performed, thereby enabling efficient information processing in the video processing system.

[0012] FIG. 1 is a block diagram showing the configuration of a video processing system. FIG. 2 is a block diagram showing the configuration of an information processing device. FIG. 3 is a block diagram showing the configuration of a storage. FIG. 4 is a diagram showing the configuration of a recording area. FIG. 5 is a sequence diagram showing signal transmission and reception in the video processing system. FIG. 6 is a flowchart showing the operation of the information processing device in the video processing system. FIG. 7 is a diagram showing the configuration of a time slot. FIG. 8 is a diagram showing the configuration of inter-frame compressed video data. FIG. 9 is a sequence diagram showing signal transmission and reception in the video processing system of a second embodiment. FIG. 10 is a flowchart showing the operation of the information processing device in the video processing system of the second embodiment. FIG. 11 is a block diagram showing the configuration of a video processing system of a third embodiment. FIG. 12 is a block diagram showing the configuration of the information processing device in the third embodiment. FIG. 13 is a sequence diagram showing signal transmission and reception in the video processing system of the third embodiment. FIG. 14 is a flowchart showing the operation of the information processing device in the video processing system of the third embodiment.

[0013] Hereinafter, embodiments will be described in detail with reference to the drawings as appropriate. However, more detailed description than necessary may be omitted. For example, detailed description of already well-known matters or redundant description of substantially identical configurations may be omitted. This is to avoid unnecessary redundancy in the following description and to facilitate understanding by those skilled in the art. Note that the inventors provide the accompanying drawings and the following description to enable those skilled in the art to fully understand the present disclosure, and do not intend for them to limit the subject matter described in the claims.

[0014] In this disclosure, "video data" refers to data including video data, audio data, and metadata, data including only video data, and data including still image data.

[0015] [1. First Embodiment] [1-1. Video Processing System] Hereinafter, a video processing system 100 according to the present disclosure will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the video processing system 100. The video processing system 100 can record video data output from a video input / output device 2 in a storage 3 of the video processing system 100. The video data recorded in the storage 3 is used, for example, for future playback and editing. Editing of video data includes, for example, generating new video data by inserting a specific portion of other video data into video data.

[0016] Furthermore, in the video processing system 100 , video data read from the storage 3 can be input to the video input / output device 2 .

[0017] The configuration of the video processing system 100 will be described below with reference to Fig. 1. The video processing system 100 includes an information processing device 1, a storage 3, a configuration unit 5, and an arbitration unit 6.

[0018] The information processing device 1 is connected to a video input / output device 2 and a storage 3 , and controls transmission and reception of video data between the video input / output device 2 and the storage 3 .

[0019] The video input / output device 2 includes a plurality of video output devices 2 a and a plurality of video input devices 2 b. The number of video output devices 2 a and video input devices 2 b included in the video input / output device 2 can be any number within the capacity allowed by the information processing device 1.

[0020] The video output device 2a acquires video and audio data, converts it into electrical signals, and outputs the data to the outside as video data. The video output device 2a is, for example, a video capture device equipped with a camera for capturing predetermined video, a microphone for capturing audio of the predetermined video, etc. Alternatively, the video output device 2a may be a media server that records a large number of videos. The video output from the video output device 2a is, for example, high-quality video such as uncompressed 4K video.

[0021] Video input device 2b inputs video and audio data as video data. Video input device 2b is, for example, a display (e.g., a liquid crystal display, an organic electroluminescence (EL) display, a plasma display, etc.) that plays back and displays the input video data. The video played back and displayed by video input device 2b is, for example, high-quality video such as uncompressed 4K video.

[0022] The video input / output device 2 may include a device that has both the function of the video output device 2a and the function of the video input device 2b.

[0023] The information processing device 1 receives video data from the video output device 2a and performs various information processing operations on the received video data. Specifically, for example, the information processing device 1 can convert the video data into compressed data. The information processing device 1 can also output the video data to an external device in uncompressed format. The information processing device 1 can edit the video data in accordance with user operations.

[0024] The information processing device 1 is capable of recording video data input from the video output device 2a, video data converted into a compressed format, edited video data, etc. in the storage 3. This allows the information processing device 1 to function as a recording device that records video data in the storage 3.

[0025] Furthermore, the information processing device 1 is capable of reading out video data recorded in the storage 3 and outputting the read-out video data to the video input device 2b, which allows the information processing device 1 to function as a playback device that plays back video data using the video input device 2b.

[0026] The information processing device 1 is connected to a storage 3. The information processing device 1 records video data input from a video output device 2a, video data converted into a compressed format, edited video data, etc. in the storage 3. The information processing device 1 also reads out the video data recorded in the storage 3 and outputs it to a video input device 2b.

[0027] Although the image processing system 100 of the present embodiment is provided with one information processing device 1, the present invention is not limited to this. The number of information processing devices 1 provided in the image processing system 100 can be any number.

[0028] The storage 3 records video data received from the information processing device 1 in accordance with a command from the information processing device 1. The storage 3 also reads designated video data in accordance with a command from the information processing device 1. As will be described later, the storage 3 is a recording device configured with a NAND element. The storage 3 is, for example, a solid state drive (SSD). In the video processing system 100 of this embodiment, one storage 3 is provided, but two or more storages 3 may be provided. The number of storages 3 provided in the video processing system 100 can be any number.

[0029] The configuration unit 5 is connected to the information processing device 1, the storage 3, and the arbitration unit 6 (described later). The configuration unit 5 sets the configuration of the video processing system 100. The configuration unit 5 is, for example, hardware configured by circuits that realize the above functions. The configuration unit 5 may be a computer system that includes a CPU (Central Processing Unit), a storage device, various interfaces, etc. and realizes the above functions. The configuration unit 5 may realize some or all of the above functions by software.

[0030] The arbitration unit 6 is connected to the information processing device 1 and the configuration unit 5. When the information processing device 1 requests access to the storage 3, the arbitration unit 6 determines whether to permit the information processing device 1 to access the storage 3 and notifies the information processing device 1 of the determination result. The arbitration unit 6 is, for example, hardware configured by circuits that realize the above functions. The arbitration unit 6 may be a computer system that includes a CPU, a storage device, various interfaces, etc. and realizes the above functions. The arbitration unit 6 may realize some or all of the above functions by software.

[0031] [1-2. Information Processing Device] The configuration of the information processing device 1 will be described with reference to Fig. 2. Fig. 2 is a diagram showing the configuration of the information processing device 1. The information processing device 1 has a CPU 11, a video interface 12, a storage interface 13, a RAM (Random Access Memory) 14, a storage device 15, and an interface 16.

[0032] The CPU 11 executes various processes in the information processing device 1. Specifically, the CPU 11 executes information processes such as video data compression, information processing related to video data editing, and video data analysis. The CPU 11 executes the above processes by executing instructions indicated in a program stored in the storage device 15. Note that some of the processes in the information processing device 1 may be realized by hardware implemented separately from the CPU 11 or by an external device. The CPU 11 generates commands for executing various processes.

[0033] The video interface 12 connects the information processing device 1 and the video input / output device 2. The video interface 12 is provided with a plurality of connection terminals. One video output device 2a or one video input device 2b included in the video input / output device 2 may be connected to only one connection terminal of the video interface 12, or may be connected to a plurality of video terminals.

[0034] The video interface 12 is an interface for connecting video-related devices, such as an interface conforming to the Serial Digital Interface (SDI) standard. Alternatively, the video interface 12 may be a network interface. In this case, transmission conforming to the ST2110 standard of the SMPTE standardization organization, for example, may be used. The video interface 12 may also be a network interface, such as a Gigabit Ethernet (registered trademark) interface, which connects the information processing device 1 to other devices via a network such as a WAN (Wide Area Network) or a LAN (Local Area Network).

[0035] A video channel is assigned to each of the multiple connection terminals of the video interface 12. The information processing device 1 shown in Fig. 2 has m+n connection terminals. Video channels CH1, ..., CHm+n are assigned to the m+n connection terminals, respectively. Video channels CH1, ..., CHm are assigned to the m connection terminals connected to the video output device 2a, respectively. Meanwhile, video channels CHm+1, ..., CHm+n are assigned to the n connection terminals connected to the video input device 2b, respectively.

[0036] 2, one video output device 2a or one video input device 2b is connected to one video channel, but this is not limiting. For example, one video output device 2a or one video input device 2b may be connected to multiple video channels.

[0037] The information processing device 1 transmits and receives video data between the multiple video channels CH1, ... CHm+n and the storage 3 by sequentially transmitting and receiving video data between each of the multiple video channels CH1, ... CHm+n and the storage 3 within a time slot TS (Figure 7) having a predetermined length of time.

[0038] Moreover, by sequentially allocating a plurality of time slots TS in chronological order, the information processing device 1 can repeatedly transmit and receive video data between the plurality of video channels CH1, ..., CHm+n and the storage 3. That is, after completing transmission and reception of video data in one time slot TS, the information processing device 1 transmits and receives video data in the next time slot TS, thereby repeatedly transmitting and receiving video data between the plurality of video channels CH1, ..., CHm+n and the storage 3.

[0039] The storage interface 13 connects the information processing device 1 and the storage 3. The storage interface 13 connects the information processing device 1 and the storage 3 via a direct transfer path. The storage interface 13 is, for example, a PCIe interface that complies with the PCI express standard of the PCI-SIG standard. This allows the information processing device 1 and the storage 3 to send and receive data at high speed using a protocol dedicated to non-volatile memory (NVMe (Non-Volatile Memory Express)) using a PCI-Express bus.

[0040] In NVMe, the controller acquires data from the NAND memory using the NAND protocol, converts it to the PCIe protocol, and transfers it to the host. In contrast, with conventional SATA (Serial-ATA), the DMA controller that transfers data directly to the host converts data from the NAND memory to the SATA protocol, acquires it, and then converts the data to the PCIe protocol before transferring it to the host. In other words, because NVMe processing directly converts from the NAND protocol to the PCIe protocol, the data transfer processing speed is faster than conventional SATA.

[0041] The RAM 14 is a storage area that temporarily stores commands, video data, etc. generated by the CPU 11. In the RAM 14, buffer areas BF1, BF2, ..., BFm+n are assigned to the video channels CH1, CH2, ..., CHm+n, respectively. The buffer areas BF1, BF2, ..., BFm+n are temporary storage areas that buffer the video data acquired via the corresponding video channels CH1, CH2, ..., CHm+n. The size of one buffer area is set to the access size, which is the size of video data that can be transmitted and received in one time slot, with a certain margin.

[0042] When recording video data input from the video output device 2a in the storage 3, the information processing device 1 buffers the video data in buffer areas BF1, ..., BFm assigned to the video channels CH1, ..., CHm to which the video output device 2a is connected, respectively. The video data buffered in the buffer areas is called "buffered data."

[0043] Specifically, when recording video data obtained by a certain video output device 2a in storage 3, the information processing device 1 buffers the video data obtained by the video output device 2a in a buffer area assigned to the video channel to which the video output device 2a is connected, and transmits the buffered data in the buffer area to storage 3.

[0044] On the other hand, when reading video data from storage 3 and outputting it to video input device 2b, information processing device 1 buffers the video data read from storage 3 in buffer areas BFm+1, ... BFm+n assigned respectively to video channels CHm+1, ... CHm+n to which video input device 2b is connected.

[0045] Specifically, when outputting video data read from storage 3 to a video input device 2b, the information processing device 1 buffers the video data read from storage 3 in a buffer area assigned to the video channel to which the video input device 2b is connected, and transmits the buffered data in the buffer area to the video input device 2b.

[0046] The RAM 14 also has a processing queue QU (see FIG. 12, which will be described later). The processing queue QU stores interrupt commands that instruct interrupt processing to be executed instead of the transmission and reception of video data that would have been executed in the small slot SS (see FIG. 7, which will be described later). The CPU 11 reads out and executes the interrupt commands stored in the processing queue QU one command at a time.

[0047] The storage device 15 is composed of a ROM (Read Only Memory), a hard disk (HDD), a solid state drive (SSD), etc. The storage device 15 stores programs executed by the CPU 11, settings related to the processing of the information processing device 1, parameters used for the processing, etc.

[0048] The interface 16 is an interface for connecting the information processing device 1 to other devices. The configuration unit 5 and the arbitration unit 6 are connected to the interface 16. The interface 16 is a network interface such as a Gigabit Ethernet (registered trademark) interface that connects the information processing device 1 to other devices via a network such as a WAN or LAN.

[0049] At least one of the storage interface 13 and the interface 16 may be capable of directly transmitting and receiving data between the RAM 14 of the information processing device 1 and a storage device of another device by remote direct memory access (RDMA), thereby enabling high-speed data transmission and reception between the information processing device 1 and the other device.

[0050] Note that the functions of at least one of the above-described configuration unit 5 and arbitration unit 6 may be realized by the information processing device 1. In this case, at least one of the configuration unit 5 and arbitration unit 6 does not need to be connected to the interface 16. In other words, when at least one of the configuration unit 5 and arbitration unit 6 is a device separate from the information processing device 1, at least one of the configuration unit 5 and arbitration unit 6, which is a separate device, is connected to the interface 16.

[0051] [1-3. Storage] The configuration of the storage 3 will be described using Fig. 3. Fig. 3 is a diagram showing the configuration of the storage 3. The storage 3 has an access port 31, a flash memory 33, a controller 35, and a storage unit 37. The access port 31 is an interface that connects the storage 3 to other devices. The information processing device 1 is connected to the access port 31.

[0052] The flash memory 33 is composed of multiple NAND elements. Fig. 4 is a diagram showing the configuration of the recording area of ​​the storage 3. As shown in Fig. 4, the flash memory 33 has a recording area RA for recording video data. In addition, the recording area RA stores a table that associates addresses (logical addresses) specified by an external device with addresses (physical addresses) of erase blocks BL corresponding to the logical addresses.

[0053] The recording area RA is divided into a plurality of erase blocks BL. The erase blocks BL are units for erasing data in the flash memory 33. The erase blocks BL are further divided into a plurality of pages PA. The pages PA are units for recording data.

[0054] The recording area RA of the storage 3 is composed of a spare area and a user area. When the storage 3 starts to be used, all data in the recording area RA is physically erased, and then the entire recording area RA becomes the spare area. When a user writes data to the storage 3, the data is written to this spare area, and the area into which the data is written becomes the user area. Note that data can be written to the spare area in page PA units.

[0055] The upper limit size of the user area is a predetermined size that is smaller than the entire size of the recording area RA. In other words, the upper limit of the data writing size of the storage 3 that can be recognized by the user is the upper limit size of the user area. Furthermore, even after the user area reaches its upper limit size, a spare area remains in the recording area RA. The spare area remaining in the recording area RA is called a remaining spare area. This remaining spare area cannot be recognized by the user.

[0056] When a user deletes data from a user area on a file system, the deleted data from the user area simply becomes invalid and remains physically in the user area. In this state, when a user writes new data on the file system, the new data is written to the remaining spare area. Writing data to the remaining spare area is also done in page PA units.

[0057] When data is repeatedly deleted and new data is written in the file system, the amount of invalid data in the user area increases. The area in the remaining spare area where data can be written decreases. When the size of the area in the remaining spare area where data can be written falls below a predetermined size, the invalid data in the user area and the remaining spare area is physically erased.

[0058] As described above, data can only be erased in units of erase blocks BL in the storage 3. Therefore, the physical erasure of invalid data is performed by first moving all valid data present in the erase block BL in which the invalid data to be erased is recorded to another erase block BL to which data can be written (for example, an erase block BL in the remaining spare area to which data can be written), and then physically erasing all data (both invalid data and valid data) recorded in the erase block BL from which the valid data was moved (the erase block BL in which the invalid data to be erased was recorded) in units of erase blocks BL (garbage collection). After the data has been physically erased in this way, it becomes possible to write data in units of pages PA in the erase blocks BL.

[0059] As described above, in the storage 3, new data can be written in units of pages PA to unused areas and areas from which data has been erased as described above in the recording area RA. On the other hand, new data can be written to areas to which data has already been written after the data has been physically erased in units of erase blocks BL each consisting of a plurality of pages PA.

[0060] The controller 35 executes control related to the storage 3. In particular, the controller 35 controls the recording of data to the flash memory 33 and the reading of data from the flash memory 33. The controller 35 also executes other processes required for the solid state drive, such as garbage collection and wear leveling. The controller 35 executes programs stored in the storage unit 37 to execute the above processes.

[0061] The storage unit 37 is provided as a memory separate from the flash memory 33, or is part of the recording area RA, and stores various parameters related to the control of the storage 3. The storage unit 37 stores, for example, the size of the page PA, the size of the erase block BL, the number of times data is recorded in each erase block BL, parameters for executing various processes, and the like.

[0062] 5 and 6, the operation of the video processing system 100 will be described. Fig. 5 is a sequence diagram showing signal transmission and reception in the video processing system 100. Fig. 6 is a flowchart showing the operation of the information processing device 1 in the video processing system 100.

[0063] In the example described below, it is assumed that video data is recorded using m video channels CH1, CH2, ... CHm, and video data is read using n video channels CHm+1, CHm+2, ... CHm+n. It is also assumed that access permission to record video data via video channel CHp (1 < p < m) is not granted. The interrupt process is a process of reading video data via the qth video channel CHm+q (1 < q < n) among the video channels from which video data is read.

[0064] The processing described below can be applied in the same manner based on the operations described below even when either or both of the following occurs: access permission is not granted to any of the m+n video channels; or recording / reading of any video data via any of the video channels is performed as an interrupt process.

[0065] First, the configuration unit 5 sets the configuration of the video processing system 100. Specifically, the following process is executed. First, the user instructs the configuration unit 5 on the mode (recording mode, playback mode) to be used when recording / playing back video data in the video processing system 100. The recording mode includes the recording rate of the video data (the amount of video data recorded per unit time), and the playback mode includes the playback rate of the video data (the amount of video data read out per unit time). These modes may be set individually for each of the video channels CH1, CH2, ..., CHm+n, or the same mode may be set for all of the video channels CH1, CH2, ..., CHm+n.

[0066] Next, the configuration unit 5 requests information about the size of pages PA and erase blocks BL stored in the flash memory 33 of the storage 3 from the storage 3 (step S101 in FIG. 5). Upon receiving this request, the controller 35 of the storage 3 reads information about the size of pages PA and erase blocks BL from the memory unit 37 and transmits this information to the configuration unit 5 (step S102 in FIG. 5).

[0067] Thereafter, the configuration unit 5 sets a time slot TS for transmitting and receiving video data via video channels CH1, CH2, ... CHm+n based on the mode, the size of the page PA received from the storage 3, the size of the erase block BL, etc. As shown in Fig. 7, a time slot TS is defined as a period having a predetermined time length T. Fig. 7 is a diagram showing the configuration of a time slot TS.

[0068] A time slot TS is composed of multiple small slots SS. A small slot SS is assigned to each video channel. In one time slot TS, video data transmitted and received on one video channel is transmitted and received within the period of the small slot SS assigned to that video channel. Hereinafter, the size of the video data transmitted and received within the period of one small slot SS will be referred to as the "access size." In other words, in the video processing system 100, data having the above access size is transmitted and received via one video channel at a period corresponding to the time length T of the time slot TS.

[0069] The configuration unit 5 can determine the access size for recording video data, i.e., the access size of the small slot SS to be assigned to video channels CH1, CH2, ... CHm, to be an integer multiple or more of the size of the erase block BL, and to a size that suppresses fragmentation of the video data.

[0070] On the other hand, the configuration unit 5 can determine the access size for reading video data, i.e., the access size of the short slots SS assigned to video channels CHm+1, CHm+2, ... CHm+n, to a size that allows video data to be reproduced without interruption at least during the time length T of the time slot TS. For example, if the reproduction rate of video data is eMbps, the access size for reading video data can be e*T (unit: Mbit).

[0071] Furthermore, the configuration unit 5 sets the duration of the small slots SS and the duration T of the time slots TS based on the determined access size, etc. For example, if the data transfer rate between the information processing device 1 and the storage 3 is bMbps and the access size of a particular video channel is determined to be cMB (8*cMbits), the duration of the small slots SS assigned to that video channel can be determined to be 8*c / b seconds. The duration T of the time slots TS can be the sum of the durations of the small slots SS assigned to multiple video channels CH1, CH2, ... CHm+n.

[0072] When determining the access size, consideration is also given to the sector size accessible to the storage 3. Specifically, for example, if the sector size is 4 KB, the access size is set to an integral multiple of 4 KB (sector size).

[0073] The time length T of the time slot TS and the access size are such that, even when video data is transmitted and received via each video channel at a period corresponding to the time length T of the time slot TS, the video data can be recorded without interruption at the set recording rate and played back without interruption at the set playback rate.

[0074] For example, if the maximum recording rate and playback rate of video data in the video processing system 100 is dMbps and the access size allocated to the video channel that transmits and receives the video data is cMB (8*cMbits), then the time length T of the time slot TS is set to c / d or less.

[0075] After completing the setting of the time slot TS, the configuration unit 5 transmits the setting information of the time slot TS (such as the time length T of the time slot TS and the access size) to the arbitration unit 6 (step S103 in FIG. 5). Having received the setting information of the time slot TS, the arbitration unit 6 determines, based on the setting of the time slot TS, when to permit each of the video channels CH1, CH2, ... CHm+n to access the storage 3.

[0076] Furthermore, the configuration unit 5 transmits the time slot setting information to the information processing device 1 (step S104 in FIG. 5). The CPU 11 of the information processing device 1 executes a process of receiving the time slot TS setting information transmitted from the configuration unit 5 (step S1 in FIG. 6).

[0077] Thereafter, the CPU 11 configures the information processing device 1 based on the settings of the received time slot TS. Specifically, the CPU 11 determines the reservation sizes of the buffer areas BF1, BF2, ..., BFm+n to be allocated to the video channels CH1, CH2, ..., CHm+n, respectively, based on the settings of the time slot TS (access sizes of each video channel), and reserves the buffer areas BF1, BF2, ..., BFm+n in the RAM 14 (step S2 in FIG. 6). The reservation size of each buffer area can be determined as the access size determined for the video channel to which the buffer area is allocated, plus a predetermined margin.

[0078] After securing buffer areas BF1, BF2, ..., BFm+n, in the video processing system 100, transmission and reception (recording / reading of video data) of video data is performed between the information processing device 1, the multiple video input / output devices 2 (video output device 2a, video input device 2b), and the storage 3. When a user issues a command using the information processing device 1 or the like to output video data from the video output device 2a, the video data is output from each video output device 2a (step S105 in FIG. 5).

[0079] When a predetermined process is commanded as an interrupt process while transmission and reception of video data is being performed, the CPU 11 of the information processing device 1 stores the interrupt command for executing the interrupt process in the process waiting queue QU.

[0080] The interrupt process is, for example, a process of reading video data that needs to be read with priority from the storage 3. For example, in the information processing device 1, when a command is issued to read video data via one of video channels CHm+1, CHm+2, ... CHm+n and this video data needs to be read immediately, the process of reading the video data via that video channel is treated as an interrupt process. As described above, the interrupt process can be, for example, a process of reading video data via video channel CHm+q (1<q<n).

[0081] When the video data to be read by the execution of the interrupt process is inter-frame compressed video data, the CPU 11 determines the size of the video data to be read by the execution of the interrupt process based on the size of a GOP (Group of Pictures) of the video data. Specifically, the CPU 11 determines that the size of the video data to be read by the interrupt process is an integral multiple of the GOP.

[0082] Fig. 8 is a diagram showing the structure of inter-frame compressed video data. As shown in Fig. 8, inter-frame compressed video data includes an I frame and a P frame or a B frame. An I frame is a frame that holds all the information required to display a frame of video data. In other words, a video can be displayed using only the I frame. A P frame holds differential information from the previous I frame, and therefore cannot display a video using only this frame. A B frame holds differential information from the preceding I frame, P frame, or B frame, and therefore cannot display a video using only this frame.

[0083] A GOP is a data unit consisting of multiple frames of video data. Specifically, a GOP is data structured such that there is one I frame at the beginning, followed by at least one of B frames and P frames. Note that a GOP may be composed of only I frames.

[0084] In this way, by determining the video data to be read by the interrupt process based on the GOP size, it is possible to prevent the video data to be read by the interrupt process from being cut off halfway, for example.

[0085] Furthermore, when the CPU 11 reads video data in an interrupt process, it reads the video data by dividing it into pieces. Specifically, when instructed to read certain video data by an interrupt process, the CPU 11 generates multiple interrupt processes for reading the video data divided into pieces, and stores the multiple interrupt commands in the processing queue QU.

[0086] In the above case, the size of the video data read in one interrupt process (read access size) can be determined based on, for example, the size of the page PA and the number of parallel NAND elements constituting the storage 3. The number of parallel NAND elements is, for example, the number of dies on which the NAND elements are formed that are included in the flash memory 33. Specifically, the read access size of the video data read in one interrupt process can be the product of the size of the page PA and the number of parallel NAND elements.

[0087] As described above, by setting the read access size of the video data read in one interrupt process to a small size as described above, the time required to execute one interrupt process can be shortened, thereby increasing the feasibility of executing the interrupt process. Specifically, the process of reading large-sized video data takes time and cannot be completed within the short slot SS, but the process of reading small-sized video data can be completed within the short slot SS.

[0088] Returning to the explanation of transmission and reception of video data in the video processing system 100, when the current time reaches the start time of a certain short slot SS in a certain time slot TS during transmission and reception of video data, the CPU 11 of the information processing device 1 outputs an access request to the arbitration unit 6 for the video channel assigned to that short slot SS (any of video channels CH1, CH2, ... CHm+n) (step S106 in FIG. 5, step S3 in FIG. 6).

[0089] The arbitration unit 6 that has received the access request determines whether or not to grant access permission to the video channel assigned to the small slot SS for which the access request has been made. Specifically, the arbitration unit 6 acquires from the information processing device 1 the amount of video data buffered in the buffer area (the buffer area assigned to the video channel among buffer areas BF1, BF2, ..., BFm+n) assigned to the video channel for which the access request has been made (any of video channels CH1, CH2, ..., CHm+n), and determines whether or not to grant access permission for the access request based on the amount of video data buffered in the buffer area.

[0090] For example, in the case of an access request to a video channel (any of video channels CH1, CH2, ... CHm) that records video data, if the video data is not buffered in the buffer area assigned to the video channel for which the access request was made (for example, if video data is not being output from the video output device 2a connected to that video channel), or if there is room in the buffer area and recording of the video data can wait until the next time slot TS, the arbitration unit 6 determines that it is possible to skip sending and receiving video data in the small slot SS assigned to the current time, and does not grant access permission for that access request.

[0091] On the other hand, if a sufficient amount of video data (an integer multiple of the erase block BL and an amount that can suppress fragmentation) is buffered in the buffer area allocated to the video channel for which an access request has been made, or if there is no room in the buffer area and it is necessary to record video data in the current time slot TS and secure free space in the buffer area, access is permitted for the access request.

[0092] In the example of Fig. 5, access is permitted for the access requests for recording video channels CH1, ..., CHp-1. On the other hand, access is not permitted for the access request for video channel CHp. Access is also permitted for the access requests for the subsequent video channels CHp+1, ..., CHm.

[0093] For example, in the case of an access request to video channels CHm+1, CHm+2, ... CHm+n that read video data, if no video data is buffered in the buffer area assigned to the video channel for which the access request was made (for example, if no video data is input to the video input device 2b connected to that video channel), or if a sufficient amount of video data (an amount sufficient to input video data to the video input device 2b without interruption until the next time slot TS) is buffered in the buffer area, the arbitration unit 6 determines that it is possible to skip sending and receiving video data in the small slot SS assigned to the current time, and does not grant access permission for the access request.

[0094] On the other hand, if there is sufficient space in the buffer area allocated to the video channel for which an access request has been made, or if the amount of data buffered in the buffer area is small and a sufficient amount of video data needs to be further buffered, access is permitted for the access request.

[0095] In the example of FIG. 5, access is permitted for all access requests for readout of video channels CHm+1, . . . CHm+n.

[0096] If the arbitration unit 6 grants access to a request for access to a video channel assigned to a small slot SS executed at the current time (step S107 in Figure 5, "Yes" in step S4 in Figure 6), the CPU 11 of the information processing device 1 executes transmission and reception of video data in the small slot SS (step S6 in Figure 6).

[0097] For example, as shown in FIG. 5, if access is permitted for a request to access a video channel other than the video channel CHp that records video data, i.e., video channels CH1, ... CHp-1, CHp+1, ... CHm, in the small slot SS allocated to the corresponding video channel, the CPU 11 transmits the buffered data buffered in the buffer area for that video channel to the storage 3 (step S108 in FIG. 5).

[0098] 5, when an access request for each of video channels CHm+1, ..., CHm+n for reading video data is granted, the CPU 11 reads the specified video data from the storage 3 in the small slot SS assigned to the corresponding video channel and buffers the video data read from the storage 3 in the buffer area assigned to the video channel (step S109 in FIG. 5). The CPU 11 also transmits the buffered data in this buffer area to the video input device 2b connected to the video channel (step S110 in FIG. 5). This inputs the video data to the video input device 2b, and the video data is played back and displayed on the video input device 2b, for example.

[0099] On the other hand, if the arbitration unit 6 does not grant access permission for the access request to the video channel assigned to the short slot SS executed at the current time ("No" in step S4 of FIG. 6), the CPU 11 of the information processing device 1 determines whether or not to execute interrupt processing in the short slot SS. Specifically, the CPU 11 determines whether or not an interrupt command is stored in the processing waiting queue QU (step S5 of FIG. 6). In the example shown in FIG. 5, access permission has not been granted for video channel CHp, so the CPU 11 determines whether or not to execute interrupt processing in the short slot SS assigned to video channel CHp.

[0100] If the arbitration unit 6 does not grant access permission and no interrupt command is stored in the processing queue QU, i.e., if there is no interrupt processing to be executed in the current short slot SS ("No" in step S5 of FIG. 6), the CPU 11 cannot execute the interrupt processing in that short slot SS, and therefore skips the transmission and reception of video data in that short slot SS. In this case, the CPU 11 decides to execute the transmission and reception of video data in the next short slot SS (step S9 of FIG. 6), and executes steps S3 to S7 in that next short slot SS.

[0101] On the other hand, if an interrupt command is stored in the processing waiting queue QU, that is, if there is an interrupt process to be executed in the current small slot SS ('Yes' in step S5), the CPU 11 executes the interrupt command stored in the processing waiting queue QU in the small slot SS and executes the interrupt process (step S7 in Figure 6).

[0102] 5, the access request to the video channel CHp for recording video data is denied. Furthermore, it is assumed that the judgment in step S5 above determines that interrupt processing can be executed in the short slot SS assigned to the video channel CHp. In this case, in the short slot SS assigned to the video channel CHp, the CPU 11 executes the interrupt command stored in the processing queue QU to execute the interrupt processing, instead of recording the video data.

[0103] As described above, the interrupt commands stored in the processing queue QU are for reading out segmented video data and therefore require a short processing time. Therefore, the CPU 11 reads out from the processing queue QU multiple interrupt processes that can be executed within the small slot SS and executes them. In other words, by shortening the time required for one interrupt process, an interrupt process can be executed even when the free time in the small slot SS is short, and multiple interrupt processes can be executed when there is sufficient free time.

[0104] 5, the interrupt processing is a process of reading video data via video channel CHm+q, which reads video data. Therefore, in the small slot SS assigned to video channel CHp, the CPU 11 executes the process of reading video data via video channel CHm+q as an interrupt processing, instead of executing the recording of video data via video channel CHp.

[0105] Specifically, the CPU 11 reads designated video data from the storage 3 in the short slot SS assigned to the video channel CHp, and buffers the video data read from the storage 3 in the buffer area BFm+q assigned to the video channel CHm+q (step S111 in FIG. 5).The CPU 11 also transmits the buffered data buffered in the buffer area BFm+q to the video input device 2b connected to the video channel CHm+q (step S112 in FIG. 5).

[0106] In this way, in the video processing system 100, video data is transmitted and received between the storage 3 and each of the multiple video channels CH1, CH2, ... CHm+n in sequence within a time slot TS having a predetermined length of time, thereby transmitting and receiving video data between the multiple video channels CH1, CH2, ... CHm+n and the storage 3. This allows the communication bandwidth to be monopolized for transmission and reception of video data between one video channel and the storage 3 at a specific timing within the time slot TS. As a result, the speed of transmission and reception of video data between the video channel and the storage 3 does not decrease.

[0107] Furthermore, the video processing system 100 executes interrupt processing during free time in a time slot TS when no video data is being transmitted or received. Specifically, when transmission or reception of video data between a video channel and the storage 3 in a short slot SS can be skipped, the interrupt processing is executed in the short slot SS. This prevents the video processing system 100 from having unnecessary short slots SS in which no processing is performed, thereby enabling efficient information processing in the video processing system 100.

[0108] For example, as shown in Figure 5, if there is a video channel CHp for which the recording of video data can be skipped while video data is being transmitted and received (recorded in storage 3) on video channels CH1, CH2, ... CHm that record video data, reading of the video data on video channel CHm+q can be performed with priority as an interrupt process in the small slot SS assigned to video channel CHp.

[0109] This means that, for example, when an instruction is given to transmit video data to a video input device 2b connected to video channel CHm+q, the video data can be read immediately after the instruction is given, without waiting until the short slot SS assigned to video channel CHm+q or the corresponding short slot SS in the next time slot TS to read the video data via video channel CHm+q.

[0110] After executing the above steps S3 to S7 for the current short slot SS, the CPU 11 of the information processing device 1 determines whether or not steps S3 to S7 have been executed for all short slots SS included in the current time slot TS (step S8 in FIG. 6).

[0111] If there is a short slot SS within the current time slot TS in which the above steps S3 to S7 have not been executed ("No" in step S8 of Figure 6), the CPU 11 decides to execute the next short slot SS (step S9 of Figure 6) and executes steps S3 to S7 in the next short slot SS.

[0112] On the other hand, if the above steps S3 to S7 have been executed for all small slots SS within the current time slot TS, i.e., if the current small slot SS is the last small slot in the current time slot TS (step S8 in Figure 6 is "Yes"), the CPU 11 decides to allocate and execute the next time slot TS (step S10 in Figure 6), and executes steps S3 to S7 for the small slot SS of the next time slot TS.

[0113] [1-5. Modifications] In the above embodiment, when transmission and reception of video data for a specific video channel can be skipped, in the small slot SS assigned to that video channel, instead of executing transmission and reception of video data via that video channel, an interrupt process stored in the processing waiting queue QU is executed.

[0114] However, this is not limited to this, and in a particular small slot SS, if the transmission and reception of video data for the video channel assigned to that small slot SS can be completed in a short time, and there is a free time between the end of the transmission and reception of the video data and the end time of that small slot SS that is longer than the execution time of the interrupt processing, the interrupt processing may be executed after the transmission and reception of the video data in that small slot SS is completed.

[0115] [2. Second Embodiment] In the above-described first embodiment, if it is possible to skip the transmission and reception of video data in a certain small slot SS included in a time slot TS, or if there is sufficient free time between the end of the transmission and reception of video data in that small slot SS and the end time of that small slot SS, interrupt processing is executed in that small slot SS.

[0116] However, the interrupt process can be executed at any timing during the free time when the transmission and reception of video data is not being executed. In the video processing system 200 according to the second embodiment, if the time from the end of the transmission and reception of video data in a first time slot among the plurality of time slots TS to the start of a second time slot allocated after the first time slot is equal to or longer than the time required for the interrupt process, the interrupt process can be executed in the first time slot.

[0117] As described above, the video processing system 200 of the second embodiment has the same configuration and functions as the video processing system 100 of the first embodiment, except that the execution timing of the interrupt process is different from that of the first embodiment. Therefore, the following will describe the parts that are different from the video processing system 100 of the first embodiment, and detailed descriptions of other matters will be omitted.

[0118] In the following explanation, it is assumed that access permission to record video data via video channel CHp (1<p<m) has not been granted. The interrupt process is a process of reading video data via video channel CHm+q (1<q<n), which is the qth video channel among the video channels that read video data.

[0119] In the second embodiment, the arbitration unit 6 determines whether or not an interrupt process can be executed by executing an interrupt command stored in the processing queue QU between the end of transmission and reception of video data in one time slot TS and the start of the next allocated time slot TS. The arbitration unit 6 notifies the information processing device 1 of this determination result. Specifically, when the arbitration unit 6 determines that the interrupt process can be executed, it transmits an interrupt process execution permission to the information processing device 1.

[0120] This determination can be made, for example, by determining whether the difference between the time when transmission and reception of video data in the first time slot ends and the time when the next second time slot begins is equal to or greater than the time required to execute the interrupt process.

[0121] Alternatively, this determination can also be made based on the amount of buffered data in the buffer areas BF1, BF2, ..., BFm+n allocated to the RAM 14 of the information processing device 1 at the end of transmission and reception of video data in the first time slot. For example, if it is determined that there is sufficient free space in the buffer areas BF1, BF2, ..., BFm that buffer video data to be recorded in the storage 3 at the end of transmission and reception of video data in the first time slot, and that the buffer areas will not overflow even if the video data is buffered until it is recorded in the storage 3 in the next time slot (video data can be buffered until the next recording), then it can be determined that the time until the start of the second time slot is equal to or longer than the time required to execute the interrupt process.

[0122] On the other hand, if, at the end of the transmission and reception of video data in the first time slot, sufficient buffering data is buffered in the buffer areas BFm+1, BFm+2, ... BFm+n that buffer the video data to be read, and it can be determined that the buffer areas will not become empty by the time the video data is read from storage 3 in the next time slot (buffering data can be read from the buffer areas until the next read), then it can be determined that the time until the start of the second time slot is longer than the time required to execute interrupt processing.

[0123] The operation of the video processing system 200 in the second embodiment will be described below with reference to Fig. 9 and Fig. 10. Fig. 9 is a sequence diagram showing signal transmission and reception in the video processing system 200 in the second embodiment. Fig. 10 is a flowchart showing the operation of the information processing device 1 in the video processing system 200 in the second embodiment.

[0124] First, the user instructs the configuration unit 5 on the mode to be used when recording / playing back video data in the video processing system 200. Next, the configuration unit 5 requests information on the size of pages PA and erase blocks BL stored in the flash memory 33 of the storage 3 from the storage 3 (step S201 in FIG. 9). Upon receiving this request, the controller 35 of the storage 3 reads information on the size of pages PA and erase blocks BL from the memory unit 37 and transmits this information to the configuration unit 5 (step S202 in FIG. 9).

[0125] Thereafter, the configuration unit 5 sets time slots TS for transmitting and receiving video data via video channels CH1, CH2, ... CHm+n. After setting the time slots TS, the configuration unit 5 transmits the setting information of the time slots TS to the arbitration unit 6 (step S203 in FIG. 9). The configuration unit 5 also transmits the setting information of the time slots TS to the information processing device 1 (step S204 in FIG. 9, step S11 in FIG. 10).

[0126] Based on the settings of the received time slot TS, the CPU 11 of the information processing device 1 sets up the information processing device 1. Specifically, the CPU 11 determines the sizes of buffer areas BF1, BF2, ..., BFm+n to be allocated to the video channels CH1, CH2, ..., CHm+n, respectively, and reserves the buffer areas BF1, BF2, ..., BFm+n in the RAM 14 (step S12 in FIG. 10).

[0127] After securing buffer areas BF1, BF2, ..., BFm+n, in the video processing system 200, transmission and reception (recording / reading of video data) of video data is performed between the information processing device 1, the multiple video input / output devices 2 (video output device 2a, video input device 2b), and the storage 3. When a user issues a command using the information processing device 1 or the like to output video data from the video output device 2a, the video data is output from each video output device 2a (step S205 in FIG. 9 ).

[0128] When a predetermined process is commanded as an interrupt process while transmission and reception of video data is being performed, the CPU 11 of the information processing device 1 stores the interrupt command for executing the interrupt process in the process waiting queue QU.

[0129] During transmission and reception of video data, when the current time reaches the start time of a certain short slot SS within a certain time slot TS, the CPU 11 of the information processing device 1 outputs an access request to the arbitration unit 6 for the video channel assigned to that short slot SS (any of video channels CH1, CH2, ... CHm+n) (step S206 in Figure 9, step S13 in Figure 10).

[0130] If the arbitration unit 6 does not grant access to the access request for the video channel assigned to the short slot SS executed at the current time ("No" in step S14 of FIG. 10), the CPU 11 determines to execute transmission and reception of video data in the next short slot SS (step S17 of FIG. 10), and executes steps S13 to S15 in the next short slot SS. In the example of FIG. 9, access is not granted to the access request for video channel CHp, and transmission and reception of video data (recording of video data) at this time is skipped.

[0131] In this way, if access permission is not issued for a certain short slot SS, the CPU 11 skips sending and receiving video data in that short slot SS. This reduces the time required to send and receive video data in the current time slot TS by the time of the short slot SS for which access permission was not issued. As a result, there is a vacant period between the end of sending and receiving video data in the current time slot TS and the start time of the next time slot TS.

[0132] On the other hand, if access is permitted by the arbitration unit 6 (step S207 in Figure 9, step S14 in Figure 10: "Yes"), the CPU 11 of the information processing device 1 performs transmission and reception of video data in the small slot SS (steps S208 to S210 in Figure 9, step S15 in Figure 10).

[0133] Specifically, when recording video data, the CPU 11 buffers the video data acquired from the video channel to be recorded in a buffer area, and transmits the buffered data buffered in the buffer area to the storage 3 (step S208 in Figure 9).

[0134] On the other hand, when reading video data, the CPU 11 reads the specified video data from the storage 3 and buffers the video data read from the storage 3 in a buffer area assigned to the video channel to which the video data is to be transmitted (step S209 in FIG. 9).The CPU 11 also transmits the buffered data buffered in the buffer area to the video input device 2b connected to the video channel to which the video data is to be transmitted (step S210 in FIG. 9).

[0135] Even if video data transmission and reception is performed in a certain short slot SS, if the transmission and reception of the video data is completed in a time shorter than the time allotted to that short slot SS, the time required to transmit and receive the video data in the current time slot TS is reduced by the time from the end of the transmission and reception of the video data in that short slot SS to the start of the next short slot SS. As a result, there is a vacant period between the end of the transmission and reception of the video data in the current time slot TS and the start time of the next time slot TS.

[0136] After transmitting and receiving video data in the current short slot SS, the CPU 11 of the information processing device 1 determines whether or not video data has been transmitted and received in all short slots SS included in the current time slot TS (step S16 in FIG. 10).

[0137] If there is a short slot SS within the current time slot TS that is not currently transmitting or receiving video data ("No" in step S16 of Figure 10), the CPU 11 decides to execute the next short slot SS (step S17 of Figure 10) and executes steps S13 to S15 in the next short slot SS.

[0138] On the other hand, if transmission and reception of video data has been performed in all small slots SS within the current time slot TS, i.e., if the current small slot SS is the last small slot in the current time slot TS ("Yes" in step S16 of Figure 10), transmission and reception of video data in the current time slot TS is terminated.

[0139] When the transmission and reception of video data in the current time slot TS is completed, the arbitration unit 6 determines whether the time from the completion of the transmission and reception of video data in the current time slot TS to the start of the time slot TS allocated next to the current time slot TS is equal to or longer than the time required to execute the interrupt process.

[0140] This determination can be made, for example, based on at least one of the difference between the time when transmission and reception of video data in the current time slot TS ends and the time when the next time slot TS starts, and the amount of buffered data in buffer areas BF1, BF2, ... BFm+n at the time when transmission and reception of video data in the current time slot TS ends.

[0141] If it is determined that the time until the start of the next time slot TS is shorter than the time required to execute the interrupt process and that the interrupt process cannot be executed in the current time slot TS, the arbitration unit 6 does not send permission to execute the interrupt process to the information processing device 1.

[0142] On the other hand, if it is determined that the time until the start of the next time slot TS is longer than the time required to execute the interrupt processing and that the interrupt processing can be executed in the first time slot, the arbitration unit 6 sends permission to execute the interrupt processing to the information processing device 1 (step S211 in Figure 9).

[0143] If permission to execute interrupt processing has not been received from the arbitration unit 6 and interrupt processing cannot be executed ("No" in step S18 of Figure 10), the CPU 11 of the information processing device 1 decides to execute transmission and reception of video data in the next time slot TS without executing the interrupt processing stored in the processing waiting queue QU (step S19 of Figure 10), and executes steps S13 to S21 of Figure 10 in the next time slot TS.

[0144] On the other hand, if permission to execute interrupt processing has been received from the arbitration unit 6 and the interrupt processing can be executed (step S211 in FIG. 9 and "Yes" in step S18 in FIG. 10), the CPU 11 determines whether an interrupt command is stored in the processing waiting queue QU (step S20 in FIG. 10).

[0145] If no interrupt command is stored in the processing queue QU ("No" in step S20 of FIG. 10), the CPU 11 decides to execute transmission and reception of video data in the next time slot TS (step S19 of FIG. 10), and executes steps S13 to S21 of FIG. 10 in the next time slot TS.

[0146] On the other hand, if an interrupt command is stored in the processing waiting queue QU ('Yes' in step S20 of Figure 10), the CPU 11 executes the interrupt command stored in the processing waiting queue QU to perform interrupt processing after the transmission and reception of video data is completed in the current time slot TS (steps S212 to S213 of Figure 9, step S21 of Figure 10).

[0147] For example, if the interrupt processing is a process of reading video data via video channel CHm+q, after the current time slot TS ends and before the next time slot TS starts, the CPU 11 reads the designated video data from the storage 3 and buffers the video data read from the storage 3 in the buffer area BFm+q assigned to the video channel CHm+q (step S212 in FIG. 9).The CPU 11 also transmits the buffered data buffered in the buffer area BFm+q to the video input device 2b connected to the video channel CHm+q (step S213 in FIG. 9).

[0148] After executing the interrupt process in the current time slot TS, the CPU 11 determines to execute transmission and reception of video data in the next time slot TS (step S19 in FIG. 10), and executes steps S13 to S21 in FIG. 10 in the next time slot TS.

[0149] In the video processing system 200 of the second embodiment, if the time from the end of transmission and reception of video data in a first time slot of the multiple time slots TS to the start of a second time slot allocated after the first time slot is equal to or longer than the time required to execute the interrupt process, the interrupt process is executed in the first time slot. This prevents the creation of wasted free time in the time slot TS where no process is executed, thereby enabling efficient information processing in the video processing system 200.

[0150] [3. Third Embodiment] In the first and second embodiments described above, the interrupt process is a process of reading video data to be read preferentially from the storage 3. The interrupt process is not limited to this. In the video processing system 300 of the third embodiment, a process of reading video data to be read ahead (referred to as pre-read video data) from the storage 3 in advance is executed as the interrupt process.

[0151] Fig. 11 is a block diagram showing the configuration of a video processing system 300 of the third embodiment. As shown in Fig. 11, the video processing system 300 of the third embodiment has the same configuration and functions as the video processing systems 100 and 200 of the first and second embodiments, except that it includes an information processing device 1' instead of the information processing device 1 of the first and second embodiments, and the interrupt processing is the reading of pre-fetched video data. Therefore, the following will describe only the parts that are different from the video processing systems 100 and 200 of the first and second embodiments, and will not describe in detail other matters.

[0152] The configuration of an information processing device 1' according to the third embodiment will be described with reference to Fig. 12. Fig. 12 is a block diagram showing the configuration of the information processing device 1' according to the third embodiment. The information processing device 1' includes a CPU 11', a video interface 12', a storage interface 13', a RAM 14', a storage device 15', an interface 16', and a prefetch data storage device 17'.

[0153] The CPU 11', video interface 12', storage interface 13', RAM 14', storage device 15', and interface 16' have the same configurations and functions as the CPU 11, video interface 12, storage interface 13, RAM 14, storage device 15, and interface 16 described in the first embodiment, respectively, and therefore will not be described here.

[0154] The pre-read data storage device 17′ stores pre-read video data that has been read in advance from the storage 3. The pre-read data storage device 17′ is, for example, a memory (such as a RAM) connected to a local bus of the information processing device 1′. The local bus to which the pre-read data storage device 17′ is connected is, for example, a CXL (Compute Express Link).

[0155] The pre-read video data is, for example, video data that is estimated to be required by a user, etc. The pre-read video data stored in the pre-read data storage device 17′ has a size that is an integral multiple of the GOP, similar to the video data read by interrupt processing in the first and second embodiments.

[0156] Next, the operation of the video processing system 300 in the third embodiment will be described with reference to Fig. 13 and Fig. 14. Fig. 13 is a sequence diagram showing signal transmission and reception in the video processing system 300 in the third embodiment. Fig. 14 is a flowchart showing the operation of the information processing device 1' in the video processing system 300 in the third embodiment.

[0157] First, the user instructs the configuration unit 5 on the mode to be used when recording / playing back video data in the video processing system 300. Next, the configuration unit 5 requests information on the size of pages PA and erase blocks BL stored in the flash memory 33 of the storage 3 from the storage 3 (step S301 in FIG. 13). Upon receiving this request, the controller 35 of the storage 3 reads information on the size of pages PA and erase blocks BL from the memory unit 37 and transmits this information to the configuration unit 5 (step S302 in FIG. 3).

[0158] Thereafter, the configuration unit 5 sets time slots TS for transmitting and receiving video data via video channels CH1, CH2, ... CHm+n. After setting the time slots TS, the configuration unit 5 transmits the setting information of the time slots TS to the arbitration unit 6 (step S303 in FIG. 13). The configuration unit 5 also transmits the setting information of the time slots TS to the information processing device 1' (step S304 in FIG. 13, step S31 in FIG. 14).

[0159] The CPU 11′ of the information processing device 1′ sets up the information processing device 1′ based on the settings of the received time slot TS. Specifically, the CPU 11′ determines the sizes of buffer areas BF1, BF2, ..., BFm+n to be allocated to the video channels CH1, CH2, ..., CHm+n, respectively, and reserves the buffer areas BF1, BF2, ..., BFm+n in the RAM 14′ (step S32 in FIG. 14).

[0160] After securing buffer areas BF1, BF2, ..., BFm+n, in the video processing system 300, transmission and reception (recording / reading of video data) of video data is performed between the information processing device 1', the multiple video input / output devices 2 (video output device 2a, video input device 2b), and the storage 3. When a user issues a command to output video data from the video output device 2a using the information processing device 1' or the like, the video data is output from each video output device 2a (step S305 in FIG. 13 ).

[0161] When a command to read pre-read video data is issued as an interrupt process while video data is being transmitted or received, the CPU 11' of the information processing device 1' stores a command to read pre-read video data (pre-read command) in the processing queue QU.

[0162] During transmission and reception of video data, when the current time reaches the start time of a certain short slot SS within a certain time slot TS, the CPU 11' determines whether or not pre-read video data is stored in the pre-read data storage device 17' (step S33 in Figure 14).

[0163] If the pre-read video data is stored in the pre-read data storage device 17' ("Yes" in step S33 of FIG. 14), the CPU 11' reads the pre-read video data from the pre-read data storage device 17' and inputs the pre-read video data to the video input device 2b designated as input (step S306 of FIG. 13, step S34 of FIG. 14). Thereafter, transmission and reception of video data in the current short slot SS is executed (steps S307 to S311 of FIG. 13, steps S35 to S39 of FIG. 14).

[0164] On the other hand, if the pre-read video data is not stored in the pre-read data storage device 17' ('No' in step S33 of Figure 14), the CPU 11' performs transmission and reception of video data in the current small slot SS without reading the pre-read video data (steps S307 to S311 of Figure 13, steps S35 to S39 of Figure 14).

[0165] Transmission and reception of video data in a short slot SS is performed as follows: First, the CPU 11′ of the information processing device 1′ outputs an access request for the video channel (any of video channels CH1, CH2, . . . CHm+n) assigned to the current short slot SS to the arbitration unit 6 (step S307 in FIG. 13, step S35 in FIG. 14).

[0166] If the arbitration unit 6 does not grant access to the access request for the video channel assigned to the current short slot SS ('No' in step S36 of Figure 14), the CPU 11' decides to execute the next short slot SS (step S37 of Figure 14) and executes steps S33 to S39 in the next short slot SS.

[0167] On the other hand, if access is permitted by the arbitration unit 6 (step S308 in FIG. 13, "Yes" in step S36 in FIG. 14), the CPU 11' executes transmission and reception of video data in the current small slot SS (steps S309 to S311 in FIG. 13, step S38 in FIG. 14).

[0168] Specifically, when recording video data, the CPU 11' buffers the video data acquired from the video channel to be recorded in a buffer area, and transmits the buffered data buffered in the buffer area to the storage 3 (step S309 in Figure 13).

[0169] On the other hand, when reading video data, the CPU 11' reads the designated video data from the storage 3 and buffers the video data read from the storage 3 in a buffer area assigned to the video channel to which the video data is to be transmitted (step S310 in FIG. 13). The CPU 11' also transmits the buffered data buffered in the buffer area to the video input device 2b connected to the video channel to which the video data is to be transmitted (step S311 in FIG. 13).

[0170] After transmitting and receiving video data in the current short slot SS, the CPU 11' of the information processing device 1' determines whether or not video data has been transmitted and received in all short slots SS included in the current time slot TS (step S39 in FIG. 14).

[0171] If there is a short slot SS within the current time slot TS that is not currently transmitting or receiving video data ("No" in step S39 of Figure 14), the CPU 11 decides to execute the next short slot SS (step S37 of Figure 14) and executes steps S33 to S39 in the next short slot SS.

[0172] On the other hand, if transmission and reception of video data has been performed in all small slots SS within the current time slot TS, that is, if the current small slot SS is the last small slot in the current time slot TS ("Yes" in step S39 of Figure 14), transmission and reception of video data in the current time slot TS is terminated.

[0173] When transmission and reception of video data in the current time slot TS is completed, the arbitration unit 6 judges whether or not the time from the completion of transmission and reception of video data in the current time slot TS to the start of the time slot TS allocated next to the current time slot TS is equal to or longer than the time required for pre-reading the pre-read video data.

[0174] This determination can be made, for example, based on at least one of the difference between the time when transmission and reception of video data in the current time slot TS ends and the time when the next time slot TS starts, and the amount of buffered data in buffer areas BF1, BF2, ... BFm+n at the time when transmission and reception of video data in the current time slot TS ends.

[0175] When it is determined that the time until the start of the next time slot TS is shorter than the time required for pre-reading the pre-read video data and pre-reading of the pre-read video data cannot be executed in the current time slot TS, the arbitration unit 6 does not transmit permission to execute interrupt processing to the information processing device 1.

[0176] On the other hand, if it is determined that the time until the start of the next time slot TS is longer than the time required to pre-read the pre-read video data and that pre-reading of the pre-read video data can be performed in the first time slot, the arbitration unit 6 sends permission to execute interrupt processing to the information processing device 1 (step S312 in Figure 13).

[0177] If permission to execute interrupt processing has not been received from the arbitration unit 6 and pre-reading of pre-read video data is not possible ('No' in step S40 of Figure 14), the CPU 11' of the information processing device 1' decides to execute transmission and reception of video data in the next time slot TS without executing the pre-read command stored in the processing waiting queue QU (step S41 of Figure 14), and executes steps S33 to S42 in the next time slot TS.

[0178] On the other hand, if permission to execute interrupt processing has been received from the arbitration unit 6 and pre-reading of the pre-read video data can be performed (step S312 in Figure 13, step S40 in Figure 14: "Yes"), the CPU 11' executes the pre-read command stored in the processing waiting queue QU and reads out the pre-read video data (step S42 in Figure 14).

[0179] Specifically, the CPU 11′ reads the video data designated as the pre-read video data from the storage 3 and stores the read video data in the pre-read data storage device 17′ (step S313 in FIG. 13). The video data stored in the pre-read data storage device 17′ is input to the video input device 2b designated as the pre-read video data by executing the above-mentioned step S34.

[0180] If no pre-read command is stored in the processing queue QU, step S42 is not executed, and steps S33 to S42 are executed in the next time slot TS.

[0181] In the video processing system 300 of the third embodiment, if the time from the end of transmission and reception of video data in a first time slot of the multiple time slots TS to the start of a second time slot allocated after the first time slot is equal to or longer than the time required to execute pre-reading of pre-read video data, pre-reading of the pre-read video data is executed as an interrupt process in the first time slot. This prevents the occurrence of wasted free time in the time slot TS where no processing is executed, thereby enabling efficient information processing in the video processing system 100.

[0182] Furthermore, in the video processing system 300 of the third embodiment, the pre-read video data stored in the pre-read data storage device 17' can be input to the designated video input device 2b in each of the multiple short slots SS included in the time slot TS. This allows, for example, after a command is issued to input pre-read video data to the designated video input device 2b, the pre-read video data can be immediately input to the designated video input device 2b in the short slot SS immediately after the command.

[0183] [4. Other Embodiments] While one embodiment of the present disclosure has been described above, the present disclosure is not limited to the above embodiment, and various modifications are possible without departing from the spirit and scope of the present disclosure. In particular, multiple embodiments and modifications described in this specification can be combined as needed.

[0184] (A) At least one of the processing content of each step and the order of steps shown in FIGS. 5, 6, 9, 10, 13, and 14 can be changed as appropriate without departing from the spirit of the invention.

[0185] (B) The connection relationship between the multiple video input / output devices 2 and the multiple video channels CH1, CH2, ... CHm+n of the information processing device 1 is not limited to the connection relationship described above. In the above embodiment, for ease of explanation, an example was shown in which a video output device 2a is connected to each of the multiple consecutive video channels CH1, CH2, ... CHm, and a video input device 2b is connected to each of the multiple consecutive video channels CHm+1, CHm+2, ... CHm+n.

[0186] However, the present invention is not limited to this, and the video output devices 2a and video input devices 2b may be connected randomly to the multiple video channels CH1, CH2, ... CHm+n. Furthermore, any number of video output devices 2a and video input devices 2b may be connected, and there may be a video channel to which no device is connected.

[0187] (C) Processing that can be executed as an interrupt process is not limited to reading video data that needs to be read with priority and pre-reading video data. For example, recording video data that needs to be recorded with priority may be executed as an interrupt process.

[0188] (D) The first to third embodiments described above may be combined. Specifically, in the video processing system, interrupt processing may be executed when there is free time in each small slot SS within a time slot TS (for example, if transmission and reception of video data in a small slot SS is skipped, and there is free time between the end of transmission and reception of video data in that small slot SS and the start of the next small slot SS), and further, when there is free time between the end of transmission and reception of video data in a first time slot and the start of the next second time slot).

[0189] Furthermore, as an interrupt process, both reading of video data that needs to be read with priority and pre-reading of pre-read video data may be executed.

[0190] [5. Supplementary Notes] (1) A video processing system (e.g., video processing systems 100, 200, 300) includes a storage (e.g., storage 3), an information processing device (e.g., information processing device 1, 1′), a configuration unit (e.g., configuration unit 5), and an arbitration unit (e.g., arbitration unit 6). The storage includes a nonvolatile memory unit (e.g., flash memory 33) that can write data in units of page size (e.g., page PA) and erase data in units of erase block size (e.g., erase block BL) consisting of multiple pages. The information processing device controls the transmission and reception of video data with the storage via multiple video channels (e.g., video channels CH1, CH2, ... CHm+n) to which video input / output devices (e.g., video input / output device 2, video output device 2a, video input device 2b) are connected. The configuration unit sets a time slot (e.g., time slot TS) having a predetermined length of time for transmitting and receiving video data based on the page size and erase block size of the storage. The arbitration unit determines the timing at which each video channel is permitted to access the storage based on the time slot settings.

[0191] In this video processing system, the information processing device transmits and receives video data to and from the storage via a plurality of video channels by transmitting and receiving video data to and from the storage via each of a plurality of video channels within a time slot at the timing determined by the arbitration unit. The information processing device also executes interrupt processing during free time in the time slot when no video data is being transmitted or received.

[0192] In the above video processing system, video data is transmitted and received to and from the storage via multiple video channels by transmitting and receiving video data to and from the storage via each of the multiple video channels within a time slot having a predetermined length. As a result, at a specific timing within the time slot, the communication bandwidth can be monopolized for transmitting and receiving video data to and from the storage via one video channel. As a result, the speed of transmitting and receiving video data to and from the storage via the video channels does not decrease.

[0193] Furthermore, in the above video processing system, interrupt processing is performed during the free time in a time slot when no video data is being transmitted or received, thereby preventing the video processing system from wasting time during which no processing is being performed, thereby enabling efficient information processing in the video processing system.

[0194] (2) In the video processing system of (1) above, the information processing device may assign small slots (e.g., small slots SS) within a time slot for transmitting and receiving video data to each of the multiple video channels, thereby transmitting and receiving video data to and from the storage via each of the multiple video channels. In this case, if the information processing device can skip transmitting and receiving video data to and from the storage via the video channel in the small slot, it may execute interrupt processing in the small slot.

[0195] This prevents the occurrence of wasted short slots in which no processing is performed in the video processing system, thereby enabling information processing in the video processing system to be carried out efficiently.

[0196] (3) In the video processing system of (1) or (2) above, the information processing device may have a temporary storage unit (e.g., buffer areas BF1, BF2, ... BFm+n). The temporary storage unit buffers video data transmitted to and received from storage via each of a plurality of video channels. In this case, the information processing device may determine whether to execute interrupt processing in a short slot based on the amount of video data buffered in the temporary storage unit assigned to the video channel that transmits and receives video data in the short slot.

[0197] This allows interrupt processing to be performed at an appropriate timing while preventing interruptions in transmission and reception of video data between a plurality of video input / output devices, information processing devices, and storage due to an excess or shortage of buffered data.

[0198] (4) In any of the video processing systems (1) to (3), the information processing device may be capable of repeatedly transmitting and receiving video data to and from the storage via multiple video channels by sequentially allocating multiple time slots. In this case, the information processing device may execute interrupt processing in the first time slot if the time from the end of transmission and reception of video data in a first time slot of the multiple time slots to the start of a second time slot allocated after the first time slot is equal to or longer than the time required for interrupt processing.

[0199] This prevents the occurrence of wasted free time during a time slot in which no processing is performed, thereby enabling efficient information processing in the video processing system.

[0200] (5) In any of the video processing systems (1) to (4) above, the interrupt process may be a process of reading video data to be read preferentially from storage, thereby enabling the video data to be read preferentially immediately without delay.

[0201] (6) In any of the video processing systems (1) to (5) above, the interrupt process may be a process of reading video data from storage in advance, thereby enabling the pre-read video data to be output immediately without delay.

[0202] (7) In any of the video processing systems (1) to (6) above, the nonvolatile memory unit may be configured with a NAND element. In this case, the read access size of the video data in the interrupt process may be determined based on the size of a page, which is the unit of data writing in the NAND element, and the number of parallel NAND elements. This reduces the time required to execute the interrupt process, thereby increasing the probability of the interrupt process being executed.

[0203] (8) In any of the video processing systems (1) to (7) above, if the video data read by the interrupt process is inter-frame compressed video data, the size of the video data read by the interrupt process may be determined based on the size of the GOP of the video data. This prevents the video data read by the interrupt process from being cut off midway.

[0204] (9) The information processing device is an information processing device connected to a storage and having multiple video channels connected to a video input / output device. The information processing device has an information processing unit (e.g., CPUs 11 and 11'). The storage has a non-volatile memory unit that can write data in page-size units and erase data in erase block-size units consisting of multiple pages. The information processing unit transmits and receives video data to and from the storage via each of the multiple video channels at predetermined timings within a time slot having a predetermined length, thereby transmitting and receiving video data to and from the storage via the multiple video channels, and executes interrupt processing during free time within the time slot when video data is not being transmitted or received.

[0205] In the information processing device, video data is transmitted and received with the storage via multiple video channels by sequentially transmitting and receiving video data with the storage via each of the multiple video channels within a time slot having a predetermined length. As a result, at a specific timing within the time slot, the communication bandwidth can be monopolized for transmitting and receiving video data with the storage via one video channel. As a result, the speed of transmitting and receiving video data with the storage via the video channels does not decrease.

[0206] Furthermore, the information processing device executes interrupt processing during the free time in the time slot when no video data is being transmitted or received, thereby preventing the information processing device from wasting time during which no processing is being performed, thereby enabling the information processing device to perform information processing efficiently.

[0207] (10) A control method is a method for controlling transmission and reception of video data to and from storage via multiple video channels in an information processing device having multiple video channels connected to a video input / output device. The storage has a non-volatile memory unit that allows data to be written in page-size units and data to be erased in erase block-size units consisting of multiple pages. The control method includes the following steps. The following steps (a) and (b) do not limit the order of processing.

[0208] (a) A step of transmitting and receiving video data with the storage via a plurality of video channels by transmitting and receiving video data with the storage via each of the plurality of video channels at a predetermined timing within a time slot having a predetermined length of time.

[0209] (b) A step of executing an interrupt process during a vacant time in a time slot when no video data is being transmitted or received.

[0210] In the above control method, video data is transmitted and received with the storage via multiple video channels by transmitting and receiving video data with the storage via each of multiple video channels within a time slot having a predetermined length. As a result, at a specific timing within the time slot, the communication bandwidth can be monopolized for transmitting and receiving video data with the storage via one video channel. As a result, the speed of transmitting and receiving video data with the storage via the video channels does not decrease.

[0211] Furthermore, in the above control method, interrupt processing is performed during the free time in the time slot when no video data is being transmitted or received, thereby preventing the occurrence of wasted time when no processing is being performed, and enabling efficient information processing.

[0212] The present disclosure can be widely applied to the transmission and reception of video data in storage.

[0213] 100, 200, 300: Video processing system 1, 1': Information processing device 11, 11': CPU 12, 12': Video interface CH1 to CHm+n: Video channel 13, 13': Storage interface 14, 14': RAM BF1 to BFm+n: Buffer area QU: Processing queue 15, 15': Storage device 16, 16': Interface 17': Read-ahead data storage device 2: Video input / output device 2a: Video output device 2b: Video input device 3: Storage 31: Access port 33: Flash memory RA: Recording area PA: Page BL: Erase block 35: Controller 37: Storage unit 5: Configuration unit 6: Arbitration unit TS: Time slot SS: Small slot

Claims

1. A video processing system comprising: a storage having a non-volatile memory unit in which data can be written in page size units and data can be erased in erase block size units consisting of multiple pages; an information processing device that controls the transmission and reception of video data to and from the storage via multiple video channels connected to video input / output devices; a configuration unit that sets time slots having a predetermined length of time for transmitting and receiving the video data based on the page size and erase block size of the storage; and an arbitration unit that determines the timing of allowing each video channel to access the storage based on the setting of the time slot, wherein the information processing device transmits and receives video data to and from the storage via each of the multiple video channels within the time slot at the timing determined by the arbitration unit, and performs interrupt processing during free time in the time slot when the video data is not being transmitted or received.

2. The video processing system of claim 1, wherein the information processing device transmits and receives video data to and from storage via each of the plurality of video channels by allocating small slots within the time slot for transmitting and receiving video data to each of the plurality of video channels, and executes the interrupt processing in the small slot if transmission and reception of video data to and from the storage via the video channel in the small slot can be skipped.

3. The video processing system of claim 2, wherein the information processing device has a temporary storage unit that buffers video data sent and received to the storage via each of the multiple video channels, and determines whether or not to execute the interrupt processing in the small slot based on the amount of video data buffered in the temporary storage unit assigned to the video channel that sends and receives video data in that small slot.

4. The video processing system of claim 1, wherein the information processing device is capable of repeatedly transmitting and receiving video data to and from the storage via the multiple video channels by sequentially allocating multiple time slots, and executes the interrupt processing in the first time slot if the time from the end of transmission and reception of video data in a first time slot of the multiple time slots to the start of a second time slot allocated after the first time slot is longer than the time required for the interrupt processing.

5. The video processing system according to claim 1, wherein the interrupt processing is processing for reading video data to be read preferentially from the storage.

6. The video processing system according to claim 1, wherein the interrupt processing is processing for reading video data from the storage in advance.

7. The video processing system according to claim 1, wherein the nonvolatile memory unit is configured with NAND elements, and the read access size of the video data in the interrupt processing is determined based on the size of a page, which is the unit of data writing in the NAND elements, and the number of parallel NAND elements.

8. The video processing system of claim 1, wherein, when the video data read by executing the interrupt processing is inter-frame compressed video data, the size of the video data read by executing the interrupt processing is determined based on the size of a GOP of the video data.

9. An information processing device connected to a storage and having multiple video channels to which video input / output devices are connected, wherein the storage has a non-volatile memory unit that allows data to be written in page size units and data to be erased in erase block size units consisting of multiple pages, the information processing device has an information processing unit that controls transmission and reception of video data with the storage via the multiple video channels, the information processing unit transmits and receives video data to and from the storage via the multiple video channels by transmitting and receiving video data to and from the storage via each of the multiple video channels within a time slot having a predetermined length at a predetermined timing, and executes interrupt processing during free time within the time slot when the video data is not being transmitted or received.

10. A control method for controlling the transmission and reception of video data with storage via the multiple video channels in an information processing device having multiple video channels connected to a video input / output device, wherein the storage has a non-volatile memory unit that allows data to be written in page size units and data to be erased in erase block size units consisting of multiple pages, the control method comprising: a step of transmitting and receiving video data with the storage via the multiple video channels by transmitting and receiving video data with the storage via each of the multiple video channels within a time slot having a predetermined length at a predetermined timing; and a step of executing interrupt processing during free time within the time slot when the video data is not being transmitted or received.

Images