Video processing system, information processing device, and control method

Abstract

A video processing system (100) includes a plurality of video input / output devices (2), a storage (3), and an information processing device (1). The information processing device (1) sequentially transmits and receives video data between each of a plurality of video channels (CH1, CH2, . . . CHm+n) and a storage (3) within a time slot (TS) having a prescribed time length. If a time from when transmission and reception of video data in a first time slot from among a plurality of time slots (TS) is completed to when a second time slot allocated after the first time slot starts is equal to or longer than a time required for an erasing process to erase erasable data from the storage (3), the information processing device (1) executes the erasing process after completing transmission and reception of video data in the first time slot.

Description

Video processing system, information processing device, and control method

[0001] The present disclosure relates to a video processing system, an information processing device, and a control method for recording and reading video data.

[0002] A system is known that records video data output from a video output device such as a camera in a recording device and reads the video data recorded in the recording device. A known recording device for recording video data is a recording device configured with a NAND element. This recording device is known as a solid state drive (SSD), for example.

[0003] When recording data such as video data in storage, it is known to reduce the amount of data collected if the total rate of collected data exceeds the throughput parameters of the network infrastructure (see, for example, Patent Document 1).

[0004] Special Publication No. 2020-530159

[0005] Currently, recording and playback of video data between a video input / output device and a storage device configured with a NAND element is being considered. If multiple video data are simultaneously recorded without any control over the transmission and reception of the data between the video input / output device and the storage device, a large amount of data will be transmitted and received between the video input / output device and the storage device, resulting in a decrease in the transmission and reception speed of the video data.

[0006] Furthermore, video data deleted from a file system by user operation or the like may remain recorded as valid data in the storage. In storage configured with NAND elements, new data cannot be recorded (overwritten) in an area where data has been recorded. As the recording area where unnecessary data deleted from a file system by user operation is recorded increases, the recording area available for recording new data decreases. Furthermore, repeated recording and deletion causes fragmentation of video data. When such fragmentation of video data occurs, a process is required to aggregate the data of multiple fragmented blocks into a separate area before recording the data, which reduces the recording / playback rate of the video data.

[0007] To solve this problem, storage devices configured with NAND elements may perform a process to notify the storage device of video data deleted by user operation. This process is called "trim." Valid data that is fragmented is moved to another area to create a contiguous deleted area. Then, by performing this trim process on this area, the data deleted by user operation is physically erased from the storage device's recording area, making it possible to record new data in that recording area. As a result, video data can be recorded in a contiguous recording area, thereby suppressing fragmentation of the video data.

[0008] However, if the above process is executed without any control, it may be executed at the timing when video data is being transmitted and received between the storage and the video input / output device, which may cause the transmission and reception of video data to stop, resulting in a decrease in the processing speed of the video data.

[0009] The present disclosure aims to suppress a decrease in the speed of sending and receiving video data between a plurality of video input / output devices and storage configured with NAND elements.

[0010] The video processing system disclosed herein includes a storage device, an information processing device, a configuration unit, and an arbitration unit. If the storage device has a spare area of ​​a predetermined size or more, it can record data in the spare area in units of pages. On the other hand, if the spare area does not have a predetermined size or more, all valid data in an erase block in which invalid data is recorded is moved to another erase block, and all data in the source erase block is erased in units of erase blocks before data can be recorded. An erase block is made up of multiple pages. The information processing device controls the transmission and reception of video data with the storage device via multiple video channels connected to video input / output devices. The configuration unit sets a time slot having a predetermined length of time for transmitting and receiving video data based on the page size and erase block size of the storage device. The arbitration unit determines the timing at which each video channel is permitted to access the storage device based on the time slot setting.

[0011] In this video processing system, the information processing device transmits and receives video data to and from the storage via the multiple video channels by transmitting and receiving video data to and from the storage via each of the multiple video channels within the time slot at the timing determined by the arbitration unit. Also, the information processing device can repeatedly transmit and receive video data to and from the storage via the multiple video channels by sequentially allocating the multiple time slots.

[0012] In addition, if the time from when the transmission and reception of video data in a first time slot among the multiple time slots is completed to when the second time slot allocated after the first time slot begins is longer than the time required for the erasure process to erase erasable data from the storage, the information processing device executes the erasure process after the transmission and reception of video data in the first time slot is completed.

[0013] In the video processing system disclosed herein, video data is transmitted and received with the storage via multiple video channels by transmitting and receiving video data with the storage via each of multiple video channels within a time slot having a predetermined length. As a result, at a specific timing within the time slot, the communication bandwidth can be monopolized for transmitting and receiving video data with the storage via one video channel. As a result, the speed of transmitting and receiving video data with the storage does not decrease.

[0014] Furthermore, in the above video processing system, if the time from the end of transmission and reception of video data in a first time slot among the multiple time slots to the start of a second time slot allocated after the first time slot is equal to or longer than the time required for the erasure process to erase erasable data from the storage, the erasure process is executed after the end of transmission and reception of video data in the first time slot. In other words, the erasure process is executed if there is a sufficient time during which no video data is being transmitted or received between the end of transmission and reception of video data in the first time slot and the start of the next second time slot. As a result, the erasure process is not executed when video data is being transmitted or received, and therefore the speed of transmission and reception of video data with the storage does not decrease.

[0015] FIG. 1 is a block diagram showing the configuration of a video processing system. FIG. 2 is a block diagram showing the configuration of an information processing device. FIG. 3 is a block diagram showing the configuration of a storage. FIG. 4 is a diagram showing the configuration of a recording area. FIG. 5 is a sequence diagram showing signal transmission and reception in the video processing system. FIG. 6 is a flowchart showing the operation of the information processing device in the video processing system. FIG. 7 is a diagram showing the configuration of time slots. FIG. 8 is a flowchart showing the operation of the information processing device when recording video data. FIG. 9 is a flowchart showing the operation of the information processing device when reading video data.

[0016] Hereinafter, embodiments will be described in detail with reference to the drawings as appropriate. However, more detailed description than necessary may be omitted. For example, detailed description of already well-known matters or redundant description of substantially identical configurations may be omitted. This is to avoid unnecessary redundancy in the following description and to facilitate understanding by those skilled in the art. Note that the inventors provide the accompanying drawings and the following description to enable those skilled in the art to fully understand the present disclosure, and do not intend for them to limit the subject matter described in the claims.

[0017] In this disclosure, "video data" refers to data including video data, audio data, and metadata, data including only video data, and data including still image data.

[0018] [1. First Embodiment] [1-1. Video Processing System] Hereinafter, a video processing system 100 according to the present disclosure will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the video processing system 100. The video processing system 100 can record video data output from a video input / output device 2 in a storage 3 of the video processing system 100. The video data recorded in the storage 3 is used, for example, for future playback and editing. Editing of video data includes, for example, generating new video data by inserting a specific portion of other video data into video data.

[0019] Furthermore, the video processing system 100 can output video data read from the storage 3 to the video input / output device 2 .

[0020] The configuration of the video processing system 100 will be described below with reference to Fig. 1. The video processing system 100 includes an information processing device 1, a storage 3, a configuration unit 5, and an arbitration unit 6.

[0021] The information processing device 1 is connected to a video input / output device 2 and a storage 3 , and controls transmission and reception of video data between the video input / output device 2 and the storage 3 .

[0022] The video input / output device 2 includes a plurality of video output devices 2 a and a plurality of video input devices 2 b. The number of video output devices 2 a and video input devices 2 b included in the video input / output device 2 can be any number within the capacity allowed by the information processing device 1.

[0023] The video output device 2a acquires video and audio data, converts it into electrical signals, and outputs the data to the outside as video data. The video output device 2a is, for example, a video capture device equipped with a camera for capturing predetermined video, a microphone for capturing audio of the predetermined video, etc. Alternatively, the video output device 2a may be a media server that records a large number of videos. The video output from the video output device 2a is, for example, high-quality video such as uncompressed 4K video.

[0024] Video input device 2b inputs video and audio data as video data. Video input device 2b is, for example, a display (e.g., a liquid crystal display, an organic electroluminescence (EL) display, a plasma display, etc.) that plays back and displays the input video data. The video played back and displayed by video input device 2b is, for example, high-quality video such as uncompressed 4K video.

[0025] The video input / output device 2 may include a device that has both the function of the video output device 2a and the function of the video input device 2b.

[0026] The information processing device 1 receives video data from the video output device 2a and performs various information processing operations on the received video data. Specifically, for example, the information processing device 1 can convert the video data into compressed data. The information processing device 1 can also output the video data to an external device in uncompressed format. The information processing device 1 can edit the video data in accordance with user operations.

[0027] The information processing device 1 is capable of recording video data input from the video output device 2a, video data converted into a compressed format, edited video data, etc. in the storage 3. This allows the information processing device 1 to function as a recording device that records video data in the storage 3.

[0028] Furthermore, the information processing device 1 is capable of reading out video data recorded in the storage 3 and outputting the read-out video data to the video input device 2b, which allows the information processing device 1 to function as a playback device that plays back video data using the video input device 2b.

[0029] Although the image processing system 100 of the present embodiment is provided with one information processing device 1, the present invention is not limited to this. The number of information processing devices 1 provided in the image processing system 100 can be any number.

[0030] The storage 3 records video data received from the information processing device 1 in accordance with a command from the information processing device 1. The storage 3 also reads designated video data in accordance with a command from the information processing device 1. As will be described later, the storage 3 is a recording device configured with a NAND element. The storage 3 is, for example, a solid state drive (SSD). In the video processing system 100 of this embodiment, one storage 3 is provided, but two or more storages 3 may be provided. The number of storages 3 provided in the video processing system 100 can be any number.

[0031] The configuration unit 5 is connected to the information processing device 1, the storage 3, and the arbitration unit 6 (described later). The configuration unit 5 sets the configuration of the video processing system 100. The configuration unit 5 is, for example, hardware configured by circuits that realize the above functions. The configuration unit 5 may be a computer system that includes a CPU (Central Processing Unit), a storage device, various interfaces, etc. and realizes the above functions. The configuration unit 5 may realize some or all of the above functions by software.

[0032] The arbitration unit 6 is connected to the information processing device 1 and the configuration unit 5. When an access request to the storage 3 is made from the information processing device 1, the arbitration unit 6 determines whether or not to permit the information processing device 1 to access the storage 3, and notifies the information processing device 1 of the result of the determination.

[0033] The arbitration unit 6 is, for example, hardware configured with circuits that realize the above functions. The arbitration unit 6 may be a computer system that includes a CPU, a storage device, various interfaces, etc. and realizes the above functions. The arbitration unit 6 may realize some or all of the above functions by software.

[0034] [1-2. Information Processing Device] The configuration of the information processing device 1 will be described with reference to Fig. 2. Fig. 2 is a diagram showing the configuration of the information processing device 1. The information processing device 1 has a CPU 11, a video interface 12, a storage interface 13, a RAM (Random Access Memory) 14, a storage device 15, and an interface 16.

[0035] The CPU 11 executes various processes in the information processing device 1. Specifically, the CPU 11 executes information processes such as video data compression, information processing related to video data editing, and video data analysis. The CPU 11 executes the above processes by executing instructions indicated in a program stored in the storage device 15. Note that some of the processes in the information processing device 1 may be realized by hardware implemented separately from the CPU 11 or by an external device. The CPU 11 generates commands for executing various processes.

[0036] The video interface 12 connects the information processing device 1 and the video input / output device 2. The video interface 12 is provided with a plurality of connection terminals. One video output device 2a or one video input device 2b included in the video input / output device 2 may be connected to only one connection terminal of the video interface 12, or may be connected to a plurality of video channels.

[0037] The video interface 12 is an interface for connecting video-related devices, such as an interface conforming to the Serial Digital Interface (SDI) standard. Alternatively, the video interface 12 may be a network interface. In this case, transmission conforming to the ST2110 standard of the SMPTE standardization organization, for example, may be used. The video interface 12 may also be a network interface, such as a Gigabit Ethernet (registered trademark) interface, which connects the information processing device 1 to other devices via a network such as a WAN (Wide Area Network) or a LAN (Local Area Network).

[0038] A video channel is assigned to each of the multiple connection terminals of the video interface 12. The information processing device 1 shown in Fig. 2 has m+n connection terminals. Video channels CH1, ..., CHm+n are assigned to the m+n connection terminals, respectively. Video channels CH1, ..., CHm are assigned to the m connection terminals connected to the video output device 2a, respectively. Meanwhile, video channels CHm+1, ..., CHm+n are assigned to the n connection terminals connected to the video input device 2b, respectively.

[0039] 2, one video output device 2a or one video input device 2b is connected to one video channel, but this is not limiting. For example, one video output device 2a or one video input device 2b may be connected to multiple video channels.

[0040] The information processing device 1 transmits and receives video data between the multiple video channels CH1, ... CHm+n and the storage 3 by sequentially transmitting and receiving video data between each of the multiple video channels CH1, ... CHm+n and the storage 3 within a time slot TS (Figure 7) having a predetermined length of time.

[0041] Moreover, by sequentially allocating a plurality of time slots TS in chronological order, the information processing device 1 can repeatedly transmit and receive video data between the plurality of video channels CH1, ..., CHm+n and the storage 3. That is, after completing transmission and reception of video data in one time slot TS, the information processing device 1 transmits and receives video data in the next time slot TS, thereby repeatedly transmitting and receiving video data between the plurality of video channels CH1, ..., CHm+n and the storage 3.

[0042] The storage interface 13 connects the information processing device 1 and the storage 3. The storage interface 13 connects the information processing device 1 and the storage 3 via a direct transfer path. The storage interface 13 is, for example, a PCIe interface that complies with the PCI express standard of the PCI-SIG standard. This allows the information processing device 1 and the storage 3 to send and receive data at high speed using a protocol dedicated to non-volatile memory (NVMe (Non-Volatile Memory Express)) using a PCI-Express bus.

[0043] In NVMe, the controller acquires data from the NAND memory using the NAND protocol, converts it to the PCIe protocol, and transfers it to the host. In contrast, with conventional SATA (Serial-ATA), the DMA controller that transfers data directly to the host converts data from the NAND memory to the SATA protocol, acquires it, and then converts the data to the PCIe protocol before transferring it to the host. In other words, because NVMe processing directly converts from the NAND protocol to the PCIe protocol, the data transfer processing speed is faster than conventional SATA.

[0044] The RAM 14 is a storage area that temporarily stores commands, video data, etc. generated by the CPU 11. In the RAM 14, buffer areas BF1, BF2, ..., BFm+n are assigned to the video channels CH1, CH2, ..., CHm+n, respectively. The buffer areas BF1, BF2, ..., BFm+n are temporary storage areas that buffer the video data acquired via the corresponding video channels CH1, CH2, ..., CHm+n. The size of one buffer area is set to the access size, which is the size of video data that can be transmitted and received in one time slot, with a certain margin.

[0045] When recording video data input from the video output device 2a in the storage 3, the information processing device 1 buffers the video data in buffer areas BF1, ..., BFm assigned to the video channels CH1, ..., CHm to which the video output device 2a is connected, respectively. The video data buffered in the buffer areas is called "buffered data."

[0046] Specifically, when recording video data obtained by a certain video output device 2a in storage 3, the information processing device 1 buffers the video data obtained by the video output device 2a in a buffer area assigned to the video channel to which the video output device 2a is connected, and transmits the buffered data in the buffer area to storage 3.

[0047] On the other hand, when reading video data from storage 3 and outputting it to video input device 2b, information processing device 1 buffers the video data read from storage 3 in buffer areas BFm+1, ... BFm+n assigned respectively to video channels CHm+1, ... CHm+n to which video input device 2b is connected.

[0048] Specifically, when outputting video data read from storage 3 to a video input device 2b, the information processing device 1 buffers the video data read from storage 3 in a buffer area assigned to the video channel to which the video input device 2b is connected, and transmits the buffered data in the buffer area to the video input device 2b.

[0049] The storage device 15 is composed of a ROM (Read Only Memory), a hard disk (HDD), a solid state drive (SSD), etc. The storage device 15 stores programs executed by the CPU 11, settings related to the processing of the information processing device 1, parameters used for the processing, etc.

[0050] The interface 16 is an interface for connecting the information processing device 1 to other devices. The configuration unit 5 and the arbitration unit 6 are connected to the interface 16. The interface 16 is a network interface such as a Gigabit Ethernet (registered trademark) interface that connects the information processing device 1 to other devices via a network such as a WAN or LAN.

[0051] At least one of the storage interface 13 and the interface 16 may be capable of directly transmitting and receiving data between the RAM 14 of the information processing device 1 and a storage device of another device by remote direct memory access (RDMA), thereby enabling high-speed data transmission and reception between the information processing device 1 and the other device.

[0052] Note that the functions of at least one of the above-described configuration unit 5 and arbitration unit 6 may be realized by the information processing device 1. In this case, at least one of the configuration unit 5 and arbitration unit 6 does not need to be connected to the interface 16. In other words, when at least one of the configuration unit 5 and arbitration unit 6 is a device separate from the information processing device 1, at least one of the configuration unit 5 and arbitration unit 6, which is a separate device, is connected to the interface 16.

[0053] [1-3. Storage] The configuration of the storage 3 will be described using Fig. 3. Fig. 3 is a diagram showing the configuration of the storage 3. The storage 3 has an access port 31, a flash memory 33, a controller 35, and a storage unit 37. The access port 31 is an interface that connects the storage 3 to other devices. The information processing device 1 is connected to the access port 31.

[0054] The flash memory 33 is composed of multiple NAND elements. Fig. 4 is a diagram showing the configuration of the recording area of ​​the storage 3. As shown in Fig. 4, the flash memory 33 has a recording area RA for recording video data. In addition, the recording area RA stores a table that associates addresses (logical addresses) specified by an external device with addresses (physical addresses) of erase blocks BL corresponding to the logical addresses.

[0055] The recording area RA is divided into a plurality of erase blocks BL. An erase block BL is a unit of data erasure in the flash memory 33. An erase block BL is further divided into a plurality of pages PA. A page PA is a unit of data recording. When data in an erase block BL is erased in the flash memory 33, a process is executed in which the data contained in this erase block BL is moved to another erase block BL and then erased. As a result, the erase block BL from which data has been erased becomes a "free block" into which data can be written.

[0056] The recording area RA of the storage 3 is composed of a spare area and a user area. When the storage 3 starts to be used, all data in the recording area RA is physically erased, and then the entire recording area RA becomes the spare area. When a user writes data to the storage 3, the data is written to this spare area, and the area into which the data is written becomes the user area. Note that data can be written to the spare area in page PA units.

[0057] The upper limit size of the user area is a predetermined size that is smaller than the entire size of the recording area RA. In other words, the upper limit of the data writing size of the storage 3 that can be recognized by the user is the upper limit size of the user area. Furthermore, even after the user area reaches its upper limit size, a spare area remains in the recording area RA. The spare area remaining in the recording area RA is called a remaining spare area. This remaining spare area cannot be recognized by the user.

[0058] When a user deletes data from a user area on a file system, the deleted data from the user area simply becomes invalid and remains physically in the user area. In this state, when a user writes new data on the file system, the new data is written to the remaining spare area. Writing data to the remaining spare area is also done in page PA units.

[0059] When data is repeatedly deleted and new data is written in the file system, the amount of invalid data in the user area increases. The area in the remaining spare area where data can be written decreases. When the size of the area in the remaining spare area where data can be written falls below a predetermined size, the invalid data in the user area and the remaining spare area is physically erased.

[0060] As described above, data can only be erased in units of erase blocks BL in the storage 3. Therefore, the physical erasure of invalid data is performed by first moving all valid data present in the erase block BL in which the invalid data to be erased is recorded to another erase block BL to which data can be written (for example, an erase block BL in the remaining spare area to which data can be written), and then physically erasing all data (both invalid data and valid data) recorded in the erase block BL from which the valid data was moved (the erase block BL in which the invalid data to be erased was recorded) in units of erase blocks BL (garbage collection). After the data has been physically erased in this way, it becomes possible to write data in units of pages PA in the erase blocks BL.

[0061] As described above, in the storage 3, new data can be written in units of pages PA to unused areas and areas from which data has been erased as described above in the recording area RA. On the other hand, new data can be written to areas to which data has already been written after the data has been physically erased in units of erase blocks BL each consisting of a plurality of pages PA.

[0062] The controller 35 executes control related to the storage 3. In particular, the controller 35 controls the recording of data to the flash memory 33 and the reading of data from the flash memory 33. The controller 35 also executes other processes required for the solid state drive, such as garbage collection and wear leveling. The controller 35 executes the above processes by executing programs stored in the storage unit 37. The controller 35 may also realize the above processes by its own hardware.

[0063] As described above, even if video data recorded in the storage 3 is deleted by a user operation or the like in the information processing device 1 (on the file system of the information processing device 1), the controller 35 of the storage 3 cannot grasp this. Therefore, even if video data is deleted in the information processing device 1, the video data remains physically recorded in the flash memory 33 of the storage 3.

[0064] Furthermore, in the flash memory 33, when video data is deleted, added, or the contents of the video data are updated, if the video data that has become unnecessary as a result of these operations remains recorded, invalid pages PA will not exist in long succession, but will exist in fragments.

[0065] In this way, when new video data is to be recorded in flash memory 33 in a state where unnecessary video data remains and invalid pages PA exist in fragments, the valid video data recorded in the erase block BL containing the fragmented invalid page PA is aggregated into another erase block BL (for example, an erase block BL in a spare area), and the video data recorded in the source area is erased (garbage collected) in units of erase block BL before the new video data is recorded in flash memory 33.

[0066] When short, consecutive invalid pages PA are fragmented and exist in the flash memory 33, garbage collection is performed more frequently, which makes it take longer to record new video data.Furthermore, as a result of garbage collection being performed more frequently, the data transfer speed of the storage 3 decreases.

[0067] To prevent this, in the video processing system 100, the information processing device 1 moves erasable video data from the flash memory 33 of the storage 3 to consecutive addresses (for example, in a spare area of ​​the storage 3). After this movement, the information processing device 1 physically erases the erasable video data from the flash memory 33 in units of the erase blocks BL in which the video data was recorded. This makes it possible to record new video data in consecutive pages PA in the erase blocks BL after the video data has been erased. This process is called an erasure process.

[0068] That is, the erasure process comprises a data movement process for moving the video data to be erased (referred to as video data to be erased) from the currently recorded area (erase block BL) to another area (for example, an erase block BL in a spare area), and a physical erase process for physically erasing the video data to be erased from the currently recorded area after the data movement process. The data movement process is a process for securing a continuous area, i.e., continuous erase blocks BL. The physical erase process is a process for physically erasing data from the continuous area secured by the data movement process, and securing a continuous free area, i.e., continuous erase blocks BL in which no data is recorded.

[0069] The above erasure process physically erases from the flash memory 33 video data that does not need to be recorded therein, thereby securing many consecutive free pages PA onto which new video data can be recorded. As a result, new video data is more likely to be recorded in consecutive pages PA, which reduces the likelihood of video data fragmentation within the flash memory 33 and allows the data transfer speed of the storage 3 to be maintained at a high level.

[0070] Furthermore, as described above, in addition to the above erasure process, the controller 35 executes garbage collection on areas where data less than an erase block BL unit is recorded as needed, thereby ensuring many free erase blocks BL in the flash memory 33.

[0071] The storage unit 37 is provided as a memory separate from the flash memory 33, or is part of the recording area RA, and stores various parameters related to the control of the storage 3. The storage unit 37 stores, for example, the size of the page PA, the size of the erase block BL, the number of times data is recorded in each erase block BL, parameters for executing various processes, and the like.

[0072] 5 and 6, the operation of the video processing system 100 will be described. Fig. 5 is a sequence diagram showing signal transmission and reception in the video processing system 100. Fig. 6 is a flowchart showing the operation of the information processing device 1 in the video processing system 100.

[0073] First, the configuration unit 5 sets the configuration of the video processing system 100. Specifically, the following process is executed. First, the user instructs the configuration unit 5 on the mode (recording mode, playback mode) to be used when recording / playing back video data in the video processing system 100. The recording mode includes the recording rate of the video data (the amount of video data recorded per unit time), and the playback mode includes the playback rate of the video data (the amount of video data read out per unit time). These modes may be set individually for each of the video channels CH1, CH2, ..., CHm+n, or the same mode may be set for all of the video channels CH1, CH2, ..., CHm+n.

[0074] Next, the configuration unit 5 requests information about the size of pages PA and erase blocks BL stored in the flash memory 33 of the storage 3 from the storage 3 (step S101 in FIG. 5). Upon receiving this request, the controller 35 of the storage 3 reads information about the size of pages PA and erase blocks BL from the memory unit 37 and transmits this information to the configuration unit 5 (step S102 in FIG. 5).

[0075] Thereafter, the configuration unit 5 sets a time slot TS for transmitting and receiving video data via video channels CH1, CH2, ... CHm+n based on the mode, the size of the page PA received from the storage 3, the size of the erase block BL, etc. As shown in Fig. 7, a time slot TS is defined as a period having a predetermined time length T. Fig. 7 is a diagram showing the configuration of a time slot TS.

[0076] A time slot TS is composed of multiple small slots SS. A small slot SS is assigned to each video channel. In one time slot TS, video data transmitted and received on one video channel is transmitted and received within the period of the small slot SS assigned to that video channel. Hereinafter, the size of the video data transmitted and received within the period of one small slot SS will be referred to as the "access size." In other words, in the video processing system 100, data having the above access size is transmitted and received via one video channel at a period corresponding to the time length T of the time slot TS.

[0077] The configuration unit 5 can determine the access size for recording video data, i.e., the access size of the small slot SS to be assigned to video channels CH1, CH2, ... CHm, to be an integer multiple or more of the size of the erase block BL, and to a size that suppresses fragmentation of the video data.

[0078] On the other hand, the configuration unit 5 can determine the access size for reading video data, i.e., the access size of the short slots SS assigned to video channels CHm+1, CHm+2, ... CHm+n, to a size that allows video data to be reproduced without interruption at least during the time length T of the time slot TS. For example, if the reproduction rate of video data is eMbps, the access size for reading video data can be e*T (unit: Mbit).

[0079] Furthermore, the configuration unit 5 sets the duration of the small slots SS and the duration T of the time slots TS based on the determined access size, etc. For example, if the data transfer rate between the information processing device 1 and the storage 3 is bMbps and the access size of a particular video channel is determined to be cMB (8*cMbits), the duration of the small slots SS assigned to that video channel can be determined to be 8*c / b seconds. The duration T of the time slots TS can be the sum of the durations of the small slots SS assigned to multiple video channels CH1, CH2, ... CHm+n.

[0080] When determining the access size, consideration is also given to the sector size accessible to the storage 3. Specifically, for example, if the sector size is 4 KB, the access size is set to an integral multiple of 4 KB (sector size).

[0081] The time length T of the time slot TS and the access size are such that, even when video data is transmitted and received via each video channel at a period corresponding to the time length T of the time slot TS, the video data can be recorded without interruption at the set recording rate and played back without interruption at the set playback rate.

[0082] For example, if the maximum recording rate and playback rate of video data in the video processing system 100 is dMbps and the access size allocated to the video channel that transmits and receives the video data is cMB (8*cMbits), then the time length T of the time slot TS is set to c / d or less.

[0083] After completing the setting of the time slot TS, the configuration unit 5 transmits the setting information of the time slot TS (such as the time length T of the time slot TS and the access size) to the arbitration unit 6 (step S103 in FIG. 5). Having received the setting information of the time slot TS, the arbitration unit 6 determines, based on the setting of the time slot TS, when to permit each of the video channels CH1, CH2, ... CHm+n to access the storage 3.

[0084] Furthermore, the configuration unit 5 transmits the time slot setting information to the information processing device 1 (step S104 in FIG. 5). The CPU 11 of the information processing device 1 executes a process of receiving the time slot TS setting information transmitted from the configuration unit 5 (step S1 in FIG. 6).

[0085] Thereafter, the CPU 11 configures the information processing device 1 based on the settings of the received time slot TS. Specifically, the CPU 11 determines the reservation sizes of the buffer areas BF1, BF2, ..., BFm+n to be allocated to the video channels CH1, CH2, ..., CHm+n, respectively, based on the settings of the time slot TS (access sizes of each video channel), and reserves the buffer areas BF1, BF2, ..., BFm+n in the RAM 14 (step S2 in FIG. 6). The reservation size of each buffer area can be determined as the access size determined for the video channel to which the buffer area is allocated, plus a predetermined margin.

[0086] After reserving buffer areas BF1, BF2, ..., BFm+n, the CPU 11 of the information processing device 1 notifies the flash memory 33 of the video data that can be erased, physically erases the notified erasable video data from the flash memory 33, and calculates the time required for the erasure process to enable new video data to be recorded on the page PA after the video data has been erased (step S3 in Figure 6).

[0087] The time required for the erase process can be calculated, for example, by performing the erase process on data of the access size, measuring the processing time multiple times, and adding a predetermined margin to the worst value (i.e., the slowest processing time). Alternatively, if design values ​​for the storage 3 (e.g., the operating speeds of data movement, erasure, recording, etc., and the time required for the erase process itself) can be obtained from the storage 3 vendor, the obtained design values ​​can be used or the calculation can be based on them.

[0088] After measuring the time required for the erasure process, the CPU 11 of the information processing device notifies the arbitration unit 6 of the measured time required for the erasure process (step S105 in FIG. 5).

[0089] Thereafter, in the video processing system 100, transmission and reception of video data (recording / reading of video data) is performed between the information processing device 1, multiple video input / output devices 2 (video output device 2a, video input device 2b), and storage 3 (steps S106 to S113 in Figure 5, step S4 in Figure 6).

[0090] Details will be explained later, but in the video processing system 100, the information processing device 1 transmits and receives video data between the storage 3 and each of the multiple video channels CH1, CH2, ... CHm+n by sequentially transmitting and receiving video data between the storage 3 and each of the multiple video channels CH1, CH2, ... CHm+n within one time slot TS.

[0091] After completing the transmission and reception of video data in one time slot TS (first time slot), the CPU 11 of the information processing device 1 determines whether or not it has received permission to execute the erasure process from the arbitration unit 6 (step S5 in Figure 6).

[0092] The arbitration unit 6 determines whether the time from the end of transmission and reception of video data in the first time slot to the start of the time slot (second time slot) allocated after the first time slot is equal to or greater than the time required for the erasure process notified by the information processing device 1.

[0093] This determination can be made, for example, by determining whether the difference between the time when transmission and reception of video data in the first time slot ends and the time when the next second time slot starts is equal to or greater than the time required for the erasure process. For example, as shown in Figure 7, if the first time slot starts at time t1 and the next second time slot starts at time t2, and transmission and reception of video data in the first time slot ends at time t3 (assuming t3<t2), then if t2-t3 is equal to or greater than the time required for the erasure process, it can be determined that the time until the start of the second time slot is equal to or greater than the time required for the erasure process.

[0094] Alternatively, this determination can be made based on the amount of buffered data in the buffer areas BF1, BF2, . . . BFm+n allocated to the RAM 14 of the information processing device 1 at the end of transmission and reception of video data in the first time slot.

[0095] For example, if, at the end of transmission and reception of video data in the first time slot, there is sufficient free space in the buffer areas BF1, BF2, ... BFm that buffer the video data to be recorded in storage 3, and it can be determined that the buffer areas will not overflow even if the video data is buffered until it is recorded in storage 3 in the next time slot (video data can be buffered until the next recording), then it can be determined that the time until the start of the second time slot is longer than the time required for the erasure process.

[0096] On the other hand, if, at the end of the transmission and reception of video data in the first time slot, sufficient buffering data is buffered in the buffer areas BFm+1, BFm+2, ... BFm+n that buffer the video data to be read, and it can be determined that the buffer areas will not become empty by the time the video data is read from storage 3 in the next time slot (buffering data can be read from the buffer areas until the next read), then it can be determined that the time until the start of the second time slot is longer than the time required for the erasure process.

[0097] As described above, by determining whether or not the erasure process can be performed before the start of the next second time slot based on the buffering amount of buffered data in the buffer areas BF1, BF2, ... BFm+n, the erasure process can be performed while preventing the transmission and reception of video data between multiple video input / output devices 2, information processing device 1, and storage 3 from being interrupted due to an excess or shortage of buffered data.

[0098] If it is determined that the time until the start of the next second time slot is shorter than the time required for the erasure process and that the erasure process cannot be performed in the first time slot, the arbitration unit 6 does not send permission to perform the erasure process to the information processing device 1.

[0099] On the other hand, if it is determined that the time until the start of the next second time slot is longer than the time required for the erasure process and that the erasure process can be performed in the first time slot, the arbitration unit 6 sends permission to perform the erasure process to the information processing device 1 (step S114 in Figure 5).

[0100] If permission to execute the erasure process has not been received from the arbitration unit 6, i.e., if the erasure process cannot be executed in the first time slot ("No" in step S5 of Figure 6), the CPU 11 of the information processing device 1 waits until the start of the next second time slot, or executes a predetermined process as necessary, and starts transmitting and receiving video data in the next time slot (returning to step S4 after step S8 of Figure 6).

[0101] On the other hand, if permission to execute the erasure process has been received from the arbitration unit 6, i.e., if the erasure process can be executed in the first time slot ("Yes" in step S5 of Figure 6), the CPU 11 of the information processing device 1 determines whether the access speed of the storage 3 has become equal to or lower than a predetermined threshold (step S6 of Figure 6).

[0102] Specifically, the CPU 11 determines that the access speed of the storage 3 has fallen below a predetermined threshold, for example, when the writing speed of video data from the information processing device 1 to the storage 3 falls below the set video data recording rate, or when the reading speed of video data from the storage 3 to the information processing device 1 falls below the video data playback rate, or when both of these conditions occur.

[0103] If it is determined that the access speed of the storage 3 is greater than a predetermined threshold and is sufficient to satisfy the recording rate / playback rate of the video data ("No" in step S6 of Figure 6), the CPU 11 of the information processing device 1 waits until the start of the next second time slot without performing the erasure process, or performs a predetermined process as necessary and starts transmitting and receiving video data in the next time slot (returns to step S4 after step S8 of Figure 6).

[0104] On the other hand, if it is determined that the access speed of the storage 3 is below a predetermined threshold and is not sufficient to meet the recording rate / playback rate of the video data ("Yes" in step S6 of Figure 6), the CPU 11 of the information processing device 1 decides to perform the erasure process in the first time slot (step S7 of Figure 6).

[0105] The erasure process of erasing erasable video data from the flash memory 33 of the storage 3 is advantageous for improving the access speed of the storage 3 (the speed at which video data is recorded / read). However, since the process includes the erasure of data from the flash memory 33, it affects the lifespan of the storage 3. Specifically, excessively frequent execution of the erasure process shortens the lifespan of the storage 3.

[0106] Therefore, unnecessary erasure processing can be prevented by executing erasure processing only when the access speed of the storage 3 is equal to or lower than a predetermined threshold and the current access speed of the storage 3 cannot satisfy the recording rate / playback rate of the video data. As a result, the access speed of the storage 3 can be maintained at a high level while preventing the lifespan of the storage 3 from being shortened.

[0107] When it is determined that the erasure process is to be performed in the first time slot, the erasure process is performed in the video processing system 100. Specifically, the erasure process is performed as follows.

[0108] First, the CPU 11 of the information processing device 1 determines which video data is to be subject to the erasure process. The CPU 11 prioritizes video data that has not been rewritten for a predetermined period of time among the video data recorded in the storage 3 as the video data to be subject to the erasure process. An example of video data that has not been rewritten for a predetermined period of time is cold data that has remained recorded for a predetermined period of time. Whether or not data is cold data can be determined, for example, by whether or not metadata included in the video data indicates that it is cold data. Cold data is, for example, video data that is important and has been determined to be recorded for a long period of time, or video data that has been determined to be recorded for a long period of time as material for video editing.

[0109] However, the target of the prioritized erasure process is cold data that has been recorded in the metadata as cold data and that has been recorded in the current page PA for a long time. That is, for example, cold data that has been recorded in the current page PA for only a short time is not targeted for the prioritized erasure process. Furthermore, when the erasure process is performed on cold data as erasable video data, the cold data is not physically erased from the storage 3, but is instead moved from the current erase block BL to another erase block BL, and the cold data recorded in the current erase block BL is physically erased.

[0110] Cold data has the characteristic of being highly contiguous (i.e., recorded in consecutive pages PA of the flash memory 33) and difficult to delete by users, etc. For this reason, the erase block BL in which cold data is recorded is unlikely to be subject to garbage collection. In other words, cold data remains recorded in the same erase block BL (same page PA) for a long period of time. If cold data remains recorded in the same erase block BL for a long period of time, the difference between the number of data writes to the page PA in which the cold data is recorded and the number of writes to other pages PA becomes large.

[0111] In order to prevent the difference between the number of data writes of the page PA in which cold data is recorded and the number of writes of other pages PA from becoming excessively large, wear leveling processing is performed on the cold data. In other words, if cold data remains recorded in the same page PA for a long period of time, wear leveling processing is likely to be performed. If wear leveling processing is performed while recording / reading video data, the recording / reading speed of the video data in the storage 3 decreases.

[0112] As described above, by prioritizing the erasure process on cold data that has remained recorded for a long period in a specific erase block BL of the storage 3, new video data can be recorded in the page PA included in the specific erase block BL, thereby preventing the number of writes to the page PA from remaining low. As a result, the difference between the number of writes to the page PA and the number of writes to other pages PA is prevented from becoming excessively large, thereby preventing the execution of wear leveling processing in the storage 3. This prevents a decrease in the recording / reading speed of video data in the storage 3 due to the execution of wear leveling processing.

[0113] On the other hand, if there is no cold data to be prioritized for deletion, the CPU 11 targets the deletion of video data deleted by user operation or the like in the information processing device 1. Note that both video data deleted by user operation or the like and cold data can be targeted for deletion.

[0114] After the video data to be erased is determined, the erasure process is executed. The erasure process will be described in detail below, taking the case where the erasure process is performed on cold data as an example.

[0115] The CPU 11 reads the cold data determined to be subject to the erasure process from the erase block BL in which it is currently recorded (step S115 in FIG. 5).Then, the CPU 11 records the read cold data in another erase block BL (e.g., an erase block BL in the spare area) of the storage 3 (step S116 in FIG. 5).

[0116] It is preferable that the destination of the cold data to be erased is an erase block BL including a page PA with a relatively high number of writes. As described above, the number of writes to a page PA in which cold data is recorded is unlikely to increase, so by selecting an erase block BL including a page PA with a relatively high number of writes as the destination of the cold data, the difference between the number of writes to the page PA included in the erase block BL to which the cold data is to be moved and the number of writes to other pages PA is prevented from becoming large (this difference is promoted to be reduced), and the execution of wear leveling processing is prevented.

[0117] After the data transfer process is executed, the CPU 11 sends a command (physical erase command) to the storage 3 to physically erase the cold data that is the target of the erase process from the erase block BL in which the cold data that is the target of the erase process was recorded (i.e., the erase block BL from which the cold data is to be moved) (step S117 in Figure 5).

[0118] The controller 35 of the storage 3 that has received the physical erase command physically erases the cold data targeted for the erase process from the erase block BL in which the cold data is currently recorded. In this way, the physical erase process of the erase process is executed, and the cold data can be physically erased from the consecutive erase blocks BL secured by the data move process. As a result, new video data can be recorded in the consecutive erase blocks BL from which the cold data has been physically erased.

[0119] In the video processing system 100, if the time from the end of transmission and reception of video data in a first time slot among a plurality of time slots TS to the start of a second time slot allocated after the first time slot is equal to or longer than the time required for an erasure process to erase erasable data from storage 3, the erasure process is performed after the end of transmission and reception of video data in the first time slot.

[0120] That is, the erasure process is executed when there is sufficient time between the end of transmission and reception of video data in the first time slot and the start of the next second time slot during which no video data is being transmitted or received. As a result, the erasure process is not executed when video data is being transmitted or received, and therefore the speed of transmission and reception of video data between the video channels CH1, CH2, ... CHm+n and the storage 3 does not decrease.

[0121] 5 and 8, the video data recording operation executed in step S4 of the flowchart shown in FIG. 6 will be described below. FIG. 8 is a flowchart showing the operation of the information processing device 1 in recording video data. The recording operation described below is a recording operation executed within one time slot TS. In the video processing system 100, as long as there is video data output to be recorded in the storage 3, multiple time slots TS are allocated in sequence and the recording operation described below is repeatedly executed, thereby repeatedly recording video data in the storage 3.

[0122] When a user issues a command to output video data from the video output devices 2a using the information processing device 1 or the like, the video data is output from each video output device 2a (step S106 in FIG. 5). The CPU 11 of the information processing device 1 acquires the video data output from the video output devices 2a via the video channels CH1, CH2, ..., CHm to which the video output devices 2a are connected (step S11 in FIG. 8). The CPU 11 buffers the video data acquired via each of the video channels CH1, CH2, ..., CHm in buffer areas BF1, BF2, ..., BFm assigned to the video channels CH1, CH2, ..., CHm, respectively (step S12 in FIG. 8).

[0123] Although omitted in Figure 8, the operation of acquiring video data output from video output device 2a (i.e., step S11) and the operation of buffering the acquired video data (i.e., step S12) are performed appropriately asynchronously with the operation of video processing system 100 if video data is output from video output device 2a while video processing system 100 is operating.

[0124] While the video data is being buffered in buffer areas BF1, BF2, ... BFm, the CPU 11 determines whether or not video data equal to or greater than the access size of the small slot SS assigned to the video channel corresponding to each buffer area has been buffered in each of the buffer areas BF1, BF2, ... BFm (step S13 in Figure 8).

[0125] For example, when recording video data acquired via video channel CHk (k=1, 2, ..., m), CPU 11 determines whether or not video data equal to or larger than the access size of the small slot SS assigned to video channel CHk has been buffered in buffer area BFk assigned to video channel CHk. Note that k starts from 1 and increases by 1 up to m by repeating steps S14 to S17 below.

[0126] If the buffer area BFk allocated to the video channel CHk does not contain video data equal to or larger than the access size of the small slot SS allocated to the video channel CHk ("No" in step S13 of FIG. 8), steps S14 to S17 described below are skipped for the video channel CHk, and step S13 is executed for the next video channel CHk+1 (i.e., after step S18, return to step S13).

[0127] That is, if the buffer area allocated to a certain video channel does not contain video data equal to or larger than the access size of the short slot SS allocated to that video channel CHk, the CPU 11 skips recording the video data using the short slot SS allocated to that video channel and continues buffering the video data in the buffer area allocated to that video channel. As a result, the time required to record video data in the currently allocated time slot TS is reduced by the time allocated to that short slot SS.

[0128] On the other hand, if video data equal to or larger than the access size of the small slot SS assigned to video channel CHk is buffered in the buffer area BFk assigned to video channel CHk ("Yes" in step S13 of Figure 8), the CPU 11 requests the arbitration unit 6 to access storage 3 for video channel CHk in order to record the buffered data, which is the video data buffered in buffer area BFk, in storage 3 (step S107 of Figure 5, step S14 of Figure 8).

[0129] The arbitration unit 6, which has received the access request, determines, based on the setting information of the time slot TS, whether to permit the video channel CHk to access the storage 3. If the arbitration unit 6 determines, based on the setting information of the time slot TS, that the short slot SS can be allocated to the video channel CHk at the current time (the timing at which the access request was received), it transmits an access permission to the information processing device 1 in response to the access request from the information processing device 1 (step S108 in FIG. 5).

[0130] If no access permission is received from the arbitration unit 6 ("No" in step S15 of FIG. 8), the CPU 11 of the information processing device 1 skips recording of video data through video channel CHk and executes step S13 for the next video channel CHk+1 (i.e., returns to step S13 after step S18). Note that if no access permission is received, the CPU 11 may wait for a predetermined time, and if no access permission is received even after the time has elapsed, skip recording of video data through video channel CHk.

[0131] On the other hand, if an access permission is received from the arbitration unit 6 ("Yes" in step S15 of FIG. 8), the CPU 11 determines that a small slot SS for accessing the storage 3 and recording video data has been allocated to the video channel CHk. In this case, the CPU 11 transmits the buffered data buffered in the buffer area BFk to the storage 3 in the small slot SS allocated to the video channel CHk (step S109 of FIG. 5, step S16 of FIG. 8).

[0132] The controller 35 of the storage 3 receives the buffered data and records the received buffered data in consecutive pages PA of the flash memory 33. As described above, the buffered data has a size that is equal to or greater than an integral multiple of the size of the erase block BL. Therefore, the buffered data is recorded across a predetermined number of consecutive erase blocks BL of the flash memory 33. In other words, the number of erase blocks BL in which data is only partially recorded can be reduced. As a result, the occurrence of garbage collection processing in the storage 3 can be suppressed. Furthermore, by recording relatively large buffered data (video data) in consecutive pages PA (consecutive erase blocks BL), fragmentation of the video data can be suppressed.

[0133] After recording the video data (buffering data) of one video channel CHk in the storage 3 in the small slot SS assigned to that video channel CHk, the CPU 11 of the information processing device 1 determines whether there is a video channel among the video channels CH1, CH2, ... CHm that has not finished recording video data in the current time slot TS, that is, whether recording of video data has been completed for all video channels CH1, CH2, ... CHm (whether k has increased from 1 to m) (step S17 in Figure 8).

[0134] If there is a video channel among video channels CH1, CH2, ... CHm that has not finished recording video data in the current time slot TS, that is, if k is a value smaller than m ("No" in step S17 of Figure 8), k is incremented by 1 (step S18 of Figure 8), and steps S107 to S109 of Figure 5 and steps S13 to S17 of Figure 8 are executed for the next video channel CHk+1.

[0135] On the other hand, when the recording of video data has been completed for all video channels CH1, CH2, ... CHm in the current time slot TS, that is, when k becomes m (k = m) ("Yes" in step S17 of FIG. 8), the recording of video data in the current time slot TS is terminated. Thereafter, steps S106 to S109 in FIG. 5 and steps S11 to S18 in FIG. 8 are repeatedly executed in the next time slot TS.

[0136] In this way, in the video processing system 100, video data from the corresponding video channels CH1, CH2, ... CHm is buffered in each of the multiple buffer areas BF1, BF2, ... BFm, and the buffered data buffered in each of the buffer areas BF1, BF2, ... BFm is sequentially recorded in the corresponding small slot SS within one time slot TS. This allows the data transmission bandwidth of the data line connecting the information processing device 1 and the storage 3 to be exclusively used for recording one piece of video data (buffered data), thereby preventing a decrease in the recording rate of the video data.

[0137] 5 and 9, the video data read operation executed in step S4 of the flowchart shown in FIG. 6 will be described below. FIG. 9 is a flowchart showing the operation of the information processing device 1 when reading video data. In this embodiment, the read operation described below is executed for video channels CHm+1, CHm+2, . . . CHm+n after the video data recording operation described above is executed for video channels CH1, CH2, . . . CHm+n within one time slot TS. In the video processing system 100, as long as there is video data to be read, multiple time slots TS are allocated sequentially and the read operation described below is repeatedly executed, thereby repeatedly reading video data from the storage 3.

[0138] When a user instructs one of the video input devices 2b to input any of the video data recorded in the storage 3 using the information processing device 1 or the like, a request is made to the arbitration unit 6 for access to the storage 3 for the video channel (video channel CHj (j = m + 1, m + 2, ... m + n)) to which the video input device 2b instructed to input the video data is connected (step S110 in Figure 5, step S21 in Figure 9).

[0139] 5 and steps S21 to S27 in FIG. 9, which will be described below, are not executed for a video channel connected to a video input device 2b that has not been instructed to input video. In other words, when video data is not input to the video input device 2b via a certain video channel, the CPU 11 skips reading of the video data using the short slot SS assigned to that video channel. As a result, the time required to read the video data in the currently assigned time slot TS is reduced by the time assigned to that short slot SS.

[0140] The arbitration unit 6, which has received the access request, determines, based on the setting information of the time slot TS, whether to permit the video channel CHj to access the storage 3. If the arbitration unit 6 determines, based on the setting information of the time slot TS, that the short slot SS can be allocated to the video channel CHj at the current time (the timing at which the access request was received), it transmits an access permission to the information processing device 1 in response to the access request from the information processing device 1 (step S111 in FIG. 5).

[0141] If no access permission is received from the arbitration unit 6 ("No" in step S22 of FIG. 9), the CPU 11 of the information processing device 1 skips reading of video data through video channel CHj and executes step S21 for the next video channel CHk+1 (i.e., returns to step S21 after step S27). Note that if no access permission is received, the CPU 11 may wait for a predetermined time, and if no access permission is received even after the time has elapsed, skip reading of video data through video channel CHj.

[0142] On the other hand, if access permission is received from the arbitration unit 6 ("Yes" in step S22 of FIG. 9), the CPU 11 determines that a short slot SS for accessing the storage 3 and reading video data has been allocated to the video channel CHj. In this case, the CPU 11 reads the specified video data from the storage 3 in the short slot SS allocated to the video channel CHj (step S112 of FIG. 5, step S23 of FIG. 9). The CPU 11 buffers the video data read from the storage 3 in the buffer area BFj allocated to the video channel CHj (step S24 of FIG. 9).

[0143] When the short slot SS assigned to the video channel CHj ends, the CPU 11 transmits the buffered data buffered in the buffer area BFj assigned to the video channel CHj to the video input device 2b connected to the video channel CHj. As a result, the video data is input to the video input device 2b, and the video data is reproduced and displayed on the video input device 2b, for example.

[0144] The time length of the short slot SS for reading video data (i.e., corresponding to the access size) is set as the time during which the video input device 2b can read and buffer from the storage 3 an amount of data that will allow the video data to be reproduced without interruption until reading of the video data begins in the next time slot TS. Normally, if video data is read from the storage 3 in the short slot SS, it is possible to read and buffer from the storage 3 an amount of data that will allow the video data to be reproduced without interruption.

[0145] On the other hand, if for some reason it is not possible to read and buffer a sufficient amount of data from storage 3 within small slot SS, CPU 11 may, for example, reduce the playback rate and input the video data to video input device 2b, or may input video data with reduced image quality by thinning out pixels to video input device 2b.

[0146] After inputting the video data (buffered data) of one video channel CHj to the video input device 2b connected to that video channel CHj, the CPU 11 of the information processing device 1 determines whether or not there is a video channel among the video channels CHm+1, CHm+2, ..., CHm+n that has not finished reading out its video data in the current time slot TS, that is, whether or not reading out of the video data has been completed for all the video channels CHm+1, CH2, ..., CHm+n (whether or not j has increased from m+1 to m+n) (step S26 in FIG. 9).

[0147] If there is a video channel among video channels CHm+1, CHm+2, ... CHm+n that has not finished reading video data in the current time slot TS, that is, if j is a value smaller than m+n ("No" in step S26 of Figure 9), j is incremented by 1 (step S27 of Figure 9), and steps S110 to S113 of Figure 5 and steps S21 to S27 of Figure 9 are executed for the next video channel CHj+1.

[0148] On the other hand, when the reading of video data has been completed for all video channels CHm+1, CHm+2, ... CHm+n in the current time slot TS, that is, when j becomes n (j = m + n) ("Yes" in step S26 of FIG. 9), the reading of video data in the current time slot TS is terminated. Thereafter, steps S110 to S113 in FIG. 5 and steps S21 to S27 in FIG. 9 are repeatedly executed in the next time slot TS.

[0149] In this way, in video processing system 100, within one time slot, video data to be input to video input device 2b is sequentially read from storage 3, the read video data is sequentially buffered in buffer areas BFm+1, BFm+2, ..., BFm+n assigned respectively to video channels CHm+1, CHm+2, ..., CHm+n to which video input device 2b is connected, and the buffered data buffered in buffer areas BFm+1, BFm+2, ..., BFm+n is input to video input device 2b. This allows the data transmission bandwidth of the data line connecting information processing device 1 and storage 3 to be monopolized for reading one piece of video data (buffered data), thereby suppressing a decrease in the playback rate of the video data.

[0150] [2. Other Embodiments] While one embodiment of the present disclosure has been described above, the present disclosure is not limited to the above embodiment, and various modifications are possible without departing from the spirit and scope of the present disclosure. In particular, multiple embodiments and modifications described in this specification can be combined as needed.

[0151] (A) At least one of the processing content of each step and the order of steps shown in FIGS. 5, 6, 8, and 9 can be changed as appropriate without departing from the spirit of the invention.

[0152] (B) The connection relationship between the multiple video input / output devices 2 and the multiple video channels CH1, CH2, ... CHn of the information processing device 1 is not limited to the connection relationship described using Figures 1 and 2. In the above embodiment, for ease of explanation, an example is shown in which a video output device 2a is connected to each of the multiple consecutive video channels CH1, CH2, ... CHm, and a video input device 2b is connected to each of the multiple consecutive video channels CHm+1, CHm+2, ... CHm+n.

[0153] However, the present invention is not limited to this, and the video output devices 2a and video input devices 2b may be connected randomly to the multiple video channels CH1, CH2, ... CHm+n. Furthermore, any number of video output devices 2a and video input devices 2b may be connected, and there may be a video channel to which no device is connected.

[0154] [3. Supplementary Notes] (1) A video processing system (e.g., video processing system 100) includes a storage (e.g., storage 3), an information processing device (e.g., information processing device 1), a component (e.g., component 5), and an arbitration unit (e.g., arbitration unit 6). If the storage has a spare area of ​​a predetermined size or more, it can record data in the spare area in units of pages (e.g., pages PA). On the other hand, if the spare area does not have a predetermined size or more, all valid data in an erase block (e.g., erase block BL) in which invalid data is recorded is moved to another erase block, and all data in the source erase block is erased in units of erase blocks before data can be recorded. An erase block is made up of multiple pages. The information processing device controls the transmission and reception of video data to and from the storage via multiple video channels (e.g., video channels CH1, ... CHm+n) connected to multiple video input / output devices (e.g., video input / output device 2, video output device 2a, video input device 2b).

[0155] The configuration unit sets a time slot (e.g., time slot TS) having a predetermined time length for transmitting and receiving video data based on the page size and erase block size of the storage. The arbitration unit determines the timing at which each video channel is permitted to access the storage based on the time slot setting.

[0156] In this video processing system, the information processing device transmits and receives video data to and from the storage via the multiple video channels by transmitting and receiving video data to and from the storage via each of the multiple video channels within the time slot at the timing determined by the arbitration unit. Also, the information processing device can repeatedly transmit and receive video data to and from the storage via the multiple video channels by sequentially allocating the multiple time slots.

[0157] In addition, if the time from when the transmission and reception of video data in a first time slot among the multiple time slots is completed to when the second time slot allocated after the first time slot begins is longer than the time required for the erasure process to erase erasable data from the storage, the information processing device executes the erasure process after the transmission and reception of video data in the first time slot is completed.

[0158] In the above video processing system, video data is transmitted and received with the storage via multiple video channels by transmitting and receiving video data with the storage via each of the multiple video channels within a time slot having a predetermined length. As a result, at a specific timing within the time slot, the communication bandwidth can be monopolized for transmitting and receiving video data with the storage via one video channel. As a result, the speed of transmitting and receiving video data with the storage does not decrease.

[0159] Furthermore, in the above video processing system, if the time from the end of transmission and reception of video data in a first time slot among the multiple time slots to the start of a second time slot allocated after the first time slot is equal to or longer than the time required for the erasure process to erase erasable data from the storage, the erasure process is executed after the end of transmission and reception of video data in the first time slot. In other words, the erasure process is executed if there is a sufficient time during which no video data is being transmitted or received between the end of transmission and reception of video data in the first time slot and the start of the next second time slot. As a result, the erasure process is not executed when video data is being transmitted or received, and therefore the speed of transmission and reception of video data with the storage does not decrease.

[0160] (2) In the video processing system of (1), the information processing device may execute an erasure process when the access speed to the storage falls below a predetermined threshold. This prevents unnecessary erasure processes from being executed, thereby reducing the number of times data is erased from the storage while maintaining a high access speed to the storage, thereby extending the life of the storage.

[0161] (3) In the video processing system of (1) or (2), the erasure process may include a data transfer process for transferring the video data to be erased from the currently recorded area to another area, and a physical erase process for physically erasing the video data to be erased from the currently recorded area after the data transfer process. This ensures that consecutive erase blocks are secured, and that new video data can be recorded in the secured consecutive erase blocks.

[0162] (4) In the video processing system of (3), the information processing device may prioritize cold data, which is video data that has been recorded for a predetermined period or more, and perform data movement processing and physical erase processing on the cold data as video data to be erased. This allows cold data that has been recorded in the same location in the storage for a long period of time to be moved, preventing an excessive difference in the number of data writes between the location where the cold data was recorded and other locations in the storage. As a result, the execution of wear leveling processing in the storage is suppressed, and a decrease in the access speed of the storage due to the execution of wear leveling processing can be suppressed.

[0163] (5) In any of the video processing systems (1) to (4) above, the information processing device may have a temporary storage unit (e.g., buffer areas BF1, BF2, ..., BFm+n) that buffers video data transmitted to and received from the storage. In this case, whether or not to perform the deletion process in the first time slot may be determined based on the amount of buffered data in the temporary storage unit at the end of the transmission and reception of video data in the first time slot. This allows the deletion process to be performed while preventing interruptions in the transmission and reception of video data between multiple video input / output devices, the information processing device, and the storage due to an excess or shortage of buffered data.

[0164] (6) The information processing device is a device that has multiple video channels to which multiple video input / output devices are connected and is connected to a storage. If the storage has a spare area of ​​a predetermined size or more, it can record data in the spare area in page units. On the other hand, if the spare area does not have a predetermined size or more, all valid data in an erase block in which invalid data is recorded is moved to another erase block, and all data in the erase block from which data is moved is erased in erase block units, after which data can be recorded.

[0165] The information processing device has an information processing unit (e.g., CPU 11) that controls transmission and reception of video data with a storage via a plurality of video channels. The information processing unit transmits and receives video data with the storage via the plurality of video channels by transmitting and receiving video data with the storage via each of the plurality of video channels at predetermined timing within a time slot having a predetermined length of time, and can repeatedly transmit and receive video data with the storage via the plurality of video channels by sequentially allocating a plurality of time slots.

[0166] In addition, if the time from when transmission and reception of video data in a first time slot among the multiple time slots is completed to when the second time slot allocated after the first time slot begins is longer than the time required for the erasure process to erase erasable data from the storage, the information processing unit executes the erasure process after completion of transmission and reception of video data in the first time slot.

[0167] In the information processing device, at a specific timing within a time slot, the communication bandwidth can be exclusively used for transmitting and receiving video data to and from the storage via one video channel, so the speed of transmitting and receiving video data to and from the storage does not decrease. Furthermore, because the erasure process is not executed while video data is being transmitted and received, the speed of transmitting and receiving video data to and from the storage does not decrease.

[0168] (7) A control method is a method for controlling transmission and reception of video data to and from the storage via multiple video channels in an information processing device connected to the storage, the information processing device having multiple video channels connected to multiple video input / output devices. If the storage has a spare area of ​​a predetermined size or larger, data can be recorded in the spare area in page units. On the other hand, if the spare area does not have a predetermined size or larger, all valid data in an erase block in which invalid data is recorded is moved to another erase block, and all data in the source erase block is erased in erase block units before data can be recorded.

[0169] The above control method includes the following steps (a) to (c): The order in which the steps (a) to (c) are performed is not limited.

[0170] (a) A step of transmitting and receiving video data with the storage via a plurality of video channels by transmitting and receiving video data with the storage via each of the plurality of video channels at a predetermined timing within a time slot having a predetermined length of time.

[0171] (b) repeatedly transmitting and receiving video data to and from the storage via the plurality of video channels by sequentially allocating the plurality of time slots;

[0172] (c) A step of executing an erasure process after completing the transmission and reception of video data in a first time slot among the multiple time slots, if the time from completing the transmission and reception of video data in a first time slot to the start of a second time slot allocated after the first time slot is equal to or longer than the time required for an erasure process to erase erasable data from the storage.

[0173] With the above control method, at a specific timing within a time slot, the communication bandwidth can be exclusively used for sending and receiving video data to and from the storage via one video channel, so the speed of sending and receiving video data to and from the storage does not decrease. Also, because the erasure process is not executed while video data is being sent and received, the speed of sending and receiving video data to and from the storage does not decrease.

[0174] The present disclosure can be widely applied to systems that transmit and receive video data to and from storage configured using NAND elements.

[0175] 100: Video processing system 11: CPU 12: RAM 13: Storage device 14: Video interface 15: Storage interface 16: Interface 1: Information processing device 2: Video output device 3: Storage 31: Access port 33: Flash memory 35: Controller 37: Storage unit 5: Configuration unit 6: Arbitration unit BF1 to BFm+n: Buffer area CH1 to CHm+n: Video channel RA: Recording area BL: Erase block PA: Page

Claims

a storage device in which, if a spare area of ​​a predetermined size or more exists, data can be recorded in the spare area in page units, and, if a spare area of ​​the predetermined size or more does not exist, all valid data in an erase block made up of a plurality of pages in which invalid data is recorded is moved to another erase block, and all data in the erase block from which data is moved is erased in erase block units, and then data can be recorded; an information processing device that controls transmission and reception of video data to and from the storage via a plurality of video channels to which a plurality of video input / output devices are connected; a configuration unit that sets a time slot having a predetermined time length for transmitting and receiving the video data based on a page size and an erase block size of the storage; an arbitration unit that determines a timing for permitting each video channel to access the storage based on the setting of the time slot, The information processing device includes: transmitting and receiving video data to and from the storage via each of the plurality of video channels within the time slot at the timing determined by the arbitration unit, By sequentially allocating a plurality of time slots, transmission and reception of video data to and from the storage via the plurality of video channels can be repeatedly performed; when a time period from the end of transmission and reception of video data in a first time slot among the plurality of time slots to the start of a second time slot allocated after the first time slot is equal to or longer than a time required for an erasure process of erasing erasable data from the storage, execute the erasure process after the end of transmission and reception of video data in the first time slot. Video processing system. 　 The video processing system according to claim 1 , wherein the information processing device executes the deletion process when an access speed to the storage falls below a predetermined threshold.

2. The video processing system of claim 1, wherein the erasure process includes a data movement process for moving the video data to be erased from the currently recorded area to another area, and a physical erase process for physically erasing the video data to be erased from the currently recorded area after the data movement process.

4. The video processing system according to claim 3, wherein the information processing device performs the data movement process and the physical erase process by giving priority to cold data, which is video data that has been recorded for a predetermined period of time or more, as the video data to be erased. 　 The information processing device includes: a temporary storage unit for buffering video data transmitted to and received from the storage; 2. The video processing system according to claim 1, wherein whether or not to execute the deletion process in the first time slot is determined based on the amount of buffered data in the temporary storage unit at the end of transmission and reception of the video data in the first time slot. 　 An information processing device having a plurality of video channels to which a plurality of video input / output devices are connected, and connected to a storage, When a spare area of ​​a predetermined size or more exists, the storage is capable of recording data in the spare area in page units, and when the spare area of ​​the predetermined size or more does not exist, the storage moves all valid data in an erase block made up of a plurality of pages in which invalid data is recorded to another erase block, and erases all data in the erase block from which the data is moved in erase block units, and then becomes capable of recording data; the information processing device includes an information processing unit that controls transmission and reception of video data to and from the storage via the plurality of video channels; The information processing unit transmitting and receiving video data to and from the storage via the plurality of video channels at predetermined timings within a time slot having a predetermined length of time; By sequentially allocating a plurality of time slots, transmission and reception of video data to and from the storage via the plurality of video channels can be repeatedly performed; when a time period from the end of transmission and reception of video data in a first time slot among the plurality of time slots to the start of a second time slot allocated after the first time slot is equal to or longer than a time required for an erasure process of erasing erasable data from the storage, execute the erasure process after the end of transmission and reception of video data in the first time slot. Information processing device.

1. A control method for controlling transmission and reception of video data to and from a storage via a plurality of video channels connected to a plurality of video input / output devices in an information processing device connected to the storage, the method comprising: When a spare area of ​​a predetermined size or more exists, the storage is capable of recording data in the spare area in page units, and when the spare area of ​​the predetermined size or more does not exist, the storage moves all valid data in an erase block made up of a plurality of pages in which invalid data is recorded to another erase block, and erases all data in the erase block from which the data is moved in erase block units, and then becomes capable of recording data; transmitting and receiving video data to and from the storage via the plurality of video channels at a predetermined timing within a time slot having a predetermined time length; repeatedly transmitting and receiving video data to and from the storage via the plurality of video channels by sequentially allocating a plurality of time slots; a step of executing the erasure process after completing transmission and reception of the video data in a first time slot among the plurality of time slots, when a time period from completion of transmission and reception of the video data in a first time slot to a start of a second time slot allocated after the first time slot is equal to or longer than a time required for an erasure process of erasing erasable data from the storage; A control method comprising:

Images