Information processing device, information processing method, and information processing program

Abstract

An information processing device according to the present invention comprises a control unit. The control unit acquires a quantum circuit that is formed from a plurality of quantum bit gates and repeatedly executes first, second, and third processing until scheduling for all of the plurality of quantum bit gates of the quantum circuit is complete. The first processing schedules an unscheduled multi–quantum bit gate of a front layer of the unprocessed quantum circuit, the second processing schedules a first single–quantum bit gate that is an unscheduled single–quantum bit gate of the front layer, and the third processing schedules a second single–quantum bit gate that is an unscheduled single–quantum bit gate of a subsequent layer and can be scheduled at the same time step as the first single–quantum bit gate.

Description

Information processing device, information processing method, and information processing program

[0001] The present disclosure relates to an information processing device, an information processing method, and an information processing program for realizing a quantum computer.

[0002] Various technologies are being considered for quantum computer architecture. For example, Non-Patent Document 1 discloses an architecture that integrates semiconductor spin qubits, which simplifies the structure for controlling the semiconductor spin qubits, but does not allow multiple single-qubit gates to be implemented simultaneously.

[0003] In addition, various mappers have been proposed assuming a superconducting system with the constraint that a two-qubit gate can only be implemented between two coupled qubits. For example, Non-Patent Document 2 discloses an algorithm for solving the qubit mapping problem in a noisy intermediate-scale quantum computer (NISQ) device.

[0004] Ruoyu Li et al., “A crossbar network for silicon quantum dot qubits”, Science Advances, Vol4, Issue 7, [online], July 18, 2018, [Retrieved July 18, 2020], Internet <https: / / www.science.org / doi / 10.1126 / sciadv.aar3960> Gushu Li et al., “Tackling the Qubit Mapping Problem for NISQ-Era Quantum Devices”, Cornell university, Springer Nature Limited, [online], September 7, 2018, [searched on July 18, 2020], Internet <https: / / arxiv.org / pdf / 1809.02573>

[0005] The architecture described in Non-Patent Document 1 has only one resonant frequency band that can simultaneously use one-qubit gates, which makes it difficult to implement efficiently. Also, the mapper described in Non-Patent Document 2 cannot be applied to architectures that do not have direct coupling.

[0006] In one aspect, an information processing device is provided that includes a control unit configured to acquire a quantum circuit composed of a plurality of qubit gates, and, in the quantum circuit, perform a first process of scheduling an unscheduled multi-qubit gate in a frontmost layer of an unprocessed quantum circuit, a second process of scheduling a first one-qubit gate that is an unscheduled one-qubit gate in the frontmost layer, and a third process of scheduling a second one-qubit gate that is an unscheduled one-qubit gate in a subsequent layer and that is schedulable for the same time step as the first one-qubit gate, and repeatedly perform the first through third processes until scheduling of all of the plurality of qubit gates is completed.

[0007] In another aspect, there is provided an information processing method using an information processing device including a control unit, the information processing method including: the control unit acquiring a quantum circuit configured from a plurality of qubit gates; the control unit executing a first process in the quantum circuit to schedule an unscheduled multi-qubit gate in a frontmost layer of an unprocessed quantum circuit; the control unit executing a second process to schedule a first one-qubit gate that is an unscheduled one-qubit gate in the frontmost layer; the control unit executing a third process to schedule a second one-qubit gate that is an unscheduled one-qubit gate in a subsequent layer and that can be scheduled for the same time step as the first one-qubit gate; and the control unit repeatedly executing the first process to the third process until scheduling of all of the plurality of qubit gates has been completed.

[0008] In yet another aspect, a non-transitory computer-readable medium storing an information processing program is provided, which, when executed by a control unit of an information processing device, causes the control unit to acquire a quantum circuit composed of a plurality of qubit gates, perform a first process in the quantum circuit to schedule an unscheduled multi-qubit gate in a frontmost layer of an unprocessed quantum circuit, perform a second process to schedule a first one-qubit gate that is an unscheduled one-qubit gate in the frontmost layer, perform a third process to schedule a second one-qubit gate that is an unscheduled one-qubit gate in a subsequent layer and that is schedulable for the same time step as the first one-qubit gate, and repeatedly perform the first through third processes until scheduling of all of the plurality of qubit gates is completed.

[0009] FIG. 1 is a system schematic diagram of one embodiment. FIG. 2 is an explanatory diagram of a hardware configuration of one embodiment. FIG. 3 is an explanatory diagram of an outline of a processing procedure of one embodiment. FIG. 4A is an explanatory diagram of a quantum circuit to be compiled in one embodiment. FIG. 4B is an explanatory diagram of scheduling of a multi-qubit gate in the quantum circuit of FIG. 4A. FIG. 4C is an explanatory diagram of scheduling of a single-qubit gate in the quantum circuit of FIG. 4B. FIG. 5A is an explanatory diagram of the use of other operation means in the quantum circuit of FIG. 4C. FIG. 5B is an explanatory diagram of determining time steps t1 to t3 in the quantum circuit of FIG. 5A. FIG. 5C is an explanatory diagram of scheduling of a multi-qubit gate in the quantum circuit of FIG. 5B. FIG. 6A is an explanatory diagram of scheduling of a single-qubit gate in the quantum circuit of FIG. 5C. FIG. 6B is an explanatory diagram of determining time steps t4 and t5 in the quantum circuit of FIG. 6A. FIG. 6C is an explanatory diagram of determining time step t6 in the quantum circuit of FIG. 6B.

[0033] Figure 7A is an explanatory diagram of an arrangement of physical qubits and physical quantum dots in a virtual qubit of the first architecture of one embodiment, and Figure 7B is an explanatory diagram of an arrangement of logical qubits corresponding to the virtual qubit of Figure 7A. Figure 8A is an explanatory diagram of an arrangement of physical qubits and physical quantum dots in a virtual qubit of the second architecture of one embodiment, and Figure 8B is an explanatory diagram of an arrangement of logical qubits corresponding to the virtual qubit of Figure 8A. Figures 9A and 9B are explanatory diagrams of the movement cost of movement within the same quantum dot group and the movement cost of movement between different quantum dot groups, respectively, in one embodiment. Figures 10A to 10C are explanatory diagrams of one-qubit gate operations, multi-qubit gate operations, and SWAP gate operations, respectively, in quantum computing of the first architecture of one embodiment. Figures 11A to 11C are explanatory diagrams of one-qubit gate operations, multi-qubit gate operations, and SWAP gate operations, respectively, in quantum computing of the second architecture of one embodiment.

[0010] First Disclosed Embodiment Hereinafter, a first embodiment of an information processing device, an information processing method, and an information processing program will be described with reference to FIGS. 1 to 6C.

[0011] In the first disclosed embodiment, a compiler for a one-dimensional or multidimensional array of two-level quantum bits having one-qubit gates and two-qubit gates is described. When implementing a quantum algorithm to be solved on a physical quantum computer, it is necessary to compile the quantum algorithm into a quantum circuit that can be implemented by the physical quantum computer. The operations that the compiler must provide are quantum gate decomposition, qubit routing / qubit mapping, and operation scheduling. These operations are performed using operation means (quantum control technology) appropriate for the type of quantum computer. Quantum gate decomposition decomposes various operations on the quantum circuit into operations that can be implemented by the quantum computer to be implemented. Qubit routing, when implementing a multi-qubit gate, moves physical qubits so that operations can be performed on multiple qubits to be implemented and operations that entangle quantum information can be performed. Qubit mapping considers which logical qubits correspond to which physical qubits. Operation scheduling determines the timing and processing content of specific hardware operations.

[0012] In this embodiment, an algorithm for performing quantum computation in an architecture that integrates quantum bits will be described. Furthermore, a virtual physical quantum bit consisting of multiple quantum dots will be described to realize the algorithm. In this embodiment, an information processing device A1 shown in FIG. 1 uses a user device 10, a computing device 20, and a quantum computing unit 30.

[0013] 2, the hardware configuration of the computer device H10 that constitutes the user device 10 and the arithmetic device 20 will be described. The computer device H10 includes a communication device H11, an input device H12, a display device H13, a storage device H14, and a processor H15. Note that this hardware configuration is an example, and it may also be realized by other hardware.

[0014] The communication device H11 is an interface that establishes a communication path with another device and executes data transmission and reception, and is, for example, a network interface, a wireless interface, an optical interface, or the like.

[0015] The input device H12 is a device that accepts input from a user, etc., such as a mouse or keyboard. The display device H13 is a display that displays various information, etc. The storage device H14 is a device that stores data and various programs for executing various functions of the user device 10 and the computing device 20. Examples of the storage device H14 include ROM, RAM, hard disk, etc., which are non-transitory computer-readable media. Non-transitory computer-readable media include any available media that can be accessed by a general-purpose or dedicated computer. Note that the recording medium may be any physical quantity, such as light, electric charge, magnetism, or quantum state, or a combination of these.

[0016] The processor H15 uses programs and data stored in the storage device H14 to control each process in the arithmetic device 20. Examples of the processor H15 include a CPU and an MPU. The processor H15 executes various processes for each service.

[0017] The processor H15 is not limited to a processor that performs all of its processing using software. For example, the processor H15 may include a dedicated hardware circuit (e.g., an application-specific integrated circuit) that performs hardware processing for at least some of the processing it performs. That is, the processor H15 may be configured as a circuit including one or more processors that operate according to a computer program, dedicated hardware circuits, or a combination of these. Here, the circuit includes not only electrical circuits but also optical circuits, etc.

[0018] (System Configuration of Information Processing Apparatus A1) Next, the system configuration of the information processing apparatus A1 will be described with reference to Fig. 1. The user device 10 is a computer terminal used by a user.

[0019] The arithmetic device 20 is a computer for implementing a quantum algorithm. The arithmetic device 20 includes a control unit 21 for performing the processes described below (such as processes in the management stage and compilation stage). By executing a program for this purpose, the control unit 21 functions as a management unit 211 and a compiler 212.

[0020] The management unit 211 acquires a quantum algorithm. The compiler 212 compiles a quantum circuit expressed by the quantum algorithm into a quantum circuit that can be implemented by a quantum computer.

[0021] The quantum computing unit 30 performs quantum computation as a quantum computer. This quantum computing unit 30 includes an operation unit 31, a state-holding unit 32, and a measurement unit 33. The operation unit 31 performs quantum operations on the quantum bits in the state-holding unit 32 according to a program. In this case, the operation unit 31 operates (creates) the state held by the state-holding unit 32 based on a quantum circuit configured with quantum gates and the like. The state-holding unit 32 has a plurality of quantum bits and holds any quantum state. The measurement unit 33 observes the superposition state of the quantum bits in the state-holding unit 32.

[0022] (Outline of Compilation Process) Next, an outline of the compilation process will be described with reference to FIGS. 3 to 6C.

[0023] First, the control unit 21 of the arithmetic device 20 executes a quantum circuit acquisition process (step S11). Specifically, the management unit 211 of the control unit 21 acquires, from the user device 10, a quantum circuit that realizes the quantum algorithm to be calculated.

[0024] Next, a first process will be described for scheduling unscheduled multi-qubit gates in the frontmost layer (hereinafter referred to as the "frontmost layer") of an unprocessed quantum circuit composed of multiple quantum gates. Here, a layer is a set of quantum gates that can be scheduled independently of other quantum gates in a quantum circuit, and the frontmost layer is the first layer of multiple layers in the quantum circuit. A subsequent layer is the first layer in the quantum circuit obtained by excluding the quantum gates included in the frontmost layer from the original quantum circuit.

[0025] Here, the control unit 21 executes a multi-qubit gate determination (1) process (step S12). In this multi-qubit gate determination (1), it is determined whether or not there is a multi-qubit gate in the unscheduled frontmost layer. Specifically, the compiler 212 of the control unit 21 determines whether or not there is a multi-qubit gate in the frontmost layer of the quantum circuit.

[0026] In the multi-qubit gate determination (1), if it is determined that a multi-qubit gate exists in the front layer (if "YES" in step S12), the control unit 21 executes a scheduling process for the multi-qubit gate (step S13). Specifically, the compiler 212 provisionally assigns a time step to the identified multi-qubit gate. Note that, if multiple multi-qubit gates are identified in the front layer, the compiler 212 provisionally assigns undetermined subsequent time steps to all of the multi-qubit gates in sequence.

[0027] Next, the control unit 21 executes a one-qubit gate determination (1) process (step S14). Here, a second process is performed to schedule unscheduled one-qubit gates in the front layer. In this one-qubit gate determination (1), it is determined whether there is an unscheduled one-qubit gate in the front layer. Specifically, the compiler 212 determines whether there is an unscheduled one-qubit gate in the front layer of the quantum circuit.

[0028] The following describes a case where it is determined in the one-qubit gate determination (1) that there is an unscheduled one-qubit gate in the front layer ("YES" in step S14). In this case, the control unit 21 executes a scheduling process for the one-qubit gate in the front layer (step S15). Specifically, the compiler 212 provisionally assigns a time step subsequent to the time step provisionally assigned in step S13 to the unscheduled one-qubit gate in the front layer.

[0029] Next, the control unit 21 executes a one-qubit gate determination (2) process (step S16). In this one-qubit gate determination (2), it is determined whether there is a one-qubit gate in the subsequent layer that can be simultaneously operated by the same operation means as the one-qubit gate scheduled in step S15. Specifically, the compiler 212 determines whether there is an unscheduled one-qubit gate in the subsequent layer that can be simultaneously operated by the same operation means as the one-qubit gate scheduled in step S15. If the one-qubit gates can be simultaneously operated by the same operation means, these one-qubit gates can be scheduled for the same time step (i.e., simultaneously).

[0030] In the one-qubit gate determination (2), it is determined that there is a one-qubit gate (second one-qubit gate) in the subsequent layer that can be operated simultaneously with the one-qubit gate (first one-qubit gate) scheduled in step S15 (if "YES" in step S16). In this case, the control unit 21 executes a scheduling process for the one-qubit gate that can be operated simultaneously (step S17). Specifically, the compiler 212 provisionally assigns the same time step as the first one-qubit gate to the second one-qubit gate.

[0031] Then, the control unit 21 returns to the 1-qubit gate determination (1) process (step S14). Next, a case where it is determined in the 1-qubit gate determination (1) that there is no unscheduled 1-qubit gate in the front layer ("NO" in step S14) will be described. In this case, the control unit 21 executes a determination process as to whether another 1-qubit gate can be operated at the same time (step S18). Specifically, the compiler 212 determines whether there is another operation means in the subsequent layer that operates a 1-qubit gate at the same time as any of the time steps tentatively assigned so far.

[0032] If it is determined that another one-qubit gate is operable ("YES" in step S18), the control unit 21 executes a one-qubit gate determination (3) process (step S19). In the one-qubit gate determination (3), it is determined whether or not there is a one-qubit gate in the subsequent layer that can be operated by another operation means. Specifically, the compiler 212 determines whether or not there is a one-qubit gate in the subsequent layer that can be operated by another operation means, among the unscheduled one-qubit gates in the subsequent layer.

[0033] The following describes the case where it is determined in the one-qubit gate determination (3) that there is a one-qubit gate in the subsequent layer that can be operated by another operation means ("YES" in step S19). In this case, the control unit 21 executes a process of scheduling the one-qubit gate in the subsequent layer together with the one-qubit gate (first one-qubit gate) in the preceding layer (step S20). Here, scheduling (third process) is performed for another one-qubit gate in the subsequent layer that is an unscheduled one-qubit gate that can be scheduled for the same time step as the first one-qubit gate using an operation means different from that of the first one-qubit gate. Specifically, the compiler 212 provisionally assigns to this other one-qubit gate a time step in a layer that can be scheduled for the same time step as the one-qubit gate scheduled in steps S15 and S17. Here, if multiple one-qubit gates are identified in the subsequent layer, priority is given to those that do not have one-qubit gates that can be simultaneously operated in the next subsequent layer.

[0034] Then, the control unit 21 returns to the process of determining whether another one-qubit gate can be simultaneously operated at the time step provisionally assigned up to that point (step S18). If it is determined that another one-qubit gate cannot be operated or that there is no one-qubit gate in the subsequent layer ("NO" in steps S18 and S19), the control unit 21 executes a schedule determination process (step S21). Specifically, the compiler 212 determines the time step provisionally assigned by scheduling.

[0035] Next, the control unit 21 executes a process of determining whether all quantum gates have been scheduled (step S22). Specifically, the compiler 212 determines whether there is a quantum gate in the quantum circuit whose schedule has not been determined.

[0036] If there are any unscheduled quantum gates remaining, it is determined that all quantum gates have not been scheduled ("NO" in step S22). In this case, the control unit 21 repeats the first to third processes described above. Specifically, the control unit 21 returns to the multi-qubit gate determination (1) process (step S12). The above processes are repeated until the scheduling of all quantum gates is completed.

[0037] On the other hand, if it is determined that all quantum gates have been scheduled ("YES" in step S22), the control unit 21 executes a schedule output process (step S23). Specifically, the compiler 212 outputs a definite schedule to the quantum computing unit 30. Then, the quantum computing unit 30 performs quantum computing according to the definite schedule.

[0038] (Example of Compilation Process) Next, an example of efficiently implementing a quantum algorithm in an architecture that selectively controls qubits in semiconductor spin qubits will be described.

[0039] In this embodiment, an algorithm for performing quantum computation in an architecture in which quantum bits are integrated will be described.

[0040] An example of the compilation process will be described using Figures 4A to 6C. Here, an example of a quantum circuit is shown in which a one-qubit gate operable by two different manipulation means can be scheduled for the same time step, but the number of different manipulation means schedulable for the same time step may be three or more. As shown in Figure 4A, assume that quantum circuit 500 is acquired in step S11. Quantum circuit 500 includes two-qubit gates 501, 502, 505, and 509, which are CZ gates, as multi-qubit gates. Quantum circuit 500 also includes one-qubit gates 503, 504, 506, 507, and 508. Note that parameters U1 to U4 indicate that the circuit has different manipulation means. Then, in step S12, it is determined that quantum circuit 500 has a multi-qubit gate in the front layer.

[0041] As shown in FIG. 4B, in step S13, time steps t1 and t2 are provisionally assigned to two-qubit gates 501 and 502 of quantum circuit 510, respectively.

[0042] 4C , quantum circuit 520 determines that there is an unscheduled 1-qubit gate in the front layer ("YES" in step S14), and in step S15, tentatively assigns time step t3 to 1-qubit gate 503. Note that quantum circuit 520 determines in the 1-qubit gate determination (2) process (step S16) that there is no simultaneously operable 1-qubit gate in the subsequent layer.

[0043] If it is determined that the other one-qubit gates are operable ("YES" in step S18), the control unit 21 executes one-qubit gate determination (3) processing (step S19). In the quantum circuit 520 shown in FIG. 4C, one-qubit gates 504, 507, and 508 are located in the layer subsequent to the one-qubit gate U1. Note that one-qubit gate 506 having parameter U3 is located in the layer subsequent to the one-qubit gate U1.

[0044] 5A, in quantum circuit 530, another operation means is used to provisionally assign time step t3 to one-qubit gate 504. As shown in FIG. 5B, in step S21, time steps t1 to t3 in quantum circuit 540 are determined.

[0045] As shown in Figure 5C, in step S13, a time step t4 is provisionally assigned to the two-qubit gate 505 in the quantum circuit 550. As shown in Figure 6A, it is determined that there is an unscheduled one-qubit gate in the front layer in the quantum circuit 560 ("YES" in step S14). In this case, in step S15, the one-qubit gates 507 and 508 have different operation means but can be operated simultaneously. Therefore, a time step t5 is provisionally assigned to both of them (step S15).

[0046] As shown in Fig. 6B, in step S17, a time step t5 is tentatively assigned to the one-qubit gate 506 in quantum circuit 570. Then, since operation of other one-qubit gates is impossible, the time step is finalized in step S21. Then, as shown in Fig. 6C, in step S13, a time step t6 is tentatively assigned to the two-qubit gate 509 in quantum circuit 580. Since scheduling is performed for all quantum gates, the time step is finalized in step S21.

[0047] (Example of Application to Semiconductor Quantum Dots) The compiler can be realized by a quantum computer that handles quantum gates for semiconductor spin quantum devices, superconducting circuits, ions, neutral atoms, photons, etc. Below, an example of application to semiconductor quantum dots will be described.

[0048] To implement a rotation operation about the X (Y) axis on the Bloch sphere using a single-qubit gate consisting of this semiconductor spin qubit, an alternating current magnetic field corresponding to the resonant frequency of the quantum dot in which the physical qubit (charge spin) to be manipulated is located is applied as the manipulation means. To implement a rotation operation about the Z axis, the physical qubit is moved to a quantum dot with a resonant frequency different from the frequency used as the calculation basis, and then time is evolved. In multi-qubit gates such as CNOT gates and CZ gates, the operation is implemented by utilizing the difference in resonant frequencies between two quantum dots in which the physical qubit to be manipulated is confined, so each physical qubit is moved to a nearby quantum dot with a different resonant frequency.

[0049] (Effects of the First Disclosed Embodiment) (1-1) In this embodiment, the control unit 21 of the arithmetic device 20 executes a multi-qubit gate determination (1) process (step S12). If the multi-qubit gate determination (1) determines that a multi-qubit gate is present in the front layer, the control unit 21 executes a multi-qubit gate schedule process (step S13). This allows quantum gate operations that affect multiple qubits to be processed with priority.

[0050] (1-2) In this embodiment, if it is determined that there is an unscheduled 1-qubit gate in the front layer, the control unit 21 executes a scheduling process for the 1-qubit gate in the front layer (step S15). This allows the unscheduled 1-qubit gates to be scheduled in order.

[0051] (1-3) In this embodiment, if it is determined that there are simultaneously operable one-qubit gates in the subsequent layer, the control unit 21 executes a scheduling process for the simultaneously operable one-qubit gates (step S17). This allows multiple one-qubit gates to be scheduled together using the same operation means.

[0052] (1-4) In this embodiment, if it is determined that another one-qubit gate is operable, the control unit 21 executes the one-qubit gate determination (3) process (step S19). If it is determined that there is a one-qubit gate in a subsequent layer that can be operated by another operation means, the control unit 21 executes a process of scheduling the one-qubit gate in the subsequent layer together with the one-qubit gate in the preceding layer (step S20). This allows multiple one-qubit gates to be operated together using multiple operation means.

[0053] (1-5) In this embodiment, if it is determined that another one-qubit gate is not operable or if it is determined that there is no one-qubit gate in the subsequent layer, the control unit 21 executes a schedule determination process (step S21). This allows the next multi-qubit gate determination process (1) to be repeated. As described above, according to the present disclosure, quantum algorithms can be efficiently compiled.

[0054] (Another Example of the First Disclosure) This embodiment can be modified as follows: This embodiment and the following modified examples can be combined and implemented within the scope of no technical contradiction.

[0055] In the above embodiment, the scheduling of the one-qubit gate is performed after the scheduling of the multi-qubit gate. Alternatively, the scheduling of the one-qubit gate may be performed after the scheduling of the multi-qubit gate. In this case, the processing of steps S12 to S13 is performed after the processing of steps S14 to S20. However, if it is necessary to implement a two-qubit gate before the one-qubit gate in step S16, steps S12 to S13 are performed.

[0056] In the above embodiment, the control unit 21 of the computing device 20 executes a multi-qubit gate determination (1) process (step S12). An example of a multi-qubit gate is a two-qubit gate, but the present invention is not limited to a two-qubit gate and can be applied to a multi-qubit gate of three or more qubits.

[0057] Second Disclosed Embodiment Hereinafter, a second disclosed embodiment of an information processing device, an information processing method, and an information processing program will be described with reference to FIGS. 7A to 11C.

[0058] In the second disclosed embodiment, the architecture of a virtual physical qubit is described. A physical qubit is a physical system that can hold and manipulate quantum information. This physical qubit is composed of a quantum dot, which is a minute region that holds a quantum state. The quantum state in the quantum dot constitutes the physical qubit. A virtual physical qubit composed of multiple physical qubits is used. The design rules (α) and (β) of this virtual physical qubit are described below.

[0059] This virtual physical qubit architecture must be an architecture capable of implementing each quantum gate included in the quantum algorithm.

[0060] (α) This architecture needs to have multiple types of operation means. (β) In this architecture, the operation costs of each physical qubit must all be the same.

[0061] The following are the state-like conditions that such an architecture has: The same virtual physical qubit is repeatedly arranged. This condition is for making the operation cost of implementing a single qubit gate the same. When implementing a single qubit gate, the physical qubit moves to a quantum dot with a different operation means within the virtual physical qubit in which it is stored. Therefore, in an architecture in which the same virtual physical qubit is repeatedly arranged, the operation cost of a single qubit gate in each case can be considered to be the same.

[0062] The cost of moving each physical quantum bit when implementing a multi-qubit gate or a SWAP gate must be the same. This condition is for making the operation cost the same when implementing a multi-qubit gate or a SWAP gate. When implementing these operations, it is necessary to move the two physical quantum bits to be operated to adjacent quantum dot pairs, and the cost of this movement must be the same for all adjacent virtual physical quantum bit pairs.

[0063] 7A to 8B show an example of a virtual physical quantum bit architecture. FIGS. 9A and 9B are explanations using the architecture shown in FIGS. 7A and 7B as an example. Here, movement C1 (shuttling), interaction C2, and movement C3 (shuttling) are performed. In FIG. 9A, movements C1 and C3 are performed within one quantum dot group 600, and interaction C2 is performed between different quantum dot groups 600. In FIG. 9B, movements C1 and C3 are performed between different quantum dot groups 600, and interaction C2 is performed within one quantum dot group 600. Even in such cases, the movement cost between quantum dots of physical quantum bits within the architecture is assumed to be the same for all quantum dots.

[0064] In the architecture shown in FIG. 7A, each quantum dot group 600 is configured by repeatedly arranging four quantum dots 601, 602, 603, and 604 in a square shape. In this case, the state of the quantum dot group 600 is determined by whether any of the quantum dots 601 to 604 has a physical quantum bit. In this case, the quantum dots 601 to 603 have different operation means. Each of the four quantum dot groups 600 arranged in a square shape has a virtual physical quantum bit Q i00， Q i01， Q i10， Q i11 Then, the movement cost of each physical quantum bit is set to be the same. Then, as shown in FIG. 7B, the virtual physical quantum bit Q i00， Q i01， Q i10， Q i11 are logical qubits q 0， q 1， q 2， Corresponds to q3.

[0065] 8A, each quantum dot group 700 is configured by repeatedly arranging three quantum dots 701, 702, and 703 in a triangular shape. In this case, too, the movement cost of each physical quantum bit is set to be the same. The four quantum dot groups 700 are configured by a virtual physical quantum bit Q i0， Q i1， Q i2， Qi3 Configure.

[0066] Then, as shown in FIG. 8B, the virtual physical qubit Q i0， Q i1， Q i2， Q i3 are logical qubits q 0， q 1， q 2， Corresponds to q3.

[0067] Next, we will explain how to operate a one-qubit gate: (A1) Transferring a physical qubit to a quantum dot with an operating means to be implemented; (A2) Implementing a one-qubit gate by applying an AC magnetic field; (A3) Transferring a physical qubit to the original quantum dot.

[0068] Next, we will explain how to operate a multi-qubit gate. (B1) Moving the physical qubit to be operated to an adjacent quantum dot. (B2) Implementing a multi-qubit gate using exchange interactions. (B3) Moving the physical qubit to the original quantum dot.

[0069] Regarding specific operation methods, we will explain the operation methods for an architecture in which quantum dots are arranged on a square lattice. First, we will explain the operation method for a one-qubit gate. Since both architectures have three operation means, up to two types of one-qubit gates can be operated simultaneously.

[0070] In the following, the quantum dot of the manipulation means α is used as the quantum dot that holds the physical quantum bit, so the physical quantum bit to be manipulated is moved to the quantum dots of the manipulation means β and γ, and then the respective manipulation means are added to implement a one-qubit gate. Finally, the quantum bit is moved back to the quantum dot of the manipulation means α, completing the series of operations. In this way, the movement of the physical quantum bit when simultaneously operating two types of one-qubit gates is shown.

[0071] 10A-10C show an example of quantum manipulation using quantum dot groups 600 in a square-shaped architecture. Each quantum dot group 600 is composed of an upper right quantum dot 601, an upper left quantum dot 602, a lower right quantum dot 603, and a lower left quantum dot 604, similar to FIG. 7A.

[0072] FIG. 10A shows an example of the movement of a physical quantum bit in a one-qubit gate when a quantum dot group 600 is used. Here, the virtual physical quantum bit Q i00 and the virtual physical qubit Q i11 Each implements a different type of one-qubit gate simultaneously.

[0073] State 811 is the initial state. Next, as shown in state 812, the virtual physical qubit Q i00 The physical quantum bit is a quantum dot 602, and the virtual physical quantum bit Q i11 Then, as shown in state 813, the virtual physical qubit Q i00 quantum dot 602, virtual physical quantum bit Q i11 Then, as shown in state 814, the quantum state of the physical qubit of the quantum dot 603 is changed. i00 The physical quantum bit is a quantum dot 601, and the virtual physical quantum bit Q i11 The physical quantum bit is transferred to the quantum dot 601.

[0074] FIG. 10B shows an example of a multi-qubit gate, and FIG. 10C shows an example of a physical qubit movement when a SWAP gate is implemented. i00 and virtual physical quantum Q i10 FIG. 10C shows an example of the movement of a physical qubit when implementing a multi-qubit gate between virtual physical qubits Q i00 and the virtual physical qubit Q i10 This is an example of the movement of a physical quantum bit when implementing a SWAP gate between

[0075] In the method of operating a multi-qubit gate or a SWAP gate, the physical qubits to be operated are moved to adjacent quantum dots, and then the multi-qubit gate or the SWAP gate is implemented. Finally, the operation is completed by moving them back to the quantum dot of the original operating means α.

[0076] State 821 in Figure 10B is the initial state. Next, as shown in state 822, the virtual physical qubit Q i00Then, as shown in state 823, the virtual physical qubit Q i00 quantum dot 603 and virtual physical qubit Q i10 Next, as shown in state 824, the virtual physical qubit Q i00 The physical quantum bit is transferred to the quantum dot 601.

[0077] State 831 in Figure 10C is the initial state. Next, as shown in state 832, the virtual physical qubit Q i00 Then, as shown in state 833, the virtual physical qubit Q i00 quantum dot 603 and virtual physical qubit Q i10 Next, as shown in state 834, the virtual physical qubit Q i00 The physical quantum bit is transferred to the quantum dot 601.

[0078] 11A-11C show an example of quantum manipulation using quantum dot groups 700 in a triangular architecture. Each quantum dot group 700 is composed of an upper quantum dot 701, a lower left quantum dot 702, and a lower right quantum dot 703, similar to FIG. 8A.

[0079] 11A is the initial state. Next, as shown in state 912, the virtual physical qubit Q i0 The physical quantum bit is a quantum dot 702, and the virtual physical quantum bit Q i3 Then, as shown in state 913, the virtual physical qubit Q i0 quantum dot 702, virtual physical quantum bit Q i3 Then, as shown in state 914, the quantum state of the physical qubit of the quantum dot 703 is changed. i0 The physical quantum bit is the quantum dot 701, and the virtual physical quantum bit Q i3 The physical quantum bit is transferred to the quantum dot 701.

[0080] 11B is the initial state. Next, as shown in state 922, the virtual physical qubit Q i0 Then, as shown in state 923, the virtual physical qubit Q i0 quantum dot 702 and virtual physical qubit Q i1 Next, as shown in state 924, the virtual physical qubit Q i0 The physical quantum bit is transferred to the quantum dot 701.

[0081] 11C is the initial state. Next, as shown in state 932, the virtual physical qubit Q i0 Then, as shown in state 933, the virtual physical qubit Q i0 quantum dot 702 and virtual physical qubit Q i3 Next, as shown in state 934, the virtual physical qubit Q i0 The physical quantum bit is transferred to the quantum dot 701.

[0082] (Example of a method for realizing the architecture) The above architecture can be realized by a quantum computer that handles semiconductor spin quantum devices, superconducting circuits, ions, neutral atoms, photons, anyons, and other quantum bit gates.

[0083] When the quantum bit is a semiconductor quantum dot, the quantum state can be maintained by spin or by something other than spin. The quantum state can be maintained by other means such as charge or orbital states. The quantum state can be manipulated by adjusting electric or magnetic fields.

[0084] (Effects of the Second Disclosed Embodiment) (2-1) In the architecture of this embodiment, a virtual physical quantum bit is configured using a quantum dot group consisting of multiple quantum dots. This makes it possible to realize an architecture with multiple types of manipulation means. This is particularly effective for architectures with three or more manipulation means. If an architecture has one manipulation means, using that manipulation means for a one-qubit gate makes it impossible to retain information about other quantum bits that do not implement a one-qubit gate. If an architecture has two manipulation means, using both of the two manipulation means of the architecture simultaneously to process a one-qubit gate makes it impossible to retain information within the quantum bit. If one manipulation means is used for a one-qubit gate and the other manipulation means is used to retain information about another quantum bit, multiple one-qubit gates cannot be implemented simultaneously, and simultaneous operation cannot be made more efficient. In the architecture of this embodiment, the number of manipulation means that can be simultaneously used to process a one-qubit gate is "(the number of manipulation means of the architecture) - 1". In an architecture with three or more operating means, the number of frequencies that can be used simultaneously to process one quantum bit gate is two or more, so the present embodiment can improve the efficiency of simultaneous processing of one quantum bit gates.

[0085] (2-2) In the architecture of this embodiment, the operation costs of the physical quantum bits are all the same. If the operation costs differ depending on the physical quantum bit, the costs must be optimized taking into account quantum bit routing and quantum bit mapping, and then specific scheduling must be considered. On the other hand, in this embodiment, the processes of quantum bit routing and quantum bit mapping and operation scheduling can be optimized separately.

[0086] (Another Example of the Second Disclosure) This embodiment can be modified as follows: This embodiment and the following modified examples can be combined and implemented within the scope of no technical contradiction.

[0087] In the architecture of the above embodiment, quantum dots arranged in a square or triangular shape are used. The arrangement is not limited to these as long as the design rules of the architecture are met. In the architecture of the above embodiment, a group of quantum dots is used to implement multiple operation means. Therefore, the compilation of the first disclosure may be realized using the architecture of the second disclosure.

[0088] (Supplementary Notes) Next, the technical ideas that can be understood from the above-described embodiments and other examples are further described below. (Supplementary Note 1) A quantum computing device including a quantum dot group (virtual physical quantum bit) consisting of three or more quantum dots, wherein each of the quantum dots included in the quantum dot group can be operated by one of three or more different types of operation means, the quantum dots can perform each operation at the same cost, the state of the physical quantum bit held by one of the quantum dots represents the quantum state of the quantum dot group, and the quantum dot groups are arranged so that the operation cost between adjacent quantum dot groups is the same.

[0089] (Appendix 2) A quantum computing device as described in (Appendix 1), characterized in that in the quantum dot group, the quantum dots are arranged at the vertex positions of a square, and at least quantum dots of the first, second, and third operating means are arranged at each vertex position.

[0090] (Appendix 3) A quantum computing device as described in (Appendix 2), characterized in that in the group of quantum dots, quantum dots with the same operation means are arranged at the vertex positions on one diagonal line of the square.

[0091] (Appendix 4) A quantum computing device as described in (Appendix 1), characterized in that in the quantum dot group, the quantum dots are arranged at the vertex positions of an equilateral triangle, and at least quantum dots of the first, second, and third operating means are arranged at each vertex position.

[0092] (Appendix 5) A quantum computing device according to any one of (Appendixes 1 to 4), characterized in that a multi-qubit gate is formed using two of the quantum dot groups, and the costs between any of the quantum dot groups are the same.

Claims

1. An information processing device having a control unit, wherein the control unit is configured to: acquire a quantum circuit composed of a plurality of quantum bit gates; execute a first process in the quantum circuit to schedule an unscheduled multi-qubit gate in a frontmost layer of an unprocessed quantum circuit; execute a second process to schedule a first one-qubit gate that is an unscheduled one-qubit gate in the frontmost layer; execute a third process to schedule a second one-qubit gate that is an unscheduled one-qubit gate in a subsequent layer and that can be scheduled for the same time step as the first one-qubit gate; and repeatedly execute the first to third processes until scheduling of all of the plurality of quantum bit gates has been completed.

2. The information processing device according to claim 1, wherein the control unit is further configured to schedule, in the second process, another one-qubit gate that can be operated by the same operation means as the first one-qubit gate for the same time step as the first one-qubit gate.

3. The information processing device according to claim 1 or 2, wherein the control unit is further configured to schedule, in the third process, another one-qubit gate that can be operated by an operation means different from that of the first one-qubit gate, for the same time step as the first one-qubit gate.

4. The information processing device according to any one of claims 1 to 3, wherein the control unit is further configured to output a finalized schedule for quantum computation by the quantum computation unit upon completion of scheduling of all quantum gates of the plurality of quantum bit gates that constitute the quantum circuit.

5. An information processing method using an information processing device having a control unit, wherein the control unit acquires a quantum circuit composed of a plurality of quantum bit gates; the control unit executes a first process in the quantum circuit to schedule an unscheduled multi-qubit gate in a frontmost layer of an unprocessed quantum circuit; the control unit executes a second process to schedule a first one-qubit gate that is an unscheduled one-qubit gate in the frontmost layer; the control unit executes a third process to schedule a second one-qubit gate that is an unscheduled one-qubit gate in a subsequent layer and that can be scheduled for the same time step as the first one-qubit gate; and the control unit repeatedly executes the first to third processes until scheduling of all of the plurality of quantum bit gates has been completed.

6. A non-transitory computer-readable medium storing an information processing program, which, when executed by a control unit of an information processing device, causes the control unit to: acquire a quantum circuit composed of a plurality of quantum bit gates; execute a first process in the quantum circuit that schedules an unscheduled multi-qubit gate in a frontmost layer of an unprocessed quantum circuit; execute a second process that schedules a first one-qubit gate that is an unscheduled one-qubit gate in the frontmost layer; execute a third process that schedules a second one-qubit gate that is an unscheduled one-qubit gate in a subsequent layer and that can be scheduled for the same time step as the first one-qubit gate; and repeatedly execute the first to third processes until scheduling of all of the plurality of quantum gates has been completed.

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