Display panel and display apparatus

Abstract

A display panel, comprising a display area (AA) and a non-display area (NA); the display area (AA) comprises a plurality of first reference voltage lines (11), a plurality of second reference voltage lines (12) and data lines (23), the data lines (23) extending in a first direction (Y); the non-display area (NA) comprises a first reference voltage bus (13) and a second reference voltage bus (14), the first reference voltage lines (11) being electrically connected to the first reference voltage bus (13), and the second reference voltage lines (12) being electrically connected to the second reference voltage bus (14). The non-display area (NA) comprises a fan-out area (15) and a first non-display area (NA1) which are located on two sides of the display area (AA) in the first direction (Y), the non-display area (NA) comprising a first bus segment (131) and a second bus segment (132), at least part of the first bus segment (131) being located in the fan-out area (15), and at least part of the second bus segment (132) being located in the first non-display area (NA1).

Description

Display panel and display device

[0001] The present application claims priority to the Chinese patent application No. 202411259130.7, filed on September 9, 2024, with the Chinese Patent Office, the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the technical field of display, for example, to a display panel and a display device. BACKGROUND

[0003] An organic light-emitting diode (OLED) display panel refers to a display panel in which a light-emitting material emits light under the driving of an electric field through carrier injection and recombination. Compared with a liquid crystal display panel, an OLED display panel is lighter and thinner, has a better viewing angle and contrast ratio, and thus has attracted widespread attention.

[0004] In the related art, in order to achieve a narrow frame of an OLED, a fanout in AA (FIAA) technology is used. For example, metal in the row direction and the column direction in the display area is increased as FIAA wiring, and is connected to each other through a wire changing hole, so as to change the fanout wiring of the lower R corner of the original display panel to a mode of being led out from the display area, reduce the space of the lower R corner and the lower frame, and achieve a narrow frame design.

[0005] SUMMARY

[0006] Embodiments of the present application provide a display panel and a display device to reduce the width of the side frame of the display panel and achieve a narrow frame design.

[0007] In a first aspect, embodiments of the present application provide a display panel, comprising: a display area and a non-display area surrounding the display area;

[0008] The display area comprises a plurality of first reference voltage lines, a plurality of second reference voltage lines and a data line; the data line extends along a first direction;

[0009] The non-display area comprises a first reference voltage bus and a second reference voltage bus; the first reference voltage line is electrically connected to the first reference voltage bus; and the second reference voltage line is electrically connected to the second reference voltage bus;

[0010] The first reference voltage bus comprises a first bus segment and a second bus segment;

[0011] The non-display area includes a fan-out area and a first non-display area located on two sides of the display area along the first direction respectively; at least part of the first bus segment is located in the fan-out area; and at least part of the second bus segment is located in the first non-display area.

[0012] In a second aspect, the embodiments of the present application further provide a display device including the display panel provided by any of the embodiments of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0013] FIG. 1 is a structural schematic diagram of a display panel in the related art;

[0014] FIG. 2 is a structural schematic diagram of a display panel provided by an embodiment of the present application;

[0015] FIG. 3 is a structural schematic diagram of another display panel provided by an embodiment of the present application;

[0016] FIG. 4 is a structural schematic diagram of another display panel provided by an embodiment of the present application;

[0017] FIG. 5 is an enlarged structural schematic diagram of a partial area B1 in the display panel in FIG. 4;

[0018] FIG. 6 is another partial structural schematic diagram of the partial area B1 in FIG. 4;

[0019] FIG. 7 is another partial structural schematic diagram of the partial area B1 in FIG. 4;

[0020] FIG. 8 is another partial structural schematic diagram of the partial area B1 in FIG. 4;

[0021] FIG. 9 is a structural schematic diagram of another display panel provided by an embodiment of the present application;

[0022] FIG. 10 is a structural schematic diagram of another display panel provided by an embodiment of the present application;

[0023] FIG. 11 is a cross-sectional structural schematic diagram of a display panel provided by an embodiment of the present application;

[0024] FIG. 12 is a structural schematic diagram of another display panel provided by an embodiment of the present application;

[0025] FIG. 13 is another partial structural schematic diagram of the partial area B1 in FIG. 4;

[0026] FIG. 14 is a structural schematic diagram of another display panel provided by an embodiment of the present application;

[0027] FIG. 15 is a structural schematic diagram of another display panel provided by an embodiment of the present application;

[0028] FIG. 16 is a structural schematic diagram of a pixel driving circuit provided by an embodiment of the present application;

[0029] FIG. 17 is a structural schematic diagram of another pixel driving circuit provided by an embodiment of the present application;

[0030] FIG. 18 is a structural schematic diagram of another pixel driving circuit provided by an embodiment of the present application;

[0031] FIG. 19 is a structural schematic diagram of another display panel provided by an embodiment of the present application;

[0032] FIG. 20 is a structural schematic diagram of a display device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0033] In the related art, in order to achieve a narrow frame design of a display panel, a fanout in AA (FIAA) technology is used to lead out the fanout of the original display panel lower frame from the display area, thereby reducing the lower frame width. In the process of implementing the present application, the applicant found that the side frame width of the display panel is large, which is not conducive to the design of a narrow frame. As shown in FIG. 1, which is a structural schematic diagram of a display panel in the related art, the non-display area NA' of the display panel includes a plurality of buses arranged around the display area AA'. Each bus outputs a corresponding signal to the display area AA'. For example, buses BUS1' and BUS2' arranged to output reference voltages, and BUS3' arranged to output a power signal. In the Y' direction, the opposite sides of the display area AA' are provided with side frames, one side of which is provided with a binding area 12' as a lower frame. In the X' direction, the opposite sides of the display area AA' are provided with a left frame and a right frame. The applicant found that the lower frame of the related technical solution needs to be designed with FIAA and fanout, so the buses BUS1', BUS2' and BUS3' are arranged in the side frame. The display panel side frame usually has many drive circuits, and the above buses occupy a large space of the side frame, which is not conducive to the design of a narrow frame of the side frame.

[0034] In order to reduce the width of the side frame of the display panel and achieve the design of a narrow frame of the side frame, an embodiment of the present application provides a display panel, as shown in FIG. 2, which is a structural schematic diagram of a display panel provided by an embodiment of the present application, including a display area AA and a non-display area NA surrounding the display area AA;

[0035] The display area AA includes a plurality of first reference voltage lines 11, a plurality of second reference voltage lines 12 and a data line 23; the data line 23 extends along a first direction Y;

[0036] The non-display area NA includes a first reference voltage bus 13 and a second reference voltage bus 14; the first reference voltage line 11 is electrically connected to the first reference voltage bus 13; the second reference voltage line 12 is electrically connected to the second reference voltage bus 14;

[0037] The first reference voltage bus 13 includes a first bus segment 131 and a second bus segment 132.

[0038] The non-display area NA includes a fan-out area 15 and a first non-display area NA1 located on both sides of the display area AA along the first direction Y; at least part of the first bus segment 131 is located in the fan-out area 15; and at least part of the second bus segment 132 is located in the first non-display area NA1.

[0039] In the embodiment, the display area of the display panel is provided with a first reference voltage line, a second reference voltage line and a data line extending along the first direction, and the non-display area of the display panel includes a first reference voltage bus and a second reference voltage bus. The first reference voltage bus is configured to transmit a first reference voltage to the first reference voltage line, and the second reference voltage bus is configured to transmit a second reference voltage to the second reference voltage line. The first reference voltage bus includes a first bus segment and a second bus segment, and the display area is respectively provided with a fan-out area and a first non-display area on opposite sides along the first direction. At least part of the first bus segment is located in the fan-out area, and at least part of the second bus segment is located in the first non-display area. In this embodiment, the first reference voltage bus is arranged in the lower frame where the fan-out area is located and the upper frame where the first non-display area is located, does not occupy the plane area of the side frame connecting the upper frame and the lower frame, leaves layout space for the buses of other signals, reduces the resistance value of the buses of other signals, and can further realize the narrow frame design of the side frame.

[0040] The display panel includes a substrate and a drive circuit layer arranged on one side of the substrate. The display panel includes a display area AA and a non-display area NA, and the non-display area NA is arranged around the display area AA. The display area AA is provided with a data line 23 extending along a first direction Y, wherein the first direction Y is a direction parallel to the plane where the substrate of the display panel is located. The display area AA of the drive circuit layer further includes a pixel drive circuit (not shown in FIG. 2) arranged in an array, and the side of the drive circuit layer away from the substrate further includes a light emitting element. The pixel drive circuit is configured to output a drive current to the light emitting element to make the light emitting element emit light. The data line 23 is configured to provide a data signal for the pixel drive circuit.

[0041] The display area AA further includes a first reference voltage line 11 and a second reference voltage line 12. The first reference voltage line 11 is electrically connected with the first reference voltage bus 13 and is configured to receive a first reference voltage signal vref1. The first reference voltage line 11 is further configured to transmit the first reference voltage signal vref1 to the pixel drive circuit. The second reference voltage line 12 is electrically connected with the second reference voltage bus 14 and is configured to receive a second reference voltage signal vref2. The second reference voltage line 12 is further configured to transmit the second reference voltage signal vref2 to the pixel drive circuit.

[0042] Continuing to refer to FIG. 2, along the first direction Y, the display area AA is provided with a fan-out area 15 and a first non-display area NA1 on opposite sides, respectively. The fan-out area 15 is arranged in a lower step area of the display panel, and a binding area 151 is further arranged on a side of the fan-out area 15 away from the display area AA in the lower step area. The binding area 151 is arranged to bind a driving chip, and a pad terminal of the driving chip is electrically connected to a data line 23 through a fan-out wire in the fan-out area 15, and is arranged to output a signal to the corresponding data line 23. The first reference voltage bus 13 includes at least a first bus segment 131 and a second bus segment 132, and at least part of the first bus segment 131 is arranged in the fan-out area 15, and at least part of the second bus segment 132 is arranged in the first non-display area NA1. The fan-out area 15 and the first non-display area NA1 are connected through a side non-display area. Compared with a case where the first reference voltage bus 13 and the second reference voltage bus 14 are both arranged in the side non-display area, in the embodiment, the first reference voltage bus 13 is arranged in the first non-display area NA1 and the fan-out area 15, that is, the first reference voltage bus 13 is arranged in the upper and lower side frames in the embodiment, so that the width of the side non-display area can be effectively saved, and narrow frame design of the side frame of the display panel can be realized. In addition, because the embodiment can also combine the FIAA technology to reduce the width of the lower frame occupied by the fan-out wire and reduce the width of the fan-out area 15 along the first direction Y, narrow frame design of the lower frame of the display panel can be realized, and the embodiment can simultaneously realize narrow design of the side frame and the lower frame, improve the screen ratio of the display area of the entire display panel, and improve the picture display effect.

[0043] For example, the first reference voltage vref1 is a reset signal provided to a pixel circuit, for example, a reset signal of a control terminal of a driving transistor in a pixel driving circuit, or a reset signal of a light emitting element, and the embodiment does not make special limitation thereto.

[0044] FIG. 3 is a structural schematic diagram of another display panel provided by the embodiment of the application. For example, the non-display area NA can further include a second non-display area NA2 and a third non-display area NA3 located on both sides of the display area AA along a second direction X; the second direction X intersects the first direction Y; the first non-display area NA1 is arranged adjacent to the second non-display area NA2 and the third non-display area NA3, respectively; the second reference voltage bus 14 includes at least a third bus segment 141 and a fourth bus segment 142; at least part of the third bus segment 141 is located in the second non-display area NA2; and at least part of the fourth bus segment 142 is located in the third non-display area NA3.

[0045] As shown in FIG. 3, in the embodiment, along the first direction Y, the first non-display area NA1 and the fan-out area 15 are arranged on opposite sides of the display area AA; along the second direction X, the second non-display area NA2 and the third non-display area NA3 are arranged on opposite sides of the display area AA. Among them, the first non-display area NA1 is arranged adjacent to the second non-display area NA2 and the third non-display area NA3 respectively; the fan-out area 15 is arranged adjacent to the second non-display area NA2 and the third non-display area NA3 respectively. In the embodiment, the second direction X and the first direction Y are intersected, for example, the second direction X and the first direction Y can be perpendicular to each other.

[0046] The second reference voltage bus 14 can include a third bus segment 141 and a fourth bus segment 142. At least part of the third bus segment 141 is arranged in the second non-display area NA2, and at least part of the fourth bus segment 142 is arranged in the third non-display area NA3. In the embodiment, the first bus segment 131 of the first reference voltage bus 13 is located in the fan-out area 15, and the second bus segment 132 is located in the first non-display area NA1; the third bus segment 141 of the second reference voltage bus 14 is located in the second non-display area NA2, and the fourth bus segment 142 is located in the third non-display area NA3. That is, the first reference voltage bus 13 is arranged in the non-display area on the opposite side of the display panel along the first direction Y, and the second reference voltage bus 14 is arranged in the non-display area on the opposite side of the display panel along the second direction X. The first reference voltage bus 13 and the second reference voltage bus 14 are not arranged side by side in the same non-display area, so that the fan-out area 15, the first non-display area NA1, the second non-display area NA2 and the third non-display area NA3 are not occupied by multiple side-by-side buses. The setting width of the non-display area is reduced, and the narrow frame design of the display panel is further realized. Compared with the scheme shown in FIG. 1, the first reference voltage bus 13 is arranged in the upper frame and the lower frame in the embodiment, which effectively reduces the occupied space of the side frame, facilitates the wiring and arrangement of the second reference voltage bus 14 in the side frame, reduces the transmission resistance of the second reference voltage bus 14, and effectively reduces the signal line overlapping of the side frame, and optimizes the transmission performance of multiple signal lines.

[0047] Continuing to refer to FIG. 3, for example, the adjacent non-display areas NA can be connected through the R-angle area 16. In order to enhance the use and viewing experience of the display panel, the display panel in the embodiment can be a rounded corner screen, for example, as shown in FIG. 3, the adjacent two non-display areas NA can be connected through the R-angle area 16. For example, the first non-display area NA1 and the second non-display area NA2 are connected through the R-angle area 16. The arrangement of the R-angle area 16 makes the display panel form a rounded rectangular plane. The display panel including a curved portion is not only beautiful but also not easy to be damaged, while the display panel including a right angle is easy to be damaged under force during use.

[0048] As shown in FIG. 3, for example, the first non-display area NA1 and the second non-display area NA2 can be connected through the first R-angle area 161; the first non-display area NA1 and the third non-display area NA3 can be connected through the second R-angle area 162; and the second bus segment 132 can include a first part 1311 located at the first R-angle area 161 and / or a second part 1312 located at the second R-angle area 162. For example, the second bus segment 132 can be partially arranged in the first non-display area NA1, or entirely arranged in the first non-display area NA1. FIG. 3 illustrates the case where the second bus segment 132 is partially arranged in the first non-display area NA1. Since each of the two adjacent non-display areas NA is connected through an R-angle area 16, in order to further extend the arrangement length of the second bus segment 132 and optimize the resistance of the first reference voltage bus 13, the second bus segment 132 can be extended to the R-angle areas 16 on both sides of the first non-display area NA1. For example, as shown in FIG. 3, the first R-angle area 161 and the second R-angle area 162 are arranged on both sides of the first non-display area NA1, the part of the second bus segment 132 extended to the first R-angle area 161 can be the first part 1311, and the part of the second bus segment 132 extended to the second R-angle area 162 can be the second part 1312. In this embodiment, the second bus segment 132 can include at least one of the first part 1311 and the second part 1312. On the one hand, the first reference voltage bus 13 and the second reference voltage bus 14 are arranged in different non-display areas respectively, so as to reduce the width of the frame, for example, the width of the side frame; on the other hand, the second bus segment 132 in the first non-display area NA1 is extended to the R-angle area 16, which can effectively increase the length of the first reference voltage bus 13, so as to directly provide the first reference voltage signal vref1 for more first reference voltage lines 11, instead of transmitting the first reference voltage signal vref1 through other first reference voltage lines 11, which is beneficial to reduce the voltage drop of the first reference voltage signal vref1 on the first reference voltage line 11 and improve the power supply effect of the first reference voltage bus 13 on the pixel driving circuit. It can be understood that the display area of the display panel including the R-angle area is usually arranged in correspondence with the shape of the R-angle area, that is, the R-angle area also corresponds to a part of the pixel driving circuit, and extending the second bus segment 132 in the first non-display area NA1 to the R-angle area 16 can make the pixel driving circuit in the display area connected with the second bus segment 132, thereby improving the power supply effect of the first reference voltage line 11.

[0049] With reference to FIG. 3, for example, the fan-out area 15 and the second non-display area NA2 can be connected by a third R-angle area 163; the fan-out area 15 and the third non-display area NA3 can be connected by a fourth R-angle area 164; the first bus segment 131 includes a third portion 1313 located at the third R-angle area 163 and / or a fourth portion 1314 located at the fourth R-angle area 164. Similarly, the first bus segment 131 can be partially arranged in the fan-out area 15 or entirely arranged in the fan-out area 15. FIG. 3 illustrates the case where the first bus segment 131 is partially arranged in the fan-out area 15. In order to further extend the arrangement length of the first bus segment 131 and optimize the resistance of the first reference voltage bus 13, the first bus segment 131 can be extended to the R-angle areas 16 on both sides of the first non-display area NA1. For example, as shown in FIG. 3, the fan-out area 15 is provided with the third R-angle area 163 and the fourth R-angle area 164 on both sides, and the first bus segment 131 can be extended to the third R-angle area 163 to form the third portion 1313, the first bus segment 131 can also be extended to the fourth R-angle area 164 to form the fourth portion 1314, or the first bus segment 131 can be extended to the third R-angle area 163 and the fourth R-angle area 164 respectively to form the third portion 1313 and the fourth portion 1314. In this embodiment, the first bus segment 131 in the fan-out area 15 is extended to the R-angle area 16, which can effectively increase the length of the first reference voltage bus 13, facilitate the provision of the first reference voltage signal vref1 to more first reference voltage lines 11, and improve the power supply effect of the first reference voltage bus 13 on the pixel driving circuit. It can be understood that the display area of the display panel including the R-angle area is usually provided with a shape corresponding to the R-angle area, that is, the R-angle area also corresponds to a part of the pixel driving circuit. The extension of the first bus segment 131 in the fan-out area 15 to the R-angle area 16 can make the pixel driving circuit in the display area connected to the first bus segment 131 and the extension (the third portion 1313 and / or the fourth portion 1314) thereof, and improve the power supply effect of the first reference voltage line 11.

[0050] FIG. 4 is a structural schematic diagram of another display panel provided by an embodiment of the present application, and FIG. 5 is a partial structural schematic diagram of a local area B1 in FIG. 4. For example, the display area AA can include arrayed pixel driving circuits 18; the display area AA includes a first special-shaped area 17; the first special-shaped area 17 is adjacent to the R-angle area 16, and the pixel driving circuits 18 in the first special-shaped area 17 are distributed in a stepped manner; the first bus segment 131 and the second bus segment 132 extend along the edge of the first special-shaped area 17.

[0051] As shown in FIG. 4, the display area AA includes the pixel driving circuit 18 arranged in an array. The display area AA further includes the first reference voltage line 11 extending along the first direction Y and / or extending along the second direction X, and the second reference voltage line 12 extending along the first direction Y and / or extending along the second direction X, the first reference voltage line 11 and the second reference voltage line 12 crossing to define the area where the pixel driving circuit 18 can be arranged. For example, the display panel in FIG. 4 includes the first reference voltage line 11 extending along the first direction Y and extending along the second direction X, and the second reference voltage line 12 extending along the first direction Y and extending along the second direction X. For the purpose of distinguishing the first reference voltage line 11 from the second reference voltage line 12, the first reference voltage line 11 is represented by a solid line and the second reference voltage line 12 is represented by a dashed line in this embodiment.

[0052] According to the above embodiment, the adjacent non-display areas are adjacent through the R corner area 16, and the part of the display area AA adjacent to the R corner area 16 in the display panel is also a special-shaped structure, as shown in FIG. 4, the display area AA includes a first special-shaped area 17, and the first special-shaped area 17 is adjacent to the R corner area 16. As shown in FIG. 5, FIG. 5 is an enlarged structural schematic diagram of a local area B1 in the display panel in FIG. 4. It should be noted that the local area B1 is taken as the structure of part of the first special-shaped area 17 and part of the R corner area 16, so as to clearly obtain the structure of the display panel at the junction position of the first special-shaped area 17 and the R corner area 16. As shown in FIG. 5, in the first special-shaped area 17, the pixel driving circuit 18 is distributed in a stepped manner along the extension direction of the first reference voltage line 11. Because the part of the first reference voltage line 11 extending to the R corner area 16 is a curve, the pixel driving circuit 18 is arranged in a stepped manner, and if the pixel driving circuit 18 is arranged in rows along the second direction X, the number of pixel driving circuits 18 in each row gradually decreases along the first direction Y, so that the edge of the first special-shaped area 17 is arranged in a stepped manner. As shown in FIG. 5, only part of the metal film layer of the driving circuit layer is shown in FIG. 5, which specifically shows two metal layers, one of which is the film layer in which the first reference voltage line 11 is arranged. In this embodiment, the part of the second bus segment 132 extending to the R corner area 16 can be arranged along the edge of the first special-shaped area 17, that is, the second bus segment 132 of the R corner area 16 is also stepped. The stepped second bus segment 132 can be arranged close to the edge of the first special-shaped area 17, effectively saving the space of the R corner area 16 occupied by the second bus segment 132, facilitating the layout of other circuits and wires in the R corner area 16, and reducing the width of the R corner area 16, further realizing the narrow frame design of the R corner area 16. As shown in FIG. 4 and FIG. 5, the part of the second bus segment 132 extending to the first R corner area 161 is a first part 1311, and the first part 1311 is arranged along the pixel driving circuit 18 arranged in a stepped manner. In addition, as shown in FIG. 4, the part of the first bus segment 131 extending to the R corner area 16 can also extend along the edge of the first special-shaped area 17, so that the first bus segment 131 is arranged in a stepped manner in the R corner area 16, which can electrically connect the pixel circuits corresponding to the R corner area 16 of the first bus segment 131, and at the same time, the space utilization rate is higher, the space occupied by the R corner area 16 is reduced, and the narrow frame design of the display panel is further realized.

[0053] With reference to FIGS. 3 and 4, for example, the third bus segment 141 and the fourth bus segment 142 can extend along the edge of the first irregular area 17. In the present embodiment, the third bus segment 141 can be arranged only in the second non-display area NA2, or can extend from the second non-display area NA2 to the R corner area 16. As shown in FIG. 3, the second non-display area NA2 is adjacent to the first R corner area 161 and the third R corner area 163, respectively, and thus the third bus segment 141 can extend to the first R corner area 161 and / or the third R corner area 163 to increase the length of the third bus segment 141, so that the third bus segment 141 can be connected to more second reference voltage lines 12, thereby directly providing the second reference voltage signal vref2 to more second reference voltage lines 12 instead of transmitting the second reference voltage signal vref2 to each other through other second reference voltage lines 12. This is advantageous to reduce the voltage drop of the second reference voltage signal vref2 on the second reference voltage lines 12, and to improve the power supply effect of the second reference voltage bus 14 on the pixel driving circuit. Similarly, the fourth bus segment 142 can extend to the second R corner area 162 and / or the fourth R corner area 164 to increase the length of the fourth bus segment 142, so that the fourth bus segment 142 can be connected to more second reference voltage lines 12, thereby reducing the voltage drop of the second reference voltage signal vref2 on the second reference voltage lines 12, and improving the power supply effect of the second reference voltage bus 14 on the pixel driving circuit.

[0054] FIG. 6 is another partial structure diagram of the partial area B1 in FIG. 4. When the display area adjacent to the R corner area 16 includes the first irregular area 17, and the edge of the first irregular area 17 includes the pixel driving circuit 18 arranged in a stepped manner, the part of the third bus segment 141 and the fourth bus segment 142 extending to the R corner area 16 can extend along the edge of the first irregular area 17, i.e., along the pixel driving circuit 18 arranged in a stepped manner. For example, as shown in FIG. 6, the part of the third bus segment 141 extending to the first R corner area 161 forms a step, and the part of the second bus segment 132 extending to the first R corner area 161 also forms a step. In the present embodiment, the first reference voltage bus 13 and the second reference voltage line 12 are arranged in a stepped manner in the R corner area 16, which further reduces the area occupied by the above-mentioned bus in the R corner area 16, reduces the frame width of the R corner area 16, and further realizes the narrow frame design of the R corner area 16.

[0055] FIG. 7 is another partial structure diagram of the local area B1 in FIG. 4. FIG. 8 is another partial structure diagram of the local area B1 in FIG. 4. For example, the display panel can further include: a shielding bus 19; the shielding bus 19 extends along the edge of the first irregular area 17; in the first irregular area 17, the shielding bus 19 includes a linear first bus 191 and a stepped second bus 192; the first reference voltage bus 13 includes a plurality of first stages 133 extending in the first direction Y and a plurality of second stages 134 extending in the second direction X in the first irregular area 17; the stepped second bus 192 includes a plurality of third stages 193 extending in the first direction Y and a plurality of fourth stages 194 extending in the second direction X in the first irregular area 17; and there is an overlapping area between the second stage 134 and the fourth stage 194.

[0056] In the embodiment, a shielding layer M0 can be further arranged between the substrate and the driving circuit layer. In the plane parallel to the substrate, the shielding layer M0 and the active layer 18a of the driving transistor in the pixel driving circuit have an overlapping area, so as to avoid the driving transistor from generating a leakage current. In addition, the shielding layer M0 needs to be applied with a fixed potential, so as to avoid the shielding layer from floating, thereby avoiding the shielding layer from affecting other metal layers. As shown in FIG. 7, FIG. 7 only shows two film layers of the shielding layer and the active layer 18a. In the embodiment, the shielding layer can form a shielding bus 19, and the shielding bus 19 can be arranged around the display area. In the first irregular area 17, the shielding bus 19 includes a linear first bus 191 and a stepped second bus 192. The linear first bus 191 is arranged in a linear shape along the edge of the first irregular area 17. The stepped second bus 192 includes a plurality of third stages 193 extending in the first direction Y and a plurality of fourth stages 194 extending in the second direction X, and the third stages 193 and the fourth stages 194 are alternately connected to form a stepped shape. The first bus 191 and the stepped second bus 192 are electrically connected to form a whole bus. In the embodiment, the shielding bus 19 can be arranged to simultaneously supply the shielding layer M0 corresponding to a plurality of rows of pixel driving circuits at a plurality of connection ends, so as to reduce the resistance value of the shielding layer M0 and reduce the voltage drop (IR drop) of the shielding layer M0.

[0057] With reference to FIG. 8, the metal layer M0 and the metal layer M3 provided with the first reference voltage bus 13 are included in FIG. 8. In the first special-shaped area 17, the first reference voltage bus 13 includes a plurality of first stages 133 extending along the first direction Y and a plurality of second stages 134 extending along the second direction X, and the first stages 133 and the second stages 134 are alternately connected to form a stepped shape (staircase shape). Because the first reference voltage bus 13 and the shielding bus 19 are located in different film layers, in a plane parallel to the substrate, the fourth stage 194 of the stepped second bus 192 extending along the second direction X overlaps the second stage 134 of the first reference voltage bus 13 extending along the second direction X in the overlapping area B2. The design of the overlapping area B2 can improve the utilization of the planar space, save the space of the R-angle area in the plane parallel to the substrate, and overlap the first reference voltage bus 13 and the shielding bus 19, which can improve the transmission effect and stability of the first reference voltage signal on the first reference voltage bus 13, so that the pixel driving circuit is completely reset in the reset stage and does not affect the conduction of the pixel driving circuit in the next frame time, thereby enhancing the reliability of the pixel driving circuit and improving the display effect of the display panel.

[0058] FIG. 9 is a structural schematic diagram of another display panel provided by an embodiment of the present application. For example, the first reference voltage bus 13 can further include a fifth bus segment 135. The fifth bus segment 135 is located in the second non-display area NA2. In this embodiment, the first reference voltage bus 13 can be arranged on one side of the side bezel, as shown in FIG. 9. The fifth bus segment 135 can be arranged in the second non-display area NA2, for example, the second bus segment 132, the fifth bus segment 135 and the first bus segment 131 are sequentially electrically connected to extend the total length of the first reference voltage bus 13. In this embodiment, the third non-display area NA3 is not provided with the first reference voltage bus 13, so that the total length of the first reference voltage bus 13 is extended to the second non-display area NA2 in this embodiment to connect more first reference voltage lines corresponding to the pixel driving circuits in the row, reduce the loss of the first reference voltage line in the transmission process, improve the reliability of the pixel driving circuit, and thus improve the reliability of the entire display panel.

[0059] Fig. 10 is a structural schematic view of another display panel provided by the embodiment of the present application. For example, the first reference voltage bus 13 can further include: a sixth bus segment 136; the sixth bus segment 136 is located in the third non-display area NA3. In the embodiment, the sixth bus segment 136 is further formed in the third non-display area NA3. For example, the second bus segment 132, the fifth bus segment 135, the first bus segment 131 and the sixth bus segment 136 can be electrically connected in sequence, effectively lengthening the first reference voltage bus 13, so that more first reference voltage lines corresponding to the row pixel driving circuit can be connected through the plurality of connection ends, reducing the loss of the first reference voltage line in the transmission process, improving the reliability of the pixel driving circuit, and thus improving the reliability of the entire display panel. For example, along the second direction X, the width d1 of the fifth bus segment 135 can be less than the width d2 of the third bus segment 141; the width d3 of the sixth bus segment 136 can be less than the width d4 of the fourth bus segment 142. In order to further reduce the space of the side frame occupied by the first reference voltage bus 13, the width d1 of the fifth bus segment 135 can be less than the width d2 of the third bus segment 141, and the width d3 of the sixth bus segment 136 can be less than the width d4 of the fourth bus segment 142 in the embodiment. Then, the width of the first reference voltage bus 13 in the second non-display area NA2 and the third non-display area NA3 is less than the width of the second reference voltage bus 14 in the second non-display area NA2 and the third non-display area NA3. Therefore, although the first reference voltage bus 13 and the second reference voltage bus 14 are arranged in the side frame in the embodiment, the width of the first reference voltage bus 13 is relatively small, and the width of the side frame occupied by the first reference voltage bus 13 is relatively small, which is conducive to the narrow frame design of the display panel.

[0060] For example, the first bus segment 131, the fifth bus segment 135, the second bus segment 132 and the sixth bus segment 136 can be connected in sequence to form a ring. In the embodiment, the first bus segment 131, the fifth bus segment 135, the second bus segment 132 and the sixth bus segment 136 can be separately arranged, and each of the first bus segment 131, the fifth bus segment 135, the second bus segment 132 and the sixth bus segment 136 can separately output the first reference voltage signal to the first reference voltage line, which can also lengthen the length of the first reference voltage bus and reduce the loss of the first reference voltage signal in the transmission process. In the embodiment, the first bus segment 131, the fifth bus segment 135, the second bus segment 132 and the sixth bus segment 136 can be connected to form a ring, so that only one input end can be arranged when the first reference voltage signal is input to the first reference voltage bus 13, and the input end does not need to be arranged for the first bus segment 131, the fifth bus segment 135, the second bus segment 132 and the sixth bus segment 136, which can simplify the wiring design and reduce the width of the plurality of side frames.

[0061] FIG. 11 is a schematic view of a cross-sectional structure of a display panel provided in an embodiment of the present application. For example, the first reference voltage bus 13 and the second reference voltage bus 14 can be located in different film layers; the fifth bus segment 135 and the third bus segment 141 at least partially overlap; and / or the sixth bus segment 136 and the fourth bus segment 142 at least partially overlap. As shown in FIG. 11, the display panel includes a substrate 100 and a drive circuit layer 101 disposed on one side of the substrate 100. In the display area AA, the drive circuit layer 101 includes pixel drive circuits arranged in an array, and each pixel drive circuit includes a plurality of thin film transistors T. In the non-display area NA, the first reference voltage bus 13 and the second reference voltage bus 14 can be located in different metal layers. When the first reference voltage bus 13 is provided with the fifth bus segment 135 and the sixth bus segment 136, the first reference voltage bus 13 and the second reference voltage bus 14 can be at least partially overlapped, thereby reducing the occupation of the planar space of the side frame, improving the planar space utilization rate of the display panel, and facilitating the narrow frame design of the side frame of the display panel. For example, as shown in FIG. 11, the drive circuit layer 101 can include, in sequence, a shielding layer M0, an active layer 18a, a gate layer 102, an intermediate metal layer 103, a source-drain layer 104, a third metal layer M3, and a fourth metal layer M4, which are away from the substrate 100. The first reference voltage bus 13 can be disposed on the fourth metal layer M4, and the second reference voltage bus 14 can be disposed on the third metal layer M3. In the plane parallel to the substrate 100, the fifth bus segment 135 and the third bus segment 141 can have an overlapping area, and the sixth bus segment 136 and the fourth bus segment 142 can also have an overlapping area. In addition, as shown in FIG. 11, the display area AA also includes a data line 11 disposed in the same layer as the second reference voltage bus 14, and the data line 11 is electrically connected to the source or drain of the thin film transistor T. The display area AA also includes an auxiliary wire 61 disposed in the same layer as the first reference voltage bus 13, which is an FIAA wire and is configured to transfer the fan-out line of the data line close to the R corner region to the display area AA.

[0062] For example, the first reference voltage bus 13 and the second reference voltage bus 14 can be disposed in the same layer. It can be understood that the first reference voltage bus 13 and the second reference voltage bus 14 can be disposed in the same layer. For example, the first reference voltage bus 13 and the second reference voltage bus 14 can be disposed in the third metal layer M3. In order to reduce the planar space occupied by the first reference voltage bus 13 and the second reference voltage bus 14, the width of the bus segment of the first reference voltage bus 13 can be controlled to be smaller than the width of the second reference voltage bus 14, thereby achieving the narrow frame design of the display panel and improving the user viewing experience.

[0063] Continuing to refer to FIG. 3, for example, the first reference voltage line 11 can include a first connection line 111 extending along the first direction Y and a second connection line 112 extending along the second direction X; the first connection line 111 is electrically connected with the second connection line 112; the second reference voltage line 12 includes a third connection line 121 extending along the first direction Y and a fourth connection line 122 extending along the second direction X; the third connection line 121 is electrically connected with the fourth connection line 122; the first connection line 111 is connected with the first bus segment 131 and the second bus segment 132, respectively; the fourth connection line 122 is connected with the third bus segment 141 and the fourth bus segment 142, respectively.

[0064] In the embodiment, the first reference voltage line 11 can form a grid structure in the display area, for example, the first reference voltage line 11 includes a first connection line 111 extending along the first direction Y and a second connection line 112 extending along the second direction X, as shown in FIG. 3, at the intersection of the first connection line 111 and the second connection line 112, the first connection line 111 and the second connection line 112 can be electrically connected by a via. Similarly, the second reference voltage line 12 can also form a grid structure in the display area, for example, including a third connection line 121 extending along the first direction Y and a fourth connection line 122 extending along the second direction X, and the third connection line 121 and the fourth connection line 122 are electrically connected by a via.

[0065] In the embodiment, because the first reference voltage bus 13 is arranged in the fan-out area 15 and the first non-display area NA1, the first connection line 111 extending along the first direction Y is connected with the first bus segment 131 and the second bus segment 132, respectively, to obtain the first reference voltage signal vref1 and transmit it to the second connection line 112. Similarly, the second reference voltage line 12 is arranged in the second non-display area NA2 and the third non-display area NA3, the fourth connection line 122 extending along the second direction X is connected with the third bus segment 141 and the fourth bus segment 142, respectively, to obtain the second reference voltage signal vref2 and transmit it to the third connection line 121. It should be noted that because the length of the upper and lower frames in the second direction X is less than the length of the side frames in the first direction Y, that is, the length of the fan-out area 15 and the first non-display area NA1 is small, the embodiment can arrange the bus branch 137 in the non-display area NA, so that the embodiment transmits the first reference voltage signal vref1 to the bus branch 137 through multiple input terminals, and the bus branch 137 is connected to multiple first connection lines 111 in proximity, thereby improving the power supply capability of the first reference voltage bus 13 to drive the pixel circuit. In addition, as shown in FIG. 2, the first reference voltage line 11 can only be arranged with the first connection line 111 extending along the first direction Y, and the second reference voltage line 12 can only be arranged with the fourth connection line 122 extending along the second direction X, to reduce the wiring density of the display area.

[0066] FIG. 12 is a structural schematic diagram of another display panel provided by the embodiment of the present application. In FIG. 12, the structures of the first reference voltage line 11 and the second reference voltage line 12 are omitted, and only the power lines are shown separately. For example, the display area AA can further include: the first power line 21 and the second power line 22 extending along the second direction X; the non-display area NA further includes the first power bus 25 and the second power bus 24; the first power bus 25 is connected with the first power line 21; the second power bus 24 is connected with the second power line 22; the first power bus 25 includes the portions located in the second non-display area NA2 and the third non-display area NA3 and the portion extending to the R corner area 16; and / or, the second power bus 24 includes the portions located in the second non-display area NA2 and the third non-display area NA3 and the portion extending to the R corner area 16.

[0067] In addition to the first reference voltage bus 13 and the second reference voltage bus 14, the buses in the non-display area NA further include the first power bus 25 and the second power bus 24. For example, as shown in FIG. 12, in the direction away from the display area AA, the buses in the non-display area NA are sequentially provided with the reference voltage bus 13, the second reference voltage bus 14, the first power bus 25 and the second power bus 24. The first power bus 25 can include the portions located in the second non-display area NA2 and the third non-display area NA3 and the portion extending to the R corner area 16, and the second power bus 24 can also include the portions located in the second non-display area NA2 and the third non-display area NA3 and the portion extending to the R corner area 16. The display area AA is provided with the first power line 21 and the second power line 22, both of which extend along the second direction X. The first power line 21 is configured to obtain the first power signal PVDD from the first power bus 25 and transmit the first power signal PVDD to the plurality of pixel driving circuits, and the second power line 22 is configured to obtain the second power signal PVEE from the second power bus 24 and transmit the second power signal PVEE to the plurality of pixel driving circuits. The embodiment shows the case of more types of buses. The multiple types of buses are usually provided in the third metal layer M3. When the buses are more, the first reference voltage bus 13 is only provided in the fan-out area 15 and the first non-display area NA1, occupying the area of the upper and lower frames. The remaining buses are provided in the second non-display area NA2 and the third non-display area NA3, occupying the space of the side frames. The embodiment effectively balances the bus arrangement of multiple frames, so that the frame width of the display panel is smaller as a whole, realizing the user's narrow frame requirement.

[0068] In addition, the display panel can further include a first power line 21 and a second power line 22 extending along the second direction Y. Then, the first power line 21 and the second power line 22 can form a mesh shape. FIG. 13 is another partial structure diagram of the local area B1 in FIG. 4. As shown in FIG. 13, the second power bus 24 can form a linear second power bus 241 and a stepped second power bus 242 in the first irregular area 17, so as to reduce the resistance value of the second power bus 24, thereby reducing the loss of the second power signal PVEE in the transmission process. Similarly, the first power bus 25 can also be even the above linear and stepped combination, so as to improve the signal transmission effect of the first power signal PVDD.

[0069] Fig. 14 is a structural schematic diagram of another display panel provided by the embodiment of the present application. For example, the display panel can include: touch wires 106 connected with touch electrodes 105; a fan-out area 15 including a plurality of lead lines; the lead lines at least include: a first reference voltage lead line 31, a first power supply lead line 32, a second power supply lead line 33, a second reference voltage lead line 34, and a touch lead line 35; the first reference voltage lead line 31 is electrically connected with the first reference voltage bus 13; the second reference voltage lead line 34 is electrically connected with the second reference voltage bus 14; the touch lead line 35 is electrically connected with the touch wire 106; the first power supply lead line 32 is connected with the first power supply bus 25; the second power supply lead line 33 is connected with the second power supply bus 24; along the second direction X, the second reference voltage lead line 34 is located between the first reference voltage lead line 31 and the touch lead line 35. As shown in Fig. 14, the fan-out area 15 is provided with a signal transmission from the binding area 151 to the corresponding fan-out line. The fan-out area 15 can include the first reference voltage lead line 31, the first power supply lead line 32, the second power supply lead line 33, and the second reference voltage lead line 34, the first reference voltage lead line 31 is configured to transmit the first reference voltage signal vref1 to the first reference voltage bus, the second reference voltage lead line 34 is configured to transmit the second reference voltage signal vref2 to the second reference voltage bus, the first power supply lead line 32 is configured to transmit the first power supply signal PVDD to the first power supply bus 25, and the second power supply lead line 33 is configured to transmit the second power supply signal PVEE to the second power supply bus 24. For the display panel with touch function, a plurality of touch electrodes 105 are provided, and the touch wires 106 connected with the touch electrodes 105, and the corresponding fan-out area 15 is provided with the touch lead line 35. Along the second direction X, the plurality of touch lead lines 35 are arranged at the center position, and the other lead lines are arranged on both sides of the touch lead line 35, and there is a gap between the touch lead line 35 and the other lead lines. In the embodiment, the second reference voltage lead line 34 is located between the first reference voltage lead line 31 and the touch lead line 35, so that the second reference voltage lead line 34 can be arranged in the above-mentioned gap, and has a larger arrangement space. In the embodiment, the width of the second reference voltage lead line 34 can be larger than that of the other lead lines, so as to reduce the resistance value of the second reference voltage lead line 34, reduce the loss of the second reference voltage signal vref2 in the transmission process, and provide strong guarantee for the reset of the light emitting element, improve the display effect of the display panel, and avoid the occurrence of residual image in the display process.

[0070] Continuing to refer to FIG. 14, for example, the non-display area NA can further include a binding area 151; the binding area 151 is located on a side of the fan-out area 15 away from the display area AA; the binding area 151 includes a plurality of pads 411; the pads 411 are respectively connected with corresponding lead wires; along the second direction X, the pad 411 connected with the second reference voltage lead wire 34 is located between the pad 411 connected with the first power supply lead wire 32 and the pad 411 connected with the second power supply lead wire 33; the second reference voltage lead wire 34 connects the corresponding pad 411 by crossing the first reference voltage lead wire 31 by a jumper. In this embodiment, the binding area 151 is provided with the pads 411 corresponding to the fan-out lead wires. Although this embodiment sets the position of the second reference voltage lead wire 34 on the side of the first reference voltage lead wire 31 close to the touch lead wire 35, the path sequence of the driving chip in the related art is that the pad 411 of the second reference voltage lead wire 34 is located on the side of the first reference voltage lead wire 31 away from the touch lead wire 35. For example, as shown in FIG. 14, the second reference voltage lead wire 34 connects the corresponding pad 411 by crossing the first reference voltage lead wire 31 and the first power supply lead wire 32 by a jumper. Then, this embodiment does not need to change the related design of the driving chip, and by connecting the corresponding pads by the jumper while ensuring that the second reference voltage lead wire 34 has a relatively large width, the manufacturing cost of the display panel is effectively reduced.

[0071] FIG. 15 is a structural schematic diagram of another display panel provided by an embodiment of the present application. For example, the display area AA can further include an adjustment signal line 51; the non-display area NA further includes an adjustment signal bus 52; the adjustment signal bus 52 is electrically connected with the adjustment signal line 51; the adjustment signal bus 52 includes a seventh bus segment 53 and an eighth bus segment 54; the seventh bus segment 53 is located in the second non-display area NA2; the eighth bus segment 54 is located in the third non-display area NA3. The adjustment signal bus 52 can output an adjustment signal to the adjustment signal line 51 in the display area AA, so that the adjustment signal line 51 transmits the adjustment signal to the pixel driving circuit, and is configured to adjust the bias state of the driving transistor in the pixel driving circuit. The adjustment signal bus 52 includes the seventh bus segment 53 and the eighth bus segment 54, wherein the seventh bus segment 53 is located in the second non-display area NA2, and the eighth bus segment 54 is located in the third non-display area NA3. For example, the seventh bus segment 53 further extends to the R corner area 16 on both sides of the second non-display area NA2, and the eighth bus segment 54 extends to the R corner area 16 on both sides of the third non-display area NA3, thereby enhancing the power supply effect of the adjustment signal bus 52 for the pixel driving circuit, effectively preventing the bias problem of the driving transistor, and improving the accuracy of the picture display of the display panel. It should be noted that the specific film layer of the adjustment signal bus 52 is shown in FIG. 5, and the adjustment signal bus 52 is arranged on the side of the second reference voltage bus 14 away from the display area.

[0072] With reference back to FIG. 15, for example, the adjusting signal line 51 can include a fifth connection line 511 extending along the first direction Y and a sixth connection line 512 extending along the second direction X; the fifth connection line 511 is electrically connected with the sixth connection line 512; the sixth connection line 512 is electrically connected with the seventh bus segment 53 and the eighth bus segment 54, respectively. In this embodiment, the fifth connection line 511 extending along the first direction Y and the sixth connection line 512 extending along the second direction X form a grid-shaped adjusting signal line 51, which reduces the loss of the adjusting signal in the transmission process and improves the control performance of the adjusting signal on the pixel driving circuit. In addition, the display area AA can also be provided with the first reference voltage line 11 which can include a first connection line 111 extending along the first direction Y and a second connection line 112 extending along the second direction X, so as to reduce the loss of the first reference voltage signal vref1 in the transmission process. The second reference voltage line 12 includes a fourth connection line 122 extending along the second direction X. Of course, this embodiment can also be provided with a third connection line (not shown in FIG. 15) of the second reference voltage line 12 extending along the first direction Y. In this embodiment, the grid structure of the adjusting signal line 51, the first reference voltage line 11 and the second reference voltage line 12 can be formed in the display area at the same time, which improves the driving ability of the adjusting signal bus 52, the first reference voltage bus 13 and the second reference voltage bus 14 on the pixel driving circuit.

[0073] With reference back to FIG. 15, for example, the first reference voltage bus 13, the second reference voltage bus 14 and the adjusting signal bus 52 can be provided in the same layer. As shown in FIG. 15, the first reference voltage bus 13, the second reference voltage bus 14 and the adjusting signal bus 52 are provided side by side, and the first reference voltage bus 13 is provided in the fan-out area 15 and the first non-display area NA1 of the display panel, occupying the area of the upper and lower bezels, and the second reference voltage bus 14 and the adjusting signal bus 52 are provided in the second non-display area NA2 and the third non-display area NA3, occupying the space of the side bezels. Therefore, this embodiment effectively balances the bus arrangement of the multiple bezels, so that the overall bezel width of the display panel is relatively small, realizing the user's narrow bezel requirement.

[0074] With reference back to FIG. 15, for example, the display area AA can also include the adjusting signal line 51; the non-display area NA also includes the adjusting signal bus 52; the adjusting signal bus 52 is electrically connected with the adjusting signal line 51; the lead wire also includes the adjusting signal lead wire 55; the adjusting signal lead wire 55 is electrically connected with the adjusting signal bus 52; along the second direction X, the second reference voltage lead wire 34 is located between the adjusting signal lead wire 55 and the touch lead wire 35; the adjusting signal lead wire 55 is located between the first reference voltage lead wire 31 and the second reference voltage lead wire 34.

[0075] The touch wires 106 of the touch electrodes 105 are omitted in FIG. 15, and only the touch leads 35 are shown. In this embodiment, the fan-out area 15 includes an adjusting signal lead 55, which can transmit an adjusting signal to the adjusting signal bus 52, so that the adjusting signal bus 52 transmits the signal to the fifth connecting line 511 and the sixth connecting line 512. In the second direction X, a plurality of touch leads 35 are arranged at the center position, and other leads are arranged on both sides of the touch leads 35, and there is a gap between the touch leads 35 and the other leads. In this embodiment, the second reference voltage lead 34 is located between the first reference voltage lead 31 and the touch lead 35, so that the second reference voltage lead 34 can be arranged in the above-mentioned gap, and has a larger arrangement space. In this embodiment, the width of the second reference voltage lead 34 can be greater than that of the other leads, so as to reduce the resistance value of the second reference voltage lead 34, reduce the loss of the second reference voltage signal vref2 in the transmission process, and provide strong guarantee for the reset of the light emitting element in this embodiment, improve the display effect of the display panel, and avoid the occurrence of residual image in the display process. It should be noted that the adjusting signal lead 55 is located between the first reference voltage lead 31 and the second reference voltage lead 34, so that the adjusting signal lead 55 is closer to the touch lead 35, and also has a wider arrangement space. The width of the adjusting signal lead 55 can be greater than that of the other leads, so as to reduce the loss of the adjusting signal in the transmission process.

[0076] For example, the non-display area NA can further include a binding area 151; the binding area 151 is located on the side of the fan-out area 15 far away from the display area AA; the binding area 151 includes a plurality of pads 411; the pads 411 are respectively connected with corresponding leads; along the second direction X, the pad 411 connected with the second reference voltage lead 34 is located between the pad 411 connected with the first power lead 32 and the pad 411 connected with the second power lead 33; the second reference voltage lead 34 connects the corresponding pad 411 through the jumper across the first reference voltage lead 31 and the adjusting signal lead 55. In the related art, the path sequence of the driving chip is that the pad 411 of the second reference voltage lead 34 is located on the side of the pad 411 of the first reference voltage lead 31 far away from the pad 411 of the touch lead 35. For example, as shown in FIG. 15, the second reference voltage lead 34 connects the corresponding pad 411 through the jumper across the first reference voltage lead 31, the adjusting signal lead 55 and the first power lead 32. In this embodiment, the related design of the driving chip does not need to be changed, and the width of the second reference voltage lead 34 and the adjusting signal lead 55 is ensured to be large, and the corresponding pads are connected through the jumper, so as to effectively reduce the manufacturing cost of the display panel.

[0077] For example, the display area AA can include an array of pixel driving circuits. As shown in FIG. 16, which is a structural schematic diagram of a pixel driving circuit according to an embodiment of the present application. The pixel driving circuit 18 includes a driving transistor 181, a first reset module 182, and a second reset module 183. The first end of the first reset module 182 is electrically connected to the control end of the driving transistor 181, and the second end of the first reset module 182 is electrically connected to the first reference voltage line 11. The first end of the driving transistor 181 is electrically connected to the first power supply line. The second end of the driving transistor 181 is electrically connected to the first end of the light emitting element D1. The first end of the second reset module 183 is electrically connected to the first end of the light emitting element D1, and the second end of the second reset module 183 is electrically connected to the second reference voltage line 12. The second end of the light emitting element D1 is electrically connected to the second power supply line.

[0078] In this embodiment, the pixel driving circuit 18 includes the first reset module 182 and the second reset module 183. The first reset module 182 is configured to transmit the first reference voltage signal vref1 output by the first reference voltage line 11 to the control end of the driving transistor 181, and reset the control end of the driving transistor 181, so as to prevent the current frame picture from having residual voltage of the previous frame picture. The second reset module 183 is configured to transmit the second reference voltage signal vref2 output by the second reference voltage line 12 to the first end of the light emitting element D1, and reset the first end of the light emitting element D1, so as to avoid the light emitting element D1 from having a leakage current. When the pixel driving circuit 18 needs to output a driving current, the driving transistor 181 is turned on, and the first power supply line, the driving transistor 181, the light emitting element D1, and the second power supply line are sequentially connected to form a path.

[0079] FIG. 17 is a structural schematic diagram of another pixel driving circuit provided by an embodiment of the present application. For example, the pixel driving circuit 18 can further include a storage capacitor C1, a light emitting control module 184, a data writing module 185, and a threshold value grabbing module 186; a first plate of the storage capacitor C1 is electrically connected with the first power supply line 21, and a second plate of the storage capacitor C1 is electrically connected with the control terminal of the driving transistor 181; a first terminal of the data writing module 185 is electrically connected with the first terminal of the driving transistor 181, and a second terminal of the data writing module 185 is electrically connected with the corresponding data line 23; a first terminal of the threshold value grabbing module 186 is electrically connected with the control terminal of the driving transistor 181, and a second terminal of the threshold value grabbing module 186 is electrically connected with the second terminal of the driving transistor 181; a first terminal of a first light emitting control unit 187 of the light emitting control module 184 is electrically connected with the first power supply line 21, and a second terminal of the first light emitting control unit 187 is electrically connected with the first terminal of the driving transistor 181; a first terminal of a second light emitting control unit 188 of the light emitting control module 184 is electrically connected with the second terminal of the driving transistor 181, and a second terminal of the second light emitting control unit 188 is electrically connected with the first terminal of the light emitting element D1.

[0080] FIG. 17 shows a pixel driving circuit of 7T1C. For example, the first reset module 182 includes the sixth transistor T6, the second reset module 183 includes the seventh transistor T7, the threshold value grabbing module 186 includes the fifth transistor T5, the first light-emitting control unit 187 includes the second transistor T2, the second light-emitting control unit 188 includes the third transistor T3, and the data writing module 185 includes the fourth transistor T4. The driving transistor 181 can be referred to as the first transistor T1. The embodiment is taken as an example of a low-temperature polycrystalline oxide (LTPO) display panel. In the pixel driving circuit of 7T1C, the fifth transistor T5 and the sixth transistor T6 are P-type transistors, the active layers of which are formed of indium gallium zinc oxide, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the seventh transistor T7 are N-type transistors, the active layers of which are made of polysilicon material. For example, the first reset module 182 is configured to work in response to the first scan signal SCAN1 to connect the control end of the driving transistor T1 to the first reference voltage signal vref1; the storage capacitor C1 is configured to connect the first power supply signal PVDD to the control end of the driving transistor T1; the data writing module 185 is configured to work in response to the third scan signal SCAN3 to connect the first end of the driving transistor T1 to the corresponding data signal Vdata; the threshold value grabbing module 186 is configured to work in response to the second scan signal SCAN2 to connect the control end of the driving transistor to the second end; the light-emitting control module 184 is configured to work in response to the light-emitting control signal EM to connect the first end of the driving transistor T1 to the first power supply signal PVDD and connect the second end of the driving transistor T1 to the first end of the light-emitting element D1; the second end of the light-emitting element D1 is connected to the second power supply signal PVEE; and the second reset module 183 is configured to work in response to the third scan signal SCAN3 to connect the first end of the light-emitting element D1 to the second reference voltage signal vref1. It should be noted that the embodiment can be configured with the first scan signal SCAN1, the second scan signal SCAN2, the third scan signal SCAN3, and the fourth scan signal SCAN4, the effective levels of the first scan signal SCAN1 and the second scan signal SCAN2 are high, and the effective levels of the third scan signal SCAN3 and the fourth scan signal SCAN4 are low. The effective level duration of the second scan signal SCAN2 is completely the same as that of the third scan signal SCAN3; and the effective level duration of the first scan signal SCAN1 is completely the same as that of the fourth scan signal SCAN4.

[0081] The working process of the pixel driving circuit includes a reset stage, a data writing stage and a light emitting stage. In the reset stage, the sixth transistor T6 is turned on, the driving transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the seventh transistor T7 are turned off, the first reference voltage signal vref1 is written into the N1 node (the control end of the driving transistor) to initialize the control end of the driving transistor T1; in the data writing stage, the driving transistor T1, the fourth transistor T4, the fifth transistor T5 and the seventh transistor T7 are turned on, the second transistor T2, the third transistor T3 and the sixth transistor T6 are turned off, the second reference voltage signal vref2 is written into the N4 node (the first end of the light emitting element D1) to initialize the first end of the light emitting element D1; the data signal Vdata flows to the N2 node (the first end of the light emitting element D1) through the fourth transistor T4, and then flows to the N3 node (the first end of the driving transistor) through the driving transistor T1, and then flows to the N1 through the fifth transistor; in the light emitting stage, the driving transistor T1, the second transistor T2 and the third transistor T3 are turned on, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are turned off, a current path is formed from the first power supply signal PVDD to the second power supply signal PVEE, and the light emitting element D1 is lit up.

[0082] FIG. 18 is a structural schematic diagram of another pixel driving circuit provided by the embodiment of the present application. For example, the pixel driving circuit 18 can further include an adjusting signal module 189; the first end of the adjusting signal module 189 is connected with the adjusting signal line 51; the second end of the adjusting signal module 189 is connected with the first end of the driving transistor 181; the adjusting signal module 189 is configured to transmit the adjusting signal DVH to the driving transistor 181.

[0083] FIG. 18 is a pixel driving circuit of 8T1C, compared with the pixel driving circuit shown in FIG. 17, the pixel driving circuit of 8T1C increases the adjusting signal module 189, the adjusting signal module 189 includes the eighth transistor T8, the control end of the eighth transistor T8 is connected with the fourth scanning signal SCAN4, the second end of the eighth transistor T8 is connected with the first end of the driving transistor T1 and the second end of the fourth transistor T4 respectively, and the first end of the eighth transistor T8 is connected with the adjusting signal DVH, in the reset stage, the eighth transistor T8 is turned on, the adjusting signal DVH is written into N2 to improve the bias state of the driving transistor T1, in the data writing stage and the light emitting stage, the eighth transistor T8 is in the off state, and the rest of the working process is the same as the working process of the pixel driving transistor T1 in the above-mentioned FIG. 17, which will not be described again.

[0084] In the embodiment, the pixel driving circuit needs the first reference voltage bus 13, the second reference voltage bus 14, the first power bus 25, the second power bus 24, and the adjusting signal bus 52 to provide working power sources. The embodiment shows a case of more buses, and the buses are usually arranged in the third metal layer M3. When the buses are more, the first reference voltage bus 13 is arranged only in the fan-out area 15 and the first non-display area NA1, occupying the area of the upper and lower frames. The remaining buses are arranged in the second non-display area NA2 and the third non-display area NA3, occupying the space of the side frames. The embodiment effectively balances the bus arrangement of the multiple frames, so that the frame width of the display panel is smaller as a whole, realizing the user's narrow frame requirement.

[0085] FIG. 19 is a structural schematic diagram of another display panel provided by an embodiment of the present application. For example, the display area AA can further include an auxiliary wire 61; the data line 23 includes a first data line 23a and a second data line 23b; the fan-out area 15 includes a first data lead 15a and a second data lead 15b; the first data line 23a is electrically connected with the first data lead 15a; and the second data line 23b is electrically connected with the second data lead 15b through the auxiliary wire 61. As shown in FIG. 19, the display area AA can be divided into a first display area AA1 and a second display area AA2; the data line 23 includes the first data line 23a and the second data line 23b, the first display area AA1 is provided with the first data line 23a, and the second display area AA2 is provided with the second data line 23b.

[0086] For example, a virtual wire 12a can be arranged in the same layer as the auxiliary wire 61, the virtual wire 12a and the auxiliary wire 61 form a grid shape, and the display uniformity of the display panel is maintained. The virtual wire 12a can reduce the current attenuation caused by the wire resistance of different signals, thereby effectively improving the display effect of the display panel. The virtual wire 12a can be connected to any one of the following signals: the first power signal PVDD, the second power signal PVEE, the first reference voltage signal vref1, and the second reference voltage signal vref2. Similarly, in order to reduce the current attenuation caused by the wire resistance of different signals, the shielding bus can be connected to the first power signal PVDD, the second power signal PVEE, the first reference voltage signal vref1, or the second reference voltage signal vref2, thereby improving the display effect of the display panel.

[0087] The embodiment of the present application further provides a display device. FIG. 20 is a structural schematic diagram of a display device provided by an embodiment of the present application. As shown in FIG. 20, the display device provided by the embodiment of the present application includes the display panel 200 described in any embodiment of the present application. The display device can be a display device of a mobile phone as shown in FIG. 20, or a display device of a computer, a television, a smart wearable device, or other electronic equipment, which is not specially limited in the embodiment.

[0088] The display device in this embodiment comprises the technical features of the display panel provided in any embodiment of the present application, has the beneficial effects possessed by the corresponding features, which will not be described here again.

Claims

1. A display panel, comprising: The display region and a non-display region surrounding the display region; The display region comprises a plurality of first reference voltage lines, a plurality of second reference voltage lines and data lines; the data lines extend along a first direction; The non-display region comprises a first reference voltage bus and a second reference voltage bus; The first reference voltage lines are electrically connected with the first reference voltage bus; The second reference voltage lines are electrically connected with the second reference voltage bus; The first reference voltage bus comprises a first bus segment and a second bus segment; The non-display region comprises a fan-out region and a first non-display region respectively located on two sides of the display region along the first direction; at least part of the first bus segment is located in the fan-out region; at least part of the second bus segment is located in the first non-display region.

2. The display panel of claim 1, wherein, The non-display region further comprises a second non-display region and a third non-display region respectively located on two sides of the display region along a second direction; the second direction intersects with the first direction; the first non-display region is arranged adjacent to the second non-display region and the third non-display region respectively; The second reference voltage bus comprises at least a third bus segment and a fourth bus segment; At least part of the third bus segment is located in the second non-display region; at least part of the fourth bus segment is located in the third non-display region.

3. The display panel of claim 2, wherein, Adjacent non-display regions are connected through R-angle regions.

4. The display panel of claim 2, wherein, The first non-display region and the second non-display region are connected through a first R-angle region; the first non-display region and the third non-display region are connected through a second R-angle region; The second bus segment comprises a first part located in the first R-angle region and / or a second part located in the second R-angle region.

5. The display panel of claim 2, wherein, The fan-out region and the second non-display region are connected through a third R-angle region; the fan-out region and the third non-display region are connected through a fourth R-angle region; The first bus segment comprises a third part located in the third R-angle region and / or a fourth part located in the fourth R-angle region.

6. The display panel of claim 3, wherein, The display region comprises arrayed pixel driving circuits; the display region comprises a first special-shaped region; The first special-shaped region is adjacent to the R-angle region; a plurality of the pixel driving circuits in the first special-shaped region are distributed in a stepped manner; The first bus segment and the second bus segment extend along an edge of the first special-shaped region.

7. The display panel of claim 6, wherein, The third bus segment and the fourth bus segment extend along an edge of the first special-shaped region.

8. The display panel of claim 6, further comprising: A shielding bus; The shielding bus extends along an edge of the first special-shaped region; In the first special-shaped region, the shielding bus comprises a linear first bus and a stepped second bus; The first reference voltage bus comprises, in the first special-shaped region, a plurality of first steps extending along a first direction and a plurality of second steps extending along a second direction; The second bus comprises, in the first special-shaped region, a plurality of third steps extending along a first direction and a plurality of fourth steps extending along a second direction; There is an overlapping region between the second step and the fourth step.

9. The display panel of claim 2, wherein, The first reference voltage bus further comprises a fifth bus segment; The fifth bus segment is located in the second non-display region.

10. The display panel of claim 9, wherein, The first reference voltage bus further comprises a sixth bus segment; The sixth bus segment is located in the third non-display area.

11. The display panel of claim 10, wherein, In the second direction, a width of the fifth bus segment is less than a width of the third bus segment; and a width of the sixth bus segment is less than a width of the fourth bus segment.

12. The display panel of claim 10, wherein, The first bus segment, the fifth bus segment, the second bus segment, and the sixth bus segment are sequentially connected to form a ring shape.

13. The display panel of claim 10, wherein, The first reference voltage bus and the second reference voltage bus are located in different film layers. The display panel further satisfies at least one of: the fifth bus segment at least partially overlaps the third bus segment; and the sixth bus segment at least partially overlaps the fourth bus segment.

14. The display panel of claim 1, wherein, The first reference voltage bus and the second reference voltage bus are located in the same layer.

15. The display panel of claim 2, wherein, The first reference voltage line includes a first connection line extending in the first direction and a second connection line extending in the second direction; the first connection line is electrically connected to the second connection line. The second reference voltage line includes a third connection line extending in the first direction and a fourth connection line extending in the second direction; the third connection line is electrically connected to the fourth connection line. The first connection line is connected to the first bus segment and the second bus segment, respectively. The fourth connection line is connected to the third bus segment and the fourth bus segment, respectively.

16. The display panel of claim 3, the display area further comprising: A first power supply line and a second power supply line extending in the second direction; The non-display area further includes a first power supply bus and a second power supply bus; The first power supply bus is connected to the first power supply line; and the second power supply bus is connected to the second power supply line; wherein the display panel further satisfies at least one of: the first power supply bus includes a portion located in the second non-display area and the third non-display area and a portion extending to the R-angle area; and the second power supply bus includes a portion located in the second non-display area and the third non-display area and a portion extending to the R-angle area.

17. The display panel of claim 16, further comprising; Touch control wires connected with the touch control electrodes; the fan-out area includes a plurality of lead wires; the lead wires at least include: a first reference voltage lead line, a first power supply lead line, a second power supply lead line, a second reference voltage lead line, and a touch lead line; The first reference voltage lead line is electrically connected to the first reference voltage bus; the second reference voltage lead line is electrically connected to the second reference voltage bus; the touch lead line is electrically connected to the touch trace; and the first power supply lead line is connected to the first power supply bus. The second power supply lead line is connected to the second power supply bus. In the second direction, the second reference voltage lead line is located between the first reference voltage lead line and the touch lead line.

18. The display panel of claim 16, the non-display area further comprising: A binding area; The binding area is located on a side of the fan-out area away from the display area; The binding area includes a plurality of pads; the plurality of pads are respectively connected to corresponding lead lines; In the second direction, a pad connected to the second reference voltage lead line is located between a pad connected to the first power supply lead line and a pad connected to the second power supply lead line. The second reference voltage lead line connects a corresponding pad by a jumper across the first reference voltage lead line.

19. The display panel of claim 2, wherein the display region further comprises an adjusting signal line; the non-display region further comprises an adjusting signal bus; the adjusting signal bus is electrically connected with the adjusting signal line; The adjustment signal bus includes a seventh bus segment and an eighth bus segment. the seventh bus segment is located in the second non-display region; the eighth bus segment is located in the third non-display region.

20. The display panel of claim 19, wherein, the adjusting signal line comprises a fifth connection line extending along the first direction and a sixth connection line extending along the second direction; the fifth connection line is electrically connected with the sixth connection line; the sixth connection line is electrically connected with the seventh bus segment and the eighth bus segment, respectively.

21. The display panel of claim 19, wherein, the first reference voltage bus, the second reference voltage bus and the adjusting signal bus are arranged in the same layer.

22. The display panel of claim 17, wherein the display region further comprises an adjusting signal line; the non-display region further comprises an adjusting signal bus; the adjusting signal bus is electrically connected with the adjusting signal line; the lead wire further comprises an adjusting signal lead wire; the adjusting signal lead wire is electrically connected with the adjusting signal bus; in the second direction, the second reference voltage lead wire is located between the adjusting signal lead wire and the touch lead wire; the adjusting signal lead wire is located between the first reference voltage lead wire and the second reference voltage lead wire.

23. The display panel of claim 22, the non-display area further comprising: a binding region; the binding region is located on the side of the fan-out area away from the display region; the binding region comprises a plurality of pads; the plurality of pads are connected with corresponding lead wires, respectively; in the second direction, the pad connected with the second reference voltage lead wire is located between the pad connected with the first power supply lead wire and the pad connected with the second power supply lead wire; the second reference voltage lead wire connects corresponding pads by jumper wires across the first reference voltage lead wire and the adjusting signal lead wire.

24. The display panel of claim 1, wherein, the display region comprises an array of pixel driving circuits; the pixel driving circuit comprises a driving transistor, a first reset module and a second reset module; a first end of the first reset module is electrically connected with a control end of the driving transistor; a second end of the first reset module is electrically connected with the first reference voltage line; a first end of the driving transistor is electrically connected with a first power supply line; a second end of the driving transistor is electrically connected with a first end of a light emitting element; a first end of the second reset module is electrically connected with the first end of the light emitting element; a second end of the second reset module is electrically connected with the second reference voltage line; a second end of the light emitting element is electrically connected with a second power supply line.

25. The display panel of claim 24, the pixel drive circuit further comprising: a storage capacitor, a light emitting control module, a data writing module and a threshold value grabbing module; The first plate of the storage capacitor is electrically connected with the first power line, and the second plate of the storage capacitor is electrically connected with the control end of the driving transistor; the first end of the data writing module is electrically connected with the first end of the driving transistor, and the second end of the data writing module is electrically connected with the corresponding data line; the first end of the threshold value grabbing module is electrically connected with the control end of the driving transistor, and the second end of the threshold value grabbing module is electrically connected with the second end of the driving transistor; the first end of the first light emitting control unit of the light emitting control module is electrically connected with the first power line, and the second end of the first light emitting control unit is electrically connected with the first end of the driving transistor; the first end of the second light emitting control unit of the light emitting control module is electrically connected with the second end of the driving transistor, and the second end of the second light emitting control unit is electrically connected with the first end of the light emitting element.

26. The display panel of claim 24, further comprising an adjusting signal module. The first end of the adjusting signal module is connected with an adjusting signal line; the second end of the adjusting signal module is connected with the first end of the driving transistor; and the adjusting signal module is configured to transmit an adjusting signal to the driving transistor.

27. The display panel of claim 1, wherein the display area further comprises an auxiliary trace; the data line comprises a first data line and a second data line; and the fan-out area comprises a first data lead and a second data lead. The first data line is electrically connected with the first data lead; and the second data line is electrically connected with the second data lead through the auxiliary trace.

28. A display device comprising the display panel of any one of claims 1-27.

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