Display panel and display apparatus

Abstract

A display panel comprises data signal lines and data connection wires. The data connection wires comprise first wire sub-portions, the first wire sub-portions and the data signal lines both extending in a first direction, and control ends of a plurality of distribution switches connected to the correspondingly arranged data signal lines and first wire sub-portions being connected to the same switch control signal. The distance between the correspondingly arranged data signal lines and first wire sub-portions is less than the distance between the first data signal lines and any other first wire sub-portion, and is less than the distance between the first data signal lines and any other data signal line.

Description

Display panel and display device

[0001] The present application claims priority to the Chinese patent application No. 202411253582.4, filed on September 6, 2024, to the Chinese Patent Office, the whole content of the above application being incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the technical field of display, for example, to a display panel and a display device. BACKGROUND

[0003] With the continuous development of display technology, display panels have been widely used in people's production and life. However, there are still some technical problems in the display panel in the related art that need to be solved. For example, the signals on some signal lines will exist coupling interference, thereby affecting the display effect of the display panel.

[0004] SUMMARY

[0005] In a first aspect, an embodiment of the present application provides a display panel, comprising a signal line;

[0006] The signal line comprises a data signal line, and a plurality of data signal lines extend along a first direction and are arranged along a second direction; the first direction and the second direction intersect;

[0007] The display panel further comprises a display area and a non-display area surrounding at least part of the display area; the display area comprises a first display area and a second display area, and the second display area is located on at least one side of the first display area along the second direction; the non-display area comprises a plurality of distribution units arranged in a distribution unit arrangement area on one side of the display area along the first direction, and the distribution unit arrangement area is provided with a plurality of distribution units and at least two switch control lines; the distribution unit comprises at least two distribution switches, and the distribution switch comprises an input end, an output end and a control end; in the same distribution unit, the input ends of the at least two distribution switches are connected, the output ends of the at least two distribution switches are respectively electrically connected with different data signal lines, and the control ends of the at least two distribution switches are respectively electrically connected with different switch control lines;

[0008] The first display area and the second display area each comprise a plurality of data signal lines, and the signal line further comprises a plurality of data connection traces, and the data signal lines located in the second display area are electrically connected with the output ends of the distribution switches through the data connection traces;

[0009] The data connection trace comprises a first trace part, and the first trace part extends along the first direction;

[0010] The plurality of data signal lines comprises a first data signal line, the first data signal line is provided with a first trace part corresponding to the first data signal line; the control end of the multi-way distribution switch connected with the first data signal line and the control end of the multi-way distribution switch connected with the first trace part corresponding to the first data signal line are connected to the same switch control signal; the distance between the first data signal line and the first trace part corresponding to the first data signal line in the second direction is smaller than the distance between the first data signal line and any other first trace part in the second direction, and is smaller than the distance between the first data signal line and any other data signal line in the second direction.

[0011] In a second aspect, the embodiments of the present application provide a display panel, comprising a signal line;

[0012] The signal line comprises a data signal line, a plurality of the data signal lines extend along a first direction and are arranged along a second direction; the first direction and the second direction intersect;

[0013] The display panel further comprises a display area and a non-display area surrounding the display area at least partially; the display area comprises a first display area and a second display area, the second display area is located at least one side of the first display area along the second direction; the non-display area comprises a multi-way distribution unit setting area located at one side of the display area along the first direction, the multi-way distribution unit setting area is provided with a plurality of multi-way distribution units and at least two switch control lines; the multi-way distribution unit comprises at least two multi-way distribution switches, the multi-way distribution switch comprises an input end, an output end and a control end; in the same multi-way distribution unit, the input ends of at least two multi-way distribution switches are connected, the output ends of at least two multi-way distribution switches are respectively electrically connected with different data signal lines, and the control ends of at least two multi-way distribution switches are respectively electrically connected with different switch control lines;

[0014] The first display area and the second display area both comprise a plurality of data signal lines, the signal line further comprises a plurality of data connection traces, the data signal lines located in the second display area are electrically connected with the output ends of the multi-way distribution switches through the data connection traces;

[0015] The data connection trace comprises a first trace part, the first trace part extends along the first direction;

[0016] At least two first trace parts connected with the output end of the same multi-way distribution unit comprise a first sub-trace part and a second sub-trace part, the display panel further comprises a first virtual axis, the part of the first sub-trace part and the second sub-trace part overlapping in the second direction is arranged symmetrically about the first virtual axis.

[0017] In a third aspect, the embodiments of the present application provide a display device, comprising the display panel of the first aspect and the second aspect. BRIEF DESCRIPTION OF DRAWINGS

[0018] FIG. 1 is a structural schematic diagram of a display panel according to an embodiment of the present application;

[0019] FIG. 2 is a structural schematic diagram of another display panel according to an embodiment of the present application;

[0020] FIG. 3 is a connection schematic diagram of a demultiplexer and a data signal line and a data connection trace according to an embodiment of the present application;

[0021] FIG. 4 is a structural schematic diagram of a display panel in a display area and a partial non-display area according to an embodiment of the present application;

[0022] FIG. 5 is a structural schematic diagram of a display panel in a demultiplexer setting area according to an embodiment of the present application;

[0023] FIG. 6 is a structural schematic diagram of a first semiconductor layer in the display panel of FIG. 4 in the display area and the partial non-display area;

[0024] FIG. 7 is a structural schematic diagram of the first semiconductor layer in the display panel of FIG. 5 in the demultiplexer setting area;

[0025] FIG. 8 is a structural schematic diagram of a first metal layer in the display panel of FIG. 4 in the display area and the partial non-display area;

[0026] FIG. 9 is a structural schematic diagram of the first metal layer in the display panel of FIG. 5 in the demultiplexer setting area;

[0027] FIG. 10 is a structural schematic diagram of a second metal layer in the display panel of FIG. 4 in the display area and the partial non-display area;

[0028] FIG. 11 is a structural schematic diagram of a second semiconductor layer in the display panel of FIG. 4 in the display area;

[0029] FIG. 12 is a structural schematic diagram of a third metal layer in the display panel of FIG. 4 in the display area;

[0030] FIG. 13 is a structural schematic diagram of a fourth metal layer in the display panel of FIG. 4 in the display area and the partial non-display area;

[0031] FIG. 14 is a structural schematic diagram of the fourth metal layer in the display panel of FIG. 5 in the demultiplexer setting area;

[0032] FIG. 15 is a structural schematic diagram of a fifth metal layer in the display panel of FIG. 4 in the display area and the partial non-display area;

[0033] FIG. 16 is a structural schematic diagram of a sixth metal layer in the display panel provided in FIG. 4 in the display area and the partial non-display area;

[0034] FIG. 17 is a structural schematic diagram of an anode layer in the display panel provided in FIG. 4 in the display area;

[0035] FIG. 18 is a schematic diagram of a stack of a partial film layer in the display panel provided in FIG. 4;

[0036] FIG. 19 is a schematic diagram of a stack of another partial film layer in the display panel provided in FIG. 4;

[0037] FIG. 20 is a structural schematic diagram of another display panel provided in an embodiment of the present application in the display area and the partial non-display area;

[0038] FIG. 21 is a structural schematic diagram of another display panel provided in an embodiment of the present application in the multi-path distribution unit setting area;

[0039] FIG. 22 is a structural schematic diagram of a first semiconductor layer in the display panel provided in FIG. 20 in the display area and the partial non-display area;

[0040] FIG. 23 is a structural schematic diagram of a first semiconductor layer in the display panel provided in FIG. 21 in the multi-path distribution unit setting area;

[0041] FIG. 24 is a structural schematic diagram of a first metal layer in the display panel provided in FIG. 20 in the display area and the partial non-display area;

[0042] FIG. 25 is a structural schematic diagram of a first metal layer in the display panel provided in FIG. 21 in the multi-path distribution unit setting area;

[0043] FIG. 26 is a structural schematic diagram of a second metal layer in the display panel provided in FIG. 20 in the display area and the partial non-display area;

[0044] FIG. 27 is a structural schematic diagram of a second metal layer in the display panel provided in FIG. 21 in the multi-path distribution unit setting area;

[0045] FIG. 28 is a structural schematic diagram of a second semiconductor layer in the display panel provided in FIG. 20 in the display area and the partial non-display area;

[0046] FIG. 29 is a structural schematic diagram of a third metal layer in the display panel provided in FIG. 20 in the display area and the partial non-display area;

[0047] FIG. 30 is a structural schematic diagram of a fourth metal layer in the display panel provided in FIG. 20 in the display area and the partial non-display area;

[0048] FIG. 31 is a structural schematic diagram of a fourth metal layer in the display panel provided in FIG. 21 in the multi-path distribution unit setting area;

[0049] FIG. 32 is a structural schematic diagram of the fifth metal layer in the display panel provided in FIG. 20 in the display area and part of the non-display area;

[0050] FIG. 33 is a structural schematic diagram of the fifth metal layer in the display panel provided in FIG. 21 in the multi-path distribution unit setting area;

[0051] FIG. 34 is a structural schematic diagram of the sixth metal layer in the display panel provided in FIG. 20 in the display area and part of the non-display area;

[0052] FIG. 35 is a structural schematic diagram of the sixth metal layer in the display panel provided in FIG. 21 in the multi-path distribution unit setting area;

[0053] FIG. 36 is a structural schematic diagram of the anode layer in the display panel provided in FIG. 20 in the display area;

[0054] FIG. 37 is a schematic diagram of the stack of a part of the film layers in the display panel provided in FIG. 20;

[0055] FIG. 38 is a schematic diagram of the stack of a part of the film layers in the display panel provided in FIG. 21;

[0056] FIG. 39 is a schematic diagram of the stack of another part of the film layers in the display panel provided in FIG. 20;

[0057] FIG. 40 is a schematic diagram of the stack of another part of the film layers in the display panel provided in FIG. 21;

[0058] FIG. 41 is a schematic diagram of the stack of still another part of the film layers in the display panel provided in FIG. 20;

[0059] FIG. 42 is a schematic diagram of the electrical connection of a pixel circuit provided in an embodiment of the present application;

[0060] FIG. 43 is a timing schematic diagram of the pixel circuit described in FIG. 42;

[0061] FIG. 44 is a schematic diagram of the electrical connection of another pixel circuit provided in an embodiment of the present application;

[0062] FIG. 45 is a timing schematic diagram of the pixel circuit described in FIG. 44;

[0063] FIG. 46 is a structural schematic diagram of another display panel provided in an embodiment of the present application;

[0064] FIG. 47 is a structural schematic diagram of the first semiconductor layer in the display panel provided in FIG. 46;

[0065] FIG. 48 is a structural schematic diagram of the first metal layer in the display panel provided in FIG. 46;

[0066] FIG. 49 is a structural schematic diagram of the second metal layer in the display panel provided in FIG. 46;

[0067] FIG. 50 is a structural schematic diagram of a second semiconductor layer in the display panel provided in FIG. 46;

[0068] FIG. 51 is a structural schematic diagram of a third metal layer in the display panel provided in FIG. 46;

[0069] FIG. 52 is a structural schematic diagram of a fourth metal layer in the display panel provided in FIG. 46;

[0070] FIG. 53 is a structural schematic diagram of a fifth metal layer in the display panel provided in FIG. 46;

[0071] FIG. 54 is a structural schematic diagram of a sixth metal layer in the display panel provided in FIG. 46;

[0072] FIG. 55 is a structural schematic diagram of an anode layer in the display panel provided in FIG. 46;

[0073] FIG. 56 is a schematic diagram of a stack of a partial film layer in the display panel provided in FIG. 46;

[0074] FIG. 57 is a schematic diagram of a stack of another partial film layer in the display panel provided in FIG. 46;

[0075] FIG. 58 is a structural schematic diagram of yet another display panel provided in embodiments of the present application;

[0076] FIG. 59 is a structural schematic diagram of a first semiconductor layer in the display panel provided in FIG. 58;

[0077] FIG. 60 is a structural schematic diagram of a first metal layer in the display panel provided in FIG. 58;

[0078] FIG. 61 is a structural schematic diagram of a second metal layer in the display panel provided in FIG. 58;

[0079] FIG. 62 is a structural schematic diagram of a second semiconductor layer in the display panel provided in FIG. 58;

[0080] FIG. 63 is a structural schematic diagram of a third metal layer in the display panel provided in FIG. 58;

[0081] FIG. 64 is a structural schematic diagram of a fourth metal layer in the display panel provided in FIG. 58;

[0082] FIG. 65 is a structural schematic diagram of a fifth metal layer in the display panel provided in FIG. 58;

[0083] FIG. 66 is a structural schematic diagram of an anode layer in the display panel provided in FIG. 58;

[0084] FIG. 67 is a schematic diagram of a stack of a partial film layer in the display panel provided in FIG. 58;

[0085] FIG. 68 is a schematic diagram of a stack of another partial film layer in the display panel provided in FIG. 58;

[0086] FIG. 69 is a structural schematic diagram of still another display panel according to an embodiment of the present application;

[0087] FIG. 70 is a structural schematic diagram of a first semiconductor layer in the display panel of FIG. 69;

[0088] FIG. 71 is a structural schematic diagram of a first metal layer in the display panel of FIG. 69;

[0089] FIG. 72 is a structural schematic diagram of a second metal layer in the display panel of FIG. 69;

[0090] FIG. 73 is a structural schematic diagram of a second semiconductor layer in the display panel of FIG. 69;

[0091] FIG. 74 is a structural schematic diagram of a third metal layer in the display panel of FIG. 69;

[0092] FIG. 75 is a structural schematic diagram of a fourth metal layer in the display panel of FIG. 69;

[0093] FIG. 76 is a structural schematic diagram of a fifth metal layer in the display panel of FIG. 69;

[0094] FIG. 77 is a structural schematic diagram of an anode layer in the display panel of FIG. 69;

[0095] FIG. 78 is a schematic diagram of a stack of a partial film layer in the display panel of FIG. 69;

[0096] FIG. 79 is a schematic diagram of a stack of another partial film layer in the display panel of FIG. 69;

[0097] FIG. 80 is a schematic diagram of a film layer structure of a display panel according to an embodiment of the present application;

[0098] FIG. 81 is a schematic diagram of a film layer structure of another display panel according to an embodiment of the present application;

[0099] FIG. 82 is a structural schematic diagram of a display device according to an embodiment of the present application. DETAILED DESCRIPTION

[0100] The terms "first", "second", and the like, as used in the specification and in the claims of the application, and in the above Description of Embodiments, unless otherwise specified, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the use of the terms so construed herein is merely for convenience and illustrative purposes and not a limitation on the scope of the application. Exemplary embodiments of the application described herein can be implemented in a chronological order, in parallel, or in a reverse order unless otherwise specified. Further, the terms "comprise", "comprising", "include", "including", and the like, as used herein, are specifically intended to be construed as in a non-exhaustive sense. That is, these terms are used synonymously with the term "comprising" and are intended not to exclude other elements or steps.

[0101] The embodiments of the application provide a display panel and a display device. By setting a control end of a multi-way distribution switch connected with a corresponding set of data signal lines and first wire parts, a same switch control signal is accessed, data signals are simultaneously transmitted in the connection between the corresponding set of data signal lines and the first wire parts, mutual interference between the corresponding set of data signal lines and the first wire parts is reduced, and display stability is ensured.

[0102] FIG. 1 is a structural schematic diagram of a display panel provided in an embodiment of the present application, FIG. 2 is a structural schematic diagram of another display panel provided in an embodiment of the present application, and FIG. 3 is a connection schematic diagram of a demultiplexing unit and a data signal line and a data connection trace. In combination with the display panel shown in FIGS. 1-3, the display panel provided in an embodiment of the present application includes a signal line, the signal line includes a data signal line DATA, a plurality of data signal lines DATA extend along a first direction (e.g., the X direction shown in the figure) and are arranged along a second direction (e.g., the Y direction shown in the figure); the first direction and the second direction intersect; the display panel further includes a display area AA and a non-display area NAA surrounding at least part of the display area; the display area AA includes a first display area AA1 and a second display area AA2, the second display area AA2 is located at least one side of the first display area AA1 along the second direction; the non-display area NAA includes a demultiplexing unit setting area NAA1 located at one side of the display area AA along the first direction, the demultiplexing unit setting area NAA1 is provided with a plurality of demultiplexing units DEMUX and at least two switch control lines SW; the demultiplexing unit DEMUX includes at least two demultiplexing switches K, the demultiplexing switch K includes an input end S, an output end D and a control end G; in the same demultiplexing unit DEMUX, the input ends S of the at least two demultiplexing switches K are connected, the output ends D of the at least two demultiplexing switches K are respectively electrically connected with different data signal lines DATA, and the control ends G of the at least two demultiplexing switches are respectively electrically connected with different switch control lines SW; the first display area AA1 and the second display area AA2 both include a plurality of data signal lines DATA, the signal line further includes a plurality of data connection traces FIAA, the data signal lines DATA located in the second display area AA2 are electrically connected with the output ends D of the demultiplexing switches K through the data connection traces FIAA; the data connection trace FIAA includes a first trace part FIAA1, the first trace part FIAA1 extends along the first direction; the plurality of data signal lines DATA include a first data signal line DATA1, the first data signal line DATA1 is provided with a corresponding first trace part FIAA1; in the corresponding first data signal line DATA1 and the first trace part FIAA1, the control end G of the demultiplexing switch K connected with the first data signal line DATA1 and the control end G of the demultiplexing switch K connected with the first trace part FIAA1 are connected with the same switch control signal; the distance between the first data signal line DATA1 and the corresponding first trace part FIAA1 in the second direction is smaller than the distance between the first data signal line DATA1 and any other first trace part FIAA1 in the second direction, and the distance between the first data signal line DATA1 and the corresponding first trace part FIAA1 in the second direction is smaller than the distance between the first data signal line DATA1 and any other data signal line DATA in the second direction.

[0103] Referring to FIG. 1 and FIG. 2, the display panel includes signal lines, which include a data signal line DATA and other signal lines required to ensure normal operation of the display panel, such as a power signal line, a scanning signal line, and a touch signal line, and the like. Optionally, referring to FIG. 1, the display panel can further include a pixel circuit 20 and a light emitting element 30, the signal lines are electrically connected to the pixel circuit 20 and are configured to provide a voltage signal and / or a current signal to the pixel circuit 20; the pixel circuit 20 is electrically connected to the light emitting element 30 and is configured to drive the light emitting element 30 to emit light under the action of the voltage signal and / or the current signal. Optionally, the pixel circuit 20 can be configured in various ways, and the pixel circuit can be "2T1C", "7T1C", or "8T1C", wherein "T" represents a transistor, and "C" represents a storage capacitor. The specific configuration of the pixel circuit is not limited in the embodiments of the present application, for example, "3T1C" and "6T1C" pixel circuits are also within the scope of the technical solutions protected by the embodiments of the present application. The light emitting element 30 can be at least one of a light emitting diode, an organic light emitting diode, and a micro light emitting diode, and the specific form of the light emitting element 30 is also not limited in the embodiments of the present application.

[0104] Continuing to refer to FIG. 1 and FIG. 2, the display panel provided by the embodiments of the present application includes a display area AA and a non-display area NAA, the data signal line DATA, the pixel circuit 20, and the light emitting element 30 described above can be disposed in the display area AA, and the non-display area NAA includes a plurality of demultiplexing unit setting areas NAA1. The plurality of demultiplexing unit setting areas NAA1 are provided with a plurality of demultiplexing units DEMUX and at least two switch control lines SW; the demultiplexing unit DEMUX includes at least two demultiplexing switches K; the input ends S of the at least two demultiplexing switches K in the same demultiplexing unit DEMUX are connected, the output ends D of the at least two demultiplexing switches K are respectively electrically connected to different data signal lines DATA, and the control ends G of the at least two demultiplexing switches are respectively electrically connected to different switch control lines SW. The demultiplexing unit K is used to transmit the signal input from the input end S to the data signal line DATA through the output end D under the action of the control signal in the switch control line SW, and the enable phases of the control signals in the different switch control signal lines SW are staggered to ensure that the at least two demultiplexing switches K of the same demultiplexing unit DEMUX are turned on at different times. That is, the same demultiplexing unit DEMUX can time-divisionally distribute the input signal transmitted by the same signal output terminal to any one of the plurality of data signal lines DATA, so as to reduce the number of signal output terminals under the premise of realizing normal output of the data signal, and reduce the difficulty of layout of the signal output terminals in the display panel.

[0105] Optionally, the display area AA further comprises a first display area AA1 and a second display area AA2. The second display area AA2 is located on both sides of the first display area AA1 along the second direction Y, as exemplarily shown in FIG. 2, but is not limited thereto. In this arrangement, along the orientation shown in FIG. 2, the second display area AA2 is located between the first display area AA1 and the non-display areas NAA on the left and right sides, along the second direction Y, the first display area AA1 is closer to the center of the display panel, and the second display area AA2 is closer to the edge of the display panel. The data signal line DATA located in the second display area is electrically connected to the output end D of the demultiplexing switch K through the data connection trace FIAA. At least part of the data connection trace FIAA is located in the display area AA, and at least part of the data connection trace FIAA is located in the first display area AA1. In this way, the demultiplexing unit DEMUX connected to the data signal line DATA and the data connection trace FIAA can be more concentrated below the first display area AA1. In this way, the connection line when the data signal line DATA and the data connection trace FIAA are connected to the demultiplexing switch K occupies less space in the first direction, which is beneficial to reducing the occupied space of the non-display area, improving the display area ratio of the display panel, and improving the screen-to-body ratio of the display panel.

[0106] Exemplarily, FIG. 3 takes the example of the demultiplexing unit DEMUX including two demultiplexing switches K1 and K2. Correspondingly, the display panel includes two switch control lines SW1 and SW2, the control end of the demultiplexing switch K1 is electrically connected with the switch control line SW1, the control end of the demultiplexing switch K2 is electrically connected with the switch control line SW2, and the switch control lines SW1 and SW2 time-divisionally transmit the enable signals of the demultiplexing switches. When the enable signal is transmitted in the switch control line SW1, the demultiplexing switch K1 is turned on, and the demultiplexing switch K1 is used to transmit the data signal inputted by the input end to the data signal line DATA directly or to the data signal line connected with it through the data connection wire FIAA; at this time, the non-enable signal is transmitted in the switch control line SW2, and the data signal line DATA or the data connection wire FIAA connected with the demultiplexing switch K2 is in the state of potential floating. Similarly, when the enable signal is transmitted in the switch control line SW2, the demultiplexing switch K2 is turned on, and the demultiplexing switch K2 is used to transmit the data signal inputted by the input end to the data signal line DATA directly or to the data signal line connected with it through the data connection wire FIAA; at this time, the non-enable signal is transmitted in the switch control line SW1, and the data signal line DATA or the data connection wire FIAA connected with the demultiplexing switch K1 is in the state of potential floating. As shown in FIGS. 2 and 3, since the data signal line DATA and the first wire part FIAA1 have a small distance in the second direction, when the data signal line DATA or the first wire part FIAA1 is in the state of potential floating, it is easy to be coupled with the first wire part FIAA1 or the data signal line DATA adjacent to it and then to pull down or pull up the signal on it, resulting in display abnormality. Based on this, the data signal line DATA in the embodiment of the application includes the first data signal line DATA1, which can be understood as the data signal line corresponding to the first wire part FIAA1 arranged in correspondence therewith. The corresponding arrangement here can be understood as that the distance between the first data signal line DATA1 and the first wire part FIAA1 arranged in correspondence therewith in the second direction is smaller than the distance between the first data signal line DATA1 and any other first wire part FIAA1 in the second direction, and the distance between the first data signal line DATA1 and the first wire part FIAA1 arranged in correspondence therewith in the second direction is smaller than the distance between the first data signal line DATA1 and any other data signal line DATA in the second direction, that is, the first data signal line DATA1 and the first wire part FIAA1 arranged in correspondence therewith are the closest transmission data signal wires.Or it can also be understood that the data signal is transmitted, and the distance between the first data signal line DATA1 and the nearest first trace part FIAA1 is the reference distance, the data signal line DATA and the first trace part FIAA1 meeting the reference distance are the corresponding first data signal line DATA1 and the first trace part FIAA1, and the data signal line DATA and the first trace part FIAA1 greater than the reference distance do not meet the corresponding setting defined in the embodiment of the application. The control ends of the two multiplexing switches K connected with the corresponding first data signal line DATA and the first trace part FIAA1 are connected with the same switch control signal, that is, the two multiplexing switches K connected with the corresponding first data signal line DATA and the first trace part FIAA1 are turned on or turned off at the same time, so that the corresponding first data signal line DATA1 and the first trace part FIAA1 can write data signals at the same time, and there will be no case that one of them is floating and the other is coupled with other signals, which ensures the high accuracy of the data signal in the corresponding first data signal line DATA1 and the first trace part FIAA1 and ensures good display effect.

[0107] For example, as shown in FIG. 3, the multiplexing switch connected with the switch control signal line SW1 is recorded as K1, and the multiplexing switch connected with the switch control signal line SW2 is recorded as K2. The control ends of the multiplexing switch K2 in the first group of multiplexing units and the multiplexing switch K2 in the second group of multiplexing units are both electrically connected with the switch control signal line SW2. The first data signal line and the first trace part connected with the two multiplexing switches K2 can be a group of corresponding first data signal lines DATA1 and first trace parts FIAA1. The two multiplexing switches K2 are turned on at the same time, the first data signal line DATA1 and the first trace part FIAA1 connected therewith write data signals at the same time, and the coupling interference of the data signals transmitted in the first data signal line DATA1 and the first trace part FIAA1 is small. For another example, the control ends of the multiplexing switch K1 in the second group of multiplexing units and the multiplexing switch K1 in the third group of multiplexing units are both electrically connected with the switch control signal line SW1. The first data signal line and the first trace part connected with the two multiplexing switches K1 can be a group of corresponding first data signal lines DATA1 and first trace parts FIAA1. The two multiplexing switches K1 are turned on at the same time, the first data signal line DATA1 and the first trace part FIAA1 connected therewith write data signals at the same time, and the coupling interference of the data signals transmitted in the first data signal line DATA1 and the first trace part FIAA1 is small.

[0108] In summary, the display panel provided by the embodiment of the present application is characterized in that the data signal lines in the first display area are directly electrically connected with the output ends of the multi-way distribution switch, the data signal lines in the second display area are electrically connected with the output ends of the multi-way distribution switch through the data connection traces, and at least part of the data connection traces is located in the display area. In this way, the data signal lines in the second display area can be prevented from being directly electrically connected with the output ends of the multi-way distribution switch, and the area of the non-display area can be prevented from being increased due to the direct electrical connection between the data signal lines in the second display area and the output ends of the multi-way distribution switch, thereby improving the screen-to-body ratio of the display panel. Optionally, the data connection traces include first trace parts, the first trace parts and the data signal lines both extend along the first direction, and there are first data signal lines corresponding to the first trace parts. The distance between the first data signal line and the first trace part corresponding to the first data signal line is smaller than the distance between the first data signal line and any other first trace part, and smaller than the distance between the first data signal line and any other data signal line. The control ends of the multi-way distribution switches connected with the corresponding data signal lines and the first trace parts are connected with the same switch control signal, so that the corresponding data signal lines and the first trace parts are simultaneously written with data signals, and are not coupled with other signals due to the floating potential of a certain signal line, thereby ensuring high data signal accuracy. Optionally, the first data signal lines and the first trace parts corresponding to the first data signal lines are connected with the control ends of two multi-way distribution switches, and the control ends of the two multi-way distribution switches are connected with the same switch control signal. That is, the first data signal lines and the first trace parts corresponding to the first data signal lines simultaneously input data signals, so as to avoid that a signal line with floating potential is coupled and disturbed when the two signal lines do not simultaneously input data signals. In this way, the data signal accuracy of the first data signal lines and the first trace parts corresponding to the first data signal lines can be ensured to be high, and the display effect of the display panel can be ensured to be good.

[0109] Optionally, continuing to refer to FIG. 2, in the display panel provided by the embodiment of the present application, the data connection traces can further include second trace parts FIAA2, which are respectively electrically connected with the first trace parts FIAA1 and the data signal lines DATA in the second display area AA2, and are used to transmit data signals from the first trace parts FIAA1 to the data signal lines DATA in the second display area AA2. Optionally, the second trace parts FIAA2 and the first trace parts FIAA1 can be arranged on the same layer or different layers, and the embodiment of the present application does not limit this.

[0110] Optionally, the signal line can further include a virtual data connection trace L0, which is insulated from the data connection trace FIAA. The virtual data connection trace L0 can balance the wiring density of the film layer where the data connection trace FIAA is located at different positions of the display area, ensure that the wiring density of different areas of the display area is the same or similar, and ensure that the flatness and optical properties of different areas of the display area are good. Specifically, the virtual data connection trace L0 can include a first virtual trace portion L01 and a second virtual trace portion L02. The first virtual trace portion L01 extends along a first direction, and the second virtual trace portion L02 extends along a second direction. The first virtual trace portion L01 is in the same layer and insulated from the first trace portion FIAA1, and the second virtual trace portion L02 is in the same layer and insulated from the second trace portion FIAA2. The wiring density in the first direction is balanced by the first virtual trace portion L01, and the wiring density in the second direction is balanced by the second virtual trace portion L02, so as to ensure that the film layer where the data connection trace FIAA is located has balanced wiring density in different areas of the display area.

[0111] Optionally, the virtual data connection trace L0 can be electrically connected to the fixed potential signal line. On the one hand, it can reduce the resistance of the fixed potential signal line, and solve the problem of precision decline caused by transmission loss in the transmission process of the low fixed potential signal. On the other hand, the electrical connection of the virtual data connection trace L0 and the fixed potential signal line can also avoid the influence of other signals on the actual due to the floating coupling of the virtual data connection trace L0, and ensure the display effect of the display panel.

[0112] On the basis of the above-mentioned embodiments, FIG. 4 is a structural schematic diagram of a display panel in a display area and a partial non-display area according to an embodiment of the present application, FIG. 5 is a structural schematic diagram of a display panel in a multi-way distribution unit setting area according to an embodiment of the present application, FIG. 6 is a structural schematic diagram of a first semiconductor layer in the display area and the partial non-display area of the display panel according to FIG. 4, FIG. 7 is a structural schematic diagram of the first semiconductor layer in the multi-way distribution unit setting area of the display panel according to FIG. 5, FIG. 8 is a structural schematic diagram of a first metal layer in the display area and the partial non-display area of the display panel according to FIG. 4, FIG. 9 is a structural schematic diagram of the first metal layer in the multi-way distribution unit setting area of the display panel according to FIG. 5, FIG. 10 is a structural schematic diagram of a second metal layer in the display area and the partial non-display area of the display panel according to FIG. 4, FIG. 11 is a structural schematic diagram of a second semiconductor layer in the display area of the display panel according to FIG. 4, FIG. 12 is a structural schematic diagram of a third metal layer in the display area of the display panel according to FIG. 4, FIG. 13 is a structural schematic diagram of a fourth metal layer in the display area and the partial non-display area of the display panel according to FIG. 4, FIG. 14 is a structural schematic diagram of the fourth metal layer in the multi-way distribution unit setting area of the display panel according to FIG. 5, FIG. 15 is a structural schematic diagram of a fifth metal layer in the display area and the partial non-display area of the display panel according to FIG. 4, FIG. 16 is a structural schematic diagram of a sixth metal layer in the display area and the partial non-display area of the display panel according to FIG. 4, FIG. 17 is a structural schematic diagram of an anode layer in the display area of the display panel according to FIG. 4, FIG. 18 is a schematic diagram of a partial film layer stack of the display panel according to FIG. 4, FIG. 19 is a schematic diagram of another partial film layer stack of the display panel according to FIG. 4, in combination with the diagrams shown in FIGS. 4-19, in the embodiments of the present application, the at least two first wiring branches FIAA1 connected to the output end of the same multi-way distribution unit DEMUX include a first sub-wiring branch FIAA11 and a second sub-wiring branch FIAA12; the display panel further includes a first virtual axis X1, the first virtual axis X1 extending along a first direction; and the portion of the first sub-wiring branch FIAA11 and the second sub-wiring branch FIAA12 overlapping in a second direction is symmetrical about the first virtual axis X1.

[0113] For example, referring to FIGS. 4-41, the signal lines can further include a power signal line PVDD, the first sub-wiring section FIAA11 and the second sub-wiring section FIAA12 connected to the same demultiplexer DEMUX are located on two sides of the power signal line PVDD, and the overlapping part of the first sub-wiring section FIAA11 and the second sub-wiring section FIAA12 in the second direction is symmetrical about the first virtual axis X1, that is, the first sub-wiring section FIAA11 and the second sub-wiring section FIAA1 connected to the same demultiplexer DEMUX are an axisymmetric structure, and the axis of symmetry can be the first virtual axis X1 passing through the center of the power signal line PVDD. The first virtual axis X1 is also the boundary line of the adjacent two pixel circuit classes. The first sub-wiring section FIAA11 and the second sub-wiring section FIAA1 connected to the same demultiplexer DEMUX are an axisymmetric structure, and the boundary line of the adjacent two pixel circuit classes is the axis of symmetry. On the one hand, the two first sub-wiring sections FIAA11 connected to the same demultiplexer DEMUX are neatly arranged, and on the other hand, it is beneficial to make the color shift of the display image have better symmetry, so that the four-orientation color shift can be changed, that is, no matter from which direction the display image is viewed, the consistency and accuracy of the color will be improved, and then the display image can be viewed from a wider angle range without feeling obvious color change, enhancing the user experience.

[0114] Optionally, FIG. 20 is a structural schematic of another display panel in a display area and a partial non-display area according to an embodiment of the present application, FIG. 21 is a structural schematic of another display panel in a multi-path distribution unit setting area according to an embodiment of the present application, FIG. 22 is a structural schematic of a first semiconductor layer in the display area and the partial non-display area of the display panel of FIG. 20, FIG. 23 is a structural schematic of the first semiconductor layer in the multi-path distribution unit setting area of the display panel of FIG. 21, FIG. 24 is a structural schematic of a first metal layer in the display area and the partial non-display area of the display panel of FIG. 20, FIG. 25 is a structural schematic of the first metal layer in the multi-path distribution unit setting area of the display panel of FIG. 21, FIG. 26 is a structural schematic of a second metal layer in the display area and the partial non-display area of the display panel of FIG. 20, FIG. 27 is a structural schematic of the second metal layer in the multi-path distribution unit setting area of the display panel of FIG. 21, FIG. 28 is a structural schematic of a second semiconductor layer in the display area and the partial non-display area of the display panel of FIG. 20, FIG. 29 is a structural schematic of a third metal layer in the display area and the partial non-display area of the display panel of FIG. 20, FIG. 30 is a structural schematic of a fourth metal layer in the display area and the partial non-display area of the display panel of FIG. 20, FIG. 31 is a structural schematic of the fourth metal layer in the multi-path distribution unit setting area of the display panel of FIG. 21, FIG. 32 is a structural schematic of a fifth metal layer in the display area and the partial non-display area of the display panel of FIG. 20, FIG. 33 is a structural schematic of the fifth metal layer in the multi-path distribution unit setting area of the display panel of FIG. 21, FIG. 34 is a structural schematic of a sixth metal layer in the display area and the partial non-display area of the display panel of FIG. 20, FIG. 35 is a structural schematic of the sixth metal layer in the multi-path distribution unit setting area of the display panel of FIG. 21, FIG. 36 is a structural schematic of an anode layer in the display area of the display panel of FIG. 20, FIG. 37 is a schematic of a partial layer stack of the display panel of FIG. 20, FIG. 38 is a schematic of a partial layer stack of the display panel of FIG. 21, FIG. 39 is a schematic of another partial layer stack of the display panel of FIG. 20, FIG. 40 is a schematic of another partial layer stack of the display panel of FIG. 21, and FIG. 41 is a schematic of still another partial layer stack of the display panel of FIG. 20, as shown in FIGS. 20-41, the overlapping portions of the first sub-wire branch FIAA11 and the second sub-wire branch FIAA12 in the second direction are also symmetrical about the first virtual axis X1, which on one hand makes the two first-wire branch connections to the same multi-path distribution unit DEMUX neat, and on the other hand facilitates better symmetry of color shift of the display image, so that the four-orientation color shift can be changed.

[0115] FIG. 42 is a schematic view of an electrical connection of a pixel circuit, FIG. 43 is a timing sequence of the pixel circuit of FIG. 42, FIG. 44 is a schematic view of an electrical connection of another pixel circuit, FIG. 45 is a timing sequence of the pixel circuit of FIG. 44, FIG. 46 is a schematic view of a structure of a display panel, FIG. 47 is a schematic view of a first semiconductor layer of the display panel of FIG. 46, FIG. 48 is a schematic view of a first metal layer of the display panel of FIG. 46, FIG. 49 is a schematic view of a second metal layer of the display panel of FIG. 46, FIG. 50 is a schematic view of a second semiconductor layer of the display panel of FIG. 46, FIG. 51 is a schematic view of a third metal layer of the display panel of FIG. 46, FIG. 52 is a schematic view of a fourth metal layer of the display panel of FIG. 46, FIG. 53 is a schematic view of a fifth metal layer of the display panel of FIG. 46, FIG. 54 is a schematic view of a sixth metal layer of the display panel of FIG. 46, FIG. 55 is a schematic view of an anode layer of the display panel of FIG. 46, FIG. 56 is a schematic view of a stack of a partial film layer of the display panel of FIG. 46, FIG. 57 is a schematic view of a stack of another partial film layer of the display panel of FIG. 46, FIG. 58 is a schematic view of a structure of another display panel, FIG. 59 is a schematic view of a first semiconductor layer of the display panel of FIG. 58, FIG. 60 is a schematic view of a first metal layer of the display panel of FIG. 58, FIG. 61 is a schematic view of a second metal layer of the display panel of FIG. 58, FIG. 62 is a schematic view of a second semiconductor layer of the display panel of FIG. 58, FIG. 63 is a schematic view of a third metal layer of the display panel of FIG. 58, FIG. 64 is a schematic view of a fourth metal layer of the display panel of FIG. 58, FIG. 65 is a schematic view of a fifth metal layer of the display panel of FIG. 58, FIG. 66 is a schematic view of an anode layer of the display panel of FIG. 58, FIG. 67 is a schematic view of a stack of a partial film layer of the display panel of FIG. 58, FIG. 68 is a schematic view of a stack of another partial film layer of the display panel of FIG. 58, FIG. 69 is a schematic view of a structure of another display panel, FIG. 70 is a schematic view of a first semiconductor layer of the display panel of FIG. 69, FIG. 71 is a schematic view of a first metal layer of the display panel of FIG. 69, FIG. 72 is a schematic view of a second metal layer of the display panel of FIG. 69, FIG. 73 is a schematic view of a second semiconductor layer of the display panel of FIG. 69, FIG. 74 is a schematic view of a third metal layer of the display panel of FIG. 69, FIG. 75 is a schematic view of a fourth metal layer of the display panel of FIG. 69, FIG. 76 is a schematic view of a fifth metal layer of the display panel of FIG. 69, FIG. 77 is a schematic view of an anode layer of the display panel of FIG. 69, FIG. 78 is a schematic view of a stack of a partial film layer of the display panel of FIG. 69, and FIG. 79 is a schematic view of a stack of another partial film layer of the display panel of FIG. 69.FIG. 79 is a schematic view of another partial layer stack of the display panel of FIG. 69, in conjunction with FIGS. 4-79, the display panel further includes pixel circuit 20; the pixel circuit includes at least one first type transistor and at least one second type transistor, the first type transistor includes a first active layer POLY, and the second type transistor includes a second active layer IGZO; the first active layer POLY includes silicon, and the second active layer IGZO includes oxide.

[0116] For example, the pixel circuit provided by the embodiments of the present application includes the first type transistor and the second type transistor, the first type transistor can be a low temperature poly-silicon (LTPS) transistor, and the active layer of the low temperature poly-silicon transistor includes silicon. The low temperature poly-silicon transistor has the advantages of high switching speed, high carrier mobility and small power. The second type transistor can be an oxide (IGZO) transistor, and the active layer of the oxide transistor includes oxide. The oxide transistor has the advantage of small leakage current. The pixel circuit provided by the embodiments of the present application includes the first type transistor and the second type transistor, and the pixel circuit has the advantages of high switching speed, high carrier mobility, small power and small leakage current, and the performance of the pixel circuit is excellent.

[0117] Optionally, as shown in FIGS. 42, 43 and 46-57, the pixel circuit provided by the embodiment of the present application can include a pixel circuit in the form of "7T1C", where "T" represents a transistor and "C" represents a capacitor. The pixel circuit includes a first light emitting control transistor T1, a data writing transistor T2, a driving transistor T3, a threshold compensation transistor T4, an initialization reset transistor T5, a second light emitting control transistor T6, an anode reset transistor T7 and a storage capacitor Cst. The working process can be roughly as follows: a scan signal line (shown as S1N in the figure) connected to the control end of the initialization reset transistor T5 can control the on and off of the initialization reset transistor T5, and write the reset signal in the reset signal line (shown as VREF1 in the figure) connected to the input end of the initialization reset transistor T5 to the gate of the driving transistor T3 when the initialization reset transistor T5 is turned on, so as to reset the first node N1. The storage capacitor Cst provided can ensure the stability of the potential of the first node N1. A scan signal line (shown as S2N in the figure) connected to the control end of the threshold compensation transistor T4 can control the on and off of the threshold compensation transistor T4, and perform threshold voltage compensation on the driving transistor T3 when the threshold compensation transistor T4 is turned on. A scan signal line (shown as SP* in the figure) connected to the control end of the data writing transistor T2 can control the on and off of the data writing transistor T2, and write the data signal on the data signal line DATA to the first electrode of the driving transistor T3 when the data writing transistor T2 is turned on. At the same time, a scan signal line (shown as SP in the figure) connected to the control end of the anode reset transistor T7 can control the on and off of the anode reset transistor T7, and reset the anode of the light emitting element 30 connected to the pixel circuit, i.e. write the reset signal on the reset signal line (shown as VFER2 in the figure) to the anode of the light emitting element 30, when the anode reset transistor T7 is turned on. The light emitting control signal line EMIT connected to the control end of the first light emitting control transistor T1 and the control end of the second light emitting control transistor T6 can control the on and off of the control end of the first light emitting control transistor T1 and the second light emitting control transistor T6, and write the power signal transmitted by the power signal line PVDD to the light emitting element 30 when the first light emitting control transistor T1 and the second light emitting control transistor T6 are turned on, so as to realize the display and light emission of the light emitting element 30. Specifically, as shown in FIG. 43, in one driving period Y of the pixel circuit, it includes a data writing stage Y1, a light emitting stage Y2 and a light emitting maintaining stage Y3, wherein the data writing stage Y1 includes one non-enabled level stage of the light emitting control signal Emit, the light emitting stage Y2 includes one enabled level stage of the light emitting control signal Emit, and in the light emitting maintaining stage Y3, the light emitting control signal Emit includes multiple non-enabled level stages and at least one enabled level stage (one enabled level stage is taken as an example for illustration in FIG. 43).Optionally, the signal transmitted by the scan signal line SP during the data writing stage Y1 includes at least one low level period, the anode reset transistor T7 is turned on, and the anode reset signal line VREF2 can reset the anode of the light emitting element 30 through the anode reset transistor T7. And during the period, the signal transmitted by the scan signal line S2N includes at least one high level period, the initialization transistor T5 is turned on, and the initialization signal line VREF1 can adjust the gate of the driving transistor T3 through the initialization transistor T5. Optionally, the signal transmitted by the scan signal line SP* includes at least one low level period, the data writing transistor T2 is turned on, and at the same time, the signal transmitted by the scan signal line S1N includes at least one high level period, the threshold compensation transistor T4 is turned on, and the data signal Vdata can be transmitted to the gate of the driving transistor T3 through the data writing transistor T2 and the threshold compensation transistor T4; At the same time, the signal transmitted by the light emitting control signal line EMIT includes at least one low level device, the light emitting control transistor T1 and T6 are turned on, and the driving transistor T3 is used to convert the power signal provided by the power signal line PVDD and the data signal provided by the data signal line DATA into a driving current for driving the light emitting element 30 to emit light, realizing light emitting.

[0118] Optionally, with continued reference to FIGS. 4-41, 44, 45, and 58-79, the pixel circuit provided by embodiments of the present application can be in the form of an "8T1C" pixel circuit, where "T" represents a transistor and "C" represents a capacitor. The pixel circuit can include a first light emitting control transistor T1, a data writing transistor T2, a driving transistor T3, a threshold compensation transistor T4, an initialization reset transistor T5, a second light emitting control transistor T6, an anode reset transistor T7, a bias transistor T8, and a storage capacitor Cst. The working process can be roughly as follows: a scan signal line (shown as S1N in the figure) connected to the control end of the initialization reset transistor T5 can control the on and off of the initialization reset transistor T5, and when the initialization reset transistor T5 is turned on, the reset signal in the reset signal line (shown as VREF1 in the figure) connected to the input end of the initialization reset transistor T5 is written to the gate of the driving transistor T3, and the first node N1 is reset. The storage capacitor Cst provided can ensure the stability of the potential of the first node N1. A scan signal line (shown as S2N in the figure) connected to the control end of the threshold compensation transistor T4 can control the on and off of the threshold compensation transistor T4, and when the threshold compensation transistor T4 is turned on, the driving transistor T3 is threshold voltage compensated. A scan signal line (shown as SP* in the figure) connected to the control end of the data writing transistor T2 can control the on and off of the data writing transistor T2, and when the data writing transistor T2 is turned on, the data signal on the data signal line DATA is written to the first electrode of the driving transistor T3. At the same time, a scan signal line (shown as SP in the figure) connected to the control end of the anode reset transistor T7 and the control end of the bias transistor T8 can control the on and off of the anode reset transistor T7 and the bias transistor T8, and when the anode reset transistor T7 is turned on, the anode of the light emitting element 30 connected to the pixel circuit is reset, i.e., the reset signal on the reset signal line (shown as VFER2 in the figure) is written to the anode of the light emitting element 30; when the bias transistor T8 is turned on, the bias signal transmitted by the reset signal line (shown as DVH in the figure) is written to the bias transistor T8, and the second node N2 is biased and adjusted. The light emitting control signal line EMIT connected to the control end of the first light emitting control transistor T1 and the control end of the second light emitting control transistor T6 can control the on and off of the first light emitting control transistor T1 and the second light emitting control transistor T6, and when the first light emitting control transistor T1 and the second light emitting control transistor T6 are turned on, the power supply signal transmitted by the power supply signal line PVDD is written to the light emitting element 30, thereby realizing the display and light emission of the light emitting element 30.For example, referring to FIG. 45, in one driving period Y of the pixel circuit, a data writing stage Y1, a light emitting stage Y2 and a light emitting maintaining stage Y3 are included, wherein the data writing stage Y1 includes one non-enabling stage of the light emitting control signal Emit, the light emitting stage Y2 includes one enabling stage of the light emitting control signal Emit, and the light emitting maintaining stage Y3 includes a plurality of non-enabling stages and at least one enabling stage (one enabling stage is exemplified in FIG. 45). The level of the bias voltage signal line DVH in the data writing stage Y1 and the light emitting stage Y2 can be the same as or different from the level of the bias voltage signal line DVH in the light emitting maintaining stage Y3 (as shown in FIG. 45). Optionally, the data writing stage Y1 includes a first bias adjusting stage Y11, in which the signal transmitted by the scanning signal line SP includes at least one low voltage period, and the signal transmitted by the scanning signal line S2N includes at least one high voltage period, in other words, in the first bias adjusting stage Y11, at least the bias transistor T8 and the threshold compensation transistor T4 are turned on, the bias signal of the bias voltage signal line DVH is transmitted to the driving transistor T3 through the bias transistor T8, and is further transmitted to the gate of the driving transistor T3 through the threshold compensation transistor T4, that is, in the first bias adjusting stage Y11, the bias signal can be used for bias adjusting the first node N1, the second node N2 and the third node N3. The data writing stage Y1 further includes an initializing and second bias adjusting stage Y12, in which the signal transmitted by the scanning signal line S2N includes at least one high voltage period, and there is also a period in which the signal transmitted by the scanning signal line S2N includes at least one high voltage period, in other words, in the initializing and second bias adjusting stage Y12, the initializing transistor T5 is turned on, and the threshold compensation transistor T4 is also turned on later, the initializing signal line VREF1 can be used for adjusting the gate of the driving transistor T3 through the initializing transistor T5, and the initializing signal line VREF1 can also be used for adjusting the third node N3 through the initializing transistor T5 and the threshold compensation transistor T4. The data writing stage Y1 further includes a data signal writing stage Y13, in which the signal transmitted by the scanning signal line S2N includes a high voltage period, and there is also a period in which the signal transmitted by the scanning signal line SP includes at least one low voltage period, in other words, in the data signal writing stage Y13, the data writing transistor T2 and the threshold compensation transistor T4 are turned on, and the data signal Vdata can be transmitted to the gate of the driving transistor T3 through the data writing transistor T2 and the threshold compensation transistor T4.The data writing stage Y1 further comprises a third bias adjusting stage Y14, in which the signal transmitted by the scan signal line SP comprises at least one low level period, and the second stage N2 can be further biased by the bias transistor T8 during the period.

[0119] Optionally, FIG. 80 is a schematic view of a film layer structure of a display panel provided by an embodiment of the present application. In combination with FIGS. 4-41, 46-57 and 80, the pixel circuit 20 further comprises a storage capacitor Cst, the storage capacitor Cst comprises a first plate Cst1 and a second plate Cst2 arranged oppositely, the second plate Cst2 is located on a side of the first plate Cst1 away from the first active layer POLY; the second type transistor further comprises a top gate MG, the top gate MG is located on a side of the second active layer IGZO away from the first active layer POLY; the display panel further comprises a first semiconductor layer 101, a first metal layer 102, a second metal layer 103, a second semiconductor layer 104, a third metal layer 105, a fourth metal layer 106, a fifth metal layer 107 and a sixth metal layer 108; the first active layer POLY is located on the first semiconductor layer 101, the first plate Cst1 is located on the first metal layer 102, the second plate Cst2 is located on the second metal layer 103, the second active layer IGZO is located on the second semiconductor layer 104, the top gate MG is located on the third metal layer 105, the fourth metal layer 106 is located on a side of the third metal layer 105 away from the first active layer POLY, the fifth metal layer 107 is located on a side of the fourth metal layer 106 away from the first active layer POLY, and the sixth metal layer 108 is located on a side of the fifth metal layer 107 away from the first active layer POLY; the data signal line DATA and the first walk line part FIAA1 are arranged on the same layer and are both located on the sixth metal layer 108.

[0120] For example, the first plate Cst1 is located on the first metal layer 102, which can be an M1 metal layer; the second plate Cst2 is located on the second metal layer 103, which can be an MC metal layer; the top gate MG is located on the third metal layer 105, which can be an MG metal layer; the fourth metal layer 106 is located on the side of the third metal layer 105 away from the first active layer POLY, which can be a first source-drain metal layer SD1 in the display panel, that is, an M2 metal layer; the fifth metal layer 107 is located on the side of the fourth metal layer 106 away from the first active layer POLY, which can be a second source-drain metal layer SD2 in the display panel, that is, an M3 metal layer; the sixth metal layer 108 is located on the side of the fifth metal layer 107 away from the first active layer POLY, which can be a third source-drain metal layer SD3 in the display panel, that is, an M4 metal layer; and the display panel further includes an anode layer 109, that is, an RE metal layer. The sixth metal layer 108 can be the metal layer closest to the anode layer in the display panel, that is, the display panel in the embodiment of the present application can be a display panel including three source-drain metal layers. The data signal line DATA and the first trace part FIAA1 are arranged on the same layer and are both located on the sixth metal layer 108, that is, both are located on the third source-drain metal layer SD3. Optionally, at least one insulating layer exists between two adjacent metal layers or between a metal layer and a semiconductor layer, which can be an organic insulating layer or an inorganic insulating layer.

[0121] On the basis of the above embodiment, FIG. 81 is a schematic diagram of a film layer structure of another display panel provided in an embodiment of the present application. In combination with FIGS. 58-79 and FIG. 81, the pixel circuit 20 further includes a storage capacitor Cst, which includes a first plate Cst1 and a second plate Cst2 arranged oppositely, and the second plate Cst2 is located on the side of the first plate Cst1 away from the first active layer POLY; the second type transistor further includes a top gate MG, which is located on the side of the second active layer IGZO away from the first active layer POLY; the display panel further includes a first semiconductor layer 101, a first metal layer 102, a second metal layer 103, a second semiconductor layer 104, a third metal layer 105, a fourth metal layer 106, and a fifth metal layer 107; the first active layer POLY is located on the first semiconductor layer 101, the first plate Cst1 is located on the first metal layer 102, the second plate Cst2 is located on the second metal layer 103, the second active layer IGZO is located on the second semiconductor layer 104, the top gate MG is located on the third metal layer 105, the fourth metal layer 106 is located on the side of the third metal layer 105 away from the first active layer POLY, and the fifth metal layer 107 is located on the side of the fourth metal layer 106 away from the first active layer POLY; the data signal line DATA and the first trace part FIAA1 are arranged on the same layer and are both located on the fifth metal layer 107.

[0122] For example, the first electrode plate Cst1 is located in the first metal layer 102, which can be an M1 metal layer; the second electrode plate Cst2 is located in the second metal layer 103, which can be an MC metal layer; the top gate MG is located in the third metal layer 105, which can be an MG metal layer; the fourth metal layer 106 is located on the side of the third metal layer 105 away from the first active layer POLY, which can be a first source-drain metal layer SD1 in the display panel, i.e., an M2 metal layer; the fifth metal layer 107 is located on the side of the fourth metal layer 106 away from the first active layer POLY, which can be a second source-drain metal layer SD2 in the display panel, i.e., an M3 metal layer; and the display panel further includes an anode layer 109, i.e., an RE metal layer. The fifth metal layer 107 can be the metal layer closest to the anode layer in the display panel, i.e., the display panel in the embodiment of the present application can be a display panel including two source-drain metal layers. The data signal line DATA and the first trace portion FIAA1 are arranged in the same layer and are both located in the fifth metal layer 107, i.e., both are located in the second source-drain metal layer SD2. Optionally, at least one insulating layer exists between two adjacent metal layers or between a metal layer and a semiconductor layer, which can be an organic insulating layer or an inorganic insulating layer.

[0123] Optionally, continuing to refer to FIGS. 4-19, 46-57, and 58-68, the display panel further includes a plurality of groups of data signal lines 40, each group of data signal lines 40 including a plurality of data signal lines DATA, and the plurality of data signal lines DATA in the same group of data signal lines 40 are electrically connected to the outputs D of a plurality of demultiplexing switches K in the same demultiplexing unit DEMUX; and the first trace portion FIAA1 is located outside the group of data signal lines 40 in which the first data signal line DATA corresponding thereto is arranged.

[0124] As shown in FIGS. 4-19, 46-57, and 58-68, the plurality of data signal lines DATA in the same data signal line group 40 are electrically connected to the output ends D of the plurality of demultiplexing switches K in the same demultiplexing unit DEMUX, so that the plurality of data signal lines DATA in each data signal line group 40 input data signals in time under the control of the demultiplexing unit DEMUX. Optionally, the data signal lines DATA and the first wiring section FIAA1 can be arranged in the same layer, and in order to match the arrangement positions of different transistors in the pixel circuit, the first wiring section FIAA1 can be arranged in the data signal line group 40 in which the first data signal line DATA1 corresponding to the first wiring section FIAA1 is arranged, so as to satisfy the electrical connection relationship between the data signal line DATA and the corresponding data writing transistor. It should be noted that FIGS. 4-19, 46-57, and 58-68 all take an example in which each data signal line group 40 includes two data signal lines DATA, and the number of data signal lines DATA included in each data signal line group 40 is not limited in the embodiments of the present application.

[0125] Optionally, continuing to refer to FIGS. 20-41 and 69-79, the display panel further includes a plurality of data signal line groups 40, each data signal line group 40 includes a plurality of data signal lines DATA, the plurality of data signal lines DATA in the same data signal line group 40 are electrically connected to the output ends D of the plurality of demultiplexing switches K in the same demultiplexing unit DEMUX; and the first wiring section FIAA1 is arranged in the data signal line group 40 in which the first data signal line DATA1 corresponding to the first wiring section FIAA1 is arranged.

[0126] As shown in FIGS. 20-41 and 69-79, the plurality of data signal lines DATA in the same data signal line group 40 are electrically connected to the output ends D of the plurality of demultiplexing switches K in the same demultiplexing unit DEMUX, so that the plurality of data signal lines DATA in each data signal line group 40 input data signals in time under the control of the demultiplexing unit DEMUX. Optionally, the data signal lines DATA and the first wiring section FIAA1 can be arranged in the same layer, and in order to match the arrangement positions of different transistors in the pixel circuit, the first wiring section FIAA1 can be arranged in the data signal line group 40 in which the first data signal line DATA1 corresponding to the first wiring section FIAA1 is arranged, so as to satisfy the electrical connection relationship between the data signal line DATA and the corresponding data writing transistor. It should be noted that FIGS. 20-41 and 69-79 all take an example in which each data signal line group 40 includes two data signal lines DATA, and the number of data signal lines DATA included in each data signal line group 40 is not limited in the embodiments of the present application.

[0127] Optionally, continuing to refer to FIGS. 4-41, the display panel further comprises a plurality of data signal line groups 40, each data signal line group 40 comprising a plurality of data signal lines DATA, the plurality of data signal lines DATA in the same data signal line group 40 being electrically connected to the output ends D of the plurality of demultiplexing switches K in the same demultiplexing unit DEMUX; the display panel further comprises a plurality of first trace segment groups 50, each first trace segment group 50 comprising a plurality of first trace segments FIAA1, the plurality of first trace segments FIAA1 in the same first trace segment group 50 being electrically connected to the output ends D of the plurality of demultiplexing switches K in the same demultiplexing unit DEMUX; each data signal line group 40 comprises at least one first data signal line DATA1.

[0128] For example, the plurality of data signal lines DATA in the same data signal line group 40 are electrically connected to the output ends D of the plurality of demultiplexing switches K in the same demultiplexing unit DEMUX, so that the plurality of data signal lines DATA in each data signal line group 40 input data signals in time under the control of the demultiplexing unit DEMUX. The plurality of first trace segments FIAA1 in the same first trace segment group 50 are electrically connected to the output ends D of the plurality of demultiplexing switches K in the same demultiplexing unit DEMUX, so that the plurality of first trace segments FIAA1 in each first trace segment group 50 input data signals in time under the control of the demultiplexing unit DEMUX. Optionally, each data signal line group 40 comprises at least one first data signal line DATA1, that is, there is at least one data signal line in each data signal line group 40 that has a corresponding first trace segment FIAA1 arranged therewith, so that the data signal line is not interfered by the first trace segment FIAA1 arranged in close proximity thereto when the potential of the first trace segment FIAA1 is floating, and does not interfere with the signal in the first trace segment FIAA1 arranged in close proximity thereto when the potential of the first trace segment FIAA1 is floating, ensuring the accuracy of the data signal during transmission.

[0129] For example, in the embodiments shown in FIGS. 4-19, each data signal line group 40 includes two data signal lines DATA, for example, the two data signal lines DATA can include two first data signal lines DATA1, so that each data signal line DATA in the data signal line group 40 will not be greatly disturbed by the first trace section FIAA1 disposed in close proximity thereto when the potential is floating, and will also not greatly disturb the data signal in the first trace section FIAA1 disposed in close proximity thereto, ensuring the accuracy during data signal transmission. In the embodiments shown in FIGS. 20-41, each data signal line group 40 includes two data signal lines DATA, for example, the two data signal lines DATA include one first data signal line DATA1, so that one data signal line DATA in the data signal line group 40 will not be greatly disturbed by the first trace section FIAA1 disposed in close proximity thereto when the potential is floating, and will also not greatly disturb the data signal in the first trace section FIAA1 disposed in close proximity thereto, ensuring the accuracy during data signal transmission. Moreover, when each data signal line group 40 includes one first data signal line DATA1, the signal access mode of the control end of the multiplexing switch electrically connected to the data signal line DATA in the data signal line group 40 is higher in degree of freedom, and the control logic of the multiplexing switch is simpler and more efficient.

[0130] On the basis of the above embodiments, continuing to refer to FIGS. 4-41, at least two first data signal lines DATA1 corresponding to at least two first trace sections FIAA1 in the same first trace section group 50 are disposed in at least two data signal line groups 40 disposed adjacent along the second direction.

[0131] Referring to FIGS. 4-41, at least two first trace sections FIAA1 in the same first trace section group 50 can be a first sub-trace section FIAA11 and a second sub-trace section FIAA12, respectively. For example, in the position shown in the figure, the first sub-trace section FIAA11 is located on the left side of the second sub-trace section FIAA12 in the same first trace section group 50, and the first data signal line DATA1 corresponding to the first sub-trace section FIAA11 is also located on the left side of the second sub-trace section FIAA12. The second sub-trace section FIAA12 is located on the right side of the first sub-trace section FIAA11, and the first data signal line DATA1 corresponding to the second sub-trace section FIAA12 is also located on the right side of the first sub-trace section FIAA12. Compared with the scheme in which the at least two first data signal lines DATA1 corresponding to the at least two first trace sections FIAA1 in the same first trace section group 50 are located in the same data signal line group 40, the problem of lengthening the line when the first data signal line DATA1 is electrically connected to the multi-way distribution switch can be avoided, the wiring difficulty when the first data signal line DATA1 is electrically connected to the multi-way distribution switch is reduced, and the correspondence difficulty of the first trace section FIAA1 and the first data signal line DATA1 is simplified.

[0132] On the basis of the above-mentioned embodiments, with continued reference to FIGS. 4-19, each data signal line group 40 includes at least two first data signal lines DATA1; and at least two first trace sections FIAA1 corresponding to the at least two first data signal lines DATA1 in the same data signal line group 40 are electrically connected to the output ends of the multi-way distribution switches in different multi-way distribution units DEMUX.

[0133] For example, at least two first data signal lines DATA1 in the same data signal line group 40 can be a first sub-data signal line DATA11 and a second sub-data signal line DATA12, respectively. For example, in the position shown in FIG. 16, in the same data signal line group 40, the first sub-data signal line DATA11 is located on the right side of the second sub-data signal line DATA12, and the first trace part FIAA1 corresponding to the first sub-data signal line DATA11 is also located on the right side of the second sub-data signal line DATA12; the second sub-data signal line DATA12 is located on the left side of the first sub-data signal line DATA11, and the first trace part FIAA1 corresponding to the second sub-data signal line DATA12 is also located on the left side of the first sub-data signal line DATA11. Compared with the scheme that the at least two first trace parts FIAA1 corresponding to the at least two first data signal lines DATA1 in the same data signal line group 40 are located in the same first trace part group 50, the problem of lengthening the line when the first trace part FIAA1 is electrically connected with the multi-way distribution switch can be avoided, the wiring difficulty when the first trace part FIAA1 is electrically connected with the multi-way distribution switch is reduced, and the correspondence difficulty of the first trace part FIAA1 and the first data signal line DATA1 is simplified.

[0134] In summary, the above embodiments describe the correspondence setting mode between the data signal line and the first trace part. On the basis of the above embodiments, with reference to FIGS. 20-41, 58-68, and 69-79, the display panel provided by the embodiments of the present application can further include an auxiliary connection line 60, the auxiliary connection line 60 extends along the first direction, and the auxiliary connection line is arranged in the same layer as the first trace part FIAA1.

[0135] For example, referring to FIGS. 20-41, 58-68 and 69-79, the display panel provided by the embodiments of the present application further comprises an auxiliary connection line 60, which is arranged in the same layer as the first trace part FIAA1, for example, in the second source-drain electrode layer or in the third source-drain metal layer. In one aspect, the auxiliary connection line 60 can serve as an isolation line between different data signal lines, for example, between data signal lines, between data signal lines and the first trace part, or between first trace parts, to avoid coupling interference between different signal lines. In another aspect, the auxiliary connection line 60 can balance the wiring density in different areas. For example, referring to FIGS. 20-41 and 69-79, at least part of the auxiliary connection line 60 and at least part of the first trace part FIAA1 can be symmetrically arranged about a virtual axis, to avoid differences in flatness in different areas of the panel due to different wiring densities, thereby affecting the preparation of subsequent film layers and the uniformity of the overall light transmission effect.

[0136] Optionally, continuing to refer to FIGS. 20-41, each data signal line group 40 comprises a first data signal line DATA1; each data signal line group 40 further comprises a second data signal line DATA2; the display panel further comprises a second virtual axis X2 extending in the first direction; at least part of the first data signal line DATA1 and at least part of the second data signal line DATA2 are symmetric about the second virtual axis X2; at least part of the first trace part FIAA1 and at least part of the auxiliary connection line 60 are symmetric about the second virtual axis X2.

[0137] For example, referring to FIGS. 20-41, each data signal line group 40 includes a first data signal line DATA1, that is, a data signal line in each data signal line group 40, and part of the data signal lines, that is, the first data signal line DATA1, has a first routing section FIAA1 arranged thereon; part of the data signal lines, that is, the second data signal line DATA2, does not have a first routing section FIAA1 arranged thereon. In terms of routing density, the first data signal line DATA1 has a first routing section FIAA1 arranged thereon, while the second data signal line DATA2 does not have a first routing section FIAA1 arranged thereon, and thus the first data signal line DATA1 and the second data signal line DATA2 have an uneven routing density. In the embodiments of the present application, at least part of the first data signal line DATA1 and at least part of the second data signal line DATA2 are symmetrical about the second virtual axis X2, and at least part of the first routing section FIAA1 and at least part of the auxiliary connection line 60 are symmetrical about the second virtual axis X2, that is, in terms of routing density, the auxiliary connection line 60 and the first routing section FIAA1 have the same or similar routing positions, and thus the first data signal line DATA1 and the second data signal line DATA2 have the same or similar routing densities, and the same data signal line group has the same or similar routing densities around different data signal lines, and thus the display panel has good flatness and optical properties due to the balanced routing density.

[0138] On the basis of the above embodiments, the first routing section is arranged on the side of the first data signal line away from the auxiliary connection line, and the auxiliary connection line is arranged on the side of the second data signal line away from the first routing section, that is, the first routing section and the auxiliary connection line are arranged on the two sides of the same data signal line group, that is, outside the data signal line group. Such an arrangement is used to match the arrangement of the transistors in the pixel circuit, to ensure the electrical connection between the data signal line and the data writing transistor, and is also conducive to the routing density of the same data signal line group, for example, in the second display area where no data connection routing is arranged, the good routing density of the data signal line can compress the space, so as to leave space for arranging more data signal line groups and pixel circuits, and thus the display resolution of the display panel is improved.

[0139] Optionally, continuing to refer to FIGS. 20-41, the first trace portion FIAA1 is located on one side of the first data signal line DATA1 close to the auxiliary connection line 60, and the auxiliary connection line 60 is located on one side of the second data signal line DATA2 close to the first trace portion FIAA1, that is, the first trace portion FIAA1 and the auxiliary connection line 60 are located in the same data signal line group, respectively. In this way, on the one hand, it is used to match the arrangement of the transistors in the pixel circuit, to ensure the electrical connection relationship between the data signal line DATA and the data writing transistor, and on the other hand, the auxiliary connection line 60 can serve as a physical isolation line between the first trace portion FIAA1 and the second data signal line DATA2, to reduce the mutual interference between the signals in the first trace portion FIAA1 and the second data signal line DATA2, and to ensure the independence and stability of the signals in the first trace portion FIAA1 and the second data signal line DATA2. At the same time, the auxiliary connection line 60 can also serve as a physical isolation line between the first data signal line DATA1 and the second data signal line DATA2, to reduce the mutual interference between the signals in the first data signal line DATA1 and the second data signal line DATA2, and to ensure the independence and stability of the signals in the first data signal line DATA1 and the second data signal line DATA2.

[0140] On the basis of the above embodiment, continuing to refer to FIGS. 58-68, each data signal line group 40 includes two first data signal lines DATA1; the display panel further includes a third virtual axis X3 extending along the first direction; at least part of the two first data signal lines DATA1 in the same data signal line group 40 are symmetrical about the third virtual axis X3; at least part of the two first trace portions FIAA1 corresponding to the two first data signal lines DATA1 are symmetrical about the third virtual axis X3; and the auxiliary connection line 60 and the third virtual axis X3 at least partially overlap in the orthographic projection on the substrate plane.

[0141] For example, as shown in FIGS. 58-68, at least part of the two first data signal lines DATA1 in the same data signal line group 40 are symmetric about the third virtual axis X3, at least part of the two first trace sections FIAA1 corresponding to the two first data signal lines DATA1 are symmetric about the third virtual axis X3, that is, on both sides of the third virtual axis X3, there are corresponding first data signal lines DATA1 and first trace sections FIAA1, and the control ends of the two multiplexing switches connected to the corresponding first data signal lines DATA1 and first trace sections FIAA1 are connected to the same switch control signal, which ensures that the corresponding first data signal lines DATA1 and first trace sections FIAA1 input data signals at the same time, and one of them does not float and is not disturbed by the coupling of the other, which ensures that the coupling interference between data signals is small, which is beneficial to the accurate transmission of data signals. Optionally, the orthogonal projection of the auxiliary connection line 60 on the substrate plane at least partially overlaps the orthogonal projection of the third virtual axis X3 on the substrate plane, that is, at least part of the two first data signal lines DATA1 in the same data signal line group 40 are symmetric about the auxiliary connection line 60, and at least part of the two first trace sections FIAA1 corresponding to the two first data signal lines DATA1 are symmetric about the auxiliary connection line 60, that is, on both sides of the third virtual axis X3, which can isolate the two first data signal lines DATA1 in the same data signal line group 40 that transmit data signals at different times, and isolate the two first trace sections FIAA1 that transmit data signals at different times, and isolate the first data signal lines DATA1 and the first trace sections FIAA1 that transmit data signals at different times, which reduces the coupling interference between the two signal lines that transmit data signals at different times and improves the accuracy of data signal transmission.

[0142] Optionally, the first trace section corresponding to the first data signal line is located on the side of the first data signal line close to the auxiliary connection line axis, that is, among the corresponding first data signal line and the first trace section, the first trace section is located on the side close to the auxiliary connection line, which ensures that the data signals in the two first trace sections that transmit data signals at different times can be well isolated by the auxiliary connection line.

[0143] Optionally, continuing to refer to FIGS. 58-68, the first trace section FIAA1 corresponding to the first data signal line DATA1 is located on the side of the first data signal line DATA1 away from the auxiliary connection line 60, that is, among the corresponding first data signal line DATA1 and the first trace section FIAA1, the first data signal line DATA1 is located on the side close to the auxiliary connection line 60, which ensures that the data signals in the two first data signal lines DATA1 that transmit data signals at different times can be well isolated by the auxiliary connection line.

[0144] On the basis of the above-mentioned embodiments, with continued reference to FIGS. 20-41, the auxiliary connection line 60 is electrically connected with the fixed potential signal line.

[0145] Exemplarily, the auxiliary connection line 60 is electrically connected with the fixed potential signal line, so that the fixed potential signal is transmitted in the auxiliary connection line 60, which can further isolate the mutual interference between the signal lines located on both sides of the auxiliary connection line 60, for example, isolate the coupling interference between the data signal lines, for example, isolate the coupling interference between the data signal line and the first trace part, for example, isolate the coupling interference between the first trace parts, so as to ensure to reduce the coupling interference between different signal lines and improve the signal transmission accuracy. Moreover, the auxiliary connection line 60 and the fixed potential signal line form a parallel structure, which can further reduce the loss of the signal transmitted in the fixed potential signal line in the transmission process, so as to ensure that the fixed potential signal transmission loss is small.

[0146] On the basis of the above-mentioned embodiments, the display panel further comprises a pixel circuit 20; the pixel circuit comprises a reset transistor; the signal line further comprises a reset signal line; the reset signal line is electrically connected with the first electrode of the reset transistor, and the auxiliary connection line is multiplexed as the reset signal line.

[0147] As described above, the pixel circuit 20 comprises a transistor for performing gate reset on the gate of the driving transistor T3, a transistor for performing reset on the anode of the light emitting element, and a transistor for performing reset on some connection nodes, and these reset transistors are coupled between the reset signal line and the node to be reset, and the signals transmitted in the reset signal line are all fixed potential signals. Therefore, the auxiliary connection line is multiplexed as the reset signal line, which can reduce the layout difficulty of the reset signal line and simplify the preparation process of the display panel.

[0148] Exemplarily, with reference to FIGS. 58-79, the display panel further comprises a light emitting element 30; the reset transistor comprises an initialization reset transistor T5 and an anode reset transistor T7; the reset signal line comprises an initialization reset signal line VREF1 and an anode reset signal line VREF2; the pixel circuit further comprises a driving transistor T3; the initialization reset transistor T5 is electrically connected between the initialization reset signal line VREF1 and the gate of the driving transistor T3; the anode reset transistor T7 is electrically connected between the anode reset signal line VREF2 and the light emitting element 30; and the auxiliary connection line 60 is multiplexed as the initialization reset signal line VREF1 and / or the anode reset signal line VREF2.

[0149] As described above, the initialization reset signal in the initialization reset signal line VREF1 connected to the input end of the initialization reset transistor T5 can be written to the gate of the driving transistor T3 to reset the gate of the driving transistor T3 when the initialization reset transistor T5 is turned on. The anode reset signal in the anode reset signal line VREF2 connected to the input end of the anode reset transistor T7 can be written to the anode of the light emitting element to reset the anode of the light emitting element when the anode reset transistor T7 is turned on. Optionally, the initialization reset signal line VREF1 can include a first initialization reset line VREF11 extending in the first direction, and the anode reset signal line VREF2 can include a first anode reset line VREF21 extending in the first direction. The auxiliary connection line 60 is multiplexed as at least one of the first initialization reset line VREF11 and the first anode reset line VREF21 to reduce the wiring difficulty of the first initialization reset line VREF11 and / or the first anode reset line VREF21.

[0150] Optionally, continuing to refer to FIGS. 58-79, the initialization reset signal line VREF1 can further include a second initialization reset line VREF12 extending in the second direction, and / or the anode reset signal line VREF2 can include a second anode reset line VREF22 extending in the second direction. The second initialization reset line VREF12 is arranged in a layer different from the first initialization reset line VREF11 and is electrically connected, so as to form a grid-shaped initialization reset signal line to reduce the transmission loss of the initialization reset signal. Similarly, the second anode reset line VREF22 is arranged in a layer different from the first anode reset line VREF21 and is electrically connected, so as to form a grid-shaped anode reset signal line to reduce the transmission loss of the anode reset signal. Referring to FIGS. 58-79, the anode reset signal line VREF2 is taken as an example to illustrate that the second anode reset line VREF22 extends in the second direction, and the second anode reset line VREF22 includes two parts arranged alternately and electrically connected in the second direction, which are respectively located in the third metal layer MG and the fourth metal layer M2.

[0151] Optionally, continuing to refer to FIGS. 58-79, the display panel further comprises the light emitting element 30; the reset transistor comprises the initialization reset transistor T5, the anode reset transistor T7 and the bias reset transistor T8; the reset signal line comprises the initialization reset signal line VREF1, the anode reset signal line VREF2 and the bias reset signal line DVH; the pixel circuit further comprises the driving transistor T3; the initialization reset transistor T3 is electrically connected between the initialization reset signal line VREF1 and the gate of the driving transistor T3, the anode reset transistor T7 is electrically connected between the anode reset signal line VREF2 and the light emitting element 30; the bias reset transistor T8 is electrically connected between the bias reset signal line DVH and the first pole and / or the second pole of the driving transistor T3; the auxiliary connection line is multiplexed as at least one of the initialization reset signal line VREF1, the anode reset signal line VREF2 and the bias reset signal line DVH.

[0152] As previously described, the initialization reset signal in the initialization reset signal line VREF1 connected to the input end of the initialization reset transistor T5 can be written to the gate of the driving transistor T3 to reset the gate of the driving transistor T3 when the initialization reset transistor T5 is turned on. The anode reset signal in the anode reset signal line VREF2 connected to the input end of the anode reset transistor T7 can be written to the anode of the light emitting element to reset the anode of the light emitting element when the anode reset transistor T7 is turned on. The bias adjustment signal in the bias adjustment signal line DVH connected to the input end of the bias adjustment transistor T8 can be written to the first pole and / or the second pole of the driving transistor T3 to bias adjust the first pole and / or the second pole of the driving transistor T3 when the bias adjustment transistor T8 is turned on. Optionally, the initialization reset signal line VREF1 can comprise a first initialization reset line VREF11 extending in the first direction, the anode reset signal line VREF2 can comprise a first anode reset line VREF21 extending in the first direction, the bias adjustment signal line DVH can comprise a first bias adjustment line DVH1 extending in the first direction, and the auxiliary connection line 60 is multiplexed as at least one of the first initialization reset line VREF11, the first anode reset line VREF21 and the first bias adjustment line DVH1 to reduce the wiring difficulty of at least one of the first initialization reset line VREF11, the first anode reset line VREF21 and the first bias adjustment line DVH1.

[0153] Optionally, continuing to refer to FIGS. 58-79, FIGS. 58-79 take the auxiliary connection line 60 multiplexing as the first anode reset line VREF21 and the first bias adjustment line DVH1 as an example for illustration. When the auxiliary connection line 60 multiplexes as the first anode reset line VREF21 and the first bias adjustment line DVH1, the first anode reset line VREF21 and the first bias adjustment line DVH1 are alternately arranged in the second direction to ensure that the first anode reset line VREF21 and the first bias adjustment line DVH1 have relatively balanced distribution in the entire display area.

[0154] Optionally, the initialization reset signal line VREF1 can also include a second initialization reset line VREF12 extending in the second direction, the anode reset signal line VREF2 can include a second anode reset line VREF22 extending in the second direction, and the bias adjustment signal line DVH can include a second bias adjustment line DVH2 extending in the second direction. The second initialization reset line VREF12 is arranged in a different layer from the first initialization reset line VREF11 and is electrically connected, thus forming a grid-shaped initialization reset signal line to reduce the transmission loss of the initialization reset signal. Similarly, the second anode reset line VREF22 is arranged in a different layer from the first anode reset line VREF21 and is electrically connected, thus forming a grid-shaped anode reset signal line to reduce the transmission loss of the anode reset signal. Similarly, the second bias adjustment line DVH2 is arranged in a different layer from the first bias adjustment line DVH1 and is electrically connected, thus forming a grid-shaped bias adjustment signal line to reduce the transmission loss of the bias adjustment signal. Referring to FIGS. 58-79, the anode reset signal line VREF2 includes a second anode reset line VREF22 extending in the second direction, and the bias adjustment signal line DVH can include a second bias adjustment line DVH2 extending in the second direction as an example for illustration. The second anode reset line VREF22 includes two parts arranged alternately and electrically connected in the second direction, which are located in the third metal layer MG and the fourth metal layer M2 respectively, and the second bias adjustment line DVH2 is located in the second metal layer MC.

[0155] In summary of the above, the above embodiments illustrate the setting mode of the data signal line and the data connection trace. Next, the setting mode of the multiplexing unit connected with the data signal line and the data connection trace is further illustrated.

[0156] Referring to FIGS. 4-41, the demultiplexer DEMUX includes a plurality of first demultiplexers DEMUX1 and a plurality of second demultiplexers DEMUX2. The output terminals of the demultiplexing switches in the first demultiplexers DEMUX1 are electrically connected to the data signal lines DATA, and the output terminals of the demultiplexing switches in the second demultiplexers DEMUX2 are electrically connected to the first routing sections FIAA1. In the second direction, the second demultiplexers DEMUX2 are arranged between adjacent first demultiplexers DEMUX1.

[0157] For example, the demultiplexers DEMUX electrically connected to the data signal lines DATA are the first demultiplexers DEMUX1, and the demultiplexers DEMUX electrically connected to the first routing sections FIAA1 are the second demultiplexers DEMUX2. The second demultiplexers DEMUX2 are arranged between adjacent first demultiplexers DEMUX1, as distinguished from the scheme in which the plurality of first demultiplexers DEMUX1 are arranged together and the plurality of second demultiplexers DEMUX2 are arranged together. In the embodiment of the present application, the arrangement of the first demultiplexers DEMUX1 and the plurality of second demultiplexers DEMUX2 can ensure that the distance between the first demultiplexers DEMUX1 and the data signal lines DATA to which the first demultiplexers DEMUX1 are connected is small, and the pull length of the connection structure connecting the data signal lines DATA and the first demultiplexers DEMUX1 is small. In addition, the distance between the second demultiplexers DEMUX2 and the first routing sections FIAA1 to which the second demultiplexers DEMUX2 are connected is small, and the pull length of the connection structure connecting the first routing sections FIAA1 and the first demultiplexers DEMUX1 is small. In this way, on the one hand, the pull difficulty can be reduced and the connection stability can be improved. On the other hand, the connection structure with a small length occupies a small space, and does not occupy too much space of the non-display area, which is conducive to reducing the proportion of the non-display area and improving the proportion of the display area.

[0158] Optionally, referring to FIGS. 4-19, in the second direction, the first demultiplexers DEMUX1 and the plurality of second demultiplexers DEMUX2 are arranged alternately, which further reduces the pull length of the connection structure connecting the data signal lines DATA and the first demultiplexers DEMUX1, and the pull length of the connection structure connecting the first routing sections FIAA1 and the first demultiplexers DEMUX1, sufficiently reduces the wiring difficulty and the occupied space, and takes into account the connection stability and the proportion of the display screen.

[0159] On the basis of the above-mentioned embodiments, with reference to FIGS. 4-19, the display panel further comprises a fan-out area NAA2, the fan-out area NAA2 comprises a plurality of fan-out wires FANOUT; the fan-out area NAA2 is located at a side of the demultiplexing unit setting area NAA1 close to the display area AA, and the data signal line DATA or the first wire part FIAA1 is electrically connected to the output end of the demultiplexing switch through the fan-out wire FANOUT.

[0160] With reference to FIGS. 4-19, the fan-out area NAA2 is located at a side of the demultiplexing unit setting area NAA1 close to the display area AA, the output end D of the demultiplexing switch K is electrically connected to the fan-out wire FANOUT, and the fan-out wire FANOUT is electrically connected to the data signal line DATA or the first wire part FIAA1, so that the normal transmission of the data signal is realized.

[0161] On the basis of the above-mentioned embodiments, with reference to FIGS. 20-41, the display panel further comprises a fan-out area NAA2, the fan-out area NAA2 comprises a plurality of fan-out wires FANOUT; the fan-out area NAA2 is located at a side of the demultiplexing unit setting area NAA1 away from the display area AA, and the input end S of the demultiplexing switch K is electrically connected to the data signal output terminal through the fan-out wire FANOUT.

[0162] With reference to FIGS. 20-41, the demultiplexing unit setting area NAA1 is located between the fan-out area NAA2 and the display area AA, the input end S of the demultiplexing switch K is electrically connected to the fan-out wire FANOUT, and the output end D is electrically connected to the data signal line DATA or the first wire part FIAA1, so that the normal transmission of the data signal is realized.

[0163] Optionally, when the fan-out area NAA2 is located at a side of the demultiplexing unit setting area NAA1 away from the display area AA, the number of the fan-out wires FANOUT can be the same as the number of the demultiplexing units, so that the number of the fan-out wires FANOUT can be reduced, and the wiring difficulty and the occupied space of the fan-out wires FANOUT can be reduced.

[0164] Optionally, with reference to FIGS. 4-41, the fan-out wire FANOUT comprises a first fan-out wire FANOUT1 and a second fan-out wire FANOUT2 arranged alternately in a second direction; the first fan-out wire FANOUT1 and the second fan-out wire FANOUT2 are arranged in different layers.

[0165] The fan-out wires FANOUT are arranged in different layers and the first fan-out wires FANOUT1 and the second fan-out wires FANOUT2 are arranged alternately in the second direction, which can reduce the coupling interference between the adjacent two fan-out wires FANOUT and the wiring difficulty of the adjacent two fan-out wires FANOUT. Optionally, the first fan-out wires FANOUT1 can be arranged in the first metal layer M1, and the second fan-out wires FANOUT2 can be arranged in the second metal layer MC. The arrangement of the fan-out wires FANOUT does not increase the metal film layers in the display panel, which is beneficial to the thin design of the display panel.

[0166] Optionally, continuing to refer to FIGS. 4-19, the same demultiplexer DEMUX includes at least a first demultiplexing switch K1 and a second demultiplexing switch K2; the at least two switch control lines SW include at least a first switch control line SW1 and a second switch control line SW2; the control ends of the plurality of first demultiplexing switches K1 are electrically connected to the first switch control line SW1, and the control ends of the plurality of second demultiplexing switches K2 are electrically connected to the second switch control line SW2.

[0167] Optionally, continuing to refer to FIGS. 4-19, the same demultiplexer DEMUX includes at least a first demultiplexing switch K1 and a second demultiplexing switch K2; the at least two switch control lines SW include at least a first switch control line SW1 and a second switch control line SW2; the control ends of the plurality of first demultiplexing switches K1 are electrically connected to the first switch control line SW1, and the control ends of the plurality of second demultiplexing switches K2 are electrically connected to the second switch control line SW2.

[0168] Optionally, continuing to refer to FIGS. 20-41, the same demultiplexer includes at least a first demultiplexing switch K1 and a second demultiplexing switch K2; the at least two switch control lines SW include at least a first switch control line SW1, a second switch control line SW2, a third switch control line SW3, and a fourth switch control line SW4, the first switch control line SW1 and the third switch control line SW3 are electrically connected to the same switch control signal output end, and the second switch control line SW2 and the fourth switch control line SW4 are electrically connected to the same switch control signal output end; the control ends of part of the first demultiplexing switches K1 are electrically connected to the first switch control line SW1, and the control ends of part of the first demultiplexing switches K1 are electrically connected to the third switch control line SW3; the control ends of part of the second demultiplexing switches K2 are electrically connected to the second switch control line SW2, and the control ends of part of the second demultiplexing switches K2 are electrically connected to the fourth switch control line SW4.

[0169] For example, the control terminals of some of the first plurality of distribution switches K1 are electrically connected to the first switch control line SW1, and the control terminals of some of the first plurality of distribution switches K1 are electrically connected to the third switch control line SW3. The first switch control line SW1 and the third switch control line SW3 are electrically connected to the same switch control signal output terminal, and the same switch control signal is transmitted thereon. In this way, the plurality of first plurality of switches K1 can be turned on or turned off at the same time. Similarly, the control terminals of some of the second plurality of distribution switches K2 are electrically connected to the second switch control line SW2, and the control terminals of some of the second plurality of distribution switches K2 are electrically connected to the fourth switch control line SW4. The second switch control line SW2 and the fourth switch control line SW4 are electrically connected to the same switch control signal output terminal, and the same switch control signal is transmitted thereon. In this way, the plurality of second plurality of switches K2 can be turned on or turned off at the same time. Optionally, the number of switch control lines SW is greater than the number of distribution switches in each distribution unit DEMUX. In this way, the number of loads connected to each switch control line SW can be reduced, and the switching control efficiency can be improved.

[0170] Optionally, continuing to refer to FIGS. 20-41, the first switch control line SW1, the second switch control line SW2, the third switch control line SW3, and the fourth switch control line SW4 are arranged in the first direction in sequence. In this way, the positions of the punched holes for connecting the control terminals of the distribution switches and the switch control lines can be staggered in the first direction, avoiding the problem of high difficulty in the punching process caused by the close proximity of the punched hole positions, and reducing the process difficulty.

[0171] For example, referring to FIGS. 20-41, the positions of the punched holes for connecting the control terminals of the distribution switches and the switch control lines are arranged in a "Z" shape, and are dispersed in the first direction and the second direction, thereby sufficiently reducing the process difficulty of the punched holes.

[0172] On the basis of the above-mentioned embodiments, continuing to refer to FIGS. 4-41, the display panel further includes a plurality of connection structures 70, which include a first connection structure 701 and a second connection structure 702. One end of the first connection structure 701 is electrically connected to the output end D of the distribution switch K, and the other end is electrically connected to the data signal line DATA. The first connection structure 701 is disposed in a different layer from the data signal line DATA. One end of the second connection structure 702 is electrically connected to the output end D of the distribution switch K, and the other end is electrically connected to the first wiring section FIAA1. The second connection structure 702 is disposed in a different layer from the first wiring section.

[0173] Exemplarily, the display panel further comprises a connection structure 70 for connecting the demultiplexing unit DEMUX and the data signal line DATA, or for connecting the demultiplexing unit DEMUX and the data connection trace FIAA. Specifically, a first connection structure 701 is used for connecting the demultiplexing unit DEMUX and the data signal line DATA, and a second connection structure 702 is used for connecting the demultiplexing unit DEMUX and the data connection trace FIAA. In the first direction, at least part of the connection structure 70 can be arranged between the demultiplexing unit DEMUX and the data signal line DATA, or between the demultiplexing unit DEMUX and the data connection trace FIAA; in terms of film layer relationship, at least part of the film layer of the connection structure 70 can be arranged between the film layer where the output end of the demultiplexing unit DEMUX is located and the film layer where the data signal line DATA is located, or between the film layer where the output end of the demultiplexing unit DEMUX is located and the film layer where the data connection structure FIAA is located, so as to realize the electrical connection relationship between the demultiplexing unit DEMUX and the data signal line DATA, or between the demultiplexing unit DEMUX and the data connection trace FIAA.

[0174] It should be noted that the connection structure provided in the embodiments of the present application can be a single-layer structure or a multi-film layer structure. As shown in FIGS. 4-19, the connection structure 70 is a multi-film layer structure comprising a fourth metal layer M2 and a fifth metal layer M3 film layer; as shown in FIGS. 20-41, the connection structure 70 is a single-film layer structure comprising a fifth metal layer M3. The number of film layers of the connection structure is not limited in the embodiments of the present application, as long as the electrical connection relationship between the demultiplexing unit DEMUX and the data signal line DATA, or between the demultiplexing unit DEMUX and the data connection trace FIAA can be realized.

[0175] Optionally, continuing to refer to FIGS. 4-19, the first trace part FIAA1 is located outside the data signal line group where the first data signal line DATA1 corresponding thereto is located; in the thickness direction of the display panel, the first connection structure 701 electrically connected with the first data signal line DATA1 and the first trace part FIAA1 corresponding to the first data signal line DATA1 do not overlap.

[0176] Exemplarily, since the first routing portion FIAA1 is arranged outside the data signal line group where the first data signal line DATA1 corresponding to the first routing portion FIAA1 is arranged, and the multiplexing / demultiplexing units connected to the first routing portion FIAA1 and the multiplexing / demultiplexing units electrically connected to the data signal line are arranged in sequence in the second direction, the first connection structure 701 electrically connected to the first data signal line DATA1 is arranged, and the first routing portion FIAA1 corresponding to the first data signal line DATA1 does not overlap, so that the connection between the data signal line and the multiplexing / demultiplexing unit and the connection between the data connection routing and the multiplexing / demultiplexing unit can be realized through the connection structure respectively, and the arrangement mode of the connection structure is simple.

[0177] Optionally, continuing to refer to FIGS. 20-41, the first routing portion FIAA1 is arranged in the data signal line group where the first data signal line DATA1 corresponding to the first routing portion FIAA1 is arranged; along the thickness direction of the display panel, the first connection structure 701 electrically connected to the first data signal line DATA1 overlaps the first routing portion FIAA1 corresponding to the first data signal line DATA1.

[0178] Exemplarily, since the first routing portion FIAA1 is arranged in the data signal line group where the first data signal line DATA1 corresponding to the first routing portion FIAA1 is arranged, and the multiplexing / demultiplexing units connected to the first routing portion FIAA1 and the multiplexing / demultiplexing units electrically connected to the data signal line are arranged in sequence in the second direction, the first connection structure 701 electrically connected to the first data signal line DATA1 is arranged, and the first routing portion FIAA1 corresponding to the first data signal line DATA1 overlaps, so that the connection between the data signal line and the multiplexing / demultiplexing unit and the connection between the data connection routing and the multiplexing / demultiplexing unit can be realized through the connection structure respectively, and the connection stability is ensured.

[0179] On the basis of the above-mentioned embodiments, continuing to refer to FIGS. 20-41, the display panel further comprises a power signal bus PVDD BUS arranged in the non-display area; along the thickness direction of the display panel, the power signal bus PVDD BUS overlaps the multiplexing / demultiplexing unit DEMUX.

[0180] As shown in FIGS. 20-41, by arranging the power signal bus PVDD BUS to overlap the multiplexing / demultiplexing unit DEMUX, for example, arranging the multiplexing / demultiplexing unit DEMUX in the lower film layer of the power signal bus PVDD BUS, the multiplexing / demultiplexing unit DEMUX is protected by the power signal bus PVDD BUS, and the structure and electrical performance of the multiplexing / demultiplexing unit DEMUX are stable. Optionally, arranging the multiplexing / demultiplexing unit DEMUX in the lower film layer of the power signal bus PVDD BUS can also save the lower frame area of the display panel, which is conducive to realizing the narrow frame design.

[0181] On the basis of the above-mentioned embodiments, with reference to FIGS. 4-19, 20-41, 46-57, 58-68 and 69-79 shown, in the lower frame area of the display panel, a plurality of vias can also be provided in the fifth transistor M3 and the sixth metal layer M4, through which the gas and stress in the panel are released, ensuring the stability of the structure and performance of the display panel in the lower frame area.

[0182] On the basis of the above-mentioned embodiments, with reference to FIGS. 4-19, 20-41, 46-57, 58-68 and 69-79 shown, the display panel further comprises light emitting elements 30; the light emitting elements 30 comprise first color light emitting elements 301, second color light emitting elements 302, third color light emitting elements 303 and fourth color light emitting elements 304, the first color light emitting elements 301, the second color light emitting elements 302, the third color light emitting elements 303 and the fourth color light emitting elements 304 are one or more of red light emitting elements, blue light emitting elements, green light emitting elements and white light emitting elements; a plurality of first color light emitting elements 301 and second color light emitting elements 302 constitute a first virtual quadrilateral S1, the first color light emitting elements 301 are at the first vertices of the first virtual quadrilateral, the second color light emitting elements 302 are at the second vertices of the first virtual quadrilateral S1, the first vertices and the second vertices are alternately and spaced apart, and the third color light emitting elements 303 or the fourth color light emitting elements 304 are inside the first virtual quadrilateral; a plurality of third color light emitting elements 303 and / or fourth color light emitting elements 304 constitute a second virtual quadrilateral S2, the plurality of third color light emitting elements 303 and / or fourth color light emitting elements 304 are respectively at the vertices of the second virtual quadrilateral S2, and the first color light emitting elements 301 or the second color light emitting elements 302 are inside the second virtual quadrilateral S2.

[0183] For example, with reference to FIGS. 4-19, 20-41, 46-57, 58-68 and 69-79 shown, a plurality of first color light emitting elements 301 and second color light emitting elements 302 constitute a first virtual quadrilateral S1, two first color light emitting elements 301 are located at opposite corners of the first virtual quadrilateral S1, two second color light emitting elements 302 are located at the other two opposite corners of the first virtual quadrilateral S1, and the third color light emitting elements 303 or the fourth color light emitting elements 304 are placed inside the first virtual quadrilateral S1, and the third color light emitting elements 303 inside the first virtual quadrilateral S1 are taken as an example for illustration in the figure.

[0184] Optionally, the third color light emitting elements 303 and / or the fourth color light emitting elements 304 can also form a second virtual quadrilateral S2, in which the first color light emitting elements 301 can be located inside, or the second color light emitting elements 302 can be located inside. Optionally, the first color, the second color, the third color and the fourth color correspond to one of red, blue, green and white respectively, and through the above arrangement of light emitting elements, the rendering effect of the light emitting elements can be better, and the color display effect of the display panel is further ensured.

[0185] On the basis of the above embodiments, with reference to FIGS. 4-19 and FIGS. 20-41, the display panel includes a signal line; the signal line includes a data signal line DATA, a plurality of data signal lines DATA extend along a first direction (X direction shown in the figure) and are arranged along a second direction (Y direction shown in the figure); the first direction and the second direction intersect; the display panel further includes a display area AA and a non-display area NAA surrounding at least part of the display area; the display area includes a first display area AA1 and a second display area AA1, the second display area AA1 is located on at least one side of the first display area AA1 along the second direction; the non-display area NAA includes a plurality of demultiplexer setting areas NAA1 located on one side of the display area along the first direction, the demultiplexer setting area NAA1 is provided with a plurality of demultiplexers DEMUX and at least two switch control lines SW; the demultiplexer DEMUX includes at least two demultiplexing switches K, the demultiplexing switch K includes an input end S, an output end D and a control end G; in the same demultiplexer DEMUX, the input ends S of the at least two demultiplexing switches K are connected, the output ends D of the at least two demultiplexing switches K are respectively electrically connected with different data signal lines DATA, and the control ends G of the at least two demultiplexing switches K are respectively electrically connected with different switch control lines SW; the first display area AA1 and the second display area AA2 both include a plurality of data signal lines DATA, and the signal line further includes a plurality of data connection traces FIAA, the data signal lines DATA located in the second display area AA1 are electrically connected with the output ends D of the demultiplexing switches K through the data connection traces FIAA; the data connection traces FIAA include a first trace part FIAA1, the first trace part FIAA1 extends along the first direction; the at least two first trace parts FIAA1 connected with the output ends of the same demultiplexer DEMUX include a first sub-trace part FIAA11 and a second sub-trace part FIAA12, and the display panel further includes a first virtual axis X1, the overlapping part of the first sub-trace part FIAA11 and the second sub-trace part FIAA12 in the second direction is symmetrically arranged about the first virtual axis X1.

[0186] For example, referring to FIG. 1 and FIG. 2, the display panel includes signal lines, which include a data signal line DATA and other signal lines required for ensuring normal operation of the display panel, such as a power signal line, a scanning signal line, and a touch signal line, and the like. Optionally, referring to FIG. 1, the display panel can further include a pixel circuit 20 and a light emitting element 30, the signal lines are electrically connected to the pixel circuit 20 and are configured to provide a voltage signal and / or a current signal to the pixel circuit 20; the pixel circuit 20 is electrically connected to the light emitting element 30 and is configured to drive the light emitting element 30 to emit light under the action of the voltage signal and / or the current signal. Optionally, the pixel circuit 20 can be configured in various ways, and the pixel circuit can be "2T1C", "7T1C", or "8T1C", wherein "T" represents a transistor, and "C" represents a storage capacitor. The specific configuration of the pixel circuit is not limited in the embodiments of the present application, for example, a "3T1C" or "6T1C" pixel circuit is also within the scope of the technical solutions protected by the embodiments of the present application. The light emitting element 30 can be at least one of a light emitting diode, an organic light emitting diode, and a micro light emitting diode, and the specific form of the light emitting element 30 is also not limited in the embodiments of the present application.

[0187] Continuing to refer to FIG. 1 and FIG. 2, the display panel provided by the embodiments of the present application includes a display area AA and a non-display area NAA, the data signal line DATA, the pixel circuit 20, and the light emitting element 30 described above can be disposed in the display area AA, and the non-display area NAA includes a plurality of demultiplexing unit setting areas NAA1. The plurality of demultiplexing unit setting areas NAA1 are provided with a plurality of demultiplexing units DEMUX and at least two switch control lines SW; the demultiplexing unit DEMUX includes at least two demultiplexing switches K; the input ends S of the at least two demultiplexing switches K in the same demultiplexing unit DEMUX are connected, the output ends D of the at least two demultiplexing switches K are respectively electrically connected to different data signal lines DATA, and the control ends G of the at least two demultiplexing switches are respectively electrically connected to different switch control lines SW. The demultiplexing unit K is used to transmit the signal input from the input end S to the data signal line DATA through the output end D under the action of the control signal in the switch control line SW, and the enable phases of the control signals in the different switch control signal lines SW are staggered to ensure that the at least two demultiplexing switches K in the same demultiplexing unit DEMUX are turned on at different times. That is, the same demultiplexing unit DEMUX can time-divisionally distribute the input signal transmitted by the same signal output end to any one of the plurality of data signal lines DATA, so as to reduce the number of signal output ends under the premise of realizing normal output of the data signal, and reduce the difficulty of layout of the signal output ends in the display panel.

[0188] Optionally, the display area AA further comprises a first display area AA1 and a second display area AA2. The second display area AA2 is located on both sides of the first display area AA1 along the second direction Y, as shown in FIG. 2, but is not limited thereto. In this arrangement, along the orientation shown in FIG. 2, the second display area AA2 is located between the first display area AA1 and the non-display areas NAA on the left and right sides, and along the second direction Y, the first display area AA1 is closer to the center of the display panel, and the second display area AA2 is closer to the edge of the display panel. The data signal line DATA located in the second display area is electrically connected to the output end D of the demultiplexing switch K through the data connection trace FIAA. At least part of the data connection trace FIAA is located in the display area AA, and at least part of the data connection trace FIAA is located in the first display area AA1. In this way, the demultiplexing unit DEMUX connected to the data signal line DATA and the data connection trace FIAA can be more concentrated below the first display area AA1, so that the connection line when the data signal line DATA and the data connection trace FIAA are connected to the demultiplexing switch K occupies less space in the first direction, which is beneficial to reducing the occupied space of the non-display area, and is beneficial to improving the display area ratio of the display panel and improving the screen-to-body ratio of the display panel.

[0189] For example, FIG. 3 illustrates an example in which the demultiplexing unit DEMUX includes two demultiplexing switches K1 and K2. Correspondingly, the display panel includes two switch control lines SW1 and SW2, the control end of the demultiplexing switch K1 is electrically connected to the switch control line SW1, the control end of the demultiplexing switch K2 is electrically connected to the switch control line SW2, and the switch control lines SW1 and SW2 transmit the enable signals of the demultiplexing switches in time division. When the enable signal is transmitted in the switch control line SW1, the demultiplexing switch K1 is turned on, and the demultiplexing switch K1 is used to transmit the data signal input by the input end to the data signal line DATA directly or through the data connection trace FIAA to the data signal line connected thereto. Similarly, when the enable signal is transmitted in the switch control line SW2, the demultiplexing switch K2 is turned on, and the demultiplexing switch K2 is used to transmit the data signal input by the input end to the data signal line DATA directly or through the data connection trace FIAA to the data signal line connected thereto.

[0190] Referring to FIGS. 4-41, the signal lines can further include a power signal line PVDD, the first sub-wiring section FIAA11 and the second sub-wiring section FIAA12 connected to the same demultiplexing unit DEMUX are located on two sides of the power signal line PVDD, and the overlapping part of the first sub-wiring section FIAA11 and the second sub-wiring section FIAA12 in the second direction is symmetric about the first virtual axis X1, that is, the first sub-wiring section FIAA11 and the second sub-wiring section FIAA12 connected to the same demultiplexing unit DEMUX are an axisymmetric structure, and the axis of symmetry can be the first virtual axis X1 passing through the center of the power signal line PVDD, and the first virtual axis X1 is also the boundary line of the adjacent two pixel circuit classes. The first sub-wiring section FIAA11 and the second sub-wiring section FIAA12 connected to the same demultiplexing unit DEMUX are an axisymmetric structure, and the boundary line of the adjacent two pixel circuit classes is used as the axis of symmetry, which not only makes the two first-wire sections connected to the same demultiplexing unit DEMUX regular, but also helps to make the color deviation of the display image have better symmetry, so that the four-direction color deviation can be changed, that is, the consistency and accuracy of the color can be improved when viewing the display image from any direction, and the display image can be viewed from a wider angle range without feeling obvious color change, thereby enhancing the user experience.

[0191] In summary, the display panel provided by the embodiments of the present application has the following advantages. The data signal line in the first display area is directly electrically connected to the output end of the demultiplexing switch, and the data signal line in the second display area is electrically connected to the output end of the demultiplexing switch through the data connection wire, and at least part of the data connection wire is located in the display area. In this way, the data signal line in the second display area can be avoided from being directly electrically connected to the output end of the demultiplexing switch, and the area of the non-display area can be avoided from being increased due to the direct electrical connection between the data signal line in the second display area and the output end of the demultiplexing switch, thereby improving the screen-to-body ratio of the display panel. Optionally, the first-wire section FIAA1 includes the first sub-wiring section FIAA11 and the second sub-wiring section FIAA12, and the overlapping part of the first sub-wiring section FIAA11 and the second sub-wiring section FIAA12 in the second direction is symmetric about the first virtual axis X1. In this way, the two first-wire sections connected to the same demultiplexing unit DEMUX are regular, and the color deviation of the display image has better symmetry, so that the four-direction color deviation can be changed.

[0192] Based on the same application concept, the embodiment of the present application also provides a display device, which comprises any one of the display panels provided by the above embodiments. FIG. 82 is a structural schematic diagram of a display panel provided by the embodiment of the present application. As shown in FIG. 82, the display device 1 comprises a display panel 100. Therefore, the display device also has the beneficial effects of the display panel in the above embodiments, and the same parts can be understood with reference to the above explanation and description of the display panel, which will not be repeated hereinafter.

[0193] The display device 1 provided by the embodiment of the present application can be a mobile phone as shown in FIG. 82, or any electronic product with display function, including but not limited to the following categories: television, notebook computer, desktop display, tablet computer, digital camera, smart bracelet, smart glasses, vehicle-mounted display, industrial control equipment, medical display screen, touch interaction terminal, etc., which are not specially limited by the embodiment of the present application.

Claims

1. A display panel comprising signal lines; the signal lines comprise data signal lines, a plurality of the data signal lines extend along a first direction and are arranged along a second direction; the first direction and the second direction intersect; the display panel further comprises a display area and a non-display area at least partially surrounding the display area; the display area comprises a first display area and a second display area, the second display area is located at least one side of the first display area along the second direction; the non-display area comprises a plurality of demultiplexing unit arrangement areas located at one side of the display area along the first direction, the plurality of demultiplexing unit arrangement areas are provided with a plurality of demultiplexing units and at least two switch control lines; the demultiplexing unit comprises at least two demultiplexing switches, the demultiplexing switch comprises an input end, an output end and a control end; in the same demultiplexing unit, the input ends of the at least two demultiplexing switches are connected, the output ends of the at least two demultiplexing switches are respectively electrically connected with different data signal lines, and the control ends of the at least two demultiplexing switches are respectively electrically connected with different switch control lines; the first display area and the second display area each comprise a plurality of data signal lines, the signal lines further comprise a plurality of data connection traces, the data signal lines located in the second display area are electrically connected with the output ends of the demultiplexing switches through the data connection traces; the data connection traces comprise first trace parts, the first trace parts extend along the first direction; the plurality of data signal lines comprise a first data signal line, the first data signal line is provided with a corresponding first trace part; in the corresponding first data signal line and first trace part, the control ends of the demultiplexing switches connected with the first data signal line and the control ends of the demultiplexing switches connected with the first trace part are connected with the same switch control signal; the distance between the first data signal line and the corresponding first trace part in the second direction is less than the distance between the first data signal line and any other first trace part in the second direction, and less than the distance between the first data signal line and any other data signal line in the second direction.

2. The display panel of claim 1, wherein, the at least two first trace parts connected with the output ends of the same demultiplexing unit comprise a first sub-trace part and a second sub-trace part; the display panel further comprises a first virtual axis, the first virtual axis extends along the first direction; the overlapping part of the first sub-trace part and the second sub-trace part in the second direction is symmetrical about the first virtual axis.

3. The display panel of claim 1, further comprising a plurality of data signal line groups, each data signal line group comprising a plurality of data signal lines, the plurality of data signal lines in the same data signal line group being electrically connected with the output ends of a plurality of demultiplexing switches in the same demultiplexing unit. The display panel further comprises a plurality of first trace sub-groups, each of the first trace sub-groups comprises a plurality of first trace sub-lines, and the plurality of first trace sub-lines in the same first trace sub-group are electrically connected to the output terminals of the plurality of multiplexing switches in the same multiplexing unit. Each of the data signal line groups comprises at least one first data signal line.

4. The display panel of claim 3, wherein, At least two first data signal lines corresponding to at least two first trace sub-lines in the same first trace sub-group are arranged in at least two data signal line groups arranged adjacently along the second direction.

5. The display panel of claim 3, wherein, Each of the data signal line groups comprises at least two first data signal lines. At least two first trace sub-lines corresponding to at least two first data signal lines in the same data signal line group are electrically connected to the output terminals of the multiplexing switches in different multiplexing units.

6. The display panel of claim 3, wherein, The signal lines further comprise auxiliary connection lines, the auxiliary connection lines extend along the first direction, and the auxiliary connection lines are arranged in the same layer as the first trace sub-lines.

7. The display panel of claim 6, wherein, Each of the data signal line groups comprises one first data signal line. Each of the data signal line groups further comprises one second data signal line. The display panel further comprises a second virtual axis extending along the first direction, and at least part of the first data signal lines and at least part of the second data signal lines are symmetrical about the second virtual axis. At least part of the first trace sub-lines and at least part of the auxiliary connection lines are symmetrical about the second virtual axis.

8. The display panel of claim 7, wherein, The first trace sub-lines are located on one side of the first data signal lines away from the auxiliary connection lines, and the auxiliary connection lines are located on one side of the second data signal lines away from the first trace sub-lines.

9. The display panel of claim 7, wherein, The first trace sub-lines are located on one side of the first data signal lines close to the auxiliary connection lines, and the auxiliary connection lines are located on one side of the second data signal lines close to the first trace sub-lines.

10. The display panel of claim 6, wherein, Each of the data signal line groups comprises two first data signal lines. The display panel further comprises a third virtual axis extending along the first direction, and at least part of the two first data signal lines in the same data signal line group are symmetrical about the third virtual axis. At least part of the two first trace sub-lines corresponding to the two first data signal lines are symmetrical about the third virtual axis. The display panel further comprises a substrate, and a projection of the auxiliary connection lines on a plane in which the substrate is located at least partially overlaps a projection of the third virtual axis on the plane in which the substrate is located. The first trace sub-line corresponding to the first data signal line is located on one side of the first data signal line close to the auxiliary connection line.

11. The display panel of claim 10, wherein, The first trace sub-line corresponding to the first data signal line is located on one side of the first data signal line away from the auxiliary connection line.

12. The display panel of claim 10, wherein, The auxiliary connection line is electrically connected to a fixed potential signal line.

13. The display panel of claim 6, wherein, 14. The display panel of claim 13, further comprising pixel circuits. ​ The pixel circuit comprises a reset transistor; The signal line further comprises a reset signal line; The reset signal line is electrically connected with the first electrode of the reset transistor, The auxiliary connection line is multiplexed as the reset signal line.

15. The display panel of claim 14, further comprising a light emitting element; The reset transistor comprises an initialization reset transistor and an anode reset transistor; The reset signal line comprises an initialization reset signal line and an anode reset signal line; The pixel circuit further comprises a driving transistor; the initialization reset transistor is electrically connected between the initialization reset signal line and the gate of the driving transistor; the anode reset transistor is electrically connected between the anode reset signal line and the light emitting element; The auxiliary connection line is multiplexed as the initialization reset signal line and / or the anode reset signal line.

16. The display panel of claim 14, further comprising a light emitting element; The reset transistor comprises an initialization reset transistor, an anode reset transistor and a bias reset transistor; The reset signal line comprises an initialization reset signal line, an anode reset signal line and a bias reset signal line; The pixel circuit further comprises a driving transistor; the initialization reset transistor is electrically connected between the initialization reset signal line and the gate of the driving transistor; the anode reset transistor is electrically connected between the anode reset signal line and the light emitting element; the bias reset transistor is electrically connected between the bias reset signal line and the first electrode and / or the second electrode of the driving transistor; The auxiliary connection line is multiplexed as at least one of the initialization reset signal line, the anode reset signal line and the bias reset signal line.

17. The display panel of claim 1, further comprising a plurality of data signal line groups, each of the data signal line groups comprising a plurality of the data signal lines, the plurality of the data signal lines in the same data signal line group being electrically connected with the outputs of a plurality of the demultiplication switches in the same demultiplication unit; The first trace subpart is located within the data signal line group in which the first data signal line is arranged.

18. The display panel of claim 1, further comprising a plurality of data signal line groups, each of the data signal line groups comprising a plurality of the data signal lines, the plurality of the data signal lines in the same data signal line group being electrically connected with the outputs of a plurality of the demultiplication switches in the same demultiplication unit; The first trace subpart is located outside the data signal line group in which the first data signal line is arranged.

19. The display panel of claim 1, further comprising a pixel circuit; The pixel circuit comprises at least one first type transistor and at least one second type transistor, the first type transistor comprising a first active layer, the second type transistor comprising a second active layer; The first active layer comprises silicon, and the second active layer comprises oxide.

20. The display panel of claim 19, wherein, The pixel circuit further comprises a storage capacitor, the storage capacitor comprises a first plate and a second plate arranged oppositely, and the second plate is located on a side of the first plate away from the first active layer; The second type transistor further comprises a top gate, and the top gate is located on a side of the second active layer away from the first active layer; The display panel further comprises a first semiconductor layer, a first metal layer, a second metal layer, a second semiconductor layer, a third metal layer, a fourth metal layer, and a fifth metal layer; The first active layer is located on the first semiconductor layer, the first plate is located on the first metal layer, the second plate is located on the second metal layer, the second active layer is located on the second semiconductor layer, the top gate is located on the third metal layer, the fourth metal layer is located on a side of the third metal layer away from the first active layer, and the fifth metal layer is located on a side of the fourth metal layer away from the first active layer; The data signal line and the first wire part are arranged in the same layer and are both located on the fifth metal layer.

21. The display panel of claim 19, wherein, The pixel circuit further comprises a storage capacitor, the storage capacitor comprises a first plate and a second plate arranged oppositely, and the second plate is located on a side of the first plate away from the first active layer; The second type transistor further comprises a top gate, and the top gate is located on a side of the second active layer away from the The display panel further comprises a first semiconductor layer, a first metal layer, a second metal layer, a second semiconductor layer, a third metal layer, a fourth metal layer, a fifth metal layer, and a sixth metal layer; The first active layer is located on the first semiconductor layer, the first plate is located on the first metal layer, the second plate is located on the second metal layer, the second active layer is located on the second semiconductor layer, the top gate is located on the third metal layer, the fourth metal layer is located on a side of the third metal layer away from the first active layer, the fifth metal layer is located on a side of the fourth metal layer away from the first active layer, and the sixth metal layer is located on a side of the fifth metal layer away from the first active layer; The data signal line and the first wire part are arranged in the same layer and are both located on the sixth metal layer. The plurality of distribution units comprises a plurality of first distribution units and a plurality of second distribution units, the output end of the distribution switch in the first distribution unit is electrically connected with the data signal line, and the output end of the distribution switch in the second distribution unit is electrically connected with the first wire part; 22. The display panel of claim 1, wherein, In the second direction, the second distribution unit is arranged between two adjacent first distribution units.

23. The display panel of claim 1, further comprising a fan-out area, the fan-out area comprising a plurality of fan-out wires; The fan-out area is located on a side of the plurality of distribution unit arrangement areas close to the display area, and the data signal line or the first wire part is electrically connected with the output end of the distribution switch through the fan-out wire.

24. The display panel of claim 1, further comprising a fan-out area, the fan-out area comprising a plurality of fan-out wires; ​ The fan-out area is located on the side of the demultiplexing unit setting area away from the display area, and the input end of the demultiplexing switch is electrically connected with the data signal output terminal through the fan-out wire.

25. The display panel of claim 23 or 24, wherein, The fan-out wire includes first fan-out wires and second fan-out wires arranged alternately in the second direction. The first fan-out wires and the second fan-out wires are arranged in different layers.

26. The display panel of claim 1, wherein, The same demultiplexing unit includes at least a first demultiplexing switch and a second demultiplexing switch. The at least two switch control lines include at least a first switch control line and a second switch control line. The control ends of the plurality of first demultiplexing switches are electrically connected with the first switch control line, and the control ends of the plurality of second demultiplexing switches are electrically connected with the second switch control line.

27. The display panel of claim 1, wherein, The same demultiplexing unit includes at least a first demultiplexing switch and a second demultiplexing switch. The at least two switch control lines include at least a first switch control line, a second switch control line, a third switch control line and a fourth switch control line, the first switch control line and the third switch control line are electrically connected with the same switch control signal output terminal, and the second switch control line and the fourth switch control line are electrically connected with the same switch control signal output terminal. The control ends of part of the first demultiplexing switches are electrically connected with the first switch control line, and the control ends of part of the first demultiplexing switches are electrically connected with the third switch control line. The control ends of part of the second demultiplexing switches are electrically connected with the second switch control line, and the control ends of part of the second demultiplexing switches are electrically connected with the fourth switch control line.

28. The display panel of claim 26, wherein, The first switch control line, the second switch control line, the third switch control line and the fourth switch control line are arranged in sequence along the first direction.

29. The display panel of claim 3, further comprising a plurality of connection structures, the connection structures comprising first connection structures and second connection structures; One end of the first connection structure is electrically connected with the output end of the demultiplexing switch, the other end is electrically connected with the data signal line, and the first connection structure is arranged in a different layer from the data signal line; One end of the second connection structure is electrically connected with the output end of the demultiplexing switch, the other end is electrically connected with the first wire part, and the second connection structure is arranged in a different layer from the first wire part.

30. The display panel of claim 29, wherein, The first wire part is located in the data signal line group in which the first data signal line corresponding to the first wire part is located; Along the thickness direction of the display panel, the first connection structure electrically connected with the first data signal line and the first wire part corresponding to the first data signal line overlap.

31. The display panel of claim 29, wherein, The first wire part is located outside the data signal line group in which the first data signal line corresponding to the first wire part is located; Along the thickness direction of the display panel, the first connection structure electrically connected with the first data signal line and the first wire part corresponding to the first data signal line do not overlap.

32. The display panel of claim 1, wherein, The display panel further comprises a power signal bus located in the non-display area; The power supply signal bus overlaps the plurality of distribution units in a thickness direction of the display panel.

33. The display panel of claim 1, further comprising light emitting elements; The light emitting elements comprise first color light emitting elements, second color light emitting elements, third color light emitting elements, and fourth color light emitting elements, the first color light emitting elements, the second color light emitting elements, the third color light emitting elements, and the fourth color light emitting elements being one or more of red light emitting elements, blue light emitting elements, green light emitting elements, and white light emitting elements; A plurality of the first color light emitting elements and the second color light emitting elements form a first virtual quadrilateral, the first color light emitting elements being at first vertices of the first virtual quadrilateral, the second color light emitting elements being at second vertices of the first virtual quadrilateral, the first vertices and the second vertices being alternately and spaced apart, and the third color light emitting elements or the fourth color light emitting elements being inside the first virtual quadrilateral; A plurality of the third color light emitting elements and / or the fourth color light emitting elements form a second virtual quadrilateral, the plurality of the third color light emitting elements and / or the fourth color light emitting elements being at vertices of the second virtual quadrilateral, respectively, and the first color light emitting elements or the second color light emitting elements being inside the second virtual quadrilateral.

34. A display panel, comprising signal lines; The signal lines comprise data signal lines, the data signal lines extending in a first direction and being arranged in a second direction; the first direction and the second direction intersecting; The display panel further comprises a display area and a non-display area at least partially surrounding the display area; the display area comprises a first display area and a second display area, the second display area being located at least on one side of the first display area in the second direction; the non-display area comprises a plurality of distribution unit arrangement areas located on one side of the display area in the first direction, the plurality of distribution unit arrangement areas being provided with a plurality of distribution units and at least two switch control lines; the distribution unit comprises at least two distribution switches, the distribution switches comprising input ends, output ends, and control ends; in the same distribution unit, the input ends of the at least two distribution switches are connected, the output ends of the at least two distribution switches are respectively electrically connected with different data signal lines, and the control ends of the at least two distribution switches are respectively electrically connected with different switch control lines; The first display area and the second display area each comprise a plurality of data signal lines, the signal lines further comprising a plurality of data connection traces, the data signal lines in the second display area being electrically connected with the output ends of the distribution switches through the data connection traces; The data connection traces comprise first trace sections, the first trace sections extending in the first direction; ​ At least two of the first sub-wire sections and the second sub-wire sections comprise a first sub-wire section and a second sub-wire section, and the display panel further comprises a first virtual axis, and the overlapping parts of the first sub-wire section and the second sub-wire section in the second direction are symmetrically arranged about the first virtual axis.

35. The display panel of claim 34, wherein, The plurality of data signal lines comprises a first data signal line, and the first data signal line is provided with a first sub-wire section corresponding thereto; the control end of the multiplexing switch connected to the first data signal line and the control end of the multiplexing switch connected to the first sub-wire section corresponding to the first data signal line are connected to the same switch control signal; the distance between the first data signal line and the first sub-wire section corresponding thereto in the second direction is less than the distance between the first data signal line and any other first sub-wire section in the second direction, and is less than the distance between the first data signal line and any other data signal line in the second direction; The display panel further comprises a plurality of data signal line groups, each data signal line group comprising a plurality of data signal lines, and the plurality of data signal lines in the same data signal line group are electrically connected to the output ends of a plurality of multiplexing switches in the same multiplexing unit; The display panel further comprises a plurality of first sub-wire section groups, each first sub-wire section group comprising a plurality of first sub-wire sections, and the plurality of first sub-wire sections in the same first sub-wire section group are electrically connected to the output ends of a plurality of multiplexing switches in the same multiplexing unit; Each data signal line group comprises at least one first data signal line.

36. The display panel of claim 35, wherein, At least two first data signal lines corresponding to at least two first sub-wire sections in the same first sub-wire section group are located in at least two data signal line groups arranged adjacent to each other in the second direction.

37. The display panel of claim 35, wherein, Each data signal line group comprises at least two first data signal lines; At least two first sub-wire sections corresponding to at least two first data signal lines in the same data signal line group are electrically connected to the output ends of the multiplexing switches in different multiplexing units.

38. The display panel of claim 35, wherein, The signal lines further comprise an auxiliary connection line, the auxiliary connection line extends in the first direction, and the auxiliary connection line is arranged on the same layer as the first sub-wire section.

39. The display panel of claim 38, wherein, Each data signal line group comprises one first data signal line; Each data signal line group further comprises one second data signal line; The display panel further comprises a second virtual axis, the second virtual axis extends in the first direction; at least part of the first data signal lines and at least part of the second data signal lines are symmetric about the second virtual axis; At least part of the first sub-wire sections and at least part of the auxiliary connection lines are symmetric about the second virtual axis.

40. The display panel of claim 39, wherein, The first trace part is located on a side of the first data signal line away from the auxiliary connection line.

41. The display panel of claim 39, wherein, The first trace part is located on a side of the first data signal line close to the auxiliary connection line.

42. The display panel of claim 38, wherein, Each of the data signal line groups includes two first data signal lines. The display panel further includes a third virtual axis extending along the first direction; at least part of the two first data signal lines in the same data signal line group are symmetric about the third virtual axis. At least part of the two first trace parts corresponding to the two first data signal lines are symmetric about the third virtual axis. The display panel further includes a substrate, and a projection of the auxiliary connection line on a plane where the substrate is located at least partially overlaps a projection of the third virtual axis on the plane where the substrate is located.

43. The display panel of claim 42, wherein, The first trace part corresponding to the first data signal line is located on a side of the first data signal line close to the auxiliary connection line.

44. The display panel of claim 42, wherein, The first trace part corresponding to the first data signal line is located on a side of the first data signal line away from the auxiliary connection line.

45. The display panel of claim 38, wherein, The auxiliary connection line is electrically connected with a fixed potential signal line.

46. The display panel of claim 45, further comprising a pixel circuit. The pixel circuit includes a reset transistor. The signal line further includes a reset signal line. The reset signal line is electrically connected with a first electrode of the reset transistor. The auxiliary connection line is multiplexed as the reset signal line.

47. The display panel of claim 46, further comprising a light emitting element. The reset transistor includes an initialization reset transistor and an anode reset transistor. The reset signal line includes an initialization reset signal line and an anode reset signal line. The pixel circuit further includes a driving transistor; the initialization reset transistor is electrically connected between the initialization reset signal line and a gate electrode of the driving transistor; the anode reset transistor is electrically connected between the anode reset signal line and the light emitting element. The auxiliary connection line is multiplexed as the initialization reset signal line and / or the anode reset signal line.

48. The display panel of claim 46, further comprising a light emitting element. The reset transistor includes an initialization reset transistor, an anode reset transistor and a bias reset transistor. The reset signal line includes an initialization reset signal line, an anode reset signal line and a bias reset signal line. The pixel circuit further includes a driving transistor; the initialization reset transistor is electrically connected between the initialization reset signal line and a gate electrode of the driving transistor; the anode reset transistor is electrically connected between the anode reset signal line and the light emitting element; the bias reset transistor is electrically connected between the bias reset signal line and a first electrode and / or a second electrode of the driving transistor. ​ The auxiliary connection line is multiplexed as at least one of the initial reset signal line, the anode reset signal line and the bias reset signal line.

49. The display panel of claim 34, wherein, The plurality of data signal lines comprises a first data signal line, the first data signal line is provided with a first trace part corresponding thereto; the control end of the multiplexing switch connected with the first data signal line and the control end of the multiplexing switch connected with the first trace part corresponding thereto of the first data signal line and the first trace part corresponding thereto are connected with the same switch control signal; the distance between the first data signal line and the first trace part corresponding thereto in the second direction is less than the distance between the first data signal line and any other first trace part in the second direction, and is less than the distance between the first data signal line and any other data signal line in the second direction; The display panel further comprises a plurality of data signal line groups, each data signal line group comprises a plurality of data signal lines, and the plurality of data signal lines in the same data signal line group are electrically connected with the output ends of a plurality of multiplexing switches in the same multiplexing unit; The first trace part is located in the data signal line group where the first data signal line corresponding thereto is located.

50. The display panel of claim 34, wherein, The plurality of data signal lines comprises a first data signal line, the first data signal line is provided with a first trace part corresponding thereto; the control end of the multiplexing switch connected with the first data signal line and the control end of the multiplexing switch connected with the first trace part corresponding thereto of the first data signal line and the first trace part corresponding thereto are connected with the same switch control signal; the distance between the first data signal line and the first trace part corresponding thereto in the second direction is less than the distance between the first data signal line and any other first trace part in the second direction, and is less than the distance between the first data signal line and any other data signal line in the second direction; The display panel further comprises a plurality of data signal line groups, each data signal line group comprises a plurality of data signal lines, and the plurality of data signal lines in the same data signal line group are electrically connected with the output ends of a plurality of multiplexing switches in the same multiplexing unit; The first trace part is located out of the data signal line group where the first data signal line corresponding thereto is located.

51. The display panel of claim 34, further comprising a pixel circuit; The pixel circuit comprises at least one first type transistor and at least one second type transistor, the first type transistor comprises a first active layer, and the second type transistor comprises a second active layer; The first active layer comprises silicon, and the second active layer comprises oxide.

52. The display panel of claim 51, wherein, The pixel circuit further comprises a storage capacitor, the storage capacitor comprises a first plate and a second plate arranged oppositely, and the second plate is located on the side of the first plate away from the first active layer. The second type transistor further comprises a top gate located on a side of the second active layer away from the first active layer; The display panel further comprises a first semiconductor layer, a first metal layer, a second metal layer, a second semiconductor layer, a third metal layer, a fourth metal layer, and a fifth metal layer; The first active layer is located on the first semiconductor layer, the first electrode plate is located on the first metal layer, the second electrode plate is located on the second metal layer, the second active layer is located on the second semiconductor layer, the top gate is located on the third metal layer, the fourth metal layer is located on a side of the third metal layer away from the first active layer, and the fifth metal layer is located on a side of the fourth metal layer away from the first active layer. The data signal line and the first wiring branch are arranged in the same layer and are both located on the fifth metal layer.

53. The display panel of claim 51, wherein, The pixel circuit further comprises a storage capacitor comprising a first electrode plate and a second electrode plate arranged oppositely, the second electrode plate being located on a side of the first electrode plate away from the first active layer; The second type transistor further comprises a top gate located on a side of the second active layer away from the first active layer; The display panel further comprises a first semiconductor layer, a first metal layer, a second metal layer, a second semiconductor layer, a third metal layer, a fourth metal layer, a fifth metal layer, and a sixth metal layer; The first active layer is located on the first semiconductor layer, the first electrode plate is located on the first metal layer, the second electrode plate is located on the second metal layer, the second active layer is located on the second semiconductor layer, the top gate is located on the third metal layer, the fourth metal layer is located on a side of the third metal layer away from the first active layer, the fifth metal layer is located on a side of the fourth metal layer away from the first active layer, and the sixth metal layer is located on a side of the fifth metal layer away from the first active layer. The data signal line and the first wiring branch are arranged in the same layer and are both located on the sixth metal layer.

54. The display panel of claim 34, wherein, The multiplexing unit comprises a plurality of first multiplexing units and a plurality of second multiplexing units, the output end of the multiplexing switch in the first multiplexing unit is electrically connected with the data signal line, and the output end of the multiplexing switch in the second multiplexing unit is electrically connected with the first wiring branch; In the second direction, the second multiplexing unit is arranged between two adjacent first multiplexing units.

55. The display panel of claim 34, further comprising a fan-out area, the fan-out area comprising a plurality of fan-out wirings; The fan-out area is located on a side of the multiplexing unit arrangement area close to the display area, and the data signal line or the first wiring branch is electrically connected with the output end of the multiplexing switch through the fan-out wiring.

56. The display panel of claim 34, further comprising a fan-out area, the fan-out area comprising a plurality of fan-out wirings; The fan-out area is located on a side of the multiplexing unit arrangement area away from the display area, and the input end of the multiplexing switch is electrically connected with the data signal output terminal through the fan-out wiring.

57. The display panel of claim 55 or 56, wherein, The fan-out wires include first fan-out wires and second fan-out wires arranged alternately in the second direction; The first fan-out wires and the second fan-out wires are arranged in different layers.

58. The display panel of claim 34, wherein, The same multi-branch distribution unit includes at least a first multi-branch distribution switch and a second multi-branch distribution switch; The at least two switch control lines include at least a first switch control line and a second switch control line; The control ends of the plurality of first multi-branch distribution switches are electrically connected to the first switch control line, and the control ends of the plurality of second multi-branch distribution switches are electrically connected to the second switch control line.

59. The display panel of claim 34, wherein, The same multi-branch distribution unit includes at least a first multi-branch distribution switch and a second multi-branch distribution switch; The at least two switch control lines include at least a first switch control line, a second switch control line, a third switch control line, and a fourth switch control line, the first switch control line and the third switch control line are electrically connected to the same switch control signal output end, and the second switch control line and the fourth switch control line are electrically connected to the same switch control signal output end; The control ends of part of the first multi-branch distribution switches are electrically connected to the first switch control line, and the control ends of part of the first multi-branch distribution switches are electrically connected to the third switch control line; The control ends of part of the second multi-branch distribution switches are electrically connected to the second switch control line, and the control ends of part of the second multi-branch distribution switches are electrically connected to the fourth switch control line.

60. The display panel of claim 59, wherein, The first switch control line, the second switch control line, the third switch control line, and the fourth switch control line are arranged in the first direction in sequence.

61. The display panel of claim 35, further comprising a plurality of connection structures, the connection structures comprising first connection structures and second connection structures; One end of the first connection structure is electrically connected to the output end of the multi-branch distribution switch, the other end is electrically connected to the data signal line, and the first connection structure is arranged in a different layer from the data signal line; One end of the second connection structure is electrically connected to the output end of the multi-branch distribution switch, the other end is electrically connected to the first wire part, and the second connection structure is arranged in a different layer from the first wire part.

62. The display panel of claim 61, wherein, The first wire part is located in the data signal line group in which the first data signal line corresponding to the first wire part is located; In the thickness direction of the display panel, the first connection structure electrically connected to the first data signal line and the first wire part corresponding to the first data signal line overlap.

63. The display panel of claim 61, wherein, The first wire part is located outside the data signal line group in which the first data signal line corresponding to the first wire part is located; In the thickness direction of the display panel, the first connection structure electrically connected to the first data signal line and the first wire part corresponding to the first data signal line do not overlap.

64. The display panel of claim 34, further comprising a power signal bus located in the non-display area; In the thickness direction of the display panel, the power signal bus overlaps the multi-branch distribution unit.

65. The display panel of claim 34, further comprising a light emitting element; The light emitting elements include a first color light emitting element, a second color light emitting element, a third color light emitting element, and a fourth color light emitting element, the first color light emitting element, the second color light emitting element, the third color light emitting element, and the fourth color light emitting element being one or more of a red light emitting element, a blue light emitting element, a green light emitting element, and a white light emitting element; A plurality of the first color light emitting elements and the second color light emitting elements form a first virtual quadrilateral, the first color light emitting elements being at first vertices of the first virtual quadrilateral, the second color light emitting elements being at second vertices of the first virtual quadrilateral, the first vertices and the second vertices being alternately and spaced apart, and the third color light emitting elements or the fourth color light emitting elements being inside the first virtual quadrilateral; A plurality of the third color light emitting elements and / or the fourth color light emitting elements form a second virtual quadrilateral, the plurality of the third color light emitting elements and / or the fourth color light emitting elements being at vertices of the second virtual quadrilateral respectively, and the first color light emitting elements or the second color light emitting elements being inside the second virtual quadrilateral.

66. A display device comprising the display panel of any one of claims 1-65.

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