Display panel and display apparatus

Abstract

Embodiments of the present disclosure disclose a display panel and a display apparatus. The display panel comprises a first display area, wherein the first display area comprises a plurality of light-through holes, and projections of the light-through holes in a thickness direction of the display panel do not overlap with projections of pixel circuits and signal lines in the thickness direction, respectively; a plurality of pixel circuits sequentially arranged in a first direction form pixel circuit groups, and the plurality of pixel circuit groups are sequentially arranged in a second direction; at least a portion of the light-through holes is configured such that: one first sub-data connection trace is provided between one side of the light-through holes in the second direction and an adjacent pixel circuit group; and at least a portion of the light-through holes is configured such that: a first sub-voltage regulation signal line is provided between one side of the light-through holes in the second direction and an adjacent pixel circuit group, which solves the problems of limited space and routing challenges when display panels with fingerprint recognition or ambient light detection integrate FIAA technology and mesh technology. This enables fingerprint recognition or ambient light detection functionality in the display panel, while reducing the area of fan-out regions, and improving display uniformity.

Description

Display panel and display device

[0001] The present application claims priority to the Chinese patent application No. 202411259270.4, filed on September 9, 2024, and entitled "Display panel and display device", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] Embodiments of the present application relate to the technical field of display, and in particular, to a display panel and a display device. BACKGROUND

[0003] With the development of display technology, users have higher and higher requirements for the functional diversification of display products. For example, functions such as fingerprint recognition and ambient light recognition have become essential functions of display products. However, when integrating sensing units with these functions inside display products, the specific area of the display panel needs to have a certain light transmittance. In order to better meet the needs of the light sensing function, the display panel can be adjusted, for example, part of the wiring is adjusted, so as to improve the overall effect of the display panel.

[0004] SUMMARY

[0005] Therefore, embodiments of the present application provide a display panel and a display device to solve the problem of limited space and high wiring difficulty when integrating FIAA technology and mesh technology in a display panel with fingerprint recognition or ambient light detection.

[0006] In a first aspect, embodiments of the present application provide a display panel, comprising a pixel circuit and a signal line.

[0007] The pixel circuit comprises a data writing transistor and a voltage adjusting transistor; the signal line comprises a data signal line and a voltage adjusting signal line, the data signal line is electrically connected with the first electrode of the data writing transistor, and the voltage adjusting signal line is electrically connected with the first electrode of the voltage adjusting transistor.

[0008] A plurality of data signal lines extend along a first direction and are arranged along a second direction, and the first direction and the second direction intersect.

[0009] The display panel further comprises a display area and a fan-out area located on one side of the display area; the display area comprises a first display area and a second display area, and the second display area is located on at least one side of the first display area.

[0010] The fan-out region comprises a plurality of fan-out wires, the first display region and the second display region each comprise a plurality of data signal lines; the data signal lines are connected with the fan-out wires; wherein the data signal lines of the second display region are connected with the fan-out wires through data connection wires located in the first display region;

[0011] The data connection wires comprise first sub-data connection wires, a plurality of the first sub-data connection wires extend along the first direction and are arranged along the second direction; the voltage adjustment signal lines comprise first sub-voltage adjustment signal lines, a plurality of the first sub-voltage adjustment signal lines extend along the first direction and are arranged along the second direction; wherein the first sub-voltage adjustment signal lines, the first sub-data connection wires and the data signal lines are arranged on the same layer;

[0012] The first display region further comprises a plurality of light transmission holes, projections of the light transmission holes and the pixel circuits and the signal lines along the display panel thickness direction do not overlap, respectively;

[0013] A plurality of pixel circuits arranged along the first direction in sequence form a pixel circuit group, and a plurality of the pixel circuit groups are arranged along the second direction in sequence;

[0014] At least part of the light transmission holes satisfy that a first sub-data connection wire is arranged between one side thereof and an adjacent pixel circuit group in the second direction;

[0015] At least part of the light transmission holes satisfy that a first sub-voltage adjustment signal line is arranged between one side thereof and an adjacent pixel circuit group in the second direction.

[0016] In a second aspect, an embodiment of the present application provides a display device comprising the display panel as any one of the embodiments of the present application.

[0017] In the technical solution of the embodiment of the present application, the first display area is provided with a plurality of light transmission holes, projections of the light transmission holes along the thickness direction of the display panel do not overlap with projections of the pixel circuit and the signal line along the thickness direction of the display panel respectively, a plurality of pixel circuits arranged in the first direction in sequence form a pixel circuit group, and a plurality of pixel circuit groups are arranged in the second direction in sequence; at least part of the light transmission holes satisfy that a first sub-data connection wire is arranged between one side in the second direction and an adjacent pixel circuit group; at least part of the light transmission holes satisfy that a first sub-voltage adjustment signal line is arranged between one side in the second direction and an adjacent pixel circuit group, thereby solving the problem of high wiring difficulty due to limited space when the display panel integrating the FIAA technology and the mesh technology has the fingerprint recognition or the ambient light detection function, reducing the number of fan-out wires of the fan-out area FANOUT, reducing the area of the fan-out area FANOUT, forming a voltage adjustment signal line network, reducing the attenuation of the voltage adjustment signal when transmitted on the signal line, ensuring that each pixel circuit receives the same voltage adjustment, keeping the driving process of each pixel circuit consistent, improving the display uniformity of the display panel, enriching the function of the display panel, and improving the comprehensive performance of the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0019] FIG. 1 is a structural schematic diagram of a display panel in the related art;

[0020] FIG. 2 is a structural schematic diagram of another display panel in the related art;

[0021] FIG. 3 is a structural schematic diagram of a display panel provided by an embodiment of the present application;

[0022] FIG. 4 is a partial enlarged schematic diagram of the display panel shown in FIG. 3;

[0023] FIG. 5 is a partial cross-sectional structural schematic diagram of the display panel shown in FIG. 4;

[0024] FIG. 6 is a structural schematic diagram of a pixel circuit in the display panel shown in FIG. 3;

[0025] FIG. 7 is a driving timing diagram of the pixel circuit shown in FIG. 6;

[0026] FIG. 8 is a partial enlarged schematic diagram of another display panel provided by an embodiment of the present application;

[0027] FIG. 9 is a schematic diagram of a partial cross-sectional structure of the display panel shown in FIG. 8;

[0028] FIG. 10 is a schematic diagram of a spatial layout of data connection wires and voltage adjustment signal lines in another display panel according to an embodiment of the present application;

[0029] FIG. 11 is a partial enlarged physical diagram of an M3 metal layer in another display panel according to an embodiment of the present application;

[0030] FIGS. 12-17 are partial enlarged physical diagrams of MG, IGZO, MC, M1 and LTPS layers in another display panel according to an embodiment of the present application, respectively;

[0031] FIG. 18 is a schematic diagram of a cross-sectional structure of another display panel according to an embodiment of the present application;

[0032] FIG. 19 is a partial enlarged schematic diagram of yet another display panel according to an embodiment of the present application;

[0033] FIG. 20 is a partial enlarged schematic diagram of yet another display panel according to an embodiment of the present application;

[0034] FIG. 21 is a partial enlarged schematic diagram of yet another display panel according to an embodiment of the present application;

[0035] FIG. 22 is a schematic diagram of a cross-sectional structure of yet another display panel according to an embodiment of the present application;

[0036] FIG. 23 is a top view of yet another display panel according to an embodiment of the present application;

[0037] FIG. 24 is a schematic diagram of a structure of a display device according to an embodiment of the present application. DETAILED DESCRIPTION

[0038] The present application will be further described below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are intended to be merely illustrative of the present application and not in limitation thereof. It should also be noted that, for the purpose of description, only the parts related to the present application are shown in the drawings rather than all the parts.

[0039] The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. It is further noted that the use of the terms "first", "second", etc. do not imply any order or precedence in terms of importance, but rather are used to distinguish one from another. In addition, the use of the terms "a" or "an" are employed to describe at least one of an element; thus, by way of example, "a" can be construed in the context as "one or more" unless otherwise stated.

[0040] The term "include," and derivations thereof, is used im- elastically and is open-ended and means "including but not limited to." The term "based on" means "based, at least in part, on." The term "one embodiment" means "at least one embodiment."

[0041] It should be noted that the terms "first", "second", etc. are used herein only to describe corresponding content, and are not intended to limit the order or interdependence.

[0042] It should be noted that the modification of "one" or "more" in the present application is illustrative and not restrictive, and those skilled in the art should understand that unless otherwise explicitly stated in the context, it should be understood as "one or more".

[0043] With the progress of display products, the demand for narrow frame or even frameless is more and more urgent. Because the lower frame circuit of the display panel screen body has many traces, it will occupy a large space of the lower frame. At present, the FIAA (Fanout in AA, fanout traces in the display area) technology is generally used to design part of the fanout traces in the display area to reduce the space of the lower frame. FIG. 1 is a structural schematic diagram of a display panel in the related art. Referring to FIG. 1, in the related art, the display area AA of the display panel is provided with FIAA traces 23' to provide data signals data to the data signal lines 21'. Among them, the FIAA traces 23' can be generally divided into horizontal FIAA traces 2302' and vertical FIAA traces 2301'. The vertical FIAA traces 2301' are arranged between the normal data signal lines 21' and extend in parallel with the data signal lines 21'. The horizontal FIAA traces 2302' are responsible for crossing the data signal lines 21', connecting the vertical FIAA traces 2301' with the target data signal lines 21', and providing data signals data to the target data signal lines 21'. In addition, the horizontal FIAA traces 2302' and the vertical FIAA traces 2301' are located in different film layers, so as to ensure the insulation between the horizontal FIAA traces 2302' and the data signal lines 21' crossed thereby.

[0044] FIG. 2 is a structural schematic diagram of another display panel in the related art. Referring to FIG. 2, in the related art, when the display panel is provided with functions such as fingerprint recognition and ambient light recognition, a photosensitive unit 2' is arranged on the back of the display panel 1' to collect fingerprint images or ambient light. The corresponding area of the display panel 1' where the photosensitive unit 2' is arranged needs to ensure a certain light transmittance. Generally, a plurality of light transmission holes 30' are arranged in this area, and the photosensitive unit is arranged below the light transmission holes 30'. The photosensitive unit 2' can be a structure with a size corresponding to that of the light transmission holes 30', which collects images of each light transmission hole 30' one by one and then performs image splicing in the back end; or the photosensitive unit 2' can be a structure with a size capable of covering all the light transmission holes 30', which synchronously obtains light transmitted by each light transmission hole 30'. It can be understood that the arrangement of the light transmission holes 30' in a specific area needs to ensure that the area still has normal display function, that is, the arrangement of the corresponding pixel circuits driving the light emitting units in this area needs to be more compact.

[0045] As can be seen from the above, when the display panel integrated with functions such as fingerprint recognition and ambient light recognition adopts the FIAA technology, for the area provided with light transmission holes, the area is limited, which will inevitably lead to a substantial increase in the arrangement difficulty of the pixel circuits and signal lines, and it is difficult to achieve a high light transmission hole aperture ratio.

[0046] To solve the above problems, the embodiment of the present application provides a display panel. FIG. 3 is a structural schematic diagram of a display panel provided by the embodiment of the present application, FIG. 4 is a partial enlarged schematic diagram of the display panel shown in FIG. 3, FIG. 5 is a partial cross-sectional structural schematic diagram of the display panel shown in FIG. 4, FIG. 6 is a structural schematic diagram of a pixel circuit in the display panel shown in FIG. 3, and FIG. 7 is a driving timing diagram of the pixel circuit shown in FIG. 6. Referring to FIGS. 3-7, the display panel comprises a pixel circuit 10 and a signal line 20; the pixel circuit 10 comprises a data writing transistor 11 and a voltage adjusting transistor 12; the signal line 20 comprises a data signal line 21 and a voltage adjusting signal line 22, the data signal line 21 is electrically connected with a first electrode of the data writing transistor 11, and the voltage adjusting signal line 12 is electrically connected with a first electrode of the voltage adjusting transistor 22; a plurality of data signal lines 21 extend along a first direction X and are arranged along a second direction Y, and the first direction X and the second direction Y intersect.

[0047] The display panel further comprises a display area AA and a fan-out area FANOUT located at one side of the display area AA; the display area comprises a first display area AA1 and a second display area AA2, and the second display area AA2 is located at least one side of the first display area AA1; the fan-out area FANOUT comprises a plurality of fan-out wires 24; the first display area AA1 and the second display area AA2 both comprise a plurality of data signal lines 21; the data signal line 21 is connected with the fan-out wire 24; wherein the data signal line 21 of the second display area AA2 is connected with the fan-out wire 24 through a data connection wire 23 located in the first display area AA1.

[0048] The data connection wire 23 comprises a first sub-data connection wire 2301, and a plurality of first sub-data connection wires 2301 extend along the first direction X and are arranged along the second direction Y; the voltage adjusting signal line 22 comprises a first sub-voltage adjusting signal line 2201, and a plurality of first sub-voltage adjusting signal lines 2201 extend along the first direction X and are arranged along the second direction Y; wherein the first sub-voltage adjusting signal line 2201, the first sub-data connection wire 2301 and the data signal line 21 are arranged on the same layer.

[0049] The first display area AA1 further comprises a plurality of light transmission holes 30, projections of the light transmission holes 30 along a display panel thickness direction Z do not overlap with projections of the pixel circuit 10 and the signal line 20 along the display panel thickness direction Z respectively; a plurality of pixel circuits 10 arranged in sequence along the first direction X form a pixel circuit group 100, and a plurality of pixel circuit groups 100 are arranged in sequence along the second direction Y.

[0050] At least some of the light transmission holes 30 satisfy: one side in the second direction Y is provided with a first sub-data connection wire 2301 between adjacent pixel circuit groups 100; at least some of the light transmission holes 30 satisfy: one side in the second direction Y is provided with a first sub-voltage adjustment signal line 2201 between adjacent pixel circuit groups 100.

[0051] As shown in FIG. 1, the display panel 1 includes a pixel circuit 10, which is electrically connected with a light emitting element 40 in the display panel 1, to drive the light emitting element 40 and ensure the light emitting display of the light emitting element 40. Further, the display panel 1 also includes a signal line 20 configured to provide a voltage signal and / or a current signal to the pixel circuit 10, so as to drive the light emitting element 40 by the pixel circuit 10. Taking the “8T1C” pixel circuit shown in FIG. 6 as an example, the process of receiving the driving signal of the signal line 20 by the pixel circuit 10 and driving the light emitting element 40 to emit light is introduced as follows:

[0052] Referring to FIGS. 6 and 7, first, in the “8T1C” pixel circuit, the voltage adjustment transistor 12 can include a first voltage adjustment transistor 121, a second voltage adjustment transistor 122 and a third voltage adjustment transistor 123. The first voltage adjustment transistor 121 can also be referred to as a gate reset transistor M4, the second voltage adjustment transistor 122 can also be referred to as an anode reset transistor M7, and the third voltage adjustment transistor 123 can also be referred to as a bias adjustment transistor M8. In addition to the data writing transistor 11 and the voltage adjustment transistor 12, the pixel circuit also includes a driving transistor 13 (also shown as M3 in the figure), a threshold compensation transistor 14 (also shown as M5 in the figure), a first light emitting control transistor 151 (also shown as M1 in the figure), a second light emitting control transistor 152 (also shown as M6 in the figure) and a storage capacitor 16 (also shown as Cst in the figure). The connection relationship of the above-mentioned elements is shown in the figure, which is not described here. In addition, it should be noted that the channel type of each transistor can be N-type or P-type. For example, referring to FIG. 6, the first voltage adjustment transistor 121 and the threshold compensation transistor 14 can be N-type channel transistors, and the remaining transistors can be P-type channel transistors.

[0053] The pixel circuit 10 comprises a gate reset stage ta, a data write stage tb and an emitting stage tc. In the gate reset stage ta, the gate of the gate reset transistor 121 receives a scanning signal S1N which is a high level pulse signal at this time, the gate reset transistor 121 is turned on, and the gate reset signal Vref1 is input to the first node N1, i.e. the gate of the driving transistor 13, so as to reset the gate of the driving transistor 13. In the data write stage tb, the gate of the data write transistor 11 receives a scanning signal SP which is a low level pulse signal at this time, the data write transistor 11 is turned on; at the same time, the gate of the threshold compensation transistor 14 receives a scanning signal S2N which is a high level pulse signal at this time, the threshold compensation transistor 14 is turned on. The data signal Vdata is input to the first node N1 through the data write transistor 11, the driving transistor 13 and the threshold compensation transistor 14, and is stored by the storage module 16. In the emitting stage tc, the gates of the first emitting control transistor 151 and the second emitting control transistor 152 both receive an emitting control signal Emit which is a low level pulse at this time, the first emitting control transistor 151 and the second emitting control transistor 152 are turned on, and the driving transistor 13 provides a corresponding driving current to the light emitting element 40 according to the data signal Vdata stored in the gate, so that the light emitting element 40 emits light with a target brightness.

[0054] Since there is the emitting stage tc in each display frame, the driving transistor 13 in the pixel circuit 10 is always in a forward bias state, which causes a certain degree of characteristic curve drift of the driving transistor 13, resulting in a change in the driving current generated by the pixel circuit 10 and a deviation in the emitting brightness of the light emitting element 40. In view of this, the pixel circuit 10 is further provided with a bias stage td, in which the third voltage adjustment transistor 123 is turned on, the bias signal end DVH is configured to receive a bias signal DVH, the bias signal DVH is written to the first pole of the driving transistor 13, i.e. the second node N2, through the third voltage adjustment transistor 123, and the driving transistor 13 is adjusted by the bias signal DVH to compensate for the characteristic curve drift caused by the forward bias. In order to achieve sufficient bias adjustment effect, as shown in FIG. 7, a bias stage td is arranged before and after the data write stage tb, which is an embodiment of the present application, and a person skilled in the art can also choose to arrange the bias stage td only before or after, which is not limited here.

[0055] As can be seen from the driving process and working principle of the pixel circuit, the pixel circuit 10 needs to write the data signal Vdata in the process of driving the light emitting element 40 to emit light, which is provided by the data signal line 21. For the display panel with narrow frame design, when the data signal is directly provided to the data signal line 21 through the fan-out lines 24 of the fan-out area FANOUT, the number of the fan-out lines 24 needs to be consistent with the number of the data signal lines 21, which leads to the area of the fan-out area FANOUT being too large. In view of this, with reference to FIGS. 1 and 3, the display panel of the embodiment of the present application adopts the FIAA technology, that is, the data connection lines 23 are arranged in the first display area AA1, and the data signal is provided to the data signal line 21 in the edge area through the data connection lines 23, so as to avoid the fan-out area FANOUT needing to be provided with too many fan-out lines 24 in the edge, thereby being able to leave more horizontal space and facilitating the design of reducing the area of the fan-out area. As shown in FIG. 3, the number of the data connection lines 23 is only an example, and a person skilled in the art can set it according to actual needs, which is not limited herein.

[0056] With continuous reference to FIG. 3, the data signal line 21 located at the edge of the second display area AA2 is connected with the data connection line 23 arranged in the first display area AA1, and the data signal is provided to the data signal line 21 through the data connection line 23, so as to drive the pixel circuit 10 connected with the data signal line 21 to work normally. The first direction X can be understood as the column direction, and the second direction Y can be understood as the row direction. Each data connection line 23 includes the first sub-data connection line 2301 extending along the column direction and the second sub-data connection line 2302 extending along the row direction, and the first sub-data connection line 2301 and the second sub-data connection line 2302 are connected. With reference to FIGS. 4 and 5, for the first sub-data connection line 2301, it is arranged in the same layer as the data signal line 21 in the embodiment of the present application, and since the data signal line 21 also extends along the column direction, the first sub-data connection line 2301 and the data signal line 21 are substantially parallel extending lines.

[0057] As can be known from the driving process and working principle of the pixel circuit, the pixel circuit 10 also needs to perform voltage adjustment of corresponding nodes in the process of driving the light emitting element 40 to emit light, which can specifically include: the gate reset signal Vref1 adjusts the gate voltage of the driving transistor 13, the anode reset signal Vref2 adjusts the anode voltage of the light emitting element 40, and the bias adjustment signal DVH adjusts the voltage of the source and drain of the driving transistor 13. In other words, the “8T1C” pixel circuit in the embodiment example can include three voltage adjustment signals, and three voltage adjustment signal lines 22 need to be provided, that is, the first voltage adjustment signal line 221 corresponds to the gate reset signal line Vref1, the second voltage adjustment signal line 222 corresponds to the anode reset signal line Vref2, and the third voltage adjustment signal line 223 corresponds to the bias adjustment signal line DVH. Of course, the node voltage adjustment here is for the “8T1C” pixel circuit as an example, and in other embodiments of the present application, other types of pixel circuits can also be designed to provide voltage adjustment of the corresponding nodes, which is not limited here.

[0058] In addition, with reference to FIG. 3, it also needs to be explained that, since the voltage adjustment of the nodes of the pixel circuit generally does not need to be distinguished from the pixel circuit, that is, the adjustment of the node voltage is a unified operation on all pixel circuits, in order to avoid the attenuation of the voltage adjustment signal, the voltage adjustment signal line 22 adopts a mesh design, that is, the voltage adjustment signal line 22 is designed in a mesh structure, and the voltage adjustment signal line 22 can include a first sub-voltage adjustment signal line 2201 and a second sub-voltage adjustment signal line 2202, wherein the first sub-voltage adjustment signal line 2201 extends along the first direction X, that is, the column direction, and the second sub-voltage adjustment signal line 2202 extends along the second direction Y, that is, the row direction, the first sub-voltage adjustment signal line 2201 is electrically connected with each second sub-voltage adjustment signal line 2202, and the second sub-voltage adjustment signal line 2202 is electrically connected with each first sub-voltage adjustment signal line 2201, thereby forming a mesh structure. As shown in FIG. 3, only the mesh design of the region where the light through hole 30 is located in the column direction is exemplified, and the voltage adjustment signal line 22 is in a mesh structure, and it can be understood that the mesh structure here actually covers the entire display panel.

[0059] In summary, since the data signal line 21, the first sub-voltage adjustment signal line 2201 and the first sub-data connection wire 2301 all extend along the first direction X, that is, the column direction, the embodiment of the present application is provided to be parallelly extended in the same layer, and the same layer is provided to be prepared in the same process step by using the same process, thereby saving the preparation cost.

[0060] In addition, the display panel of the embodiment of the present application integrates the functions of fingerprint identification and ambient light detection. Specifically, a plurality of light transmission holes 30 are arranged in the first display area AA1 of the display panel, in which the data connection traces 23 are arranged. The projections of the light transmission holes along the thickness direction Z of the display panel do not overlap with the projections of the pixel circuits and the signal lines along the thickness direction Z of the display panel, respectively. Thus, a light sensing unit (not shown in the figure) can be added to the back of the display panel. The light sensing unit can collect fingerprint images or ambient light through the plurality of light transmission holes 30, so as to realize the functions of fingerprint identification and ambient light detection. Specifically, the light transmission holes 30, the data signal lines 21, the voltage adjustment signal lines 22 and the data connection traces 23 are designed in the first display area AA1 at the same time. The data signal lines 21, the first sub-voltage adjustment signal lines 2201 and the first sub-data connection traces 2301 are arranged on the same layer.

[0061] To this end, the embodiment of the present application is essentially that a plurality of pixel circuits 10 arranged along the first direction X, i.e. the column direction, form a pixel circuit group 100. The light transmission holes 30 are arranged between two adjacent pixel circuit groups 100. The first sub-data connection traces 2301 or the first sub-voltage adjustment signal lines 2201 are arranged between the pixel circuit group 100 and the light transmission hole 30. Specifically, a first sub-data connection trace 2301 is arranged between at least part of the light transmission holes 30 and the adjacent pixel circuit group 100. A first sub-voltage adjustment signal line 2201 is arranged between at least part of the light transmission holes 30 and the adjacent pixel circuit group 100. As shown in FIG. 4, a first sub-data connection trace 2301 is arranged between the light transmission holes 30 and the left pixel circuit group 100. A first sub-data connection trace 2301 is arranged between the light transmission holes 30 and the right pixel circuit group 100. Thus, the data signal lines 21 of the second display area AA2 can be provided with data signals through the first sub-data connection traces 2301 of the first display area AA1, without the need to arrange fan-out traces in the fan-out area FANOUT corresponding to the data signal lines 21 of the second display area AA2. The number of fan-out traces in the fan-out area FANOUT is reduced, so as to facilitate the reduction of the area of the fan-out area FANOUT. Meanwhile, the first sub-voltage adjustment signal lines 2201 arranged between at least part of the light transmission holes 30 and the pixel circuit group 100 are connected with the transversely extended voltage adjustment signal line part, i.e. the second sub-voltage adjustment signal line 2202, to form a voltage adjustment signal line network. Thus, the attenuation of the voltage adjustment signal during transmission on the signal line is reduced, the same voltage adjustment is ensured to be received by each pixel circuit, the driving process of each pixel circuit is kept consistent, and the display uniformity of the display panel is improved.

[0062] It should be noted that, as shown in FIG. 4 and FIG. 5, a first sub-data connection wire 2301 and a first sub-voltage adjustment signal line 2201 are respectively arranged between the left and right sides of the light transmission hole 30 and the respective adjacent pixel circuit groups 100, which is only one optional embodiment of the present application, and in other embodiments, a first sub-data connection wire 2301 can also be arranged between one side, for example, the left side, of the light transmission hole 30 and the pixel circuit group 100 in the row direction of the light transmission hole 30, and the first sub-voltage adjustment signal line 2201 is not arranged on the other side, for example, the right side.

[0063] In the above technical solution, the first display area is provided with a plurality of light transmission holes, the projections of the light transmission holes and the pixel circuits and the signal lines along the thickness direction of the display panel do not overlap; a plurality of pixel circuits arranged in the first direction form a pixel circuit group, and a plurality of pixel circuit groups are arranged in the second direction; at least part of the light transmission holes satisfy that a first sub-data connection wire is arranged between one side and an adjacent pixel circuit group in the second direction; at least part of the light transmission holes satisfy that a first sub-voltage adjustment signal line is arranged between one side and an adjacent pixel circuit group in the second direction, which solves the problem of high wiring difficulty due to limited space when integrating FIAA technology and mesh technology in the display panel with fingerprint recognition or ambient light detection, reduces the number of fan-out wires in the fan-out area FANOUT, which is conducive to reducing the area of the fan-out area FANOUT, forms a voltage adjustment signal line network, thereby reducing the attenuation of the voltage adjustment signal when transmitted on the signal line, ensures that each pixel circuit receives the same voltage adjustment, and makes the driving process of each pixel circuit consistent, which is conducive to improving the display uniformity of the display panel, enriching the functions of the display panel, and improving the comprehensive performance of the display panel.

[0064] With reference to FIG. 3 and FIG. 4, further, at least part of the light transmission holes 30 also satisfy that a data signal line 21 is arranged between the adjacent pixel circuit group 100 on one side in the second direction Y and the first sub-data connection wire 2301; at least part of the light transmission holes 30 also satisfy that a data signal line 21 is arranged between the adjacent pixel circuit group 100 on one side in the second direction Y and the first sub-voltage adjustment signal line 2201.

[0065] Here, the essence is that a data signal line 21 is arranged between the pixel circuit group 100 and the first sub data connection wire 2301 and between the pixel circuit group 100 and the first sub voltage adjustment signal line 2201, as shown in FIG. 4, which can also be understood as that one data signal line 21 is arranged on each side of the pixel circuit group 100, one of which provides data signals to the pixel circuit 10 of the light emitting element 40 of one color, for example, green light emitting element, and the other alternately provides data signals to the pixel circuit 10 of the light emitting element 40 of two colors, for example, red and blue light emitting elements.

[0066] It needs to be supplemented that the data signal line 21 is arranged between the pixel circuit group 100 and the first sub data connection wire 2301 or the first sub voltage adjustment signal line 2201, which is an embodiment of the present application. FIG. 8 is a partial enlarged schematic view of another display panel provided by the embodiment of the present application, FIG. 9 is a partial cross-sectional structure schematic view of the display panel shown in FIG. 8, FIG. 10 is a schematic view of the spatial layout of the data connection wire and the voltage adjustment signal line in another display panel provided by the embodiment of the present application, and FIG. 11 is a partial enlarged actual view of the M3 metal layer in another display panel provided by the embodiment of the present application. With reference to FIGS. 8-11, in other possible embodiments, the first sub data connection wire 2301 or the first sub voltage adjustment signal line 2201 can also be arranged between the data signal line 21 and the pixel circuit group 100, or in other words, the data signal line 21 can be arranged between the through hole 30 and the first sub data connection wire 2301 or the first sub voltage adjustment signal line 2201.

[0067] Continuing to refer to FIGS. 4 and 5, further, the signal line 20 further includes a plurality of positive power supply signal lines 25 extending along the second direction Y and arranged along the first direction X; the positive power supply signal lines 25, the data signal lines 21, the first sub data connection wires 2301 and the first sub voltage adjustment signal lines 2201 are arranged in the same layer, and the positive power supply signal lines 25 are overlapped with the pixel circuit group 100 in the thickness direction Z. The positive power supply signal lines 25 and the through holes 30 are alternately arranged along the second direction Y, and between some of the positive power supply signal lines 25 and the through holes 30, there is one data signal line 21 and one first sub data connection wire 2301, and between some of the positive power supply signal lines 25 and the through holes 30, there is one data signal line 21 and one first sub voltage adjustment signal line 2201.

[0068] As can be seen from the pixel circuit, in the light emitting stage tc, the first light emitting control transistor 151 and the second light emitting control transistor 152 are both turned on, a path is formed between the positive power signal terminal PVDD and the negative power signal terminal PVEE, the driving transistor 13 is responsible for controlling the current of the path, and the light emitting element 40 is controlled by the current to control the light emitting brightness. The positive power signal terminal PVDD is electrically connected with the positive power signal line 25 to receive the positive power signal. The positive power signal line 25 is arranged in the same layer as the data signal line 21, the first sub-data connection wire 2301 and the first sub-voltage adjustment signal line 2201, and extends along the column direction in parallel with the data signal line 21, the first sub-data connection wire 2301 and the first sub-voltage adjustment signal line 2201. In the row direction, the positive power signal line 25 is arranged between the two data signal lines 21 and above the pixel circuit group 100. Therefore, between the positive power signal line 25 and the light transmission hole 30, there is one data signal line 21 or one first sub-data connection wire 2301, or one data signal line 21 or one first sub-voltage adjustment signal line 2201.

[0069] Of course, for the embodiment in which one side of the light transmission hole 30 is provided with one data signal line 21 or one first sub-voltage adjustment signal line 2201 of the pixel circuit group 100, and the other side is not provided with the data signal line 21 and the first sub-voltage adjustment signal line 2201, there may be only one data signal line 21 between the positive power signal line 25 and the light transmission hole 30.

[0070] Continuing to refer to FIG. 3, further, the data connection wire 23 further includes a second sub-data connection wire 2302, a plurality of second sub-data connection wires 2302 extend along the second direction Y and are arranged along the first direction X; the second sub-data connection wire 2302 is arranged in a different layer from the first sub-data connection wire 2301; one end of the second sub-data connection wire 2302 is electrically connected with the first sub-data connection wire 2301 one by one, and the other end of the second sub-data connection wire 2302 extends to the second display area AA2 and is electrically connected with the data signal line 21 one by one.

[0071] The second sub-data connection wire 2302 is a part of the data connection wire extending in the row direction, which is responsible for electrically connecting the part extending in the column direction, i.e., the first sub-data connection wire 2301, with the data signal line 21 in the corresponding second display area AA2, replacing the fan-out wire, to provide the data signal to the data signal line 21. It can be understood that the second sub-data connection wire 2302 extending in the row direction needs to extend from the first display area AA1 to the second display area AA2, which needs to cross a plurality of data signal lines 21. In order to be insulated from the data signal lines 21, the second sub-data connection wire 2302 is arranged in a layer different from the data signal lines 21 and the first sub-data connection wire 2301. The second sub-data connection wire 2302 arranged in the different layer can be electrically connected to the data signal lines 21 and the first sub-data connection wire 2301 through a via hole. It should be noted that the different layers in the embodiment of the present application refer to two conductive layers separated by an insulating layer. If the signal lines of the two conductive layers need to be electrically connected, the two conductive layers can be electrically connected through a via hole.

[0072] With continuous reference to FIGS. 8-11, in an optional embodiment of the present application, the light transmission hole 30 includes a first side and a second side facing away from each other in the second direction Y; part of the first sub-data connection wire 2301 is located on the first side of the light transmission hole 30, and part of the first sub-data connection wire 2301 is located on the second side of the light transmission hole 30. More specifically, in the second direction Y, each first sub-data connection wire 2301 is alternately located on the first side and the second side of the light transmission hole 30.

[0073] As mentioned above, in the first display area AA1 and the second display area AA2, one pixel circuit group 100 is provided with two data signal lines 21 in the embodiment of the present application. As shown in FIGS. 3 and 8, one data signal line 21 is arranged on each side of the pixel circuit group 100. Among the two data signal lines 21, one provides the first data signal Data1 to the pixel circuit 10 corresponding to the green light emitting element, and the other is responsible for providing the second data signal Data2 and the third data signal Data3 to the pixel circuit 10 corresponding to the red and blue light emitting elements, respectively, in time division. In the first display area AA1, the data signal line 21 transmitting the first data signal Data1 is uniformly arranged on the first side (e.g., the left side) of the light transmission hole 30, and the data signal line 21 transmitting the second data signal Data2 and the third data signal Data3 is uniformly arranged on the second side (e.g., the right side) of the light transmission hole 30.

[0074] Based on this, it can be understood that when the data connection wire 23 is arranged in the first display area AA1 to provide the data signal to the data signal line 21 of the second display area AA2, two kinds of data connection wires 23 are also needed, one of which transmits the first data signal Data1 for driving the green light emitting element to emit light, and the other transmits the second data signal Data2 or the third data signal Data3 in time division for driving the red and blue light emitting elements to emit light, respectively. And since in the first display area AA1, one pixel circuit group 100 only corresponds to arrange a longitudinal part of the data connection wire 23, that is, the first sub-data connection wire 2301, by alternately arranging the first sub-data connection wire 2301 on the first side and the second side of the light transmission hole 30 in the second direction Y, that is, the row direction, the first sub-data connection wire 2301 transmitting the first data signal Data1 can be adjacent to the data signal line 21 also transmitting the first data signal Data1 located on the first side of the light transmission hole 30, and the first sub-data connection wire 2301 transmitting the second data signal Data2 and the third data signal Data3 can be adjacent to the data signal line 21 also transmitting the second data signal Data2 and the third data signal Data3 located on the second side of the light transmission hole 30, thereby the data signal line 21 and the first sub-data connection wire 2301 synchronously transmitting the same data signal are adjacent, avoiding that the adjacent data signal line 21 and the first sub-data connection wire 2301 transmit different data signals, which can prevent the signal interference between the signal lines and avoid the coupling effect on another signal line when the signal transmitted on one signal line jumps.

[0075] With continuous reference to FIGS. 3-6, the pixel circuit includes multiple voltage regulating transistors 12, and the voltage regulating signal line 22 electrically connected to the first electrode of the different voltage regulating transistors 12 transmits different voltage regulating signals; each first sub-voltage regulating signal line 2201 in the voltage regulating signal line 22 electrically connected to the first electrode of the different voltage regulating transistors 12 is arranged in the second direction Y in turn and circularly.

[0076] As shown in the above examples, the voltage regulating transistor 12 can include a first voltage regulating transistor 121, a second voltage regulating transistor 122, and a third voltage regulating transistor 123, the first voltage regulating transistor 121 can also be referred to as a gate reset transistor M4, the second voltage regulating transistor 122 can also be referred to as an anode reset transistor M7, and the third voltage regulating transistor 123 can also be referred to as a bias regulating transistor M8. Therefore, the voltage regulating signal lines 22 electrically connected to the first poles of the different voltage regulating transistors 12 are: a first voltage regulating signal line 221 corresponding to a gate reset signal line Vref1; a second voltage regulating signal line 222 corresponding to an anode reset signal line Vref2; and a third voltage regulating signal line 223 corresponding to a bias regulating signal line DVH. The embodiment essentially sets the third voltage regulating signal line 223, the second voltage regulating signal line 222, and each first sub-voltage regulating signal line 2201 in the first voltage regulating signal line 221, which are arranged in the row direction in a fixed order and repeatedly arranged in the row direction.

[0077] Further, with reference to FIGS. 3 and 10, the voltage regulating signal lines 22 further include a plurality of second sub-voltage regulating signal lines 2202 extending along the second direction Y and arranged along the first direction X; the second sub-voltage regulating signal lines 2202 are electrically connected to the first sub-voltage regulating signal lines 2201 and are arranged in different layers from the first sub-voltage regulating signal lines 2201.

[0078] The second sub-voltage regulating signal lines 2202 extending along the row direction are electrically connected to the first sub-voltage regulating signal lines 2201 extending along the column direction, forming a mesh structure, which can reduce the attenuation of the voltage regulating signal. The second sub-voltage regulating signal lines 2202 need to avoid the film layer in which the first sub-voltage regulating signal lines 2201 are arranged due to the need for lateral extension, so the two need to be arranged in different layers and can be electrically connected through a via hole.

[0079] With reference to FIGS. 3 and 6, optionally, the pixel circuit 10 includes a plurality of voltage regulating transistors 12, and the voltage regulating signal lines 22 electrically connected to the first poles of the different voltage regulating transistors 12 transmit different voltage regulating signals; each second sub-voltage regulating signal line 2202 in the voltage regulating signal lines 22 electrically connected to the first poles of the different voltage regulating transistors 12 is arranged in a different layer.

[0080] The different second sub-voltage adjustment signal lines 2202 in the embodiment are arranged in different layers, which means that the second sub-voltage adjustment signal lines 2202 extending in the lateral direction and transmitting different voltage adjustment signals are arranged in different conductive layers, so that when the plurality of second sub-voltage adjustment signal lines 2202 extending in the lateral direction are arranged in the same layer, the arrangement area of the layer in the longitudinal direction is increased, and the arrangement difficulty of the layer is increased.

[0081] Referring to FIGS. 6 and 8-11, specifically, the voltage adjustment transistor 12 includes a first voltage adjustment transistor 121, and the pixel circuit 10 further includes the driving transistor 13; the first electrode of the first voltage adjustment transistor 121 is electrically connected with the gate electrode of the driving transistor 13; the voltage adjustment signal line 22 includes a first voltage adjustment signal line 221; the first voltage adjustment signal line 221 is electrically connected with the second electrode of the first voltage adjustment transistor 121.

[0082] The first voltage adjustment signal line 221 is essentially a gate reset signal line Vref1, and the first voltage adjustment transistor 121 is essentially a gate reset transistor M4, which is responsible for providing the gate reset signal Vref1 to the gate electrode of the driving transistor 13 (here, the signal line and the signal adopt the same mark) to reset the gate electrode of the driving transistor 13.

[0083] Referring to FIGS. 6 and 8-11, specifically, the voltage adjustment transistor 12 includes a second voltage adjustment transistor 122, and the pixel circuit 10 further includes the driving transistor 13; the first electrode of the second voltage adjustment transistor 122 is electrically connected with the second electrode of the driving transistor 13; the voltage adjustment signal line 22 includes a second voltage adjustment signal line 222; the second voltage adjustment signal line 222 is electrically connected with the second electrode of the second voltage adjustment transistor 122.

[0084] The second voltage adjustment signal line 222 is essentially an anode reset signal line Vref2, and the second voltage adjustment transistor 122 is essentially an anode reset transistor M7, which is responsible for providing the anode reset signal Vref2 to the anode of the light emitting element 40 (here, the signal line and the signal adopt the same mark) to reset the anode of the light emitting element 40.

[0085] Referring to FIGS. 6 and 8-11, specifically, the voltage adjustment transistor 12 includes a third voltage adjustment transistor 123, and the pixel circuit 10 further includes the driving transistor 13; the second electrode of the data write transistor 11 and the first electrode of the third voltage adjustment transistor 123 are both electrically connected with the first electrode of the driving transistor 13; the voltage adjustment signal line 22 includes a third voltage adjustment signal line 223; the third voltage adjustment signal line 223 is electrically connected with the second electrode of the third voltage adjustment transistor 123.

[0086] The third voltage adjustment signal line 223 is essentially a bias adjustment signal line DVH, and the third voltage adjustment transistor 123 is essentially a bias adjustment transistor M8, which is responsible for providing a bias signal DVH to the source-drain of the driving transistor 13 (here, the same signal line and signal are represented by the same mark) to form a reverse bias for the driving transistor 13, compensate for the threshold drift caused by the forward bias of the driving transistor 13 in the light-emitting stage tc, and maintain the electrical stability of the driving transistor 13.

[0087] As known from the above, in the embodiment of the present application, the second sub-voltage adjustment signal line 2202, which transmits the laterally extending voltage adjustment signals, can specifically be the second sub-voltage adjustment signal line 2202 of the gate reset signal line Vref1, the anode reset signal line Vref2, and the bias adjustment signal line DVH. The longitudinal wires in the network structure of the three voltage adjustment signal lines 22, i.e., the first sub-voltage adjustment signal line 2201, are in the same layer as the data signal line 21 and the positive power voltage signal line 25, while the laterally extending wires, i.e., the second sub-voltage adjustment signal line 2202, are arranged in other conductive layers.

[0088] FIG. 11 is a partial enlarged physical diagram of another metal layer of a display panel M2 provided by the embodiment of the present application. With reference to FIGS. 3 and 8-11, the data connection wires 23 can also optionally include second sub-data connection wires 2302, and the second sub-data connection wires 2302 extend along the second direction Y and are arranged along the first direction X; the second sub-data connection wires 2302 are arranged in different layers from the first sub-data connection wires 2301; one end of each of the second sub-data connection wires 2302 is electrically connected to one of the first sub-data connection wires 2301, and the other end of each of the second sub-data connection wires 2302 extends to the second display area AA2 and is electrically connected to one of the data signal lines 21; the second sub-data connection wires 2302 are arranged in different layers from the second sub-voltage adjustment signal lines 2202.

[0089] Similarly, in the embodiment, the second sub-data connection wires 2302 and the second sub-voltage adjustment signal lines 2202 are arranged in different conductive layers, which can avoid the increase in the arrangement area of the layer in the longitudinal direction when the second sub-data connection wires 2302 and the second sub-voltage adjustment signal lines 2202 are arranged in the same layer, and thus increase the arrangement difficulty of the layer.

[0090] Fig. 12-17 are partial enlarged physical diagrams of another display panel MG, IGZO, MC, M1 and LTPS layer provided by the embodiment of the present application, referring to Fig. 3 and Fig. 8-17, further, the vertical projection of at least two wires in the second sub-data connection wire 2302 and each second sub-voltage adjustment signal line 2202 electrically connected with the first pole of the different voltage adjustment transistor 12 on the thickness direction Z of the display panel at least partially overlaps.

[0091] In this embodiment, the essence is that at least two wires in the transverse part of the data connection wire 23 and the voltage adjustment signal line 22 are arranged to project and overlap, that is, in the projection of the entire pixel circuit, the transverse part wires can be concentrated in the same projection area, which can leave space for other components, signal lines and other circuit structures in the pixel circuit, thereby facilitating the layout of other circuit structures and avoiding interference between circuit structures. At the same time, from the projection, the transverse wires of each layer overlap with each other, which can reduce the length of the pixel circuit in the vertical direction, that is, the area of the pixel circuit can be reduced, which is conducive to improving the resolution of the display panel.

[0092] Fig. 18 is a cross-sectional structure schematic diagram of another display panel provided by the embodiment of the present application, referring to Fig. 10-18, further, the display panel 1 includes a substrate 1000 and a plurality of metal layers 2000 on the substrate 1000 in the thickness direction Z.

[0093] The data signal line 21, the first sub-data connection wire 2301 and the first sub-voltage adjustment signal line 2201 in each voltage adjustment signal line 22 electrically connected with the first pole of the different voltage adjustment transistor 12 are located on the top metal layer 2001, and the top metal layer 2001 is the metal layer 2000 farthest from the substrate 1000.

[0094] The second sub-data connection wire 2302 and the second sub-voltage adjustment signal line 2202 in each voltage adjustment signal line 22 electrically connected with the first pole of the different voltage adjustment transistor 12 are respectively distributed on the middle metal layer 2002 and the bottom metal layer 2003, the middle metal layer 2002 is the metal layer 2000 between the top metal layer 2001 and the bottom metal layer 2003, and the bottom metal layer 2003 is the metal layer 2000 closest to the substrate 1000; at least one middle metal layer 2002 is provided with a switching part 20000.

[0095] The first sub-data connection wire 2301 and the second sub-data connection wire 2302 are spaced apart by at least one intermediate metal layer 2002, and the first sub-data connection wire 2301 and the second sub-data connection wire 2302 are electrically connected through a switching part 20000 on the intermediate metal layer 2002; and / or, the first sub-voltage adjustment signal line 2201 and the second sub-voltage adjustment signal line 2202 of the same voltage adjustment signal line 22 are spaced apart by at least one intermediate metal layer 2002, and the first sub-voltage adjustment signal line 2201 and the second sub-voltage adjustment signal line 2202 are electrically connected through a switching part 20000 on the intermediate metal layer 2002.

[0096] It can be understood that when the first sub-data connection wire 2301 and the second sub-data connection wire 2302 are spaced apart by at least one intermediate metal layer 2002, and when the first sub-voltage adjustment signal line 2201 and the second sub-voltage adjustment signal line 2202 of the same voltage adjustment signal line 22 are spaced apart by at least one intermediate metal layer 2002, direct electrical connection of the signal lines arranged in different layers as described above through a single via will result in limited conductive material in the via due to the limited size of the via, and excessively deep vias will have the problem of poor conduction. In the embodiment, the switching part 20000 is arranged in the intermediate metal layer 2002, which substantially divides the via into multiple parts in the thickness direction Z, and connects two signal lines with a large distance in the thickness direction through multiple vias in the thickness direction, wherein the switching part 20000 serves as an intermediate connection structure to achieve electrical connection of the two signal lines with a large distance in the thickness direction.

[0097] It should be noted that when two signal lines in the thickness direction Z are spaced apart by multiple intermediate metal layers 2002, the switching part 20000 can be arranged in only part of the intermediate metal layers 2002, or the switching part 20000 can be arranged in each intermediate metal layer 2002. Those skilled in the art can select and design according to actual needs, which is not limited here.

[0098] With reference to FIGS. 6 and 10-18, specifically, the display panel 1 includes, in the thickness direction Z, a substrate 1000, a first metal layer 2100, a second metal layer 2200, a third metal layer 2300, a fourth metal layer 2400, and a fifth metal layer 2500 in sequence; the first sub-voltage adjustment signal line 2201, the first sub-data connection wire 2301, and the data signal line 21 are located in the fifth metal layer 2500.

[0099] The voltage adjustment transistor 12 includes a first voltage adjustment transistor 121, a second voltage adjustment transistor 122, and a third voltage adjustment transistor 123, and the pixel circuit 10 further includes a driving transistor 13.

[0100] The first electrode of the first voltage adjusting transistor 121 is electrically connected with the gate electrode of the driving transistor 13, the first electrode of the second voltage adjusting transistor 122 is electrically connected with the second electrode of the driving transistor 13, the second electrode of the data writing transistor 11 and the first electrode of the third voltage adjusting transistor 123 are electrically connected with the first electrode of the driving transistor 13; the voltage adjusting signal line 22 includes the first voltage adjusting signal line 221, the second voltage adjusting signal line 222 and the third voltage adjusting signal line 223.

[0101] The first voltage adjusting signal line 221 is electrically connected with the second electrode of the first voltage adjusting transistor 121, the second voltage adjusting signal line 222 is electrically connected with the second electrode of the second voltage adjusting transistor 122, and the third voltage adjusting signal line 223 is electrically connected with the second electrode of the third voltage adjusting transistor 123.

[0102] The second sub-data connection wire 2302, the second sub-voltage adjusting signal line 2202 in the first voltage adjusting signal line 221, the second sub-voltage adjusting signal line 2202 in the second voltage adjusting signal line 222 and the second sub-voltage adjusting signal line 2202 in the third voltage adjusting signal line 223 are respectively located in one of the first metal layer 2100, the second metal layer 2200, the third metal layer 2300 and the fourth metal layer 2400.

[0103] Specifically, the second sub-voltage adjusting signal line 2202 in the first voltage adjusting signal line 221 is located in the first metal layer 2100, the second sub-voltage adjusting signal line 2202 in the second voltage adjusting signal line 222 is located in the second metal layer 2200, the second sub-voltage adjusting signal line 2202 in the third voltage adjusting signal line 223 is located in the third metal layer 2300, and the second sub-data connection wire 2302 is located in the fourth metal layer 2400.

[0104] The first voltage regulating transistor 121 is a gate reset transistor, the second voltage regulating transistor 122 is an anode reset transistor, and the third voltage regulating transistor 123 is a bias regulating transistor. The first voltage regulating signal line 221 is a gate reset signal line, the second voltage regulating signal line 222 is an anode reset signal line, and the third voltage regulating signal line 223 is a bias regulating signal line. In this embodiment, the horizontal part of the gate reset signal line is arranged in the first metal layer 2100, the horizontal part of the anode reset signal line is arranged in the second metal layer 2200, the horizontal part of the bias regulating signal line is arranged in the third metal layer 2300, the horizontal part of the data connection wire is arranged in the fourth metal layer 2400, and the vertical part of the gate reset signal line, the anode reset signal line, the bias regulating signal line, and the data connection wire is arranged in the fifth metal layer 2500. That is, the horizontal part of the gate reset signal line Vref1 is arranged in the M1 metal layer, the horizontal part of the anode reset signal line Vref2 is arranged in the MC metal layer, the horizontal part of the bias regulating signal line DVH is arranged in the MG metal layer, the horizontal part of the FIAA is arranged in the M2 metal layer, and the horizontal parts of the gate reset signal line Vref1, the anode reset signal line Vref2, the bias regulating signal line DVH, and the FIAA are arranged in the M3 metal layer.

[0105] As shown in FIGS. 10-18, the vertical part of the gate reset signal line Vref1 arranged in the fifth metal layer 2500, that is, the first sub-voltage regulating signal line 2201 in the first voltage regulating signal line 221, is electrically connected to the horizontal part of the gate reset signal line Vref1 arranged in the first metal layer 2100, that is, the second sub-voltage regulating signal line 2202 in the first voltage regulating signal line 221, through the first transfer part 20001 arranged in the fourth metal layer 2400 and the second transfer part 20002 arranged in the third metal layer 2300. The vertical part of the anode reset signal line Vref2 arranged in the fifth metal layer 2500, that is, the first sub-voltage regulating signal line 2201 in the second voltage regulating signal line 222, is electrically connected to the horizontal part of the anode reset signal line Vref2 arranged in the second metal layer 2200, that is, the second sub-voltage regulating signal line 2202 in the second voltage regulating signal line 222, through the third transfer part 20003 arranged in the fourth metal layer 2400. The vertical part of the bias regulating signal line DVH arranged in the fifth metal layer 2500, that is, the first sub-voltage regulating signal line 2201 in the third voltage regulating signal line 223, is electrically connected to the horizontal part of the bias regulating signal line DVH arranged in the third metal layer 2300, that is, the second sub-voltage regulating signal line 2202 in the third voltage regulating signal line 223, through the fourth transfer part 20004 arranged in the fourth metal layer 2400.

[0106] With reference back to FIG. 6 and FIG. 10-18, further, the signal lines 20 further include a first scan signal line 261 and a second scan signal line 262; the first scan signal lines 261 and the second scan signal lines 262 both extend along the second direction Y and are arranged along the first direction X;

[0107] The display panel 1 further includes a first semiconductor layer 3000, the first semiconductor layer 3000 is located between the substrate 1000 and the first metal layer 2100; the second voltage adjustment transistor 122, the third voltage adjustment transistor 123 and the data write transistor 11 all include an active layer, the active layer is located in the first semiconductor layer 3000;

[0108] The first scan signal line 261 and the active layer of the second voltage adjustment transistor 122 and the third voltage adjustment transistor 123 are overlapped in the thickness direction, and the overlapped part forms the gate of the second voltage adjustment transistor 122 and the third voltage adjustment transistor 123;

[0109] The second scan signal line 262 and the active layer of the data write transistor 11 are overlapped in the thickness direction, and the overlapped part forms the gate of the data write transistor 11.

[0110] In this embodiment, the first scan signal line 261 and the active layer of the second voltage adjustment transistor 122 and the third voltage adjustment transistor 123 are overlapped in the thickness direction, and the overlapped part forms the gate of the second voltage adjustment transistor 122 and the third voltage adjustment transistor 123, which is essentially that the first scan signal line 261 controls the switch of the second voltage adjustment transistor 122 and the third voltage adjustment transistor 123, that is, synchronously controls the switch of the anode reset transistor M7 and the bias adjustment transistor M8 in the pixel circuit, and the first scan signal line 261 is essentially the anode reset / bias adjustment control signal line SP*. The second scan signal line 262 and the active layer of the data write transistor 11 are overlapped in the thickness direction, and the overlapped part forms the gate of the second voltage adjustment transistor 122 and the third voltage adjustment transistor 123, which is essentially that the second scan signal line 262 controls the switch of the data write transistor 11 in the pixel circuit, and the second scan signal line 262 is essentially the data write control signal line SP.

[0111] It can be understood that the embodiment is essentially that the anode reset / bias adjustment control signal line SP* and the data write control signal line SP, and the transverse part of the gate reset signal line Vref1, that is, the second sub-voltage adjustment signal line 2202 in the first voltage adjustment signal line 221, are all arranged in the first metal layer 2100.

[0112] Further, the pixel circuit 10 further comprises a first light emitting control transistor 151 (also exemplified as M1) and a second light emitting control transistor 152 (also exemplified as M6); the first electrode of the first light emitting control transistor 151 is electrically connected with the first electrode of the driving transistor 13, and the second electrode receives a positive power supply signal PVDD; the second light emitting control transistor 152 is connected between the second electrode of the driving transistor 13 and the first electrode of the second voltage adjusting transistor 122;

[0113] The signal line 20 further comprises a light emitting control signal line 27 (also exemplified as Emit), and a plurality of light emitting control signal lines 27 extend along the second direction Y and are arranged along the first direction X; the light emitting control signal line 27 is located in the third metal layer 2300;

[0114] The gate of the first light emitting control transistor 151 and the second light emitting control transistor 152 is a line segment-shaped gate G, and the line segment-shaped gate G is located in the first metal layer 2100 and overlaps with the light emitting control signal line 27 in the thickness direction Z; the light emitting control signal line 27 is electrically connected with the line segment-shaped gate G1 of the first light emitting control transistor 151 and the second light emitting control transistor 152 respectively through a via.

[0115] In this embodiment, not only the anode reset / bias adjustment control signal line SP* and the data write control signal line SP, but also the transverse part of the gate reset signal line Vref1, i.e., the second sub-voltage adjusting signal line 2202 in the first voltage adjusting signal line 221, are arranged in the first metal layer 2100, and two kinds of line segment-shaped gates G1 are arranged in the first metal layer 2100, which respectively overlap with the active layers of the first light emitting control transistor 151 and the second light emitting control transistor 152, so as to control the switches of the first light emitting control transistor 151 and the second light emitting control transistor 152 as the gates. Since the line segment-shaped gates G on the first metal layer 2100 are independent of each other, the light emitting control signal line 27 is arranged in the third metal layer 2300 in this embodiment, and is electrically connected with the two kinds of line segment-shaped gates G1 respectively through a via, so as to provide the light emitting control signal Emit to the line segment-shaped gate G1 and control the switches of the first light emitting control transistor 151 and the second light emitting control transistor 152. In this embodiment, the independent line segment-shaped gates G1 are arranged in the first metal layer 2100, and the signals are provided to the line segment-shaped gate G1 from the third metal layer 2300, which can avoid the light emitting control signal line crossing the panel in the first metal layer 2100, save the wiring space of the first metal layer 2100, and simplify the wiring difficulty of the first metal layer 2100.

[0116] Further, the pixel circuit 1 further comprises a threshold compensation transistor 14 (also exemplified as M5), which is connected between the gate and the second electrode of the driving transistor 13;

[0117] The signal lines 20 further include a third scan signal line 263 and a fourth scan signal line 264; the third scan signal line 263 and the fourth scan signal line 264 each extend along the second direction Y and are arranged along the first direction X;

[0118] The display panel 1 further includes a second semiconductor layer 4000, the second semiconductor layer 4000 being located between the second metal layer 2200 and the third metal layer 2300;

[0119] The first voltage adjustment transistor 121 and the threshold compensation transistor 14 each include an active layer, the active layer being located in the second semiconductor layer 4000;

[0120] The first voltage adjustment transistor 121 and the threshold compensation transistor 14 each further include a top gate and a bottom gate;

[0121] The third scan signal line 263 and the active layer of the first voltage adjustment transistor 121 project and overlap in a thickness direction, and the overlapping part forms the top gate of the first voltage adjustment transistor 121;

[0122] The fourth scan signal line 264 and the active layer of the threshold compensation transistor 14 project and overlap in a thickness direction, and the overlapping part forms the top gate of the threshold compensation transistor 14;

[0123] The bottom gate of the first voltage adjustment transistor 121 and the threshold compensation transistor 14 is a line segment-shaped bottom gate G2;

[0124] The line segment-shaped bottom gate of the first voltage adjustment transistor 121 is located in the second metal layer 2200 and projects and overlaps with the third scan signal line 263 in a thickness direction, and the third scan signal line 263 is electrically connected to the line segment-shaped bottom gate G2 of the first voltage adjustment transistor 121 through a via hole;

[0125] The line segment-shaped bottom gate of the threshold compensation transistor 14 is located in the second metal layer 2200 and projects and overlaps with the fourth scan signal line 264 in a thickness direction, and the fourth scan signal line 264 is electrically connected to the line segment-shaped bottom gate G2 of the threshold compensation transistor 14 through a via hole.

[0126] The first voltage adjusting transistor 121 and the threshold compensation transistor 14 also each include a top gate and a bottom gate, indicating that both of the transistors adopt a double-gate structure. As shown in FIG. 6, the first voltage adjusting transistor 121 is essentially a gate reset transistor M4, which, like the threshold compensation transistor 14, is connected to the gate of the driving transistor 13, i.e., the first node N1. According to the driving process and principle of the pixel circuit, the first node N1 is responsible for storing a data signal. In this embodiment, the gate reset transistor M4 and the threshold compensation transistor M5 are both set as double-gate transistors, which can to some extent avoid current leakage of the two transistors, affect the data signal stored in the first node N1, and further ensure that the pixel circuit 10 drives the light-emitting element 40 to emit light at the target brightness. Specifically, the top gate and the bottom gate of the two double-gate transistors are arranged in the third metal layer 2300 and the second metal layer 2200, respectively. The third metal layer 2300 essentially provides a third scan signal line 263 and a fourth scan signal line 264 that traverse the panel, which respectively overlap the active layer of the first voltage adjusting transistor 121 and the threshold compensation transistor 14 in the second semiconductor layer 4000, and control the switching of one sub-transistor in the first voltage adjusting transistor 121 and the threshold compensation transistor 14. The second metal layer 2200 provides two independent linear bottom gates G2, which also respectively overlap the active layer of the first voltage adjusting transistor 121 and the threshold compensation transistor 14 in the second semiconductor layer 4000, and control the switching of the other sub-transistor in the first voltage adjusting transistor 121 and the threshold compensation transistor 14. For the linear bottom gate G2 on the second metal layer 2200, it is electrically connected to the third scan signal line 263 or the fourth scan signal line 264 on the third metal layer 2300 through a via hole, indirectly receives a gate reset control signal S1N through the third scan signal line 263, or receives a threshold compensation control signal S2N through the fourth scan signal line 264. Similarly, by providing independent linear bottom gates G2 on the second metal layer 2200 and providing signals to the linear gates G2 from the third metal layer 2300, the preparation of scan signal lines that traverse the panel on the second metal layer 2200 can be avoided, the wiring space of the second metal layer 2200 is saved, and the wiring difficulty of the second metal layer 2200 is simplified. In addition, it should be emphasized that by providing independent linear gates G2 on the second metal layer 2200, sufficient space can be reserved for the light transmission hole 30, which can form a larger area of the light transmission hole 30 on the display panel, and improve the aperture ratio of the light transmission hole 30.

[0127] With reference to FIGS. 6 and 11-18, further, the display panel 1 also includes a first semiconductor layer 3000 between the substrate 1000 and the first metal layer 2100; the driving transistor 13 includes an active layer in the first semiconductor layer 2100;

[0128] The pixel circuit 10 further comprises a storage capacitor 16 (also exemplified as Cst in the figure), the storage capacitor 16 comprising a first plate 161 and a second plate 162, the first plate 161 being located at the first metal layer 2100, and the second plate 162 being located at the second metal layer 2200, the first plate 161 and the second plate 162 being overlapped in the thickness direction;

[0129] The first plate 161 is overlapped with the active layer of the driving transistor 13 in the thickness direction and is multiplexed as the gate of the driving transistor 13, and the second plate 162 is connected with the positive power supply signal.

[0130] With reference to FIG. 6 and FIGS. 11-18, further, the positive power supply signal line 25 comprises a first line segment 251 and a second line segment 252 in the first direction X; the first line segment 251 is aligned with the through hole 30 in the second direction Y, and the second line segment 252 is misaligned with the through hole 30 in the second direction Y; the first line segment 251 and the second line segment 252 satisfy: D1 < D2; wherein D1 is the maximum width of the first line segment in the second direction, and D2 is the maximum width of the second line segment in the second direction.

[0131] In this embodiment, the first line segment 251 is aligned with the through hole 30 in the second direction Y, i.e. the row direction, indicating that the first line segment 251 is in the same position as the through hole 30 in the column direction. It can also be known that the second line segment 252 is misaligned with the through hole 30 in the second direction Y, i.e. the row direction, indicating that the second line segment 252 is not in the same position as the through hole 30 in the column direction. The maximum width of the first line segment 251 and the second line segment 252 in the second direction Y represents the maximum line width thereof. In this embodiment, the maximum line width D1 of the first line segment 251 is set to be less than the maximum line width D2 of the second line segment 252. In essence, the line width of the first line segment 251 of the positive power supply signal line 25 is appropriately narrowed, thereby leaving space for the through hole 30 adjacent and aligned in the row direction, so that the area of the through hole 30 can be increased, and the aperture ratio of the through hole 30 can be improved.

[0132] Optionally, D1 ≥ 2.4 μm.

[0133] The maximum line width D1 of the first line segment 251 is set to be not less than 2.4 μm. On the one hand, considering that the impedance of the signal line is negatively correlated with the line width of the signal line, the narrower the line width, the greater the impedance, which will cause the positive power supply voltage signal to attenuate. Setting the line width to be not less than 2.4 μm can improve the impedance of the positive power supply signal line 25 and prevent the positive power supply signal from attenuating. On the other hand, the narrower the line width, the higher the preparation precision requirement and the higher the preparation difficulty. Setting the line width to be not less than 2.4 μm can reduce the preparation precision to a certain extent and reduce the preparation difficulty.

[0134] Fig. 19 is a partial enlarged schematic view of yet another display panel provided by the embodiment of the present application. In an optional embodiment of the present application, at least two positive power signal lines 25 are electrically connected by a power connection trace 253 extending along the second direction Y and arranged in a layer different from the positive power signal lines 25.

[0135] The power connection trace 253 connects the at least two positive power signal lines 25, which can be connected in parallel, thereby reducing the impedance on the two positive power signal lines 25, avoiding attenuation of the positive power signal, ensuring that the pixel circuits receive the same positive power signal, keeping the driving process of each pixel circuit consistent, and being conducive to improving the display uniformity of the display panel. It should be noted here that the positive power signal lines 25 can form a network structure through the power connection trace 253, and the number thereof can be multiple. Each power connection trace 253 can connect a certain number of positive power signal lines 25 or even all the positive power signal lines 25.

[0136] Referring to Figs. 18 and 19, further, the display panel includes a substrate 1000 and a plurality of metal layers 2000 on the substrate 1000 in the thickness direction Z; the positive power signal lines 25, the data signal lines 21, the first sub-data connection traces 2301, and the first sub-voltage adjustment signal lines 2201 are located on a top metal layer 2001, which is the metal layer 2000 farthest from the substrate 1000; and the power connection trace 253 is located on a next-top metal layer 2004, which is the metal layer 2000 farthest from the substrate 1000 except the top metal layer 2004.

[0137] Similarly, the power connection trace 253 extending along the row direction is responsible for connecting the positive power signal lines 25 extending along the column direction, which needs to cross the data signal lines 21, the first sub-data connection traces 2301, and the first sub-voltage adjustment signal lines 2201 in the same layer and extending in parallel. To insulate from the data signal lines 21, the first sub-data connection traces 2301, and the first sub-voltage adjustment signal lines 2201, the power connection trace 253 needs to be arranged in another metal layer. In the embodiment of the present application, the power connection trace 253 is exemplarily arranged on the next-top metal layer 2004, and then connected with the positive power signal lines 25 through a via.

[0138] Continuing to refer to Fig. 11, further, the data signal lines 21, the first sub-data connection traces 2301, and the first sub-voltage adjustment signal lines 2201 each include a straight segment 201 and a curved segment or a polyline segment 202; the straight segment 201 extends along the first direction X and connects two adjacent curved segments or polyline segments 202, and the curved segment or polyline segment 202 is in a C shape.

[0139] The curve segment or broken line segment 202 of the first sub data connection wire 2301 and the curve segment or broken line segment 202 of the first sub voltage adjustment signal line 2201 are opposite and surround the through hole 30.

[0140] The curve segment or broken line segment 202 of the partial data signal line 21 surrounds the curve segment or broken line segment 202 of the first sub data connection wire 2301, and the curve segment or broken line segment 202 of the partial data signal line 21 surrounds the curve segment or broken line segment 202 of the first sub voltage adjustment signal line 2201.

[0141] This embodiment provides a specific extension shape of the data signal line 21, the first sub data connection wire 2301 and the first sub voltage adjustment signal line 2201 near the through hole 30, and the data signal line 21, the first sub data connection wire 2301 and the first sub voltage adjustment signal line 2201 all include the broken line segment 202. The straight line segment 201 part extends normally along the first direction X, i.e. the column direction, and the broken line segment 202 part is in a C shape and surrounds the through hole 30, which has the same purpose of reserving sufficient space for the through hole 30 and increasing the area of the through hole 30, and is conducive to improving the aperture ratio of the through hole 30.

[0142] Referring to FIGS. 4, 8 and 11, as in the above embodiment, the through hole 30 satisfies that one side is provided with a first sub data connection wire 2301 between an adjacent one pixel circuit group 100 in the second direction Y, and the other side is provided with a first sub voltage adjustment signal line 2201 between an adjacent another pixel circuit group 100.

[0143] FIG. 20 is a partial enlarged schematic view of another display panel provided by an embodiment of the present application. Referring to FIG. 20, in another optional embodiment, the through hole 30 satisfies that one side is provided with a first sub data connection wire 2301 between an adjacent one pixel circuit group 100 in the second direction Y, and the other side is provided with a first sub voltage adjustment signal line 2201 or is empty.

[0144] The embodiment is essentially that between the two pixel circuit groups 100 provided with the light transmission hole 30, only one data connection wire 23 extending in the column direction, that is, a first sub-data connection wire 2301, or a data connection wire 23 and a voltage adjustment signal line 22 extending in the column direction, that is, a first sub-data connection wire 2301 and a first sub-voltage adjustment signal line 2201, are provided. It can be understood that when only one first sub-data connection wire 2301 is provided on one side of the light transmission hole 30, and the other side is no longer provided with a first sub-voltage adjustment signal line 2201, it can be understood that a first sub-voltage adjustment signal line 2201 is removed, and more space can be left for the light transmission hole 30, further increasing the area of the light transmission hole 30 and improving the aperture ratio of the light transmission hole 30.

[0145] In addition, it needs to be explained that in the embodiment, a first sub-data connection wire 2301 is only provided between part of the light transmission hole 30 and the two pixel circuit groups 100 adjacent thereto, and a first sub-data connection wire 2301 and a first sub-voltage adjustment signal line 2201 are respectively provided between part of the light transmission hole 30 and the two pixel circuit groups 100 adjacent thereto. For the light transmission hole 30 provided with only a first sub-data connection wire 2301, compared with other light transmission holes 30, a first sub-voltage adjustment signal line 2201 is essentially removed. Therefore, it can be understood that although not all light transmission holes 30 are provided with a first sub-voltage adjustment signal line 2201, a certain number of first sub-voltage adjustment signal lines 2201 can cooperate with the second sub-voltage adjustment signal line 2202 to form a mesh structure, that is, to reduce the impedance on the voltage adjustment signal line 22 and avoid signal attenuation. In other words, only a first sub-data connection wire 2301 is provided near the light transmission hole 30, which only affects the number or density of the voltage adjustment signal line, but does not affect the formation of the mesh structure of the voltage adjustment signal line, thereby improving the display uniformity, providing a higher opening area for the light transmission hole 30, and improving the aperture ratio.

[0146] It also needs to be supplemented that since the first sub-data connection wire 2301 needs to extend in the first direction X, that is, the column direction, to provide the data signal provided by the fan-out area FANOUT to the second sub-data connection wire 2302 extending in the second direction Y, that is, the row direction, the first sub-data connection wire 2301 cannot be removed like the first sub-voltage adjustment signal line 2201 to leave space for the light transmission hole 30 and increase the aperture ratio.

[0147] On the basis of the above-mentioned scheme of removing one first sub-voltage adjustment signal line 2201 and increasing the opening area of the light passing hole 30, the embodiment of the present application can design whether the light passing hole 30 in the row direction adopts the scheme. Specifically, with reference to FIG. 20, in the possible case, the two light passing holes 30 adjacent in the second direction Y both satisfy that one first sub-data connection trace 2301 is arranged between one side and the adjacent pixel circuit group 100 in the second direction Y, and the other side is vacant.

[0148] As shown in FIG. 20, in the area where the light passing hole 30 in the odd row is located, the embodiment is to arrange the light passing hole 30 in the row direction to remove one first sub-voltage adjustment signal line 2201, so that the light passing hole 30 in the row has a larger light passing area.

[0149] With reference to FIG. 20, in another possible case, among the two light passing holes 30 adjacent in the second direction Y, one light passing hole 30 satisfies that one first sub-data connection trace 2301 is arranged between one side and the adjacent pixel circuit group 100 in the second direction Y, and the other side is vacant; and the other light passing hole 30 satisfies that one first sub-data connection trace 2301 is arranged between one side and the adjacent pixel circuit group 100 in the second direction Y, and one first sub-voltage adjustment signal line 2201 is arranged between the other side and the adjacent pixel circuit group 100.

[0150] As shown in FIG. 20, in the area where the light passing hole 30 in the even row is located, the embodiment is to arrange the light passing hole 30 in the row direction to remove the first sub-voltage adjustment signal line 2201 alternately, so that half of the light passing holes 30 have a larger light passing area, and meanwhile, the first sub-voltage adjustment signal line 2201 is not removed too much to affect the density of the network structure of the voltage adjustment signal line 22, which is beneficial to effectively reduce the impedance on the voltage adjustment signal line 22 and avoid the problem of signal attenuation; in addition, it can also avoid that the area where the light passing hole 30 in the row is located is completely free of the first sub-voltage adjustment signal line 2201, so that the second sub-voltage adjustment signal line 2202 extending in the row direction at different positions in the column direction can be connected through the first sub-voltage adjustment signal line 2201 in the area where the light passing hole 30 in the row is located, so that the network structure of the voltage adjustment signal line 22 covers the entire area of the display panel, which is more beneficial to effectively reduce the impedance on the voltage adjustment signal line 22 and avoid the problem of signal attenuation.

[0151] FIG. 21 is a partial enlarged schematic view of yet another display panel according to an embodiment of the present application, and FIG. 22 is a schematic view of a cross-sectional structure of yet another display panel according to an embodiment of the present application. Referring to FIGS. 20-22, the display panel 1 can include a color filter layer 5000, which includes a first color filter region 5100 and a second color filter region 5200. The reflectivity of the first color filter region 5100 is higher than that of the second color filter region 5200.

[0152] The first color filter region 5100 and the second color filter region 5200 are alternately arranged in the first direction X and the second direction Y. In the second direction Y, the light transmission hole 30 is located between adjacent first color filter region 5100 and second color filter region 5200.

[0153] The light transmission hole 30 satisfies that a first sub-data connection wire 2301 is arranged between the side close to the first color filter region 5100 and the adjacent pixel circuit group 100 in the second direction Y, and the side close to the second color filter region 5200 is empty or a first sub-voltage adjustment signal line 2201 is arranged between the side close to the second color filter region 5200 and the adjacent pixel circuit group.

[0154] In this embodiment, the display panel 1 includes the color filter layer 5000, which is substantially a CFOT (Color Filter On TFE) technology, that is, a circular polarizer is replaced by a color filter CF to reduce ambient light reflection and improve panel contrast. Each color filter region on the color filter layer 5000 is formed by a corresponding color filter material, which has a certain reflectivity. The reflectivity of the first color filter region 5100 is higher than that of the second color filter region 5200, which means that the color filter materials of different color filter regions on the color filter layer 5000 are different, and their reflectivities are different, which leads to the difference in reflectivity between different color filter regions. The reflectivity of the first color filter region 5100 is relatively high, which leads to higher brightness in this region and poorer brightness uniformity of the display region. For example, the first color filter region 5100 with high reflectivity can be a blue color filter region CF B, and the second color filter region 5200 with low reflectivity can be a red color filter region CF R.

[0155] In this embodiment, a first sub-data connection wire 2301 is arranged between the side close to the first color film region 5100 and the adjacent pixel circuit group 100 in the second direction Y, and a first sub-voltage adjustment signal line 2201 is arranged or not arranged between the side close to the second color film region 5200 and the adjacent pixel circuit group 100, that is, in the row direction, for some light transmission holes 30, the first sub-data connection wire 2301 is arranged on the side close to the first color film region 5100 with high reflectivity, and no signal line is arranged on the side close to the second color film region 5200 with low reflectivity. On the one hand, the side without signal line can leave more space for the light transmission hole 30, which helps to increase the opening area of the light transmission hole 30. On the other hand, although the light transmission hole 30 has light transmission, it does not mean that the light transmission hole 30 is a through hole. It only means that the area where the light transmission hole 30 is located is not blocked by a structure with low transmittance such as a signal line. In fact, the display panel is provided with a whole layer of transparent cathode layer (not shown in the figure), which has a certain reflectivity. By not arranging a signal line on the side close to the second color film region 5200 with low reflectivity, the edge of the light transmission hole 30 can expand to the second color film region 5200, so that more transparent cathode layer is exposed compared with the color film of the second color film region 5200, and is not blocked by the color film of the second color film region 5200. Thus, the exposed transparent cathode layer can be used to increase the reflectivity of the area near the second color film region 5200, thereby compensating for the brightness difference caused by the low reflectivity of the second color film region 5200 compared with the first color film region 5100, thereby helping to improve the display uniformity of the display area.

[0156] It should be noted that in the color film layer 5000 of the embodiment of the present application, in addition to the first color film region 5100 and the second color film region 5200, a third color film region 5300 can also be arranged. For example, the first color film region 5100, the second color film region 5200 and the third color film region 5300 can correspond to the blue color film region CF B, the red color film region CF R and the green color film region CF G respectively. The third color film region 5300 can be arranged between two first color film regions 5100 and two second color film regions 5200 adjacent to each other in the first direction X and the second direction Y. The two first color film regions 5100 are diagonally arranged, and the two second color film regions 5200 are diagonally arranged.

[0157] Continuing to refer to FIGS. 21 and 22, further, the light transmission hole 30 includes a first light transmission hole 31 and a second light transmission hole 32; the first light transmission hole 31 and the second light transmission hole 32 are arranged alternately along the first direction X in sequence, a plurality of first light transmission holes 31 are arranged along the second direction Y in sequence, and a plurality of second light transmission holes 32 are arranged along the second direction Y in sequence.

[0158] The first light passing hole 31 satisfies that a first sub data connection wire 2301 is arranged between the side close to the first color film area 5100 and the adjacent one pixel circuit group 100 in the second direction Y, and the side close to the second color film area 5200 is empty or a first sub voltage adjustment signal line 2201 is arranged.

[0159] The second light passing hole 32 satisfies that a first sub voltage adjustment signal line 2201 is arranged between the side close to the first color film area 5100 and the adjacent one pixel circuit group 100 in the second direction Y, and a first sub data connection wire 2301 is arranged between the side close to the second color film area 5200 and the adjacent one pixel circuit group 100.

[0160] It needs to be understood that, since the first sub data connection wire 2301 needs to avoid the coupling effect between the signal lines caused by transmitting different data signals with the data signal line 21, the first sub data connection wire 2301 needs to be alternately arranged on the first side and the second side of the light passing hole 30, and the first color film area 5100 and the second color film area 5200 are also alternately arranged in the row direction. Therefore, when the side close to the second color film area 5200 of the light passing hole 30 is left with space by not arranging the signal line, if the side of the first sub data connection wire 2301 of the light passing hole 30 is not the side close to the second color film area 5200 of the light passing hole 30, that is, the other side is the side close to the second color film area 5200 of the light passing hole 30, then the adjacent position of the light passing hole 30 in the row of the first color film area 5100 and the second color film area 5200 can only be arranged with the first sub data connection wire 2301, and the other side does not need to be arranged with the first sub voltage adjustment signal line 2201. In other words, the adjacent position of the light passing hole 30 in this row will alternately arrange the first sub data connection wire 2301 on the first side and the second side. If the side of the first sub data connection wire 2301 of the light passing hole 30 is the side close to the second color film area 5200 of the light passing hole 30, since the purpose of arranging the first sub data connection wire 2301 is not to form a network structure, but to transmit the data signal from the fan-out area FANOUT to the second sub data connection wire 2302 extending in the row direction, therefore, it is not possible to leave space for the light passing hole 30 by removing the signal line on the side close to the second color film area 5200 of the light passing hole 30, that is, it is not possible to leave the position for the light passing hole 30 by removing the first sub data connection wire 2301, thereby making the first sub voltage adjustment signal line 2201 on the side close to the first color film area 5100 of the second light passing hole 30 not need to be removed, the first sub data connection wire 2301 on the side close to the second color film area 5200 of the second light passing hole 30 cannot be removed, and the second light passing hole 30 is arranged with a first sub voltage adjustment signal line 2201 and a first sub data connection wire 2301 on both sides.

[0161] With reference back to FIGS. 21 and 22, further, the first light passing hole 31 includes a first sub light passing hole 311 and a second sub light passing hole 312, the first sub light passing hole 311 and the second sub light passing hole 312 are arranged alternately in sequence along the second direction Y;

[0162] The first sub light passing hole 311 satisfies that a first sub data connection wire 2301 is arranged between a side close to the first color filter area 5100 and an adjacent one of the pixel circuit groups 100 in the second direction Y, and a side close to the second color filter area 5200 is vacant;

[0163] The second sub light passing hole 312 satisfies that a first sub data connection wire 2301 is arranged between a side close to the first color filter area 5100 and an adjacent one of the pixel circuit groups 100 in the second direction Y, and a first sub voltage adjustment signal line 2201 is arranged between a side close to the second color filter area 5200 and an adjacent one of the pixel circuit groups 100.

[0164] This embodiment is also a scheme of alternately removing the first sub voltage adjustment signal line 2201 in the plurality of first light passing holes 31 arranged in the row direction, so that half of the first light passing holes 31, i.e., the first sub light passing holes 311, have a larger light passing area, and meanwhile, the first sub voltage adjustment signal line 2201 is not removed too much, which does not affect the density of the network structure of the voltage adjustment signal line 22, is conducive to effectively reducing the impedance on the voltage adjustment signal line 22, and avoids the problem of signal attenuation. In addition, it can also avoid that the area where the first light passing hole 31 is located in the column direction is completely free of the first sub voltage adjustment signal line 2201, and can ensure that the second sub voltage adjustment signal line 2202 is located in the area where the second light passing hole 32 is located, and can be connected through the first sub voltage adjustment signal line 2201 in the area where the first light passing hole 31 is located, so that the network structure of the voltage adjustment signal line 22 covers the entire area of the display panel, which is more conducive to effectively reducing the impedance on the voltage adjustment signal line 22 and avoiding the problem of signal attenuation.

[0165] With reference back to FIGS. 21 and 22, further, the light passing hole 30 includes a first side and a second side facing away from each other in the second direction Y; each first sub data connection wire 2301 is alternately located on the first side and the second side of the first light passing hole 31. The pixel circuit 10 includes a plurality of voltage adjustment transistors 12, the voltage adjustment signal line 22 electrically connected to the first electrode of different voltage adjustment transistors 12 transmits different voltage adjustment signals; each first sub voltage adjustment signal line 2201 in the voltage adjustment signal line 22 electrically connected to the first electrode of different voltage adjustment transistors 12 is arranged in sequence and alternately on the first side and the second side of the second light passing hole 32 in the second direction Y.

[0166] As mentioned above, the first sub data connection wires 2301 need to be arranged alternately on the first side and the second side of the light passing holes 30 to avoid the coupling with the data signal lines 21. For each first light passing hole 31 arranged in the row direction, the first sub data connection wires 2301 are arranged alternately on the first side and the second side, and for each first light passing hole 31, the other side can be provided with the first sub voltage adjustment signal line 2201 or can be left empty, which is not limited here.

[0167] For each second light passing hole 32 arranged in the row direction, the first sub data connection wires 2301 are also arranged alternately on the first side and the second side, and for each second light passing hole 32, the other side needs to be provided with the first sub voltage adjustment signal line 2201. As mentioned above, in the embodiment of the present application, there are different nodes in the pixel circuit that need to be adjusted in voltage, that is, there are more than one voltage adjustment signal line 22. The voltage adjustment transistor 12 can specifically include a first voltage adjustment transistor 121, a second voltage adjustment transistor 122 and a third voltage adjustment transistor 123, and the voltage adjustment signal line 22 can specifically include a first voltage adjustment signal line 221, a second voltage adjustment signal line 222 and a third voltage adjustment signal line 223. Exemplarily, the first voltage adjustment transistor 121 can be a gate reset transistor, the second voltage adjustment transistor 122 can be an anode reset transistor, and the third voltage adjustment transistor 123 can be a bias adjustment transistor, the first voltage adjustment signal line 221 corresponds to a gate reset signal line, the second voltage adjustment signal line 222 corresponds to an anode reset signal line, and the third voltage adjustment signal line 223 corresponds to a bias adjustment signal line. In the embodiment, the first sub voltage adjustment signal line 2201 in each of the different voltage adjustment signal lines 22 is arranged in the second direction Y in turn and alternately on the first side and the second side of the second light passing hole 32, which is arranged in the first side and the second side of the first sub data connection wire 2301 alternately, and is also arranged alternately on the second side and the first side of the second light passing hole 32, and the first sub voltage adjustment signal line 2201 of the different voltage adjustment signal lines 22 is arranged in the row direction in turn according to a fixed order, for example, the order of the third voltage adjustment signal line 223, the second voltage adjustment signal line 222 and the first voltage adjustment signal line 221.

[0168] FIG. 23 is a top view of yet another display panel according to an embodiment of the present application. Referring to FIG. 23, the first color filter region 5100 and the second color filter region 5200 alternately arranged in the first direction X have a first axis of symmetry L1, and between two adjacent first axes of symmetry L1 in the second direction Y, there is a second axis of symmetry L2. Any straight line extending in the second direction Y and passing through the first color filter region 5100, the second color filter region 5200 and the light transmission hole 30 is a first straight line L3. The edges of the first color filter region 5100 and the second color filter region 5200 each include an intersection edge L4, which is an edge formed by all intersection points with the first straight line L3. The first color filter region 5100 and the second color filter region 5200 satisfy S1 < S2, where S1 is the area of the region between the intersection edge L4 of the first color filter region 5100 and the adjacent second axis of symmetry L2, and S2 is the area of the region between the intersection edge L4 of the second color filter region 5200 and the adjacent second axis of symmetry L2.

[0169] The region between the intersection edge L4 and the second axis of symmetry L3 can be understood as the region reserved by the color filter region for the adjacent light transmission hole 30. In this embodiment, the area S1 of the region between the intersection edge L4 of the first color filter region 5100 and the second axis of symmetry L3 is set to be smaller than the area S2 of the region between the intersection edge L4 of the second color filter region 5200 and the second axis of symmetry L3. The essence is that when designing the specific shapes of the first color filter region 5100 and the second color filter region 5200, the opening area of the light transmission hole 30 and the reflectivity difference between the first color filter region 5100 and the second color filter region 5200 are considered. The edge of the second color filter region 5200 with lower reflectivity is made farther away from the light transmission hole 30, that is, more space is reserved for the light transmission hole 30. It can also be understood that the edge of the light transmission hole 30 is made to expand more towards the second color filter region 5200. Thus, while increasing the opening area of the light transmission hole 30, the reflectivity of the region near the second color filter region 5200 is improved by using the exposed transparent cathode layer, thereby compensating for the brightness difference caused by the lower reflectivity of the second color filter region 5200 compared to the first color filter region 5100, and improving the display uniformity of the display region.

[0170] Continuing to refer to FIG. 23, the first color filter region 5100 and the second color filter region 5200 alternately arranged in the first direction X have a first axis of symmetry L1, and between two adjacent first axes of symmetry L1 in the second direction Y, there is a second axis of symmetry L2. Any straight line extending in the second direction Y and passing through the first color filter region 5100, the second color filter region 5200 and the light transmission hole 30 is a first straight line L3. The first color filter region 5100 and the second color filter region 5200 satisfy D3 < D4, where D3 is the distance from the intersection of the first straight line L3 and the edge of the first color filter region 5100 to the adjacent second axis of symmetry L2, and D4 is the distance from the intersection of the first straight line L3 and the edge of the second color filter region 5200 to the adjacent second axis of symmetry L2.

[0171] The distance from the intersection point of the first straight line L3 and the edge of the color film region to the adjacent second symmetry axis L2 can reflect the distance of the color film region away from the light transmission hole 30, or can reflect the distance of the edge line of the color film region extending away from the light transmission hole 30. In this embodiment, the distance D3 from the intersection point of the first straight line L3 and the edge of the first color film region 5100 to the adjacent second symmetry axis L2 is less than the distance D4 from the intersection point of the first straight line L3 and the edge of the second color film region 5200 to the adjacent second symmetry axis L2. When designing the specific shapes of the first color film region 5100 and the second color film region 5200, the opening area of the light transmission hole 30 and the reflectivity difference between the first color film region 5100 and the second color film region 5200 are considered, the edge of the second color film region 5200 with lower reflectivity is farther away from the light transmission hole 30, that is, more space is reserved for the light transmission hole 30, or it can be understood that the edge of the light transmission hole 30 is more extended to the second color film region 5200, thereby increasing the opening area of the light transmission hole 30, using the exposed transparent cathode layer to improve the reflectivity of the region near the second color film region 5200, and then compensating for the brightness difference caused by the lower reflectivity of the second color film region 5200 compared with the first color film region 5100, thereby improving the display uniformity of the display region.

[0172] Based on the same inventive concept, the embodiment of the present application also provides a display device. FIG. 24 is a structural schematic diagram of a display device provided by an embodiment of the present application. As shown in FIG. 24, the display device includes the display panel 1 described in any of the above embodiments. Therefore, the display device provided by the embodiment of the present application has the corresponding beneficial effects of the above embodiments, which will not be described here. For example, the display device can be a mobile phone, a computer, a smart wearable device (for example, a smart watch), a vehicle-mounted display device, or other electronic devices, which are not limited by the embodiment of the present application.

[0173] Note that the above are only preferred embodiments of the present application and the technical principles applied. Those skilled in the art will understand that the present application is not limited to the specific embodiments described herein, and those skilled in the art can make various obvious changes, re-adjustments, mutual combinations and substitutions without departing from the scope of the present application. Therefore, although the present application has been described in more detail through the above embodiments, the present application is not limited to the above embodiments, and can include more other equivalent embodiments without departing from the concept of the present application, and the scope of the present application is determined by the scope of the appended claims.

Claims

1. A display panel, characterized by, The pixel circuit comprises a data writing transistor and a voltage regulating transistor; the signal line comprises a data signal line and a voltage regulating signal line, the data signal line is electrically connected with the first electrode of the data writing transistor, and the voltage regulating signal line is electrically connected with the first electrode of the voltage regulating transistor; A plurality of data signal lines extend along a first direction and are arranged along a second direction, and the first direction and the second direction intersect; The display panel further comprises a display area and a fan-out area located on one side of the display area; the display area comprises a first display area and a second display area, and the second display area is located on at least one side of the first display area; The fan-out area comprises a plurality of fan-out wires, and the first display area and the second display area each comprise a plurality of data signal lines; the data signal lines are connected with the fan-out wires; wherein the data signal lines of the second display area are connected with the fan-out wires through data connection wires located in the first display area; The data connection wires comprise first sub-data connection wires, and a plurality of first sub-data connection wires extend along the first direction and are arranged along the second direction; the voltage regulating signal line comprises first sub-voltage regulating signal lines, and a plurality of first sub-voltage regulating signal lines extend along the first direction and are arranged along the second direction; wherein the first sub-voltage regulating signal lines, the first sub-data connection wires and the data signal lines are arranged on the same layer; The first display area further comprises a plurality of light transmission holes, and the projections of the light transmission holes along the thickness direction of the display panel do not overlap with the projections of the pixel circuit and the signal line along the thickness direction of the display panel, respectively; A plurality of pixel circuits arranged along the first direction in sequence form a pixel circuit group, and a plurality of pixel circuit groups are arranged along the second direction in sequence; At least part of the light transmission holes satisfy that a first sub-data connection wire is arranged between one side and an adjacent pixel circuit group in the second direction; at least part of the light transmission holes satisfy that a first sub-voltage regulating signal line is arranged between one side and an adjacent pixel circuit group in the second direction. At least part of the light transmission holes further satisfy that a data signal line is arranged between the adjacent pixel circuit group and the first sub-data connection wire on one side in the second direction; 2. The display panel of claim 1, wherein, At least part of the light transmission holes further satisfy that a data signal line is arranged between the adjacent pixel circuit group and the first sub-voltage regulating signal line on one side in the second direction. The data connection wires further comprise second sub-data connection wires, and a plurality of second sub-data connection wires extend along the second direction and are arranged along the first direction; the second sub-data connection wires are arranged on different layers from the first sub-data connection wires; 3. The display panel of claim 1, wherein, One end of the second sub-data connection wire is electrically connected with the first sub-data connection wire in one-to-one correspondence, and the other end of the second sub-data connection wire extends to the second display area and is electrically connected with the data signal line in one-to-one correspondence. ​ 4. The display panel of claim 1, wherein, The light through hole comprises a first side and a second side which are opposite to each other in the second direction; Part of the first sub data connection wires are located on the first side of the light through hole, and part of the first sub data connection wires are located on the second side of the light through hole.

5. The display panel of claim 4, wherein, In the second direction, each of the first sub data connection wires is alternately located on the first side and the second side of the light through hole.

6. The display panel of claim 1, wherein, The pixel circuit comprises a plurality of voltage adjustment transistors, and the voltage adjustment signal lines electrically connected to the first poles of different voltage adjustment transistors transmit different voltage adjustment signals. Each of the first sub voltage adjustment signal lines in the voltage adjustment signal lines electrically connected to the first poles of different voltage adjustment transistors is arranged in sequence in the second direction.

7. The display panel of claim 1, wherein, The voltage adjustment signal lines further comprise second sub voltage adjustment signal lines, and a plurality of second sub voltage adjustment signal lines extend along the second direction and are arranged along the first direction. The second sub voltage adjustment signal lines are electrically connected to the first sub voltage adjustment signal lines, and the second sub voltage adjustment signal lines are arranged in different layers from the first sub voltage adjustment signal lines.

8. The display panel of claim 7, wherein, The pixel circuit comprises a plurality of voltage adjustment transistors, and the voltage adjustment signal lines electrically connected to the first poles of different voltage adjustment transistors transmit different voltage adjustment signals. Each of the second sub voltage adjustment signal lines in the voltage adjustment signal lines electrically connected to the first poles of different voltage adjustment transistors is arranged in different layers.

9. The display panel of claim 8, wherein, The voltage adjustment transistor comprises a first voltage adjustment transistor, and the pixel circuit further comprises a driving transistor. The first pole of the first voltage adjustment transistor is electrically connected to the gate of the driving transistor, and the voltage adjustment signal line comprises a first voltage adjustment signal line. The first voltage adjustment signal line is electrically connected to the second pole of the first voltage adjustment transistor.

10. The display panel of claim 8, wherein, The voltage adjustment transistor comprises a second voltage adjustment transistor, and the pixel circuit further comprises a driving transistor. The first pole of the second voltage adjustment transistor is electrically connected to the second pole of the driving transistor. The voltage adjustment signal line comprises a second voltage adjustment signal line, and the second voltage adjustment signal line is electrically connected to the second pole of the second voltage adjustment transistor.

11. The display panel of claim 8, wherein, The voltage adjustment transistor comprises a third voltage adjustment transistor, and the pixel circuit further comprises a driving transistor. The second pole of the data write transistor and the first pole of the third voltage adjustment transistor are both electrically connected to the first pole of the driving transistor. The voltage adjustment signal line comprises a third voltage adjustment signal line, and the third voltage adjustment signal line is electrically connected to the second pole of the third voltage adjustment transistor.

12. The display panel of claim 8, wherein, The data connection wire further comprises a second sub data connection wire, and a plurality of second sub data connection wires extend along the second direction and are arranged along the first direction; the second sub data connection wire is arranged in different layers from the first sub data connection wire. One end of the second sub data connection wire is electrically connected to the first sub data connection wire one by one, and the other end of the second sub data connection wire extends to the second display area and is electrically connected to the data signal line one by one. The second sub-data connection wire is arranged in a layer different from the second sub-voltage adjustment signal line.

13. The display panel of claim 12, wherein, At least two wires in the second sub-data connection wire and the second sub-voltage adjustment signal line electrically connected with the first electrode of the different voltage adjustment transistor are at least partially overlapped in the vertical projection in the thickness direction of the display panel.

14. The display panel of claim 12, wherein, The display panel comprises a substrate and a plurality of metal layers on the substrate in the thickness direction. The data signal line, the first sub-data connection wire, and the first sub-voltage adjustment signal line electrically connected with the first electrode of the different voltage adjustment transistor are located on the top metal layer, which is the farthest metal layer from the substrate. The second sub-data connection wire and the second sub-voltage adjustment signal line electrically connected with the first electrode of the different voltage adjustment transistor are respectively distributed on the intermediate metal layer and the bottom metal layer, the intermediate metal layer is between the top metal layer and the bottom metal layer, and the bottom metal layer is the closest metal layer to the substrate. At least one intermediate metal layer is provided with a switching part. The first sub-data connection wire and the second sub-data connection wire are separated by at least one intermediate metal layer, and the first sub-data connection wire and the second sub-data connection wire are electrically connected through the switching part on the intermediate metal layer; and / or, the first sub-voltage adjustment signal line and the second sub-voltage adjustment signal line of the same voltage adjustment signal line are separated by at least one intermediate metal layer, and the first sub-voltage adjustment signal line and the second sub-voltage adjustment signal line are electrically connected through the switching part on the intermediate metal layer.

15. The display panel of claim 12, wherein, The display panel comprises a substrate, a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, and a fifth metal layer in the thickness direction. The first sub-voltage adjustment signal line, the first sub-data connection wire, and the data signal line are located on the fifth metal layer. The voltage adjustment transistor comprises a first voltage adjustment transistor, a second voltage adjustment transistor, and a third voltage adjustment transistor, and the pixel circuit further comprises a driving transistor. The first electrode of the first voltage adjustment transistor is electrically connected with the gate electrode of the driving transistor, the first electrode of the second voltage adjustment transistor is electrically connected with the second electrode of the driving transistor, and the second electrode of the data write transistor and the first electrode of the third voltage adjustment transistor are both electrically connected with the first electrode of the driving transistor. The voltage adjustment signal line comprises a first voltage adjustment signal line, a second voltage adjustment signal line, and a third voltage adjustment signal line. The first voltage adjustment signal line is electrically connected with the second electrode of the first voltage adjustment transistor, the second voltage adjustment signal line is electrically connected with the second electrode of the second voltage adjustment transistor, and the third voltage adjustment signal line is electrically connected with the second electrode of the third voltage adjustment transistor. The second sub-data connection wire, the second sub-voltage adjustment signal line in the first voltage adjustment signal line, the second sub-voltage adjustment signal line in the second voltage adjustment signal line, and the second sub-voltage adjustment signal line in the third voltage adjustment signal line are located in one of the first metal layer, the second metal layer, the third metal layer, and the fourth metal layer.

16. The display panel of claim 15, wherein, The second sub-voltage adjustment signal line in the first voltage adjustment signal line is located in the first metal layer, the second sub-voltage adjustment signal line in the second voltage adjustment signal line is located in the second metal layer, the second sub-voltage adjustment signal line in the third voltage adjustment signal line is located in the third metal layer, and the second sub-data connection wire is located in the fourth metal layer.

17. The display panel of claim 15, wherein, The signal lines further include first scan signal lines and second scan signal lines; the first scan signal lines and the second scan signal lines each extend along the second direction and are arranged along the first direction; The display panel further includes a first semiconductor layer, and the first semiconductor layer is located between the substrate and the first metal layer; The second voltage adjustment transistor, the third voltage adjustment transistor, and the data write transistor each include an active layer, and the active layer is located in the first semiconductor layer; The first scan signal lines are respectively overlapped with the active layers of the second voltage adjustment transistor and the third voltage adjustment transistor in a thickness direction, and the overlapped portions form gates of the second voltage adjustment transistor and the third voltage adjustment transistor; The second scan signal lines are overlapped with the active layer of the data write transistor in a thickness direction, and the overlapped portions form a gate of the data write transistor.

18. The display panel of claim 15, wherein, The pixel circuit further includes first light-emitting control transistors and second light-emitting control transistors; The first light-emitting control transistors are electrically connected to the first electrodes of the driving transistors, and the second electrodes receive positive power supply signals; the second light-emitting control transistors are connected between the second electrodes of the driving transistors and the first electrodes of the second voltage adjustment transistors; The signal lines further include light-emitting control signal lines, and the light-emitting control signal lines each extend along the second direction and are arranged along the first direction; the light-emitting control signal lines are located in the third metal layer; The gates of the first light-emitting control transistors and the second light-emitting control transistors are line segment-shaped gates, the line segment-shaped gates are located in the first metal layer and are overlapped with the light-emitting control signal lines in a thickness direction, and the light-emitting control signal lines are electrically connected to the line segment-shaped gates of the first light-emitting control transistors and the second light-emitting control transistors through vias.

19. The display panel of claim 15, wherein, The pixel circuit further includes threshold compensation transistors, and the threshold compensation transistors are connected between the gates and the second electrodes of the driving transistors; The signal lines further include third scan signal lines and fourth scan signal lines; the third scan signal lines and the fourth scan signal lines each extend along the second direction and are arranged along the first direction; The display panel further comprises a second semiconductor layer, the second semiconductor layer is located between the second metal layer and the third metal layer; The first voltage adjusting transistor and the threshold compensation transistor each comprise an active layer, the active layer is located in the second semiconductor layer; The first voltage adjusting transistor and the threshold compensation transistor each further comprise a top gate and a bottom gate; The third scan signal line and the active layer of the first voltage adjusting transistor overlap in a thickness direction, and the overlapping part forms a top gate of the first voltage adjusting transistor; The fourth scan signal line and the active layer of the threshold compensation transistor overlap in a thickness direction, and the overlapping part forms a top gate of the threshold compensation transistor; The bottom gates of the first voltage adjusting transistor and the threshold compensation transistor are line segment-shaped bottom gates; The line segment-shaped bottom gate of the first voltage adjusting transistor is located in the second metal layer and overlaps with the third scan signal line in a thickness direction, the third scan signal line is electrically connected with the line segment-shaped bottom gate of the first voltage adjusting transistor through a via hole; The line segment-shaped bottom gate of the threshold compensation transistor is located in the second metal layer and overlaps with the fourth scan signal line in a thickness direction, the fourth scan signal line is electrically connected with the line segment-shaped bottom gate of the threshold compensation transistor through a via hole. The display panel further comprises a first semiconductor layer, the first semiconductor layer is located between the substrate and the first metal layer; the driving transistor comprises an active layer, the active layer is located in the first semiconductor layer; 20. The display panel of claim 15, wherein, The pixel circuit further comprises a storage capacitor, the storage capacitor comprises a first plate and a second plate, the first plate is located in the first metal layer, the second plate is located in the second metal layer, and the first plate and the second plate overlap in a thickness direction; The first plate and the active layer of the driving transistor overlap in a thickness direction and are multiplexed as a gate of the driving transistor, and the second plate is connected with a positive power signal. The signal line further comprises a positive power signal line, a plurality of positive power signal lines extend along the second direction and are arranged along the first direction; 21. The display panel of claim 2, wherein, The positive power signal line, the data signal line, the first sub-data connection trace and the first sub-voltage adjusting signal line are arranged in the same layer, and the positive power signal line overlaps with the pixel circuit group in a thickness direction; The positive power signal line and the light through hole are alternately arranged in the second direction, one data signal line and one first sub-data connection trace are included between part of the positive power signal line and the light through hole, and one data signal line and one first sub-voltage adjusting signal line are included between part of the positive power signal line and the light through hole. The positive power signal line comprises a first line segment and a second line segment in the first direction; the first line segment is aligned with the light through hole in the second direction, and the second line segment is misaligned with the light through hole in the second direction; 22. The display panel of claim 21, wherein, The first line segment and the second line segment satisfy D1 ​ D1 is a maximum width of the first line segment in the second direction, and D2 is a maximum width of the second line segment in the second direction.

23. The display panel of claim 22, wherein, D1 is greater than or equal to 2.4 μm.

24. The display panel of claim 21, wherein, At least two positive power signal lines are electrically connected by a power connection trace extending in the second direction and arranged in a layer different from the positive power signal lines.

25. The display panel of claim 24, wherein, The display panel includes a substrate and a plurality of metal layers on the substrate in a thickness direction. The positive power signal lines, the data signal lines, the first sub-data connection traces, and the first sub-voltage adjustment signal lines are located on a top metal layer, which is the farthest metal layer from the substrate. The power connection trace is located on a sub-top metal layer, which is the farthest metal layer from the substrate except the top metal layer.

26. The display panel of claim 2, wherein, The data signal lines, the first sub-data connection traces, and the first sub-voltage adjustment signal lines each include a straight line segment and a curved line segment or a polyline segment; the straight line segment extends in the first direction and connects two adjacent curved line segments or polyline segments; and the curved line segments or the polyline segments are in a C shape. The curved line segment or the polyline segment of the first sub-data connection trace and the curved line segment or the polyline segment of the first sub-voltage adjustment signal line are oppositely open and surround the light transmission hole. Part of the curved line segments or the polyline segments of the data signal lines surround the curved line segment or the polyline segment of the first sub-data connection trace, and part of the curved line segments or the polyline segments of the data signal lines surround the curved line segment or the polyline segment of the first sub-voltage adjustment signal line.

27. The display panel of claim 1, wherein, The light transmission hole satisfies that one side thereof is provided with one first sub-data connection trace between an adjacent one of the pixel circuit groups, and the other side thereof is provided with one first sub-voltage adjustment signal line between an adjacent other of the pixel circuit groups.

28. The display panel of claim 1, wherein, The light transmission hole satisfies that one side thereof is provided with one first sub-data connection trace between an adjacent one of the pixel circuit groups, and the other side thereof is empty or provided with one first sub-voltage adjustment signal line.

29. The display panel of claim 28, wherein, Both of the two adjacent light transmission holes in the second direction satisfy that one side thereof is provided with one first sub-data connection trace between an adjacent one of the pixel circuit groups, and the other side thereof is empty. Alternatively, One of the two adjacent light transmission holes in the second direction satisfies that one side thereof is provided with one first sub-data connection trace between an adjacent one of the pixel circuit groups, and the other side thereof is empty; and the other of the two adjacent light transmission holes in the second direction satisfies that one side thereof is provided with one first sub-data connection trace between an adjacent one of the pixel circuit groups, and the other side thereof is provided with one first sub-voltage adjustment signal line between an adjacent other of the pixel circuit groups.

30. The display panel of claim 28, wherein, The display panel includes a color filter layer, the color filter layer includes a first color filter region and a second color filter region, and a reflectivity of the first color filter region is higher than a reflectivity of the second color filter region. The first color film region and the second color film region are alternately arranged in the first direction and the second direction; in the second direction, the light transmission hole is located between adjacent first color film regions and second color film regions; The light transmission hole satisfies: in the second direction, one side close to the first color film region is provided with one first sub-data connection wire between adjacent pixel circuit groups, and one side close to the second color film region is left empty or provided with one first sub-voltage adjustment signal line.

31. The display panel of claim 30, wherein, The light transmission hole includes a first light transmission hole and a second light transmission hole; The first light transmission hole and the second light transmission hole are alternately arranged in the first direction, a plurality of first light transmission holes are arranged in the second direction, and a plurality of second light transmission holes are arranged in the second direction; The first light transmission hole satisfies: in the second direction, one side close to the first color film region is provided with one first sub-data connection wire between adjacent pixel circuit groups, and one side close to the second color film region is left empty or provided with one first sub-voltage adjustment signal line; The second light transmission hole satisfies: in the second direction, one side close to the first color film region is provided with one first sub-voltage adjustment signal line between adjacent pixel circuit groups, and one side close to the second color film region is provided with one first sub-data connection wire between adjacent pixel circuit groups.

32. The display panel of claim 31, wherein, The first light transmission hole includes a first sub-light transmission hole and a second sub-light transmission hole, and the first sub-light transmission hole and the second sub-light transmission hole are alternately arranged in the second direction; The first sub-light transmission hole satisfies: in the second direction, one side close to the first color film region is provided with one first sub-data connection wire between adjacent pixel circuit groups, and one side close to the second color film region is left empty; The second sub-light transmission hole satisfies: in the second direction, one side close to the first color film region is provided with one first sub-data connection wire between adjacent pixel circuit groups, and one side close to the second color film region is provided with one first sub-voltage adjustment signal line.

33. The display panel of claim 31, wherein, The light transmission hole includes a first side and a second side facing away from each other in the second direction; Each first sub-data connection wire is alternately located on the first side and the second side of the first light transmission hole; The pixel circuit includes a plurality of voltage adjustment transistors, and the voltage adjustment signal lines electrically connected to the first electrodes of different voltage adjustment transistors transmit different voltage adjustment signals; Each first sub-voltage adjustment signal line in the voltage adjustment signal lines electrically connected to the first electrodes of different voltage adjustment transistors is arranged in the second direction in a cycle and alternately located on the first side and the second side of the second light transmission hole.

34. The display panel of claim 30, wherein, The first color film region and the second color film region arranged alternately in the first direction have first symmetry axes, and between two adjacent first symmetry axes in the second direction, there is a second symmetry axis; any straight line extending in the second direction and passing through the first color film region, the second color film region and the light through hole is a first straight line, edges of the first color film region and the second color film region each include an intersection edge, and the intersection edge is an edge formed by all intersection points intersecting with the first straight line; The first color film region and the second color film region satisfy S1 < S2; Wherein, S1 is an area of a region between the intersection edge of the first color film region and the adjacent second symmetry axis, and S2 is an area of a region between the intersection edge of the second color film region and the adjacent second symmetry axis.

35. The display panel of claim 30, wherein, The first color film region and the second color film region arranged alternately in the first direction have first symmetry axes, and between two adjacent first symmetry axes in the second direction, there is a second symmetry axis; any straight line extending in the second direction and passing through the first color film region, the second color film region and the light through hole is a first straight line; The first color film region and the second color film region satisfy D3 < D4; Wherein, D3 is a distance from an intersection point of the first straight line and an edge of the first color film region to the adjacent second symmetry axis, and D4 is a distance from an intersection point of the first straight line and an edge of the second color film region to the adjacent second symmetry axis.

36. A display device comprising: The display panel comprises the display panel as claimed in any one of claims 1-35.

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