Display panel and display device

Abstract

The present application discloses a display panel and a display device. The display panel comprises: first light-emitting elements, second light-emitting elements, and third light-emitting elements that emit light of different colors; each first unit column comprises first light-emitting elements and second light-emitting elements that are alternately arranged in a first direction, each second unit column comprises a plurality of third light-emitting elements that are arranged in the first direction, and the first unit columns and the second unit columns are alternately arranged in a second direction; each first circuit column comprises a plurality of first pixel circuits arranged in the first direction, each second circuit column comprises a plurality of second pixel circuits arranged in the first direction, and each third circuit column comprises a plurality of third pixel circuits arranged in the first direction, the first pixel circuits are electrically connected to a first data line and the first light-emitting elements, the second pixel circuits are electrically connected to a second data line and the second light-emitting elements, and the third pixel circuits are electrically connected to a third data line and the third light-emitting elements. The embodiments of the present application can reduce power consumption of a driving chip.

Description

Display panel and display device

[0001] Cross-reference to Related Applications

[0002] This application claims priority to Chinese Patent Application No. 202411258996.6, filed on September 9, 2024, entitled “Display panel and display device”, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0003] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0004] With the development of display technology, the application of display panels is becoming more and more common, and users' requirements for the performance of display panels are also increasing. For example, users hope that the power consumption of display products can be lower and lower, therefore, how to reduce power consumption is an important problem that puzzles those skilled in the art.

[0005] SUMMARY

[0006] The embodiments of the present application provide a display panel and a display device, which can reduce power consumption.

[0007] In a first aspect, the embodiments of the present application provide a display panel, comprising: a light emitting element, comprising a first light emitting element, a second light emitting element and a third light emitting element, the light emitting colors of the first light emitting element, the second light emitting element and the third light emitting element are different, a first unit column comprises the first light emitting element and the second light emitting element arranged alternately in a first direction, a second unit column comprises a plurality of third light emitting elements arranged in the first direction, the first unit column and the second unit column are arranged alternately in a second direction, the first direction and the second direction intersect; a first circuit column, a second circuit column and a third circuit column, the first circuit column comprises a plurality of first pixel circuits arranged in the first direction, the second circuit column comprises a plurality of second pixel circuits arranged in the first direction, the third circuit column comprises a plurality of third pixel circuits arranged in the first direction, the first pixel circuit is electrically connected with a first data line and the first light emitting element, the second pixel circuit is electrically connected with a second data line and the second light emitting element, and the third pixel circuit is electrically connected with a third data line and the third light emitting element.

[0008] In a second aspect, the embodiments of the present application provide a display device, comprising the display panel according to the first aspect. BRIEF DESCRIPTION OF DRAWINGS

[0009] Other features, objects, and advantages of the present application will become more apparent from the following detailed description of non-limiting embodiments thereof as taken in conjunction with the accompanying drawings, in which like references denote like features, and in which:

[0010] FIG. 1 shows a structural schematic diagram of a display panel in a comparative example;

[0011] FIG. 2 shows a timing diagram of a signal on a data line in FIG. 1;

[0012] FIG. 3 shows a structural schematic diagram of a display panel provided by an embodiment of the present application;

[0013] FIG. 4 shows another structural schematic diagram of a display panel provided by an embodiment of the present application;

[0014] FIG. 5 shows still another structural schematic diagram of a display panel provided by an embodiment of the present application;

[0015] FIG. 6 shows a layout structural schematic diagram of a display panel corresponding to FIG. 3;

[0016] FIG. 7 shows a layout structural schematic diagram of an anode, a second metal layer and a third metal layer in FIG. 6;

[0017] FIG. 8 shows a layout structural schematic diagram of the anode in FIG. 6;

[0018] FIG. 9 shows a layout structural schematic diagram of the third metal layer in FIG. 6;

[0019] FIG. 10 shows a layout structural schematic diagram of the second metal layer in FIG. 6;

[0020] FIG. 11 shows a layout structural schematic diagram of the first metal layer in FIG. 6;

[0021] FIG. 12 shows a layout structural schematic diagram of a second gate layer corresponding to FIG. 6;

[0022] FIG. 13 shows a layout structural schematic diagram of a second semiconductor layer corresponding to FIG. 6;

[0023] FIG. 14 shows a layout structural schematic diagram of a capacitor metal layer corresponding to FIG. 6;

[0024] FIG. 15 shows a layout structural schematic diagram of a first gate layer corresponding to FIG. 6;

[0025] FIG. 16 shows a layout structural schematic diagram of a first semiconductor layer corresponding to FIG. 6;

[0026] FIG. 17 shows a layout structural schematic diagram of an auxiliary metal layer corresponding to FIG. 6;

[0027] FIG. 18 shows a cross-sectional structural schematic diagram of a display panel provided by an embodiment of the present application;

[0028] FIG. 19 shows a structural schematic diagram of a pixel circuit in a display panel provided by an embodiment of the present application;

[0029] FIG. 20 shows another layout structure diagram of the display panel corresponding to FIG. 3;

[0030] FIG. 21 shows a layout structure diagram of the anode, the second metal layer and the third metal layer in FIG. 20;

[0031] FIG. 22 shows a layout structure diagram of the anode in FIG. 20;

[0032] FIG. 23 shows a layout structure diagram of the third metal layer in FIG. 20;

[0033] FIG. 24 shows a layout structure diagram of the second metal layer in FIG. 20;

[0034] FIG. 25 shows a layout structure diagram of the first metal layer corresponding to FIG. 20;

[0035] FIG. 26 shows a layout structure diagram of the capacitor metal layer corresponding to FIG. 20;

[0036] FIG. 27 shows a layout structure diagram of the first gate layer corresponding to FIG. 20;

[0037] FIG. 28 shows a layout structure diagram of the first semiconductor layer corresponding to FIG. 20;

[0038] FIG. 29 shows another cross-sectional structure diagram of the display panel provided by the embodiment of the present application;

[0039] FIG. 30 shows another structure diagram of the pixel circuit in the display panel provided by the embodiment of the present application;

[0040] FIG. 31 shows another layout structure diagram of the display panel corresponding to FIG. 3;

[0041] FIG. 32 shows a layout structure diagram of the anode, the second metal layer and the third metal layer in FIG. 31;

[0042] FIG. 33 shows a layout structure diagram of the anode in FIG. 31;

[0043] FIG. 34 shows a layout structure diagram of the third metal layer in FIG. 31;

[0044] FIG. 35 shows a layout structure diagram of the second metal layer in FIG. 31;

[0045] FIG. 36 shows a layout structure diagram of the anode of the display panel corresponding to FIG. 4;

[0046] FIG. 37 shows a layout structure diagram of the display panel corresponding to FIG. 5;

[0047] FIG. 38 shows a layout structure diagram of the anode in FIG. 37;

[0048] FIG. 39 shows a layout structure diagram of the third metal layer in FIG. 37;

[0049] FIG. 40 shows a schematic diagram of a layout structure of the second metal layer in FIG. 37;

[0050] FIG. 41 shows another schematic diagram of a layout structure of the display panel corresponding to FIG. 5;

[0051] FIG. 42 shows a schematic diagram of a layout structure of the anode, the second metal layer and the third metal layer in FIG. 41;

[0052] FIG. 43 shows a schematic diagram of a layout structure of the anode in FIG. 41;

[0053] FIG. 44 shows a schematic diagram of a layout structure of the third metal layer in FIG. 41;

[0054] FIG. 45 shows a schematic diagram of a layout structure of the second metal layer in FIG. 41;

[0055] FIG. 46 shows a schematic diagram of a layout structure of the display panel corresponding to FIG. 5;

[0056] FIG. 47 shows a schematic diagram of a layout structure of the anode in FIG. 46;

[0057] FIG. 48 shows a schematic diagram of a layout structure of the third metal layer in FIG. 46;

[0058] FIG. 49 shows a schematic diagram of a layout structure of the second metal layer in FIG. 46;

[0059] FIG. 50 shows a schematic diagram of a layout structure of the display panel corresponding to FIG. 5;

[0060] FIG. 51 shows a schematic diagram of a layout structure of the anode in FIG. 50;

[0061] FIG. 52 shows a schematic diagram of a layout structure of the third metal layer in FIG. 50;

[0062] FIG. 53 shows a schematic diagram of a layout structure of the second metal layer in FIG. 50;

[0063] FIG. 54 shows a schematic diagram of a layout structure of the display panel corresponding to FIG. 5;

[0064] FIG. 55 shows a schematic diagram of a layout structure of the anode in FIG. 54;

[0065] FIG. 56 shows a schematic diagram of a layout structure of the third metal layer in FIG. 54;

[0066] FIG. 57 shows a schematic diagram of a layout structure of the second metal layer in FIG. 54;

[0067] FIG. 58 shows another schematic diagram of a structure of the display panel provided in the embodiments of the present application;

[0068] FIG. 59 shows a schematic diagram of a layout structure of the display panel corresponding to FIG. 58;

[0069] FIG. 60 shows a schematic diagram of a layout structure of the anode in FIG. 59;

[0070] FIG. 61 shows a schematic diagram of a layout structure of the anode in FIG. 59;

[0071] FIG. 62 shows a schematic diagram of a layout structure of the first metal layer in FIG. 59;

[0072] FIG. 63 shows a schematic diagram of a layout structure of the capacitor metal layer in FIG. 59;

[0073] FIG. 64 shows a schematic diagram of a layout structure of the first gate layer in FIG. 59;

[0074] FIG. 65 shows a schematic diagram of a layout structure of the first semiconductor layer in FIG. 59;

[0075] FIG. 66 shows a schematic diagram of a layout structure of the first semiconductor layer, the first gate layer and the capacitor metal layer in FIG. 59;

[0076] FIG. 67 shows a schematic diagram of a layout structure of the auxiliary metal layer in FIG. 59;

[0077] FIG. 68 shows a schematic diagram of another cross-sectional structure of a display panel according to an embodiment of the present application;

[0078] FIG. 69 shows a schematic diagram of another structure of a pixel circuit in a display panel according to an embodiment of the present application;

[0079] FIG. 70 shows a schematic diagram of another structure of a display panel according to an embodiment of the present application;

[0080] FIG. 71 shows a schematic diagram of another structure of a display panel according to an embodiment of the present application;

[0081] FIG. 72 shows a schematic diagram of a structure of a power supply branch in FIG. 71;

[0082] FIG. 73 shows a schematic diagram of a structure of a display device according to an embodiment of the present application. DETAILED DESCRIPTION

[0083] The features and exemplary embodiments of various aspects of the present application will be described in detail below with reference to the drawings. The following detailed description is merely provided to explain the present application in the form of examples and is not intended to limit the present application. The present application can be implemented without some of the specific details, which will be apparent to those skilled in the art. The following description of the embodiments is merely provided to provide a better understanding of the present application by showing examples of the present application.

[0084] It should be noted that, in the present document, relational terms such as first and second and the like can be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. The terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the presence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0085] It should be understood that when a layer, region or element is referred to as being "on" or "above" another layer, region or element, it can be directly on or above the other layer, region or element or intervening layers or regions can also be present. In addition, when an element is referred to as being "beneath" or "below" another element, it can be directly beneath or below the other element, or intervening layers or regions can also be present.

[0086] It should be understood that the term "and / or" as used herein merely means one or all of the associated listed items, for example, A and / or B can mean A alone, A and B together, or B alone.

[0087] In the embodiments of the present application, the term "electrically connected" can mean that two components are directly electrically connected or that two components are electrically connected via one or more other components. The term "drives" can mean "controls" or "operates". The term "part" can mean "portion". The term "pattern" can mean "member". The term "end" can mean "end section" or "end edge". The display panel can be a display device or a module / part of a display device.

[0088] Various modifications and changes can be made to the present application in matters of construction and arrangement of parts without departing from the scope of the present application, which is defined in the claims. Accordingly, all matters therein raised by way of examples are intended to be illustrative and not restrictive. The embodiments provided in the present application can be combined with each other without contradiction if possible.

[0089] Before the technical solutions provided by the embodiments of the present application are described, in order to facilitate the understanding of the embodiments of the present application, the present application first shows a comparative example. As shown in FIG. 1, it is a structural schematic diagram of a display panel in the comparative example, the display panel includes red sub-pixels R, green sub-pixels G and blue sub-pixels B, a data line DL1 is connected to the red sub-pixels R and the blue sub-pixels B located in the same column, and a data line DL2 is connected to the green sub-pixels G located in the same column. The data line is used to provide a data signal to the sub-pixel. The data line is connected with a driving chip (not shown in the figure), and the driving chip is used to generate the data signal.

[0090] Taking the display of a pure color picture (such as a pure red picture or a pure blue picture) by the display panel as an example, as shown in FIG. 2, the voltage on the data line DL1 will fluctuate back and forth, resulting in an increase in the power consumption of the driving chip connected with the data line.

[0091] To solve the above technical problems, the embodiments of the present application provide a display panel and a display device. The various embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0092] As shown in FIGS. 3 to 5, the display panel provided by the embodiments of the present application includes a light emitting element 10, a pixel circuit 20 and a data line 30.

[0093] Exemplarily, the light emitting element 10 includes an organic light emitting diode (OLED). The light emitting element 10 includes an anode, a light emitting layer and a cathode. In the drawings of the present application, the position of the light emitting element can be understood as the position of the anode of the light emitting element.

[0094] The data line 30 is electrically connected with the pixel circuit 20, and the data line 30 is used to provide a data signal to the pixel circuit 20. The pixel circuit 20 generates a certain driving current based on the data signal from the data line 30, and the driving current is used to drive the light emitting element 10.

[0095] The data line 30 is electrically connected with a driving chip (not shown in the figure), and the driving chip is used to generate the data signal and transmit it to the data line 30.

[0096] The light emitting element 10 includes a first light emitting element 11, a second light emitting element 12 and a third light emitting element 13, and the light emitting colors of the first light emitting element 11, the second light emitting element 12 and the third light emitting element 13 are different.

[0097] The first unit column 10a includes the first light emitting element 11 and the second light emitting element 12 arranged alternately in the first direction X, and the second unit column 10b includes a plurality of third light emitting elements 13 arranged in the first direction X. The first unit column 10a and the second unit column 10b are arranged alternately in the second direction Y, and the first direction X and the second direction Y intersect. For example, the first direction X is a column direction, and the second direction Y is a row direction.

[0098] As an example, as shown in FIGS. 3 to 5, the first light emitting element 11 is a red light emitting element, the second light emitting element 12 is a blue light emitting element, and the third light emitting element 13 is a green light emitting element. In this example, the red light emitting element and the blue light emitting element are arranged alternately in a column, and the green light emitting element is arranged in another column.

[0099] As another example, the first light emitting element 11 is a red light emitting element, the second light emitting element 12 is a green light emitting element, and the third light emitting element 13 is a blue light emitting element, which will be illustrated in subsequent drawings. In this example, the red light emitting element and the green light emitting element are arranged alternately in a column, and the blue light emitting element is arranged in another column.

[0100] It should be noted that the light emitting colors of the first light emitting element and the second light emitting element can be interchangeable.

[0101] For example, the three kinds of light emitting elements each include an anode, a light emitting layer, and a cathode arranged in a stack, and the anode of the light emitting element is electrically connected to the pixel circuit through a via (one end of the via extends to the film layer where the anode is located and is overlapped with the anode or the anode and the via are connected through a wire).

[0102] The pixel circuit 20 includes a first pixel circuit 21, a second pixel circuit 22, and a third pixel circuit 23. It should be noted that in the drawings of the present application marked with pixel circuits, the approximate positions of the pixel circuits are illustrated with dashed boxes.

[0103] The plurality of pixel circuits 20 form a first circuit column 20a, a second circuit column 20b, and a third circuit column 20c. The first circuit column 20a includes a plurality of first pixel circuits 21 arranged in the first direction X, the second circuit column 20b includes a plurality of second pixel circuits 22 arranged in the first direction X, and the third circuit column 20c includes a plurality of third pixel circuits 23 arranged in the first direction X.

[0104] It can be understood that the second pixel circuit 22 and the third pixel circuit 23 are not included in the first circuit column 20a, the first pixel circuit 21 and the third pixel circuit 23 are not included in the second circuit column 20b, and the first pixel circuit 21 and the second pixel circuit 22 are not included in the third circuit column 20c.

[0105] The first pixel circuit 21 is electrically connected with the first data line 31 and the first light emitting element 11, the second pixel circuit 22 is electrically connected with the second data line 32 and the second light emitting element 12, and the third pixel circuit 23 is electrically connected with the third data line 33 and the third light emitting element 13.

[0106] From the perspective of transmitting data signals, the first data line 31 is only used for transmitting data signals required by the first light emitting element 11, the second data line 32 is only used for transmitting data signals required by the second light emitting element 12, and the third data line 33 is only used for transmitting data signals required by the third light emitting element 13.

[0107] For example, when displaying a pure color picture corresponding to the first light emitting element 11, the first data line 31 only needs to transmit data signals required by the first light emitting element 11, and does not need to transmit data signals required by the second light emitting element 12, so that the first data line 31 does not need to provide varying data signals. Similarly, when displaying a pure color picture corresponding to the second light emitting element 12, the second data line 32 only needs to transmit data signals required by the second light emitting element 12, and does not need to transmit data signals required by the first light emitting element 11, so that the second data line 32 does not need to provide varying data signals.

[0108] According to the display panel provided by the embodiment of the present application, one data line is used to provide data signals required by light emitting elements of the same light emitting color, so that the data signals on the data line do not need to jump during the process of displaying a pure color picture, thereby reducing the power consumption of a driving chip connected with the data line.

[0109] It should be noted that in FIGS. 3 to 5, the first data line 31 and the first circuit column 20a are overlapped to represent that each first pixel circuit 21 in the first data line 31 and the first circuit column 20a is electrically connected, the second data line 32 and the second circuit column 20b are overlapped to represent that each second pixel circuit 22 in the second data line 32 and the second circuit column 20b is electrically connected, and the third data line 33 and the third circuit column 20c are overlapped to represent that each third pixel circuit in the third data line 33 and the third circuit column 20c is electrically connected. One end of the wire 01 points to the first light emitting element 11, and the other end points to the first data line 31, which is used to represent that the first data line 31 is used to provide data signals required by the first light emitting element 11, rather than limiting that the first light emitting element 11 and the first data line 31 are electrically connected through the wire 01. The wires 02 and 03 are the same, and details are not described herein. In addition, in order to distinguish the marking lines and the structure of the display panel, the marking lines extending into the dashed line width are provided with arrows, for example, the marking lines corresponding to 11, 12 and 13 are provided with arrows.

[0110] As an example, as shown in FIG. 3, (i)-(i+3) and (j)-(j+3) represent 8 unit columns, and 9 circuit columns are shown, wherein the (i)th, (i+1)th, (i+2)th, and (i+3)th unit columns are 4 first unit columns 10a, and the (j)th, (j+1)th, (j+2)th, and (j+3)th unit columns are 4 second unit columns 10b. 20a1, 20a2, 20a3 represent 3 first circuit columns 20a, 20b1, 20b2 represent 2 second circuit columns 20b, and 20c1, 20c2, 20c3, 20c4 represent 4 third circuit columns 20c.

[0111] FIG. 3, the relative positional relationship between the third light emitting element 13 and the pixel circuit connected thereto does not change, and the difference includes:

[0112] The first pixel circuit 21 in the 1st first circuit column 20a1 is used to drive the first light emitting element 21 in the (i)th first unit column 10a, the first pixel circuit 21 in the 2nd first circuit column 20a2 is used to drive the first light emitting element 21 in the (i+1)th and (i+2)th first unit columns 10a, and the first pixel circuit 21 in the 3rd first circuit column 20a3 is used to drive the first light emitting element 21 in the (i+3)th first unit column 10a.

[0113] The second pixel circuit 22 in the 1st second circuit column 20b1 is used to drive the second light emitting element 22 in the (i)th and (i+1)th first unit columns 10a, and the second pixel circuit 22 in the 2nd second circuit column 20b is used to drive the second light emitting element 22 in the (i+2)th and (i+3)th first unit columns 10a.

[0114] The number of pixel circuit columns in FIG. 3 is one more than the number of light emitting element columns, wherein the 1st first circuit column 20a1 and the 3rd first circuit column 20a3 include dummy pixel circuits dummy, which are not connected to light emitting elements, i.e., the dummy pixel circuits dummy are not used to drive light emitting elements.

[0115] It should be noted that the number of pixel circuit columns here refers to that at least one pixel circuit in the pixel circuit column is connected to a light emitting element. For example, the display panel can further include a dummy pixel circuit column, wherein the dummy pixel circuits in the dummy pixel circuit column are not used to drive light emitting elements.

[0116] As another example, as shown in FIG. 4, the same as FIG. 3 will not be described again, and the difference includes:

[0117] The first pixel circuit 21 in the first first-circuit column 20a1 is configured to drive the first light emitting element 11 in the (i)th and (i+1)th first unit columns 10a, and the first pixel circuit 21 in the second first-circuit column 20a2 is configured to drive the first light emitting element 11 in the (i+2)th and (i+3)th first unit columns 10a.

[0118] The second pixel circuit 22 in the first second-circuit column 20b1 is configured to drive the second light emitting element 12 in the (i)th first unit column 10a, the second pixel circuit 22 in the second second-circuit column 20b2 is configured to drive the second light emitting element 12 in the (i+1)th and (i+2)th first unit columns 10a, and the second pixel circuit 22 in the third second-circuit column 20b3 is configured to drive the second light emitting element 12 in the (i+3)th first unit column 10a.

[0119] The number of the pixel circuit columns in FIG. 4 is one more than the number of the light emitting element columns, wherein the first second-circuit column 20b1 and the third second-circuit column 20b3 include dummy pixel circuits.

[0120] As another example, as shown in FIG. 5, the same as FIG. 3 and FIG. 4 will not be repeated, and the difference includes:

[0121] The first pixel circuit 21 in the first first-circuit column 20a1 is configured to drive the first light emitting element 21 in the (i)th and (i+1)th first unit columns 10a, and the first pixel circuit 21 in the second first-circuit column 20a2 is configured to drive the first light emitting element 21 in the (i+2)th and (i+3)th first unit columns 10a.

[0122] The second pixel circuit 22 in the first second-circuit column 20b1 is configured to drive the second light emitting element 22 in the (i)th and (i+1)th first unit columns 10a, and the second pixel circuit 22 in the second second-circuit column 20b2 is configured to drive the second light emitting element 22 in the (i+2)th and (i+3)th first unit columns 10a.

[0123] The number of the pixel circuit columns in FIG. 5 is equal to the number of the light emitting element columns. None of the circuit columns in FIG. 5 includes a dummy pixel circuit.

[0124] It should be noted that FIG. 3 to FIG. 5 are not used to limit the present application, and in other embodiments, the arrangement structure of the light emitting elements of the display panel can also be other manners, or the arrangement structure of the pixel circuits can also be other manners, as long as the same column unit column includes light emitting elements of different colors, and the same color light emitting elements can be connected by the data line to reduce the power consumption of the driving chip.

[0125] As shown in FIGS. 3-5, for the first circuit column without dummy virtual pixel circuit, the first circuit column needs to electrically connect the first light emitting elements located in two unit columns. For at least part of the first light emitting elements, a connecting line is needed to connect the first light emitting elements and the first pixel circuit. The longer the connecting line is, the greater the voltage drop is, which will affect the driving capability of the first pixel circuit to the first light emitting elements. Similarly, the same situation exists for the second light emitting elements and the second pixel circuit electrically connected thereto. Therefore, while reducing power consumption, how to balance the driving capability of the pixel circuit is also important.

[0126] To this end, in some embodiments, as shown in FIG. 3 or FIG. 4, the number of pixel circuit columns in the display panel is greater than the number of light emitting element columns, and the virtual pixel circuit is included in part of the circuit columns. FIGS. 6-8 show schematic diagrams of the arrangement of the connecting vias between the light emitting elements and the pixel circuits. In FIGS. 6, 7, 8 and the subsequent schematic diagrams, the approximate positions of the plurality of circuit columns are shown by vertical dashed lines. In order to avoid too many dashed lines, the approximate positions of each pixel circuit are not framed by a dashed line. It can be understood that one circuit column between two vertical dashed lines includes a plurality of pixel circuits.

[0127] Please refer to FIGS. 3, 6, 7 and 8, the first light emitting element 11 is electrically connected to the first pixel circuit 21 through the first via 41. The first end of the first via 41 extends to the film layer where the anode of the first light emitting element 11 is located, and the second end of the first via 41 is electrically connected to the first pixel circuit 21. The plurality of first vias 41 corresponding to the same first circuit column 20a form a first via column 41a. For the first circuit column not including the virtual pixel circuit, in the second direction Y, the plurality of first light emitting elements 11 electrically connected to the first pixel circuit through the vias in the same first via column 41a are located on both sides of the first via column 41a, respectively. In the figure, the plurality of first vias located in the same column are framed by a dashed line to represent the first via column, and the plurality of second vias located in the same column are framed by another dashed line to represent the second via column.

[0128] For example, in FIG. 7, there are 4 first unit columns 10a from i to i+3, 4 second unit columns 10b from j to j+3, 8 pixel circuit columns and 8 circuit columns. The first unit column 10a includes the first light emitting element 11 and the second light emitting element 12 arranged alternately in the first direction X. For example, the first light emitting element 11 is a red light emitting element, and the second light emitting element 12 is a blue light emitting element. The second unit column 10b includes the third light emitting element 13 arranged alternately in the first direction X. For example, the third light emitting element 13 is a green light emitting element.

[0129] The first circuit column 20a includes a plurality of first pixel circuits 21 arranged along the first direction, and the first pixel circuits 21 are configured to drive the first light emitting elements 11. The second circuit column 20b includes a plurality of second pixel circuits 22 arranged along the first direction, and the second pixel circuits 22 are configured to drive the second light emitting elements 12. The third circuit column 20c includes a plurality of third pixel circuits 23 arranged along the first direction, and the third pixel circuits 23 are configured to drive the third light emitting elements 13.

[0130] Taking the second first circuit column 20a2 in FIG. 6 and FIG. 7 as an example, the second first circuit column 20a2 does not include a virtual pixel circuit, and the second first circuit column 20a2 is configured to drive the first light emitting elements 11 in the (i+1)th first unit column 10a and the (i+2)th first unit column 10a, and the first via hole 41 of the first light emitting element 11 in the (i+1)th first unit column 10a is located at the right side of the first light emitting element, and the first via hole 41 of the first light emitting element 11 in the (i+2)th first unit column 10a is located at the left side of the first light emitting element. That is, the first via holes of the first light emitting elements connected to the same first circuit column and located in the two first unit columns are all arranged towards the direction close to the first circuit column, so that the length of the connection line between the first light emitting element and the first pixel circuit can be shortened, thereby avoiding large voltage drop caused by the too long connection line, and thus achieving the reduction of power consumption while considering the driving capability of the first pixel circuit.

[0131] For example, referring to FIG. 6 to FIG. 8, for the first circuit column including a virtual pixel circuit, taking the first first circuit column 20a1 as an example, the first first circuit column 20a1 is configured to drive the first light emitting elements 11 in the (i)th first unit column 10a, and the plurality of first via holes 41 of the (i)th first unit column 10a are located on the same side of the (i)th first unit column 10a.

[0132] The second light emitting element 12 is electrically connected to the second pixel circuit 22 through the second via hole 42, and the plurality of second via holes 42 corresponding to the same second circuit column 20b constitute a second via hole column 42a. The first end of the second via hole 42 extends to the film layer where the anode of the second light emitting element 12 is located, and the second end of the second via hole 42 is electrically connected to the second pixel circuit 22. For the second circuit column not including a virtual pixel circuit, in the second direction Y, the plurality of second light emitting elements 12 electrically connected to the second pixel circuit 22 through the via holes on the same second via hole column 42a are respectively located on both sides of the second via hole column 42a.

[0133] For example, the first second-circuit column 20b1 does not include a dummy pixel circuit, and is configured to drive the second light emitting elements 12 in the (i)th first unit column 10a and the (i+1)th first unit column 10a. The second via hole 42 of the second light emitting element 12 in the (i)th first unit column 10a is located at the right side of the second light emitting element, and the second via hole 42 of the second light emitting element 12 in the (i+1)th first unit column 10a is located at the left side of the second light emitting element. That is, the second via holes of the second light emitting elements in the two first unit columns connected to the same second-circuit column are both arranged towards the direction close to the second-circuit column, so that the length of the connection line between the second light emitting element and the second pixel circuit can be shortened, thereby avoiding large voltage drop caused by too long connection line, and achieving low power consumption while ensuring the driving capability of the second pixel circuit.

[0134] For the first-circuit column including a dummy pixel circuit, the corresponding multiple first via holes are located at the same side of the first-circuit column. For example, the first first-circuit column 20a1 in FIG. 6 includes a dummy pixel circuit, and the corresponding first via holes are all located at the left side of the first first-circuit column 20a1.

[0135] For the second-circuit column including a dummy pixel circuit, the corresponding multiple second via holes are located at the same side of the second-circuit column.

[0136] In some embodiments, as shown in FIGS. 6-8, for the same first unit column 10a, the first via hole 41 and the second via hole 42 are located at the two sides of the first unit column 10a in the second direction Y.

[0137] For example, in the (i)th first unit column 10a, the multiple first via holes 41 are all located at the left side of the (i)th first unit column 10a, and the multiple second via holes 42 are all located at the right side of the (i)th first unit column 10a.

[0138] For example, in the (i)th first unit column 10a, the multiple first via holes 41 are all located at the left side of the (i)th first unit column 10a, and the multiple second via holes 42 are all located at the right side of the (i)th first unit column 10a.

[0139] Since the first light emitting elements 11 and the second light emitting elements 12 in the first unit column 10a are alternately arranged in the second direction Y, the first via holes 41 and the second via holes 42 are alternately arranged at the two sides of the first unit column 10a, which avoids the corresponding via holes of the first unit column 10a being too dense due to being arranged at the same side, and thus the via holes do not need to occupy too much layout space, which is beneficial to improving the pixel density. Therefore, the embodiments of the present application are beneficial to improving the pixel density and improving the signal interference between different via holes.

[0140] In some embodiments, referring to FIG. 8, the first light emitting elements 11 and the second light emitting elements 12 are arranged alternately in the second direction Y to form first unit rows 10c. In FIG. 8, (e)~(e+3) are marked beside the mark 10c, where (e) represents the (e)th first unit row 10c, (e+1) represents the (e+1)th first unit row 10c, (e+2) represents the (e+2)th first unit row 10c, and (e+3) represents the (e+3)th first unit row 10c.

[0141] The plurality of third light emitting elements 13 are arranged in the second direction Y to form second unit rows, and the first unit rows and the second unit rows are arranged alternately in the first direction.

[0142] For the same first unit row 10c, the relative position relationship between the first via hole 41 and the first light emitting element 11 and the relative position relationship between the second via hole 42 and the second light emitting element 12 are the same in the second direction Y. That is, for the same unit row, the first via hole and the second via hole are both located on the same side of the first light emitting element or the second light emitting element to which they are electrically connected.

[0143] For example, in the (e)th and the (e+2)th first unit rows 10c, the first via holes 41 are all on the left side of the first light emitting elements 11 to which they are connected. For another example, in the (e+1)th and the (e+3)th first unit rows 10c, the first via holes 41 are all on the right side of the first light emitting elements 11 to which they are connected.

[0144] In this example, in the same first unit row 10c, the first via holes 41 and the first light emitting elements 11 to which they are electrically connected are arranged according to the same position rule, so that the driving capability of each first light emitting element 11 in the same row is equivalent, which is conducive to improving display uniformity.

[0145] For example, in the (e)th and the (e+2)th first unit rows 10c, the second via holes 42 are on the left side of the second light emitting elements 12 to which they are electrically connected. For another example, in the (e+1)th and the (e+3)th first unit rows 10c, the second via holes 42 are on the right side of the second light emitting elements 12 to which they are electrically connected.

[0146] Similarly, in the same first unit row 10c, the second via holes 42 and the second light emitting elements 12 to which they are electrically connected are arranged according to the same position rule, so that the driving capability of each second light emitting element 12 in the same row is equivalent, which is conducive to improving display uniformity.

[0147] It should be noted that “left side” and “right side” in this article represent two different sides, and are not used to absolutely limit the left side or the right side.

[0148] Further, the relative position relationship between the first via hole 41 and the first light emitting element 11 and the relative position relationship between the second via hole 42 and the second light emitting element 12 are the same, so that for the same first unit row, the first via hole and the second via hole can be prevented from being adjacent to each other to cause the via hole to be too dense. For adjacent first unit rows, the first via hole and the second via hole are located on different sides of the first light emitting element and the second light emitting element in different first unit rows. For example, in the (e) first unit row 10c in FIG. 8, the first via hole 41 and the second via hole 42 are both located on the first side of the first light emitting element 11 and the second light emitting element 12 electrically connected thereto, while in the (e+2) first unit row 10c adjacent to the (e) first unit row 10c, the first via hole 41 and the second via hole 42 are both located on the second side of the first light emitting element 11 and the second light emitting element 12 electrically connected thereto. Such arrangement is conducive to connecting the first light emitting elements in adjacent first unit columns to the same circuit column.

[0149] In some embodiments, as shown in FIGS. 6-18, the display panel can include at least two semiconductor layers. For example, referring to FIG. 18, the display panel includes a first semiconductor layer B1 and a second semiconductor layer B2. As an example, the material of the first semiconductor layer B1 includes Low Temperature Poly-Silicon (LTPS), and the material of the second semiconductor layer B2 includes Indium Gallium Zinc Oxide (IGZO), and the display panel is a Low Temperature Polycrystalline Oxide (LTPO) type display panel. The carrier moving speed of the LTPS type transistor is faster, and the leakage current of the IGZO type transistor is smaller.

[0150] For example, the structure of the pixel circuit can be as shown in FIG. 19, where the driving transistor T3 can be an LTPS type transistor, and the threshold compensation transistor T4 and the reset transistor T5 can be IGZO type transistors. It should be noted that the structure of the pixel circuit shown in FIG. 19 and subsequent drawings is only some examples and is not intended to limit the present application.

[0151] As shown in FIG. 18, the display panel can further include an auxiliary metal layer M0, a first gate layer GAT, a capacitor metal layer MC, a second gate layer MG, a first metal layer SD1, a second metal layer SD2, a third metal layer SD3, and an anode layer RE. The relative positions of the various film layers are shown in FIG. 18, and will not be described again here. It should be noted that the auxiliary metal layer M0 can be provided as needed, and in some examples, the auxiliary metal layer M0 can also not be provided. Similarly, the second metal layer SD2 and the third metal layer SD3 can be provided as needed, and in some examples, the second metal layer SD2 and the third metal layer SD3 can also not be provided. It can be understood that the first gate layer GAT, the capacitor metal layer MC, and the second gate layer MG are also metal layers, and the first metal layer, the second metal layer, and the third metal layer in this context are merely names for different metal layers, and do not serve to limit the order of the metal layers.

[0152] Corresponding to the film layer structure shown in FIG. 18 and the circuit structure shown in FIG. 19, FIGS. 8-17 show the layout structures of the various film layers in order from top to bottom. Among them, FIG. 8 is the layout structure of the anode layer RE, the anode of the light emitting element is provided on the anode layer RE, and the connecting lines between the light emitting element and the pixel circuit can also be provided at least partially on the anode layer RE. FIG. 9 is the layout structure of the third metal layer SD3, which can include wires extending along the second direction Y, such as the power branch lines 612, 624. FIG. 10 is the layout structure of the second metal layer SD2, which can include wires extending along the first direction X, such as the data lines 31-33, the power branch lines 611, 623, 635, and the wires 91, 92. FIG. 11 is the layout structure of the first metal layer SD1, which can include wires extending along the second direction, such as the second line segments 72 for connecting the data lines. FIG. 12 is the layout of the second gate layer MG, which can include scan lines S1N, S2N extending along the second direction. FIG. 13 is the layout structure of the second semiconductor layer B2, which can include the active layers of transistors, such as the active layers of the transistors T4, T5 in FIG. 19, which are provided on the second semiconductor layer B2. FIG. 14 is the layout structure of the capacitor metal layer MC, which includes scan lines S1N, S2N extending along the second direction, as well as reset signal lines Vref1, Vref2, and one plate of a storage capacitor. FIG. 15 is the layout structure of the first gate layer GAT, which includes scan lines SP, SP* extending along the second direction, as well as light emitting control signal lines EM. FIG. 16 shows the layout structure of the first semiconductor layer B1, which can include the active layers of transistors, such as the active layers of the transistors T1-T3, T6-T8 in FIG. 19, which are provided on the first semiconductor layer B1. FIG. 17 shows the layout structure of the auxiliary metal layer M0, and the wire structure within the auxiliary metal layer M0 can shade the active layers of the transistors to stabilize the characteristics of the transistors.

[0153] The anode of each light emitting element is disposed in the anode layer RE, the pixel definition layer PDL includes a pixel opening KK, and the light emitting layer (not shown in FIG. 18) of the light emitting element is disposed in the opening KK, and the cathode (not shown in FIG. 18) of the light emitting element covers the light emitting layer.

[0154] As shown in FIGS. 8 and 9, the anode of the first light emitting element 11 is electrically connected to the first end of the first via hole 41 through the first connecting line 51, the second end of the first via hole 41 is electrically connected to the first pixel circuit, and the first connecting line 51 and the anode of the first light emitting element 11 are located in the same film layer. The first connecting line 51 and the anode of the first light emitting element 11 are both located in the anode layer RE shown in FIG. 18. The anode of the first light emitting element 11 is the light emitting region of the first light emitting element, and the first connecting line 51 can be a non-light emitting region. Alternatively, in the thickness direction of the display panel, the anode of the first light emitting element 11 overlaps the opening KK, and the first connecting line 51 does not overlap the opening KK.

[0155] The anode of the second light emitting element 12 is electrically connected to the first end of the second via hole 42 through the second connecting line 52, the second end of the second via hole 42 is electrically connected to the second pixel circuit, and the second connecting line 52 and the anode of the second light emitting element 12 are located in the same film layer. The second connecting line 52 and the anode of the second light emitting element 12 are both located in the anode layer RE shown in FIG. 18. The anode of the second light emitting element 12 is the light emitting region of the second light emitting element, and the second connecting line 52 can be a non-light emitting region. Alternatively, in the thickness direction of the display panel, the anode of the second light emitting element 12 overlaps the opening KK, and the second connecting line 52 does not overlap the opening KK.

[0156] As introduced above, the plurality of first light emitting elements connected by the first circuit column are alternately distributed on both sides, so that the first light emitting elements are relatively close to the first pixel circuits required to be connected, and in the LTPO pixel circuit, two adjacent pixel circuits in the second direction are designed in a mirror image. Such a design makes the length of the first connecting line between the first light emitting element and the first pixel circuit not too long, so that the film layer where the light emitting element is located has space to set the first connecting line, without the need to change the line, which can avoid increasing the process difficulty. The second connecting line is the same, which will not be described here.

[0157] In some embodiments, referring to FIG. 8, the length of the first connecting line 51 is less than the maximum width of the first light emitting element 11 along the second direction Y, and the length of the second connecting line 50 is less than the maximum width of the second light emitting element 12 along the second direction Y. That is, the anode of the light emitting element does not need to be provided with a wire winding around the anode, and the short length of the connecting line can reduce the influence of voltage drop, and it is not necessary to wind the connecting line from one end of the light emitting element to the other end, which can avoid problems such as short circuit caused by the length of the connecting line on the anode layer being too long.

[0158] In some embodiments, as shown in FIG. 8, the first connection lines 51 and the second connection lines 52 extend in directions intersecting with each other for the same unit column. For example, the first connection line 51 and the second connection line 52 corresponding to the (i)th unit column 10a extend in directions intersecting with each other. The intersection of the two connection lines can facilitate the setting of a shorter length of the connection line.

[0159] The architecture shown in FIG. 3 can also be implemented by the specific structure shown in FIGS. 20-30. The display panel in the structure shown in FIGS. 20-30 includes one semiconductor layer. For example, as shown in FIG. 29, the display panel includes a first semiconductor layer B1. For example, the material of the first semiconductor layer B1 includes LTPS, and as shown in FIG. 30, each transistor of the pixel circuit is an LTPS transistor. In addition, by comparison with FIG. 29 and FIG. 18, the film layer structure shown in FIG. 29 does not include the second semiconductor layer B2 and the second gate layer MG. Corresponding to the film layer structure shown in FIG. 29 and the circuit structure shown in FIG. 30, FIGS. 22-27 schematically show the layout structure of each film layer in order from top to bottom. Among them, FIG. 22 is the layout structure of the anode layer RE, the anode of the light emitting element is arranged on the anode layer RE, and the connection line between the light emitting element and the pixel circuit can also be at least partially arranged on the anode layer RE. FIG. 23 is the layout structure of the third metal layer SD3, which can include wires extending along the second direction Y, for example, the power supply branch lines 612, 624. FIG. 24 is the layout structure of the second metal layer SD2, which can include wires extending along the first direction X, for example, the data lines 31-33, the power supply branch lines 611, 623, 635. FIG. 25 is the layout structure of the first metal layer SD1, which can include wires extending along the first direction, for example, the reset signal lines Vref1, Vref2, the power supply branch lines 617, 628, 639. FIG. 26 is the layout structure of the capacitor metal layer MC, which includes the reset signal lines Vref1, Vref2 extending along the second direction and one plate of the storage capacitor. FIG. 27 is the layout structure of the first gate layer GAT, which includes the scan lines S1, S2 extending along the second direction and the light emitting control signal line EM. FIG. 28 shows the layout structure of the first semiconductor layer B1, which can include the active layer of the transistors, for example, the active layers of the transistors M1-M7 in FIG. 28 are arranged on the first semiconductor layer B1. It can be understood that the auxiliary metal layer M0 shown in FIG. 29 can also be provided with a wire structure, and the wire structure in the auxiliary metal layer M0 can shield the active layer of the transistors to stabilize the characteristics of the transistors.

[0160] For the LTPS display panel, a non-mirror design is adopted. Even if the multiple first light emitting elements connected by the first circuit column are alternately distributed on both sides, and the first light emitting elements are closer to the first pixel circuit to which they are connected, in the non-mirror design, there are still some first light emitting elements that are relatively far away from the first pixel circuit to which they are connected. If the connection line is still completely arranged on the anode film layer, the connection line needs to bypass the anodes of other color light emitting elements, which makes the length of the connection line longer, and increases the voltage drop of the connection line, resulting in the weakening of the driving ability of the first pixel circuit to the first light emitting element. In addition, if the connection line is completely arranged on the anode, the distance between the connection line and the anode of other light emitting elements is close, which increases the risk of short circuit between different light emitting elements. The same applies to the second light emitting element, which will not be described here.

[0161] To this end, the first connection line and the second connection line can be designed in a cross-line manner (the cross-line includes a wire arranged on at least two film layers).

[0162] For example, as shown in FIG. 21, the first light emitting element 11 is correspondingly provided with a first connection line 51, and the first connection line 51 is used to connect the first light emitting element 11 and the first pixel circuit. The second light emitting element 12 is correspondingly provided with a second connection line 52, and the second connection line 52 is used to connect the second light emitting element 12 and the second pixel circuit.

[0163] The first connection line 51 includes a first segment 511 and a second segment 512. The first segment 511 is connected between the anode of the first light emitting element 11 and the first end of the first via hole 41. The second segment 512 is connected between the second end of the first via hole 41 and the first pixel circuit.

[0164] The second connection line 52 includes a third segment 523 and a fourth segment 524. The third segment 523 is connected between the anode of the second light emitting element 12 and the first end of the second via hole 42. The fourth segment 524 is connected between the second end of the second via hole 42 and the second pixel circuit.

[0165] The length of the first connection line 51 corresponding to the (i)th and (i+2)th first unit columns 10a is less than the length of the first connection line 51 corresponding to the (i+1)th and (i+3)th first unit columns 10a.

[0166] The length of the second connection line 52 corresponding to the (i)th and (i+2)th first unit columns 10a is greater than the length of the second connection line 52 corresponding to the (i+1)th and (i+3)th first unit columns 10a.

[0167] Specifically, please refer to FIG. 21, 22 and 23, the display panel includes a first connection line 51 and a second connection line 52, the first connection line 51 includes a first segment 511 and a second segment 512, the first segment 511 is connected between the anode of the first light emitting element 11 and the first end of the first via hole 41, the second segment 512 is connected between the second end of the first via hole 41 and the first pixel circuit, the first segment 511 and the anode of the first light emitting element 11 are located in the same film layer, and the second segment 512 is located in the metal layer on the side of the anode of the first light emitting element 11 facing the substrate.

[0168] The second connection line 52 includes a third segment 523 and a fourth segment 524, the third segment 523 is connected between the anode of the second light emitting element 12 and the first end of the second via hole 42, the fourth segment 524 is connected between the second end of the second via hole 42 and the second pixel circuit, the third segment 523 and the anode of the second light emitting element 12 are located in the same film layer, and the fourth segment 524 is located in the metal layer on the side of the anode of the second light emitting element 12 facing the substrate.

[0169] In the embodiments of the present application, since the second segment 512 and the fourth segment 524 are located in the metal layer below the anode, the length of the connection line in the anode film layer can be reduced, and the connection line in the metal layer is less constrained by the anode, so the connection line can be arranged in a near-connection manner, the second segment 512 and the fourth segment 524 are both straight lines, and do not need to be windingly arranged due to the constraint of the anode, so the total length of the first connection line and the total length of the second connection line can be reduced as a whole.

[0170] In some embodiments, please refer to FIG. 22, 23, 24 and 29, the display panel includes data lines, the data lines include a first data line 31, a second data line 32 and a third data line 33, and the three types of data lines are located in the same film layer. In the thickness direction of the display panel, the film layer where the second segment 512 and the fourth segment 524 are located is between the film layer where the data lines are located and the anode of the light emitting element.

[0171] For example, please refer to FIG. 24 and 29, the data lines 31, 32 and 33 are located in the second metal layer SD2, please refer to FIG. 23 and 29, the second segment 512 and the fourth segment 524 are located in the third metal layer SD3, and the anode of each type of light emitting element is located in the anode layer RE shown in FIG. 29. The third metal layer SD3 is located between the second metal layer SD2 and the anode layer RE. That is, in the thickness direction of the display panel, the second segment 512 and the fourth segment 524 are closer to the anode of the light emitting element, so that the second segment 512 and the fourth segment 524 can be connected to the anode of the corresponding light emitting element.

[0172] It should be noted that the implementation of FIG. 3 is not limited to the examples shown in FIGS. 6-30, and in other examples, the architecture shown in FIG. 3 can also be implemented by the specific structures shown in FIGS. 31-35. For example, the cross-sectional structure of the display panel corresponding to the structures shown in FIGS. 31-35 can also be as shown in FIG. 18, and the structure in the layout shown in FIG. 34 is located in the third metal layer SD3 shown in FIG. 18, and the structure in the layout shown in FIG. 35 is located in the second metal layer SD2 shown in FIG. 18.

[0173] The structures shown in FIGS. 31-35 are the same as the structures shown in FIGS. 6-19, and the differences include that the traces of the second metal layer and the third metal layer are interchanged. For example, in the structures shown in FIGS. 6-19, the traces extending in the first direction X are provided in the second metal layer SD2, and the traces extending in the second direction Y are provided in the third metal layer SD3. In the structures shown in FIGS. 31-35, the traces extending in the first direction X are provided in the third metal layer SD3, and the traces extending in the second direction Y are provided in the second metal layer SD2.

[0174] For example, as shown in FIGS. 8, 22, and 33, the layout of the anode layer can be substantially similar. FIG. 34 is a layout structure of the third metal layer SD3, which can include traces extending in the first direction X, such as the data lines 31-33, the power supply branch lines 611, 623, 635, and the traces 91, 92. FIG. 35 is a layout structure of the second metal layer SD2, which can include traces extending in the second direction Y, such as the power supply branch lines 612, 624.

[0175] In some embodiments, referring to FIGS. 6, 20, or 31, in the thickness direction of the display panel, the first circuit column 20a at least partially overlaps with at least part of the plurality of first light emitting elements 11 connected thereto, and the second circuit column 20b at least partially overlaps with at least part of the plurality of second light emitting elements 12 connected thereto.

[0176] For example, for the first circuit column 20a that does not include a virtual pixel circuit, the plurality of first light emitting elements 11 connected to the first circuit column 20a are alternately distributed on both sides thereof, and the first circuit column 20a at least partially overlaps with the first light emitting elements 11 on the second side.

[0177] For another example, the plurality of second light emitting elements 12 connected to the second circuit column 20b are alternately distributed on both sides thereof, and the second circuit column 20b at least partially overlaps with the second light emitting elements 12 on the second side.

[0178] In the case where the light emitting element overlaps with the pixel circuit to which it is electrically connected, the spacing between the light emitting element and the pixel circuit is not too far apart, which can avoid the length of the connection line between the light emitting element and the pixel circuit being too long, so as to ensure the driving capability of the pixel circuit to the light emitting element.

[0179] In some embodiments, referring to FIG. 7 or FIG. 32, in the thickness direction of the display panel, one part of the first unit columns 10a at least partially overlap with the first data line 31 and the third data line 33, another part of the first unit columns 10a at least partially overlap with the second data line 32 and the third data line 33, and the second unit columns 10b do not overlap with the data lines.

[0180] In some embodiments, the anode layout structure corresponding to the driving architecture shown in FIG. 4 can be as shown in FIG. 36, and the layout structures of other film layers corresponding to the driving architecture shown in FIG. 4 can be as shown in FIGS. 6-17, or as shown in FIGS. 20-28, or as shown in FIGS. 31-35, which will not be described herein again.

[0181] As shown in FIG. 5, the number of the pixel circuits in the display panel is equal to the number of the light emitting elements. In some embodiments, the driving architecture shown in FIG. 5 can be realized by the design manners shown in FIGS. 37-40.

[0182] Specifically, referring to FIGS. 37-40, two adjacent first unit columns 10a form a first unit column group, and the display panel includes a plurality of first unit column groups. For example, the (i)th first unit column 10a and the (i+1)th first unit column 10a form a first unit column group 10_1, and the (i+2)th first unit column 10a and the (i+3)th first unit column 10a form another first unit column group 10_2.

[0183] Each first circuit column 20a is electrically connected with a plurality of first light emitting elements 11 in the first unit column group, and each second circuit column 20b is electrically connected with a plurality of second light emitting elements 12 in the first unit column group.

[0184] That is, one first unit column group is provided with one first circuit column 20a and one second circuit column 20b, each first circuit column 20a is used to connect the first light emitting elements 11 located in two unit columns, and each second circuit column 20b is used to connect the second light emitting elements 12 located in two unit columns, so that the number of the pixel circuits in the display panel is equal to the number of the light emitting elements. In this design manner, one column of pixel circuits does not need to be additionally provided, and a virtual pixel circuit does not need to be provided, which is conducive to realizing a narrow frame.

[0185] In the case that the number of the pixel circuit columns is equal to the number of the light emitting elements, each first circuit column needs to electrically connect the first light emitting element located between two unit columns, so for at least part of the first light emitting elements, a connecting line needs to be set to connect the first light emitting element and the first pixel circuit, and the longer the connecting line is, the greater the voltage drop is, which will affect the driving ability of the first pixel circuit to the first light emitting element. Similarly, the same situation also exists for the second light emitting element and the second pixel circuit electrically connected thereto. Therefore, for the design mode shown in FIG. 5, how to balance the driving ability of the pixel circuit while reducing power consumption is also important.

[0186] In this regard, in some embodiments, please refer to FIG. 5, FIG. 37 and FIG. 38, the first light emitting element 11 is electrically connected with the first pixel circuit 21 through the first via 41. The first end of the first via 41 extends to the film layer where the anode of the first light emitting element 11 is located, and the second end of the first via 41 is electrically connected with the first pixel circuit 21. The second light emitting element 12 is electrically connected with the second pixel circuit 22 through the second via 42, and the plurality of second vias 42 corresponding to the same second circuit column 20b constitute a second via column 42a. The first end of the second via 42 extends to the film layer where the anode of the second light emitting element 12 is located, and the second end of the second via 42 is electrically connected with the second pixel circuit 22.

[0187] In the first unit column group, in the second direction Y, the first via 41 of one of the first unit columns 10a is on the first side of the first unit column 10a, and the second via 42 is on the second side of the first unit column. The first via 41 and the second via 42 of the other first unit column 10a are distributed on the same side of the first unit column.

[0188] For example, the (i)th first unit column 10a and the (i+1)th first unit column 10a constitute a first unit column group 10_1, wherein in the (i)th first unit column 10a, the first via 41 is on the left side and the second via 42 is on the right side; in the (i+1)th first unit column 10a, the first via 41 and the second via 42 are both on the left side.

[0189] The (i+2)th first unit column 10a and the (i+3)th first unit column 10a constitute another first unit column group 10_2, wherein in the (i+2)th first unit column 10a, the first via 41 is on the left side and the second via 42 is on the right side; in the (i+3)th first unit column 10a, the first via 41 and the second via 42 are both on the left side.

[0190] It can be understood that in this embodiment, the first via hole of the first light emitting element connected to the same first circuit column and located in the two first unit columns is arranged towards the direction close to the first circuit column, so that the length of the connection line between the first light emitting element and the first pixel circuit can be shortened, thereby avoiding large voltage drop caused by too long connection line, so that the driving capability of the first pixel circuit can be considered while reducing power consumption.

[0191] In some embodiments, please refer to FIG. 37, FIG. 38 and FIG. 39, the first light emitting element 11 is electrically connected to the first pixel circuit through the first connection line 51, and the first connection line 51 and the data line of the display panel are located in different film layers.

[0192] For example, for the first light emitting element 11 in the (i+1)th and (i+3)th first unit column 10a, the first connection line 51 is arranged in the metal layer below the anode, and the first connection line 51 is used to connect the first light emitting element 11 and the first pixel circuit. Specifically, the first end of the first connection line 51 is connected to the first via hole 41, and the other end is connected to the first pixel circuit, and the other end of the first via hole 41 is connected to the anode of the first light emitting element 11.

[0193] In some embodiments, in the thickness direction of the display panel, the first connection line 51 at least partially overlaps the second light emitting element 12, and in this design, the first connection line can be avoided to be wound, and the length of the first connection line can be reduced, thereby reducing the voltage drop.

[0194] For example, the corresponding film layer structure of FIG. 37 to FIG. 40 can be as shown in FIG. 18, and in FIG. 37 to FIG. 40, the data line includes the first data line 31, the second data line 32 and the third data line 33, the first data line 31, the second data line 32 and the third data line 33 are located in the second metal layer SD2 as shown in FIG. 18, and the first connection line 51 is arranged in the third metal layer SD3, so that the first connection line 51 and the data line are located in different film layers.

[0195] In some embodiments, please refer to FIG. 5, FIG. 37 and FIG. 18, in the thickness direction of the display panel, at least part of the second light emitting element 12 and the second pixel circuit 22 electrically connected thereto at least partially overlap, and the display panel includes at least two semiconductor layers, which are the first semiconductor layer B1 and the second semiconductor layer B2. Here, "overlap" means that at least part of them overlaps in the thickness direction of the display panel.

[0196] For example, the second light emitting element 12 in the (i+1)th first unit column 10a at least partially overlaps with the second pixel circuit in the 1st second circuit column 20b1. The 1st second circuit column 20b1 is also used to drive the second light emitting element 12 in the (i)th first unit column 10a, and for the (i)th first unit column 10a, the second via hole 42 is located at the side close to the 1st second circuit column 20b1, so that each second light emitting element does not need to be provided with an excessively long connection line to connect the second pixel circuit.

[0197] If the metal layer under the anode is provided with a connection line, referred to as a “pulling line” of the light emitting element, in this embodiment, only the first light emitting element 11 in the (i+1)th and (i+3)th first unit column 10a needs to be designed as a “pulling line”, and the second light emitting element 12 and the third light emitting element 13 do not need to be designed as a “pulling line”. In this regard, the embodiment of the present application is equivalent to reducing the length of the connection line required by the second light emitting element 12 and the third light emitting element 13, and the anode of part of the second light emitting element 12 or the third light emitting element 13 does not need to be connected to the pixel circuit through a connection line, but is directly connected to the pixel circuit through a via hole.

[0198] In addition, as introduced above, the first light emitting element 11 in the (i+1)th and (i+3)th first unit column 10a needs to be designed as a “pulling line”, and the “pulling line” here refers to the first connection line 51 as shown in FIG. 37 and FIG. 39. If the first light emitting element 11 in the (i)th and (i+2)th first unit column 10a is not designed as a “pulling line”, the pressure drop (or referred to as loading) corresponding to different first light emitting elements 11 is different, which affects the display uniformity. In this regard, for the first light emitting element 11 in the (i)th and (i+2)th first unit column 10a, a compensation line 54 can be provided, and the compensation line 54 is connected to the first via hole of the first light emitting element 11 in the (i)th and (i+2)th first unit column 10a. Exemplarily, the other end of the compensation line 54 is suspended. The compensation line 54 is provided in the same layer as the first connection line 51 in the metal layer.

[0199] Exemplarily, the first connection line 51 and the compensation line 54 corresponding to the first light emitting element connected by the same first circuit column are alternately arranged in the first direction.

[0200] It should be noted that the structure shown in FIG. 18 has been introduced above, and will not be described again here. In addition, in the design mode corresponding to FIG. 37 to FIG. 40, the structures of other film layers can be respectively as shown in FIG. 11 to FIG. 17.

[0201] In other embodiments, the driving architecture shown in FIG. 5 can be implemented by the design modes shown in FIG. 41 to FIG. 45.

[0202] Please refer to FIG. 5 and FIG. 41 to FIG. 45, the first light emitting element 11 is electrically connected with the first pixel circuit 21 through the first connecting line 51, the second light emitting element 12 is electrically connected with the second pixel circuit 22 through the second connecting line 52, at least part of the first connecting line 51 and at least part of the second connecting line 52 are located in different film layers from the data line of the display panel, and the display panel includes a semiconductor layer.

[0203] For example, the corresponding film layer structure of FIG. 41 to FIG. 45 can be as shown in FIG. 29, in FIG. 41 to FIG. 45, the data line includes the first data line 31, the second data line 32 and the third data line 33, the first data line 31, the second data line 32 and the third data line 33 are located in the second metal layer SD2 as shown in FIG. 29, and at least part of the first connecting line 51 and at least part of the second connecting line 52 are arranged in the third metal layer SD3, so that at least part of the first connecting line 51 and at least part of the second connecting line 52 are located in different film layers from the data line, thereby avoiding crosstalk between the connecting line and the data line.

[0204] For the LTPS type display panel, a non-mirror design is adopted, so that even if the via hole of the light emitting element is located on the side of the light emitting element facing the pixel circuit connected thereto, and the light emitting element is designed to be as close as possible to the pixel circuit to be connected, in the non-mirror design, there will still be some light emitting elements and the pixel circuits to be connected which are relatively far away. If the connecting line is still arranged in the anode film layer, the connecting line needs to bypass the anodes of the light emitting elements of other colors, which will make the length of the connecting line longer, and then the voltage drop of the connecting line will be increased, resulting in the driving ability of the first pixel circuit to the first light emitting element being weakened. The second light emitting element is the same, which will not be described here.

[0205] In this regard, at least part of the first connecting line and at least part of the second connecting line can be designed in the form of a cross-line (the cross-line includes a wire arranged in at least two film layers).

[0206] Specifically, please refer to FIG. 43 and FIG. 44, for the (i+1)th first unit column 10a and the (i+3)th first unit column 10a, the first connecting line 51 includes a first segment 511 and a second segment 512, the first segment 511 is connected between the anode of the first light emitting element 11 and the first end of the first via hole 41, and the second segment 512 is connected between the second end of the first via hole 41 and the first pixel circuit, the first segment 511 and the anode of the first light emitting element 11 are located in the same film layer, and the second segment 512 is located in the metal layer on the side of the anode of the first light emitting element 11 facing the substrate.

[0207] For the (i)th first unit column 10a and the (i+2)th first unit column 10a, the second connection line 52 includes a third segment 523 and a fourth segment 524, the third segment 523 is connected between the anode of the second light emitting element 12 and the first end of the second via hole 42, the fourth segment 524 is connected between the second end of the second via hole 42 and the second pixel circuit, the third segment 523 and the anode of the second light emitting element 12 are located in the same film layer, and the fourth segment 524 is located in the metal layer on the side of the anode of the second light emitting element 12 facing the substrate.

[0208] In the embodiments of the present application, since the second segment 512 and the fourth segment 524 are located in the metal layer below the anode, the length of the connection line in the anode film layer can be reduced, and the connection line in the metal layer is less constrained by the anode, so that the connection line can be arranged in a near-connection manner, and the second segment 512 and the fourth segment 524 do not have to be excessively winding due to the constraint of the anode. Therefore, the total length of the first connection line and the total length of the second connection line can be reduced as a whole. In addition, the problem of possible short circuit caused by direct wiring on the anode can be avoided.

[0209] For example, referring to FIGS. 43 and 44, for the (i+1)th first unit column 10a and the (i+3)th first unit column 10a, the connection line for connecting the second light emitting element 12 and the second pixel circuit can be arranged only in the anode film layer. For the (i)th first unit column 10a and the (i+2)th first unit column 10a, the connection line for connecting the first light emitting element 11 and the first pixel circuit can be arranged only in the anode film layer.

[0210] In other embodiments, the driving architecture shown in FIG. 5 can also be implemented by the design shown in FIGS. 46-49. For example, the cross-sectional structure of the display panel corresponding to the structure shown in FIGS. 46-49 can also be as shown in FIG. 18, and the structure in the layout shown in FIG. 48 is located in the second metal layer SD2 shown in FIG. 18, and the structure in the layout shown in FIG. 49 is located in the third metal layer SD3 shown in FIG. 18.

[0211] The same parts of the structure shown in FIGS. 46-49 and the structure shown in FIGS. 37-40 will not be repeated, and the different parts include: the wiring of the second metal layer and the third metal layer is interchanged. For example, in the structure shown in FIGS. 37-40, the wiring extending in the first direction X is arranged in the second metal layer SD2, and the wiring extending in the second direction Y is arranged in the third metal layer SD3. In the structure shown in FIGS. 46-49, the wiring extending in the first direction X is arranged in the third metal layer SD3, and the wiring extending in the second direction Y is arranged in the second metal layer SD2.

[0212] For example, FIG. 48 is a layout structure of the third metal layer SD3, which includes the data lines 31-33 extending along the first direction, the power supply branch lines 611, 623, 635, and the wires 91, 92. FIG. 49 is a layout structure of the second metal layer SD2, which includes the power supply branch lines 612, 624 extending along the second direction, the wire 72, etc.

[0213] In addition, in FIGS. 46-49, the first light emitting elements 11 in the (i+1)th and (i+3)th first unit columns 10a are designed with a "pulling line", which refers to the second segment 512 as shown in FIGS. 46 and 49. For the first light emitting elements 11 in the ith and (i+2)th first unit columns 10a, if no "pulling line" is designed, the voltage drops (or loading) corresponding to different first light emitting elements 11 are different, which affects the display uniformity. In view of this, for the first light emitting elements 11 in the ith and (i+2)th first unit columns 10a, a compensation line 54 can be provided, which is connected to the first via of the first light emitting elements 11 in the ith and (i+2)th first unit columns 10a. Exemplarily, the other end of the compensation line 54 is suspended. The compensation line 54 is arranged in the same layer as the second segment 512 of the metal layer.

[0214] In other embodiments, the driving architecture shown in FIG. 5 can also be implemented by the design manners shown in FIGS. 50-53. Exemplarily, the cross-sectional structure of the display panel corresponding to the structures shown in FIGS. 50-53 can also be as shown in FIG. 18, and the structures in the layout shown in FIG. 52 are located in the second metal layer SD2 shown in FIG. 18, and the structures in the layout shown in FIG. 53 are located in the third metal layer SD3 shown in FIG. 18.

[0215] The same parts of the structures shown in FIGS. 50-53 and the structures shown in FIGS. 37-40 will not be described again, and the different parts include that the wires of the second metal layer and the third metal layer are interchanged. For example, in the structures shown in FIGS. 37-40, the wires extending along the first direction X are arranged in the second metal layer SD2, and the wires extending along the second direction Y are arranged in the third metal layer SD3. In the structures shown in FIGS. 50-53, the wires extending along the first direction X are arranged in the third metal layer SD3, and the wires extending along the second direction Y are arranged in the second metal layer SD2.

[0216] For example, FIG. 52 is a layout structure of the third metal layer SD3, which includes the data lines 31-33 extending along the first direction, the power supply branch lines 611, 623, 635, and the wires 91, 92. FIG. 53 is a layout structure of the second metal layer SD2, which includes the power supply branch lines 612, 624 extending along the second direction, the wire 72, etc.

[0217] In some embodiments, please refer to FIG. 5 and FIG. 50 to FIG. 53, the first light emitting element 11 is electrically connected with the first pixel circuit 21 through the first via hole 41, and the second light emitting element 12 is electrically connected with the second pixel circuit 22 through the second via hole 42. In addition, the third light emitting element 13 is electrically connected with the third pixel circuit 23 through the third via hole 43.

[0218] In the second direction Y, the first via hole 41 of any one first unit column 10a is on the first side of the first unit column 10a, and the second via hole 42 is on the second side of the first unit column 10a.

[0219] For example, for the (i)th and (i+2)th first unit columns 10a, the first via holes 41 are all on the left side, and the second via holes 42 are all on the right side. For the (i+1)th and (i+3)th first unit columns 10a, the first via holes 41 are all on the right side, and the second via holes 42 are all on the left side.

[0220] For example, for the (i)th and (i+2)th first unit columns 10a, the first via holes 41 are all on the left side, and the second via holes 42 are all on the right side. For the (i+1)th and (i+3)th first unit columns 10a, the first via holes 41 are all on the right side, and the second via holes 42 are all on the left side.

[0221] Please refer to FIG. 51, in this embodiment, the distribution of the via holes corresponding to the first unit column 10a on the same side can be avoided, which can prevent the via holes from being too dense. If the via holes are too dense, more layout space will be occupied, which is not conducive to improving the pixel density. Therefore, the embodiment of the present application is conducive to improving the pixel density and improving the signal interference between different via holes.

[0222] As can be seen from the drawings, the distribution rules of the second via holes and the third via holes in the structures shown in FIG. 50 to FIG. 53 and the structures shown in FIG. 46 to FIG. 49 are the same, and the difference is that the distribution rules of the first via holes 41 of the (i)th and (i+2)th first unit columns 10a are different. In the structures shown in FIG. 46 to FIG. 49, the first via holes 41 of the (i)th and (i+2)th first unit columns 10a are all on the left side of the first light emitting element connected therewith. In the structures shown in FIG. 50 to FIG. 53, the first via holes 41 of the (i)th and (i+2)th first unit columns 10a are all on the right side of the first light emitting element connected therewith.

[0223] The first pixel circuit required to be connected by the first light emitting element of the (i)th and (i+2)th first unit columns 10a is on the left side thereof, and in the case that the first via holes 41 of the (i)th and (i+2)th first unit columns 10a are moved to the right side of the first light emitting element connected therewith, the distance between the first via holes 41 and the first pixel circuit electrically connected therewith will increase, and in this case, the length of the connecting line between the two can be lengthened.

[0224] In some embodiments, referring to FIG. 51 and FIG. 53, the first light emitting element 11 is electrically connected to the first pixel circuit through the first connecting line 51, the length of the first connecting line 51 between the first via hole 41 and the first pixel circuit in the second direction Y is L1, the width of the pixel circuit of the display panel in the second direction Y is L2, and 3*L2≤L1≤4*L2. The widths of the first pixel circuit, the second pixel circuit, and the third pixel circuit in the second direction are the same, and the widths of the first circuit column, the second circuit column, and the third circuit column in the second direction Y are approximately L2.

[0225] In this embodiment, the first connecting line 51 can also include a first segment 511 and a second segment 512, the first segment 511 is connected between the anode of the first light emitting element 11 and the first end of the first via hole 41, and the second segment 512 is connected between the second end of the first via hole 41 and the first pixel circuit. The first segment 511 and the anode of the first light emitting element 11 are located in the same film layer, and the second segment 512 is located in the metal layer on the side of the anode of the first light emitting element 11 facing the substrate. In this embodiment, the second segment 512 is located in the second metal layer.

[0226] In this embodiment, the length of the second segment 512 in the second direction Y is L1. As shown in FIG. 52, in the second direction Y, the second segment 512 needs to span approximately 3-4 circuit columns.

[0227] In other embodiments, the driving architecture shown in FIG. 5 can also be implemented by the design methods shown in FIG. 54 to FIG. 57. For example, the cross-sectional structure of the display panel corresponding to the structures shown in FIG. 54 to FIG. 57 can also be as shown in FIG. 18, and the structure in the layout shown in FIG. 56 is located in the second metal layer SD2 shown in FIG. 18, and the structure in the layout shown in FIG. 57 is located in the third metal layer SD3 shown in FIG. 18.

[0228] The same parts of the structures shown in FIG. 54 to FIG. 57 and the structures shown in FIG. 37 to FIG. 40 will not be repeated, and the different parts include: the wirings of the second metal layer and the third metal layer are interchanged. For example, in the structures shown in FIG. 37 to FIG. 40, the wirings extending in the first direction X are arranged in the second metal layer SD2, and the wirings extending in the second direction Y are arranged in the third metal layer SD3. In the structures shown in FIG. 54 to FIG. 57, the wirings extending in the first direction X are arranged in the third metal layer SD3, and the wirings extending in the second direction Y are arranged in the second metal layer SD2.

[0229] For example, FIG. 56 is a layout structure of the third metal layer SD3, the third metal layer SD3 includes data lines 31-33 extending in the first direction, power branch lines 611, 623, 635, and wirings 91, 92. FIG. 57 is a layout structure of the second metal layer SD2, the second metal layer SD2 includes power branch lines 612, 624 extending in the second direction, wirings 72, etc.

[0230] In some embodiments, please refer to FIG. 5 and FIG. 54 to FIG. 57, the first light emitting element 11 is electrically connected with the first pixel circuit 21 through the first via hole 41, and the second light emitting element 12 is electrically connected with the second pixel circuit 22 through the second via hole 42. In addition, the third light emitting element 13 is electrically connected with the third pixel circuit 23 through the third via hole 43.

[0231] In the second direction Y, the first via hole 41 and the second via hole 42 of any one first unit column 10a are distributed on the same side of the first unit column 10a.

[0232] For example, for the (i)th, (i+1)th, (i+2)th, (i+3)th first unit column 10a, the first via hole 41 and the second via hole 42 are both on the left side.

[0233] For example, for the (i)th, (i+1)th, (i+2)th, (i+3)th first unit column 10a, the first via hole 41 and the second via hole 42 are both on the left side.

[0234] Please refer to FIG. 55, in this embodiment, the distribution of the via holes corresponding to the first unit column 10a on the same side can also be avoided, which can prevent the via holes from being too dense; if the via holes are too dense, more layout space needs to be occupied, which is not conducive to improving the pixel density; therefore, the embodiment of the present application is conducive to improving the pixel density and can improve the signal interference between different via holes.

[0235] As can be seen from the drawings, the distribution rules of the first via hole and the third via hole in the structures shown in FIG. 54 to FIG. 57 are the same as those in the structures shown in FIG. 46 to FIG. 49, and the difference is that the distribution rule of the second via hole 42 is different. For example, in the structures shown in FIG. 46 to FIG. 49, the second via hole 42 of the (i)th, (i+2)th first unit column 10a is on the right side of the second light emitting element connected therewith, and the second via hole 42 of the (i+1)th, (i+3)th first unit column 10a is on the left side of the second light emitting element connected therewith. In the structures shown in FIG. 50 to FIG. 53, the second via hole 42 of each first unit column 10a is on the left side of the first light emitting element connected therewith.

[0236] The second pixel circuit required to be connected with the second light emitting element of the (i)th, (i+2)th first unit column 10a is on the right side of the second light emitting element, and in the case that the second via hole 42 of the (i)th, (i+2)th first unit column 10a is moved to the left side of the second light emitting element connected therewith, the distance between the second via hole 42 and the second pixel circuit electrically connected therewith will increase, and in this case, the length of the connecting line between the two can be lengthened. In addition, the first light emitting element of the (i+1)th, (i+3)th first unit column 10a also needs to be connected with the first pixel circuit connected therewith through a connecting line.

[0237] In some embodiments, referring to FIGS. 55 and 57, the first light emitting element 11 is electrically connected to the first pixel circuit through the first connecting line 51, and the second light emitting element 12 is electrically connected to the second pixel circuit through the second connecting line 52, and the first connecting line 51 and the second connecting line 52 do not overlap.

[0238] In this embodiment, the first connecting line 51 can include a first segment 511 and a second segment 512, the first segment 511 is connected between the anode of the first light emitting element 11 and the first end of the first via hole 41, and the second segment 512 is connected between the second end of the first via hole 41 and the first pixel circuit, the first segment 511 and the anode of the first light emitting element 11 are located in the same film layer, and the second segment 512 is located in the metal layer on the side of the anode of the first light emitting element 11 facing the substrate.

[0239] The second connecting line 52 includes a third segment 523 and a fourth segment 524, the third segment 523 is connected between the anode of the second light emitting element 12 and the first end of the second via hole 42, and the fourth segment 524 is connected between the second end of the second via hole 42 and the second pixel circuit, the third segment 523 and the anode of the second light emitting element 12 are located in the same film layer, and the fourth segment 524 is located in the metal layer on the side of the anode of the second light emitting element 12 facing the substrate.

[0240] In this embodiment, the second segment 512 and the fourth segment 524 are located in the second metal layer.

[0241] The first segment 511 and the third segment 523 do not overlap, and the second segment 512 and the fourth segment 524 do not overlap.

[0242] In this embodiment, the length of the second segment 512 and the fourth segment 524 in the second direction Y is substantially equal. The length of the second segment 512 and the fourth segment 524 in the second direction Y is substantially equal to 2 times the width L2 of the pixel circuit.

[0243] In some embodiments, as shown in FIG. 54, the third light emitting element 13 is electrically connected to the third pixel circuit through the third via hole 43, and any one third via hole 43 is on the same side of the third light emitting element 13 connected thereto. That is, the distribution rule of the plurality of third via holes in the entire display panel is the same.

[0244] For example, as shown in FIGS. 6, 31, 37, 46, 50, 54, in the first direction X, any one third via hole 43 is on the lower side of the third light emitting element 13 connected thereto.

[0245] For another example, as shown in FIGS. 20 and 41, in the second direction Y, any one third via hole 43 is on the left side of the third light emitting element 13 connected thereto.

[0246] For example, as shown in FIG. 59, in the first direction X, any one third via hole 43 is on the upper side of the third light emitting element 13 connected thereto.

[0247] For example, the display panel shown in FIG. 6, FIG. 31, FIG. 37, FIG. 46, FIG. 50, and FIG. 54 is an LTPO type display panel. The display panel shown in FIG. 20 and FIG. 41 is an LTPS type display panel. The display panel shown in FIG. 59 is an LTPS type display panel. Of course, this is not used to limit the present application.

[0248] It should be noted that in the drawings of the light emitting element shown in FIG. 3 to FIG. 57, the first light emitting element 11 is a red light emitting element and the second light emitting element 12 is a blue light emitting element, which is not used to limit the present application. In other examples, for example, the first light emitting element 11 is a blue light emitting element and the second light emitting element 12 is a red light emitting element.

[0249] In some embodiments, the same column unit column including light emitting elements of different colors can also be implemented by the design shown in FIG. 58, and the light emitting elements of the same color are connected by the data line.

[0250] As shown in FIG. 58, one first light emitting element 11, one second light emitting element 12, and one third light emitting element 13 adjacent to each other constitute an element unit 101, and a plurality of element units 101 are arranged in the first direction X and the second direction Y.

[0251] The first light emitting element 11 is electrically connected to the first pixel circuit 21 through the first via hole 41, the second light emitting element 12 is electrically connected to the second pixel circuit 22 through the second via hole 42, and the third light emitting element 13 is electrically connected to the third pixel circuit 23 through the third via hole 43; in the first direction X, the first via hole 41, the second via hole 42, and the third via hole 43 of the element unit 101 are located on the same side of the element unit 101.

[0252] For example, in FIG. 58, the first via hole 41, the second via hole 42, and the third via hole 43 are located on the upper side of the element unit 101.

[0253] As an example, in FIG. 58, the first light emitting element 11 is a red light emitting element, the second light emitting element 12 is a green light emitting element, and the third light emitting element 13 is a blue light emitting element. Of course, the red light emitting element and the green light emitting element in FIG. 58 can be interchanged.

[0254] In some embodiments, as shown in FIG. 58, the adjacent first unit column 10a and the second unit column 10b constitute a second unit column group, and each second unit column group is provided with three columns of pixel circuits.

[0255] For example, the (i)th first unit column 10a and the (j)th second unit column 10b constitute a second unit column group 10_3, the 1st first circuit column 20a1, the 1st second circuit column 20b1 and the 1st third circuit column 20c1 are used to drive the (i)th first unit column 10a and the (j)th second unit column 10b, that is, the three columns of pixel circuits corresponding to the second unit column group 10_3 are distributed as: the 1st first circuit column 20a1, the 1st second circuit column 20b1 and the 1st third circuit column 20c1.

[0256] The (i+1)th first unit column 10a and the (j+1)th second unit column 10b constitute a second unit column group 10_4, the 2nd first circuit column 20a2, the 2nd second circuit column 20b2 and the 2nd third circuit column 20c2 are used to drive the (i+1)th first unit column 10a and the (j+1)th second unit column 10b, that is, the three columns of pixel circuits corresponding to the second unit column group 10_4 are distributed as: the 2nd first circuit column 20a2, the 2nd second circuit column 20b2 and the 2nd third circuit column 20c2.

[0257] In this embodiment, when the total number of the first unit columns and the second unit columns is 2n, the total number of the pixel circuit columns is 3n. In this way, in the second direction Y, the total width of the first unit columns and the second unit columns is approximately equal to the total width of the three pixel circuit columns, so that the light emitting area of the light emitting element can be increased.

[0258] In some embodiments, please refer to FIGS. 58-61, the anode of the second light emitting element 12 is electrically connected to the second via hole 42 through the second connecting line 52, and the second connecting line 52 is located between the first light emitting element 11 and the third light emitting element 13 in a direction parallel to the light emitting surface of the display panel.

[0259] For example, the second connecting line 52 and the anode of the second light emitting element 12 are located in the same film layer.

[0260] For the first light emitting element 11, there is almost no need to set a connecting line between the anode and the first pixel circuit 21, but the anode can be directly connected to the first via hole 41.

[0261] For the third light emitting element 13, the distance between the anode and the third via hole 43 is relatively short, so the length of the connecting line directly connecting the anode of the third light emitting element 13 and the third via hole 43 can be relatively short.

[0262] Compared with the first light emitting element and the third light emitting element, the distance between the anode of the second light emitting element 12 and the second via hole 42 is relatively far, so a relatively long second connecting line can be set to connect the second light emitting element 12 and the second via hole 42.

[0263] Figs. 62 to 67 show the layout structures of some other film layers for implementing the design mode shown in Fig. 58, as shown in Figs. 59 to 69, the display panel includes a semiconductor layer. For example, as shown in Fig. 68, the display panel includes a first semiconductor layer B1. For example, the material of the first semiconductor layer B1 includes LTPS, as shown in Fig. 30, each transistor of the pixel circuit is an LTPS transistor. In this embodiment, the structures of the first pixel circuit, the second pixel circuit and the third pixel circuit can be as shown in Fig. 69, in the structure shown in Fig. 69, the pixel circuit includes 6 transistors and one capacitor, wherein the first electrode of the driving transistor M13 is connected with the power line PVDD.

[0264] In some embodiments, please refer to Figs. 65 and 69, the pixel circuit of the display panel includes the driving transistor M13 and the power line PVDD electrically connected with the driving transistor M13, and there is no connection between the active layers M13-p of adjacent driving transistors. In Fig. 65, the active layer of the driving transistor in a pixel circuit is boxed with a dashed line.

[0265] It can be understood that this example lays a foundation for implementing the light emitting elements of different light emitting colors to be powered by different power lines.

[0266] It should be noted that the no connection between the active layers M13-p of adjacent driving transistors means that there is no “semiconductor part” lapped between the active layers M13-p of adjacent driving transistors, and the “semiconductor part” refers to a structure in the same layer as the active layer of the driving transistor.

[0267] For example, as shown in Fig. 65, in the first semiconductor layer, the active layer M13-p of the driving transistor is disconnected with the active layers of other transistors, and the active layers M13-p of different driving transistors are disconnected.

[0268] It should be further noted that although this application only indicates in the corresponding examples of Figs. 58 to 69 that the active layer of the driving transistor is disconnected with the active layers of other transistors, and the active layers of different driving transistors are disconnected in the film layer where the active layer of the driving transistor is located, this does not limit the application, for example, in the corresponding examples of any one of Figs. 3 to 57, the active layer of the driving transistor can also be disconnected with the active layers of other transistors, and the active layers of different driving transistors can also be disconnected in the film layer where the active layer of the driving transistor is located. Of course, in the corresponding examples of any one of Figs. 3 to 57, the active layer of the driving transistor can also be continuously connected with the active layers of other transistors in the film layer where the active layer of the driving transistor is located.

[0269] Please refer to FIG. 62 and FIG. 69, in the same pixel circuit, the driving transistor M13 needs to be connected with other transistors. For example, the gate of the driving transistor M13 is connected with the first connection part N11, and the second electrode of the driving transistor M13 is connected with the third connection part N13. The first connection part N11 and the third connection part N13 are arranged in the metal layer. For example, the first connection part N11 and the third connection part N13 are located in the first metal layer SD1 shown in FIG. 8. In addition, the other end of the capacitor Cst is connected with the second connection part N12, and the second connection part N12 is located in the first metal layer SD1 shown in FIG. 8.

[0270] In addition, the layout structure shown in FIG. 61 is located in the anode layer RE shown in FIG. 68, the layout structure shown in FIG. 62 is located in the first metal layer SD1 shown in FIG. 68, the layout structure shown in FIG. 63 is located in the capacitor metal layer MC shown in FIG. 68, the layout structure shown in FIG. 64 is located in the first gate layer GAT shown in FIG. 68, the layout structure shown in FIG. 65 is located in the first semiconductor layer B1 shown in FIG. 68, and the layout structure shown in FIG. 67 is located in the auxiliary metal layer M0 shown in FIG. 68.

[0271] In some embodiments, as shown in the examples of FIG. 37 to FIG. 40, or as shown in the examples of FIG. 46 to FIG. 49, or as shown in the examples of FIG. 50 to FIG. 53, for some light emitting elements, a “wire drawing” design needs to be performed in the metal layer to realize the connection between the light emitting element and the pixel circuit.

[0272] Specifically, as shown in FIG. 47 and FIG. 48, the light emitting element is electrically connected with the pixel circuit through a via. For the first light emitting element 11 in the (i+1)th and (i+3)th first unit column 10a, a “wire drawing” design needs to be performed, the via between the first light emitting element 11 and the first pixel circuit is referred to as a first sub-via 411, and the first connection line between the first light emitting element 11 and the first pixel circuit includes a second segment 512. In the thickness direction of the display panel, the first sub-via 411 does not overlap with the first pixel circuit to which it is electrically connected. One end of the first sub-via 411 extends to the film layer where the anode of the first light emitting element 11 is located, and the other end of the first sub-via 411 extends to the metal layer where the second segment 512 is located. The other end of the first sub-via 411 is connected with one end of the second segment 512, and the other end of the second segment 512 is electrically connected with the first pixel circuit.

[0273] In some embodiments, the light emitting element is electrically connected with the pixel circuit through a via, the via includes a first sub-via which does not overlap with the pixel circuit to which it is electrically connected; the display panel further includes a connection line, one end of the connection line is connected with the first sub-via, and the other end of the connection line is connected with the pixel circuit.

[0274] Still illustrated in FIG. 47 and FIG. 48, the display panel includes power supply branches extending along the second direction Y, for example, the second power supply branch 612, the fourth power supply branch 624, and the like. The “wire drawing” can be performed on the film layer where the second power supply branch 612 and the fourth power supply branch 624 are located. That is, at least part of the line segment of the connection line between the light emitting element and the pixel circuit is arranged in the same layer as the power supply branch extending along the second direction.

[0275] In this embodiment, although additional “wire drawing” design is required, the “wire drawing” is arranged in the same layer as the power supply branch, so that additional film layers do not need to be added, which is conducive to the thinness of the display panel.

[0276] In some embodiments, the via hole includes a second sub-via hole, the second sub-via hole at least partially overlaps the pixel circuit electrically connected thereto; and the display panel further includes a compensation line, one end of the compensation line being connected to the second sub-via hole.

[0277] Still illustrated in FIG. 47 and FIG. 48, for the first light emitting element 11 in the (i)th and (i+2)th first unit column 10a, no “wire drawing” design is required, where “wire drawing” refers to the connection line for connecting the light emitting element and the pixel circuit. These first light emitting elements 11 and the connection via hole between the first pixel circuit are referred to as the second sub-via hole 412. One end of the second sub-via hole 412 extends to the film layer where the anode of the first light emitting element 11 is located, and the other end of the second sub-via hole 412 extends to the film layer where the first pixel circuit is located, and the other end of the second sub-via hole 412 is electrically connected to the first pixel circuit.

[0278] In the thickness direction of the display panel, the second sub-via hole 412 at least partially overlaps the first pixel circuit electrically connected thereto. The other end of the first sub-via hole 411 is connected to one end of the second segment 512, and the other end of the second segment 512 is electrically connected to the first pixel circuit.

[0279] For the first light emitting element 11 in the (i+1)th and (i+3)th first unit column 10a, “wire drawing” design is required, and for the first light emitting element 11 in the (i)th and (i+2)th first unit column 10a, “wire drawing” design is not required, where “wire drawing” refers to the connection line for connecting the light emitting element and the pixel circuit. In this way, the lengths of the connection lines for different first light emitting elements 11 are different, resulting in different voltage drops (or loadings) of different first light emitting elements 11, which affects the display uniformity.

[0280] In view of this, for the first light emitting element 11 in the (i)th and (i+2)th first unit column 10a, a compensation line 54 can also be provided, one end of the compensation line 54 being connected to the second sub-via hole 412.

[0281] For example, the total impedance of the compensation line 54 and the total impedance of the second segment 512 can be substantially equal.

[0282] In some embodiments, the compensation line is in the same film layer as the connection line of the metal layer.

[0283] Still referring to FIGS. 47 and 48, for the first light emitting element 11 in the (i)th and (i+2)th first unit column 10a, the compensation line 54 is in the same film layer as the second segment 512. In this embodiment, although an additional “compensation line” design is required, the “compensation line” is in the same film layer as the connection line of the metal layer or the anode of the light emitting element, so that no additional film layer is required, which is conducive to the thinning of the display panel.

[0284] In some embodiments, the other end of the compensation line is left dangling. In this way, other signal crosstalk or interference with the light emitting element connected by the compensation line can be avoided.

[0285] For example, in FIG. 48, one end of the compensation line 54 is connected to the second sub-via 412, and the other end is left dangling. “Dangling” means that the other end of the compensation line is not connected to other structures.

[0286] In order to provide a current source required for the light emitting element to emit light, a power line PVDD and a common voltage line PVEE are required, and the pixel circuit and the light emitting element are connected in series between the power line PVDD and the common voltage line PVEE. When the pixel circuit electrically connects the light emitting element and the power line PVDD, the light emitting element can emit light.

[0287] The light emitting element and the pixel circuit electrically connected thereto form a sub-pixel. For example, the first light emitting element and the first pixel circuit form a first sub-pixel, the second light emitting element and the second pixel circuit form a second sub-pixel, and the third light emitting element and the third pixel circuit form a third sub-pixel. The sub-pixel is connected between the power line PVDD and the common voltage line PVEE.

[0288] In the related art, different color sub-pixels share the power line PVDD and the common voltage line PVEE. However, the required voltage difference between the power line PVDD and the common voltage line PVEE for different color sub-pixels is different. In the design in which the power line PVDD is shared, in order to enable each color sub-pixel to work in the saturation region, the voltage difference between the power line PVDD and the common voltage line PVEE needs to be designed to cover the maximum voltage difference required by each color sub-pixel. For a sub-pixel requiring a small voltage difference, unnecessary power consumption loss exists.

[0289] In the embodiments of the present application, while the data lines of each color light emitting element are independent, the power line PVDD of each color light emitting element is also designed to be independent, so as to further save power consumption.

[0290] In the examples shown in FIGS. 6-69, the power supply lines PVDD of the light emitting elements of at least two colors are designed independently. The independent design of the power supply lines PVDD is exemplarily described below with reference to some of the drawings.

[0291] In some embodiments, referring to FIGS. 7, 9 and 10, the display panel further includes power supply lines PVDD, which include at least a first power supply line 61 and a second power supply line 62. The first power supply line 61 is electrically connected to the first light emitting element 11, and includes a first power supply branch 611 and a second power supply branch 612 electrically connected to each other, the first power supply branch 611 extending along the first direction X, and the second power supply branch 612 extending along the second direction Y. The second power supply line 62 is electrically connected to the second light emitting element 12, and includes a third power supply branch 623 and a fourth power supply branch 624 electrically connected to each other, the third power supply branch 623 extending along the first direction X, and the fourth power supply branch 624 extending along the second direction Y.

[0292] For example, the first power supply branch 611 and the second power supply branch 612 can be located in different film layers and connected by a via. The third power supply branch 623 and the fourth power supply branch 624 can be located in different film layers and connected by a via.

[0293] It should be noted that the first power supply line 61 and the second power supply line 62 are not connected, so that different power supply voltages can be provided by the first power supply line 61 and the second power supply line 62 respectively in the case that the first light emitting element and the second light emitting element require different cross voltages, so that a large cross voltage is not required to cover all the cross voltages required by the light emitting elements, thereby saving the power consumption of the display panel.

[0294] In addition, the first power supply branch 611 and the second power supply branch 612 extend in different directions and are electrically connected to each other, and a plurality of first power supply branches 611 and a plurality of second power supply branches 612 can form a grid-shaped first power supply line 61, thereby reducing the voltage drop of the first power supply line 61 and improving display uniformity.

[0295] Similarly, the third power supply branch 623 and the fourth power supply branch 624 extend in different directions and are electrically connected to each other, and a plurality of third power supply branches 623 and a plurality of fourth power supply branches 624 can form a grid-shaped second power supply line 62, thereby reducing the voltage drop of the second power supply line 62 and improving display uniformity.

[0296] For example, only for the first power branch 611 and the third power branch 623, in the second direction Y, the first power branch 611 and the third power branch 623 are alternately distributed. Only for the second power branch 612 and the fourth power branch 624, in the first direction X, the second power branch 612 and the fourth power branch 624 are alternately distributed. In this way, the area covered by the single grid of the first power line 61 and the single grid of the second power line 62 can be substantially consistent, thereby reducing the difference in voltage drop between the first power line 61 and the second power line 62.

[0297] In some embodiments, please refer to FIG. 7, FIG. 9, FIG. 10, or please refer to FIG. 62 and FIG. 63, the display panel further comprises a power line PVDD, the power line PVDD further comprises a third power line 63, the third power line 63 is electrically connected with the third light emitting element 13, the third power line 63 comprises a fifth power branch 635 and a sixth power branch 636 which are electrically connected with each other, the fifth power branch 635 extends along the first direction X, and the sixth power branch 636 extends along the second direction Y.

[0298] One of the second power branch and the fourth power branch is electrically connected with the sixth power branch.

[0299] As an example, please refer to FIG. 7, FIG. 9, FIG. 10, the second power branch 612 and the sixth power branch 636 can be the same trace, that is, the trace is used as both the second power branch 612 and the sixth power branch 636. This example can reduce the number of power branches extending in the second direction, and can release the layout space. It can be understood that in this example, the first light emitting element and the third light emitting element share the power signal.

[0300] It should be noted that in the layout diagrams in FIG. 6 to FIG. 57, although it is shown that the second power branch 612 and the sixth power branch 636 are the same trace, this is not used in the present application. For example, in other examples, the fourth power branch 624 and the sixth power branch 636 are the same trace, or the second power branch 612 and the sixth power branch 636 are two traces and are connected with each other, or the fourth power branch 624 and the sixth power branch 636 are two traces and are connected with each other.

[0301] As another example, please refer to FIG. 62 and FIG. 63, the second power branch 612, the fourth power branch 624, and the sixth power branch 636 are independent of each other. That is, the second power branch 612, the fourth power branch 624, and the sixth power branch 636 are not connected with each other, and the power lines of the first light emitting element, the second light emitting element, and the third light emitting element are independent of each other, which can more flexibly match the cross-voltage requirements of each light emitting element.

[0302] It should be noted that FIG. 63 shows the layout structure corresponding to 6 rows of pixel circuits, and FIGS. 58-62 and FIGS. 64-67 show the layout structure corresponding to 2 rows of pixel circuits.

[0303] For example, in the case that the second power supply branch 612, the fourth power supply branch 624, and the sixth power supply branch 636 are independent of each other, each of the second power supply branch 612, the fourth power supply branch 624, and the sixth power supply branch 636 forms a line group, and a plurality of the line groups are arranged in the first direction X.

[0304] It should be noted that in the layout diagrams in FIGS. 6-57, the second power supply branch 612, the fourth power supply branch 624, and the sixth power supply branch 636 can also be designed in the manner of being independent of each other.

[0305] In some embodiments, as shown in FIGS. 7, 21, 32, 37, 42, 46, 50, and 54, one of the first light emitting element 11 and the second light emitting element 12 is a red light emitting element, and the other is a blue light emitting element, and the third light emitting element 13 is a green light emitting element; the first power supply branch 611, the fifth power supply branch 635, the third power supply branch 623, and the fifth power supply branch 635 form a first line group, and a plurality of the first line groups are arranged in the second direction Y.

[0306] That is, in the second direction Y, the arrangement rule of the power supply branches is: one first power supply branch 611, one fifth power supply branch 635, one third power supply branch 623, and one fifth power supply branch 635, and then one first power supply branch 611, one fifth power supply branch 635, one third power supply branch 623, and one fifth power supply branch 635, and so on.

[0307] In the second direction Y, the arrangement sequence of the circuit columns is: one first circuit column 20a, one third circuit column 20c, one second circuit column 20b, and one third circuit column 20c, and then one first circuit column 20a, one third circuit column 20c, one second circuit column 20b, and one third circuit column 20c, and so on.

[0308] In the second direction Y, the arrangement rule of the power supply branches matches the arrangement sequence of the circuit columns, and each circuit column is arranged to correspond to the power supply branches extending in the first direction, so that the power supply lines PVDD of different color light emitting elements are independent while each circuit column is connected to the corresponding power supply line nearby, so that the power supply lines and the pixel circuits can be connected without additional wiring.

[0309] In other embodiments, referring to FIG. 60 and FIG. 62, one of the first light emitting element 11 and the third light emitting element 13 is a red light emitting element, the other is a blue light emitting element, and the second light emitting element 12 is a green light emitting element; the first power branch 611, the third power branch 623, and the fifth power branch 635 form a second line group, and a plurality of second line groups are arranged in the second direction Y.

[0310] That is, in the second direction Y, the arrangement rule of the power branches is: one first power branch 611, one third power branch 623, and one fifth power branch 635, and then one first power branch 611, one third power branch 623, and one fifth power branch 635, and so on.

[0311] In the second direction Y, the arrangement sequence of the circuit columns is: one first circuit column 20a, one second circuit column 20b, and one third circuit column 20c, and then one first circuit column 20a, one second circuit column 20b, and one third circuit column 20c, and so on.

[0312] Similarly, in this example, in the second direction Y, the arrangement rule of the power branches matches the arrangement sequence of the circuit columns, and each circuit column is correspondingly arranged with the power branches extending in the first direction, so that the power lines PVDD of different color light emitting elements are independent while each circuit column is connected to the corresponding power line nearby, so that the power line and the pixel circuit can be connected without additional wiring.

[0313] In some embodiments, the plurality of pixel circuits of the display panel are arranged in n1 rows; the total number of the second power branch, the fourth power branch, and the sixth power branch is n2; n1 = n2. n1 and n2 are both integers greater than 1.

[0314] For example, as shown in FIG. 7, FIG. 21, FIG. 32, FIG. 37, FIG. 42, FIG. 46, FIG. 50, and FIG. 54, for every two adjacent pixel circuit rows, one pixel circuit row is correspondingly provided with the second power branch 612 and the sixth power branch 636, and the other pixel circuit row is correspondingly provided with the fourth power branch 624.

[0315] In other embodiments, the plurality of pixel circuits of the display panel are arranged in n1 rows; the total number of the second power branch, the fourth power branch, and the sixth power branch is n2; n1 = 2*n2. n1 and n2 are both integers greater than 1.

[0316] For example, for every two adjacent pixel circuit rows, 2 second power branches, 1 fourth power branch, and 1 sixth power branch can be provided.

[0317] In some embodiments, referring to FIGS. 20, 24 and 25, the first power line 61 further includes a seventh power branch 617 extending along the first direction X, the seventh power branch 617 being electrically connected to the first power branch 611 and located in a different film layer.

[0318] The second power line 62 further includes an eighth power branch 628 extending along the first direction X, the eighth power branch 628 being electrically connected to the third power branch 623 and located in a different film layer.

[0319] The third power line 63 further includes a ninth power branch 639 extending along the first direction X, the ninth power branch 639 being electrically connected to the fifth power branch 635 and located in a different film layer.

[0320] This example is equivalent to increasing the grid density of each of the first power line 61, the second power line 62 and the third power line 63, which can further reduce the voltage drop of each power line, thereby further improving display uniformity.

[0321] For example, the seventh power branch 617, the eighth power branch 628 and the ninth power branch 639 are located in the first metal layer SD1, and in this example, the first metal layer SD1 is further provided with reset lines extending along the first direction X, such as the first reset line Vref1 and the second reset line Vref2. For example, power branches are arranged between every two reset lines.

[0322] For example, in the thickness direction of the display panel, the seventh power branch 617 at least partially overlaps the first power branch 611, and / or the eighth power branch 628 at least partially overlaps the third power branch 623, and / or the ninth power branch 639 at least partially overlaps the fifth power branch 635, so that the electrical connection between the corresponding power branches can be achieved through vias without the need to arrange additional connection traces, which can achieve a double longitudinal power branch design without occupying additional layout area, that is, without affecting the realization of high resolution.

[0323] For example, the first reset line Vref1 and / or the second reset line Vref2 can also be designed in a grid pattern. For example, in FIG. 10, at least part of the second trace 92 can be reused as the first reset line Vref1, as shown in FIG. 14, the capacitor metal layer includes the first reset line Vref1 extending along the second direction Y, and the first reset lines Vref1 in FIGS. 10 and 14 are electrically connected to each other, achieving a grid design of the first reset line Vref1.

[0324] For example, in FIG. 10, at least part of the second trace 92 can be reused as a second reset line Vref2. As shown in FIG. 14, the capacitor metal layer includes a second reset line Vref2 extending along the second direction Y. The second reset lines Vref2 in FIG. 10 and FIG. 14 are electrically connected to each other, achieving a mesh design of the second reset line Vref2.

[0325] In some embodiments, the first power branch, the third power branch and the fifth power branch are located on a first film layer of the display panel; and the first film layer includes a data line of the display panel; the second power branch, the fourth power branch and the sixth power branch are located on a second film layer of the display panel; and the first film layer and the second film layer are film layers on a side of the semiconductor layer of the display panel facing the light-emitting surface.

[0326] That is, the first power branch, the third power branch, the fifth power branch and the data line are located on the same first film layer, the second power branch, the fourth power branch and the sixth power branch are located on the same second film layer, and the first film layer and the second film layer are different metal layers. The semiconductor layer is provided with an active layer of a transistor, and the active layer will have a characteristic shift under the influence of light. In the embodiments of the present application, the traces in the first film layer and the second film layer can block light from shining on the active layer in the semiconductor layer, thereby avoiding the characteristic shift of the active layer under the influence of light, and improving the circuit reliability of the display panel.

[0327] The display panel can include one or more semiconductor layers, and the first film layer and the second film layer are located on a side of any one semiconductor layer facing the light-emitting surface.

[0328] As an example, as shown in FIG. 9 and FIG. 10, in addition, in the examples shown in FIG. 23 and FIG. 24, in the examples shown in FIG. 39 and FIG. 40, in the examples shown in FIG. 44 and FIG. 43, the film layers on which the signal lines are located are as follows: the first power branch 611, the third power branch 623, the fifth power branch 635 and the first data line 31, the second data line 32 and the third data line 33 are located on the second metal layer SD2. The second power branch 612, the fourth power branch 624 and the sixth power branch 636 are located on the third metal layer SD3.

[0329] As another example, as shown in FIG. 34 and FIG. 35, in addition, in the examples shown in FIG. 48 and FIG. 49, in the examples shown in FIG. 52 and FIG. 53, in the examples shown in FIG. 56 and FIG. 57, the film layers on which the signal lines are located are as follows: the first power branch 611, the third power branch 623, the fifth power branch 635 and the first data line 31, the second data line 32 and the third data line 33 are located on the third metal layer SD3. The second power branch 612, the fourth power branch 624 and the sixth power branch 636 are located on the second metal layer SD2.

[0330] As another example, referring to FIGS. 62, 63 and 68, the signal lines are located in the following layers: the first power supply branch 611, the third power supply branch 623, the fifth power supply branch 635, and the first data line 31, the second data line 32, and the third data line 33 are located in the first metal layer SD1. The second power supply branch 612, the fourth power supply branch 624, and the sixth power supply branch 636 are located in the capacitor metal layer MC.

[0331] In some examples, as shown in FIGS. 17 and 18, or as shown in FIGS. 67 and 68, the display panel further includes an auxiliary metal layer M0 located on the side of the semiconductor layer close to the substrate PI. The display panel can include one or more semiconductor layers, and the auxiliary metal layer M0 is located on the side of any one of the semiconductor layers close to the substrate PI.

[0332] The auxiliary metal layer M0 includes a first auxiliary line 81, a second auxiliary line 82, and a third auxiliary line 83, which are disconnected from each other. The first auxiliary line 81 is electrically connected to the first power supply line 61, the second auxiliary line 82 is electrically connected to the second power supply line 62, and the third auxiliary line 83 is electrically connected to the third power supply line 63. This example is equivalent to increasing the grid density of each of the first power supply line 61, the second power supply line 62, and the third power supply line 63, which can further reduce the voltage drop of each power supply line, thereby further improving display uniformity.

[0333] The wires in the auxiliary metal layer M0 can also be used to shield the light from the bottom surface from shining into the active layer in the semiconductor layer, thereby avoiding the characteristics of the active layer from being transferred by light, thereby improving the circuit reliability of the display panel.

[0334] As an example, as shown in FIGS. 16 and 17, the wire pattern in the auxiliary metal layer M0 and the wire pattern in the first semiconductor layer overlap in the thickness direction of the display panel.

[0335] As another example, as shown in FIGS. 65 and 67, the wire pattern in the auxiliary metal layer M0 at least overlaps the active layer of the driving transistor.

[0336] In some embodiments, as shown in FIG. 70, a transition line 70 is provided in the display area AA of the display panel, one end of the transition line 70 is connected to the data line 30, the other end of the transition line 70 is connected to the wire in the wire area NA1, and the wire in the wire area NA1 is connected to the driving chip. It can be understood that the transition line 70 is used to transmit the data signal from the driving chip to the data line 30.

[0337] This design can be referred to as "FIAA" design, which can reduce the width of the wire area NA1 and achieve narrow frame.

[0338] Further, in the embodiments of the present application, the power lines of the "FIAA" design and the different color light emitting elements are independent, and the data lines of the different color light emitting elements are independent, so that power consumption can be reduced, and a narrow frame can be realized.

[0339] For example, the adapter wire 70 includes a first wire segment 71 and a second wire segment 72 electrically connected to each other, the first wire segment 71 extends along the first direction X, and the second wire segment 72 extends along the second direction Y.

[0340] As shown in FIG. 10, the first wire segment 71 is located in the same film layer as the first power branch 611. As shown in FIG. 9 and FIG. 11, the second wire segment 72 is located in a different film layer from the second power branch 612. For example, as shown in FIG. 11 and FIG. 18, the second wire segment 72 is located in the first metal layer SD1.

[0341] For example, as shown in FIG. 10, the display area of the display panel includes a plurality of first wires 91 extending along the first direction X. For example, the area where the adapter wire 70 is located is referred to as a "FIAA area", and the area outside the adapter wire 70 is referred to as a "non-FIAA area". The first wires 91 in the "FIAA area" are multiplexed as the first wire segment 71, and the first wires 91 in the "non-FIAA area" can be multiplexed as the common voltage line PVEE. Alternatively, the first wires 91 in the "non-FIAA area" can be multiplexed as the reset lines Vref1, Vref2 or other signal lines, etc. It can be understood that when the first wires in the "FIAA area" and the "non-FIAA area" transmit different signals, the two are disconnected from each other.

[0342] For example, as shown in FIG. 11, the display area of the display panel includes a plurality of third wires 93 extending along the second direction Y. Here, the area where the adapter wire 70 is located is still referred to as a "FIAA area", and the area outside the adapter wire 70 is referred to as a "non-FIAA area". The third wires 93 in the "FIAA area" are multiplexed as the second wire segment 72, and the third wires 93 in the "non-FIAA area" can be multiplexed as the common voltage line PVEE. Alternatively, the third wires 93 in the "non-FIAA area" can be multiplexed as the reset lines Vref1, Vref2 or other signal lines, etc. It can be understood that when the third wires in the "FIAA area" and the "non-FIAA area" transmit different signals, the two are disconnected from each other.

[0343] For example, as shown in FIG. 10, the display area of the display panel further includes a plurality of second wires 92 extending along the first direction X. The first wires 91 and the second wires 92 are arranged adjacent to each other, and the first wires 91 and the second wires 92 are located between two data lines. For example, the first wires 91 and the second wires 92 are arranged between the first data line 31 and the third data line 33, and the first wires 91 and the second wires 92 are arranged between the second data line 32 and the third data line 33.

[0344] In the above embodiments, the data lines of the light emitting elements of different colors are independent, and the power supply lines of the light emitting elements of different colors are independent. In other embodiments, the power supply lines of the light emitting elements of different colors are independent, and the data lines of at least two light emitting elements of different colors are not independent.

[0345] For example, as shown in FIG. 71, the first light emitting element 11 is electrically connected with the first pixel circuit 21, the second light emitting element 12 is electrically connected with the second pixel circuit 22, and the data line 31' is electrically connected with both the first pixel circuit 21 and the second pixel circuit 22 in the same column. That is, the data line 31' is used to provide the data signals required by the two color light emitting elements, and the first light emitting element 11 and the second light emitting element 12 share the data line. In addition, the third light emitting element 13 is electrically connected with the third pixel circuit 23, and the data line 32' is electrically connected with a plurality of third pixel circuits 23 in the same column.

[0346] In FIG. 71, the approximate positions of the pixel circuits are shown by dashed boxes, and the first pixel circuit 21 is schematically shown by a dashed box filled with gray to distinguish the first pixel circuit 21 from the second pixel circuit 22.

[0347] The power supply line PVDD includes a first power supply line 61, a second power supply line 62, and a third power supply line 63. The first power supply line 61 is electrically connected with the first pixel circuit 21, and the first power supply line 61 includes a first power supply branch 611 and a second power supply branch 612 which are electrically connected with each other. One of the first power supply branch 611 and the second power supply branch 612 can be electrically connected with the first pixel circuit 21 through a via. The second power supply line 62 is electrically connected with the second pixel circuit 22, and the second power supply line 62 includes a third power supply branch 623 and a fourth power supply branch 624 which are electrically connected with each other. One of the third power supply branch 623 and the fourth power supply branch 624 can be electrically connected with the second pixel circuit 22 through a via. The third power supply line 63 is electrically connected with the third pixel circuit 23, and the third power supply line 63 includes a fifth power supply branch 635 and a sixth power supply branch 636 which are electrically connected with each other. One of the fifth power supply branch 635 and the sixth power supply branch 636 can be electrically connected with the third pixel circuit 23 through a via.

[0348] The features of each power supply branch can refer to those of the above embodiments, which will not be repeated here.

[0349] It should be noted that FIG. 71 is used to schematically show the electrical connection relationship between the data lines, the power supply lines, and the pixel circuits, and is not used to limit the relative position relationship between the data lines and the power supply lines. In FIG. 71, a solid black dot is used to represent that two power supply branches are electrically connected with each other, however, the solid black dot is not used to limit the connection positions of the two power supply branches, as long as the two power supply branches can be connected.

[0350] For example, as shown in FIG. 71, the power supply branch extending along the first direction X can include a branch that at least partially overlaps the third light emitting element 13 in the thickness direction of the display panel, so that the surface on which the third light emitting element 13 is located is as planar as possible, thereby ensuring the light emitting effect of the third light emitting element 13.

[0351] For example, as shown in FIG. 72, at least part of the power supply branch extending along the second direction Y can also include a branch, and the pixel circuit includes a driving transistor, and the gate of the driving transistor is connected to other transistors through a metal connection. In the thickness direction of the display panel, the branch of at least part of the power supply branch extending along the second direction Y overlaps the metal connection, and the branch transmits a power supply voltage, which is generally a fixed voltage, so that the branch can be used to shield the influence of other signals on the gate potential of the driving transistor.

[0352] It should be noted that the above various embodiments can be combined with each other without contradiction.

[0353] The display device provided in the present application includes the display panel provided in the present application. Please refer to FIG. 73, which is a structural schematic diagram of a display device provided in an embodiment of the present application. The display device 1000 provided in FIG. 73 includes a display panel 100, and the display panel 100 includes the display panel provided in any of the above embodiments of the present application. The display device 1000 is described by taking a mobile phone as an example in the embodiment of FIG. 73. It can be understood that the display device provided in the embodiments of the present application can be a wearable product, a computer, a television, a vehicle-mounted display device, or other display devices having a display function, and the present application does not make a specific limitation thereon. The display device provided in the embodiments of the present application has the beneficial effects of the display panel provided in the embodiments of the present application, and specific descriptions can be made with reference to the specific descriptions of the display panel in the above embodiments, which will not be described herein again.

[0354] The embodiments described above are not exhaustive in terms of details, nor do they limit the present application to only the specific embodiments described. It is obvious that, according to the above description, many modifications and changes can be made. The embodiments are selected and specifically described in this specification in order to better explain the principles and practical applications of the present application, so that those skilled in the art can well utilize the present application and make modifications and uses on the basis of the present application. The present application is limited only by the claims and their entire scope and equivalents.

Claims

1. A display panel, comprising: light emitting elements including first light emitting elements, second light emitting elements, and third light emitting elements, the first light emitting elements, the second light emitting elements, and the third light emitting elements having different light emitting colors, a first unit column including the first light emitting elements and the second light emitting elements arranged alternately in a first direction, a second unit column including a plurality of the third light emitting elements arranged in the first direction, the first unit column and the second unit column arranged alternately in a second direction, the first direction and the second direction intersecting each other; first circuit columns, second circuit columns, and third circuit columns, the first circuit columns including a plurality of first pixel circuits arranged in the first direction, the second circuit columns including a plurality of second pixel circuits arranged in the first direction, the third circuit columns including a plurality of third pixel circuits arranged in the first direction, the first pixel circuits electrically connected to first data lines and the first light emitting elements, the second pixel circuits electrically connected to second data lines and the second light emitting elements, the third pixel circuits electrically connected to third data lines and the third light emitting elements.

2. The display panel of claim 1, wherein, A number of pixel circuit columns in the display panel is greater than a number of light emitting element columns, and a part of the circuit columns includes virtual pixel circuits, the first light emitting elements are electrically connected to the first pixel circuits through first vias, and a plurality of the first vias corresponding to a same first circuit column form a first via column; for a first circuit column not including the virtual pixel circuits, in the second direction, a plurality of the first light emitting elements electrically connected to the first pixel circuits through the vias on the same first via column are respectively located on both sides of the first via column; the second light emitting elements are electrically connected to the second pixel circuits through second vias, and a plurality of the second vias corresponding to a same second circuit column form a second via column; for a second circuit column not including the virtual pixel circuits, in the second direction, a plurality of the second light emitting elements electrically connected to the second pixel circuits through the vias on the same second via column are respectively located on both sides of the second via column.

3. The display panel of claim 2, wherein, For a same first unit column, in the second direction, the first vias and the second vias are respectively located on both sides of the first unit column.

4. The display panel of claim 2, wherein, the first light emitting elements and the second light emitting elements are arranged alternately in the second direction to form first unit rows, for a same first unit row, in the second direction, a relative position relationship between the first vias and the first light emitting elements is same as a relative position relationship between the second vias and the second light emitting elements.

5. The display panel of claim 2, wherein, an anode of the first light emitting element is electrically connected to a first end of the first via through a first connection line, a second end of the first via is electrically connected to the first pixel circuit, and the first connection line and the anode of the first light emitting element are located in a same film layer; An anode of the second light emitting element is electrically connected to the first end of the second via hole through a second connecting line, and the second end of the second via hole is electrically connected to the second pixel circuit, the second connecting line and the anode of the second light emitting element are located in the same film layer. The display panel comprises at least two semiconductor layers.

6. The display panel of claim 5, wherein, The length of the first connecting line is less than the maximum width of the first light emitting element along the second direction, and the length of the second connecting line is less than the maximum width of the second light emitting element along the second direction.

7. The display panel of claim 6, wherein, For the same element column, the first connecting line and the second connecting line extend in intersecting directions.

8. The display panel of claim 2, wherein, The display panel comprises a first connecting line and a second connecting line, the first connecting line comprises a first segment and a second segment, the first segment is connected between the anode of the first light emitting element and the first end of the first via hole, and the second segment is connected between the second end of the first via hole and the first pixel circuit, the first segment and the anode of the first light emitting element are located in the same film layer, and the second segment is located in the metal layer on the side of the anode of the first light emitting element facing the substrate. The second connecting line comprises a third segment and a fourth segment, the third segment is connected between the anode of the second light emitting element and the first end of the second via hole, and the fourth segment is connected between the second end of the second via hole and the second pixel circuit, the third segment and the anode of the second light emitting element are located in the same film layer, and the fourth segment is located in the metal layer on the side of the anode of the second light emitting element facing the substrate. The display panel comprises one semiconductor layer.

9. The display panel of claim 8, wherein, The display panel comprises a data line, in the thickness direction of the display panel, the film layers where the second segment and the fourth segment are located are located between the film layer where the data line is located and the anode of the light emitting element.

10. The display panel of claim 2, wherein, In the thickness direction of the display panel, at least part of the first circuit column overlaps with at least part of the plurality of first light emitting elements connected thereto, and at least part of the second circuit column overlaps with at least part of the plurality of second light emitting elements connected thereto.

11. The display panel of claim 2, wherein, In the thickness direction of the display panel, part of the first unit columns at least partially overlap with the first data line and the third data line, and another part of the first unit columns at least partially overlap with the second data line and the third data line, and the second unit columns do not overlap with the data lines.

12. The display panel of claim 1, wherein, The number of pixel circuit columns in the display panel is equal to the number of light emitting element columns; two adjacent first unit columns form a first unit column group; the display panel comprises a plurality of first unit column groups; the first circuit column is electrically connected to a plurality of first light emitting elements in the first unit column group, and the second circuit column is electrically connected to a plurality of second light emitting elements in the first unit column group.

13. The display panel of claim 12, wherein, The first light emitting element is electrically connected to the first pixel circuit through a first via hole, and the second light emitting element is electrically connected to the second pixel circuit through a second via hole. In the first unit column group, in the second direction, the first via of one of the first unit columns is on a first side of the first unit column, the second via is on a second side of the first unit column, and the first via and the second via of another of the first unit columns are distributed on the same side of the first unit column.

14. The display panel of claim 12, wherein, The first light emitting element is electrically connected to the first pixel circuit through a first connecting line, at least a part of the first connecting line is located in a different film layer from a data line of the display panel.

15. The display panel of claim 14, wherein, In a thickness direction of the display panel, at least a part of the first connecting line overlaps the second light emitting element.

16. The display panel of claim 14, wherein, In a thickness direction of the display panel, at least a part of the second light emitting element and at least a part of the second pixel circuit electrically connected to the second light emitting element overlap, and the display panel comprises at least two semiconductor layers.

17. The display panel of claim 12, wherein, The first light emitting element is electrically connected to the first pixel circuit through a first connecting line, the second light emitting element is electrically connected to the second pixel circuit through a second connecting line, at least a part of the first connecting line and at least a part of the second connecting line are located in different film layers from a data line of the display panel, and the display panel comprises one semiconductor layer.

18. The display panel of claim 12, wherein, The first light emitting element is electrically connected to the first pixel circuit through a first via, and the second light emitting element is electrically connected to the second pixel circuit through a second via. In the second direction, the first via of any one of the first unit columns is on a first side of the first unit column, and the second via is on a second side of the second unit column.

19. The display panel of claim 18, wherein, The first light emitting element is electrically connected to the first pixel circuit through a first connecting line, the length of the first connecting line in the second direction between the first via and the first pixel circuit is L1, and the width of the pixel circuit of the display panel in the second direction is L2, 3*L2≤L1≤4*L2.

20. The display panel of claim 12, wherein, The first light emitting element is electrically connected to the first pixel circuit through a first via, and the second light emitting element is electrically connected to the second pixel circuit through a second via. In the second direction, the first via and the second via of any one of the first unit columns are distributed on the same side of the first unit column.

21. The display panel of claim 20, wherein, The first light emitting element is electrically connected to the first pixel circuit through a first connecting line, the second light emitting element is electrically connected to the second pixel circuit through a second connecting line, and the first connecting line and the second connecting line do not overlap.

22. The display panel of claim 1, wherein, The third light emitting element is electrically connected to the third pixel circuit through a third via, and in the first direction, any one of the third vias is on the same side of the third light emitting element connected thereto.

23. The display panel of claim 1, wherein, The element unit comprises adjacent first light emitting elements, second light emitting elements, and third light emitting elements. The first light emitting element is electrically connected to the first pixel circuit through a first via, the second light emitting element is electrically connected to the second pixel circuit through a second via, and the third light emitting element is electrically connected to the third pixel circuit through a third via. In the first direction, the first via, the second via and the third via of the element unit are located on the same side of the element unit.

24. The display panel of claim 23, wherein, The first unit column and the second unit column adjacent to each other form a second unit column group, and each second unit column group is provided with three pixel circuits.

25. The display panel of claim 23, wherein, The anode of the second light emitting element is electrically connected to the second via through a second connecting line, and the second connecting line is located between the first light emitting element and the third light emitting element in a direction parallel to the light emitting surface of the display panel.

26. The display panel of claim 1, wherein, The pixel circuit of the display panel comprises a driving transistor and a power supply line electrically connected to the driving transistor, and there is no connection between the active layers of adjacent driving transistors.

27. The display panel of claim 1, wherein, The light emitting element is electrically connected to the pixel circuit through a via, and the via comprises a first sub-via which does not overlap with the pixel circuit electrically connected thereto. The display panel further comprises a connecting line, one end of the connecting line being connected to the first sub-via, and the other end being connected to the pixel circuit.

28. The display panel of claim 27, wherein, The display panel comprises a power supply branch extending in the second direction, and the connecting line and the power supply branch are located in the same film layer.

29. The display panel of claim 28, wherein, The via comprises a second sub-via, and the second sub-via at least partially overlaps with the pixel circuit electrically connected thereto. The display panel further comprises a compensation line, one end of the compensation line being connected to the second sub-via.

30. The display panel of claim 29, wherein, The other end of the compensation line is suspended.

31. The display panel of claim 29, wherein, The compensation line and the connecting line are in the same film layer.

32. The display panel of claim 1, wherein, The display panel further comprises a power supply line, comprising a first power supply line and a second power supply line, the first power supply line being electrically connected to the first light emitting element, the first power supply line comprising a first power supply branch and a second power supply branch electrically connected to each other, the first power supply branch extending in the first direction, and the second power supply branch extending in the second direction; the second power supply line being electrically connected to the second light emitting element, the second power supply line comprising a third power supply branch and a fourth power supply branch electrically connected to each other, the third power supply branch extending in the first direction, and the fourth power supply branch extending in the second direction.

33. The display panel of claim 32, wherein, The power supply line further comprises a third power supply line electrically connected to the third light emitting element, the third power supply line comprising a fifth power supply branch and a sixth power supply branch electrically connected to each other, the fifth power supply branch extending in the first direction, and the sixth power supply branch extending in the second direction, wherein one of the second power supply branch and the fourth power supply branch is electrically connected to the sixth power supply branch, or the second power supply branch, the fourth power supply branch and the sixth power supply branch are independent of each other.

34. The display panel of claim 33, wherein, One of the first light emitting element and the second light emitting element is a red light emitting element, and the other is a blue light emitting element, and the third light emitting element is a green light emitting element; the first power supply branch, the fifth power supply branch, the third power supply branch and the fifth power supply branch form a first line group, and a plurality of first line groups are arranged in the second direction.

35. The display panel of claim 33, wherein, One of the first light emitting element and the third light emitting element is a red light emitting element, and the other is a blue light emitting element, and the second light emitting element is a green light emitting element; The first power supply branch, the third power supply branch and the fifth power supply branch constitute a second line group, and a plurality of the second line groups are arranged in the second direction.

36. The display panel of claim 33, wherein, The plurality of pixel circuits of the display panel are arranged in n1 rows; The total number of the second power supply branch, the fourth power supply branch and the sixth power supply branch is n2; n1 = n2, or n1 = 2*n2, and n1 and n2 are both integers greater than 1.

37. The display panel of claim 33, wherein, The first power supply line further comprises a seventh power supply branch, the seventh power supply branch extends along the first direction, the seventh power supply branch is electrically connected with the first power supply branch and located in different film layers; The second power supply line further comprises an eighth power supply branch, the eighth power supply branch extends along the first direction, the eighth power supply branch is electrically connected with the third power supply branch and located in different film layers; The third power supply line further comprises a ninth power supply branch, the ninth power supply branch extends along the first direction, the ninth power supply branch is electrically connected with the fifth power supply branch and located in different film layers.

38. The display panel of claim 33, wherein, The first power supply branch, the third power supply branch and the fifth power supply branch are located in a first film layer of the display panel; and the first film layer comprises a data line of the display panel; The second power supply branch, the fourth power supply branch and the sixth power supply branch are located in a second film layer of the display panel; The first film layer and the second film layer are both film layers on the side of the semiconductor layer of the display panel facing the light emitting surface.

39. The display panel of claim 38, wherein, The display panel further comprises an auxiliary metal layer, the auxiliary metal layer is located on the side of the semiconductor layer close to the substrate; The auxiliary metal layer comprises a first auxiliary line, a second auxiliary line and a third auxiliary line which are disconnected with each other, the first auxiliary line is electrically connected with the first power supply line, the second auxiliary line is electrically connected with the second power supply line, and the third auxiliary line is electrically connected with the third power supply line.

40. The display panel of claim 38, wherein, The display panel further comprises a transfer line, the transfer line is located in the display area and connected with the data line, the transfer line comprises a first line segment and a second line segment which are electrically connected with each other, the first line segment extends along the first direction and is located in the same film layer as the first power supply branch, and the second line segment extends along the second direction and is located in different film layers from the second power supply branch.

41. A display device comprising the display panel of any one of claims 1-40.

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