Data processing method and apparatus

Abstract

A data processing method. The method comprises: a first instance performs a first processing process, the first processing process being a full inference process performed by means of a machine learning model; and a second instance performs a second processing process, the second processing process being an incremental inference process performed by means of the machine learning model, wherein the first instance and the second instance are different instances running on a same computing unit, and the first processing process and the second processing process are performed in parallel. In embodiments of the present application, different instances running on a same computing unit are used to respectively perform a full inference process and an incremental inference process by means of a machine learning model, thereby reducing overhead of data communication between devices and storage overhead, shortening an overall end-to-end delay, and correspondingly increasing the transactions per second (TPS).

Description

Data processing method and apparatus thereof

[0001] The present application claims priority from the Chinese patent application No. 202411243006.1 filed on September 4, 2024, and entitled "A data processing method and apparatus thereof", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the field of artificial intelligence, and in particular to a data processing method and apparatus thereof. BACKGROUND

[0003] Artificial intelligence (AI) is the use of digital computers or digital computer-controlled machines to simulate, extend and expand human intelligence, perceive the environment, acquire knowledge and use knowledge to obtain the best results. In other words, artificial intelligence is a branch of computer science that aims to understand the essence of intelligence and produce a new intelligent machine that can react in a similar way to human intelligence. Artificial intelligence researches the design principles and implementation methods of various intelligent machines, enabling machines to have perception, reasoning and decision-making functions.

[0004] Currently, large language models mainly use the Transformer network structure. The Transformer network is characterized by self-attention, which can well obtain the key information in the dialogue and the relationship between the previous and subsequent words, and output better answers. The Transformer network includes many layers, each layer includes Attention and FFN structure, and the Attention structure needs to use the Q variable of the current token to calculate with the KV of the previous token to obtain the relationship between the current token and the previous token. In order to speed up the calculation process, KV Cache is usually used to store the KV of the previous token, thereby reducing the repeated calculation of the KV of the previous token. The processing process of the first token is called the full calculation process (prefill stage), and the processing process of the non-first token is called the incremental calculation stage (decoding stage).

[0005] In the prior art, the two stages are processed by the same instance, which makes the end-to-end delay and other performances poor, or the full calculation process and the incremental calculation process are performed by different processing units (physically), which will cause additional communication overhead and storage overhead between hardware. SUMMARY

[0006] In a first aspect, the present application provides a data processing method, comprising: performing a first processing process by a first instance, the first processing process being a full inference process performed by a machine learning model; performing a second processing process by a second instance, the second processing process being an incremental inference process performed by the machine learning model; wherein the first instance and the second instance are different instances running on a same computing unit, and the first processing process and the second processing process are performed in parallel.

[0007] In the embodiments of the present application, the full inference process and the incremental inference process performed by the machine learning model are respectively performed by different instances running on the same computing unit, thereby reducing the data communication overhead and storage overhead between devices, shortening the overall end-to-end latency, and accordingly improving the number of requests per second.

[0008] In a possible implementation, the method further comprises: determining an allocation strategy of allocating computing resources to the first instance according to the running performance of the computing unit; or adjusting the allocation strategy of allocating computing resources to the second instance according to the running performance of the computing unit.

[0009] The configuration of the computing resources can be performed at each Step or even finer granularity, thereby increasing the TPS.

[0010] In a possible implementation, the running performance comprises a computing power load.

[0011] The determination of the allocation strategy of allocating computing resources to the first instance according to the running performance of the computing unit comprises:

[0012] when the computing power load is lower than a first threshold, increasing the computing power resources allocated to the first instance; or

[0013] The adjustment of the allocation strategy of allocating computing resources to the second instance according to the running performance of the computing unit comprises:

[0014] when the computing power load is higher than a second threshold, reducing the computing power resources allocated to the second instance.

[0015] Generally, the Prefill stage is a computation-intensive task, and the Decoding stage is a memory-intensive task, so when the running performance of the computing unit indicates that there are more computing power resources (that is, the computing power load is lower than the first threshold), the computing power resources can be preferentially allocated to the first instance, and when the running performance of the computing unit indicates that there are fewer memory resources (that is, the computing power load is higher than the second threshold), the computing power resources allocated to the second instance can be reduced.

[0016] In a possible implementation, the running performance includes a memory access load.

[0017] The determining, according to the running performance of the computing unit, of the allocation strategy of the computing resource allocated to the first instance includes:

[0018] when the memory access load is lower than a third threshold, increasing the memory bandwidth resource allocated to the second instance.

[0019] The adjusting, according to the running performance of the computing unit, of the allocation strategy of the computing resource allocated to the second instance includes:

[0020] when the memory access load is lower than a third threshold, increasing the memory bandwidth resource allocated to the second instance.

[0021] Generally, the Prefill stage is a computation-intensive task, and the Decoding stage is a memory access-intensive task. Therefore, when the running performance on the computing unit indicates that there are more memory access resources (for example, the memory access load is lower than a third threshold), the computing resource can be preferentially allocated to the first instance, and when the running performance on the computing unit indicates that there are fewer memory access resources (for example, the memory access load is higher than a third threshold), the memory access resource can be preferentially allocated to the second instance.

[0022] In a possible implementation, the running performance includes an execution latency.

[0023] The determining, according to the running performance of the computing unit, of the allocation strategy of the computing resource allocated to the first instance includes:

[0024] when the execution latency is higher than a fourth threshold, increasing the computing resource allocated to the first instance; or

[0025] The adjusting, according to the running performance of the computing unit, of the allocation strategy of the computing resource allocated to the second instance includes:

[0026] when the execution latency is higher than a fourth threshold, increasing the memory bandwidth resource allocated to the first instance.

[0027] In a possible implementation, the method further includes:

[0028] determining the allocation strategy of the computing resource allocated to the first instance according to a processing load when the first instance performs a first processing process; or

[0029] adjusting the allocation strategy of the computing resource allocated to the second instance according to a processing load when the second instance performs a second processing process.

[0030] In a possible implementation, the determining of the allocation strategy of allocating the computing resources to the first instance according to the processing load of the first processing process performed by the first instance comprises:

[0031] when the processing load is greater than a fifth threshold, increasing the computing resource allocated to the first instance; or

[0032] the adjusting of the allocation strategy of allocating the computing resources to the second instance according to the processing load of the second processing process performed by the second instance comprises:

[0033] when the processing load is greater than a fifth threshold, increasing the memory bandwidth resource allocated to the second instance.

[0034] In a possible implementation, the method further comprises:

[0035] when the memory bandwidth for performing the second processing process by the second instance is less than a preset minimum bandwidth or the execution delay is greater than a preset maximum delay, not reducing the computing resource allocated to the second instance.

[0036] In a possible implementation, the method further comprises:

[0037] when a bottleneck of the memory resource is encountered when the first processing process is performed by the first instance or the execution delay is greater than a preset maximum delay, not reducing the memory bandwidth resource allocated to the first instance.

[0038] Decoding stage memory bandwidth is the most sensitive factor affecting Decoding delay, and Prefill stage computing core number is the most sensitive factor affecting Prefill delay, when Decoding delay increases by more than a maximum Decoding delay, the Decoding computing core is no longer reduced, when Decoding bandwidth is less than a minimum Decoding bandwidth, the Decoding computing core is no longer reduced, when Prefill delay increases by more than a maximum Prefill delay, the Prefill bandwidth is no longer reduced, and when Prefill is converted from a computing bond task to a memory bond task, the Prefill bandwidth is no longer reduced.

[0039] In a possible implementation, the method further comprises:

[0040] receiving a processing request;

[0041] adding a full-inference task in the processing request to a first queue;

[0042] adding an incremental processing task in the processing request to a second queue;

[0043] The first processing process comprises: executing a to-be-processed task in the first queue.

[0044] The second processing process comprises: executing a to-be-processed task in the second queue.

[0045] In a possible implementation, the machine learning model is a language model, the first processing process comprises loading parameters of the language model, obtaining a processing request, executing the processing request by using the parameters of the language model, and obtaining KV data and a newly generated first token, and the second processing process comprises loading the parameters of the language model, obtaining the KV data in the KV cache, and obtaining the KV data of the first token and a newly generated second token by using the parameters of the language model.

[0046] In a second aspect, the present application provides a data processing apparatus, comprising:

[0047] a full-inference module configured to perform a first processing process by using a first instance, the first processing process being a full-inference process performed by using a machine learning model;

[0048] an incremental-inference module configured to perform a second processing process by using a second instance, the second processing process being an incremental-inference process performed by using the machine learning model; wherein the first instance and the second instance are different instances running on a same computing unit, and the first processing process and the second processing process are performed in parallel.

[0049] In a possible implementation, the apparatus further comprises:

[0050] a control module configured to determine an allocation strategy of allocating computing resources to the first instance according to a running performance of the computing unit; or

[0051] adjust an allocation strategy of allocating computing resources to the second instance according to the running performance of the computing unit.

[0052] In a possible implementation, the running performance comprises a computing power load.

[0053] The control module is specifically configured to:

[0054] when the computing power load is lower than a first threshold, increase the computing power resources allocated to the first instance; or

[0055] when the computing power load is higher than a second threshold, decrease the computing power resources allocated to the second instance.

[0056] In a possible implementation, the running performance comprises a memory access load.

[0057] The control module is specifically configured to:

[0058] When the memory access load is higher than a third threshold, reduce the memory bandwidth resource allocated to the first instance; or,

[0059] When the memory access load is lower than the third threshold, increase the memory bandwidth resource allocated to the second instance.

[0060] In a possible implementation, the running performance includes an execution latency.

[0061] The control module is specifically configured to:

[0062] When the execution latency is higher than a fourth threshold, increase the computing power resource allocated to the first instance; or,

[0063] When the execution latency is higher than the fourth threshold, increase the memory bandwidth resource allocated to the first instance.

[0064] In a possible implementation, the apparatus further includes:

[0065] A control module is configured to determine an allocation strategy of computing resources allocated to the first instance according to a processing load when the first instance performs a first processing process; or,

[0066] Adjust the allocation strategy of computing resources allocated to the second instance according to a processing load when the second instance performs a second processing process.

[0067] In a possible implementation, the control module is specifically configured to:

[0068] When the processing load is greater than a fifth threshold, increase the computing power resource allocated to the first instance; or,

[0069] When the processing load is greater than the fifth threshold, increase the memory bandwidth resource allocated to the second instance.

[0070] In a possible implementation, the apparatus further includes:

[0071] A control module is configured to, when a memory access bandwidth for performing the second processing process by the second instance is less than a preset minimum bandwidth, or an execution latency is greater than a preset maximum latency, not reduce the computing power resource allocated to the second instance.

[0072] In a possible implementation, the apparatus further includes:

[0073] A control module is configured to, when a bottleneck of a memory resource is encountered when the first instance performs the first processing process, or an execution latency is greater than a preset maximum latency, not reduce the memory bandwidth resource allocated to the first instance.

[0074] In a possible implementation, the apparatus further includes:

[0075] a control module, configured to receive a processing request;

[0076] add a full-inference task in the processing request to a first queue;

[0077] add an incremental processing task in the processing request to a second queue;

[0078] the first processing procedure includes: executing a to-be-processed task in the first queue;

[0079] the second processing procedure includes: executing a to-be-processed task in the second queue.

[0080] In a possible implementation,

[0081] the machine learning model is a language model, the first processing procedure includes loading parameters of the language model, obtaining a processing request, executing the processing request by using the parameters of the language model, obtaining KV data and newly generated first tokens, and the second processing procedure includes loading the parameters of the language model, obtaining the KV data in the KV cache, and obtaining the KV data of the first tokens and newly generated second tokens by using the parameters of the language model.

[0082] In a third aspect, an embodiment of the present application provides a data processing apparatus, which can include a memory, a processor, and a bus system, wherein the memory is configured to store a program, and the processor is configured to execute the program in the memory to perform the method in the first aspect and any optional method.

[0083] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, which stores a computer program, and when the computer program is executed on a computer, the computer program causes the computer to perform the method in the first aspect and any optional method.

[0084] In a fifth aspect, an embodiment of the present application provides a computer program, which, when executed on a computer, causes the computer to perform the method in the first aspect and any optional method.

[0085] In a sixth aspect, the present application provides a chip system, which includes a processor configured to support execution of a data processing apparatus to implement functions involved in the above aspects, for example, sending or processing data involved in the above method; or, information. In a possible design, the chip system further includes a memory, and the memory is configured to save necessary program instructions and data for the execution device or the training device. The chip system can be composed of a chip, or can include a chip and other discrete devices. BRIEF DESCRIPTION OF DRAWINGS

[0086] Fig. 1 is a structural schematic diagram of an artificial intelligence subject framework;

[0087] Figs. 2 to 4 are schematic diagrams of application system frameworks of the present application;

[0088] Fig. 5 is a flow schematic diagram of a data processing method provided by an embodiment of the present application;

[0089] Figs. 6A to 7C are application example schematics provided by an embodiment of the present application;

[0090] Fig. 8 is a structural schematic diagram of a data processing apparatus provided by an embodiment of the present application;

[0091] Fig. 9 is a structural schematic diagram of an execution device provided by an embodiment of the present application;

[0092] Fig. 10 is a structural schematic diagram of a training device provided by an embodiment of the present application;

[0093] Fig. 11 is a structural schematic diagram of a chip provided by an embodiment of the present application. DETAILED DESCRIPTION

[0094] The embodiments of the present application are described below with reference to the accompanying drawings. The terms used in the embodiments section of the present application are only used to explain the specific embodiments of the present application, and are not intended to limit the present application.

[0095] The embodiments of the present application are described below with reference to the accompanying drawings. The skilled person can know that, with the development of technology and the appearance of new scenarios, the technical solutions provided by the embodiments of the present application are also applicable to similar technical problems.

[0096] The terms “first”, “second”, and the like in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or sequence. It should be understood that the terms used in this way can be interchanged under appropriate circumstances, and this is only a distinguishing way adopted in the description of the embodiments of the present application for the objects with the same attribute in the description. In addition, the terms “include” and “have” and any variations thereof are intended to cover non-exclusive inclusion, so that the processes, methods, systems, products or devices containing a series of units do not have to be limited to those units, but can include other units that are not clearly listed or inherent to these processes, methods, products or devices.

[0097] The terms "substantially," "about," and similar terms as used herein are taken to mean approximately, as in a tolerably close or approximate value, and not to mean exactly or perfectly. In describing the embodiments of the present application, the use of "may" means that one or more embodiments can. The terms "use," "using," and "used" can be taken to be synonymous with the terms "utilize," "utilizing," and "utilized," respectively. Additionally, the term "exemplary" is intended to mean an example or an illustration.

[0098] First, the overall workflow of the artificial intelligence system is described, please refer to Figure 1, which shows a structural diagram of an artificial intelligence subject framework. The following describes the artificial intelligence subject framework from two dimensions of "intelligent information chain" (horizontal axis) and "IT value chain" (vertical axis). The "intelligent information chain" reflects a series of processes from data acquisition to processing. For example, it can be a general process of intelligent information perception, intelligent information representation and formation, intelligent reasoning, intelligent decision-making, intelligent execution and output. In this process, data undergoes a condensation process of "data-information-knowledge-wisdom". The "IT value chain" reflects the value brought by artificial intelligence to the information technology industry from the underlying infrastructure of human intelligence, information (provision and processing technology implementation) to the industrial ecological process of the system.

[0099] (1) Infrastructure

[0100] The infrastructure provides computing power support for the artificial intelligence system, realizes communication with the outside world, and realizes support through the underlying platform. Communication with the outside world through sensors; computing power is provided by intelligent chips (CPU, NPU, GPU, ASIC, FPGA, etc. Hardware acceleration chips); the underlying platform includes distributed computing framework and network related platform guarantee and support, which can include cloud storage and computing, interconnection network, etc. For example, sensors and external communication obtain data, which are provided to intelligent chips in the distributed computing system provided by the underlying platform for calculation.

[0101] (2) Data

[0102] The data on the upper layer of the infrastructure is used to represent the data source in the field of artificial intelligence. Data involves graphics, images, speech, text, and also involves Internet of Things data of traditional devices, including business data of existing systems and sensing data such as force, displacement, liquid level, temperature, and humidity.

[0103] (3) Data processing

[0104] Data processing generally includes data training, machine learning, deep learning, search, reasoning, decision, etc.

[0105] Among them, machine learning and deep learning can model, extract, preprocess, train, etc. of symbolic and formalized intelligent information on data.

[0106] Reasoning refers to the process of simulating human intelligent reasoning methods in a computer or intelligent system, using formalized information to solve problems according to reasoning control strategies, and the typical function is search and matching.

[0107] Decision refers to the process of decision-making after intelligent information is reasoned, and usually provides functions such as classification, sorting, and prediction.

[0108] (4) General capabilities

[0109] After data is processed as mentioned above, some general capabilities can be formed based on the results of data processing, such as algorithms or a general system, for example, translation, text analysis, computer vision processing, speech recognition, image recognition, etc.

[0110] (5) Intelligent products and industry applications

[0111] Intelligent products and industry applications refer to products and applications of artificial intelligence systems in various fields, which are encapsulations of overall solutions of artificial intelligence, and realize application landing by productizing intelligent information decision-making. The application fields mainly include intelligent terminals, intelligent transportation, intelligent medical treatment, automatic driving, smart city, etc.

[0112] The system architecture provided by the embodiments of the present application will be described in detail below in combination with FIG. 2.

[0113] FIG. 2 is a schematic diagram of the system architecture provided by the embodiments of the present application. As shown in FIG. 2, the system architecture 500 includes an execution device 510, a training device 520, a database 530, a client device 540, a data storage system 550, and a data collection device 560.

[0114] The execution device 510 includes a computing module 511, an I / O interface 512, a preprocessing module 513, and a preprocessing module 514. The target model / rule 501 can be included in the computing module 511, and the preprocessing module 513 and the preprocessing module 514 are optional.

[0115] The data collection device 560 is used to collect training samples. After collecting the training samples, the data collection device 560 stores the training samples in the database 530.

[0116] The training device 520 can train the neural network to be trained (for example, the machine learning model in the embodiments of the present application) based on the training samples maintained in the database 530, to obtain the target model / rule 501.

[0117] It should be understood that the training device 520 can perform a pre-training process on the neural network to be trained based on the training samples maintained in the database 530, or fine-tune the model based on the pre-training.

[0118] It should be noted that in actual application, the training samples maintained in the database 530 can not all come from the collection of the data collection device 560, but can also be received from other devices. In addition, it should be noted that the training device 520 can not completely train the target model / rule 501 based on the training samples maintained in the database 530, but can also obtain training samples from the cloud or other places for model training, and the above description should not be regarded as a limitation of the embodiments of the present application.

[0119] The target model / rule 501 trained by the training device 520 can be applied to different systems or devices, such as the execution device 510 shown in FIG. 2. The execution device 510 can be a terminal such as a mobile phone terminal, a tablet computer, a notebook computer, an augmented reality (AR) / virtual reality (VR) device, a vehicle-mounted terminal, etc., and can also be a server, etc.

[0120] Specifically, the training device 520 can deliver the trained model to the execution device 510.

[0121] In FIG. 2, the execution device 510 is configured with an input / output (I / O) interface 512 for data interaction with external devices. The user can input data to the I / O interface 512 through the client device 540.

[0122] The pre-processing modules 513 and 514 are used for pre-processing the input data received by the I / O interface 512. It should be understood that there can be no pre-processing modules 513 and 514 or only one pre-processing module. When there is no pre-processing module 513 and 514, the input data can be directly processed by the calculation module 511.

[0123] During the pre-processing of the input data by the execution device 510, or during the calculation and other related processing of the calculation module 511 of the execution device 510, the execution device 510 can call the data, code, etc. in the data storage system 550 for corresponding processing, or store the data, instructions, etc. obtained by the corresponding processing in the data storage system 550.

[0124] Finally, the I / O interface 512 provides the processing result to the client device 540, and thus to the user.

[0125] In the case shown in FIG. 2, the user can manually give the input data, which can be operated through the interface provided by the I / O interface 512. In another case, the client device 540 can automatically send the input data to the I / O interface 512, and if the authorization of the user is required for the client device 540 to automatically send the input data, the user can set the corresponding permission in the client device 540. The user can view the result output by the execution device 510 in the client device 540, and the specific presentation form can be a specific way such as display, sound, action, etc. The client device 540 can also serve as a data collection end to collect the input data input into the I / O interface 512 and the output result output from the I / O interface 512 as new sample data, and store the new sample data into the database 530. Of course, the collection can also be performed without the client device 540, and the I / O interface 512 can directly store the input data input into the I / O interface 512 and the output result output from the I / O interface 512 as new sample data into the database 530.

[0126] It is worth noting that FIG. 2 is only a schematic diagram of a system architecture provided by an embodiment of the present application, and the positional relationship between the devices, components, modules, etc. shown in the diagram does not constitute any limitation. For example, in FIG. 2, the data storage system 550 is an external memory relative to the execution device 510, and in other cases, the data storage system 550 can also be placed in the execution device 510. It should be understood that the above execution device 510 can be deployed in the client device 540.

[0127] From the inference side of the model:

[0128] In the embodiment of the present application, the computing module 511 of the execution device 510 can obtain the code stored in the data storage system 550 to implement the steps related to the model inference process in the embodiment of the present application.

[0129] In the embodiments of the present application, the computing module 511 of the execution device 510 can include a hardware circuit (such as an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a general-purpose processor, a digital signal processor (DSP), a microprocessor or a microcontroller, etc.), or a combination of these hardware circuits. For example, the training device 520 can be a hardware system with an execution instruction function, such as a CPU, a DSP, etc., or a hardware system without an execution instruction function, such as an ASIC, an FPGA, etc., or a combination of the hardware system without an execution instruction function and the hardware system with an execution instruction function.

[0130] Specifically, the computing module 511 of the execution device 510 can be a hardware system with an execution instruction function. The steps related to the model inference process provided in the embodiments of the present application can be software codes stored in a memory. The computing module 511 of the execution device 510 can obtain the software codes from the memory and execute the obtained software codes to implement the steps related to the model inference process provided in the embodiments of the present application.

[0131] It should be understood that the computing module 511 of the execution device 510 can be a combination of a hardware system without an execution instruction function and a hardware system with an execution instruction function. Part of the steps related to the model inference process provided in the embodiments of the present application can also be implemented by the hardware system without an execution instruction function in the computing module 511 of the execution device 510, which is not limited here.

[0132] From the training side of the model:

[0133] In the embodiments of the present application, the training device 520 can obtain the codes stored in the memory (not shown in FIG. 2, which can be integrated in the training device 520 or deployed separately from the training device 520) to implement the steps related to the model training in the embodiments of the present application.

[0134] In the embodiments of the present application, the training device 520 can include a hardware circuit (such as an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a general-purpose processor, a digital signal processor (DSP), a microprocessor or a microcontroller, etc.), or a combination of these hardware circuits. For example, the training device 520 can be a hardware system with an instruction execution function, such as a CPU, a DSP, etc., or a hardware system without an instruction execution function, such as an ASIC, an FPGA, etc., or a combination of the hardware system without an instruction execution function and the hardware system with an instruction execution function.

[0135] It should be understood that the training device 520 can be a combination of a hardware system without an instruction execution function and a hardware system with an instruction execution function, and the part of the steps related to the training of the neutralization model provided in the embodiments of the present application can also be implemented by the hardware system without an instruction execution function in the training device 520, which is not limited here.

[0136] In the embodiments of the present application, the forward propagation process of the model can be performed by the execution device 510 or the training device 520 introduced in the above embodiments.

[0137] In addition, the execution device 510 or the training device 520 can process the input data through the machine learning model, wherein the machine learning model can include an attention layer, the attention layer can perform attention calculation on the input token, and the attention layer can obtain an intermediate result that needs to be reused when performing attention calculation on the token in the future. For example, the intermediate result can be KV data. In this process, when processing a new token, the obtained intermediate result that can be reused can be stored in the memory, so that when the intermediate result needs to be reused for attention calculation on other tokens in the future, the intermediate result can be read from the memory and used for attention calculation on the token in the future. However, the amount of intermediate results that can be reused that need to be stored will rapidly increase as the inference proceeds, resulting in a large demand for storage. In addition, too much intermediate result will also make the inference process extremely slow, so compression of the intermediate result that can be reused is particularly important.

[0138] In an implementation, the compression process can be performed by a compression module, which can be deployed centrally with the execution device 510 or the training device 520, e.g., belonging to the same chip or other granularity of computing unit, or deployed separately, e.g., belonging to different chips. For example, the execution device 510 or the training device 520 can be an AI chip, and the compression module can belong to a CPU.

[0139] Since the embodiments of the present application involve the application of a large number of neural networks, in order to facilitate understanding, the related terms and concepts related to neural networks involved in the embodiments of the present application will be introduced first.

[0140] (1) Neural network

[0141] The neural network can be composed of neural units, and a neural unit can refer to an operation unit with xs (i.e., input data) and an intercept 1 as input. The output of the operation unit can be:

[0142] where s = 1, 2, … n, n is a natural number greater than 1, Ws is the weight of xs, b is the bias of the neural unit. f is an activation function of the neural unit, which is used to introduce a nonlinear characteristic into the neural network to convert the input signal in the neural unit into an output signal. The output signal of the activation function can be used as the input of the next layer of convolutional layer, and the activation function can be a sigmoid function. The neural network is a network formed by connecting a plurality of single neural units together, i.e., the output of one neural unit can be the input of another neural unit. The input of each neural unit can be connected to the local receptive field of the previous layer to extract the features of the local receptive field, and the local receptive field can be a region composed of a plurality of neural units.

[0143] (2) Convolutional Neural Network (CNN) is a kind of deep neural network with convolutional structure. CNN contains a feature extractor composed of convolutional layers and subsampling layers, which can be regarded as a filter. The convolutional layer refers to the neuron layer in the CNN that performs convolution processing on the input signal. In the convolutional layer of the CNN, a neuron can be connected only to part of the adjacent layer neurons. A convolutional layer usually contains several feature planes, each of which can be composed of some rectangularly arranged neural units. The neural units of the same feature plane share weights, and the shared weights are the convolution kernel. The shared weights can be understood as the way of extracting features regardless of the position. The convolution kernel can be formalized in the form of a matrix of random size, and the convolution kernel can obtain reasonable weights through learning in the training process of the CNN. In addition, the direct benefit of shared weights is to reduce the connections between the layers of the CNN and reduce the risk of overfitting.

[0144] CNN is a very common neural network, and the structure of CNN will be introduced in detail below. As described in the previous introduction of basic concepts, CNN is a deep neural network with convolutional structure, which is a deep learning architecture. Deep learning architecture refers to learning at multiple levels on different abstraction levels through machine learning algorithms. As a deep learning architecture, CNN is a feed-forward artificial neural network, and each neuron in the feed-forward artificial neural network can respond to the input image.

[0145] (3) Deep Neural Network

[0146] Deep Neural Network (DNN), also known as multi-layer neural network, can be understood as a neural network with many hidden layers, where "many" has no special measurement standard. From the division of DNN by different layers, the neural network inside the DNN can be divided into three categories: input layer, hidden layer, and output layer. Generally, the first layer is the input layer, the last layer is the output layer, and the number of layers in between is the hidden layer. The layers are fully connected, that is, any neuron in the i-th layer is connected to any neuron in the i+1-th layer. Although DNN looks very complex, in terms of the work of each layer, it is actually not complex. Simply put, it is as follows: where, is the input vector, is the output vector, is the bias vector, W is the weight matrix (also called coefficient), and a() is the activation function. Each layer is only a linear relationship expression on the input vector After such a simple operation, the output vector is obtained Since the DNN has many layers, the number of coefficients W and offset vectors is also large. These parameters are defined in the DNN as follows: taking the coefficient W as an example: suppose in a three-layer DNN, the linear coefficient of the fourth neuron of the second layer to the second neuron of the third layer is defined as The superscript 3 represents the layer number of the coefficient W, and the subscript corresponds to the third layer index 2 of the output and the second layer index 4 of the input. In summary: the coefficient of the kth neuron of the L-1th layer to the jth neuron of the Lth layer is defined as It should be noted that the input layer has no W parameter. In a deep neural network, more hidden layers allow the network to better describe complex situations in the real world. In theory, the more parameters a model has, the higher its complexity and "capacity", which means it can complete more complex learning tasks. Training a deep neural network is a process of learning the weight matrix, and the ultimate goal is to obtain the weight matrix of all layers of the trained deep neural network (the weight matrix formed by many layers of vectors W).

[0147] (4) Loss function

[0148] In the process of training a deep neural network, because the output of the deep neural network is expected to be as close as possible to the value that is really wanted to be predicted, the weight vector of each layer of the neural network can be updated according to the difference between the current network prediction value and the target value that is really wanted to be predicted (of course, before the first update, there is usually an initialization process, i.e., pre-configuring parameters for each layer in the deep neural network), for example, if the network prediction value is high, adjust the weight vector to make it predict lower, and keep adjusting until the deep neural network can predict the target value that is really wanted to be predicted or a value very close to it. Therefore, it is necessary to define "how to compare the difference between the prediction value and the target value" in advance, which is the loss function or the objective function, which is an important equation for measuring the difference between the prediction value and the target value. Among them, taking the loss function as an example, the higher the output value (loss) of the loss function, the greater the difference, and then the training of the deep neural network becomes a process of trying to minimize this loss.

[0149] (5) Backpropagation algorithm

[0150] The back propagation (BP) algorithm can be used to correct the size of the parameters in the initial model during the training process, so that the error loss of the model becomes smaller and smaller. Specifically, the forward propagation of the input signal will produce an error loss, and the parameters in the initial model are updated by back propagating the error loss information, so that the error loss converges. The back propagation algorithm is a back propagation movement dominated by error loss, aiming to obtain optimal model parameters, such as weight matrices.

[0151] (6) Large Language Model: Large Language Model refers to a natural language processing model trained on large-scale data, usually with tens of billions or hundreds of billions of parameters. These models capture general features of language by learning a large amount of text data in the pre-training phase, and can then be fine-tuned on downstream tasks to adapt to specific task requirements.

[0152] (7)transformer: transformer is a deep learning model architecture, originally used for sequence-to-sequence tasks such as machine translation. It uses self-attention mechanisms to process input sequences and has achieved great success in natural language processing. Most large language models, such as BERT, GPT and T5, are based on the Transformer architecture.

[0153] (8) KV cache: KV cache refers to a cache structure that stores key-value pairs. In large language models, KV cache is usually used to store intermediate results or other useful information when processing text to improve efficiency. By using KV cache, the model can avoid repeated calculations when processing text.

[0154] (9) KV cache quantization: KV cache quantization refers to quantizing the values in the KV cache to reduce storage space and computational overhead. In some large language models, in order to make the model adapt to limited resources, the values in the KV cache can be quantized to reduce the storage and computational cost of the model.

[0155] (10) PPL (Perplexity): PPL is an index used to evaluate the performance of a language model, representing the model's prediction ability for a given text sequence. PPL is a positive real number, which can be understood as the average difficulty of the model's prediction for the observed data sequence. The lower the PPL, the better the model's performance.

[0156] (11) Non-Uniform Quantization: Non-Uniform Quantization is a quantization method in which the numerical range is divided into intervals of different sizes to better adapt to the data distribution. Unlike uniform quantization, non-uniform quantization can allocate different numbers of numerical ranges to each interval according to the distribution of data.

[0157] (12) Token: In natural language processing, "token" is the basic unit of text string segmentation. It can be a word, a character or a sub-word fragment. Large language models usually need to divide the input text into tokens, and then convert these tokens into numerical representations (such as word vectors) that the model can understand.

[0158] (13) Sequence: In the context of large language models, "sequence" refers to a sequence of elements with a certain order relationship, and multiple tokens make up a sequence.

[0159] (14) Incremental Inference: Incremental Inference allows the model to only process the newly added input part, rather than reprocessing the entire sequence every time. This is achieved by maintaining context information in the internal state of the model, allowing the model to quickly respond when receiving new input. Incremental Inference is particularly useful in interactive applications such as chatbots or real-time translation, as it can significantly reduce latency and the use of computing resources.

[0160] (15) Step: A reasoning stage for generating one or more tokens.

[0161] (16) Prefill: Prefill KV Cache stage, that is, the first token output process.

[0162] (17) Decoding: Decoding process, that is, the non-first token output process.

[0163] (18) Bond: Bottlenecked by a certain resource, such as memory bond, which is bottlenecked by memory, and compute bond, which is bottlenecked by computation.

[0164] Currently, large language models mainly use the Transformer network structure. The Transformer network is characterized by self-attention, which can well obtain the key information in the dialogue and the relationship between the previous and subsequent words, and output better answers. The Transformer network includes many layers, and each layer includes an Attention and an FFN structure. The Attention structure needs to use the Q variable of the current token to calculate the KV of the previous token to obtain the relationship between the current token and the previous token. In order to speed up the calculation process, KV Cache is usually used to store the KV of the previous token, thereby reducing the repeated calculation of the KV of the previous token. The processing process of the first token is called the full calculation process (prefill stage), and the processing process of the non-first token is called the incremental calculation stage (decoding stage).

[0165] In the prior art, the two stages of processing are performed by the same instance, which makes the end-to-end delay and other performances poor, or the full calculation process and the incremental calculation process are performed by different processing units (physically), which will cause additional communication overhead and storage overhead between hardware.

[0166] Taking FIG. 3 as an example, the process from input to output is explained. The user inputs “The future of AI is”, and the model is expected to complete the subsequent output in a text continuation manner. The user input is called a prompt. According to different encoding methods, a word can be encoded into multiple tokens, or multiple words can be encoded into one token. For the sake of simple understanding, it is assumed that a word is a token. When the user input is completed, the model starts the calculation process, and outputs one token each time. In this example, “exciting” is output first, then “and”, and then “uncertain”. Each calculation is called a step. According to whether the output is the first token, it is divided into the first token and the non-first token. For the calculation of the first token, the KV Cache calculation of the previous 5 tokens is needed, that is, the light gray part in the figure. For the calculation of the non-first token, such as “and”, only the KV Cache of “exciting” needs to be calculated, and the KV Cache of the previous 5 tokens stored in the light gray part can be directly obtained. The step of the first token is called the full calculation stage (prefill stage), and the step of the non-first token is called the incremental calculation stage (decoding stage).

[0167] The calculation of the Transformer network has the following characteristics:

[0168] 1. Prefill stage takes much longer time than Decoding stage.

[0169] 2. Prefill stage and Decoding stage have different load models, Prefill stage is compute-intensive task, Decoding stage is memory-intensive task.

[0170] Model inference service usually uses group batching to improve throughput, which means multiple user inputs are completed in one step. Generally speaking, since Prefill is a compute-intensive task, group batching cannot improve business throughput. But Decoding stage can improve throughput through group batching, because in the case of group batching, the Decoding memory bottleneck can be solved by accessing memory multiple times and computing once.

[0171] Large language model inference service business can accept different requests from multiple clients at the same time and return model output results to multiple clients. Requests and outputs can be in the form of text continuation, question and answer, etc. The performance indicators of inference service are usually as follows:

[0172] 1. End-to-end latency: the time from input to the end of all outputs for each request.

[0173] 2. TPS or RPS: that is, the number of requests per second, used to measure the throughput of the service.

[0174] 3. First token latency: the latency of the first token of each request.

[0175] 4. Non-first token latency: the latency of non-first token of each request.

[0176] Generally speaking, the smaller the end-to-end latency, first token latency, and non-first token latency, the better the performance, and the larger the TPS or RPS, the better the performance. AI service aims to achieve higher TPS under the same latency, which means it can serve more users. Existing technologies to improve TPS include Continuous Batching, SplitFuse, PD separation, etc., which will be further expanded in the following.

[0177] Continuous batching technology improves performance by calculating a Prefill and multiple Decoding groups in batch. Group batch can essentially reduce memory access overhead by accessing memory multiple times and calculating once. As shown in FIG. 4, the light gray part is the prefill, and the dark gray part is the decoding. R1 and R2 represent two incoming requests. The horizontal axis is time. After two requests arrive, the inference service calculates the prefill of R2 and the decoding of R1 in a group batch in a step. Compared with the separate execution of the prefill, this prefill can carry several decodings, although the prefill time is slightly longer than the separate execution, the gray part is the lengthened time, but the overall throughput can be increased.

[0178] The prior art can effectively improve the overall service throughput by group batch, but the end-to-end latency of R1 is lengthened. The reason for these deficiencies is that the several decodings of the group batch are slowed down by the prefill, and the decoding latency becomes the prefill latency.

[0179] To solve the above problems, the embodiment of the application provides a data processing method. The data processing method of the embodiment of the application will be described in detail below with reference to the accompanying drawings.

[0180] Referring to FIG. 5, FIG. 5 is a flow diagram of a data processing method provided by the embodiment of the application. As shown in FIG. 5, the data processing method provided by the embodiment of the application can include steps 501 to 502, which will be described in detail below.

[0181] 501. Perform a first processing process by a first instance, the first processing process being a full inference process by a machine learning model;

[0182] 502. Perform a second processing process by a second instance, the second processing process being an incremental inference process by the machine learning model; wherein the first instance and the second instance are different instances running on the same computing unit, and the first processing process and the second processing process are performed in parallel.

[0183] An instance is a software module that can run an application program or a system program, and the software module can be called an instance only when it is run by an operating system, otherwise, it is only a piece of code. There are various forms of instances, for example, processes and threads can be understood as one of the forms of instances.

[0184] The computing unit can be a computing card, such as an AI processing chip, for example, NPU, TPU, GPU, etc.

[0185] In a possible implementation, the machine learning model is a language model, the first processing procedure includes loading parameters of the language model, obtaining a processing request, performing the processing request by using the parameters of the language model, obtaining KV data and newly generated first tokens, and the second processing procedure includes loading parameters of the language model, obtaining KV data in the KV cache, and obtaining KV data of the first tokens and newly generated second tokens by using the parameters of the language model.

[0186] In a possible implementation, a processing request can be received, full-inference tasks in the processing request can be added to a first queue, and incremental processing tasks in the processing request can be added to a second queue, and then the tasks in the first queue can be executed, and the tasks in the second queue can be executed.

[0187] In the embodiments of the present application, the full-inference process and the incremental-inference process performed by the machine learning model are respectively performed by different instances running on the same computing unit, so that the data communication overhead between devices is reduced, the overall end-to-end latency is shortened, and the number of requests per second (TPS) is correspondingly improved.

[0188] In a possible implementation, an allocation strategy of allocating computing resources to the first instance can be determined according to the running performance of the computing unit, and the allocation strategy of allocating computing resources to the second instance can be adjusted according to the running performance of the computing unit.

[0189] The configuration of the computing resources can be performed at each Step or even finer granularity, so that the TPS can be increased.

[0190] The computing power resources can be configured by configuring the block dim, for example, the computing power resources can be allocated by setting the corresponding block dim parameter when launching the kernel. The computing power resources can also be controlled by controlling the grid dim or thread dim parameters.

[0191] The memory access bandwidth can be configured by using the MPAM bandwidth control interface. The memory resources can be allocated by setting the corresponding partid when launching the kernel.

[0192] In a possible implementation, the running performance includes computing power load, the computing power resources allocated to the first instance can be increased when the computing power load is lower than a first threshold, or the computing power resources allocated to the second instance can be reduced when the computing power load is higher than a second threshold.

[0193] Generally, the Prefill stage is a compute-intensive task, and the Decoding stage is a memory-intensive task. Therefore, when the running performance of the computing unit indicates that there are more computing resources (i.e., the computing load is lower than the first threshold value), the computing resources can be preferentially allocated to the first instance; and when the running performance of the computing unit indicates that there are fewer memory resources (i.e., the computing load is higher than the second threshold value), the memory resources allocated to the second instance can be reduced.

[0194] In a possible implementation, the running performance includes a memory load; the memory bandwidth resources allocated to the first instance can be reduced when the memory load is higher than a third threshold value; or the memory bandwidth resources allocated to the second instance can be increased when the memory load is lower than the third threshold value.

[0195] Generally, the Prefill stage is a compute-intensive task, and the Decoding stage is a memory-intensive task. Therefore, when the running performance of the computing unit indicates that there are more memory resources (e.g., the memory load is lower than the third threshold value), the computing resources can be preferentially allocated to the first instance; and when the running performance of the computing unit indicates that there are fewer memory resources (e.g., the memory load is higher than the third threshold value), the memory resources can be preferentially allocated to the second instance.

[0196] In a possible implementation, the running performance includes an execution latency; the computing resources allocated to the first instance can be increased when the execution latency is higher than a fourth threshold value; or the memory bandwidth resources allocated to the first instance can be increased when the execution latency is higher than the fourth threshold value.

[0197] In a possible implementation, the allocation strategy of the computing resources allocated to the first instance can be determined according to a processing load when the first instance performs the first processing process; or the allocation strategy of the computing resources allocated to the second instance can be adjusted according to a processing load when the second instance performs the second processing process.

[0198] That is, the current Prefill and Decoding loads can be obtained in real time, and the resource strategy can be dynamically adjusted according to the current load.

[0199] In a possible implementation, the computing resources allocated to the first instance can be increased when the processing load is greater than a fifth threshold value; or the memory bandwidth resources allocated to the second instance can be increased when the processing load is greater than the fifth threshold value.

[0200] In a possible implementation, when the memory access bandwidth of the second processing process performed by the second instance is less than a preset minimum bandwidth or the execution delay is greater than a preset maximum delay, the computing resource allocated to the second instance is not reduced.

[0201] In a possible implementation, when the first processing process performed by the first instance encounters a bottleneck of memory access resources or the execution delay is greater than a preset maximum delay, the memory bandwidth resource allocated to the first instance is not reduced.

[0202] The memory bandwidth in the decoding stage is the most sensitive factor affecting the decoding delay, and the number of calculation cores in the prefill stage is the most sensitive factor affecting the prefill delay. When the decoding delay increases by more than the maximum decoding delay, the decoding calculation core is no longer reduced. When the decoding bandwidth is less than the minimum decoding bandwidth, the decoding calculation core is no longer reduced. When the prefill delay increases by more than the maximum prefill delay, the prefill bandwidth is no longer reduced. When the prefill is converted from a calculation bond task to a memory bond task, the prefill bandwidth is no longer reduced.

[0203] Referring to FIG. 6A, FIG. 6A is a system architecture diagram of an embodiment of the present application: it contains software modules: AI Client, load balancing module, LLM service, wherein the optimization module: LLM service, adds a load sensing module. It contains hardware modules: GPU / NPU, wherein the optimization module: resource scheduling control unit.

[0204] Here, the hardware basis is explained in two dimensions of computing power and memory bandwidth. GPU / NPU provides the ability to accelerate the execution of large language models. GPU provides multiple SMs (NPU provides multiple acceleration cores) to perform matrix operations in parallel to improve the execution efficiency of large language models. When users use the GPU / NPU runtime interface to issue operators, they can specify how many SMs or how many cores to use for parallel execution. For example, the GPU interface cuLaunchKernel provides a BlockDim parameter for users to configure.

[0205] The above explains the hardware implementation of the computing load. The hardware control capability of the memory bandwidth is explained as follows:

[0206] For the control of memory bandwidth, ARM hardware provides MPAM capability, and X86 provides RDT capability. That is, the calculation core can bring a partid to describe the identity of the request when initiating memory access. Users can use MPAM to control the bandwidth and cache size of the request of a partid.

[0207] The software structure related to the present application has the following module functions:

[0208] The LLM service module supports prefill and decoding parallel and supports prefill and decoding parallel scheduling;

[0209] The load sensing device and resource strategy in the LLM service module support dynamic adjustment of resources according to northbound and southbound loads;

[0210] The resource scheduling control module of the GPU / NPU is modified to provide hardware interface configuration computing power and memory access resources;

[0211] Referring to FIG. 6B, which is a system architecture diagram of an embodiment of the present application:

[0212] It contains software modules: LLMEngine, PD separation scheduling module, Distributed Workers, KV Cache management module, PD Model parallel execution module (provides resource configuration interface), load sensing device and resource strategy module, wherein the newly added modules (or optimized modules) are: LLMEngine, PD separation scheduling module, PD Model parallel execution module (provides resource configuration interface), load sensing device and resource strategy module.

[0213] It contains hardware modules: GPU / NPU, wherein the newly added modules (or optimized modules) are: hardware provides resource configuration interface and profiler capability, and their functions are as follows:

[0214] LLMEngine supports Prefill and Decoding parallel (CPU): Prefill threads and Decoding threads can be started in this way;

[0215] Prefill and Decoding load independent scheduling capability: Prefill threads independently obtain Prefill scheduling results, and Decoding threads independently obtain Decoding scheduling results;

[0216] Model execution module supports Prefill and Decoding parallel (GPU / NPU): Prefill Stream and Decoding Stream can be created in this way;

[0217] Load sensing device dynamically adjusts resources: the current Prefill and Decoding load is obtained from the scheduling module in real time, the load (computing power / memory bandwidth / execution delay, etc.) is collected from the GPU / NPU in real time, and the resource strategy is dynamically adjusted according to the current business load and hardware resource situation;

[0218] Resource policy configuration: The Model Parallel Execution module configures the computing power resources according to the resource policy configuration during Prefill or Decoding execution, configures the computing power execution block dim of Prefill and Decoding, and configures the memory bandwidth through the MPAM bandwidth control interface provided by the GPU / NPU.

[0219] The logical (working / connection) relationship between the software and the hardware is as follows:

[0220] The PD Model Parallel module uses the GPU or NPU to complete model execution, and can configure the resource consumption of this run through the resource configuration interface before execution. The load sensing module can collect profiler performance data of the GPU or NPU online or offline, and adjust the resource policy. Finally, the effect of FIG. 7A is achieved.

[0221] Referring to FIG. 7B, FIG. 7B is an application flowchart of an embodiment of the present application, which includes the following steps:

[0222] Step one: LLMEngine accepts a new request and inserts the request into the prefill queue of the Scheduler module;

[0223] Step two: LLMEngine creates two threads, namely a prefill thread and a decoding thread, and the two threads execute the inference step in parallel;

[0224] Step three: the prefill thread and the decoding thread call the scheduling algorithm of the Scheduler module to obtain the corresponding request, and the interface transmits the current thread identity, for example, prefill transmits prefill and decoding transmits decoding;

[0225] Step four: the scheduler module queries the prefill queue or the decoding queue according to the thread identity, returns a prefill request for the prefill thread, and returns multiple decoding requests for the decoding thread;

[0226] Step five: the prefill thread and the decoding thread allocate their own device resources according to the resource policy, including computing power resources and memory resources. The way to allocate computing power resources is to set the corresponding blockdim parameter when launching the kernel, and the way to allocate memory resources is to set the corresponding partid when launching the kernel.

[0227] Step six: LLMEngine starts prefill inference and decoding inference;

[0228] Step seven: Distributed Workers do TP split;

[0229] Step eight: Model execution module uses GPU / NPU to complete inference and returns the result;

[0230] Step nine: whether the current request has been processed, if yes, end, if not, re-insert the corresponding scheduler queue, for example, the request of prefill end is inserted into the decoding queue of scheduler, the request of decoding end is still inserted into the decoding queue of scheduler, repeat steps three to eight until the request is processed.

[0231] In addition, the load sensing device adjusts the resource strategy in real time according to the length of the prefill and decoding queues in the scheduler and the profiler data on the GPU / NPU side, so as to achieve the optimal allocation of resources according to the PD load. When the PD load changes, the load sensing device can flexibly adjust the PD resources to achieve the optimal performance.

[0232] Referring to FIG. 7C, which is a flowchart of the load sensing module: including scheduling load conditions and device side performance Profiling data, it is known that: the decoding stage memory bandwidth is the most sensitive factor affecting the decoding delay, and the prefill stage calculation core number is the most sensitive factor affecting the prefill delay.

[0233] The device side PD delay and bandwidth are used as negative feedback to adjust the resource strategy, including:

[0234] 1. When the decoding delay increases > the maximum decoding delay, the decoding calculation core is no longer reduced;

[0235] 2. When the decoding bandwidth < the minimum decoding bandwidth, the decoding calculation core is no longer reduced;

[0236] 3. When the prefill delay increases > the maximum prefill delay, the prefill bandwidth is no longer reduced;

[0237] 4. When the prefill is converted from a calculation bond task to a memory bond task, the prefill bandwidth is no longer reduced;

[0238] It should be understood that the device side Profiling data can also come from offline data analysis.

[0239] Referring to FIG. 8, FIG. 8 is a structural diagram of a data processing apparatus provided by an embodiment of the present application. As shown in FIG. 8, the data processing apparatus provided by an embodiment of the present application includes:

[0240] a full reasoning module 801, configured to perform a first processing process by a first instance, the first processing process being a full reasoning process performed by a machine learning model;

[0241] an incremental reasoning module 802, configured to perform a second processing process by a second instance, the second processing process being an incremental reasoning process performed by the machine learning model; wherein the first instance and the second instance are different instances running on a same computing unit, and the first processing process and the second processing process are performed in parallel.

[0242] In a possible implementation, the apparatus further includes:

[0243] a control module, configured to determine an allocation strategy of allocating computing resources to the first instance according to a running performance of the computing unit; or

[0244] adjust an allocation strategy of allocating computing resources to the second instance according to the running performance of the computing unit.

[0245] In a possible implementation, the running performance includes a computing power load.

[0246] The control module is specifically configured to:

[0247] when the computing power load is lower than a first threshold, increase the computing power resources allocated to the first instance; or

[0248] when the computing power load is higher than a second threshold, decrease the computing power resources allocated to the second instance.

[0249] In a possible implementation, the running performance includes a memory access load.

[0250] The control module is specifically configured to:

[0251] when the memory access load is higher than a third threshold, decrease the memory bandwidth resources allocated to the first instance; or

[0252] when the memory access load is lower than the third threshold, increase the memory bandwidth resources allocated to the second instance.

[0253] In a possible implementation, the running performance includes an execution delay.

[0254] The control module is specifically configured to:

[0255] increase the computing power resource allocated to the first instance when the execution latency is higher than a fourth threshold; or

[0256] increase the memory bandwidth resource allocated to the first instance when the execution latency is higher than a fourth threshold.

[0257] In a possible implementation, the apparatus further includes:

[0258] a control module configured to determine an allocation strategy of computing resources allocated to the first instance according to a processing load when the first instance performs the first processing process; or

[0259] adjust the allocation strategy of computing resources allocated to the second instance according to a processing load when the second instance performs the second processing process.

[0260] In a possible implementation, the control module is specifically configured to:

[0261] increase the computing power resource allocated to the first instance when the processing load is greater than a fifth threshold; or

[0262] increase the memory bandwidth resource allocated to the second instance when the processing load is greater than a fifth threshold.

[0263] In a possible implementation, the apparatus further includes:

[0264] a control module configured to not reduce the computing power resource allocated to the second instance when a memory bandwidth for performing the second processing process by the second instance is less than a preset minimum bandwidth or an execution latency is greater than a preset maximum latency.

[0265] In a possible implementation, the apparatus further includes:

[0266] a control module configured to not reduce the memory bandwidth resource allocated to the first instance when a bottleneck of a memory resource is encountered when the first instance performs the first processing process or an execution latency is greater than a preset maximum latency.

[0267] In a possible implementation, the apparatus further includes:

[0268] a control module configured to receive a processing request;

[0269] add all-inference tasks in the processing request to a first queue;

[0270] add incremental processing tasks in the processing request to a second queue;

[0271] The first processing process comprises: executing the to-be-processed tasks in the first queue.

[0272] The second processing process comprises: executing the to-be-processed tasks in the second queue.

[0273] In a possible implementation,

[0274] The machine learning model is a language model, the first processing process comprises loading parameters of the language model, obtaining a processing request, executing the processing request through the parameters of the language model, obtaining KV data and newly generated first tokens, and the second processing process comprises loading parameters of the language model, obtaining KV data in the KV cache, and obtaining KV data of the first tokens and newly generated second tokens through the parameters of the language model.

[0275] Next, a terminal device provided in an embodiment of the present application is introduced. Referring to FIG. 9, FIG. 9 is a structural schematic diagram of a terminal device provided in an embodiment of the present application. The terminal device 900 can specifically be a virtual reality (VR) device, a mobile phone, a tablet computer, a notebook computer, a smart wearable device, etc., which is not limited herein. Specifically, the terminal device 900 comprises a receiver 901, a transmitter 902, a processor 903 and a memory 904 (wherein the number of processors 903 in the terminal device 900 can be one or more, and one processor is taken as an example in FIG. 9). The processor 903 can comprise an application processor 9031 and a communication processor 9032. In some embodiments of the present application, the receiver 901, the transmitter 902, the processor 903 and the memory 904 can be connected through a bus or other means.

[0276] The memory 904 can comprise a read-only memory and a random access memory, and provide instructions and data for the processor 903. A part of the memory 904 can further comprise a non-volatile random access memory (NVRAM). The memory 904 stores processor and operation instructions, executable modules or data structures, or subsets thereof, or extended sets thereof, wherein the operation instructions can comprise various operation instructions for implementing various operations.

[0277] The processor 903 controls the operation of the execution device. In a specific application, various components of the execution device are coupled together through a bus system, wherein the bus system can comprise a data bus, a power supply bus, a control bus and a state signal bus, etc. in addition to the data bus. However, in order to clearly illustrate, various buses are referred to as a bus system in the figure.

[0278] The method disclosed in the embodiments of the present application can be applied to the processor 903 or implemented by the processor 903. The processor 903 can be an integrated circuit chip having a signal processing capability. In the implementation process, the steps of the above method can be completed by hardware integrated logic circuits in the processor 903 or by instructions in the form of software. The processor 903 described above can be a general processor, a digital signal processor (DSP), a microprocessor or a microcontroller, and can further include an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component. The processor 903 can implement or execute the methods, steps and logic block diagrams disclosed in the embodiments of the present application. The general processor can be a microprocessor or the processor can also be any conventional processor or the like. The steps of the method disclosed in combination with the embodiments of the present application can be directly embodied as a hardware code processor for execution, or a combination of hardware and software modules in the code processor for execution. The software module can be located in a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register or other mature storage medium in the art. The storage medium is located in the memory 904, and the processor 903 reads the information in the memory 904, and combines the hardware to complete the steps related to model training or model inference process in the above method.

[0279] The receiver 901 can be used to receive input digital or character information, and generate signal input related to the relevant settings and function control of the execution device. The transmitter 902 can be used to output digital or character information through the first interface; the transmitter 902 can also be used to send instructions to the disk group through the first interface to modify the data in the disk group; the transmitter 902 can also include a display device such as a display screen.

[0280] The server provided in the embodiments of the present application can have a large difference due to different configurations or performances, and can include one or more central processing units (CPUs) 1010 (for example, one or more processors) and a memory 1032, one or more storage media 1030 (for example, one or more mass storage devices) for storing application programs 1042 or data 1044. The memory 1032 and the storage media 1030 can be temporary storage or persistent storage. The programs stored in the storage media 1030 can include one or more modules (not shown in the figure), and each module can include a series of instruction operations in the server. Further, the central processing unit 1010 can be configured to communicate with the storage media 1030 and execute the series of instruction operations in the storage media 1030 on the server 1000.

[0281] The server 1000 can also include one or more power supplies 1026, one or more wired or wireless network interfaces 1050, one or more input and output interfaces 1058, or one or more operating systems 1041, such as Windows ServerTM, Mac OS XTM, UnixTM, LinuxTM, FreeBSDTM, and the like.

[0282] In the embodiments of the present application, the central processing unit 1010 is configured to perform the actions related to model training or model inference in the above embodiments.

[0283] The embodiments of the present application also provide a computer program product including a computer program for performing the steps of the above-described execution device, or the steps of the above-described training device, when the computer program product is run on a computer.

[0284] The embodiments of the present application also provide a computer readable storage medium having a program for performing signal processing stored therein, which causes a computer to perform the steps of the above-described execution device, or the steps of the above-described training device, when the computer readable storage medium is run on the computer.

[0285] The execution device, the training device or the terminal device provided in the embodiments of the present application can specifically be a chip, which comprises a processing unit, for example, a processor, and a communication unit, for example, an input / output interface, a pin or a circuit, etc. The processing unit can execute computer execution instructions stored in a storage unit, so that the chip in the execution device executes the data processing method described in the above embodiments, or so that the chip in the training device executes the data processing method described in the above embodiments. Alternatively, the storage unit is a storage unit in the chip, such as a register, a cache, etc., and the storage unit can also be a storage unit outside the chip in the wireless access device, such as a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, a random access memory (RAM), etc.

[0286] Specifically, please refer to FIG. 11, which is a structural schematic diagram of a chip provided in the embodiments of the present application. The chip can be represented as a neural network processor NPU 1100, which is mounted on a host CPU (Host CPU) as a coprocessor and is assigned tasks by the Host CPU. The core part of the NPU is an operation circuit 1103, which extracts matrix data in a memory and performs multiplication operation under the control of a controller 1104.

[0287] In some implementations, the operation circuit 1103 internally comprises a plurality of processing units (PEs). In some implementations, the operation circuit 1103 is a two-dimensional systolic array. The operation circuit 1103 can also be a one-dimensional systolic array or other electronic circuits capable of performing mathematical operations such as multiplication and addition. In some implementations, the operation circuit 1103 is a general-purpose matrix processor.

[0288] For example, it is assumed that there are an input matrix A, a weight matrix B and an output matrix C. The operation circuit takes corresponding data of the matrix B from the weight memory 1102 and buffers them on each PE in the operation circuit. The operation circuit takes the matrix A data from the input memory 1101 and performs matrix operation with the matrix B, and the partial result or final result of the obtained matrix is saved in an accumulator 1108.

[0289] The unified memory 1106 is used to store input data and output data. The weight data is transferred to the weight memory 1102 through a direct memory access controller (DMAC) 1105. The input data is also transferred to the unified memory 1106 through the DMAC.

[0290] BIU for Bus Interface Unit, which is used for the interaction between AXI bus and DMAC and instruction fetch buffer (IFB) 1109.

[0291] The bus interface unit 1110 (Bus Interface Unit, referred to as BIU) is used for the instruction fetch buffer 1109 to obtain instructions from the external memory, and is also used for the storage unit access controller 1105 to obtain the original data of the input matrix A or the weight matrix B from the external memory.

[0292] The DMAC is mainly used to carry the input data in the external memory DDR to the unified memory 1106, or carry the weight data to the weight memory 1102, or carry the input data to the input memory 1101.

[0293] The vector calculation unit 1107 includes a plurality of operation processing units, which further process the output of the operation circuit 1103 as needed, such as vector multiplication, vector addition, exponential operation, logarithmic operation, size comparison, etc. It is mainly used for non-convolution / full connection layer network calculation in neural network, such as batch normalization, pixel-level summation, upsampling of feature plane, etc.

[0294] In some implementations, the vector calculation unit 1107 can store the processed output vector to the unified memory 1106. For example, the vector calculation unit 1107 can apply a linear function; or, a nonlinear function to the output of the operation circuit 1103, such as linear interpolation on the feature plane extracted by the convolution layer, and again, for example, a vector of accumulated values, to generate an activation value. In some implementations, the vector calculation unit 1107 generates normalized values, pixel-level summation values, or both. In some implementations, the processed output vector can be used as an activation input to the operation circuit 1103, for example, for use in subsequent layers in the neural network.

[0295] The controller 1104 is connected to the instruction fetch buffer 1109, which is used to store instructions used by the controller 1104;

[0296] The unified memory 1106, the input memory 1101, the weight memory 1102, and the instruction fetch buffer 1109 are all on-chip memories. The external memory is private to the NPU hardware architecture.

[0297] The processor mentioned in any of the above can be a general central processing unit, a microprocessor, an ASIC, or one or more integrated circuits for controlling execution of the above program.

[0298] It should be noted that the above-described apparatus embodiments are merely illustrative, and the units described as separate components can or can not be physically separated, and the components shown as units can or can not be physical units, i.e., they can be located in one place or distributed on multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the embodiment. In addition, the connection relationship between the modules in the apparatus embodiments provided in the present application indicates that there is a communication connection between them, which can be implemented as one or more communication buses or signal lines.

[0299] Through the description of the above embodiments, those skilled in the art can clearly understand that the present application can be implemented by means of software and the necessary general hardware, and of course it can also be implemented by special hardware including special integrated circuits, special CPUs, special memories, special components, etc. Generally, functions completed by computer programs can be easily implemented by corresponding hardware, and the specific hardware structure for implementing the same function can also be various, such as analog circuits, digital circuits or special circuits. However, for the present application, software program implementation is a better embodiment. Based on this understanding, the technical solutions of the present application can be embodied in the form of a software product, which is stored in a readable storage medium, such as a computer's floppy disk, U disk, mobile hard disk, ROM, RAM, magnetic disk or optical disk, etc., including a plurality of instructions for making a computer device (which can be a personal computer, training device, or network device, etc.) execute the methods described in various embodiments of the present application.

[0300] In the above embodiments, all or part can be realized by software, hardware, firmware or any combination thereof. When realized by software, it can be realized in the form of a computer program product in whole or in part.

[0301] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present application are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions can be transmitted from one website, computer, training device or data center to another website, computer, training device or data center through wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be stored by the computer or a data storage device such as a training device, a data center, etc. integrated with one or more available media sets. The available media can be a magnetic medium (for example, a floppy disk, a hard disk, a magnetic tape), an optical medium (for example, a DVD), or a semiconductor medium (for example, a solid state disk (SSD)), etc.

Claims

1. A data processing method, characterized by, The method comprises: performing a first processing process by a first instance, the first processing process being a full inference process by a machine learning model; performing a second processing process by a second instance, the second processing process being an incremental inference process by the machine learning model; wherein the first instance and the second instance are different instances running on a same computing unit, and the first processing process and the second processing process are performed in parallel.

2. The method of claim 1, wherein, The method further comprises: determining an allocation strategy of allocating computing resources to the first instance according to a running performance of the computing unit; or adjusting the allocation strategy of allocating computing resources to the second instance according to the running performance of the computing unit.

3. The method according to claim 1 or 2, characterized in that, The running performance comprises a computing power load; The determining of the allocation strategy of allocating computing resources to the first instance according to the running performance of the computing unit comprises: when the computing power load is lower than a first threshold, increasing the computing power resources allocated to the first instance; or The adjusting of the allocation strategy of allocating computing resources to the second instance according to the running performance of the computing unit comprises: when the computing power load is higher than a second threshold, decreasing the computing power resources allocated to the second instance.

4. The method according to any one of claims 1 to 3, characterized in that, The running performance comprises a memory load; The determining of the allocation strategy of allocating computing resources to the first instance according to the running performance of the computing unit comprises: when the memory load is higher than a third threshold, decreasing the memory bandwidth resources allocated to the first instance; or The adjusting of the allocation strategy of allocating computing resources to the second instance according to the running performance of the computing unit comprises: when the memory load is lower than a third threshold, increasing the memory bandwidth resources allocated to the second instance.

5. The method according to any one of claims 1 to 4, characterized in that, The running performance comprises an execution latency; The determining of the allocation strategy of allocating computing resources to the first instance according to the running performance of the computing unit comprises: when the execution latency is higher than a fourth threshold, increasing the computing power resources allocated to the first instance; or The adjusting of the allocation strategy of allocating computing resources to the second instance according to the running performance of the computing unit comprises: when the execution latency is higher than a fourth threshold, increasing the memory bandwidth resources allocated to the first instance.

6. The method according to any one of claims 1 to 5, characterized in that, The method further comprises: determining the allocation strategy of allocating computing resources to the first instance according to a processing load when the first instance performs the first processing process; or adjusting the allocation strategy of allocating computing resources to the second instance according to a processing load when the second instance performs the second processing process.

7. The method according to any one of claims 1 to 5, characterized in that, The determining of the allocation strategy of allocating computing resources to the first instance according to the processing load when the first instance performs the first processing process comprises: when the processing load is greater than a fifth threshold, increasing the computing power resources allocated to the first instance; or The adjusting of the allocation strategy of allocating computing resources to the second instance according to the processing load when the second instance performs the second processing process comprises: when the processing load is greater than a fifth threshold, increasing the memory bandwidth resources allocated to the second instance.

8. The method according to any one of claims 1 to 7, characterized in that, The method further comprises: When a memory access bandwidth of the second processing process performed by the second instance is less than a preset minimum bandwidth, or an execution time delay is greater than a preset maximum time delay, the computing resource allocated to the second instance is not reduced.

9. The method according to any one of claims 1 to 8, characterized in that, The method further includes: When a bottleneck of memory access resource is encountered in the first processing process performed by the first instance, or an execution time delay is greater than a preset maximum time delay, the memory bandwidth resource allocated to the first instance is not reduced.

10. The method according to any one of claims 1 to 9, characterized in that, The method further includes: receiving a processing request; adding a full reasoning task in the processing request to a first queue; adding an incremental processing task in the processing request to a second queue; the first processing process includes: executing a to-be-processed task in the first queue; the second processing process includes: executing a to-be-processed task in the second queue.

11. The method of any one of claims 1-10, wherein the machine learning model is a language model, the first processing process includes loading parameters of the language model, obtaining a processing request, and executing the processing request by using the parameters of the language model to obtain KV data and newly generated first tokens, and the second processing process includes loading the parameters of the language model, obtaining KV data in a KV cache, and executing the KV data in the first tokens by using the parameters of the language model to obtain newly generated second tokens.

12. A data processing apparatus, characterized by The apparatus includes: a full reasoning module configured to perform a first processing process by a first instance, the first processing process being a full reasoning process performed by a machine learning model; an incremental reasoning module configured to perform a second processing process by a second instance, the second processing process being an incremental reasoning process performed by the machine learning model; wherein the first instance and the second instance are different instances running on a same computing unit, and the first processing process and the second processing process are performed in parallel.

13. The apparatus of claim 12, wherein, The apparatus further includes: a control module configured to determine an allocation strategy of computing resources allocated to the first instance according to a running performance of the computing unit; or adjust an allocation strategy of computing resources allocated to the second instance according to the running performance of the computing unit.

14. The apparatus of claim 12 or 13, wherein, The running performance includes a computing power load; The control module is specifically configured to: when the computing power load is lower than a first threshold, increase the computing resource allocated to the first instance; or when the computing power load is higher than a second threshold, decrease the computing resource allocated to the second instance.

15. The apparatus of any one of claims 12 to 14, wherein, The running performance includes a memory load; The control module is specifically configured to: when the memory load is higher than a third threshold, decrease the memory bandwidth resource allocated to the first instance; or when the memory load is lower than the third threshold, increase the memory bandwidth resource allocated to the second instance.

16. The apparatus of any one of claims 12 to 15, wherein, The running performance includes an execution time delay; The control module is specifically configured to: when the execution time delay is higher than a fourth threshold, increase the computing resource allocated to the first instance; or when the execution time delay is higher than the fourth threshold, increase the memory bandwidth resource allocated to the first instance.

17. The apparatus of any one of claims 12 to 16, wherein, The apparatus further includes: determine an allocation strategy of allocating computing resources to the first instance according to a processing load when the first instance performs the first processing process; or adjust the allocation strategy of allocating computing resources to the second instance according to a processing load when the second instance performs the second processing process.

18. The apparatus of any one of claims 12 to 17, wherein, The control module is specifically configured to: increase the computing resource allocated to the first instance when the processing load is greater than a fifth threshold; or increase the memory bandwidth resource allocated to the second instance when the processing load is greater than a fifth threshold.

19. The apparatus of any of claims 12 to 18, wherein, The device further includes: a control module configured to not reduce the computing resource allocated to the second instance when the memory bandwidth for performing the second processing process by the second instance is less than a preset minimum bandwidth or an execution delay is greater than a preset maximum delay.

20. The apparatus of any of claims 12 to 19, wherein, The device further includes: a control module configured to not reduce the memory bandwidth resource allocated to the first instance when a memory resource encounters a bottleneck or an execution delay is greater than a preset maximum delay when the first instance performs the first processing process.

21. The apparatus of any one of claims 12 to 20, wherein, The device further includes: a control module configured to receive a processing request; add all the inference tasks in the processing request to a first queue; add incremental processing tasks in the processing request to a second queue; The first processing process includes: executing the to-be-processed tasks in the first queue; The second processing process includes: executing the to-be-processed tasks in the second queue.

22. The device of any one of claims 12-21, wherein the machine learning model is a language model, the first processing process includes loading parameters of the language model, obtaining a processing request, executing the processing request by using the parameters of the language model, obtaining KV data and newly generated first tokens, and the second processing process includes loading the parameters of the language model, obtaining KV data in a KV cache, and obtaining KV data of the first tokens and newly generated second tokens by using the parameters of the language model.

23. A computer storage medium, comprising, The computer storage medium stores one or more instructions, which, when executed by one or more computers or processors, cause the one or more computers or the processors to perform the method of any one of claims 1-11.

24. A computer program product, characterised in that, The computer storage medium stores one or more instructions, which, when executed by one or more computers or processors, cause the one or more computers or the processors to perform the method of any one of claims 1-11.

25. A system, comprising: The computer storage medium stores one or more instructions, which, when executed by one or more computers or processors, cause the one or more computers or the processors to perform the method of any one of claims 1-11. The computer storage medium stores one or more instructions, which, when executed by one or more computers or processors, cause the one or more computers or the processors to perform the method of any one of claims 1-11. The computer storage medium stores one or more instructions, which, when executed by one or more computers or processors, cause the one or more computers or the processors to perform the method of any one of claims 1-11.

26. A chip comprising a processor, wherein: The computer storage medium stores one or more instructions, which, when executed by one or more computers or processors, cause the one or more computers or the processors to perform the method of any one of claims 1-11.

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