Transistor, storage array and electronic device

Abstract

The embodiments of the present application relate to the field of electronic devices. Provided are a transistor, a storage array and an electronic device, which can improve the storage security and the storage performance. The transistor comprises a substrate and a gate structure. A trench, a source region and a drain region are disposed on the substrate. The gate structure is disposed in the trench. The gate structure comprises a dielectric layer, a first filling region, a second filling region, and a third filling region. The dielectric layer covers the inner surface of the trench. A filling material of the first filling region is disposed in contact with the bottom of the trench, and the second filling region is located above the first filling region. The third filling region is located in the second filling region. The third filling region is not in contact with the dielectric layer. A work function of the filling material in the first filling region is greater than a work function of a filling material in the second filling region. A work function of a filling material in the third filling region is greater than the work function of the filling material in the second filling region.

Description

Transistor, memory array, and electronic device TECHNICAL FIELD

[0001] The present application relates to the field of electronic devices, and in particular to a transistor, a memory array, and an electronic device. BACKGROUND

[0002] As the size of the transistor (TR) in the basic memory cell of the dynamic random access memory (DRAM) becomes smaller and smaller, the electric field of the gate edge region of the transistor becomes larger and larger, which causes the phenomenon of gate-induced drain leakage (GIDL) to become more and more serious. GIDL can cause storage data errors and affect the safety of storage.

[0003] In order to improve the problem caused by GIDL, the industry introduces a dual work-function buried word line (WF BWL) structure in the transistor. The structure includes a low work function layer with a lower work function and a high work function layer with a higher work function. By increasing the thickness of the low work function layer and reducing the thickness of the high work function layer, the difficulty of forming a tunneling current in the gate-drain overlap region is improved, thereby improving the GIDL leakage.

[0004] However, increasing the thickness of the low work function layer can significantly increase the resistivity of the transistor, causing the write recovery time (tWR) to increase, thereby affecting the storage performance. SUMMARY

[0005] Embodiments of the present application provide a transistor, a memory array, and an electronic device, which can not only improve GIDL leakage, but also improve the increase in resistivity caused by the use of low work function materials in the gate structure, the timing problem caused by the increase in tWR, thereby improving the safety of storage and storage performance.

[0006] In a first aspect, a transistor is provided, including: a substrate, a gate structure. The substrate is provided with a trench, a source region and a drain region above the substrate. The gate structure is arranged in the trench. The gate structure includes a dielectric layer, a first filling region, a second filling region and a third filling region. The dielectric layer covers the inner surface of the trench. The filling material of the first filling region is arranged in contact with the bottom of the trench, the second filling region is located above the first filling region. The third filling region is located in the second filling region. The third filling region does not contact the dielectric layer. The work function of the filling material in the first filling region is greater than the work function of the filling material in the second filling region. The work function of the filling material in the third filling region is greater than the work function of the filling material in the second filling region.

[0007] Based on the scheme, a channel for charge flow can be formed from the source region to the drain region along the outside of the trench. Since the second filling region is close to the channel, and the filling material of the second filling region has a lower work function, the electric field intensity of the area of the second filling region close to the channel is lower, which is conducive to increasing the difficulty of forming a tunneling current in the gate-drain overlap area, thereby improving the GIDL leakage and improving the storage safety. Moreover, since the filling material in the third filling region has a higher work function, the resistivity is lower, so the overall resistivity of the transistor is also lower. In this way, the problem of increased resistivity caused by the use of low work function materials in the gate structure can be improved, thereby improving the timing problem caused by the increase of tWR and improving the storage performance.

[0008] In some possible implementations, the source region and the drain region are located above the first filling region and on both sides of the trench. Based on this scheme, the distance between the high work function material of the first filling region and the drain region can be increased, thereby reducing the electric field intensity between the first filling region and the drain region, increasing the difficulty of forming a tunneling current in the gate-drain overlap area, and further improving the GIDL leakage and improving the storage safety.

[0009] In some possible implementations, the filling material of the first filling region includes titanium nitride and / or tungsten. The filling material of the third filling region includes titanium nitride and / or tungsten. Based on this scheme, the filling materials of the first filling region and the third filling region both have a higher work function, which is conducive to reducing the overall resistivity of the transistor and ensuring the storage performance of the transistor.

[0010] In some possible implementations, the filling material of the second filling region includes polysilicon. Based on this scheme, the filling material of the second filling region has a lower work function, which is conducive to reducing the electric field at the edge of the gate, thereby increasing the difficulty of forming a tunneling current in the gate-drain overlap area and improving the GIDL leakage.

[0011] In some possible implementations, the second filling region surrounds the third filling region in a "concave" shape. Based on this scheme, the third filling region is easy to etch, the process difficulty is low, and the implementation cost is low.

[0012] In some possible implementations, the surface of the third filling region that is not in contact with the second filling region is in a recessed shape. Based on this scheme, the filling material of the third filling region can be reduced, thereby reducing the overall resistivity of the transistor, improving the timing problem caused by the increase of tWR, and improving the storage performance.

[0013] In some possible implementations, the second filling region surrounds the third filling region. Based on this scheme, the low work function of the second filling region completely wraps the high work function material of the third filling region, which is conducive to further reducing the electric field at the edge of the gate and improving the GIDL leakage.

[0014] In some possible implementation manners, the thickness of the second filling region is between 0.5 nm and 15 nm. Based on this scheme, the gate edge region can be ensured to have a low electric field, so that the difficulty of forming a tunneling current in the gate leakage overlap region is increased, and the GIDL leakage is improved.

[0015] In some possible implementation manners, the volume ratio of the third filling region to the second filling region is between 1 / 9 and 9. Based on this scheme, the resistivity of the transistor as a whole can be reduced, so that the problem of increased resistivity caused by the low work function material of the gate structure is improved, and the timing problem caused by the increased tWR is improved.

[0016] In some possible implementation manners, the third filling region is in a "concave" shape. Based on this scheme, the filling material of the third filling region can be reduced, so that the resistivity of the transistor as a whole is reduced, the timing problem caused by the increased tWR is improved, and the storage performance is improved.

[0017] In a second aspect, a storage unit is provided, including a capacitor and the transistor of any one of the first aspect. One end of the capacitor is connected to the first electrode of the transistor. The first electrode is the source electrode or the drain electrode. The other end of the capacitor is grounded.

[0018] In a third aspect, a storage array is provided, including a word line, a bit line, a source line, and a plurality of storage units. The storage unit includes a capacitor and the transistor of any one of the first aspect. The plurality of storage units are arranged in an array. The word line is connected to the gate structure of the transistor. The bit line is connected to the first end of the transistor. The source line is connected to the second end of the transistor through the capacitor. The first end and the second end are the source electrode and the drain electrode of the transistor, respectively.

[0019] In a fourth aspect, a memory is provided, including a controller and the storage array of the third aspect. The controller is connected to the storage array. The controller is configured to access the storage array.

[0020] In a fifth aspect, an electronic device is provided, including a circuit board processor and the memory of the fourth aspect. The memory is integrated on the circuit board.

[0021] In a sixth aspect, a transistor manufacturing method is provided, including: forming a trench, a source region, and a drain region on a substrate; and forming a gate structure in the trench. The gate structure includes a dielectric layer, a first filling region, a second filling region, and a third filling region. The dielectric layer covers the inner surface of the trench. The filling material of the first filling region is arranged to contact the bottom of the trench. The second filling region is arranged on the first filling region. The third filling region is arranged in the second filling region. The third filling region does not contact the dielectric layer. The work function of the filling material in the first filling region is greater than the work function of the filling material in the second filling region. The work function of the filling material in the third filling region is greater than the work function of the filling material in the second filling region.

[0022] It should be understood that the second aspect to the sixth aspect of the present application are consistent with or corresponding to the technical solution of the first aspect of the present application, and the beneficial effects obtained by each aspect and the corresponding feasible implementation manners are similar, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0023] FIG. 1 is a structural schematic diagram of a storage unit;

[0024] FIG. 2 is a structural schematic diagram of an electronic device provided by an embodiment of the present application;

[0025] FIG. 3 is a cross-sectional schematic diagram of a transistor provided by an embodiment of the present application;

[0026] FIG. 4 is a cross-sectional schematic diagram of another transistor provided by an embodiment of the present application;

[0027] FIG. 5 is a cross-sectional schematic diagram of still another transistor provided by an embodiment of the present application;

[0028] FIG. 6 is a cross-sectional schematic diagram of still another transistor provided by an embodiment of the present application;

[0029] FIG. 7 is a cross-sectional schematic diagram of a double work function buried word line structure transistor;

[0030] FIG. 8 is a simulation schematic diagram of an electric field intensity of a transistor provided by an embodiment of the present application;

[0031] FIG. 9 is a structural schematic diagram of a storage array provided by an embodiment of the present application;

[0032] FIG. 10 is a structural schematic diagram of a memory provided by an embodiment of the present application;

[0033] FIG. 11 is a structural schematic diagram of still another electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0034] The transistor, storage array and electronic device of the present application are further described in detail below in combination with the accompanying drawings and specific embodiments. The present application can be implemented in various forms, and should not be interpreted as being limited to the embodiments listed herein. More specifically, these embodiments are provided so that the present disclosure will be fully and completely conveyed to those skilled in the art, and will fully convey the scope of the present application to those skilled in the art.

[0035] It is to be understood that the drawings are schematic and not drawn to scale for the purpose of convenience and clarity in illustrating the embodiments of the present application. It should be understood that in the following description, when a layer, region, pattern or structure is referred to as being "on" or "under" another layer, region, pattern or structure, it can be directly on or under the other layer, region, pattern or structure, and / or intervening layers can also be present. Similarly, when a layer is referred to as being "on" or "under" another layer, it can be directly on or under the other layer, and / or one or more intervening layers can also be present. In addition, references made to "on" and "under" in relation to layers can be made on the basis of the drawings.

[0036] In addition, it should be noted that in the present specification, "connection / coupling" not only means that one component is directly coupled with another component, but also means that one component is indirectly coupled with another component via an intermediate component. In addition, the singular form can include the plural form and vice versa, as long as it is not specifically mentioned.

[0037] For the convenience of understanding, the application scenarios of the embodiments of the present application are introduced as follows.

[0038] DRAM is a common memory, which is widely used in electronic devices such as mobile phones, computers, smart watches and vehicle terminals. From the perspective of principle, DRAM can be understood as a storage technology based on a capacitor, and data writing and reading are realized through charge accumulation and release.

[0039] Exemplarily, DRAM can be composed of a plurality of storage cells. The structure of the storage cell can be as shown in FIG. 1, which includes a transistor 101 and a capacitor 102. The transistor 101 includes a gate, a source and a drain. The source or the drain is grounded through the capacitor 102 (for example, the drain is grounded through the capacitor 102 in FIG. 1).

[0040] In the embodiments of the present application, the transistor can be a metal oxide semiconductor (MOS) transistor, such as an NMOS transistor, a PMOS transistor, a CMOS transistor and the like. In addition, the transistor can also be a junction field effect transistor (JFET), which is not limited in the embodiments of the present application.

[0041] In the memory cell, the transistor 101 can act as an electronic switch. For example, the conduction between the source and the drain of the transistor 101 can be controlled by the gate of the transistor 101. The capacitor 102 can store electric charges, and the memory 102 can record information by whether there are electric charges. For example, when there are electric charges in the capacitor 102 of the memory cell, the bit information stored in the memory cell can be recorded as "1". When there are no electric charges in the capacitor 102 of the memory cell, the bit information stored in the memory cell can be recorded as "0".

[0042] When reading the bit information stored in the memory cell, the source and the drain of the transistor 101 can be turned on. If it is detected that the transistor 101 is discharged after being turned on, it can be confirmed that the bit information stored in the memory cell is "1". If it is detected that the transistor 101 is not discharged after being turned on, it can be confirmed that the bit information stored in the memory cell is "0".

[0043] When writing the bit information into the memory cell, the source and the drain of the transistor 101 can be turned on, and a high voltage can be applied to the source of the transistor 101. In this way, the current can pass through the transistor 101 to charge the capacitor 102, so that the electric charges are stored in the capacitor 102, thereby writing the bit information "1".

[0044] When writing the bit information into the memory cell, the source of the transistor 101 can also be grounded. In this way, the electric charges in the capacitor 102 can be discharged, thereby writing the bit information "0".

[0045] As the size of the transistor is reduced, the GIDL phenomenon can occur. The GIDL refers to the phenomenon that when a voltage is applied to the drain of the transistor, the PN junction of the drain region is reverse biased, and the excess hole-electron pairs generated by the electric heat energy are driven by the electric field before they are recombined, thereby causing a leakage current. It should be understood that the leakage current of the transistor in the memory cell can cause the bit information stored in the memory cell to change, thereby affecting the accuracy and security of the memory cell.

[0046] The double work function embedded word line structure can effectively reduce the GIDL leakage. The work function, also known as the work function, is the minimum energy required to move an electron from the inside of an object to the surface. That is, the greater the work function of a material, the greater the energy required to move an electron from the inside of the material to the surface, the stronger the binding of the electron device in the material, and the more difficult the electron escapes from the surface of the material. The double work function refers to using a high work function layer and a low work function layer to construct the gate of the transistor. The embedded word line structure refers to the word line formed in the substrate and intersecting with the active region in the substrate, so that part of the word line can be used as the gate of the transistor of the memory cell, and the source-drain region of the transistor is formed in the substrate on both sides of the gate.

[0047] In the embodiments of the present application, the high work function material can refer to a material with a work function higher than the mid-gap work function of silicon. The low work function material can refer to a material with a work function lower than the mid-gap work function of silicon. The mid-gap work function of silicon can be considered as 4.5 eV.

[0048] Exemplarily, in the embodiments of the present application, the high work function material can be a metal, such as tantalum, titanium, molybdenum, tungsten, platinum, aluminum, hafnium, ruthenium, etc. The high work function material can also be a metal silicide, such as titanium silicide, cobalt silicide, nickel silicide, tantalum silicide, etc. The high work function material can also be a metal nitride, such as titanium nitride, tantalum nitride, etc. The low work function material can be polysilicon, or polysilicon doped with a dopant such as phosphorus, arsenic, boron, indium, etc. The present application does not make a specific limitation in this regard.

[0049] By further increasing the thickness of the low work function layer and reducing the thickness of the high work function layer in the dual work function buried word line structure, the potential barrier of the gate-drain overlap region of the transistor can be improved. In this way, the difficulty of forming a tunneling current in the gate-drain overlap region of the transistor is increased, and the GIDL leakage can be improved.

[0050] However, the resistivity of the material used in the low work function layer is greater than that of the material used in the high work function layer, and increasing the thickness of the low work function layer will increase the resistivity of the transistor, resulting in an increase in tWR. The tWR is used to indicate the number of clock cycles that must be waited for before completing an effective write operation and pre-charging in an activated memory bank. This period of clock cycles is used to ensure that the data in the buffer can be written into the memory cell before pre-charging occurs. Therefore, it should be understood that the increase of tWR will affect the storage performance.

[0051] To solve the above problems, the embodiments of the present application provide a transistor, a storage array, a memory and an electronic device, which can ensure that a lower GIDL leakage is achieved while reducing the impact on the resistivity of the transistor, thereby improving the security of the storage without significantly affecting the storage performance.

[0052] It should be noted that the transistor, the storage array and the memory provided by the embodiments of the present application can be applied in various electronic devices, such as the memory of various electronic devices. The electronic device can include a personal computer, a mobile phone, a notebook computer, a server, a wearable device (such as a smart watch), a vehicle-mounted device, a base station, a handheld device, a tablet computer (pad), a mobile internet device (MID), a virtual reality (VR) terminal, an augmented reality (AR) terminal, a wireless terminal in industrial control, etc.

[0053] Exemplarily, refer to FIG. 2, a structural schematic diagram of an electronic device provided by the embodiment of the present application is shown. As shown in FIG. 2, the electronic device can include a circuit board 201 and a memory 202. The memory 202 can include the transistor and the memory array provided by the embodiment of the present application. The memory 202 is integrated in the circuit board 201.

[0054] The circuit board 201 can be a printed circuit board (PCB). The circuit board 201 can further integrate a central processing unit (CPU), a power management chip and other devices (not shown in FIG. 2), which are not limited herein.

[0055] The memory 202 can be one memory or can include a plurality of memories, which are used to store program instructions. In an embodiment, the memory 202 stores computer readable instructions. The processor 201 executes the computer readable instructions to perform corresponding operations.

[0056] The transistor, the memory array and the electronic device provided by the embodiment of the present application are introduced as follows.

[0057] Refer to FIG. 3, a cross-sectional schematic diagram of a transistor provided by the embodiment of the present application is shown. As shown in FIG. 3, the transistor includes a substrate 301 and a gate structure 302. The substrate 301 is provided with a trench 311, a source region 321 and a drain region 331. The gate structure 302 is disposed in the trench 311. The bottom of the trench 311 can refer to the bottom of the trench 311 or the region close to the bottom of the trench 311. The gate structure 302 includes a dielectric layer 312, a first filling region 322, a second filling region 332 and a third filling region 342. The dielectric layer 312 covers the inner surface of the trench 311. The filling material of the first filling region 322 is disposed in contact with the bottom of the trench 311. The second filling region 332 is located above the first filling region 322. The third filling region 342 is located in the second filling region 332. The third filling region 342 is not in contact with the dielectric layer 312. The work function of the filling material in the first filling region 322 is greater than the work function of the filling material in the second filling region 332. The work function of the filling material in the third filling region 342 is greater than the work function of the filling material in the second filling region 332.

[0058] It should be noted that the embodiments of the present application do not limit the size and range of the source region and the drain region of the transistor as long as the source region and the drain region exist. For example, the source region 321 and the drain region 331 in FIG. 3 can be located above the first filling region 322 on both sides of the trench 311. In this way, the distance between the high work function material of the first filling region and the drain region can be increased, which is beneficial to reduce the electric field intensity between the first filling region and the drain region, thereby increasing the difficulty of forming a tunneling current in the gate-drain overlap region, improving the GIDL leakage, and improving the security of storage. It should be understood that the above is only an exemplary description, and the present application is not limited thereto.

[0059] The source region 321 and the drain region 331 can be formed by doping a conductive impurity (such as phosphorus or boron) into the substrate. That is, the relationship among the substrate 301, the trench 311, the source region 321, and the drain region 331 in the transistor shown in FIG. 3 can also be described as follows: the substrate 301 is provided with the trench 311. The source region 321 and the drain region 331 are formed by doping a conductive impurity into the substrate on both sides of the trench 311. The material of the substrate 301 can include one or more of a semiconductor material, such as silicon, germanium, silicon germanium, silicon carbide, etc., can also include a silicon-on-insulator (SOI) or a germanium-on-insulator (GOI), or can also include other materials, such as one or more of a group III-V compound, such as gallium arsenide. The substrate 301 can also be doped with other substances to change the electrical parameters according to the requirements, and the embodiments of the present application do not limit the same.

[0060] The gate structure 302 can also be referred to as a gate, a gate region, or a gate electrode. The source region 321 can also be referred to as a source, a source structure, or a source electrode. The drain region 331 can also be referred to as a drain, a drain structure, or a drain electrode. The embodiments of the present application do not limit the same.

[0061] The cross-sectional structure of the trench 311 can be "U" shaped as shown in FIG. 3, or "concave" shaped, which is not limited herein. In the embodiments of the present application, the trench 311 can be formed by etching the substrate 301 once or multiple times. Exemplarily, a pad oxide layer and a hard mask layer can be deposited on the surface of the substrate 301 first. Then a photoresist layer is spin-coated on the upper surface of the hard mask layer. Then the photoresist layer in the trench 311 area is opened by exposure and development process with a mask plate. Then the hard mask layer and the pad oxide layer in the trench 311 area are etched to form an opening by etching downward with the photoresist layer with an opening pattern as a mask. Then the substrate 301 is continuously etched with the hard mask layer and the pad oxide layer with an opening pattern as a mask, so as to form the trench 311 in the substrate 301. The material of the pad oxide layer is, for example, silicon oxide, and the material of the hard mask layer is, for example, silicon nitride. The formation method of the hard mask layer and the pad oxide layer is, for example, chemical vapor deposition (CVD). It should be understood that this is only an exemplary description, and the present application is not limited thereto. For example, for the trench 311, the formation method of the hard mask layer and the pad oxide layer can also be implemented according to the disclosed technology, which is not limited herein.

[0062] The gate structure 302 is formed in the trench 311, and the gate structure 302 includes a dielectric layer 312, a first filling region 322, a second filling region 332, and a third filling region 342. In other words, the dielectric layer 312, the first filling region 322, the second filling region 332, and the third filling region 342 are formed in the trench 311. In the embodiments of the present application, in the trench 311 refers to the internal region of the cavity surrounded by the inner surface of the trench 311, which will not be described in detail hereinafter.

[0063] The dielectric layer 312 can be conformally coated on the inner surface of the trench 311. The conformal coating refers to that the dielectric layer 312 is attached to the inner surface of the trench 311. The dielectric layer 312 can be a silicon dioxide layer with a thickness of to The formation method of the dielectric layer 312 can be, but is not limited to, any one of the following: formed by an oxidation process of wet or dry thermal oxidation, wherein the formation environment includes oxide, water vapor, nitric oxide, or a combination thereof; formed by an In-situ steam generation (ISSG) process, wherein the formation environment includes oxygen, water vapor, nitric oxide, or a combination thereof; formed by a chemical vapor deposition technique using tetraethyl orthosilicate (TEOS) and oxygen as precursors.

[0064] The first filling region 322 and the second filling region 332 can be located at different regions of the trench 311 respectively. The second filling region 332 is located above the first filling region 322. The first filling region 322 can be located close to a bottom region of the trench 311. The second filling region 332 can be located close to an opening region of the trench 311. Exemplarily, as shown in FIG. 3, the first filling region 322 can be located at the bottom region of the trench 311, and the second filling region 332 can be located at the opening region of the trench 311.

[0065] The third filling region 342 is located within the second filling region 332, and the third filling region 342 does not contact the dielectric layer 312. In some possible implementation manners, the second filling region 332 can surround the third filling region 342. For example, the second filling region 332 can surround the third filling region 342 in a "concave" shape as shown in FIG. 3. For another example, the second filling region 432 can also surround the third filling region 442 in a "mouth" shape as shown in FIG. 4.

[0066] In some possible implementation manners, the thickness of the second filling region 332 can be between 0.5 nm and 15 nm. In another possible implementation manner, the volume ratio of the third filling region 342 to the second filling region 332 can be between 1 / 9 and 9. In another possible implementation manner, the thickness of the second filling region 332 is between 0.5 nm and 15 nm, and the volume ratio of the third filling region 342 to the second filling region 332 is between 1 / 9 and 9.

[0067] The work function of the filling material in the first filling region 322 is greater than the work function of the filling material in the second filling region 332. The work function of the filling material in the third filling region 342 is greater than the work function of the filling material in the second filling region 332. In other words, the filling material of the first filling region 322 and the filling material of the third filling region 342 can both be high work function materials. The filling material of the second filling region 332 can be a low work function material.

[0068] In addition, in the embodiments of the present application, the third filling region can have various shapes. For example, as shown in FIG. 5, the second filling region 532 can surround the third filling region 542 in a "concave" shape. The surface of the third filling region 542 that is not in contact with the second filling region 332 is concave. For another example, as shown in FIG. 6, the third filling region 642 can also be in a "concave" shape. It should be understood that the above is only an exemplary description of the shape of the third filling region, and the third filling region can also have other shapes, such as an inverted "concave" shape, and the like, which are not limited herein.

[0069] Based on the above description, it should be understood that, in the transistor provided by the embodiments of the present application, the second filling region is close to the channel, and the filling material of the second filling region has a lower work function, so that the electric field of the area close to the channel of the second filling region is lower, which is beneficial to increase the difficulty of forming a tunneling current in the gate-drain overlapping area, thereby improving the GIDL leakage. In addition, the filling material in the third filling region has a higher work function, so that the resistivity is lower, and the overall resistivity of the transistor is also lower. In this way, the problem of increased resistivity caused by the use of a low work function material in the gate structure can be improved, and the timing problem caused by the increase of tWR can be improved.

[0070] In addition, the transistor structure provided by the embodiments of the present application has the advantage of lower process difficulty.

[0071] In some possible implementation manners, the transistor provided by the embodiments of the present application can be manufactured through the following steps. First, a trench, a source region and a drain region can be formed above a substrate. For example, the trench can be formed above the substrate first, and then the source region and the drain region can be formed on both sides of the trench above the substrate. Then, a gate structure can be formed in the trench. The gate structure includes a dielectric layer, a first filling region, a second filling region and a third filling region. The dielectric layer covers the inner surface of the trench. The filling material of the first filling region is arranged in contact with the bottom of the trench, and the second filling region is located above the first filling region. The third filling region is located in the second filling region. The third filling region does not contact the dielectric layer. The work function of the filling material in the first filling region is greater than that of the filling material in the second filling region. The work function of the filling material in the third filling region is greater than that of the filling material in the second filling region.

[0072] It should be noted that the method of forming a trench on a substrate and forming a source region and a drain region on both sides of the trench can refer to the description in the foregoing embodiments, which will not be repeated here.

[0073] In other possible implementation manners, the transistor in the embodiments of the present application can be further etched based on a transistor with a double work function embedded word line structure (or POR structure).

[0074] Please refer to FIG. 7 for a cross-sectional schematic view of a transistor with a double work function embedded word line structure. As shown in FIG. 7, the transistor includes a substrate 701 and a gate 702. The substrate 701 forms a trench therein. The source region 721 and the drain region 731 are respectively formed in the substrate on both sides of the trench. The gate 702 includes a dielectric layer 712, a high work function layer 722 and a low work function layer 732. The dielectric layer 712 conformally covers the inner wall of the trench. The high work function layer 722 is close to the bottom of the trench, and the low work function layer 732 is close to the opening of the trench.

[0075] Exemplarily, the third filling region can be etched in the low work function layer 732 based on the transistor shown in FIG. 7, and the third filling region can be filled with a high work function material. In this way, the transistor shown in FIG. 3 can be obtained.

[0076] Further, after the transistor shown in FIG. 3 is obtained, the filling material of the third filling region which is not in contact with the dielectric layer can be etched to form a recess. In this way, the transistor shown in FIG. 5 can be obtained. It should be understood that the filling material of the third filling region in the transistor shown in FIG. 5 is less than that in the transistor shown in FIG. 3, so the resistivity of the transistor shown in FIG. 5 is less than that of the transistor shown in FIG. 3, and the tWR of the transistor shown in FIG. 5 is less than that of the transistor shown in FIG. 3. That is, the transistor shown in FIG. 5 is beneficial to further improve the storage performance of the transistor.

[0077] For another example, after the transistor shown in FIG. 3 is obtained, the third filling region can be etched to form a trench, and the trench can be filled with a low work function material. In this way, the transistor shown in FIG. 6 can be obtained.

[0078] The structure of the transistor provided by the embodiment of the present application is introduced above. The effect of reducing GIDL leakage of the transistor provided by the embodiment of the present application is verified through a simulation comparison experiment between the double work function embedded word line structure transistor and the transistor provided by the embodiment of the present application.

[0079] Please refer to FIG. 8, which is a simulation diagram of the electric field intensity of a transistor provided by the embodiment of the present application. The sizes of the two transistors are the same, the connected word line voltages are all-0.5V, and the bit line voltages are all 1.5V. The work function of the high work function material can be 4.6eV, and the work function of the low work function material can be 4.0eV. In addition, the gray scale in FIG. 8 represents the electric field intensity. The greater the gray scale is, the greater the electric field intensity is.

[0080] As can be seen from FIG. 8, the gray scale of the gate edge region in the transistor provided by the embodiment of the present application is less than that of the gate edge region in the double work function embedded word line structure transistor, that is, the field intensity of the gate edge region in the transistor provided by the embodiment of the present application is less than that of the gate edge region in the double work function embedded word line structure transistor. Therefore, in the transistor provided by the embodiment of the present application, it is more difficult for the gate leakage overlap region to form a tunneling current, and thus the GIDL leakage effect is lower.

[0081] The transistor provided by the embodiments of the present application can be applied to a memory cell. In other words, the embodiments of the present application also provide a memory cell, which comprises the transistor according to any one of the preceding embodiments. For example, the transistor 101 in the memory cell shown in FIG. 1 is replaced by the transistor provided by the embodiments of the present application, and a memory cell provided by the embodiments of the present application is obtained. The source and the drain can be interchanged, and thus no further description is given herein.

[0082] Referring to FIG. 9, the embodiments of the present application also provide a memory array. FIG. 9 is a structural schematic diagram of the memory array. As shown in FIG. 9, the memory array comprises a plurality of word lines 901, a plurality of bit lines 902, a plurality of source lines 903, and a plurality of memory cells 904. The gate structure of the transistor in each memory cell 904 is connected to the word line 901. The first end of the transistor in each memory cell 903 is connected to the bit line 902, and the second end of the transistor in each memory cell 903 is connected to the source line 903. The first end can be the source of the transistor in the memory cell 903, and the second end can be the drain of the transistor in the memory cell 903. Alternatively, the first end can be the drain of the transistor in the memory cell 903, and the second end can be the source of the transistor in the memory cell 903.

[0083] Referring to FIG. 10, the embodiment of the present application further provides a memory 1000, and FIG. 10 is a structural schematic diagram of the memory 1000. As shown in FIG. 10, the memory 300 can include one or more circuit structures of a memory array 1001, a decoder 1002, a driver 1003, a timing controller 1004, a buffer 1005 or an input / output driver 1006. In an implementation, the memory array 1001 includes a plurality of array-arranged memory cells 1011, each of which can be used to store 1 bit or multi-bit data. In some possible implementations, the structure of the memory array 1001 can be as shown in FIG. 9. In other possible implementations, the memory array 1001 can further include a word line (WL), a bit line (BL), a source line (SL) and a pre-charge line (CL). Each memory cell 1011 is electrically connected to a corresponding WL, BL, SL and CL. Different memory cells 1011 can be electrically connected through the WL, BL, SL or CL. One or more of the above WL, BL, SL and CL are used to select the memory cell 1011 to be read or written in the memory array by receiving a control level output by a control circuit, so as to change the polarization direction of a capacitor in the memory cell 1011, thereby realizing the read or write operation of data. For convenience, the above WL, BL, SL and CL are collectively referred to as signal lines in the embodiment of the present application. The decoder 1002 is used to realize the decoding of the address of the memory cell 1011. The decoder 1002 is used to decode the received address, so as to determine the memory cell 1011 to be accessed. The driver 1003 is used to control the level of the signal line according to the decoding result generated by the decoder 1002, so as to realize the access to the specified memory cell 1011. The buffer 1005 is used to buffer the read data, for example, a FIFO (first-in first-out) can be used for buffering. The timing controller 1003 is used to control the timing of the buffer 1005, and control the driver 1003 to drive the signal line in the memory array 1001. The input / output driver 1006 is used to drive the transmission signal, for example, to drive the received data signal and drive the data signal to be sent, so that the data signal can be transmitted at a long distance. The above memory array 1001, decoder 1002, driver 1003, timing controller 1004, buffer 1005 and input / output driver 1006 can be integrated in one chip, or can be integrated in multiple chips respectively.

[0084] Referring to FIG. 11, an electronic device is further provided in the embodiments of the present application. As shown in FIG. 11, the electronic device 1100 can be a terminal device, such as a mobile phone, a tablet computer, a smart bracelet, or a personal computer (PC), a server, a workstation, etc. The electronic device 1100 includes a bus 1101 and a system on chip (SoC) 1102 connected to the bus 1101. The SoC 1102 can be used to process data, such as processing data of an application program, processing image data, and buffering temporary data. In an implementation, the SoC 1102 can include an application processor (AP) 1112 for processing an application program, a graphics processing unit (GPU) 1122 for processing image data, and a first RAM 1132 for buffering high-speed data. The first RAM 1132 can be a static random access memory (SRAM) or an embedded flash (eflash), etc. The above-mentioned AP 1112, GPU 1122 and first RAM 1132 can be integrated in one die, or can be respectively arranged in multiple dies. The electronic device 1100 can further include a second RAM 1103 connected to the SoC 1102 through the bus 1101. The second RAM 1103 can be a dynamic random access memory (DRAM). The second RAM 1103 can be used to save volatile data, such as temporary data generated by the SoC 1102. The storage capacity of the second RAM 1103 is usually larger than that of the first RAM 1132, but the reading speed is usually slower than that of the first RAM 1132. The second RAM 1103 and the first RAM 1132 can have the structure shown in FIG. 10, which will not be described here. In addition, the electronic device 1100 can further include a communication chip 1104 and a power management chip 1105 connected to the SoC 1102 through the bus 1101. The communication chip 1104 can be used for processing of a protocol stack, or for amplifying, filtering, etc. of an analog radio frequency signal, or for simultaneously implementing the above functions. The power management chip 1105 can be used to power other chips. In an implementation, the SoC 1102 and the second RAM 1103 can be packaged in one packaging structure, such as using 2.5D (dimension) or 3D packaging, etc., to obtain a faster data transmission rate between chips. It should be understood that the storage array, the memory and the electronic device provided in the embodiments of the present application all include the transistors in any of the foregoing embodiments, and thus have similar beneficial effects, which will not be described here.

[0085] The terms "first", "second", "third", "fourth", and the like in the description and in the claims of the present application, and above, if any, are used for distinguishing between similar objects and not necessarily for describing a specific sequential or chronological order. It is to be understood that the use of the terms so construed herein can be interchanged, such that the embodiments described herein can be carried out in other than the precise construction or order disclosed. Further, the terms "comprise" and "include", along with their conjugates, do not exclude the presence of elements or steps other than those listed.

[0086] Those skilled in the art should be aware that, in the above one or more examples, only the technical solutions of the present application are used for illustration, but not for limitation. Although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can still be modified, or some technical features can be replaced by equivalent replacements, and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A transistor, characterized by, The substrate, gate structure; The substrate is provided with a trench, a source region and a drain region; The gate structure is arranged in the trench; The gate structure includes a dielectric layer, a first filling region, a second filling region and a third filling region; The dielectric layer covers the inner surface of the trench; the filling material of the first filling region is arranged in contact with the bottom of the trench, the second filling region is arranged on the first filling region, the third filling region is arranged in the second filling region, and the third filling region is not in contact with the dielectric layer; The work function of the filling material in the first filling region is greater than that of the filling material in the second filling region; the work function of the filling material in the third filling region is greater than that of the filling material in the second filling region. The source region and the drain region are arranged on the first filling region and on both sides of the trench.

2. The transistor of claim 1, wherein The filling material of the first filling region includes titanium nitride and / or tungsten; the filling material of the third filling region includes titanium nitride and / or tungsten.

3. The transistor according to claim 1 or 2, characterized in that, The filling material of the second filling region includes polysilicon.

4. The transistor according to any one of claims 1 to 3, wherein The second filling region surrounds the third filling region in a "concave" shape.

5. The transistor according to any one of claims 1 to 4, wherein The surface of the third filling region which is not in contact with the second filling region is concave.

6. The transistor of claim 4, wherein The second filling region surrounds the third filling region.

7. The transistor according to any one of claims 1 to 4, wherein The thickness of the second filling region is between 0.5 nanometers and 15 nanometers.

8. The transistor according to any one of claims 1 to 7, wherein The volume ratio of the third filling region to the second filling region is between 1 / 9 and 9.

9. The transistor according to any one of claims 1 to 8, wherein The third filling region is in a "concave" shape.

10. The transistor according to any one of claims 1 to 9, wherein The memory array includes a word line, a bit line, a source line and a plurality of memory cells; the memory cells include a capacitor and a transistor according to any one of claims 1-10; the plurality of memory cells are arranged in an array; 11. A memory array comprising: The word line is connected to the gate structure of the transistor; the bit line is connected to the first terminal of the transistor; the source line is connected to the second terminal of the transistor through the capacitor; The first terminal and the second terminal are the source and the drain of the transistor respectively. The memory array includes a controller and the memory array according to claim 11; 12. A memory, comprising: The controller is connected to the memory array; the controller is used to access the memory array. The memory includes a circuit board and the memory according to claim 12; the memory is integrated on the circuit board.

13. An electronic device, comprising: The substrate, gate structure; 14. A method of fabricating a transistor, characterized by: The substrate is provided with a trench, a source region and a drain region; The gate structure is arranged in the trench; The gate structure includes a dielectric layer, a first filling region, a second filling region and a third filling region; The dielectric layer covers the inner surface of the trench; the filling material of the first filling region is arranged in contact with the bottom of the trench, the second filling region is arranged on the first filling region, the third filling region is arranged in the second filling region, and the third filling region is not in contact with the dielectric layer; The work function of the filling material in the first filling region is greater than that of the filling material in the second filling region; the work function of the filling material in the third filling region is greater than that of the filling material in the second filling region. ​

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