Power conversion device

Abstract

Each arm unit (20) of a power conversion device (10) of one example disclosed in the present description is provided with: an overcurrent detection circuit (15, 25) that detects overcurrent flowing to a target arm (70) to be controlled; a clamp circuit (42, 47) that limits the voltage of a drive signal (Vout) to a clamp voltage (Vcl); and a clamp control circuit (48) that, if an overcurrent detection signal (SigE) indicates detection of overcurrent, lowers the voltage of the drive signal (Vout) to the clamp voltage (Vcl) and, if set conditions have been met or if a predetermined set time (Ts) has elapsed since the time at which the overcurrent detection signal (SigE) indicated detection of overcurrent, controls the clamp circuit (42, 47) so that output of the clamp voltage (Vcl) is halted.

Description

Power Conversion Device

[0001] The present disclosure relates to a power conversion device.

[0002] Power semiconductor elements, which act as switches, are essential in power conversion devices. Some power conversion devices are equipped with a function to detect short circuits caused by power semiconductor element or load failure, noise malfunction, etc., and stop power conversion to prevent damage to the device.

[0003] Patent Document 1 discloses a power conversion device in which three sets of upper and lower arms, each of which has a power semiconductor element connected in series, are connected in parallel, and each upper and lower arm constitutes one phase. Patent Document 1 describes that when the power conversion device is used as an inverter, an arm short circuit, which is one type of short circuit phenomenon, is generally classified into three short circuit modes (Type 1 to Type 3).

[0004] If the power conversion device is an inverter, and the power semiconductor elements are IGBTs (Insulated Gate Bipolar Transistors) and diodes connected in anti-parallel to the IGBTs, a Type 1 short circuit occurs when one of the upper and lower arm elements, the self-element, turns on. When the self-element is in the off state, the other upper and lower arm element, the paired element, breaks down and remains conductive. In this state, the self-element turns on, causing an excessive current to flow. The maximum current value in a Type 1 short circuit is determined by the saturation current characteristics of the IGBT, and in the case of a typical IGBT, short-circuit destruction occurs approximately 10 μs to 20 μs after the start of the short circuit.

[0005] A Type 2 short circuit occurs when a counter element in the off state suddenly breaks down while the element itself is in the on state and collector current is flowing. Because the short circuit occurs while the element itself is in the on state, the rate of current change is greater than in a Type 1 short circuit, which is limited by the element characteristics. After the collector current reaches its maximum, the gate voltage drops and the collector current rapidly changes to its saturated current value, causing an instantaneous increase in the collector-emitter voltage, i.e., the voltage between the main terminals, which can result in instantaneous overvoltage breakdown. This type of overvoltage breakdown is described in Non-Patent Document 1. When overvoltage breakdown occurs due to a Type 2 short circuit, the IGBT breaks down approximately 2 μs after the short circuit begins.

[0006] Like a Type 2 short circuit, a Type 3 short circuit is a mode in which a short circuit occurs while the device itself is in the on state. A Type 3 short circuit occurs when a pair of devices in the off state suddenly breaks down and shorts while the diode connected in anti-parallel to the device itself is conducting. In other words, a Type 3 short circuit differs from a Type 2 short circuit in that a short circuit occurs while the diode connected in anti-parallel to the device itself is conducting. Because the device itself is short-circuited in the on state, the current change rate is the same as a Type 2 short circuit, and overvoltage breakdown of the IGBT can occur in a short time of about 2 μs.

[0007] Type 2 and Type 3 short circuits are short-circuit phenomena that occur when a pair of elements is destroyed, and the purpose of the circuit that protects the element itself is to prevent secondary destruction of the element itself. In the case of Type 2 and Type 3 short circuits, the time until destruction is much shorter than in the case of Type 1 short circuits, so it is necessary to detect the short circuit phenomenon quickly and control the gate voltage appropriately.

[0008] In the power conversion device of Patent Document 1, when the power semiconductor element is an IGBT, the gate voltage and emitter current are used to determine whether a short circuit has occurred, in order to handle Type 2 and Type 3 short circuits. When an overvoltage detection signal indicating that the gate voltage, which is the earliest short circuit detection value, has exceeded a determination value is output, the power conversion device of Patent Document 1 reduces the gate voltage for a certain period of time to a level at which the power semiconductor element will not be shut off, and then, when an overcurrent detection signal is output, it determines that a short circuit has occurred and further reduces the gate voltage of the power semiconductor element to shut it off, thereby protecting the power semiconductor element.

[0009] Patent Document 2 discloses a power conversion device that can suppress overcurrent in a self-extinguishing power semiconductor element by including a means for reducing the gate voltage when a short circuit occurs. The power conversion device of Patent Document 2 further includes a means for increasing the gate voltage again when an overvoltage at the collector terminal is detected at a level that poses a problem in terms of withstand voltage during gate voltage reduction for overcurrent protection, thereby preventing overvoltage breakdown of the power semiconductor element.

[0010] JP 2018-57105 A JP 2006-94654 A

[0011] Thomas Basler, “Ruggedness of High-Voltage IGBTs and Protection Solutions”, Chemnitz University Press, 2014

[0012] The power conversion device of Patent Document 1 is capable of suppressing short-circuit current, but is ineffective in suppressing the sudden change in collector current up to the saturated current value that occurs after a current peak due to a Type 2 short circuit or a Type 3 short circuit, making it difficult to prevent overvoltage breakdown of power semiconductor elements.

[0013] The power conversion device of Patent Document 2 raises the gate voltage again only after detecting an overvoltage at the collector terminal that is at a level that would cause problems in terms of withstand voltage while reducing the gate voltage for overcurrent protection. Therefore, if the voltage between the main terminals becomes an overvoltage instantaneously due to a Type 2 or Type 3 short circuit, there is a risk that protection will not be able to be implemented in time and the device will be destroyed.

[0014] An object of the present disclosure is to provide a power conversion device that can reliably prevent overvoltage breakdown of power semiconductor elements due to type 2 short circuits and type 3 short circuits.

[0015] A power conversion device according to the present disclosure is a power conversion device that outputs output power obtained by power conversion of input power by a power conversion unit having a plurality of power semiconductor elements. The power conversion unit includes a plurality of upper and lower arms in which an upper arm having a power semiconductor element and a lower arm having a power semiconductor element controlled so as not to be turned on simultaneously with the upper arm are connected in series, and a plurality of arm control circuits that control each of the upper and lower arms. The arm control circuit includes a drive circuit unit that outputs a drive signal to drive a target arm that is the upper arm or lower arm to be controlled, an overcurrent detection circuit that uses a current slope that is the slope over time of a main current flowing through the target arm or a voltage slope that is the slope over time of a voltage between the main terminals of the target arm, detects that an overcurrent has flowed through the target arm in the on-state based on the detected slope, and outputs an overcurrent detection signal indicating the overcurrent detection, and a clamp circuit that limits the voltage of the drive signal to a clamp voltage. The clamp control circuit controls the clamp circuit to reduce the voltage of the drive signal to a clamp voltage when the overcurrent detection signal indicates an overcurrent detection, and controls the clamp circuit to stop outputting the clamp voltage when a predetermined set condition is satisfied based on the detection slope or when a predetermined set time has elapsed since the time the overcurrent detection signal indicated an overcurrent detection, and the drive circuit unit changes the voltage of the drive signal to change the target arm from an on state to an off state after the output of the clamp voltage is stopped.

[0016] The power conversion device disclosed herein includes an overcurrent detection circuit that detects the flow of an overcurrent in a target arm, a clamp circuit that limits the voltage of the drive signal to a clamp voltage, and a clamp control circuit that reduces the voltage of the drive signal to the clamp voltage when the overcurrent detection signal indicates an overcurrent detection, and controls the clamp circuit to stop outputting the clamp voltage when a set condition is satisfied or when a predetermined set time has elapsed since the time the overcurrent detection signal indicated an overcurrent detection, thereby making it possible to reliably prevent overvoltage destruction of power semiconductor elements due to Type 2 short circuits and Type 3 short circuits.

[0017] 14 is a diagram showing the configuration of a first power conversion device according to embodiment 1. FIG. 14 is a diagram showing the configuration of an arm unit of FIG. 1. FIG. 14 is a diagram showing the configuration of a drive circuit unit and a clamp circuit of FIG. 2. FIG. 14 is a diagram showing the configuration of a slope detection unit of FIG. 2. FIG. 14 is a diagram showing the configuration of an overcurrent detection unit of FIG. 2. FIG. 14 is a timing chart explaining the operation of an arm unit according to embodiment 1. FIG. 14 is a diagram explaining loop inductance of a power conversion device according to embodiment 1. FIG. 14 is a diagram showing the configuration of a second power conversion device according to embodiment 1. FIG. 14 is a diagram showing the configuration of a third power conversion device according to embodiment 1. FIG. 14 is a diagram showing the configuration of a fourth power conversion device according to embodiment 1. FIG. 14 is a diagram showing the configuration of an arm unit of FIG. 10. FIG. 14 is a diagram showing the configuration of an arm unit according to embodiment 2. FIG. 14 is a timing chart explaining the operation of an arm unit according to embodiment 2. FIG. 14 is a diagram showing the configuration of a first arm unit according to embodiment 3. FIG. 14 is a diagram showing the configuration of a drive circuit unit and a clamp circuit of FIG. 14. FIG. 14 is a diagram showing the configuration of a first slope detection unit of FIG. 14. FIG. 14 is a diagram showing the configuration of a second arm unit according to embodiment 3. FIG. 14 is a timing chart explaining the operation of a first arm unit according to embodiment 3. FIG. 14 is a diagram showing the configuration of a second arm unit according to embodiment 3. FIG. 14 is a timing chart explaining the operation of a second arm unit according to embodiment 3. FIG. 14 is a diagram showing the configuration of a third arm unit according to embodiment 3. 29 is a diagram illustrating a configuration of a power conversion device according to embodiment 4. FIG. 29 is a diagram illustrating a configuration of a first arm unit according to embodiment 4. FIG. 29 is a diagram illustrating a configuration of the tilt detection unit of FIG. 23. FIG. 29 is a diagram illustrating a configuration of the overcurrent detection unit of FIG. 23. FIG. 29 is a timing chart illustrating the operation of the first arm unit according to embodiment 4. FIG. 29 is a diagram illustrating a configuration of a second arm unit according to embodiment 4. FIG. 29 is a timing chart illustrating the operation of the second arm unit according to embodiment 4. FIG. 30 is a diagram illustrating a configuration of a third arm unit according to embodiment 4. FIG. 30 is a diagram illustrating the configuration of the drive circuit unit and clamp circuit of FIG. 29. FIG. 30 is a timing chart illustrating the operation of the third arm unit according to embodiment 4. FIG. 30 is a diagram illustrating a hardware configuration example in which the functions of the control circuit and the on / off determination unit are realized by digital calculation. FIG. 30 is a diagram illustrating the operation of a power semiconductor element. FIG. 30 is a diagram illustrating a type 1 short circuit of a power semiconductor element.1A and 1B are diagrams illustrating a type 2 short circuit in a power semiconductor element;

[0018] Hereinafter, preferred embodiments of a power conversion device according to the present disclosure will be described with reference to the drawings. The same components and corresponding parts are designated by the same reference numerals, and detailed descriptions thereof will be omitted. Similarly, in the following embodiments, redundant descriptions of components designated by the same reference numerals will be omitted.

[0019] Embodiment 1. FIG. 1 is a diagram showing the configuration of a first power conversion device according to embodiment 1, and FIG. 2 is a diagram showing the configuration of an arm unit in FIG. 1. FIG. 3 is a diagram showing the configuration of a drive circuit unit and a clamp circuit in FIG. 2, FIG. 4 is a diagram showing the configuration of a slope detection unit in FIG. 2, and FIG. 5 is a diagram showing the configuration of an overcurrent detection unit in FIG. 2. FIG. 6 is a timing chart illustrating the operation of the arm unit according to embodiment 1, and FIG. 7 is a diagram illustrating the loop inductance of the power conversion device according to embodiment 1. FIG. 8 is a diagram showing the configuration of a second power conversion device according to embodiment 1, and FIG. 9 is a diagram showing the configuration of a third power conversion device according to embodiment 1. FIG. 10 is a diagram showing the configuration of a fourth power conversion device according to embodiment 1, and FIG. 11 is a diagram showing the configuration of the arm unit in FIG. 10. The power conversion device 10 according to embodiment 1 is a device that performs power conversion between a power source 1 and a load 2, i.e., a device that outputs output power Po obtained by power conversion of input power Pi by a power conversion unit 12 having a plurality of power semiconductor elements 13. The first power conversion device 10 of the first embodiment shown in Fig. 1 is an example in which the power source 1 is an AC power source 18 and the load 2 is an AC load 19. The second power conversion device 10 of the first embodiment shown in Fig. 8 is an example in which the power source 1 is a DC power source 3 and the load 2 is an AC load 19. The third power conversion device 10 of the first embodiment shown in Fig. 9 is an example in which the power source 1 is an AC power source 18 and the load 2 is a DC load 4.

[0020] The first power conversion device 10 of the first embodiment shown in FIG. 1 includes a converter 11 that converts AC power, which is input power Pi, into DC power, and a power conversion unit 12 and a control circuit 16 that constitute an inverter that converts the DC power output from the converter 11 into AC power and outputs DC power, which is output power Po. The second power conversion device 10 of the first embodiment shown in FIG. 8 includes a power conversion unit 12, i.e., an inverter unit 5, that converts DC power, which is input power Pi, input from a DC power source 3, and outputs AC power, which is output power Po. The third power conversion device 10 of the first embodiment shown in FIG. 9 includes a power conversion unit 12, i.e., a converter unit 6, that converts AC power, which is input power Pi, input from an AC power source 18, and converts it into DC power, which is output power Po. The power conversion unit 12 shown in FIG. 1 is an example of the inverter unit 5. Note that the control circuit 16 that controls the inverter unit 5 or the converter unit 6 and the input-side capacitor 17 are omitted in FIGS. 8 and 9 .

[0021] The power conversion unit 12 of the inverter shown in FIG. 1 and the inverter unit 5 shown in FIG. 8 convert DC power, i.e., DC voltage and DC voltage, into three-phase AC power, i.e., three-phase AC voltage and three-phase AC current. The power conversion unit 12, which is the converter unit 6 shown in FIG. 9, converts three-phase AC power, i.e., three-phase AC voltage and three-phase AC current, into DC power, i.e., DC voltage and DC current. The power conversion unit 12 includes six arm units 20a, 20b, 20c, 20d, 20e, and 20f. FIG. 1 illustrates an example in which the inverter that converts DC power output from the converter 11 into three-phase AC power includes six arm units 20a, 20b, 20c, 20d, 20e, and 20f, a control circuit 16, and a capacitor 17. The arm units 20a to 20f include power semiconductor elements 13. Here, the power semiconductor elements 13 are described as IGBTs and diodes connected in anti-parallel to the IGBTs.

[0022] The power conversion unit 12 includes upper and lower arms 30a, 30b, and 30c (see FIG. 7 ), each of which includes an upper arm and a lower arm having power semiconductor elements 13 connected in series between a positive wiring 35 and a negative wiring 36. The first to fourth power conversion devices 10 of the first embodiment each include three upper and lower arms 30a, 30b, and 30c. In the upper and lower arm 30a, the upper arm having the power semiconductor element 13a and the lower arm having the power semiconductor element 13b are connected in series between the positive wiring 35 and the negative wiring 36. Similarly, in the upper and lower arm 30b, the upper arm having the power semiconductor element 13c and the lower arm having the power semiconductor element 13d are connected in series between the positive wiring 35 and the negative wiring 36. In the upper and lower arm 30c, the upper arm having the power semiconductor element 13e and the lower arm having the power semiconductor element 13f are connected in series between the positive wiring 35 and the negative wiring 36. Each of the power semiconductor elements 13a to 13f of the upper arm and lower arm is controlled by an arm control circuit 14. The upper arm having power semiconductor element 13a and the arm control circuit 14 constitute arm section 20a, and the upper arm having power semiconductor element 13b and the arm control circuit 14 constitute arm section 20b. Similarly, the upper arm having power semiconductor element 13c and the arm control circuit 14 constitute arm section 20c, and the upper arm having power semiconductor element 13d and the arm control circuit 14 constitute arm section 20d. The upper arm having power semiconductor element 13e and the arm control circuit 14 constitute arm section 20e, and the upper arm having power semiconductor element 13f and the arm control circuit 14 constitute arm section 20f. Note that the reference numeral 13 is used collectively for the power semiconductor elements, with 13a to 13f used when distinguishing between them. The reference numeral 20 is used collectively for the arm sections, with 20a to 20f used when distinguishing between them. Two or more power semiconductor elements 13 in each upper arm and lower arm may be connected in series or in parallel, but examples having one power semiconductor element 13 are shown in Figures 1, 2, and 7 to 11. The power semiconductor element 13 will be referred to as an arm as appropriate. Of the upper arm and lower arm, the arm of interest as the control target will be referred to as the target arm 70.

[0023] The upper arm or lower arm paired with the target arm 70 is called the counter arm. When the target arm 70 is the power semiconductor element 13a, the counter arm facing it, i.e., paired with it, is the power semiconductor element 13b, and when the target arm 70 is the power semiconductor element 13b, the counter arm facing it is the power semiconductor element 13a. Similarly, when the target arm 70 is the power semiconductor element 13c, the counter arm facing it is the power semiconductor element 13d, and when the target arm 70 is the power semiconductor element 13d, the counter arm facing it is the power semiconductor element 13c. When the target arm 70 is the power semiconductor element 13e, the counter arm facing it is the power semiconductor element 13f, and when the target arm 70 is the power semiconductor element 13f, the counter arm facing it is the power semiconductor element 13e. Using the arm sections 20a to 20f, the target arms and counter arms can be expressed as follows: When the target arm 70 is in arm section 20a, the paired arm is the power semiconductor element 13 in arm section 20b, and when the target arm 70 is in arm section 20b, the paired arm is the power semiconductor element 13 in arm section 20a. Similarly, when the target arm 70 is in arm section 20c, the paired arm is the power semiconductor element 13 in arm section 20d, and when the target arm 70 is in arm section 20d, the paired arm is the power semiconductor element 13 in arm section 20c. When the target arm 70 is in arm section 20e, the paired arm is the power semiconductor element 13 in arm section 20f, and when the target arm 70 is in arm section 20f, the paired arm is the power semiconductor element 13 in arm section 20e. Note that the aforementioned own element is the power semiconductor element 13 of the target arm 70, and the aforementioned paired element is the power semiconductor element 13 of the paired arm.

[0024] Before explaining the details, we will explain in detail the overvoltage breakdown due to Type 2 short circuit and Type 3 short circuit, which are mentioned in the problem of this disclosure. First, Type 1 short circuit and Type 2 short circuit will be explained using Figures 34 to 37. Figure 34 is a diagram explaining the operation of a power semiconductor element, and Figure 35 is a diagram explaining a Type 1 short circuit of a power semiconductor element. Figures 36 and 37 are diagrams each explaining a Type 2 short circuit of a power semiconductor element.

[0025] FIG. 34 shows voltage and current waveforms during normal turn-on. FIG. 34 shows a voltage characteristic 92a of the collector-emitter voltage Vce, a current characteristic 93a of the collector current Ic, and a voltage characteristic 94a of the gate-emitter voltage Vge. In FIG. 34, the horizontal axis represents time [s], the vertical axis represents voltage [V] of the collector-emitter voltage Vce, the vertical axis represents current [A] of the collector current Ic, and the vertical axis represents voltage [V] of the gate-emitter voltage Vge. The horizontal and vertical axes in FIGS. 35 to 37 are the same as those in FIG. 34. From the time at the left end to time t10, the gate-emitter voltage Vge is at an off-gate voltage Vg2 at which the power semiconductor device maintains an off-state. At time t14, the gate-emitter voltage Vge is at an on-gate voltage Vg1 at which the power semiconductor device maintains an on-state. The off-gate voltage Vg2 is, for example, a negative voltage Vn, and the on-gate voltage Vg1 is, for example, a positive voltage Vp. The negative voltage Vn may include zero. As the gate-emitter voltage Vge changes from the negative voltage Vn to the positive voltage Vp from time t10 to time t14, the collector-emitter voltage Vce decreases from the off-voltage Va to the on-voltage Vb, and the collector current Ic becomes the same current value as the load current Im. At time t10, the gate-emitter voltage Vge increases from the negative voltage Vn, and at time t11, the gate-emitter voltage Vge becomes zero, the collector-emitter voltage Vce decreases from the off-voltage Va, and the collector current Ic increases. At time t12, the collector current Ic reaches a maximum value and then begins to decrease. At time t13, the collector-emitter voltage Vce drops to the on-voltage Vb, and at time t14, the gate-emitter voltage Vge becomes the positive voltage Vp, which is the on-gate voltage Vg1.

[0026] Figure 35 shows current and voltage waveforms of a Type 1 short circuit. Figure 35 shows voltage characteristics 92b of the collector-emitter voltage Vce, current characteristics 93b of the collector current Ic, and voltage characteristics 94b of the gate-emitter voltage Vge. As mentioned above, in a Type 1 short circuit, a short circuit occurs when the power semiconductor element of the target arm 70, i.e., the target element, turns on. If the power conversion device is an inverter, while the target element is turned off, the power semiconductor element of the opposing arm, i.e., the target element, breaks down and remains conductive. In this state, the target element turns on, causing an excessive current to flow. At time t20, the gate-emitter voltage Vge of the target element rises from the negative voltage Vn, which is the off-gate voltage Vg2. At time t21, the collector-emitter voltage Vce begins to drop from the off-voltage Va, and the collector current Ic begins to rise. However, because the paired element has been destroyed and remains conductive, the collector-emitter voltage Vce of the element does not drop to the on-voltage Vb, as would normally occur. Instead, the collector-emitter voltage Vce reaches a minimum value at time t22, and then rises to the off-voltage Va at time t23. At time t24, the gate-emitter voltage Vge of the element becomes a positive voltage Vp, and the collector current Ic reaches its maximum value. Note that the off-voltage Va in a Type 1 short circuit is the input voltage Vin input to the inverter. The maximum value of the current in a Type 1 short circuit is determined by the saturation current characteristics of the IGBT. In a typical IGBT, the element will be destroyed by short circuit approximately 10 μs to 20 μs after the start of the short circuit.

[0027] FIG. 36 shows current-voltage waveforms of a Type 2 short circuit when the gate-emitter voltage Vge is not clamped to the clamp voltage Vcl. FIG. 36 shows a voltage characteristic 92c of the collector-emitter voltage Vce, a current characteristic 93c of the collector current Ic, and a voltage characteristic 94c of the gate-emitter voltage Vge. As described above, in a Type 2 short circuit, a paired element in an off state, i.e., an off-state paired element, suddenly breaks down and a short circuit occurs while the power semiconductor element in the target arm 70, i.e., the element itself, is on and the collector current Ic is flowing. In FIG. 36, the collector current Ic up to time t30 is, for example, the load current Im. Because a Type 2 short circuit occurs when the element itself is on, the current change rate is greater than that of a Type 1 short circuit, which is limited by the element characteristics. As shown in FIG. 36, after the collector current Ic reaches its maximum at time t31, the element itself may suddenly break down due to an overvoltage breakdown due to the drop in the gate-emitter voltage Vge and the sudden change in the collector current Ic to its saturated current value. The device itself and the paired device operate normally until time t30. At this time, the device itself has a gate-emitter voltage Vge that is a positive voltage Vp, which is the on-gate voltage Vg1, a collector-emitter voltage Vce that is an on-voltage Vb, and a collector current Ic that is a load current Im. When the paired device breaks down at time t30, the device itself has a collector-emitter voltage Vce, a collector current Ic, and a gate-emitter voltage Vge that increase. The collector current Ic reaches its maximum at time t31, the gate-emitter voltage Vge begins to decrease, and the collector-emitter voltage Vce rises sharply. At time t32, the collector current Ic decreases, and the negative slope, or negative rate of change, of the collector current Ic reaches its maximum. At the same time, the collector-emitter voltage Vce reaches its maximum value, and the gate-emitter voltage Vge reaches its minimum value. From time t32 to time t33, the gate-emitter voltage Vge rises to a positive voltage Vp, the collector-emitter voltage Vce falls as breakdown occurs, and the collector current Ic decreases. At time t33, the gate-emitter voltage Vge reaches a positive voltage Vp, the collector current Ic reaches a minimum, and the collector-emitter voltage Vce reaches its minimum value after breakdown. After time t33, the gate-emitter voltage Vge remains at a positive voltage Vp, the collector current Ic rises, and the collector-emitter voltage Vce gradually rises.Figure 36 shows an example in which breakdown occurs when the collector-emitter voltage Vce exceeds the element's breakdown voltage Vbr. The changes in the collector-emitter voltage Vce and collector current Ic vary depending on the breakdown state of the element itself, but generally they change as shown in Figure 36. When the element itself is broken down by an overvoltage of the collector-emitter voltage Vce due to a type 2 short circuit, that is, when overvoltage breakdown occurs, in a typical IGBT, the element itself breaks down approximately 2 μs after the start of the short circuit.

[0028] The drop in gate-emitter voltage Vge from time t31 to time t32 is explained in Non-Patent Document 1, and is caused by energy accumulated in the wiring from the gate terminal G of the power semiconductor element, which is the element itself, to the drive circuit unit, i.e., gate drive wiring 28 (see FIG. 2), and the negative differential capacitance between the gate terminal G and the collector terminal C, i.e., gate-collector. The drop in gate-emitter voltage Vge (drop to the minimum value at time t32) also causes a sudden drop in collector current Ic, and an overvoltage (Lp×dIc / dt) is generated due to the loop inductance between the capacitor on the input side of the inverter unit and the power semiconductor element, i.e., the inductance of the loop path (see FIG. 7), and the sudden drop in collector current Ic (dIc / dt), which destroys the power semiconductor element, which is the element itself. The occurrence of overvoltage breakdown in a Type 2 short circuit is determined by the length of the wiring from the gate terminal G of the power semiconductor element itself to the drive circuit, the characteristics of the power semiconductor element, the driving conditions of the inverter (driving conditions of the power conversion device), etc. The inductance of the power semiconductor element is much smaller than the inductance of the wiring pattern in the loop path, so it can be ignored.

[0029] FIG. 37 shows current-voltage waveforms when the gate-emitter voltage Vge is clamped to a clamp voltage Vcl during a type 2 short circuit. FIG. 37 also shows a voltage characteristic 92d of the collector-emitter voltage Vce, a current characteristic 93d of the collector current Ic, and a voltage characteristic 94d of the gate-emitter voltage Vge. Similar to the power conversion device of Patent Document 1, FIG. 37 shows an example in which a clamp circuit that clamps the gate-emitter voltage Vge to a clamp voltage Vcl is applied. The collector current Ic up to time t40 in FIG. 37 is, for example, the load current Im. When a clamp circuit and an overcurrent detection circuit that detects an overcurrent in the collector current Ic are provided, the device detects an overcurrent after a short circuit occurs in the device itself and reduces the gate-emitter voltage Vge to the clamp voltage Vcl, thereby suppressing the increase in the collector current Ic and the peak of the collector current Ic, and reducing stress on the device itself due to the overcurrent.

[0030] However, even if the gate-emitter voltage Vge is clamped to the clamp voltage Vcl, if the energy accumulated in the wiring from the gate terminal G of the power semiconductor element (the element itself) to the drive circuit unit, i.e., the gate drive wiring 28, and the negative differential capacitance between the gate and collector are large, a clamp circuit that is at a level that suppresses the short-circuit current of a Type 1 short circuit will not be able to maintain the clamp voltage Vcl as shown in FIG. 37, and if the gate-emitter voltage Vge falls below the clamp voltage Vcl, the negative slope of the collector current Ic, i.e., the negative rate of change, will become steep (from time t43 to time t44), and as a result, the collector current Ic will fall abruptly, which may result in overvoltage breakdown of the power semiconductor element (the element itself).

[0031] In Figure 37, the own element and the paired element operate normally until time t40. At this time, the own element has a gate-emitter voltage Vge that is a positive voltage Vp, which is the on-gate voltage Vg1, a collector-emitter voltage Vce that is an on-voltage Vb, and a collector current Ic that is a load current Im. When the paired element breaks down at time t40, the collector-emitter voltage Vce, collector current Ic, and gate-emitter voltage Vge of the own element rise. At time t41, the gate-emitter voltage Vge is clamped to a clamp voltage Vcl. From time t41 to time t42, the collector-emitter voltage Vce and collector current Ic rise. The collector current Ic reaches its maximum at time t42, and the collector-emitter voltage Vce rises sharply. At time t43, the collector-emitter voltage Vce exceeds the element's breakdown voltage Vbr, causing the own element to break down. At time t44, the collector current Ic decreases, and the negative slope, or negative rate of change, of the collector current Ic reaches its maximum. At the same time, the collector-emitter voltage Vce reaches its maximum value, and the gate-emitter voltage Vge cannot maintain the clamp voltage Vcl and reaches its minimum value. From time t44 to time t45, the gate-emitter voltage Vge rises to a positive voltage Vp, the collector-emitter voltage Vce drops as breakdown occurs, and the collector current Ic decreases. At time t45, the gate-emitter voltage Vge reaches a positive voltage Vp, the collector current Ic rises from its minimum value, and the collector-emitter voltage Vce reaches its minimum value after breakdown. After time t45, the gate-emitter voltage Vge remains at a positive voltage Vp, the collector current Ic rises, and the collector-emitter voltage Vce gradually rises.

[0032] 37, the sudden drop in collector current Ic occurs because the clamp voltage Vcl is closer to the threshold of the gate-emitter voltage Vge of the power semiconductor element itself, i.e., the gate voltage threshold, than the positive voltage Vp, so even a small drop in the gate-emitter voltage Vge causes a sudden drop in current. Also, a characteristic of Type 2 short circuit is that while the sudden rise in collector current Ic can be suppressed by operating the clamp circuit, the current value of the collector current Ic cannot be reduced.

[0033] As mentioned above, a Type 3 short circuit, like a Type 2 short circuit, is a mode in which a short circuit occurs while the device itself is in the ON state. However, it differs from a Type 2 short circuit in that the paired device, which is in the OFF state, suddenly breaks down and shorts out while the diode connected in antiparallel to the device itself is conducting. Because a Type 3 short circuit occurs while the device itself is in the ON state, the current change rate is the same as a Type 2 short circuit, and overvoltage breakdown can occur in a short period of time, such as within 2 μs, just like a Type 2 short circuit.

[0034] The present disclosure aims to reliably prevent overvoltage breakdown of power semiconductor elements caused by Type 2 short circuits and Type 3 short circuits, and by appropriately controlling the gate-emitter voltage Vge, i.e., controlling the gate voltage, based on the characteristics of the current-voltage waveforms during Type 2 short circuits and Type 3 short circuits, it is possible to suppress the collector-emitter voltage Vce within the withstand voltage, i.e., the element withstand voltage Vbr, while reducing stress on the power semiconductor element due to overcurrent.

[0035] Next, a power conversion device 10 according to the first embodiment will be described in detail. First, a first power conversion device 10 according to the first embodiment will be described. The power conversion unit 12 of the first power conversion device 10 shown in FIG. 1 includes six arm units 20a to 20f, all of which have the same configuration. The arm unit 20 includes a power semiconductor element 13 and an arm control circuit 14 that controls the power semiconductor element 13. The arm control circuit 14 includes a drive circuit unit 41 that outputs a drive signal Vout that drives the power semiconductor element 13, an overcurrent detection circuit 15 that detects that an overcurrent has flowed through the power semiconductor element 13 and outputs an overcurrent detection signal SigE indicating the detection of an overcurrent, a clamp circuit 42 that limits the voltage of the drive signal Vout to a clamp voltage Vcl, and a clamp control circuit 48 that controls the clamp circuit 42. The overcurrent detection circuit 15 includes a gradient information output device 40 that outputs a detection voltage Vdet including a current gradient Ski, which is the gradient with time of the collector current Ic, which is the main current flowing through the target arm 70; a current detection circuit 22 that detects the collector current Ic, which is the main current, based on the detection voltage Vdet; an overcurrent detection unit 23 that detects the flow of an overcurrent based on the collector current Ic detected by the current detection circuit 22 and outputs an overcurrent detection signal SigE indicating the overcurrent detection; and a gradient detection unit 43 that outputs a gradient determination signal Sg1 that determines the current gradient Ski included in the detection voltage Vdet. In FIG. 2 and FIG. 4, an inductor 21 that outputs the detection voltage Vdet including information about the current gradient Ski is shown as an example of the gradient information output device 40. In FIG. 2, the inductor 21 is connected to the emitter terminal E, which is the main terminal of the power semiconductor element 13. The inductor 21 may also be connected to the collector terminal C, which is the main terminal of the power semiconductor element 13.

[0036] The power semiconductor element 13 includes, for example, an IGBT, which is a transistor Tr, and a diode Di connected in antiparallel between a collector terminal C, which is a main terminal of the transistor Tr, and an emitter terminal E. The switching operation of the power semiconductor element 13 is controlled by a drive signal Vout input to a gate terminal G.

[0037] The drive circuit unit 41 outputs a drive signal Vout, which is based on a reference potential Vs, which is the potential of the emitter connecting wiring 29 connected to the emitter terminal E of the power semiconductor element 13, to the gate terminal G of the power semiconductor element 13 via the gate drive wiring 28. The drive signal Vout controls a gate-emitter voltage Vge, which is the voltage between the emitter terminal E and the gate terminal G of the power semiconductor element 13. The clamp circuit 42 is connected to the gate drive wiring 28 and the emitter connecting wiring 29. An inductor 21 having an inductance L includes a first terminal A1 and a second terminal A2. The inductor 21 is disposed, for example, on the emitter terminal E side of the power semiconductor element 13. The first terminal A1 and the second terminal A2 of the inductor 21 are connected to the current detection circuit 22 and the slope detection unit 43. While FIG. 2 shows an example in which the first terminal A1 is disposed away from the emitter terminal E of the power semiconductor element 13, the first terminal A1 may be set to the emitter terminal E of the power semiconductor element 13.

[0038] Here, the inductor 21 may be a parasitic inductor. The parasitic inductor may be a parasitic inductor formed by wiring within the semiconductor module of the power semiconductor element 13, or a parasitic inductor on a bus bar or circuit board. The inductor 21 may be a pattern, component, or the like that includes an inductance component.

[0039] The clamp control circuit 48 includes AND circuits 44 and 45 and a one-shot circuit 46. The slope determination signal Sg1 output from the slope detection unit 43 is input to one input of the AND circuit 44, and the on / off signal Sig1 input to the drive circuit unit 41 is input to the other input of the AND circuit 44. The on / off signal Sig1 is output from the control circuit 16. The AND circuit 44 outputs an output signal Vk1. The output signal Vk1 output from the AND circuit 44 is input to one input of the AND circuit 45, and the overcurrent detection signal SigE output from the overcurrent detection unit 23 is input to the other input of the AND circuit 45. The AND circuit 45 outputs an output signal Vk2. The overcurrent detection signal SigE is input to the drive circuit unit 41 and the control circuit 16 together with the AND circuit 45.

[0040] The one-shot circuit 46 outputs a switch drive signal Vsw that causes the clamp circuit 42 to output a clamp voltage Vcl for a predetermined set time Ts based on the output signal Vk2 output from the AND circuit 45. The switch drive signal Vsw output from the one-shot circuit 46 is output to the control circuit 16 as a breakdown detection signal SigF for notifying a higher-level device that the paired arm has been broken.

[0041] The on / off signal Sig1 output from the control circuit 16 is input to the drive circuit unit 41. The control circuit 16 outputs the on / off signal Sig1 for the upper arm and the on / off signal Sig1 for the lower arm so that the upper arm and the lower arm are not simultaneously turned on. During normal operation of the power conversion device 10, the drive circuit unit 41 outputs a drive signal Vout of a voltage that turns the power semiconductor element 13 on or off based on the on / off signal Sig1. For example, if the transistor Tr of the power semiconductor element 13 is an IGBT, the gate-emitter voltage Vge that turns the power semiconductor element 13 on is the on-gate voltage Vg1 (see FIG. 34), and the gate-emitter voltage Vge that turns the power semiconductor element 13 off is the off-gate voltage Vg2 (see FIG. 34). For example, the on-gate voltage Vg1 is set to 15 V to 20 V, and the off-gate voltage Vg2 is set to 0 V or less. The on-gate voltage Vg1 and the off-gate voltage Vg2 are output from a positive voltage power supply 60a and a negative voltage power supply 60b, which are based on a reference potential Vs. The positive voltage power supply 60a outputs a positive voltage Vp as the on-gate voltage Vg1, and the negative voltage power supply 60b outputs a negative voltage Vn, which is zero or a negative voltage, as the off-gate voltage Vg2.

[0042] The connection relationship of the six arm sections 20a to 20f in the first power conversion device 10 of the first embodiment will be described. The power conversion device 10 includes AC terminals 31a, 31b, and 31c to which voltages of each phase of an AC power source 18 that outputs three-phase AC are input, and AC terminals 32a, 32b, and 32c that output voltages of each phase of the three-phase AC to an AC load 19. The AC terminals 31a, 31b, and 31c are connected to AC terminals 33a, 33b, and 33c of a converter 11. DC terminals 34p and 34n of the converter 11 are connected to a positive side wiring 35 and a negative side wiring 36, respectively. A capacitor 17 is connected to the positive side wiring 35 and the negative side wiring 36. The power semiconductor elements 13 of the arm sections 20a, 20c, and 20e have a collector terminal C, which is a main terminal, connected to the positive side wiring 35. The emitter terminal E, which is a main terminal, of each power semiconductor element 13 in the arm portions 20b, 20d, and 20f is connected to the negative wiring 36. The emitter terminal E of the power semiconductor element 13 in the arm portion 20a is connected to the collector terminal C of the power semiconductor element 13 in the paired arm 20b, and a connection point n1 therebetween is connected to the AC terminal 32a. The emitter terminal E of the power semiconductor element 13 in the arm portion 20c is connected to the collector terminal C of the power semiconductor element 13 in the paired arm 20d, and a connection point n2 therebetween is connected to the AC terminal 32b. The emitter terminal E of the power semiconductor element 13 in the arm portion 20e is connected to the collector terminal C of the power semiconductor element 13 in the paired arm 20f, and a connection point n3 therebetween is connected to the AC terminal 32c. The phases of the three-phase AC output from the AC terminals 32a, 32b, and 32c are, for example, U-phase, V-phase, and W-phase.

[0043] The control circuit 16 outputs on / off signals Sig1a to Sig1f to the arm sections 20a to 20f, respectively. The arm section 20a outputs an overcurrent detection signal SigEa and a breakdown detection signal SigFa, and the arm section 20b outputs an overcurrent detection signal SigEb and a breakdown detection signal SigFb. The arm section 20c outputs an overcurrent detection signal SigEc and a breakdown detection signal SigFc, and the arm section 20d outputs an overcurrent detection signal SigEd and a breakdown detection signal SigFd. The arm section 20e outputs an overcurrent detection signal SigEe and a breakdown detection signal SigFe, and the arm section 20f outputs an overcurrent detection signal SigEf and a breakdown detection signal SigFf. The on / off signals are generally designated Sig1, with Sig1a to Sig1f used when distinguishing between them. The overcurrent detection signals are generally designated SigE, with SigEa to SigEf used when distinguishing between them. The destruction detection signals are generally designated as SigF, and when distinguished, SigFa to SigFf are used.

[0044] The operation of the first power conversion device 10 of embodiment 1 in the event of a type 2 short circuit will be described. The slope detection unit 43 includes a resistor 51, a capacitor 52, and a comparator 53. The clamp circuit 42 includes a clamp voltage source 54 and a switch 55. The drive circuit unit 41 includes an on / off determination unit 57, a gate output circuit 58, and a gate resistor 59. The overcurrent detection unit 23 includes a comparator 61. The current detection circuit 22 includes an integration circuit that integrates the electromotive voltage VL generated in the inductor 21, and a multiplier that multiplies this integrated value by 1 / L.

[0045] In the slope detection unit 43, the resistor 51 and the capacitor 52 form a filter 50 for removing high-frequency noise components contained in the electromotive voltage VL of the inductor 21. One end of the capacitor 52 is connected to the first terminal A1 via a wire 71a, and one end of the resistor 51 is connected to the second terminal A2 via a wire 71b. The other end of the capacitor 52 and the other end of the resistor 51 are connected to wires 71c. The wire 71c is connected to the inverting input of the comparator 53, and a reference potential power supply 72 that outputs a voltage threshold Vref based on the reference potential Vs is connected to the non-inverting input of the comparator 53. The filter 50 is a low-pass filter, and its cutoff frequency is set to a level at which the electromotive voltage caused by the current slope of the main current during a type 2 short circuit, i.e., the slope of the main current over time, does not attenuate. Therefore, the electromotive voltage VL that has passed through the filter 50 is input to the inverting input of the comparator 53. The voltage threshold Vref is input to the non-inverting input of the comparator 53. The electromotive voltage VL is expressed by equation (1) where i is the current flowing through the inductor 21 of inductance L, and di / dt is the current slope Ski, which is the slope of the change in current i over time, i.e., the slope with respect to time. Note that the current slope Ski, which is the slope of the change in current i over time, is the current change rate. The current slope Ski is detected by the slope detection unit 43, so it can also be called the detected slope Skd. VL = L x di / dt = L x Ski (1)

[0046] Since the inductance L of the inductor 21 is a constant value, detecting the electromotive voltage VL of the inductor 21 can detect the gradient di / dt of the change in current i over time, i.e., the current gradient Ski, which is the gradient of current i. Here, the current i flowing through the inductor 21 is the emitter current Ie, which is the main current flowing through the emitter terminal E of the power semiconductor element 13. The emitter current Ie of the power semiconductor element 13 in the on-state is approximately equal to the collector current Ic, which is the main current flowing through the collector terminal C of the power semiconductor element 13. In other words, Ie≈Ic. Note that the comparator 53 shown in FIG. 4 is an example that compares the electromotive voltage VL with a voltage threshold Vref. The voltage threshold Vref compared with the electromotive voltage VL can be the inductance L × current gradient threshold Krefi or the inductance L × detection gradient threshold Kref. Since the electromotive voltage VL is the inductance L times the current slope Ski or the inductance L times the detection slope Skd, the comparator 53 compares the current slope Ski with the current slope threshold Krefi, and it can also be said that it compares the detection slope Skd with the detection slope threshold Kref.

[0047] The direction of the electromotive voltage VL is defined as the positive direction from the first terminal A1 to the second terminal A2. The direction of increase of the emitter current Ie and collector current Ic, which are the main currents, is defined as the positive direction from the first terminal A1 to the second terminal A2, similar to the electromotive voltage VL. When the main current increases, the direction of increase of the main current, i.e., the slope of the main current with respect to time, becomes positive. When the main current decreases, the direction of increase of the main current, i.e., the slope of the main current with respect to time, becomes negative. As shown in the voltage characteristic 86 of FIG. 6 , when the current characteristic 81 of the collector current Ic, which is the main current, changes positive, the electromotive voltage VL changes negatively and becomes a negative value. When the current characteristic 81 of the collector current Ic, which is the main current, changes negatively, the electromotive voltage VL changes positively and becomes a positive value. The voltage threshold Vref acts as a negative value on the comparator 53. Note that, in the voltage characteristic 86 of the electromotive voltage VL, the current slope Ski can be obtained by multiplying each value by 1 / L or dividing each value by L.

[0048] The slope detection unit 43 includes a comparator 53 that compares the absolute value of the detection voltage Vdet, which is the voltage of the inductor 21, i.e., the electromotive voltage VL, with the absolute value of the voltage threshold Vref, and outputs a slope determination signal Sg1 that indicates an excess detection when the absolute value of the detection voltage Vdet is greater than the absolute value of the voltage threshold Vref, and indicates no excess detection when the absolute value of the detection voltage Vdet is equal to or less than the absolute value of the voltage threshold Vref. The slope detection unit 43 can also be expressed as follows using the current slope Ski and the current slope threshold Krefi. The slope detection unit 43 includes a comparator 53 that compares the absolute value of the current slope Ski with the absolute value of the current slope threshold Krefi, and outputs a slope determination signal Sg1 that indicates an excess detection when the absolute value of the current slope Ski is greater than the absolute value of the current slope threshold Krefi, and indicates no excess detection when the absolute value of the current slope Ski is equal to or less than the absolute value of the current slope threshold Krefi.

[0049] As shown in equation (2), the voltage threshold Vref is set to a value greater than the electromotive voltage VL2 and less than the electromotive voltage VL1. VL1 > Vref > VL2 VL1 = L × disw / dtsw VL2 = L × Vinmax / Lp (2) where disw / dtsw is the maximum current gradient during normal switching, and Vinmax is the maximum voltage of the input voltage Vin applied to the arm during normal operation. Lp is the loop inductance between the capacitor 17 and the power semiconductor element 13 described above. As shown in FIG. 7, the loop inductances Lp1, Lp2, and Lp3 of the loop paths 91a, 91b, and 91c are the sum of the inductance of the wiring and the inductance L of the two inductors 21. Therefore, in the arm sections 20a and 20b including the power semiconductor elements 13a and 13b of the upper and lower arms 30a, the loop inductance Lp in equation (2) sets the voltage threshold Vref using loop inductance Lp1. Similarly, in the arm sections 20c and 20d including the power semiconductor elements 13c and 13d of the upper and lower arms 30b, the loop inductance Lp in equation (2) sets the voltage threshold Vref using loop inductance Lp2. In the arm sections 20e and 20f including the power semiconductor elements 13e and 13f of the upper and lower arms 30c, the loop inductance Lp in equation (2) sets the voltage threshold Vref using loop inductance Lp3. The loop inductance symbol Lp is used collectively, and Lp1, Lp2, and Lp3 are used when distinguishing between them. Note that the value of loop inductance Lp differs for each phase of the three-phase AC, but this description will not distinguish between them.

[0050] The electromotive voltage VL1 on the left side of equation (2) is the electromotive voltage VL when the power semiconductor element 13 of each arm is performing normal switching. The electromotive voltage VL2 on the right side of equation (2) is the electromotive voltage VL when a type 2 short circuit occurs. The electromotive voltages VL1, VL2, and voltage threshold Vref in equation (2) all have negative signs. Equation (2) can be expressed using the absolute values ​​of the electromotive voltages VL1, VL2, and voltage threshold Vref to obtain equation (3). |VL1| < |Vref| < |VL2| ... (3)

[0051] When the power conversion device 10 is operating normally, i.e., when the power semiconductor elements 13 of each arm are switching normally, the electromotive force VL does not fall below the voltage threshold Vref, so the comparator 53 outputs a digital value of 0, i.e., a low voltage. In the event of a Type 2 short circuit, due to a current increase caused by breakdown of the power semiconductor element 13 of the paired arm, the current slope becomes larger than the maximum current slope disw / dtsw of normal switching, determined by the characteristics of the power semiconductor element 13, and approaches a value obtained by dividing the maximum voltage Vinmax during normal operation by the loop inductance Lp. Therefore, in the event of a Type 2 short circuit, the electromotive force VL falls below the voltage threshold Vref between the start of the short circuit and the time when the collector current Ic, the main current, reaches its peak value, and the comparator 53 outputs a digital value of 1, i.e., a high voltage, instead of a digital value of 0. Where appropriate, the digital values ​​0 and 1 are simply referred to as digital values ​​0 and 1. A digital value of 0 for the slope determination signal Sg1 indicates no overshoot detection, and a digital value of 1 for the slope determination signal Sg1 indicates overshoot detection.

[0052] Here, if the inductance L of the inductor 21 includes a resistance component, the DC component of the detection voltage Vdet, which is the electromotive force VL, will be input to the slope detection unit 43, complicating the design of the voltage threshold Vref. Therefore, a differentiation circuit may be provided within the slope detection unit 43 to remove the DC component of the detection voltage Vdet that is due to the resistance component of the inductor 21 and the DC component of the main current.

[0053] The current detection circuit 22 integrates the electromotive voltage VL using an integrating circuit, and multiplies this integrated value by the reciprocal of the inductance L, i.e., 1 / L, using a multiplier to calculate the collector current Ic. The collector current Ic output from the current detection circuit 22 is input to the non-inverting input of a comparator 61 of the overcurrent detection unit 23. The overcurrent detection unit 23 includes the comparator 61 and a reference potential power supply 73 that outputs an overcurrent threshold Iref based on a reference potential Vs. The overcurrent threshold Iref is input to the inverting input of the comparator 61. If the maximum load current of the load current Im expected during normal operation of the power conversion device 10 is Immax and the saturation current of the power semiconductor element 13 is Is, the overcurrent threshold Iref is set within the range expressed by equation (4). Immax < Iref < Is (4)

[0054] During normal operation of the power conversion device 10, the collector current Ic is limited by the load current Im and never exceeds the overcurrent threshold Iref, so the comparator 61 outputs a digital value of 0, i.e., a low voltage. In the event of a Type 1, Type 2, or Type 3 arm short circuit, or a short circuit in load 2, i.e., a load short circuit, the collector current Ic exceeds the maximum load current Immax and rises to the saturation current Is. Therefore, the collector current Ic exceeds the overcurrent threshold Iref, and the comparator 61 outputs a digital value of 1, i.e., a high voltage, instead of a digital value of 0. When the output of the comparator 61 changes from a digital value of 0 to a digital value of 1, the overcurrent detection unit 23 detects that an overcurrent has flowed through the target arm 70 in the on-state, i.e., the power semiconductor element 13 being detected, and outputs an overcurrent detection signal SigE indicating the detection of an overcurrent. A digital value of 0 for the overcurrent detection signal SigE indicates that an overcurrent has not been detected, while a digital value of 1 for the overcurrent detection signal SigE indicates the detection of an overcurrent. The control circuit 16 can know from the overcurrent detection signal SigE indicating the detection of an overcurrent that a short circuit has occurred in the power semiconductor element 13 of the target arm 70 and that an overcurrent has flowed through the power semiconductor element 13 of the target arm 70.

[0055] In the overcurrent detection circuit 15 including the slope detection unit 43, the current detection circuit 22, and the overcurrent detection unit 23, the slope and current value of the collector current Ic are detected from the electromotive voltage VL of the inductor 21, which is the slope information output device 40, but this is not limited thereto. The overcurrent detection circuit 15 may use a shunt resistor, a current transformer, or the like, as long as it is configured to detect the slope and current value of the collector current Ic. More specifically, the slope information output device 40 may be a shunt resistor, a current transformer, or the like. When the slope information output device 40 is a shunt resistor, the shunt resistor is connected in parallel to the wiring connecting the upper and lower arms of the upper and lower arms 30a, 30b, and 30c so as to branch off a portion of the main current flowing through the wiring connecting the upper and lower arms. When the gradient information output device 40 is a current transformer, one end and the other end of the primary winding of the current transformer are connected to the first terminal A1 and the second terminal A2, respectively, and one end and the other end of the secondary winding of the current transformer are connected to one end of the capacitor 52 and one end of the resistor 51, respectively. Alternatively, a power semiconductor element 13 with current sensing may be used as the power semiconductor element 13, and the gradient detection unit 43 may detect the current gradient Ski based on a sense current output from the power semiconductor element 13 with current sensing. For example, the sense current may be converted into a voltage by a resistor, and this voltage may be used as a detection voltage Vdet, and the current gradient Ski may be detected using a differentiation circuit or the like. Alternatively, the gradient detection unit 43 may be configured to include the function of the overcurrent detection unit 23. For example, the gradient detection unit 43, the current detection circuit 22, and the overcurrent detection unit 23 may be modularized using an integrated circuit (IC) or the like. The current detection circuit 22 may be configured to receive the output of the capacitor 52 and resistor 51, which are the filter 50, instead of the electromotive voltage VL, i.e., the electromotive voltage VL after passing through the filter 50. In this case, the filter 50 is configured to be shared by the slope detection unit 43 and the overcurrent detection unit 23.

[0056] The control circuit 16 outputs an on / off signal Sig1 indicating an on command when turning on the power semiconductor element 13, and outputs an on / off signal Sig1 indicating an off command when turning off the power semiconductor element 13. For example, an on command is a high voltage with a digital value of 1, and an off command is a low voltage with a digital value of 0. The AND circuit 44 of the clamp control circuit 48 outputs an output signal Vk1 based on the slope determination signal Sg1 and the on / off signal Sig1. When the slope determination signal Sg1 output from the comparator 53 of the slope detection unit 43 is a high voltage with a digital value of 1 and the on / off signal Sig1 is a high voltage with a digital value of 1 indicating an on command (condition J1), the AND circuit 44 sets the output signal Vk1 to a high voltage with a digital value of 1. When condition J1 is not met, the AND circuit 44 sets the output signal Vk1 to a low voltage with a digital value of 0. The AND circuit 45 of the clamp control circuit 48 outputs an output signal Vk2 based on the output signal Vk1 and the overcurrent detection signal SigE. When the output signal Vk1 output from the AND circuit 44 is a high voltage with a digital value of 1 and the overcurrent detection signal SigE output from the comparator 61 of the overcurrent detection unit 23 is a high voltage with a digital value of 1 (condition J2), the AND circuit 45 sets the output signal Vk2 to a high voltage with a digital value of 1. When condition J2 is not met, the AND circuit 45 sets the output signal Vk2 to a low voltage with a digital value of 0.

[0057] When the output signal Vk2 of the AND circuit 45 becomes a high voltage with a digital value of 1, the one-shot circuit 46 outputs a high-voltage pulse signal with a digital value of 1 for a predetermined set time Ts. When the switch drive signal Vsw output from the one-shot circuit 46 is a high voltage with a digital value of 1, the switch 55 is turned on, and the gate-emitter voltage Vge is clamped to a clamp voltage Vcl. When the switch drive signal Vsw is a low voltage with a digital value of 0, the switch 55 is turned off, and the output of the clamp voltage Vcl between the gate drive wiring 28 and the emitter-connecting wiring 29 is stopped. That is, when the overcurrent detection signal SigE indicates an overcurrent detection (a high voltage with a digital value of 1), the clamp control circuit 48 controls the clamp circuit 42 to reduce the voltage of the drive signal Vout to the clamp voltage Vcl, and also controls the clamp circuit 42 to stop outputting the clamp voltage Vcl when a predetermined set time Ts has elapsed since the time when the overcurrent detection signal SigE indicated an overcurrent detection (detection time tx).

[0058] The set time Ts may be set to the time from when overcurrent detection is performed in the event of a Type 2 or Type 3 short circuit, i.e., from when the overcurrent detection signal SigE reaches a high voltage, until the collector current Ic reaches near its maximum. By setting the end time of the set time Ts, i.e., the clamp end time te, until the collector current Ic reaches near its maximum, it is possible to suppress a sudden change in the collector current Ic due to a drop in the gate-emitter voltage Vge after the collector current Ic reaches its maximum (see FIGS. 36 and 37). Note that the set time Ts is 1 μs or less for a typical IGBT.

[0059] Furthermore, the clamp control circuit 48 controls the clamp circuit 42 to stop outputting the clamp voltage Vcl if, after controlling the clamp circuit 42 to reduce the voltage of the drive signal Vout to the clamp voltage Vcl, the collector current Ic (main current) increases, i.e., the overcurrent detection signal SigE indicates an overcurrent detection, and a predetermined set time Ts has elapsed since the time (detection time tx) when the overcurrent detection signal SigE indicated an overcurrent detection, i.e., when the overcurrent of the main current is determined to be a Type II short circuit or a Type III short circuit. The clamp control circuit 48 controls the clamp circuit 42 not to stop outputting the clamp voltage Vcl if, after controlling the clamp circuit 42 to reduce the voltage of the drive signal Vout to the clamp voltage Vcl, the collector current Ic (main current) decreases and falls below the overcurrent threshold Iref, the overcurrent detection signal SigE changes from a high voltage to a low voltage, and the overcurrent detection signal SigE indicates no overcurrent detection, i.e., when the overcurrent of the main current is determined to be other than a Type II short circuit or a Type III short circuit.

[0060] Here, the change in the output of the one-shot circuit 46, i.e., the switch drive signal Vsw, from a low voltage to a high voltage indicates the occurrence of a type 2 short circuit or a type 3 short circuit, and it can be determined that the power semiconductor element 13 in the paired arm is broken. Therefore, by outputting the switch drive signal Vsw, which is the output of the one-shot circuit, to the control circuit 16 as a breakdown detection signal SigF, it is possible to notify a higher-level unit of the arm unit 20 that the paired arm is broken. In this way, for example, if the power conversion device 10 fails due to a type 2 short circuit or a type 3 short circuit, it is possible to identify the parts including the broken arm, thereby enabling rapid part replacement.

[0061] The breakdown detection signal SigF can be explained as follows. When the on / off signal Sig1 indicates an on command, the overcurrent detection signal SigE indicates an overcurrent detection, and the tilt determination signal Sg1 indicates an excess current detection (condition J3), the arm control circuit 14 outputs the breakdown detection signal SigF indicating that the power semiconductor element 13 of the paired arm has been broken, i.e., that breakdown has been detected. In cases other than condition J3, the arm control circuit 14 outputs the breakdown detection signal SigF indicating that the power semiconductor element 13 of the paired arm has not been broken, i.e., that breakdown has not been detected. The breakdown detection signal SigF indicating breakdown has been detected is a high voltage with a digital value of 1, and the breakdown detection signal SigF indicating breakdown has not been detected is a low voltage with a digital value of 0.

[0062] Note that when the switch drive signal Vsw from the one-shot circuit 46 is high, the clamp circuit 42 activates the switch 55 and reduces the gate-emitter voltage Vge to the clamp voltage Vcl using the clamp voltage source 54. However, the configuration of the clamp circuit 42 is not limited to this, and the clamp circuit 42 need only be able to reduce the gate-emitter voltage Vge to a value lower than the positive voltage Vp. For example, in the clamp circuit 42, the clamp voltage source 54 may be replaced with a resistor, and the voltage from the positive voltage Vp to the emitter terminal E may be divided by the resistor that replaced the gate resistor 59 to set the gate-emitter voltage Vge as the voltage, thereby reducing the gate-emitter voltage Vge when the clamp circuit 42 is operating. Furthermore, the clamp circuit 42 may be provided inside the drive circuit unit 41 rather than outside it. In other words, the drive circuit unit 41 may be configured to have the same function as the clamp circuit 42.

[0063] In the drive circuit unit 41, an on / off signal Sig1 and an overcurrent detection signal SigE are input to an on / off determination unit 57. The on / off determination unit 57 outputs an on / off signal Sig2 based on the on / off signal Sig1 and the overcurrent detection signal SigE. When the overcurrent detection signal SigE is at a low voltage, i.e., when the overcurrent detection signal SigE indicates that an overcurrent has not been detected, the on / off determination unit 57 outputs the on / off signal Sig1 as the on / off signal Sig2. When the on / off signals Sig1 and Sig2 indicate an on command, the drive signal Vout becomes a positive voltage Vp, and the power semiconductor element 13 is in an on state. When the on / off signals Sig1 and Sig2 indicate an off command, the drive signal Vout becomes a negative voltage Vn, and the power semiconductor element 13 is in an off state. The on / off signals Sig1 and Sig2 indicating an on command are a high voltage with a digital value of 1, and the on / off signals Sig1 and Sig2 indicating an off command are a low voltage with a digital value of 0. If the overcurrent detection signal SigE changes from a low voltage to a high voltage while the on / off signals Sig1 and Sig2 are in an on command state, the on / off determination unit 57 changes the on / off signal Sig2 to an off command after a predetermined delay time Td, and reduces the output voltage of the gate output circuit 58 from a positive voltage Vp to a negative voltage Vn.

[0064] The delay time Td is set so that the on / off signal Sig2 changes from an on command to an off command after the sudden decrease in collector current Ic due to a Type 2 or Type 3 short circuit has ceased, i.e., after time tB (see FIG. 6 ). When the power semiconductor element 13 is a typical IGBT, the delay time Td may be set to 2 μs or more. Furthermore, if the on / off signal Sig1 changes from an on command to an off command during the delay time Td, and the on / off signal Sig2 changes to an off command and the gate-emitter voltage Vge changes to a negative voltage Vn, the overcurrent in the target arm 70 due to a Type 2 or Type 3 short circuit is interrupted, which may result in overvoltage breakdown of the target arm 70. Therefore, during the delay time Td, even if the on / off signal Sig1 changes from an on command to an off command, the on / off determination unit 57 prevents the on / off signal Sig2 from changing to an off command, i.e., maintains the on command.

[0065] When the on / off signal Sig2 is set to an off command when the overcurrent detection signal SigE changes from not detecting an overcurrent to detecting an overcurrent, turning the target arm 70 off using the same means as in a normal turn-off operation, i.e., the gate output circuit 58 and the gate resistor 59, may result in an overvoltage in the target arm 70. Therefore, when the on / off signal Sig2 is set to an off command when the overcurrent detection signal SigE changes from not detecting an overcurrent to detecting an overcurrent, for example, a soft shutoff circuit may be operated by switching an off-gate resistor before turning the target arm 70 off, or the clamp circuit 42 may be operated so that the gate-emitter voltage Vge is maintained at the clamp voltage Vcl for a certain period of time.

[0066] Next, the operation of the arm unit 20 of the first embodiment in the event of a type 2 short circuit will be described with reference to Figure 6. Figure 6 shows current characteristics 81 of the collector current Ic, voltage characteristics 82 of the collector-emitter voltage Vce, voltage characteristics 83 of the gate-emitter voltage Vge, signal characteristics 84a of the on-off signal Sig1, signal characteristics 84b of the on-off signal Sig2, signal characteristics 85 of the overcurrent detection signal SigE, voltage characteristics 86 of the electromotive voltage VL of the inductor 21, signal characteristics 87 of the output signal Vk1, and signal characteristics 88 of the breakdown detection signal SigF and the switch drive signal Vsw. In Figure 6, the horizontal axis represents time [s], and the vertical axis of the collector current Ic represents current [A]. The vertical axes of the collector-emitter voltage Vce, gate-emitter voltage Vge, on-off signals Sig1 and Sig2, overcurrent detection signal SigE, electromotive voltage VL, output signal Vk1, breakdown detection signal SigF, and switch drive signal Vsw each represent voltage [V]. For simplicity of explanation, the electromotive voltage VL waveform is assumed to be directly input to the inverting input of comparator 53 without filter 50.

[0067] From the time at the left end to time t0, the power semiconductor element 13 that is the target arm 70 of the arm unit 20 is in the ON state, and the power semiconductor element 13 of the counter arm is in the OFF state. As described above, for example, when the target arm 70 is in the arm unit 20a, the power semiconductor element 13 of the counter arm is the power semiconductor element 13 of the arm unit 20b. From the time at the left end to time t0, the gate-emitter voltage Vge is a positive voltage Vp, and the collector current Ic is a load current Im. Note that the notation of Im (see FIG. 34) is omitted in FIG. 6. From the time at the left end to time t0, the signals of the arm unit 20 shown in FIG. 6 are as follows: The on / off signals Sig1 and Sig2 are high voltages with a digital value of 1, the overcurrent detection signal SigE is a low voltage with a digital value of 0, the electromotive voltage VL is zero, the output signal Vk1 is a low voltage with a digital value of 0, and the breakdown detection signal SigF and the switch drive signal Vsw are low voltages with a digital value of 0.

[0068] At time t0, while the power semiconductor element 13 of the target arm 70 is in the on state and the collector current Ic is flowing, the power semiconductor element 13 of the opposing arm breaks down for some reason, resulting in a type 2 short circuit. After time t0, the collector current Ic rises (increases), the positive slope of the current becomes larger, and accordingly the electromotive voltage VL of the inductor 21 rises in the negative direction, i.e., the absolute value becomes negative and increases.

[0069] At time t1, when the electromotive voltage VL drops below the voltage threshold Vref, the tilt determination signal Sg1 output from the comparator 53 of the tilt detection unit 43 changes from a low voltage to a high voltage. At the inputs of the AND circuit 44 of the clamp control circuit 48, the on / off signal Sig1 is at a high voltage, and the tilt determination signal Sg1 is at a high voltage, so the output signal Vk1 changes from a low voltage to a high voltage.

[0070] At time t2, when the collector current Ic exceeds the overcurrent threshold Iref, the overcurrent detection signal SigE, which is the output of the comparator 61 of the overcurrent detection unit 23, changes from a low voltage to a high voltage. This overcurrent detection signal SigE, indicating the detection of an overcurrent, is input to the on / off determination unit 57 of the drive circuit unit 41, the control circuit 16, and the AND circuit 45 of the clamp control circuit 48. At time t6, which is a delay time Td after time t2, the on / off determination unit 57 of the drive circuit unit 41 changes the on / off signal Sig2 from a high voltage to a low voltage. Time t2 is the time when the overcurrent detection unit 23 of the overcurrent detection circuit 15 detects the collector current Ic, i.e., an overcurrent in the main current, and outputs the overcurrent detection signal SigE indicating the detection of an overcurrent, and is therefore the overcurrent detection time tx. Time t6 is the end time ty of the delay time Td. From time t2 to time t6, the arm control circuit 14 outputs a drive signal Vout that maintains the power semiconductor element 13 of the target arm 70 in an on state for a predetermined delay time Td from the detection time tx when the overcurrent detection signal SigE indicates an overcurrent detection.

[0071] Also, at time t2, both inputs of AND circuit 45 of clamp control circuit 48 become high voltage, so that output signal Vk2, which is the output of AND circuit 45, changes from low voltage to high voltage, and one-shot circuit 46 outputs switch drive signal Vsw, a pulse signal that remains at a high voltage for set time Ts. The high-voltage switch drive signal Vsw turns on switch 55 of clamp circuit 42, and gate-emitter voltage Vge begins to decrease to clamp voltage Vcl. As gate-emitter voltage Vge begins to decrease, a sudden rise in collector current Ic is suppressed, and current stress on power semiconductor element 13 is reduced.

[0072] At time t3, the output of the one-shot circuit 46 has passed the set time Ts, so the switch drive signal Vsw changes from a high voltage to a low voltage, and the switch 55 of the clamp circuit 42 changes from an on state to an off state. As a result, the gate-emitter voltage Vge begins to rise from the clamp voltage Vcl to a positive voltage Vp. The set time Ts is the clamp time Tc during which the gate-emitter voltage Vge is limited to the clamp voltage Vcl. Time t2 is the detection time tx and also the clamp start time. Time t3 is the end time of the clamp time Tc, i.e., the clamp end time te.

[0073] The clamp control circuit 48 controls the clamp circuit 42 to stop outputting the clamp voltage Vcl when a set time Ts has elapsed since the detection time tx, which is the time when the overcurrent detection signal SigE indicates an overcurrent detection, after the voltage of the drive signal Vout is limited to the clamp voltage Vcl. The set time Ts is set to be shorter than the current increase time Tm, which is the time from the detection time tx, which is the time when the overcurrent detection signal SigE indicates an overcurrent detection, until the collector current Ic, which is the main current including the overcurrent flowing through the target arm 70, reaches its maximum value. In FIG. 6 , the start time of the current increase time Tm is time t2 (detection time tx), and the end time of the current increase time Tm is time t4. The start time of the set time Ts and the start time of the current increase time Tm are the same, but the clamp end time te (time t3), which is the end time of the set time Ts, is set to be shorter than the end time t4, which is the time when the current increase time Tm ends.

[0074] At time t4, the collector current Ic reaches a peak value and then begins to decrease. After time t4, the collector-emitter voltage Vce begins to rise rapidly. The gate-emitter voltage Vge decreases from the positive voltage Vp from time t4 to time t5, reaches a minimum value at time t5, and then increases back to the positive voltage Vp. Unlike FIG. 37 , in which the gate-emitter voltage Vge decreases from the clamp voltage Vcl, in power conversion device 10 of embodiment 1, the gate-emitter voltage Vge decreases from the positive voltage Vp but does not decrease below the clamp voltage Vcl. This makes it possible to suppress a rapid decrease in collector current Ic, and to suppress the collector-emitter voltage Vce to within the element breakdown voltage Vbr of power semiconductor element 13.

[0075] 6, the clamp end time te of the clamp time Tc during which the gate-emitter voltage Vge is limited to the clamp voltage Vcl is time t3. This clamp end time te is set to a time before time t4, the time at which the collector current Ic reaches its maximum value and the time at which the collector-emitter voltage Vce begins to rise sharply. Since power conversion device 10 of embodiment 1 increases the gate-emitter voltage Vge from the clamp voltage Vcl at a time before the collector-emitter voltage Vce begins to rise sharply, it is possible to prevent an overvoltage that exceeds the element breakdown voltage Vbr shown in FIG.

[0076] At time t6, the delay time Td ends, and the on / off signal Sig2 changes from high to low as indicated by signal characteristic 84b, causing the gate-emitter voltage Vge to start decreasing. Thereafter, the power semiconductor device 13 of the target arm 70 turns off, and the collector current Ic is cut off, i.e., becomes zero.

[0077] The end time ty of the delay time Td shown in FIG. 6 is set as follows. The end time ty of the delay time Td is the time after time tB when the detected voltage Vdet, i.e., the electromotive voltage VL, passes through zero after the detection time tx and the absolute value of the detected voltage Vdet (electromotive voltage VL) drops from its maximum value. The gradient (dIc / dt) of the change in time of the collector current Ic, which is the main current, i.e., the current slope Ski, is reflected in the value of the electromotive voltage VL. Time tC shown in FIG. 6 is the time when the positive gradient, i.e., the positive rate of change, of the collector current Ic is at its maximum. Note that the period during which the positive rate of change of the collector current Ic is at its maximum is the period from time t2 to time t3, when the electromotive voltage VL is negative and approximately constant. Time tC is displayed as the midpoint of this period, representing the period during which the positive rate of change of the collector current Ic is at its maximum. The period T1 from time tA to time tB is the period after time t4, when the collector current Ic reaches its maximum, during which the electromotive force VL remains substantially constant at a positive value, and during which the negative rate of change of the collector current Ic is at its maximum. Time tD is the time when the negative slope of the collector current Ic, i.e., the negative rate of change, is at its maximum. This time is shown as the midpoint of this period T1, representing the maximum negative rate of change of the collector current Ic. The period T2 from time tB to the end time ty of the delay time Td is the period from time tB until the collector current Ic resumes its negative slope. From time tB, the electromotive force VL decreases from its maximum positive value, passes through zero, becomes a constant negative value whose absolute value is smaller than the voltage threshold Vref, and then changes to a positive value at time t6. The rate of change of the collector current Ic from time tB to time t6, i.e., the current slope Ski, is reflected in the value of the electromotive force VL and can be expressed as follows: From time tB, the negative rate of change of the collector current Ic decreases from its maximum, and after reaching its minimum value, the rate of change reverses to a positive rate, increasing at a constant positive rate, and at time t6, the rate of change reverses to a negative rate. The end time ty of the delay time Td can be expressed as follows using the rate of change of the main current: The end time ty of the delay time Td is a time that is later than time tB when the negative rate of change of the main current collector current Ic decreases from its maximum, after time t4 when the main current collector current Ic reaches its maximum value.

[0078] The operation of the arm section 20 of embodiment 1 in the event of a Type 2 short circuit has been described using FIG. 6 . As described above, a Type 3 short circuit differs from a Type 2 short circuit in that a pair of elements in the off state suddenly breaks down and shorts out while the diode connected in antiparallel to the element is conducting. However, like a Type 2 short circuit, a Type 3 short circuit occurs when the element itself is in the on state. In the case of a Type 3 short circuit, during the first short period of time after the element changes from the off state to the on state (not shown in FIG. 6 ), the collector current Ic and the collector-emitter voltage Vce differ from those in a Type 2 short circuit, but the waveforms shown in FIG. 6 remain the same even in the event of a Type 3 short circuit. Therefore, the operation of the arm section 20 of embodiment 1 in the event of a Type 3 short circuit is the same as the operation of the arm section 20 of embodiment 1 in the event of a Type 2 short circuit.

[0079] As described above, it can be seen that the power conversion device 10 of embodiment 1 can prevent overvoltage breakdown due to a type 2 short circuit or a type 3 short circuit, and can reliably prevent secondary breakdown of the power semiconductor elements 13. Furthermore, the power conversion device 10 of embodiment 1 can notify that the paired arm in the arm unit 20 paired with the arm unit 20 from which the breakdown detection signal SigF indicating breakdown detection is output is broken by transmitting the breakdown detection signal SigF indicating breakdown detection to a higher level of the arm unit 20, such as the control circuit 16. Therefore, the power conversion device 10 of embodiment 1 can identify parts including the broken arm when the power conversion device 10 fails due to a type 2 short circuit or a type 3 short circuit, for example, and can quickly replace the parts.

[0080] In the present embodiment, an example has been shown in which the operation of the clamp circuit 42 is determined by a clamp control circuit 48 including an AND circuit 44, an AND circuit 45, and a one-shot circuit 46, and the voltage of the drive signal Vout output from the drive circuit unit 41 is changed in response to the operation of the clamp circuit 42. However, the configuration for changing the voltage of the drive signal Vout when a Type 2 short circuit or a Type 3 short circuit is detected is not limited to this. The configuration for changing the voltage of the drive signal Vout when a Type 2 short circuit or a Type 3 short circuit is detected may be configured to operate such that the gate-emitter voltage Vge is higher than the clamp voltage Vcl during the period in which the collector current Ic rapidly falls from its peak, as shown in FIG. 37, when a Type 2 short circuit or a Type 3 short circuit occurs. For example, an operation similar to that of the clamp control circuit 48 including the AND circuit 44, the AND circuit 45, and the one-shot circuit 46 may be incorporated into an FPGA (Field-Programmable Gate Array) or a microcontroller. Furthermore, when the drive circuit unit 41 is configured as a gate drive IC that outputs the drive signal Vout to the gate terminal of the power semiconductor element 13, the function of the clamp control circuit 48 may be added to the drive circuit unit 41, and the drive circuit unit 41 may be configured to control the output of the drive signal Vout, including the operation of the clamp control circuit 48. Since the microcomputer includes a processor 98 and a memory 99 shown in FIG. 33, the function of the clamp control circuit 48 is realized by the processor 98 executing a program stored in the memory 99.

[0081] Although the protective operation in the event of a Type 1 short circuit has not been described in detail, the clamp circuit 42 may also be used in the event of a Type 1 short circuit, and other functions may be used in combination.

[0082] The first power conversion device 10 of embodiment 1 shown in FIG. 1 shows an example in which the overcurrent detection circuit 15 is provided in the arm control circuit 14 of each arm section 20. However, as in the fourth power conversion device 10 of embodiment 1 shown in FIGS. 10 and 11 , the overcurrent detection circuit 15 may be provided in the negative side wiring 36, and the overcurrent detection of the main current may be performed collectively by the single overcurrent detection circuit 15.

[0083] The fourth power conversion device 10 of the first embodiment differs from the first power conversion device 10 of the first embodiment in that the arm control circuit 14 includes a drive circuit unit 41, a clamp circuit 42, and a clamp control circuit 48, and an overcurrent detection circuit 15 is provided that detects an overcurrent flowing in an upper arm or a lower arm in an on state based on a detection voltage Vdet that is the voltage of an inductor 21 that is a gradient information output device 40 connected to a negative side wiring 36, i.e., a current gradient Ski that is the gradient with time of a current flowing in a negative side wiring 36 connected opposite to the upper arm of the plurality of lower arms, and outputs an overcurrent detection signal SigE indicating the detection of an overcurrent. The following mainly describes the parts that are different from the first power conversion device 10 of the first embodiment.

[0084] In the fourth power conversion device 10 of the first embodiment, a single overcurrent detection circuit 15 detects overcurrents in the power semiconductor elements 13 in the multiple upper and lower arms 30a, 30b, and 30c included in the power conversion unit 12, and outputs an overcurrent detection signal SigE and a tilt determination signal Sg1. The overcurrent detection signal SigE and the tilt determination signal Sg1 output from the overcurrent detection circuit 15 are input to all of the arm units 20a to 20f. In each arm unit 20, as shown in FIG. 11 , the arm control circuit 14 includes the power semiconductor elements 13 of the target arm 70, a drive circuit unit 41, a clamp circuit 42, and a clamp control circuit 48. The clamp control circuit 48 receives the on / off signal Sig1 output from the control circuit 16 and the overcurrent detection signal SigE and the tilt determination signal Sg1 output from the overcurrent detection circuit 15. The operation of the clamp control circuit 48 in the fourth power conversion device 10 of the first embodiment is the same as the operation of the clamp control circuit 48 in the first power conversion device 10 of the first embodiment. In the fourth power conversion device 10 of the first embodiment, even if an arm unit 20 is not provided with an overcurrent detection circuit 15, the clamp circuit 42 of the arm unit 20 can be controlled by the overcurrent detection circuit 15 commonly provided in the negative side wiring 36 and the clamp control circuit 48 of each arm unit 20. Therefore, similar to the first power conversion device 10 of the first embodiment, the fourth power conversion device 10 of the first embodiment can reliably prevent overvoltage breakdown of the power semiconductor elements 13a to 13f due to a type 2 short circuit or a type 3 short circuit.

[0085] Furthermore, the fourth power conversion device 10 of embodiment 1 outputs a destruction detection signal SigF from each arm section 20, similar to the first power conversion device 10 of embodiment 1, and therefore achieves the same effect as the first power conversion device 10 of embodiment 1.

[0086] Although the power semiconductor element 13 has been described as an IGBT and a diode connected in anti-parallel to the IGBT, this is not a limitation. The transistor Tr of the power semiconductor element 13 may function as a switching element. The transistor Tr of the power semiconductor element 13 may be a metal-oxide-semiconductor field-effect transistor (MOSFET), etc. In the case where the transistor Tr of the power semiconductor element 13 is a MOSFET, the collector terminal and the emitter terminal are replaced with the drain terminal and the source terminal, respectively. Furthermore, the number of parallel upper and lower arms is not limited to three, but may be two, six, etc. Two or more power semiconductor elements 13 in each arm may be connected in series or in parallel. Furthermore, the configuration of the power conversion device 10, the configuration of the power source 1, and the configuration and number of the load 2 are not limited, and any power conversion device in which an upper arm and a lower arm are connected in series may be applicable.

[0087] 1 and 10 show an example of a power conversion device 10 in which the power source 1 is a three-phase AC power source 18 and the load 2 is a three-phase AC load 19. The three-phase AC load 19 is, for example, a three-phase motor. The power conversion device 10 shown in FIG. 1 can be widely used as a power conversion device for home appliances such as air conditioners and refrigerators, electric vehicles, industrial equipment, etc.

[0088] The functions of the control circuit 16 and the on / off determination unit 57 may be realized by a processor 98 and a memory 99 shown in Fig. 33. Fig. 33 is a diagram showing an example of a hardware configuration in which the functions of the control circuit and the on / off determination unit are realized by digital calculations. In this case, the control circuit 16 and the on / off determination unit 57 are realized by the processor 98 executing a program stored in the memory 99. Furthermore, a plurality of processors 98 and a plurality of memories 99 may cooperate to execute each function.

[0089] The power semiconductor element 13 may be a silicon semiconductor element formed using silicon, or a wide-bandgap semiconductor element formed using a wide-bandgap semiconductor material with a wider bandgap than silicon. Examples of wide-bandgap semiconductor materials include silicon carbide (SiC), gallium nitride-based materials including gallium nitride (GaN), and diamond. When the power semiconductor element 13 is a semiconductor element formed using a wide-bandgap semiconductor material, i.e., a wide-bandgap semiconductor element, it has a faster switching speed and lower switching loss than a silicon semiconductor element. Furthermore, wide-bandgap semiconductor elements have higher voltage resistance and heat resistance than silicon semiconductor elements. Therefore, when the power semiconductor element 13 is a wide-bandgap semiconductor element, the heat sink or other cooler for the power semiconductor element 13 can be made smaller, and may even be unnecessary.

[0090] As described above, the power conversion device 10 of the first embodiment is a power conversion device that outputs output power Po obtained by power conversion of input power Pi by a power conversion unit 12 having a plurality of power semiconductor elements 13 a to 13 f. The power conversion unit 12 includes a plurality of upper and lower arms 30 a, 30 b, 30 c in which an upper arm having power semiconductor elements 13 a, 13 c, 13 e and a lower arm having power semiconductor elements 13 b, 13 d, 13 f controlled so as not to be turned on simultaneously with the upper arm are connected in series, and a plurality of arm control circuits 14 that control the upper arm and the lower arm, respectively. The arm control circuit 14 includes a drive circuit unit 41 that outputs a drive signal Vout to drive a target arm 70, which is the upper arm or lower arm to be controlled, an overcurrent detection circuit 15 that detects an overcurrent flowing through the target arm 70 in the ON state based on a current slope Ski, which is the slope with respect to time of the main current (collector current Ic) flowing through the target arm 70, and outputs an overcurrent detection signal SigE indicating the detection of an overcurrent, a clamp circuit 42 that limits the voltage of the drive signal Vout to a clamp voltage Vcl, and a clamp control circuit 48 that controls the clamp circuit 42. The clamp control circuit 48 controls the clamp circuit 42 to reduce the voltage of the drive signal Vout to the clamp voltage Vcl when the overcurrent detection signal SigE indicates the detection of an overcurrent, and controls the clamp circuit 42 to stop outputting the clamp voltage Vcl when a predetermined set time Ts has elapsed since the time (detection time tx) when the overcurrent detection signal SigE indicates the detection of an overcurrent. After the output of the clamp voltage Vcl is stopped, the drive circuit unit 41 changes the voltage of the drive signal Vout to change the target arm 70 from the ON state to the OFF state.With this configuration, the power conversion device 10 of embodiment 1 is equipped with an overcurrent detection circuit 15 that detects that an overcurrent has flowed through the target arm 70, a clamp circuit 42 that limits the voltage of the drive signal Vout to the clamp voltage Vcl, and a clamp control circuit 48 that reduces the voltage of the drive signal Vout to the clamp voltage Vcl when the overcurrent detection signal SigE indicates an overcurrent detection, and controls the clamp circuit 42 to stop outputting the clamp voltage Vcl when a predetermined set time Ts has elapsed from the time (detection time tx) when the overcurrent detection signal SigE indicates an overcurrent detection. Therefore, it is possible to reliably prevent overvoltage breakdown of the power semiconductor elements 13a to 13f due to a Type 2 short circuit or a Type 3 short circuit.

[0091] Another power conversion device 10 according to the first embodiment is a power conversion device that outputs output power Po by converting input power Pi using a power conversion unit 12 having a plurality of power semiconductor elements 13a to 13f. The power conversion unit 12 includes a plurality of upper and lower arms 30a, 30b, and 30c, each of which is connected in series with an upper arm having power semiconductor elements 13a, 13c, and 13e, and a lower arm having power semiconductor elements 13b, 13d, and 13f that are controlled so as not to be turned on simultaneously with the upper arm. The power conversion device 10 also includes an overcurrent detection circuit 15 that detects an overcurrent flowing through an on-state upper arm or lower arm based on a current slope Ski, which is the slope with time of a current flowing through a negative wiring 36 connected opposite the upper arm among the plurality of lower arms, and outputs an overcurrent detection signal SigE indicating the detection of an overcurrent. The arm control circuit 14 includes a drive circuit unit 41 that outputs a drive signal Vout to drive a target arm 70, which is the upper arm or lower arm to be controlled, a clamp circuit 42 that limits the voltage of the drive signal Vout to a clamp voltage Vcl, and a clamp control circuit 48 that controls the clamp circuit 42. When the overcurrent detection signal SigE indicates an overcurrent detection, the clamp control circuit 48 controls the clamp circuit 42 to reduce the voltage of the drive signal Vout to the clamp voltage Vcl, and controls the clamp circuit 42 to stop outputting the clamp voltage Vcl when a predetermined set time Ts has elapsed since the time (detection time tx) when the overcurrent detection signal SigE indicates an overcurrent detection. After the output of the clamp voltage Vcl is stopped, the drive circuit unit 41 changes the voltage of the drive signal Vout to change the target arm 70 from an ON state to an OFF state.With this configuration, the other power conversion device 10 of embodiment 1 includes an overcurrent detection circuit 15 that detects that an overcurrent has flowed in the target arm 70, a clamp circuit 42 that limits the voltage of the drive signal Vout to the clamp voltage Vcl, and a clamp control circuit 48 that reduces the voltage of the drive signal Vout to the clamp voltage Vcl when the overcurrent detection signal SigE indicates an overcurrent detection, and controls the clamp circuit 42 to stop outputting the clamp voltage Vcl when a predetermined set time Ts has elapsed from the time (detection time tx) when the overcurrent detection signal SigE indicates an overcurrent detection. Therefore, it is possible to reliably prevent overvoltage breakdown of the power semiconductor elements 13a to 13f due to a Type 2 short circuit or a Type 3 short circuit.

[0092] Second Embodiment. FIG. 12 is a diagram showing the configuration of an arm unit according to a second embodiment, and FIG. 13 is a timing chart illustrating the operation of the arm unit according to the second embodiment. In the power conversion device 10 of the first embodiment, the switch 55 of the clamp circuit 42 is turned on, and the clamp end time te of the clamp time Tc, during which the gate-emitter voltage Vge is limited to the clamp voltage Vcl, is determined by the set time Ts of the one-shot circuit 46. In the second embodiment, an example is described in which the one-shot circuit 46 is not provided, and the clamp end time te of the clamp time Tc is determined by the slope determination signal Sg1 of the overcurrent detection circuit 15. The power conversion device 10 of the second embodiment is configured in such a way that the clamp end time te of the clamp time Tc is determined by the slope determination signal Sg1. Therefore, even if the timing at which an overvoltage occurs in a Type 2 short circuit or a Type 3 short circuit changes due to external factors such as deterioration of the power semiconductor element 13 or the capacitor 17 or a partial disconnection of the wiring pattern, it is possible to reliably prevent an overvoltage and prevent secondary breakdown. The power conversion device 10 of the second embodiment differs from the power conversion device 10 of the first embodiment in that the clamp end time te of the clamp time Tc is determined by the slope determination signal Sg1 of the overcurrent detection circuit 15, without using the set time Ts of the one-shot circuit 46. The following mainly describes the parts that are different from the power conversion device 10 of the first embodiment.

[0093] The overall configuration of the power conversion device 10 of the second embodiment is the same as that of the first embodiment, but the internal configuration of the arm unit 20 is different. The one-shot circuit 46 is eliminated from the arm unit 20 of the second embodiment. The clamp control circuit 48 includes AND circuits 44 and 45. The input / output of the AND circuit 44 and the input of the AND circuit 45 are configured the same as those of the first embodiment. The AND circuit 45 outputs an output signal Vk2. The clamp control circuit 48 outputs the output signal Vk2 as a switch drive signal Vsw and a breakdown detection signal SigF.

[0094] In the power conversion device 10 of the first embodiment, the clamp control circuit 48 controls the clamp circuit 42 to reduce the voltage of the drive signal Vout to the clamp voltage Vcl when the overcurrent detection signal SigE indicates an overcurrent detection, and controls the clamp circuit 42 to stop outputting the clamp voltage Vcl when a predetermined set time Ts has elapsed since the time (detection time tx) when the overcurrent detection signal SigE indicates an overcurrent detection. The power conversion device 10 of the second embodiment differs from the power conversion device 10 of the first embodiment in the operation of stopping the output of the clamp voltage Vcl. In the power conversion device 10 of the second embodiment, the clamp control circuit 48 controls the clamp circuit 42 to reduce the voltage of the drive signal Vout to the clamp voltage Vcl when the overcurrent detection signal SigE indicates an overcurrent detection, and controls the clamp circuit 42 to stop outputting the clamp voltage Vcl when a predetermined set condition is satisfied based on the current slope Ski. The set condition is satisfied when, after the voltage of the drive signal Vout is limited to the clamp voltage Vcl, the current slope Ski associated with the overcurrent flowing through the target arm 70 passes a predetermined current slope threshold Krefi. The operation of the clamp control circuit 48 can be expressed as follows using the detection voltage Vdet. When the overcurrent detection signal SigE indicates an overcurrent detection, the clamp control circuit 48 controls the clamp circuit 42 to reduce the voltage of the drive signal Vout to the clamp voltage Vcl, and also controls the clamp circuit 42 to stop outputting the clamp voltage Vcl when a predetermined set condition is satisfied based on the detection voltage Vdet associated with the overcurrent flowing through the target arm 70. The set condition is satisfied when, after the voltage of the drive signal Vout is limited to the clamp voltage Vcl, the detection voltage Vdet associated with the overcurrent flowing through the target arm 70 passes a predetermined voltage threshold Vref.

[0095] Next, the operation of the arm section 20 of the second embodiment in the event of a Type 2 short circuit will be described with reference to Figure 13. Figure 13 shows current characteristics 81 of the collector current Ic, voltage characteristics 82 of the collector-emitter voltage Vce, voltage characteristics 83 of the gate-emitter voltage Vge, signal characteristics 84a of the on-off signal Sig1, signal characteristics 84b of the on-off signal Sig2, signal characteristics 85 of the overcurrent detection signal SigE, voltage characteristics 86 of the electromotive voltage VL of the inductor 21, signal characteristics 87 of the output signal Vk1, and signal characteristics 88 of the breakdown detection signal SigF and the switch drive signal Vsw. In Figure 13, the horizontal axis represents time [s], and the vertical axis of the collector current Ic represents current [A]. The vertical axes of the collector-emitter voltage Vce, gate-emitter voltage Vge, on-off signals Sig1 and Sig2, overcurrent detection signal SigE, electromotive voltage VL, output signal Vk1, breakdown detection signal SigF, and switch drive signal Vsw each represent voltage [V]. For simplicity of explanation, the electromotive voltage VL waveform is assumed to be directly input to the inverting input of comparator 53 without filter 50.

[0096] FIG. 13 of the second embodiment differs from FIG. 6 of the first embodiment in the voltage characteristic 86 of the electromotive voltage VL and the signal characteristic 87 of the output signal Vk1 around time t3. In FIG. 13 of the second embodiment, the electromotive voltage VL passes through the voltage threshold Vref at time t3 and becomes greater than the voltage threshold Vref. When the electromotive voltage VL becomes greater than the voltage threshold Vref, the tilt determination signal Sg1 of the tilt detection unit 43 changes from a low voltage to a high voltage, and the output signal Vk1 of the AND circuit 44 changes from a high voltage to a low voltage. The output signal Vk2 of the AND circuit 45 changes from a high voltage to a low voltage due to the low-voltage output signal Vk1. Because the output signal Vk2 is output as the switch drive signal Vsw and the breakdown detection signal SigF, the switch drive signal Vsw and the breakdown detection signal SigF change from a high voltage to a low voltage at time t3. Like the tilt detector 43 of the first embodiment, the tilt detector 43 of the second embodiment adjusts the voltage threshold Vref to set the rise timing, pulse width, and fall timing of the tilt determination signal Sg1. However, because the arm control circuit 14 of the second embodiment does not include the one-shot circuit 46, the rise timing, pulse width, and fall timing of the switch drive signal Vsw and the breakdown detection signal SigF when the on / off signal Sig1 is at a high voltage are determined by the overcurrent detection signal SigE and the tilt determination signal Sg1. The rise timing of the switch drive signal Vsw and the breakdown detection signal SigF is determined by the rise timing of the overcurrent detection signal SigE, and the fall timing of the switch drive signal Vsw and the breakdown detection signal SigF is determined by the fall timing of the tilt determination signal Sg1.

[0097] The overcurrent detection circuit 15 of the second embodiment is the same as that of the first embodiment, and includes a slope detection unit 43 that compares the absolute value of the detection voltage Vdet, which is the voltage of the inductor 21, i.e., the electromotive voltage VL, with the absolute value of the voltage threshold Vref, and outputs a slope determination signal Sg1 indicating an overcurrent has been detected if the absolute value of the detection voltage Vdet is greater than the absolute value of the voltage threshold Vref, and indicating no overcurrent has been detected if the absolute value of the detection voltage Vdet is equal to or less than the absolute value of the voltage threshold Vref. The overcurrent detection circuit 15 of the second embodiment also includes a slope detection unit 43 that compares the absolute value of the current slope Ski with the absolute value of the current slope threshold Krefi, and outputs a slope determination signal Sg1 indicating an overcurrent has been detected if the absolute value of the current slope Ski is greater than the absolute value of the current slope threshold Krefi, and indicating no overcurrent has been detected if the absolute value of the current slope Ski is equal to or less than the absolute value of the current slope threshold Krefi. After limiting the voltage of the drive signal Vout to the clamp voltage Vcl, the clamp control circuit 48 controls the clamp circuit 42 to stop outputting the clamp voltage Vcl based on the slope determination signal Sg1 indicating non-detection of excess output from the slope detection unit 43. Here, the above-mentioned setting conditions are satisfied when the slope determination signal Sg1 output from the slope detection unit 43 indicates non-detection of excess after limiting the voltage of the drive signal Vout to the clamp voltage Vcl.

[0098] 13 is the same as the period from the left end to time t2 in FIG. 6, but the operation of the clamp control circuit 48 is different. At time t0, the power semiconductor element 13 of the own arm, i.e., the target arm 70, is in the on state and the collector current Ic is flowing, and the power semiconductor element 13 of the opposing arm breaks down for some reason, resulting in a type 2 short circuit. After time t0, the collector current Ic rises (increases), the positive slope of the current becomes larger, and accordingly, the electromotive voltage VL of the inductor 21 rises in the negative direction, i.e., the absolute value becomes negative and increases.

[0099] At time t1, when the electromotive voltage VL drops below the voltage threshold Vref, the tilt determination signal Sg1 output from the comparator 53 of the tilt detection unit 43 changes from a low voltage to a high voltage. At the inputs of the AND circuit 44 of the clamp control circuit 48, the on / off signal Sig1 is at a high voltage, and the tilt determination signal Sg1 is at a high voltage, so the output signal Vk1 changes from a low voltage to a high voltage.

[0100] At time t2, when the collector current Ic exceeds the overcurrent threshold Iref, the overcurrent detection signal SigE, which is the output of the comparator 61 of the overcurrent detection unit 23, changes from a low voltage to a high voltage. This overcurrent detection signal SigE, indicating the detection of an overcurrent, is input to the on / off determination unit 57 of the drive circuit unit 41, the control circuit 16, and the AND circuit 45 of the clamp control circuit 48. At time t6, which is a delay time Td after time t2, the on / off determination unit 57 of the drive circuit unit 41 changes the on / off signal Sig2 from a high voltage to a low voltage. Time t2 is the time when the overcurrent detection unit 23 of the overcurrent detection circuit 15 detects the collector current Ic, i.e., an overcurrent in the main current, and outputs the overcurrent detection signal SigE indicating the detection of an overcurrent, and is therefore the overcurrent detection time tx. Time t6 is the end time ty of the delay time Td. From time t2 to time t6, the arm control circuit 14 outputs a drive signal Vout that maintains the power semiconductor element 13 of the target arm 70 in an on state for a predetermined delay time Td from the detection time tx when the overcurrent detection signal SigE indicates an overcurrent detection.

[0101] Also, at time t2, both inputs of the AND circuit 45 of the clamp control circuit 48 become high voltage, causing the output signal Vk2, which is the output of the AND circuit 45, to change from a low voltage to a high voltage. Since the output signal Vk2 is output as the switch drive signal Vsw and the breakdown detection signal SigF, at time t2, the switch drive signal Vsw changes from a low voltage to a high voltage. The high-voltage switch drive signal Vsw turns on the switch 55 of the clamp circuit 42, causing the gate-emitter voltage Vge to begin to decrease to the clamp voltage Vcl. As the gate-emitter voltage Vge begins to decrease, a sudden increase in the collector current Ic is suppressed, and current stress on the power semiconductor element 13 is alleviated.

[0102] At time t3, the positive slope of the collector current Ic becomes gentler, and the electromotive voltage VL becomes greater than the voltage threshold Vref. This causes the slope determination signal Sg1, which is the output of the comparator 53 of the slope detection unit 43, to change from a high voltage to a low voltage. This causes the output signal Vk1 of the AND circuit 44 to change from a high voltage to a low voltage. The output signal Vk2 of the AND circuit 45 changes from a high voltage to a low voltage due to the low-voltage output signal Vk1. Since the output signal Vk2 is output as the switch drive signal Vsw and the breakdown detection signal SigF, the switch drive signal Vsw and the breakdown detection signal SigF change from a high voltage to a low voltage at time t3. Because the switch drive signal Vsw changes from a high voltage to a low voltage, the switch 55 of the clamp circuit 42 changes from an on state to an off state. Therefore, the gate-emitter voltage Vge begins to rise from the clamp voltage Vcl to a positive voltage Vp. Time t2 is the detection time tx and also the clamp start time of the clamp time Tc. Time t3 is the end time of the clamp time Tc, that is, the clamp end time te.

[0103] At time t4, the collector current Ic reaches a peak value and then begins to decrease. After time t4, the collector-emitter voltage Vce begins to rise rapidly. The gate-emitter voltage Vge decreases from the positive voltage Vp from time t4 to time t5, reaches a minimum value at time t5, and then increases back to the positive voltage Vp. Unlike FIG. 37 in which the gate-emitter voltage Vge decreases from the clamp voltage Vcl, the power conversion device 10 of the second embodiment, like the power conversion device 10 of the first embodiment, decreases the gate-emitter voltage Vge from the positive voltage Vp but does not decrease below the clamp voltage Vcl. This makes it possible to suppress a rapid decrease in the collector current Ic and to suppress the collector-emitter voltage Vce to within the element withstand voltage Vbr of the power semiconductor element 13.

[0104] At time t6, the delay time Td ends, and the on / off signal Sig2 changes from high to low as indicated by signal characteristic 84b, causing the gate-emitter voltage Vge to start decreasing. Thereafter, the power semiconductor device 13 of the target arm 70 turns off, and the collector current Ic is cut off, i.e., becomes zero.

[0105] As described above, the power conversion device 10 of the second embodiment is configured such that the clamp control circuit 48 determines the clamp end time te of the clamp time Tc based on the slope determination signal Sg1. However, the configuration other than the clamp control circuit 48 is the same as that of the power conversion device 10 of the first embodiment, and therefore achieves the same effects as the power conversion device 10 of the first embodiment. Therefore, the power conversion device 10 of the second embodiment can prevent overvoltage breakdown due to a type 2 short circuit or a type 3 short circuit and reliably prevent secondary breakdown of the power semiconductor element 13. Furthermore, the power conversion device 10 of the second embodiment can notify that the paired arm of the arm unit 20 paired with the arm unit 20 from which the breakdown detection signal SigF indicating breakdown detection is output is broken by transmitting the breakdown detection signal SigF to a higher-level arm unit 20 such as the control circuit 16. Therefore, the power conversion device 10 of the second embodiment can identify the part including the broken arm when the power conversion device 10 fails due to, for example, a type 2 short circuit or a type 3 short circuit, thereby enabling rapid part replacement.

[0106] The power conversion device 10 of the second embodiment differs from the power conversion device 10 of the first embodiment in that the clamp end time te of the clamp time Tc is determined by the slope determination signal Sg1 of the slope detection unit 43 of the overcurrent detection circuit 15. As described above, the overcurrent detection circuit 15 can detect the slope di / dt of the change in current i over time, i.e., the current slope Ski, which is the slope of the current i, by detecting the detection voltage Vdet, which is the electromotive voltage VL of the inductor 21. It can also be said that the slope determination signal Sg1 of the slope detection unit 43 determines the slope of the collector current Ic. The power conversion device 10 of embodiment 2 differs from the power conversion device 10 of embodiment 1 in that the clamp end time te of the clamp time Tc is determined by the slope determination signal Sg1 of the slope detection unit 43 of the overcurrent detection circuit 15, and the clamp end time te of the clamp time Tc is determined by the slope of the collector current Ic, i.e., the current slope Ski of the collector current Ic. Therefore, even if the timing at which overvoltage occurs in the event of a Type 2 short circuit or a Type 3 short circuit changes due to external factors such as deterioration of the power semiconductor element 13 or capacitor 17 or partial disconnection of the wiring pattern, it is possible to reliably prevent overvoltage and secondary breakdown.

[0107] 10, the power conversion device 10 of the second embodiment may have an overcurrent detection circuit 15 provided in the negative-side wiring 36, and may perform overcurrent detection of the main current collectively by the single overcurrent detection circuit 15. In this case, the arm unit 20 may be configured such that the one-shot circuit 46 is removed from the arm control circuit 14 of the arm unit 20 shown in FIG. 11, and the output signal Vk2 is output as the switch drive signal Vsw and the breakdown detection signal SigF.

[0108] As described above, the power conversion device 10 of the second embodiment is a power conversion device that outputs output power Po obtained by power conversion of input power Pi by a power conversion unit 12 having a plurality of power semiconductor elements 13 a to 13 f. The power conversion unit 12 includes a plurality of upper and lower arms 30 a, 30 b, 30 c in which an upper arm having power semiconductor elements 13 a, 13 c, 13 e and a lower arm having power semiconductor elements 13 b, 13 d, 13 f controlled so as not to be turned on simultaneously with the upper arm are connected in series, and a plurality of arm control circuits 14 that control the upper arm and the lower arm, respectively. The arm control circuit 14 includes a drive circuit unit 41 that outputs a drive signal Vout to drive a target arm 70, which is the upper arm or lower arm to be controlled, an overcurrent detection circuit 15 that detects an overcurrent flowing through the target arm 70 in the ON state based on a current slope Ski, which is the slope with respect to time of the main current (collector current Ic) flowing through the target arm 70, and outputs an overcurrent detection signal SigE indicating the detection of an overcurrent, a clamp circuit 42 that limits the voltage of the drive signal Vout to a clamp voltage Vcl, and a clamp control circuit 48 that controls the clamp circuit 42. The clamp control circuit 48 controls the clamp circuit 42 to reduce the voltage of the drive signal Vout to the clamp voltage Vcl when the overcurrent detection signal SigE indicates the detection of an overcurrent, and controls the clamp circuit 42 to stop outputting the clamp voltage Vcl when a predetermined condition is satisfied based on the current slope Ski. After the output of the clamp voltage Vcl is stopped, the drive circuit unit 41 changes the voltage of the drive signal Vout to change the target arm 70 from the ON state to the OFF state. With this configuration, the power conversion device 10 of the second embodiment includes the overcurrent detection circuit 15 that detects that an overcurrent has flowed through the target arm 70, the clamp circuit 42 that limits the voltage of the drive signal Vout to the clamp voltage Vcl, and the clamp control circuit 48 that reduces the voltage of the drive signal Vout to the clamp voltage Vcl when the overcurrent detection signal SigE indicates the detection of an overcurrent and controls the clamp circuit 42 to stop the output of the clamp voltage Vcl when a set condition is satisfied, thereby making it possible to reliably prevent overvoltage breakdown of the power semiconductor elements 13 a to 13 f due to a Type 2 short circuit or a Type 3 short circuit.

[0109] Another power conversion device 10 according to the second embodiment is a power conversion device that outputs output power Po by converting input power Pi using a power conversion unit 12 having a plurality of power semiconductor elements 13a to 13f. The power conversion unit 12 includes a plurality of upper and lower arms 30a, 30b, and 30c, each of which is connected in series with an upper arm having power semiconductor elements 13a, 13c, and 13e, and a lower arm having power semiconductor elements 13b, 13d, and 13f that are controlled so as not to be turned on simultaneously with the upper arm. The power conversion device 10 also includes an overcurrent detection circuit 15 that detects an overcurrent flowing through an on-state upper arm or lower arm based on a current slope Ski, which is the slope with time of a current flowing through a negative wiring 36 connected opposite the upper arm among the plurality of lower arms, and outputs an overcurrent detection signal SigE indicating the detection of an overcurrent. The arm control circuit 14 includes a drive circuit unit 41 that outputs a drive signal Vout to drive a target arm 70, which is the upper arm or lower arm to be controlled, a clamp circuit 42 that limits the voltage of the drive signal Vout to a clamp voltage Vcl, and a clamp control circuit 48 that controls the clamp circuit 42. The clamp control circuit 48 controls the clamp circuit 42 to reduce the voltage of the drive signal Vout to the clamp voltage Vcl when the overcurrent detection signal SigE indicates an overcurrent detection, and controls the clamp circuit 42 to stop outputting the clamp voltage Vcl when a predetermined setting condition is satisfied based on the current slope Ski. After the output of the clamp voltage Vcl is stopped, the drive circuit unit 41 changes the voltage of the drive signal Vout to change the target arm 70 from an ON state to an OFF state.With this configuration, the other power conversion device 10 of embodiment 2 is equipped with an overcurrent detection circuit 15 that detects that an overcurrent has flowed in the target arm 70, a clamp circuit 42 that limits the voltage of the drive signal Vout to the clamp voltage Vcl, and a clamp control circuit 48 that reduces the voltage of the drive signal Vout to the clamp voltage Vcl when the overcurrent detection signal SigE indicates that an overcurrent has been detected, and controls the clamp circuit 42 to stop outputting the clamp voltage Vcl when set conditions are satisfied, thereby making it possible to reliably prevent overvoltage breakdown of the power semiconductor elements 13a to 13f due to a type 2 short circuit or a type 3 short circuit.

[0110] Third Embodiment. FIG. 14 is a diagram showing the configuration of a first arm unit according to a third embodiment, and FIG. 15 is a diagram showing the configurations of the drive circuit unit and clamp circuit of FIG. 14. FIG. 16 is a diagram showing the configuration of the first slope detection unit of FIG. 14, and FIG. 17 is a diagram showing the configuration of the second slope detection unit of FIG. 14. FIG. 18 is a timing chart illustrating the operation of the first arm unit according to the third embodiment. FIG. 19 is a diagram showing the configuration of a second arm unit according to the third embodiment, and FIG. 20 is a timing chart illustrating the operation of the second arm unit according to the third embodiment. FIG. 21 is a diagram showing the configuration of a third arm unit according to the third embodiment. In the power conversion devices 10 of the first and second embodiments, the clamp voltage Vcl of the clamp circuit 42 was a fixed value. In the power conversion device 10 of the third embodiment, the clamp voltage source 54 is changed to a variable voltage source 56, and the value of the clamp voltage Vcl is changed based on information on the detection voltage Vdeta or the current slope Ski output from the overcurrent detection circuit 15. By adopting such a configuration, the power conversion device 10 of embodiment 3 can further suppress sudden changes in the collector current Ic and overvoltage of the collector-emitter voltage Vce than the power conversion devices 10 of embodiments 1 and 2.

[0111] The power conversion device 10 of the third embodiment differs from the power conversion devices 10 of the first and second embodiments in that it includes a clamp circuit 47 having a variable voltage source 56 instead of the clamp circuit 42 having the clamp voltage source 54, and changes the value of the clamp voltage Vcl based on information on the detected voltage Vdata or the current slope Ski output from the overcurrent detection circuit 15. The detected voltage Vdata is information output from the first slope detection unit 43 shown in FIG. 16, and the current slope Ski is information output from the second slope detection unit 43 shown in FIG. 17. Note that in FIGS. 14, 19, and 21, the slope detection unit 43 is the first slope detection unit 43 or the second slope detection unit 43, and therefore the detected voltage Vdata and the current slope Ski are shown as being output together. 14, 19, and 21, when the slope detection unit 43 is the first slope detection unit 43, the detected voltage Vdeta is output from the slope detection unit 43, and when the slope detection unit 43 is the second slope detection unit 43, the current slope Ski is output from the slope detection unit 43. In Fig. 15, the detected voltage Vdeta and the current slope Ski input from the slope detection unit 43 are also shown together. When the slope detection unit 43 is the first slope detection unit 43, the detected voltage Vdeta is input to the clamp circuit 47, and when the slope detection unit 43 is the second slope detection unit 43, the current slope Ski is input to the clamp circuit 47. The following mainly describes the differences from the power conversion device 10 of the first and second embodiments.

[0112] The overall configuration of the power conversion device 10 of the third embodiment is the same as that of the first embodiment, but the internal configuration of the arm unit 20 is different. In the arm unit 20 of the third embodiment, the slope detection unit 43 outputs information on the detected voltage Vdeta, which is the electromotive voltage VL input via the filter 50, or the current slope Ski, and the information on the detected voltage Vdeta or the current slope Ski is input to the clamp circuit 47. As described above, the overcurrent detection circuit 15 can detect the slope di / dt of the change in current i over time, i.e., the current slope Ski, which is the slope of the current i, by detecting the detected voltage Vdet, which is the electromotive voltage VL of the inductor 21. Information on the detected voltage Vdeta can also be considered information on the current slope Ski, which is the slope of the collector current Ic. The first slope detection unit 43 is an example that directly outputs information on the detected voltage Vdeta and indirectly outputs information on the current slope Ski of the collector current Ic. The second slope detection unit 43 is an example that directly outputs information on the current slope Ski of the collector current Ic. The clamp circuit 47 operates based on information on the detected voltage Vdata or information on the current slope Ski of the collector current Ic, and a switch drive signal Vsw output from the clamp control circuit 48 .

[0113] The following describes the operation inside the arm unit 20 in the power conversion device 10 of embodiment 3. The first arm unit 20 shown in Fig. 14 is an example in which the clamp control circuit 48 includes the one-shot circuit 46, similar to embodiment 1. The second arm unit 20 shown in Fig. 19 is an example in which the clamp control circuit 48 does not include the one-shot circuit 46, similar to embodiment 2.

[0114] The first slope detection unit 43 and the second slope detection unit 43 in the third embodiment include a resistor 51, a capacitor 52, and a comparator 53, similar to the slope detection units 43 in the first and second embodiments. However, the first slope detection unit 43 in the third embodiment outputs a detection voltage Vdeta, which is the electromotive voltage VL input via a filter 50, from a wiring 71c. The second slope detection unit 43 in the third embodiment outputs the electromotive voltage VL input via the filter 50 to a wiring 71c, and outputs a current slope Ski via a multiplier 39 that multiplies the electromotive voltage VL by 1 / L. The detection voltage Vdeta output from the first slope detection unit 43 or the current slope Ski output from the second slope detection unit 43 is input to a variable voltage source 56 in a clamp circuit 47.

[0115] The variable voltage source 56 in the clamp circuit 47 varies the value of the clamp voltage Vcl based on the detected voltage Vdata or the current slope Ski of the collector current Ic. FIGS. 15 and 18 show examples in which the clamp voltage Vcl has a first clamp voltage value Vcla and a second clamp voltage value Vclb. The second clamp voltage value Vclb is greater than the first clamp voltage value Vcla. For example, during the operating period (i.e., clamp time Tc) in the timing charts of FIGS. 18 and 20, the clamp circuit 47 operates to reduce the value of the clamp voltage Vcl as the absolute value of the detected voltage Vdata or the absolute value of the current slope Ski, i.e., the positive slope of the collector current Ic, increases. In other words, the clamp circuit 47 sets the clamp voltage Vcl to a smaller value as the absolute value of the detected voltage Vdata or the absolute value of the current slope Ski, i.e., the positive slope of the collector current Ic, increases, and outputs the clamp voltage Vcl of the set voltage value. 18 , the larger the absolute value of the detection voltage Vdeta, i.e., the larger the positive slope of the collector current Ic, the smaller the first clamp voltage value Vcla, which is the value of the clamp voltage Vcl, is set to, and the clamp voltage Vcl of the set voltage value is output. In this way, the power conversion device 10 of the third embodiment can further reduce stress due to overcurrent than the power conversion devices 10 of the first and second embodiments.

[0116] Furthermore, the value of the second clamp voltage value Vclb set by the variable voltage source 56 is set to a voltage value greater than the first clamp voltage value Vcla as the absolute value of the detected voltage Vdeta increases or the absolute value of the current slope Ski increases, i.e., the negative slope of the collector current Ic increases, and the variable voltage source 56 outputs the clamp voltage Vcl of the set voltage value. That is, after the polarity of the detected voltage Vdet, Vdeta, or the polarity of the current slope Ski is reversed from the polarity at which the clamp voltage Vcl of the first clamp voltage value Vcla was output (after time t4), the variable voltage source 56 sets the second clamp voltage value Vclb to a voltage value greater than the first clamp voltage value Vcla as the absolute value of the detected voltage Vdeta or the absolute value of the current slope Ski increases. By changing the value of the second clamp voltage value Vclb based on the absolute value of the detection voltage Vdeta or the absolute value of the current slope Ski of the collector current Ic, it is possible to prevent overvoltage breakdown in the event of a type 2 short circuit or a type 3 short circuit even more effectively than the power conversion device 10 of embodiments 1 and 2.

[0117] In the power conversion devices 10 of the first and second embodiments, the switch 55 is turned off at time t3, thereby increasing the gate-emitter voltage Vge to the positive voltage Vp. That is, time t3 is the clamp end time te of the clamp time Tc. As an alternative method, the power conversion device 10 of the third embodiment may extend the set time Ts set by the one-shot circuit 46 to time t5 in FIG. 18 and operate to increase the value of the clamp voltage Vcl during the period from time t4 to time t5 when the slope of the collector current Ic becomes negative. In this way, the power conversion device 10 of the third embodiment can prevent overvoltage breakdown in the event of a type 2 short circuit or a type 3 short circuit, similar to the power conversion device 10 of the first embodiment. 18 shows an example in which the clamp voltage Vcl is changed from the first clamp voltage value Vcla to the second clamp voltage value Vclb at time tA during the period T1 from time tA to time tB during which the electromotive voltage VL and the current slope Ski are positive and substantially constant after time t4 when the collector current Ic reaches its maximum value. Note that time t3 in FIG. 18 is the clamp end time te in FIG. 6 and is shown for reference.

[0118] The range of voltage values ​​for changing the clamp voltage Vcl may be higher than the gate threshold voltage of the transistor Tr of the power semiconductor element 13 and within the withstand voltage of the gate-emitter voltage Vge of the power semiconductor element 13, and may be a value greater than the positive voltage Vp. Furthermore, instead of increasing the value of the clamp voltage Vcl, the gate-emitter voltage Vge may be increased by separately providing an active clamp circuit constituted by a Zener diode or the like between the collector terminal C and the gate terminal G, or any circuit that can increase the gate-emitter voltage Vge before an overvoltage of the collector-emitter voltage Vce occurs may be used.

[0119] Up to this point, we have described the common parts between the first arm section 20 and the second arm section 20 of the third embodiment and the parts related to the one-shot circuit 46 of the first arm section 20. FIG. 18 illustrates the operation of the first arm section 20 of the third embodiment during a Type 2 short circuit. This section will focus on differences from FIG. 6 of the first embodiment. FIG. 18 shows current characteristics 81 of the collector current Ic, voltage characteristics 82 of the collector-emitter voltage Vce, voltage characteristics 83 of the gate-emitter voltage Vge, signal characteristics 84a of the on-off signal Sig1, signal characteristics 84b of the on-off signal Sig2, signal characteristics 85 of the overcurrent detection signal SigE, voltage characteristics 86 of the electromotive voltage VL of the inductor 21, signal characteristics 87 of the output signal Vk1, and signal characteristics 88 of the breakdown detection signal SigF and the switch drive signal Vsw. In FIG. 18, the horizontal axis represents time [s], and the vertical axis of the collector current Ic represents current [A]. The vertical axes of the collector-emitter voltage Vce, gate-emitter voltage Vge, on-off signals Sig1 and Sig2, overcurrent detection signal SigE, electromotive voltage VL, output signal Vk1, breakdown detection signal SigF, and switch drive signal Vsw each represent voltage [V]. For simplicity of explanation, the electromotive voltage VL waveform is assumed to be directly input to the inverting input of comparator 53 without filter 50.

[0120] As described above, the set time Ts is the time from time t2 to time t5. During this set time Ts, the clamp control circuit 48 controls the clamp circuit 47 to limit the voltage of the drive signal Vout to the clamp voltage Vcl. After limiting the voltage of the drive signal Vout to the clamp voltage Vcl, the clamp control circuit 48 controls the clamp circuit 47 to stop outputting the clamp voltage Vcl when the set time Ts has elapsed since the time (detection time tx) when the overcurrent detection signal SigE indicates an overcurrent detection, i.e., when the clamp end time te is reached. The period from time t2 to time tA is the first clamp period T3 during which the clamp voltage Vcl of the first clamp voltage value Vcla is output, and the period from time tA to time t5 is the second clamp period T4 during which the clamp voltage Vcl of the second clamp voltage value Vclb is output. Time tA is the time when the value of the clamp voltage Vcl is changed, and is therefore the change start time tf. At time t5, when the output of the clamp voltage Vcl is stopped, the gate-emitter voltage Vge starts to rise to the positive voltage Vp.

[0121] Clamp circuit 47 outputs clamp voltage Vcl from variable voltage source 56, the voltage value of which is set based on information about detected voltage Vdeta or current slope Ski output from overcurrent detection circuit 15. The voltage value of clamp voltage Vcl output from variable voltage source 56 is a first clamp voltage value Vcla at the start of clamping (detection time tx), and is a second clamp voltage value Vclb higher than the first clamp voltage value Vcla from change start time tf during clamping to the end time of set time Ts (clamp end time te). The operation of clamp control circuit 48 can also be expressed as follows. After controlling the clamp circuit 42 to reduce the voltage of the drive signal Vout to the clamp voltage Vcl, if the overcurrent detection signal SigE indicates an overcurrent detection, i.e., if the overcurrent of the main current is determined to be a Type 2 short circuit or a Type 3 short circuit, the clamp control circuit 48 controls the clamp circuit 42 to change the clamp voltage Vcl from the first clamp voltage value Vcla at the clamp start indication (detection time tx) to a second clamp voltage value Vclb higher than the first clamp voltage value Vcla. After controlling the clamp circuit 47 to reduce the voltage of the drive signal Vout to the clamp voltage Vcl, if the collector current Ic, which is the main current, decreases and falls below the overcurrent threshold Iref, the overcurrent detection signal SigE changes from a high voltage to a low voltage, and if the overcurrent detection signal SigE indicates no overcurrent detection, i.e., if the overcurrent of the main current is determined to be other than a Type 2 short circuit or a Type 3 short circuit, the clamp control circuit 48 controls the clamp circuit 42 not to stop outputting the clamp voltage Vcl. In addition, the clamp control circuit 48 controls the clamp circuit 47 to stop outputting the clamp voltage Vcl, which has been changed to the second clamp voltage value Vclb, when the set time Ts has elapsed from the time (detection time tx) when the overcurrent detection signal SigE indicates an overcurrent detection, i.e., when the clamp end time te is reached.

[0122] The second arm unit 20 of embodiment 3 will be described. Differences from the first arm unit 20 will be mainly described. The first arm unit 20 of embodiment 3 differs from the arm unit of embodiment 1 shown in FIG. 2 in that it includes a clamp circuit 47 instead of the clamp circuit 42 and changes the value of the clamp voltage Vcl based on information about the detection voltage Vdata or the current slope Ski output from the overcurrent detection circuit 15. The second arm unit 20 of embodiment 3 differs from the arm unit of embodiment 2 shown in FIG. 12 in that it includes a clamp circuit 47 instead of the clamp circuit 42 and changes the value of the clamp voltage Vcl based on information about the detection voltage Vdata or the current slope Ski output from the overcurrent detection circuit 15. An example of the operation of the second arm unit 20 of embodiment 3 during a type 2 short circuit is shown in FIG. 20. 13 in which the value of clamp voltage Vcl is a fixed value, in Fig. 20, the greater the absolute value of detection voltage Vdata or the greater the absolute value of current slope Ski, i.e., the greater the positive slope of collector current Ic, during the period in which clamp circuit 47 is operating, i.e., the period of clamp time Tc, the smaller the value of clamp voltage Vcl is set to. The waveforms in Fig. 20 are basically the same as those in Fig. 13 of embodiment 2, and therefore description thereof will not be repeated.

[0123] As described above, the first power conversion device 10 of the third embodiment includes the clamp circuit 47 having the variable voltage source 56 and is configured to change the value of the clamp voltage Vcl based on information about the detected voltage Vdeta or the current slope Ski output from the overcurrent detection circuit 15. However, the other configuration is the same as that of the power conversion device 10 of the first embodiment, and therefore, the same effects as those of the power conversion device 10 of the first embodiment are achieved. The second power conversion device 10 of the third embodiment includes the clamp circuit 47 having the variable voltage source 56 and is configured to change the value of the clamp voltage Vcl based on information about the detected voltage Vdeta or the current slope Ski output from the overcurrent detection circuit 15. However, the other configuration is the same as that of the power conversion device 10 of the second embodiment, and therefore, the same effects as those of the power conversion device 10 of the second embodiment are achieved. Therefore, the first power conversion device 10 and the second power conversion device 10 of the third embodiment can prevent overvoltage breakdown due to a Type 2 short circuit or a Type 3 short circuit, and can reliably prevent secondary breakdown of the power semiconductor elements 13. Furthermore, the first power conversion device 10 and the second power conversion device 10 of embodiment 3 change the value of the clamp voltage Vcl based on information on the detection voltage Vdeta or the current slope Ski output from the overcurrent detection circuit 15, and therefore can further suppress sudden changes in the collector current Ic and overvoltage of the collector-emitter voltage Vce than the power conversion devices 10 of embodiments 1 and 2.

[0124] In the power conversion device 10 of the third embodiment, similar to the fourth power conversion device 10 of the first embodiment shown in FIG. 10 , the overcurrent detection circuit 15 may be provided in the negative wiring 36, and the single overcurrent detection circuit 15 may perform overcurrent detection of the main current collectively. The configuration of the third arm unit 20 shown in FIG. 21 is an example including a one-shot circuit 46. Note that the third arm unit 20 does not necessarily include the one-shot circuit 46. In the third arm unit 20, the arm control circuit 14 includes the power semiconductor element 13 of the target arm 70, a drive circuit unit 41, a clamp circuit 47, and a clamp control circuit 48. The clamp control circuit 48 receives the on / off signal Sig1 output from the control circuit 16, the overcurrent detection signal SigE output from the overcurrent detection circuit 15, and the slope determination signal Sg1. The clamp circuit 47 receives the detection voltage Vdata or the current slope Ski output from the overcurrent detection circuit 15. In the power conversion device 10 of the third embodiment, even if an arm section 20 is not provided with an overcurrent detection circuit 15, the clamp circuit 47 of the arm section 20 can be controlled by the overcurrent detection circuit 15 commonly provided in the negative side wiring 36 and the clamp control circuit 48 of each arm section 20. Therefore, the power conversion device 10 of the third embodiment, which is provided with the third arm section 20, can reliably prevent overvoltage breakdown of the power semiconductor elements 13a to 13f due to a type 2 short circuit or a type 3 short circuit.

[0125] The power conversion device 10 of the first to third embodiments determines the operation of the clamp circuits 42, 47 based on information on the detected voltage Vdeta or information on the current slope Ski of the collector current Ic. However, a configuration Conf may be adopted in which the clamp circuits 42, 47 are operated after an overcurrent is detected, i.e., after an overcurrent detection signal SigE indicating an overcurrent is output, and if the increase in the collector current Ic cannot be suppressed, the switch 55 of the clamp circuit 42 is turned off or the value of the clamp voltage Vcl output from the variable voltage source 56 of the clamp circuit 47 is increased. If the increase in collector current Ic cannot be suppressed even when switch 55 of clamp circuit 42 is turned off or the value of clamp voltage Vcl output from variable voltage source 56 of clamp circuit 47 is operated to increase, overcurrent detection circuit 15 detects electromotive voltage VL, current slope Ski, or collector current Ic, which is the output value of current detection circuit 22, and determines that the increase in collector current Ic has not been suppressed if the value of electromotive voltage VL, current slope Ski, or collector current Ic does not decrease. As described in embodiment 1, in the case of a type 2 short circuit or a type 3 short circuit, the collector current Ic does not decrease even when gate-emitter voltage Vge is limited to clamp voltage Vcl. Therefore, by adopting a configuration such as configuration Conf, it is possible to prevent an overvoltage of collector-emitter voltage Vce in the case of a type 2 short circuit or a type 3 short circuit, as in embodiments 1 to 3.

[0126] Fourth Embodiment. FIG. 22 is a diagram showing the configuration of a power conversion device according to a fourth embodiment, and FIG. 23 is a diagram showing the configuration of a first arm according to the fourth embodiment. FIG. 24 is a diagram showing the configuration of the tilt detection unit of FIG. 23, and FIG. 25 is a diagram showing the configuration of the overcurrent detection unit of FIG. 23. FIG. 26 is a timing chart explaining the operation of the first arm according to the fourth embodiment. FIG. 27 is a diagram showing the configuration of a second arm according to the fourth embodiment, and FIG. 28 is a timing chart explaining the operation of the second arm according to the fourth embodiment. FIG. 29 is a diagram showing the configuration of a third arm according to the fourth embodiment, and FIG. 30 is a diagram showing the configuration of the drive circuit unit and clamp circuit of FIG. 29. FIG. 31 is a timing chart explaining the operation of the third arm according to the fourth embodiment, and FIG. 32 is a diagram showing the configuration of a fourth arm according to the fourth embodiment. In the power conversion device 10 of the first to third embodiments, the overcurrent detection circuit 15 detects an overcurrent in the collector current Ic, which is the main current, and determines the slope of the collector current Ic based on the electromotive voltage VL output from the inductor 21, i.e., the detection voltage Vdet including the current slope Ski of the collector current Ic output from the slope information output device 40, thereby preventing an overvoltage in the collector-emitter voltage Vce. Even if the collector-emitter voltage Vce is used as the detection voltage Vdet, an overcurrent in the collector current Ic, which is the main current, and determines the slope of the collector-emitter voltage Vce can be prevented. In the fourth embodiment, an example of a power conversion device 10 will be described in which the overcurrent detection circuit 25 detects an overcurrent in the collector current Ic, which is the main current, based on the detection voltage Vdet, which is the collector-emitter voltage Vce. The method of detecting the collector-emitter voltage Vce is realized by the slope information output device 40, not shown. The method for detecting the collector-emitter voltage Vce will be described later. The following mainly describes the differences from the power conversion device 10 of the first to third embodiments.

[0127] The power conversion device 10 of the fourth embodiment shown in Fig. 22 has a configuration similar to that of the power conversion device 10 of the first embodiment shown in Fig. 1, but differs in the internal configuration of the arm unit 20. First, a first arm unit 20 and a power conversion device 10 of the fourth embodiment including the first arm unit 20 will be described with reference to Figs. 23 to 26. The arm control circuit 14 in the first arm unit 20 of the fourth embodiment includes a drive circuit unit 41 that outputs a drive signal Vout that drives the power semiconductor element 13 that is the target arm 70, an overcurrent detection circuit 25 that detects that an overcurrent has flowed through the target arm 70 in the ON state based on a voltage slope Skv that is the slope with respect to time of the voltage between the main terminals (collector-emitter voltage Vce) of the target arm 70 and outputs an overcurrent detection signal SigE indicating the detection of an overcurrent, a clamp circuit 42 that limits the voltage of the drive signal Vout to a clamp voltage Vcl, and a clamp control circuit 48 that controls the clamp circuit 42. The overcurrent detection circuit 25 differs from the overcurrent detection circuits 15 of the first to third embodiments in that it does not include an inductor 21 but includes a voltage detection unit 24, and in that the collector-emitter voltage Vce of the power semiconductor element 13 is input as the detection voltage Vdet. The overcurrent detection circuit 25 detects that an overcurrent has flowed through the target arm 70 in the ON state based on a voltage slope Skv, which is the gradient with time of the main terminal voltage (collector-emitter voltage Vce) detected based on the detection voltage Vdet, which is the main terminal voltage (collector-emitter voltage Vce) of the target arm 70, and outputs an overcurrent detection signal SigE indicating the detection of an overcurrent. Because the main terminal voltage (collector-emitter voltage Vce) is the detection voltage Vdet, the voltage slope Skv is also the gradient with time of the detection voltage Vdet.

[0128] The drive circuit 41, clamp circuit 42, and clamp control circuit 48 are the same as those in the first embodiment. The overcurrent detection circuit 25 includes a voltage detection unit 24 that outputs a collector-emitter voltage Vce1 detected from a detection voltage Vdet, which is the main terminal voltage between the collector terminal C and the emitter terminal E of the power semiconductor element 13, i.e., the collector-emitter voltage Vce; an overcurrent detection unit 23 that detects the flow of an overcurrent based on the collector-emitter voltage Vce1 output from the voltage detection unit 24 and outputs an overcurrent detection signal SigE indicating the detection of an overcurrent; and a slope detection unit 43 that outputs a slope determination signal Sg1 that determines a voltage slope Skv, which is the slope of the detection voltage Vdet with respect to time. Since the slope detection unit 43 determines the voltage slope Skv of the detection voltage Vdet, it can also be expressed as determining the detection voltage Vdet. Because the voltage slope Skv is detected by the slope detection unit 43, it can also be referred to as a detection slope Skd.

[0129] In the slope detection unit 43, a resistor 51 and a capacitor 52 form a filter 50 for removing high-frequency noise components contained in the collector-emitter voltage Vce. One end of the capacitor 52 is connected to the collector terminal C via a wiring 71a, and one end of the resistor 51 is connected to the emitter terminal E via a wiring 71b. The other end of the capacitor 52 and the other end of the resistor 51 are connected to wiring 71c. A differentiating circuit 49 is connected to the wiring 71c, and the differentiating circuit 49 outputs a voltage slope Skv, which is the slope of the temporal change in the collector-emitter voltage Vce, i.e., the slope with respect to time. The voltage slope Skv is input to the inverting input of a comparator 53, and a reference potential power supply 72, which outputs a voltage slope threshold Krefv based on a reference potential Vs, is connected to the non-inverting input of the comparator 53. The comparator 53 outputs a determination signal Sg0 to a pulse generating circuit 65. The pulse generating circuit 65 detects the rising edge of the determination signal Sg0 and outputs a slope determination signal Sg1, a pulse signal that maintains a high voltage for a fixed pulse time Tp, using a built-in timer. Since the voltage slope Skv is the detection slope Skd, the voltage slope threshold Krefv is also the detection slope threshold Kref. The output signal Vk1 of the AND circuit 44 changes in response to the slope determination signal Sg1 when the on-off signal Sig1 is at a high voltage. The high-voltage pulse width in the signal characteristic 87 of the output signal Vk1 shown in FIG. 26 corresponds to the pulse time Tp. Note that the notation of Tp (see FIG. 28) is omitted in FIG. 26. In FIG. 26, the start of the pulse time Tp is time t1, and the end of the pulse time Tp, i.e., the termination time, is set between time t4 and time t5. The filter 50 is a low-pass filter, and its cutoff frequency is set to a value sufficient to prevent the collector-emitter voltage Vce from attenuating during a type 2 short circuit.

[0130] The slope detection unit 43 of the fourth embodiment detects a voltage slope Skv, which is the slope of the collector-emitter voltage Vce, and outputs a slope determination signal Sg1, which is a pulse signal that becomes a high voltage for a certain period of time, when the voltage slope exceeds a voltage slope threshold Krefv. Here, the voltage slope threshold Krefv is set between the voltage slope Skv (first voltage slope value) of the collector-emitter voltage Vce during normal operation before time t0 and the voltage slope Skv (second voltage slope value) after the occurrence of a type 2 short circuit at time t0 and before the collector current Ic reaches its peak value. The voltage slope threshold Krefv is set within the range expressed by equation (5): first voltage slope value < Krefv < second voltage slope value (5)

[0131] The slope detection unit 43 of the fourth embodiment includes a comparator 53 that compares a voltage slope Skv of the detection voltage Vdet, which is the collector-emitter voltage Vce, with a voltage slope threshold Krefv, and outputs a determination signal Sg0 indicating an excess detection when the voltage slope Skv exceeds the voltage slope threshold Krefv, and indicating no excess detection when the voltage slope Skv is equal to or less than the voltage slope threshold Krefv. The voltage slope threshold Krefv is set to indicate no excess detection when the target arm 70 is in the ON state or OFF state of normal operation, and to indicate an excess detection when the counter arm, which is the upper arm or lower arm paired with the target arm 70, is short-circuited when the target arm 70 is in the ON state.

[0132] As shown in FIG. 26 , the voltage slope Skv of the collector-emitter voltage Vce during normal operation before time t0 is small, and the voltage slope Skv increases after a Type 2 short circuit occurs at time t0. By setting a voltage slope threshold Krefv between the first and second voltage slope values, the slope detector 43 of the fourth embodiment can detect a sudden increase in the collector current Ic due to a Type 2 short circuit, allowing operation similar to that of the slope detector 43 of the first to third embodiments. The second voltage slope value is, for example, the value of the voltage slope Skv from time t2 to time t3 in FIG. 26 . Note that even if the voltage slope Skv changes between time t2 and time t3, it is very gradual. FIG. 26 illustrates an example in which the voltage slope Skv is constant from time t2 to time t3.

[0133] The overcurrent detection unit 23 includes a comparator 61 and a reference potential power supply 73 that outputs an overcurrent detection threshold Vref3 based on a reference potential Vs. The overcurrent detection threshold Vref3 is input to the inverting input of the comparator 61. The collector-emitter voltage Vce1 output from the voltage detection unit 24 is input to the non-inverting input of the comparator 61 of the overcurrent detection unit 23. When the collector-emitter voltage Vce1 exceeds the overcurrent detection threshold Vref3, the overcurrent detection unit 23 of the fourth embodiment determines that an overcurrent has flowed through the power semiconductor element 13 and outputs an overcurrent detection signal SigE indicating the detection of an overcurrent. The overcurrent detection circuit 25 of the fourth embodiment detects that an overcurrent has flowed through the target arm 70 based on the characteristics of the collector-emitter voltage Vce, which is the voltage between the main terminals of the power semiconductor element 13 when the power semiconductor element 13 is in the on state. As shown in FIG. 26 , the collector-emitter voltage Vce has a value (second voltage value) after time t2, when the collector current Ic exceeds the overcurrent threshold Iref used in the overcurrent detection units 23 of the first to third embodiments, that is, a value greater than the value (first voltage value) during normal operation before time t0. The overcurrent detection threshold Vref3 may be set between the first and second voltage values ​​as shown in equation (6). For example, the value of the collector-emitter voltage Vce at the overcurrent threshold Iref may be set as the overcurrent detection threshold Vref3. This allows the overcurrent detection unit 23 of the fourth embodiment to detect overcurrents in the same manner as the overcurrent detection units 23 of the first to third embodiments. The second voltage value is, for example, the value of the collector-emitter voltage Vce at the midpoint between time t2 and time t3 in FIG. 26 : first voltage value < Vref3 < second voltage value (6)

[0134] The clamp control circuit 48 controls the clamp circuit 42 to reduce the voltage of the drive signal Vout to the clamp voltage Vcl, and then controls the clamp circuit 42 to stop outputting the clamp voltage Vcl when the collector-emitter voltage Vce1 increases, that is, the overcurrent detection signal SigE indicates that an overcurrent has been detected, and when a predetermined set time Ts has elapsed since the time (detection time tx) when the overcurrent detection signal SigE indicated that an overcurrent has been detected, that is, when it is determined that the overcurrent of the main current is a type 2 short circuit or a type 3 short circuit. The clamp control circuit 48 controls the clamp circuit 42 to reduce the voltage of the drive signal Vout to the clamp voltage Vcl, and then when the collector-emitter voltage Vce1 decreases and falls below the overcurrent detection threshold Vref3, the overcurrent detection signal SigE changes from a high voltage to a low voltage, and the overcurrent detection signal SigE indicates that an overcurrent has not been detected, that is, when it is determined that the overcurrent of the main current is other than a type 2 short circuit or a type 3 short circuit, the clamp control circuit 48 controls the clamp circuit 42 so as not to stop outputting the clamp voltage Vcl.

[0135] Next, the operation of the first arm 20 of the fourth embodiment in the event of a type 2 short circuit will be described with reference to Figure 26. Figure 26 shows current characteristics 81 of the collector current Ic, voltage characteristics 82 of the collector-emitter voltage Vce, voltage characteristics 83 of the gate-emitter voltage Vge, signal characteristics 84a of the on-off signal Sig1, signal characteristics 84b of the on-off signal Sig2, signal characteristics 85 of the overcurrent detection signal SigE, voltage slope characteristics 89 of the voltage slope Skv, signal characteristics 87 of the output signal Vk1, and signal characteristics 88 of the breakdown detection signal SigF and the switch drive signal Vsw. In Figure 26, the horizontal axis represents time [s], and the vertical axis of the collector current Ic represents current [A]. The vertical axes of the collector-emitter voltage Vce, gate-emitter voltage Vge, on-off signals Sig1 and Sig2, overcurrent detection signal SigE, output signal Vk1, breakdown detection signal SigF, and switch drive signal Vsw each represent voltage [V]. The vertical axis of the voltage gradient Skv represents voltage gradient [V / s].

[0136] From the time at the left end to time t0, the power semiconductor element 13 that is the target arm 70 of the arm unit 20 is in an ON state, and the power semiconductor element 13 of the counter arm is in an OFF state. From the time at the left end to time t0, the gate-emitter voltage Vge is a positive voltage Vp, and the collector current Ic is a load current Im. Note that the notation of Im (see FIG. 34) is omitted in FIG. 26. From the time at the left end to time t0, the signals of the arm unit 20 shown in FIG. 26 are as follows: the on / off signals Sig1 and Sig2 are high voltages with a digital value of 1, the overcurrent detection signal SigE is a low voltage with a digital value of 0, the voltage slope Skv is approximately zero, the output signal Vk1 is a low voltage with a digital value of 0, and the breakdown detection signal SigF and the switch drive signal Vsw are low voltages with a digital value of 0.

[0137] At time t0, while the power semiconductor element 13 of the target arm 70 is in the on state and the collector current Ic is flowing, the power semiconductor element 13 of the opposing arm breaks down for some reason, resulting in a type 2 short circuit. After time t0, the collector current Ic rises (increases), and the collector-emitter voltage Vce increases.

[0138] At time t1, when the voltage slope Skv exceeds the voltage slope threshold Krefv, the determination signal Sg0, which is the output of the comparator 53 of the slope detection unit 43, changes from a low voltage to a high voltage. As the determination signal Sg0 changes to a high voltage, the slope determination signal Sg1 changes from a low voltage to a high voltage. At the inputs of the AND circuit 44 of the clamp control circuit 48, the on / off signal Sig1 is at a high voltage, and the slope determination signal Sg1 is at a high voltage, so the output signal Vk1 changes from a low voltage to a high voltage.

[0139] At time t2, when the collector-emitter voltage Vce exceeds the overcurrent detection threshold Vref3, the overcurrent detection signal SigE, which is the output of the comparator 61 of the overcurrent detection unit 23, changes from a low voltage to a high voltage. This overcurrent detection signal SigE, indicating an overcurrent detection, is input to the on / off determination unit 57 of the drive circuit unit 41, the control circuit 16, and the AND circuit 45 of the clamp control circuit 48. At time t6, which is a delay time Td after time t2, the on / off determination unit 57 of the drive circuit unit 41 changes the on / off signal Sig2 from a high voltage to a low voltage. Time t2 is the time at which the overcurrent detection unit 23 of the overcurrent detection circuit 15 detects an overcurrent in the collector current Ic, i.e., the main current, based on the collector-emitter voltage Vce and outputs the overcurrent detection signal SigE indicating an overcurrent detection, and is therefore the overcurrent detection time tx. Time t6 is the end time ty of the delay time Td. From time t2 to time t6, the arm control circuit 14 outputs a drive signal Vout that maintains the power semiconductor element 13 of the target arm 70 in an on state for a predetermined delay time Td from the detection time tx when the overcurrent detection signal SigE indicates an overcurrent detection.

[0140] Also, at time t2, both inputs of AND circuit 45 of clamp control circuit 48 become high voltage, so that output signal Vk2, which is the output of AND circuit 45, changes from low voltage to high voltage, and one-shot circuit 46 outputs switch drive signal Vsw, a pulse signal that remains at a high voltage for set time Ts. The high-voltage switch drive signal Vsw turns on switch 55 of clamp circuit 42, and gate-emitter voltage Vge begins to decrease to clamp voltage Vcl. As gate-emitter voltage Vge begins to decrease, a sudden rise in collector current Ic is suppressed, and current stress on power semiconductor element 13 is reduced.

[0141] At time t3, the output of the one-shot circuit 46 has passed the set time Ts, so the switch drive signal Vsw changes from a high voltage to a low voltage, and the switch 55 of the clamp circuit 42 changes from an on state to an off state. As a result, the gate-emitter voltage Vge begins to rise from the clamp voltage Vcl to a positive voltage Vp. The set time Ts is the clamp time Tc during which the gate-emitter voltage Vge is limited to the clamp voltage Vcl. Time t2 is the detection time tx and also the clamp start time. Time t3 is the end time of the clamp time Tc, i.e., the clamp end time te.

[0142] At time t4, the collector current Ic reaches a peak value and then begins to decrease. From time t4 onward, the collector-emitter voltage Vce begins to rise rapidly. At time t4, the voltage gradient Skv reaches its maximum. Therefore, time t4 is also the time when the voltage gradient is maximum. The gate-emitter voltage Vge decreases from the positive voltage Vp from time t4 to time t5, reaches a minimum value at time t5, and then increases back to the positive voltage Vp. Unlike FIG. 37 , in which the gate-emitter voltage Vge decreases from the clamp voltage Vcl, in the power conversion device 10 of embodiment 4, the gate-emitter voltage Vge decreases from the positive voltage Vp but does not decrease below the clamp voltage Vcl. This makes it possible to suppress a rapid decrease in the collector current Ic, and to suppress the collector-emitter voltage Vce to within the element breakdown voltage Vbr of the power semiconductor element 13.

[0143] In Fig. 26, the clamp end time te of the clamp time Tc during which the gate-emitter voltage Vge is limited to the clamp voltage Vcl is time t3. This clamp end time te is set to a time before time t4, the time at which the collector current Ic reaches its maximum value and the time at which the collector-emitter voltage Vce begins to rise sharply. Similar to the power conversion device 10 of the first embodiment, the power conversion device 10 of the fourth embodiment increases the gate-emitter voltage Vge from the clamp voltage Vcl at a time before the collector-emitter voltage Vce begins to rise sharply, thereby preventing an overvoltage that exceeds the element breakdown voltage Vbr shown in Fig. 37. Note that when determining the set time Ts, the set time Ts may be determined in advance by observing the collector current Ic, or the set time Ts may be determined in advance by observing the voltage slope Skv.

[0144] At time t6, the delay time Td ends, and the on / off signal Sig2 changes from high to low as indicated by signal characteristic 84b, causing the gate-emitter voltage Vge to start decreasing. Thereafter, the power semiconductor device 13 of the target arm 70 turns off, and the collector current Ic is cut off, i.e., becomes zero.

[0145] 26 is set as follows: The end time ty of the delay time Td is the time that exceeds the time (maximum voltage slope tz) at which the voltage slope Skv, which is the slope with time of the detection voltage Vdet, i.e., the collector-emitter voltage Vce, associated with the overcurrent flowing through the target arm 70, reaches its maximum value after the detection time tx, and is equal to or greater than the time at which the clamp voltage Vcl is stopped (clamp end time te).

[0146] The operation of the first arm section 20 of embodiment 4 in the event of a Type 2 short circuit has been described using FIG. 26 . As described above, a Type 3 short circuit differs from a Type 2 short circuit in that a paired element in the off state suddenly breaks down and shorts while the diode connected in antiparallel to the element is conducting. However, like a Type 2 short circuit, a Type 3 short circuit occurs when the element itself is in the on state. In the case of a Type 3 short circuit, during the first short period of time after the element changes from the off state to the on state (not shown in FIG. 26 ), the collector current Ic and the collector-emitter voltage Vce differ from those in a Type 2 short circuit, but the waveforms shown in FIG. 26 remain the same even in the event of a Type 3 short circuit. Therefore, the operation of the first arm section 20 of embodiment 4 in the event of a Type 3 short circuit is similar to the operation of the first arm section 20 of embodiment 4 in the event of a Type 2 short circuit.

[0147] As mentioned above, the method of detecting the collector-emitter voltage Vce is realized by the gradient information output device 40 (not shown). Methods for detecting the collector-emitter voltage Vce include a voltage detection method using resistive voltage division and a DESAT (Desaturation) detection method consisting of a high-voltage diode, resistor, capacitor, and power supply, but any method that can detect the collector-emitter voltage Vce will do. In the case of the voltage detection method, the gradient information output device 40 is a plurality of resistors connected in series. In the case of the DESAT detection method, the gradient information output device 40 includes a high-voltage diode, resistor, capacitor, and power supply.

[0148] As described above, it can be seen that the power conversion device 10 of the fourth embodiment including the first arm unit 20 can prevent overvoltage breakdown due to a Type 2 short circuit or a Type 3 short circuit and reliably prevent secondary breakdown of the power semiconductor element 13. Furthermore, similar to the power conversion device 10 of the first embodiment, the power conversion device 10 of the fourth embodiment including the first arm unit 20 can notify that the paired arm in the arm unit 20 paired with the arm unit 20 from which the breakdown detection signal SigF indicating breakdown detection is output is broken by transmitting the breakdown detection signal SigF indicating breakdown detection to a higher level of the arm unit 20 such as the control circuit 16. Therefore, the power conversion device 10 of the fourth embodiment including the first arm unit 20 can identify parts including the broken arm when the power conversion device 10 fails due to, for example, a Type 2 short circuit or a Type 3 short circuit, enabling quick part replacement.

[0149] Next, a power conversion device 10 according to a fourth embodiment including the second arm section 20 will be described with reference to Figures 27 and 28. In the power conversion device 10 according to the fourth embodiment including the first arm section 20, the switch 55 of the clamp circuit 42 is turned on, and the clamp end time te of the clamp time Tc during which the gate-emitter voltage Vge is limited to the clamp voltage Vcl is determined by the set time Ts of the one-shot circuit 46. In the power conversion device 10 according to the fourth embodiment including the second arm section 20, an example will be described in which the one-shot circuit 46 is not provided, and the clamp end time te of the clamp time Tc is determined by the slope determination signal Sg1 of the overcurrent detection circuit 25, as in the power conversion device 10 according to the second embodiment. The power conversion device 10 of the fourth embodiment, which includes the second arm unit 20, differs from the power conversion device 10 of the fourth embodiment, which includes the first arm unit 20, in that the clamp end time te of the clamp time Tc is determined by the slope determination signal Sg1 of the overcurrent detection circuit 25, without using the set time Ts of the one-shot circuit 46. The following mainly describes the differences from the power conversion device 10 of the fourth embodiment, which includes the first arm unit 20.

[0150] The overall configuration of the power conversion device 10 of embodiment 4 including the second arm section 20 is the same as that of the power conversion device 10 of embodiment 4 including the first arm section 20, but the internal configuration of the arm section 20 is different. The one-shot circuit 46 is eliminated from the second arm section 20. The clamp control circuit 48 in the second arm section 20 includes AND circuits 44 and 45. The configuration of the input / output of the AND circuit 44 and the input of the AND circuit 45 is the same as that of the first arm section 20. The AND circuit 45 outputs an output signal Vk2. The clamp control circuit 48 outputs the output signal Vk2 as a switch drive signal Vsw and a breakdown detection signal SigF.

[0151] As described above, in the power conversion device 10 of the fourth embodiment including the first arm unit 20, the clamp control circuit 48 controls the clamp circuit 42 to reduce the voltage of the drive signal Vout to the clamp voltage Vcl when the overcurrent detection signal SigE indicates that an overcurrent has been detected, and also controls the clamp circuit 42 to stop outputting the clamp voltage Vcl when the predetermined set time Ts has elapsed since the time when the overcurrent detection signal SigE indicated that an overcurrent had been detected (detection time tx). The power conversion device 10 of the fourth embodiment including the second arm unit 20 differs from the power conversion device 10 of the fourth embodiment including the first arm unit 20 in the operation of stopping the output of the clamp voltage Vcl. In the power conversion device 10 of the fourth embodiment including the second arm unit 20, the clamp control circuit 48 controls the clamp circuit 42 to reduce the voltage of the drive signal Vout to the clamp voltage Vcl when the overcurrent detection signal SigE indicates the detection of an overcurrent, and controls the clamp circuit 42 to stop outputting the clamp voltage Vcl when a predetermined set condition is satisfied based on the voltage slope Skv. The set condition is satisfied when, after the voltage of the drive signal Vout is limited to the clamp voltage Vcl, a predetermined pulse time Tp has elapsed since the voltage slope Skv, which is the slope with time of the detection voltage Vdet associated with an overcurrent flowing through the target arm 70, becomes larger than a predetermined voltage slope threshold Krefv.

[0152] Next, the operation of the second arm 20 of the fourth embodiment in the event of a type 2 short circuit will be described with reference to Figure 28. Figure 28 shows current characteristics 81 of the collector current Ic, voltage characteristics 82 of the collector-emitter voltage Vce, voltage characteristics 83 of the gate-emitter voltage Vge, signal characteristics 84a of the on-off signal Sig1, signal characteristics 84b of the on-off signal Sig2, signal characteristics 85 of the overcurrent detection signal SigE, voltage slope characteristics 89 of the voltage slope Skv, signal characteristics 87 of the output signal Vk1, and signal characteristics 88 of the breakdown detection signal SigF and the switch drive signal Vsw. In Figure 28, the horizontal axis represents time [s], and the vertical axis of the collector current Ic represents current [A]. The vertical axes of the collector-emitter voltage Vce, gate-emitter voltage Vge, on-off signals Sig1 and Sig2, overcurrent detection signal SigE, output signal Vk1, breakdown detection signal SigF, and switch drive signal Vsw each represent voltage [V]. The vertical axis of the voltage gradient Skv represents voltage gradient [V / s].

[0153] FIG. 28 , which shows the operation of the second arm unit 20, differs from FIG. 26 , which shows the operation of the first arm unit 20, in the voltage slope characteristic 89 of the voltage slope Skv and the signal characteristic 87 of the output signal Vk1 around time t3. In FIG. 28 , which shows the operation of the second arm unit 20, a predetermined pulse time Tp elapses at time t3, and the slope determination signal Sg1 output from the slope detection unit 43 changes from a high voltage to a low voltage. The output signal Vk2 of the AND circuit 45 changes from a high voltage to a low voltage due to the low-voltage output signal Vk1. Because the output signal Vk2 is output as the switch drive signal Vsw and the breakdown detection signal SigF, the switch drive signal Vsw and the breakdown detection signal SigF change from a high voltage to a low voltage at time t3. Similar to the tilt detection unit 43 of the first arm unit 20, the tilt detection unit 43 of the second arm unit 20 adjusts the voltage tilt threshold Krefv to set the rising timing of the tilt determination signal Sg1, and sets the pulse width and falling timing of the tilt determination signal Sg1 using the pulse generation circuit 65. However, since the arm control circuit 14 of the second arm unit 20 does not include a one-shot circuit 46, the rising timing, pulse width, and falling timing of the switch drive signal Vsw and the breakdown detection signal SigF when the on / off signal Sig1 is a high voltage are determined by the overcurrent detection signal SigE and the tilt determination signal Sg1. The rising timing of the switch drive signal Vsw and the breakdown detection signal SigF is determined by the rising timing of the overcurrent detection signal SigE, and the falling timing of the switch drive signal Vsw and the breakdown detection signal SigF is determined by the falling timing of the tilt determination signal Sg1, i.e., the timing at which the pulse time Tp ends.

[0154] The overcurrent detection circuit 25 of the second arm section 20 is the same as the overcurrent detection circuit 25 of the first arm section 20, and includes a slope detection unit 43 that outputs a slope determination signal Sg1 indicating a first state, i.e., a high voltage, during a pulse time Tp elapses from a voltage slope state in which the voltage slope Skv of the detection voltage Vdet, which is the collector-emitter voltage Vce, becomes greater than the voltage slope threshold Krefv. The slope determination signal Sg1 indicates a second state, i.e., a low voltage, when the voltage slope Skv of the detection voltage Vdet has been in the voltage slope state for the pulse time Tp elapses. The clamp control circuit 48 controls the clamp circuit 42 to stop outputting the clamp voltage Vcl based on the slope determination signal Sg1 indicating the second state, i.e., a low voltage, output from the slope detection unit 43 after limiting the voltage of the drive signal Vout to the clamp voltage Vcl. Here, when the above-described set condition is satisfied, the slope determination signal Sg1 output from the slope detection unit 43 indicates the second state, i.e., a low voltage, after limiting the voltage of the drive signal Vout to the clamp voltage Vcl.

[0155] 28 is the same as the period from the left end to time t2 in FIG. 26, except for the operation of clamp control circuit 48. At time t0, power semiconductor element 13 in the target arm, i.e., target arm 70, is on and collector current Ic is flowing, and power semiconductor element 13 in the opposing arm breaks down for some reason, resulting in a type 2 short circuit. After time t0, collector current Ic rises (increases), and collector-emitter voltage Vce increases.

[0156] At time t1, when the voltage slope Skv exceeds the voltage slope threshold Krefv, the determination signal Sg0, which is the output of the comparator 53 of the slope detection unit 43, changes from a low voltage to a high voltage. As the determination signal Sg0 changes to a high voltage, the slope determination signal Sg1 changes from a low voltage to a high voltage. At the inputs of the AND circuit 44 of the clamp control circuit 48, the on / off signal Sig1 is at a high voltage, and the slope determination signal Sg1 is at a high voltage, so the output signal Vk1 changes from a low voltage to a high voltage.

[0157] At time t2, when the collector-emitter voltage Vce exceeds the overcurrent detection threshold Vref3, the overcurrent detection signal SigE, which is the output of the comparator 61 of the overcurrent detection unit 23, changes from a low voltage to a high voltage. This overcurrent detection signal SigE, indicating an overcurrent detection, is input to the on / off determination unit 57 of the drive circuit unit 41, the control circuit 16, and the AND circuit 45 of the clamp control circuit 48. At time t6, which is a delay time Td after time t2, the on / off determination unit 57 of the drive circuit unit 41 changes the on / off signal Sig2 from a high voltage to a low voltage. Time t2 is the time at which the overcurrent detection unit 23 of the overcurrent detection circuit 25 detects an overcurrent in the collector current Ic, i.e., the main current, based on the collector-emitter voltage Vce and outputs the overcurrent detection signal SigE indicating an overcurrent detection, and is therefore the overcurrent detection time tx. Time t6 is the end time ty of the delay time Td. From time t2 to time t6, the arm control circuit 14 outputs a drive signal Vout that maintains the power semiconductor element 13 of the target arm 70 in an on state for a predetermined delay time Td from the detection time tx when the overcurrent detection signal SigE indicates an overcurrent detection.

[0158] Also, at time t2, both inputs of the AND circuit 45 of the clamp control circuit 48 become high voltage, causing the output signal Vk2, which is the output of the AND circuit 45, to change from a low voltage to a high voltage. Since the output signal Vk2 is output as the switch drive signal Vsw and the breakdown detection signal SigF, at time t2, the switch drive signal Vsw changes from a low voltage to a high voltage. The high-voltage switch drive signal Vsw turns on the switch 55 of the clamp circuit 42, causing the gate-emitter voltage Vge to begin to decrease to the clamp voltage Vcl. As the gate-emitter voltage Vge begins to decrease, a sudden increase in the collector current Ic is suppressed, and current stress on the power semiconductor element 13 is alleviated.

[0159] At time t3, after a predetermined pulse time Tp has elapsed, the tilt determination signal Sg1 output from the pulse generating circuit 65 of the tilt detection unit 43 changes from a high voltage to a low voltage. This causes the output signal Vk1 of the AND circuit 44 to change from a high voltage to a low voltage. The output signal Vk2 of the AND circuit 45 changes from a high voltage to a low voltage due to the low-voltage output signal Vk1. Since the output signal Vk2 is output as the switch drive signal Vsw and the breakdown detection signal SigF, the switch drive signal Vsw and the breakdown detection signal SigF change from a high voltage to a low voltage at time t3. Because the switch drive signal Vsw changes from a high voltage to a low voltage, the switch 55 of the clamp circuit 42 changes from an on state to an off state. Therefore, the gate-emitter voltage Vge begins to rise from the clamp voltage Vcl to a positive voltage Vp. Time t2 is the detection time tx and also the clamp start time of the clamp time Tc. Time t3 is the end time of the clamp time Tc, that is, the clamp end time te.

[0160] At time t4, the collector current Ic reaches a peak value and then begins to decrease. From time t4 onward, the collector-emitter voltage Vce begins to rise rapidly. At time t4, the voltage gradient Skv reaches its maximum. Therefore, time t4 is also the time when the voltage gradient is maximum. The gate-emitter voltage Vge decreases from the positive voltage Vp from time t4 to time t5, reaches a minimum value at time t5, and then increases back to the positive voltage Vp. Unlike FIG. 37 , in which the gate-emitter voltage Vge decreases from the clamp voltage Vcl, the power conversion device 10 of the fourth embodiment including the second arm section 20, like the power conversion device 10 of the fourth embodiment including the first arm section 20, decreases the gate-emitter voltage Vge from the positive voltage Vp but does not decrease below the clamp voltage Vcl. This prevents a rapid decrease in the collector current Ic, and also prevents the collector-emitter voltage Vce from decreasing to within the element breakdown voltage Vbr of the power semiconductor element 13.

[0161] At time t6, the delay time Td ends, and the on / off signal Sig2 changes from high to low as indicated by signal characteristic 84b, causing the gate-emitter voltage Vge to start decreasing. Thereafter, the power semiconductor device 13 of the target arm 70 turns off, and the collector current Ic is cut off, i.e., becomes zero.

[0162] As described above, the power conversion device 10 of the fourth embodiment including the second arm unit 20 is configured such that the clamp control circuit 48 determines the clamp end time te of the clamp time Tc based on the slope determination signal Sg1. However, since the configuration other than the clamp control circuit 48 is the same as that of the power conversion device 10 of the fourth embodiment including the first arm unit 20, the power conversion device 10 of the fourth embodiment including the first arm unit 20 achieves the same effects as the power conversion device 10 of the fourth embodiment including the first arm unit 20. Therefore, the power conversion device 10 of the fourth embodiment including the second arm unit 20 can prevent overvoltage breakdown due to a type 2 short circuit or a type 3 short circuit and reliably prevent secondary breakdown of the power semiconductor element 13. Furthermore, the power conversion device 10 of the fourth embodiment including the second arm unit 20 can notify that the paired arm of the arm unit 20 that is paired with the arm unit 20 from which the breakdown detection signal SigF indicating breakdown detection has been output has been broken by transmitting the breakdown detection signal SigF to a higher level of the arm unit 20, such as the control circuit 16. Therefore, the power conversion device 10 of embodiment 4 equipped with the second arm portion 20 can identify the parts including the destroyed arm when the power conversion device 10 fails due to, for example, a type 2 short circuit or a type 3 short circuit, enabling rapid part replacement.

[0163] The power conversion device 10 of the fourth embodiment including the second arm unit 20 differs from the power conversion device 10 of the fourth embodiment including the first arm unit 20 in that the clamp end time te of the clamp time Tc is determined by the slope determination signal Sg1 of the slope detection unit 43 of the overcurrent detection circuit 25. The slope determination signal Sg1 is generated based on the voltage slope Skv, which is the slope of the collector-emitter voltage Vce, and the pulse time Tp. Therefore, the power conversion device 10 of the fourth embodiment including the second arm unit 20 differs from the power conversion device 10 of the fourth embodiment including the first arm unit 20 in that the clamp end time te of the clamp time Tc is determined by the slope determination signal Sg1 of the slope detection unit 43 of the overcurrent detection circuit 25 and the clamp end time te of the clamp time Tc is determined by the pulse time Tp. Therefore, it is possible to reliably prevent overvoltage and secondary breakdown without providing the one-shot circuit 46.

[0164] Next, a third arm unit 20 and a power conversion device 10 according to a fourth embodiment including the third arm unit 20 will be described with reference to FIGS. 29 to 31 . In the power conversion device 10 according to the fourth embodiment including the first arm unit 20, the clamp voltage Vcl of the clamp circuit 42 is set to a fixed value. In the power conversion device 10 according to the fourth embodiment including the third arm unit 20, the clamp voltage source 54 is changed to a variable voltage source 56, and the value of the clamp voltage Vcl is changed based on information about the voltage slope Skv output from the overcurrent detection circuit 25. With this configuration, the power conversion device 10 according to the fourth embodiment including the third arm unit 20 can further suppress abrupt changes in the collector current Ic and overvoltage of the collector-emitter voltage Vce than the power conversion device 10 according to the fourth embodiment including the first arm unit 20.

[0165] The power conversion device 10 of the fourth embodiment having the third arm unit 20 is different from the power conversion device 10 of the fourth embodiment having the first arm unit 20 in that it has a clamp circuit 47 having a variable voltage source 56 instead of the clamp circuit 42 having the clamp voltage source 54, and changes the value of the clamp voltage Vcl based on information on the voltage slope Skv output from the overcurrent detection circuit 25. The following mainly describes the parts that are different from the power conversion device 10 of the fourth embodiment having the first arm unit 20.

[0166] In the third arm unit 20, the slope detection unit 43 outputs information about the voltage slope Skv, and the information about the voltage slope Skv is input to the clamp circuit 47. The clamp circuit 47 operates based on the information about the voltage slope Skv and a switch drive signal Vsw output from a clamp control circuit 48.

[0167] The operation inside the third arm unit 20 in the power conversion device 10 of embodiment 4 will be described. The tilt detection unit 43 of the third arm unit 20 has a configuration similar to that of the tilt detection unit 43 of the first arm unit 20. However, the tilt detection unit 43 of the third arm unit 20 outputs a voltage tilt Skv to a clamp circuit 47. The voltage tilt Skv is input to a variable voltage source 56 in the clamp circuit 47.

[0168] The variable voltage source 56 in the clamp circuit 47 changes the value of the clamp voltage Vcl based on the voltage slope Skv. FIGS. 30 and 31 show examples in which the clamp voltage Vcl has a first clamp voltage value Vcla and a second clamp voltage value Vclb. The second clamp voltage value Vclb is a voltage value greater than the first clamp voltage value Vcla. For example, during the operating period of the clamp circuit 47 in the timing chart of FIG. 31 , i.e., the clamp time Tc, the clamp circuit 47 operates so that the greater the value of the voltage slope Skv, the greater the value of the clamp voltage Vcl. That is, the clamp circuit 47 sets the value of the clamp voltage Vcl to a smaller voltage value as the value of the voltage slope Skv increases, and outputs the clamp voltage Vcl at the set voltage value. In the case of FIG. 31 , the greater the value of the voltage slope Skv, the smaller the value of the first clamp voltage value Vcla, which is the value of the clamp voltage Vcl, and outputs the clamp voltage Vcl at the set voltage value. By doing so, the power conversion device 10 of embodiment 4 equipped with the third arm portion 20 can further reduce stress due to overcurrent than the power conversion device 10 of embodiment 4 equipped with the first arm portion 20.

[0169] Furthermore, the value of the second clamp voltage value Vclb set by the variable voltage source 56 is set to a voltage value greater than the first clamp voltage value Vcla as the value of the voltage slope Skv increases, and the variable voltage source 56 outputs the clamp voltage Vcl of the set voltage value. That is, the larger the value of the voltage slope Skv when the clamp voltage Vcl of the first clamp voltage value Vcla is output, the larger the second clamp voltage value Vclb is set to. By changing the value of the second clamp voltage value Vclb based on the value of the voltage slope Skv, the power conversion device 10 of the fourth embodiment including the third arm unit 20 can further prevent overvoltage breakdown in the event of a Type 2 short circuit and a Type 3 short circuit than the power conversion device 10 of the fourth embodiment including the first arm unit 20.

[0170] In the power conversion device 10 of the fourth embodiment including the first arm unit 20, the switch 55 is turned off at time t3, thereby increasing the gate-emitter voltage Vge to the positive voltage Vp. That is, time t3 was the clamp end time te of the clamp time Tc. Alternatively, the power conversion device 10 of the fourth embodiment including the third arm unit 20 may extend the set time Ts set by the one-shot circuit 46 to time t5 in FIG. 31 and operate to increase the value of the clamp voltage Vcl during the period from time t3 to time t4, when the value of the voltage slope Skv changes from a substantially constant value to its maximum value. In this way, the power conversion device 10 of the fourth embodiment including the third arm unit 20 can prevent overvoltage breakdown in the event of a Type 2 short circuit or a Type 3 short circuit, similar to the power conversion device 10 of the fourth embodiment including the first arm unit 20. Note that time t3 in FIG. 31 is the clamp end time te in FIG. 26 , and is shown for reference. In Figure 31, an example is shown in which the change start time tf, which is the time when the value of the clamp voltage Vcl is changed, is set to the time when the voltage slope Skv becomes an intermediate value between the approximately constant value from time t2 to time t3 and the maximum value at time t4.

[0171] The range of voltage values ​​for changing the clamp voltage Vcl may be higher than the gate threshold voltage of the transistor Tr of the power semiconductor element 13 and within the withstand voltage of the gate-emitter voltage Vge of the power semiconductor element 13, and may be a value greater than the positive voltage Vp. Furthermore, instead of increasing the value of the clamp voltage Vcl, the gate-emitter voltage Vge may be increased by separately providing an active clamp circuit constituted by a Zener diode or the like between the collector terminal C and the gate terminal G, or any circuit that can increase the gate-emitter voltage Vge before an overvoltage of the collector-emitter voltage Vce occurs may be used.

[0172] FIG. 31 illustrates the operation of the third arm 20 of the fourth embodiment during a Type 2 short circuit. Differences from FIG. 26 , which illustrates the operation of the first arm 20, will be mainly described. FIG. 31 illustrates a current characteristic 81 of the collector current Ic, a voltage characteristic 82 of the collector-emitter voltage Vce, a voltage characteristic 83 of the gate-emitter voltage Vge, a signal characteristic 84a of the on-off signal Sig1, a signal characteristic 84b of the on-off signal Sig2, a signal characteristic 85 of the overcurrent detection signal SigE, a voltage slope characteristic 89 of the voltage slope Skv, a signal characteristic 87 of the output signal Vk1, and signal characteristics 88 of the breakdown detection signal SigF and the switch drive signal Vsw. In FIG. 31 , the horizontal axis represents time [s], and the vertical axis of the collector current Ic represents current [A]. The vertical axes of the collector-emitter voltage Vce, gate-emitter voltage Vge, on-off signals Sig1 and Sig2, overcurrent detection signal SigE, output signal Vk1, breakdown detection signal SigF, and switch drive signal Vsw each represent voltage [V]. The vertical axis of the voltage gradient Skv represents voltage gradient [V / s].

[0173] As described above, the set time Ts is the time from time t2 to time t5. During this set time Ts, the clamp control circuit 48 controls the clamp circuit 47 to limit the voltage of the drive signal Vout to the clamp voltage Vcl. After limiting the voltage of the drive signal Vout to the clamp voltage Vcl, the clamp control circuit 48 controls the clamp circuit 47 to stop outputting the clamp voltage Vcl when the set time Ts has elapsed since the time (detection time tx) when the overcurrent detection signal SigE indicates an overcurrent detection, i.e., when the clamp end time te is reached. The period from time t2 to the change start time tf is the first clamp period T3 during which the clamp voltage Vcl of the first clamp voltage value Vcla is output, and the period from the change start time tf to time t5 is the second clamp period T4 during which the clamp voltage Vcl of the second clamp voltage value Vclb is output. When the output of the clamp voltage Vcl is stopped at time t5, the gate-emitter voltage Vge begins to rise to a positive voltage Vp.

[0174] Clamp circuit 47 outputs clamp voltage Vcl from variable voltage source 56, the voltage value of which is set based on information about voltage slope Skv output from overcurrent detection circuit 25. The voltage value of clamp voltage Vcl output from variable voltage source 56 is a first clamp voltage value Vcla at the start of clamping (detection time tx), and is a second clamp voltage value Vclb higher than the first clamp voltage value Vcla from change start time tf during clamping to the end time of set time Ts (clamp end time te). The operation of clamp control circuit 48 can also be expressed as follows. The clamp control circuit 48 controls the clamp circuit 42 to reduce the voltage of the drive signal Vout to the clamp voltage Vcl, and then, when the overcurrent detection signal SigE indicates an overcurrent detection, i.e., when the overcurrent of the main current is determined to be a type 2 short circuit or a type 3 short circuit, controls the clamp circuit 42 to change the clamp voltage Vcl from the first clamp voltage value Vcla at the clamp start indication (detection time tx) to a second clamp voltage value Vclb higher than the first clamp voltage value Vcla. After controlling the clamp circuit 47 to reduce the voltage of the drive signal Vout to the clamp voltage Vcl, if the collector-emitter voltage Vce, which is the voltage between the main terminals, drops to or below the overcurrent detection threshold Vref3 as the collector current Ic, which is the main current, decreases, the overcurrent detection signal SigE changes from a high voltage to a low voltage, and if the overcurrent detection signal SigE indicates that an overcurrent has not been detected, i.e., if the overcurrent of the main current is determined to be other than a Type 2 short circuit or a Type 3 short circuit, the clamp control circuit 48 controls the clamp circuit 42 not to stop outputting the clamp voltage Vcl. Furthermore, if a set time Ts has elapsed since the time (detection time tx) when the overcurrent detection signal SigE indicated that an overcurrent had been detected, i.e., when the clamp end time te has been reached, the clamp control circuit 48 controls the clamp circuit 47 to stop outputting the clamp voltage Vcl, which has been changed to the second clamp voltage value Vclb.

[0175] As described above, the power conversion device 10 of the fourth embodiment including the third arm unit 20 includes the clamp circuit 47 having the variable voltage source 56 and is configured to change the value of the clamp voltage Vcl based on information about the voltage slope Skv output from the overcurrent detection circuit 25. However, other configurations are the same as those of the power conversion device 10 of the fourth embodiment including the first arm unit 20, and therefore the power conversion device 10 of the fourth embodiment including the first arm unit 20 achieves the same effects as the power conversion device 10 of the fourth embodiment including the first arm unit 20. Therefore, the power conversion device 10 of the fourth embodiment including the third arm unit 20 can prevent overvoltage breakdown due to a Type 2 short circuit or a Type 3 short circuit and reliably prevent secondary breakdown of the power semiconductor element 13. Furthermore, the power conversion device 10 of the fourth embodiment including the third arm unit 20 changes the value of the clamp voltage Vcl based on information about the voltage slope Skv output from the overcurrent detection circuit 25, and therefore can further suppress abrupt changes in the collector current Ic and overvoltage in the collector-emitter voltage Vce than the power conversion device 10 of the fourth embodiment including the first arm unit 20.

[0176] Next, a fourth arm unit 20 and a power conversion device 10 according to a fourth embodiment including the fourth arm unit 20 will be described with reference to FIG. 32 . The fourth arm unit 20 according to the fourth embodiment differs from the third arm unit 20 according to the fourth embodiment in that the one-shot circuit 46 is not provided, i.e., the set time Ts of the one-shot circuit 46 is not used, and the clamp end time te of the clamp time Tc is determined by the slope determination signal Sg1 of the overcurrent detection circuit 25. Furthermore, the fourth arm unit 20 according to the fourth embodiment differs from the second arm unit 20 according to the fourth embodiment in that the fourth arm unit 20 includes a clamp circuit 47 having a variable voltage source 56 instead of the clamp circuit 42 having a clamp voltage source 54, and changes the value of the clamp voltage Vcl based on information about the voltage slope Skv output from the overcurrent detection circuit 25. Differences from the second arm unit 20 and the third arm unit 20 will be mainly described. A timing chart illustrating the operation of the fourth arm unit 20 according to the fourth embodiment during a type 2 short circuit is basically the same as that shown in FIG. 28 , and is therefore omitted. However, in the fourth arm section 20, unlike in FIG. 28 where the value of the clamp voltage Vcl is a fixed value, during the period when the clamp circuit 47 is operating, i.e., the period of the clamp time Tc, the larger the value of the voltage slope Skv, the smaller the value of the clamp voltage Vcl is set to a voltage value.

[0177] The clamp circuit 47 of the fourth arm unit 20 includes a variable voltage source 56 that can change the clamp voltage Vcl, and outputs the clamp voltage Vcl from the variable voltage source 56, the voltage value of which is set based on information about the voltage slope Skv output from the overcurrent detection circuit 25. Unlike the clamp circuit 47 of the third arm unit 20, the clamp circuit 47 of the fourth arm unit 20 does not change the voltage value of the clamp voltage Vcl during the clamp time Tc.

[0178] As described above, the power conversion device 10 of the fourth embodiment including the fourth arm unit 20 is configured such that the clamp end time te of the clamp time Tc is determined by the slope determination signal Sg1 of the overcurrent detection circuit 25 without providing the one-shot circuit 46, i.e., without using the set time Ts of the one-shot circuit 46, but the other configuration is the same as that of the power conversion device 10 of the fourth embodiment including the third arm unit 20, and therefore produces the same effects as those of the power conversion device 10 of the fourth embodiment including the third arm unit 20. Furthermore, the power conversion device 10 of the fourth embodiment including the fourth arm unit 20 is provided with the clamp circuit 47 having the variable voltage source 56, and is configured to change the value of the clamp voltage Vcl based on information about the voltage slope Skv output from the overcurrent detection circuit 25, but the other configuration is the same as that of the power conversion device 10 of the fourth embodiment including the second arm unit 20, and therefore produces the same effects as those of the power conversion device 10 of the fourth embodiment including the second arm unit 20. Therefore, the power conversion device 10 of embodiment 4 equipped with the fourth arm portion 20 can prevent overvoltage breakdown due to type 2 short circuit and type 3 short circuit, and can reliably prevent secondary breakdown of the power semiconductor element 13.

[0179] As described above, the power conversion device 10 of the fourth embodiment is a power conversion device that outputs output power Po obtained by power conversion of input power Pi by a power conversion unit 12 having a plurality of power semiconductor elements 13 a to 13 f. The power conversion unit 12 includes a plurality of upper and lower arms 30 a, 30 b, 30 c in which an upper arm having power semiconductor elements 13 a, 13 c, 13 e and a lower arm having power semiconductor elements 13 b, 13 d, 13 f that are controlled so as not to be turned on simultaneously with the upper arm are connected in series, and a plurality of arm control circuits 14 that control the upper arm and the lower arm, respectively. The arm control circuit 14 includes a drive circuit unit 41 that outputs a drive signal Vout to drive a target arm 70, which is the upper arm or lower arm to be controlled; an overcurrent detection circuit 25 that detects that an overcurrent has flowed through the target arm 70 in the ON state based on a voltage slope Skv that is the slope over time of the voltage between the main terminals (collector-emitter voltage Vce) of the target arm 70, and outputs an overcurrent detection signal SigE indicating the detection of an overcurrent; clamp circuits 42, 47 that limit the voltage of the drive signal Vout to a clamp voltage Vcl; and a clamp control circuit 48 that controls the clamp circuits 42, 47. The clamp control circuit 48 controls the clamp circuits 42, 47 to reduce the voltage of the drive signal Vout to the clamp voltage Vcl when the overcurrent detection signal SigE indicates an overcurrent detection, and controls the clamp circuits 42, 47 to stop outputting the clamp voltage Vcl when a predetermined set condition is satisfied based on the voltage slope Skv or when a predetermined set time Ts has elapsed since the time the overcurrent detection signal SigE indicated an overcurrent detection. After the output of the clamp voltage Vcl is stopped, the drive circuit unit 41 changes the voltage of the drive signal Vout to change the target arm 70 from the ON state to the OFF state.With this configuration, the power conversion device 10 of embodiment 4 is equipped with an overcurrent detection circuit 25 that detects that an overcurrent has flowed in the target arm 70, clamp circuits 42, 47 that limit the voltage of the drive signal Vout to the clamp voltage Vcl, and a clamp control circuit 48 that reduces the voltage of the drive signal Vout to the clamp voltage Vcl when the overcurrent detection signal SigE indicates that an overcurrent has been detected, and controls the clamp circuits 42, 47 to stop the output of the clamp voltage Vcl when a set condition is satisfied or when a predetermined set time Ts has elapsed since the time when the overcurrent detection signal SigE indicated that an overcurrent has been detected. Therefore, it is possible to reliably prevent overvoltage breakdown of the power semiconductor elements 13a to 13f due to a Type 2 short circuit or a Type 3 short circuit.

[0180] Although various exemplary embodiments and examples are described in this disclosure, the various features, aspects, and functions described in one or more embodiments are not limited to the application of a particular embodiment, but may be applied to the embodiments alone or in various combinations. Therefore, countless modifications not illustrated are contemplated within the scope of the technology disclosed in this specification. For example, this includes cases where at least one component is modified, added, or omitted, or where at least one component is extracted and combined with components of another embodiment.

[0181] 10...power conversion device, 12...power conversion unit, 13, 13a, 13b, 13c, 13d, 13e, 13f...power semiconductor elements, 14...arm control circuit, 15...overcurrent detection circuit, 25...overcurrent detection circuit, 30a, 30b, 30c...upper and lower arms, 36...negative side wiring, 41...drive circuit unit, 42...clamp circuit, 43...slope detection unit, 47...clamp circuit, 48...clamp control circuit, 53...comparator, 56...variable voltage source, 70...target arm, 82...voltage characteristics (characteristics of voltage between main terminals), Ie...emitter current (main current), Ic...collector current (main current), E...emitter terminal (main terminal), C...collector terminal (main terminal), Krefi... Current slope threshold, Krefv...voltage slope threshold, Pi...input power, Po...output power, Sg0...determination signal, Sg1...slope determination signal, Vout...drive signal, SigE...overcurrent detection signal, SigF...breakdown detection signal, Skd...detection slope, Ski...current slope, Skv...voltage slope, Td...delay time, Tm...current increase time, Ts...setting time, Tp...pulse time, tx...detection time, ty...termination time, tz...maximum voltage slope time, Vce...collector-emitter voltage (voltage between main terminals), Vcl...clamp voltage, Vcla...first clamp voltage value, Vclb...second clamp voltage value, VL...electromotive force, Vdet...detection voltage, Vdeta...detection voltage

Claims

1. A power conversion device that outputs output power obtained by power conversion of input power by a power conversion unit having a plurality of power semiconductor elements, wherein the power conversion unit comprises: a plurality of upper and lower arms in which an upper arm having the power semiconductor elements and a lower arm having the power semiconductor elements controlled so as not to be turned on at the same time as the upper arm are connected in series; and a plurality of arm control circuits that control the upper arm and the lower arm, respectively; the arm control circuit comprises: a drive circuit unit that outputs a drive signal to drive a target arm that is the upper arm or the lower arm to be controlled; an overcurrent detection circuit that uses a current slope that is the slope with time of a main current flowing through the target arm or a voltage slope that is the slope with time of a voltage between the main terminals of the target arm, as a detection slope, and detects that an overcurrent has flowed through the target arm that is in an on state based on the detected slope and outputs an overcurrent detection signal indicating the detection of an overcurrent; a clamp circuit that limits the voltage of the drive signal to a clamp voltage; and a clamp control circuit that controls the clamp circuit; and when the overcurrent detection signal indicates the detection of an overcurrent, the clamp control circuit controls the clamp circuit to reduce the voltage of the drive signal to the clamp voltage, a power conversion device that controls the clamp circuit to stop outputting the clamp voltage when a predetermined setting condition is satisfied based on the detected slope or when a predetermined setting time has elapsed since the time when the overcurrent detection signal indicated the detection of the overcurrent; and after the output of the clamp voltage is stopped, the drive circuit changes the voltage of the drive signal to change the target arm from an on state to an off state.

2. The power conversion device according to claim 1, wherein the detected slope is the current slope, and the set condition is satisfied when, after limiting the voltage of the drive signal to a clamp voltage, the current slope associated with an overcurrent flowing in the target arm passes a predetermined current slope threshold, and the clamp control circuit controls the clamp circuit to stop outputting the clamp voltage when the set condition is satisfied, not when the set time has elapsed.

3. The power conversion device according to claim 1, wherein the detected slope is the voltage slope, and the set condition is satisfied when a predetermined pulse time has elapsed since the voltage slope caused by an overcurrent flowing in the target arm becomes larger than a predetermined voltage slope threshold after the voltage of the drive signal has been limited to a clamp voltage, and the clamp control circuit controls the clamp circuit to stop outputting the clamp voltage when the set condition is satisfied, rather than when the set time has elapsed.

4. The power conversion device according to claim 1, wherein the clamp control circuit controls the clamp circuit to stop outputting the clamp voltage when the set time has elapsed since the time when the overcurrent detection signal indicates the detection of an overcurrent, after limiting the voltage of the drive signal to a clamp voltage, and the set time is set to a time shorter than the time when the main current including the overcurrent flowing through the target arm reaches its maximum value from the time when the overcurrent detection signal indicates the detection of an overcurrent.

5. The power conversion device according to claim 2, wherein the overcurrent detection circuit comprises a slope detection unit that compares the absolute value of the current slope with the absolute value of the current slope threshold, and outputs a slope determination signal that indicates an overcurrent has been detected if the absolute value of the current slope is greater than the absolute value of the current slope threshold, and that indicates no overcurrent has been detected if the absolute value of the current slope is equal to or less than the absolute value of the current slope threshold; and the clamp control circuit limits the voltage of the drive signal to a clamp voltage, and then controls the clamp circuit to stop outputting the clamp voltage based on the slope determination signal that indicates no overcurrent has been detected and is output from the slope detection unit.

6. The power conversion device according to claim 3, wherein the overcurrent detection circuit includes a slope detection unit that outputs a slope determination signal that indicates a first state during the period from a voltage slope state in which the voltage slope becomes larger than the voltage slope threshold until the pulse time has elapsed, and that indicates a second state when the pulse time has elapsed from the voltage slope state, and the clamp control circuit limits the voltage of the drive signal to a clamp voltage, and then controls the clamp circuit to stop outputting the clamp voltage based on the slope determination signal that indicates the second state and is output from the slope detection unit.

7. The power conversion device of claim 1, wherein the clamp control circuit controls the clamp circuit to stop outputting the clamp voltage not when the set condition is satisfied but when the set time has elapsed since the time when the overcurrent detection signal indicates the detection of an overcurrent, after limiting the voltage of the drive signal to a clamp voltage; the overcurrent detection circuit outputs information on the detection slope; the clamp circuit includes a variable voltage source capable of changing the clamp voltage, and outputs the clamp voltage from the variable voltage source, the voltage value of which is set based on the information on the detection slope output from the overcurrent detection circuit; and the voltage value of the clamp voltage output from the variable voltage source is a first clamp voltage value when clamping begins and a second clamp voltage value higher than the first clamp voltage value from the start time of change during clamping to the end time of the set time.

8. The power conversion device according to claim 2, wherein the overcurrent detection circuit outputs information about the current slope, and the clamp circuit includes a variable voltage source capable of changing the clamp voltage, and the clamp voltage, the voltage value of which is set based on the information about the current slope output from the overcurrent detection circuit, is output from the variable voltage source.

9. The power conversion device according to claim 3, wherein the overcurrent detection circuit outputs information about the voltage slope, and the clamp circuit includes a variable voltage source capable of changing the clamp voltage, and the clamp voltage, the voltage value of which is set based on the information about the voltage slope output from the overcurrent detection circuit, is output from the variable voltage source.

10. The power conversion device according to claim 5, wherein the slope detection unit includes a comparator that compares the absolute value of the current slope with the absolute value of the current slope threshold, and outputs the slope determination signal that indicates the detection of an excess when the absolute value of the current slope exceeds the absolute value of the current slope threshold, and that indicates the non-detection of an excess when the absolute value of the current slope is equal to or less than the absolute value of the current slope threshold, and wherein the current slope threshold is set to indicate the non-detection of an excess when the target arm is in an on state or off state of normal operation, and to indicate the detection of an excess when the counter arm, which is the upper arm or the lower arm paired with the target arm, is short-circuited when the target arm is in an on state.

11. The power conversion device according to claim 6, wherein the slope detection unit includes a comparator that compares the voltage slope with the voltage slope threshold and outputs a judgment signal that indicates an excess detection when the voltage slope exceeds the voltage slope threshold and that indicates no excess detection when the voltage slope is equal to or less than the voltage slope threshold, and the voltage slope threshold is set to indicate no excess detection when the target arm is in an on state or off state during normal operation, and to indicate the excess detection when a counter arm, which is the upper arm or the lower arm paired with the target arm, is short-circuited when the target arm is in an on state.

12. A power conversion device according to claim 10 or 11, wherein the arm control circuit outputs a destruction detection signal indicating that the power semiconductor element of the paired arm has been destroyed to a control circuit that controls the power conversion unit when the overcurrent detection signal indicates the overcurrent detection and the tilt determination signal indicates the excess detection.

13. The power conversion device according to claim 7, wherein the detected slope is the current slope, and the first clamp voltage value is set to a smaller voltage value as the absolute value of the current slope increases.

14. The power conversion device according to claim 7, wherein the detected slope is the voltage slope, and the first clamp voltage value is set to a smaller voltage value as the value of the voltage slope increases.

15. The power conversion device according to claim 8, wherein the clamp voltage is set to a smaller voltage value as the absolute value of the current slope increases.

16. The power conversion device according to claim 9, wherein the clamp voltage is set to a smaller voltage value as the value of the voltage gradient increases.

17. The power conversion device according to claim 7 or 13, wherein the detected slope is the current slope, and the second clamp voltage value is set to a larger voltage value as the absolute value of the current slope increases after the polarity of the current slope is reversed from the polarity at which the clamp voltage of the first clamp voltage value is output.

18. The power conversion device according to claim 7 or 14, wherein the detected slope is the voltage slope, and the second clamp voltage value is set to a larger voltage value as the value of the voltage slope when the clamp voltage of the first clamp voltage value is output increases.

19. A power conversion device according to any one of claims 1, 2, 4, 5, 7, 8, 10, 12, 13, 15 and 17, wherein the detection slope is the current slope, and the arm control circuit outputs the drive signal that maintains the power semiconductor element of the target arm in an on state for a predetermined delay time from the detection time when the overcurrent detection signal indicates the detection of the overcurrent, and the end time of the delay time is a time that is equal to or greater than the time when the current slope passes through zero after the detection time and the absolute value of the current slope decreases from its maximum value.

20. The power conversion device according to any one of claims 1, 3, 4, 6, 7, 9, 11, 12, 14, 16 and 18, wherein the detection slope is the voltage slope, and the arm control circuit outputs the drive signal that maintains the power semiconductor element of the target arm in an on state for a predetermined delay time from the detection time when the overcurrent detection signal indicates the detection of the overcurrent, and the end time of the delay time is a time that exceeds the time when the voltage slope reaches its maximum value after the detection time and is equal to or greater than the time when the clamp voltage is stopped.

21. The power conversion device according to any one of claims 1, 3, 4, 6, 7, 9, 11, 12, 14, 16, 18, and 20, wherein the detection slope is the voltage slope, and the overcurrent detection circuit detects that an overcurrent has flowed in the target arm based on characteristics of the voltage between the main terminals when the power semiconductor element is in an on-state.

22. A power conversion device that outputs output power obtained by power conversion of input power by a power conversion unit having a plurality of power semiconductor elements, wherein the power conversion unit comprises: a plurality of upper and lower arms, each of which is connected in series, and each of which has an upper arm having the power semiconductor element and a lower arm having the power semiconductor element controlled so as not to be turned on at the same time as the upper arm; and a plurality of arm control circuits that control the upper arm and the lower arm, respectively; an overcurrent detection circuit that detects an overcurrent flowing in the upper arm or the lower arm in the on state based on a current slope that is the slope with time of a current flowing in a negative side wiring connected to the opposite side of the upper arm of the plurality of lower arms, and outputs an overcurrent detection signal indicating the detection of an overcurrent; the arm control circuit comprises: a drive circuit unit that outputs a drive signal to drive the target arm, which is the upper arm or the lower arm to be controlled; a clamp circuit that limits the voltage of the drive signal to a clamp voltage; and a clamp control circuit that controls the clamp circuit; and when the overcurrent detection signal indicates the detection of an overcurrent, the clamp control circuit controls the clamp circuit to reduce the voltage of the drive signal to the clamp voltage, a power conversion device that controls the clamp circuit to stop outputting the clamp voltage when a predetermined set condition is satisfied based on the current gradient or when a predetermined set time has elapsed since the time when the overcurrent detection signal indicated the overcurrent detection, and the drive circuit unit changes the voltage of the drive signal to change the target arm from an on state to an off state after the output of the clamp voltage is stopped.

23. The power conversion device according to claim 1 or 22, wherein the clamp control circuit controls the clamp circuit to reduce the voltage of the drive signal to the clamp voltage, and then controls the clamp circuit to stop outputting the clamp voltage when the overcurrent detection signal indicates that an overcurrent has been detected.

24. The power conversion device according to claim 1 or 22, wherein the overcurrent detection circuit detects that an overcurrent has flowed through the target arm in the on state due to the current slope and outputs an overcurrent detection signal indicating the detection of an overcurrent, and the clamp control circuit controls the clamp circuit to reduce the voltage of the drive signal to the clamp voltage, and then, when the overcurrent detection signal indicates the detection of an overcurrent, controls the clamp circuit to change the clamp voltage from a first clamp voltage value at the time when clamping began to a second clamp voltage value higher than the first clamp voltage value, and controls the clamp circuit to stop outputting the clamp voltage changed to the second clamp voltage value when the set time has elapsed from the time when the overcurrent detection signal indicated the detection of an overcurrent, not when the set condition is satisfied.

25. The power conversion device according to claim 1, wherein the detection slope is the voltage slope, and wherein the clamp control circuit, after controlling the clamp circuit to reduce the voltage of the drive signal to the clamp voltage, controls the clamp circuit to change the clamp voltage from a first clamp voltage value at the time when clamping began to a second clamp voltage value higher than the first clamp voltage value when the overcurrent detection signal indicates the detection of an overcurrent, and controls the clamp circuit to stop outputting the clamp voltage changed to the second clamp voltage value when the set time has elapsed from the time when the overcurrent detection signal indicates the detection of an overcurrent, not when the set condition is satisfied.

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