Radiation detector and radiation imaging device
The radiation detector optimizes photodiode resets using a control mechanism with multiple reset clocks and a one-shot timer to address inefficiencies in detecting visible light from phosphors, reducing power consumption and improving detection accuracy.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2025-09-02
- Publication Date
- 2026-03-12
AI Technical Summary
Existing radiation detectors using SPAD elements and phosphors face challenges in efficiently resetting photodiodes to detect visible light emitted from phosphors, leading to inefficiencies and increased power consumption due to frequent resets.
A radiation detector with a control mechanism that adjusts the reset operation of avalanche photodiodes based on the detection of avalanche multiplication, using a combination of first and second reset clocks and a one-shot timer circuit to optimize reset frequency according to the burst pattern of visible light emission from phosphors.
This approach reduces power consumption by minimizing unnecessary resets and prevents photon pile-up, enhancing the efficiency and accuracy of radiation detection.
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Figure JP2025030889_12032026_PF_FP_ABST
Abstract
Description
Radiation detector and radiation imaging device
[0001] The present invention relates to a radiation detector. The radiation detector is a device mounted in a radiation imaging apparatus such as a medical diagnostic apparatus or a non-destructive testing apparatus. The radiation imaging apparatus is used as, for example, an X-ray flat panel detector.
[0002] Digital radiography devices are known that detect radiation and obtain a radiation intensity distribution as a radiation image. Recently, a configuration in which a SPAD element, which is sensitive to even a single photon, is applied to a radiography device has been considered.
[0003] A SPAD element uses a reverse-biased avalanche photodiode that is adjusted so that Geiger-mode avalanche multiplication occurs for a single photon. When a photon is incident on the SPAD element, avalanche multiplication occurs in the photodiode, causing a current to flow and dissipating the bias voltage of the photodiode. Patent Document 1 discloses a configuration in which the bias voltage of the photodiode is periodically reset and recharged by controlling the ON / OFF of a transistor.
[0004] A configuration in which a photodiode is formed on a single crystal silicon semiconductor wafer has a characteristic of being highly sensitive in the visible light region, and is therefore unsuitable for detecting radiation such as X-rays. Patent Document 2 discloses a configuration in which a SPAD element is used together with a phosphor that converts radiation into visible light.
[0005] Japanese Patent Laid-Open No. 7-67043 Japanese Patent Laid-Open No. 2016-162772
[0006] When radiation is converted into light using a phosphor as described in Patent Document 2, the phosphor emits multiple visible photons in proportion to the energy of the incident radiation. Because this emission occurs in bursts over a short period of time, it is desirable to appropriately reset the photodiode so that the emitted visible photons can be detected multiple times.
[0007] An object of the present invention is to provide a radiation detector in which the resetting of the photodiode is properly performed when detecting visible light emitted from a phosphor.
[0008] A radiation detector according to the present invention is characterized by comprising: a phosphor that converts radiation into visible light; an avalanche photodiode that detects the visible light; a reset switch that is capable of performing a reset operation by applying a potential to the avalanche photodiode; and control means that controls the reset switch so that the reset operation is performed in accordance with detection of avalanche multiplication in the avalanche photodiode.
[0009] According to the present invention, it is possible to provide a radiation detector in which the photodiode is appropriately reset when detecting visible light emitted from a phosphor.
[0010] 1 is a diagram showing a radiation imaging system; 2 is a diagram showing a radiation imaging device; 3 is a diagram showing a layer structure of a radiation detector; 4 is a diagram showing a pixel configuration; 5 is a diagram explaining the relationship between radiation photons and visible light photons; 6 is a diagram showing the configuration of a single SPAD and peripheral circuits that drive it; 7 is a timing chart showing switching of reset periods in response to incident photons; 8 is a diagram showing the configuration of a plurality of SPADs and peripheral circuits that drive them; and 9 is a timing chart showing switching of reset periods in response to incident photons.
[0011] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The claimed invention is not limited to the configurations described in the embodiments. Modifications such as replacing part of the configuration or part of the processing with equivalents or omitting them may be made within the scope of obtaining similar effects.
[0012] (First embodiment) <Radiation imaging system> A radiation imaging system 1, which is an environment in which a radiation imaging apparatus 10 (radiography apparatus, radiation imaging apparatus) is used, will be described. Fig. 1 is a diagram showing the radiation imaging system.
[0013] The radiation imaging system 1 includes a radiation imaging device 10 (10a, 10b), a control device 20, a radiation generation device 30 (30a, 30b), a display unit 25, an operation unit 26, a RIS 55, a PACS 56, and an HIS 57.
[0014] The control device 20 is a device that relays the radiation imaging device 10, the radiation generating device, and each device that can be connected via the network 50, and performs various controls. The control device 20 controls radiation imaging using the radiation imaging device 10 and the radiation generating device 30.
[0015] The radiation generating device 30 (radiation irradiation device) is equipped with a radiation tube that generates radiation, and irradiates a subject such as a patient with radiation. Here, radiation includes not only X-rays, but also α-rays, β-rays, γ-rays, particle rays, cosmic rays, and the like. The radiation generating device 30a and the radiation generating device 30b are selected and used appropriately depending on the imaging content. Unless otherwise specified, these will be collectively referred to as the radiation generating device 30.
[0016] The radiation imaging device 10 (radiography device, radiation imaging apparatus) is a device that generates an image based on radiation irradiated from a radiation generating device. The radiation imaging device 10 is, for example, a flat panel detector. The radiation imaging device 10a and the radiation imaging device 10b are selected and used appropriately depending on the imaging content. Unless there is a particular preference, these will be collectively referred to as the radiation imaging device 10.
[0017] The radiation imaging device 10 detects radiation that has been irradiated from the radiation generation device 30 and passed through a subject, and outputs image data corresponding to the radiation. Note that the image data can also be referred to as a medical image or a radiological image.
[0018] The display unit 25 is a display device equipped with a monitor such as a liquid crystal display, etc. The operation unit 26 is an input device equipped with a keyboard, a pointing device (for example, a mouse), a touch panel, etc.
[0019] The RIS 55, PACS 56, and HIS 57 are services that cooperate with the control device 20 via a network and expand various functions related to radiography. The control device 20 is also connected to the RIS 55, PACS 56, and HIS 57 via the network 50, allowing for the exchange of radiographic images, patient information, and the like. While FIG. 1 illustrates the radiographic imaging system 1 as including all of the RIS 55, PACS 56, and HIS 57, the system may not include at least some of these. Here, RIS is an abbreviation for Radiology Information Systems (radiology department information system). PACS is an abbreviation for Picture Archiving and Communication Systems (image server). HIS is an abbreviation for Hospital Information Systems (hospital information system).
[0020] 2 is a diagram showing the configuration of the radiation imaging device 10. The radiation imaging device 10 includes a sensor panel 11 (radiation detection panel, radiation detector), a power supply circuit 14, a drive circuit 15, a readout circuit 16, a signal processing unit 17, a control unit 18, and a communication I / F 19.
[0021] The sensor panel 11 has a plurality of pixels (pixel matrix) arranged in a matrix (array) to form a plurality of rows and a plurality of columns.
[0022] The drive circuit 15 is a circuit configured to supply a drive signal to the pixel to be driven in accordance with a control signal from the control unit 18 .
[0023] The readout circuit 16 is a circuit configured to read out signals from a plurality of pixels.
[0024] The signals read out from the pixels are supplied to the signal processing unit 17, where they are subjected to processing such as calculation and storage. The signal processing unit 17 generates a radiographic image based on the read out signals and supplies the generated image to the control unit 18.
[0025] The control unit 18 is a controller that controls the drive circuit 15 and the readout circuit 16 based on information from the signal processing unit 17. The control unit 18 performs overall control of the radiation imaging apparatus 10. The control unit 18 includes a CPU as an arithmetic processing circuit, and ROM and RAM as memories. The control unit 18, for example, loads a program stored in the ROM into the RAM, and the CPU executes this program to realize various controls. Note that the control unit 18 may use an MPU, an ASIC, or the like as an arithmetic processing circuit instead of a CPU.
[0026] The communication I / F 19 is a communication interface for communicating with external devices, and may use a wired LAN (IEEE802.3), a wireless LAN (IEEE802.11), or the like.
[0027] <Sensor Panel> Fig. 3 is a diagram showing the layer structure of the radiation detector, in which the multiple layers constituting the sensor panel 11 are separated from each other and illustrated three-dimensionally.
[0028] The sensor panel 11 includes a phosphor layer 111 and a semiconductor substrate layer 112. The sensor panel 11 has a plurality of pixels 113 arranged in a matrix. For example, in the x direction, the pixels are arranged as pixel 113aa, pixel ab, etc. In the y direction, the pixels are arranged as pixel 113aa, pixel ba, etc. In the figure, only some of the pixels of the sensor panel 11 are shown, and the rest are not shown. By including a large number of such pixels in a matrix, the sensor panel 11 can acquire the intensity distribution of radiation as a radiological image.
[0029] The phosphor layer 111 has phosphors (scintillators) separated into pixel units arranged thereon.
[0030] Various circuits are formed in pixel units on the semiconductor substrate layer 112. In this embodiment, the semiconductor substrate layer 112 has a laminated structure in which multiple layers are stacked. However, the semiconductor substrate layer 112 may be a single layer or three or more layers, taking into consideration the characteristics and degree of integration.
[0031] Of the layers of the semiconductor substrate layer 112, a photodiode semiconductor substrate layer 112-1 is provided as a layer in contact with the phosphor layer 111. A plurality of photodiodes 7 are formed in a matrix on the photodiode semiconductor substrate layer 112-1. In Fig. 3, only some of the photodiodes are shown, and the others are omitted.
[0032] Among the layers of the semiconductor substrate layer 112, a control circuit semiconductor substrate layer 112-2 is provided on the opposite side of the phosphor layer 111, with the photodiode semiconductor substrate layer 112-1 sandwiched therebetween. A plurality of circuits corresponding to pixel circuits are integrated and formed on the substrate of the control circuit semiconductor substrate 112-2. In Figure 3, only some of the pixel circuits are shown, and the rest are omitted.
[0033] <Pixel> FIG. 4 is a diagram showing the configuration of a pixel. As shown in FIG. 4, one pixel 113 is composed of a phosphor cell composed of a phosphor 111-1 and a partition 111-2, and multiple SPAD subpixels 114. One phosphor cell has a structure in which the phosphor 111-1, which converts radiation into visible light, is surrounded by partitions 111-2, which transmit radiation and reflect and block visible light. For ease of explanation, FIGS. 3 and 4 illustrate the partitions 111-2 for each phosphor cell as if they were spatially independent. However, the partitions 111-2 may be formed so as to be continuous across multiple phosphor cells. The multiple phosphor cells connected by the partitions 111-2 may be all or some of the phosphor cells in the phosphor layer 111. For example, multiple phosphor cells are formed by forming multiple recesses in a flat plate, which is the material for the partitions 111-2, and then forming phosphors in these recesses by a method such as vapor deposition.
[0034] In this embodiment, "one pixel" is defined by this structure. Hereinafter, one section separated by the partition 111-2 will be referred to as a "cell." The partition 111-2 has an opening on the bottom side in the figure, to which the semiconductor substrate layer 112 is in contact. A large number of photodiodes are integrated in a matrix on the semiconductor substrate layer 112. Radiation (X-ray photons) incident on the phosphor 111-1 are converted into a large number of visible light photons here. The visible light photons propagate in various directions and are dispersed and emitted in both the left-right and up-down directions. The dispersed visible light photons are reflected by the partition 111-2, and many of them reach the semiconductor substrate layer 112. In this structure, the visible light photons reach multiple photodiodes on the semiconductor substrate layer 112 in a dispersed manner, thereby reducing the possibility of pileup occurring in each photodiode. In this structure, multiple photodiodes are arranged within one pixel, and therefore these photodiodes are also referred to as SPAD subpixels 114. A collection of some or all of the subpixels within the same cell is referred to herein as a subpixel group.
[0035] As described above, the phosphors 111-1 are separated by the partitions 111-2. This reduces the possibility that radiation incident on one cell will affect the subpixel group of another cell. On the other hand, there is a high possibility that multiple visible light photons generated in a cell will simultaneously strike multiple photodiodes within that cell. In this way, subpixel groups have the property of being highly correlated with the operations of the photodiodes within the same cell and being low in correlation between the operations of different cells.
[0036] (Circuit configuration of SPAD) Figure 6 is a diagram showing the configuration of a single SPAD and the peripheral circuitry that drives it. Note that this circuit is just one example. Therefore, the circuit configuration may be changed as long as the desired effect can be obtained. For example, the polarity of the semiconductor and the positive and negative logic of the digital circuit may be reversed.
[0037] The anode side of the photodiode 7 is connected to the power supply VPDL, and the cathode side is connected to the power supply VDD via the reset switch 5. More specifically, the cathode of the photodiode 7 and the input node of the waveform shaping buffer 6 are electrically connected between the semiconductor substrate layer 112-1 and the semiconductor substrate layer 112-2.
[0038] The photodiode 7 is reverse biased deeper than the breakdown voltage due to the potential difference between VDD and VPDL, and enters a state where avalanche breakdown occurs when a single photon is incident on it. A photodiode in this state (avalanche photodiode) is called a single-photon avalanche diode (SPAD).
[0039] After the reset switch 5 is turned on to apply a bias voltage to the photodiode 7, turning the reset switch off completes the state in which the SPAD waits for photon incidence. In this state, the cathode of the photodiode 7 initially maintains the VDD potential, but when charge is suddenly lost due to the incidence of photons, the cathode potential drops. This phenomenon, in which a large potential change can be obtained from the small energy of photons, is called avalanche multiplication. The change in cathode potential due to the occurrence of avalanche multiplication is converted into a digital signal by the wave-shaping buffer 6 and counted by the incidence counter 4. Because the number of photons is counted directly, this operation is called photon counting.
[0040] Once a SPAD has generated avalanche multiplication, the potential difference between its two electrodes drops, and it loses its ability to generate avalanche multiplication. Even if additional incident photons occur during this time, the cathode potential does not fluctuate, so the incident photons cannot be counted. This phenomenon, in which incident photons overlap and are not counted, is called pile-up. To restore sensitivity to incident photons, it is necessary to turn on the reset switch 5 again and apply a reverse bias voltage. In addition to avalanche multiplication, a drop in the potential difference can also occur due to leakage current, etc. Therefore, it is desirable to reset the device at regular intervals, even if avalanche multiplication is not occurring.
[0041] In this way, it is desirable to reset the SPAD in accordance with the interval at which photons are incident. When detecting natural light, the average interval at which incident light is incident can be determined based on the target illuminance, so it is best to reset at intervals that correspond to this. On the other hand, when X-ray photons are converted into visible light photons using phosphor 111-1, the visible light photons are generated in bursts. Therefore, it is desirable to reset at intervals that are appropriate for these bursts.
[0042] FIG. 5 is a diagram illustrating the relationship between radiation photons and visible light photons. In FIG. 5, the vertical axis represents the number of visible light photons, and the horizontal axis represents the passage of time. As shown in FIG. 5, after the burst ends, there is a period during which no visible light photons are incident on the SPAD until the next X-ray photon is incident. During this period, there is no problem even if the reset of the SPAD is omitted. If the reset can be omitted, a reduction in power consumption can be expected. A mechanism for omitting the reset of the SPAD will be explained below using FIG. 6.
[0043] The pixel circuit of FIG. 6 is supplied with a first reset clock (Leak.reset.clock in the figure) having a long period and a second reset clock (Sample.reset.clock in the figure) having a short period. These clocks are supplied by respective clock circuits (not shown). The second reset clock has a period that allows a burst of visible light photons to be captured without pileup. The first reset clock has a period that is sufficient to periodically compensate for a decrease in reverse bias voltage due to leakage. This pixel circuit also includes a one-shot timer circuit 3 that is activated when an incident pulse is detected after avalanche multiplication. The one-shot timer may be realized by some circuit time constant or by counting the second reset clock. It may also be determined according to a separate clock (not shown). Regardless of the method used, the length of the one-shot timer is set to simulate the length of light emission from the phosphor. That is, the one-shot timer is started by the start of the burst light emission of the phosphor and ends at the estimated timing of the end of the burst light emission. The output of the one-shot timer is input to a clock selection circuit composed of an AND circuit and a NOR circuit. The output of the clock selection circuit is supplied to a reset switch 5, which controls the reset of the SPAD.
[0044] The operation of the pixel circuit of Fig. 6 will be described with reference to Fig. 7. Fig. 7 is a timing diagram showing switching of the reset period in response to the incidence of photons.
[0045] In FIG. 7, the horizontal axis represents time, progressing in the order of "T1," "T2," "T3," and "T4." In FIG. 7, "Leak.reset.clock" represents the behavior of the first reset clock. "Sample.reset.clock" represents the behavior of the second reset clock. In this example, the ratio between the periods of the first reset clock and the second reset clock is set to 5:1, but other ratios may be used. "Photon incident" represents the incidence of a visible light photon. "PD Vcathode" represents the cathode potential. "Buffer output" represents the output of the waveform shaping buffer 6. "Timer output" represents the output of the one-shot timer circuit 3. "Reset Tr.ON state" represents the conduction or non-conduction of the reset switch 5. It should be noted that the figure shows whether the reset switch 5 is conductive or not, and does not show the voltage of the gate electrode of the PMOS switch.
[0046] While no photons are incident on the SPAD, the second reset clock is masked by the AND circuit and does not reach the reset switch 5, and only the first reset clock is supplied to the reset switch 5. In this way, the first reset clock drives the reset switch 5 even when no photons are incident, so that the decrease in bias voltage is periodically compensated for (T1).
[0047] When a photon is incident on the SPAD, the photodiode 7 generates an avalanche multiplication, causing a current to flow and a drop in the cathode potential. The drop in the cathode potential is shaped by the wave-shaping buffer 6 while being logically inverted, generating a positive edge. This edge is counted by the incidence counter and also serves as a trigger to start the one-shot timer circuit 3 (T2).
[0048] The activated one-shot timer circuit 3 continues to output an H level. This output is supplied to the AND circuit, which masks the second reset clock. The AND circuit receives the output of the one-shot timer circuit 3 and unmasks the second reset clock. As a result, the second reset clock passes through the AND circuit and reaches the input of the NOR circuit. The NOR circuit mixes the first reset clock and the unmasked second reset clock, and supplies the result to the reset switch 5. This shortens the operating cycle of the reset switch 5, and the photodiode 7 is quickly reset after a photon is incident. When the cathode potential returns to its original state due to the reset, the output of the waveform shaping buffer 6 also returns to L. Thus, the system returns to a state of waiting for the next photon to be incident (T3).
[0049] After that, the one-shot timer circuit 3 continues to output an H level, and during that time, the reset switch 5 operates at a short cycle based on the second reset clock, regardless of whether photons are incident or not. During this period, the pixel circuit operates to reduce the possibility of pile-up, at the expense of increased power consumption due to frequent resets. Therefore, multiple reset operations are performed in response to the detection of a single avalanche multiplication. The duration (predetermined period) of the one-shot timer circuit 3 is set taking into account the time constant of the phosphor, and the output is stopped at the timing (decay time) when the burst emission is expected to end (T4).
[0050] When the output of the one-shot timer circuit 3 stops, the operating cycle of the reset switch 5 returns to the long cycle based on the first reset clock, and power consumption decreases.
[0051] In this embodiment, the circuit of FIG. 6 is configured to switch whether or not to mix the second reset clock with the first reset clock, but this is not limited to this, and a configuration in which only one of the clocks is selected using a multiplexer is also possible.
[0052] As described above, according to this embodiment, the reset frequency of the SPAD can be increased only during the necessary period and can be decreased during other periods, thereby making it possible to avoid constantly high-frequency resets and thereby reducing power consumption.
[0053] (Example 2) Next, the configuration of Example 2 will be described. Example 2 differs from Example 1 in that a timer circuit is shared among multiple photodiodes. Note that, except for the parts related to the above-mentioned characteristics, the configuration of the sensor panel 11 appearing in Example 2 is the same as the configuration of the sensor panel 11 in Example 1. Therefore, the same reference numerals are used for the common components, and detailed descriptions thereof will be omitted.
[0054] FIG. 8 shows an embodiment that focuses on the correlation between the operations of photodiodes within a group. FIG. 8 illustrates the configuration of multiple SPADs and the peripheral circuits that drive them. On the left side of FIG. 8, there is a phosphor 111-1 surrounded by a partition wall 111-2, which converts incident X-ray photons into multiple visible light photons. A photodiode semiconductor substrate layer 112-1 is laminated on the phosphor 111-1, and multiple photodiodes, such as photodiodes 7a and 7b, are formed on the substrate. A control circuit semiconductor substrate 112-2 is in contact with the surface of the photodiode semiconductor substrate layer 112-1 opposite the phosphor 111-1 side. Multiple circuits equivalent to the pixel circuits in FIG. 6 are integrated and formed on the control circuit semiconductor substrate 112-2. Specifically, a timer circuit 3, incident count counters 4a and 4b, reset switches 5a and 5b, and waveform shaping buffers 6a and 6b are provided on the control circuit semiconductor substrate 112-2.
[0055] Next, we will explain the differences between the circuit in FIG. 8 and that in FIG. 6 . In FIG. 6 , the one-shot timer circuit 3 and the clock mixing AND / NOR circuits are provided in one-to-one correspondence with the photodiodes 7. In contrast, the circuit in FIG. 8 does not have such a configuration. Instead, the one-shot timer circuit 3 and the clock mixing circuit are shared by multiple (two in the example in FIG. 8 ) subpixel circuits belonging to the same subpixel group. Pulses from multiple subpixel circuits are input to the one-shot timer circuit 3, and these pulses can be combined to determine the timer activation conditions. As mentioned above, there is a correlation between incident photons within the same cell. Therefore, if an incident photon is detected somewhere within the group, there is a high probability that incident photons will also occur in other subpixels within the group. Therefore, when an incident photon is detected in one subpixel, reset operations can be quickly initiated in the other subpixels. This reduces photon detection misses due to pileup in each subpixel. Another advantage is that each subpixel circuit does not need to have its own timer, which reduces the circuit size.
[0056] The one-shot timer circuit 3 can also perform more advanced decision-making and control by monitoring signals from multiple subpixel circuits. For example, if a signal is detected in only a few subpixels when the timer is not running, it can be assumed that this is not due to photon incidence but rather to breakdown due to dark current, and normal timer startup (execution of the first mode) can be avoided. In this case, the timer is started (execution of the second mode) for only one period of the second reset clock, which has a shorter cycle, to reset the photodiode only once and return to a standby state. FIG. 9 is a timing diagram showing switching of the reset cycle in response to photon incidence. In FIG. 9, the horizontal axis represents the time axis. "Sample.reset.clock" indicates the state of the second reset clock. "Photon incident A," "Photon incident B," and "Photon incident C" indicate the incidence of visible light photons. "Timer output" indicates the output of the one-shot timer circuit 3. "Reset Tr. ON state" indicates whether the reset switch 5 is conductive or not. As shown in FIG. 9, when a small number of incident photons are detected at a specific timing, the second mode is executed and the one-shot timer circuit 3 outputs for a short period. When a large number of incident photons are detected, the first mode is executed and the one-shot timer circuit 3 outputs for a long period.
[0057] In consideration of the case where some sub-pixels fall into a defective mode in which they constantly output signals, the one-shot timer circuit 3 may have programmability that allows it to cut off some of the inputs.
[0058] As described above, according to this embodiment, the number of one-shot timer circuits 3 can be reduced relative to the number of photodiodes. Furthermore, the one-shot timer circuits 3 can be operated based on the detection results of a plurality of photodiodes.
[0059] (Other Examples) The present invention is not limited to the above examples, and various modifications (including organic combinations of the examples) are possible based on the spirit of the present invention, and these are not excluded from the scope of the present invention.
[0060] The processor or circuitry may include a central processing unit (CPU), a microprocessing unit (MPU), a graphics processing unit (GPU), an application specific integrated circuit (ASIC), a field programmable gateway (FPGA), a digital signal processor (DSP), a data flow processor (DFP), or a neural processing unit (NPU).
[0061] In the above-described embodiment, a configuration in which a large number of sub-pixels are provided in one cell has been described, but a configuration in which only one pixel is provided in one cell may also be used.
[0062] In the above-described embodiment, an example in which only one subpixel group exists in a cell has been described, but the pixel configuration is not limited to this. One pixel may have multiple subpixel groups that are separated by position within the cell, etc.
[0063] In the above-described embodiment, the partition walls 111-2 reflect visible light, but this is not the only possible configuration. The partition walls 111-2 may be adjusted to absorb visible light, or may have a structure that selectively reflects and absorbs light depending on the location. The required property of the partition walls 111-2 is that the fluorescence does not affect other cells.
[0064] In the above-described embodiment, the structure of the phosphor cell in which the phosphor is separated for each pixel has been described, but a phosphor that spans a plurality of pixels may also be used.
[0065] In the above-described embodiment, the incident number counter is provided for each pixel in FIG. 8 , but the present invention is not limited to this configuration. For example, a counter that collectively counts the number of incidents in a subpixel group may be provided for each subpixel group. Furthermore, a structure may be adopted in which the same cell has multiple subpixel groups and the incident number counter collectively counts the number of incidents in the cell.
[0066] (Additional Note) The disclosure of this embodiment includes the following contents.
[0067] [Supplementary Note 1] A radiation detector comprising: a phosphor that converts radiation into visible light; an avalanche photodiode that detects the visible light; a reset switch that is capable of performing a reset operation by applying a potential to the avalanche photodiode; and control means that controls the reset switch so that the reset operation is performed in accordance with detection of avalanche multiplication in the avalanche photodiode.
[0068] [Supplementary Note 2] The radiation detector according to Supplementary Note 1, wherein the control means controls the reset switch so that the reset operation is performed multiple times based on one detection of the avalanche multiplication.
[0069] [Supplementary Note 3] The radiation detector according to Supplementary Note 1 or 2, wherein the reset switch performs the reset operation in response to a reset clock being supplied.
[0070] [Supplementary Note 4] The radiation detector according to any one of Supplementary Notes 1 to 3, wherein the control means supplies one reset clock to the reset switch from among a plurality of reset clocks including a first reset clock and a second reset clock having a shorter period than the first reset clock.
[0071] [Supplementary Note 5] The radiation detector according to Supplementary Note 4, further comprising: a first clock circuit for supplying the first reset clock; and a second clock circuit for supplying the second reset clock.
[0072] [Supplementary Note 6] The radiation detector according to Supplementary Note 4 or 5, wherein the control means supplies the second reset clock to the reset switch for a predetermined period after the avalanche multiplication is detected, and supplies the first reset clock to the reset switch for a period different from the predetermined period.
[0073] [Supplementary Note 7] The radiation detector according to Supplementary Note 6, further comprising a timer circuit that is activated when avalanche multiplication occurs in the avalanche photodiode and operates only for the predetermined period, wherein the control means supplies the first reset clock to the reset switch while the timer circuit is not operating, and supplies the second reset clock to the reset switch while the timer circuit is operating.
[0074] [Supplementary Note 8] The radiation detector according to Supplementary Note 6 or 7, wherein the predetermined period is a period determined in accordance with the decay time of the light emitted by the phosphor.
[0075] [Supplementary Note 9] The radiation detector according to any one of Supplementary Notes 1 to 8, wherein a plurality of sets of the avalanche photodiode and the reset switch are arranged in an array.
[0076] [Supplementary Note 10] The radiation detector according to any one of Supplementary Notes 1 to 9, wherein the phosphor has a cell structure separated by partitions that block or reflect the visible light, and a plurality of phosphors are arranged in an array.
[0077] [Supplementary Note 11] The radiation detector according to any one of Supplementary Notes 1 to 10, wherein the cell structure of the phosphor is such that one cell is provided for one pixel.
[0078] [Supplementary Note 12] The radiation detector according to Supplementary Note 11, wherein a plurality of sets of the avalanche photodiode and the reset switch are arranged as subpixels within the range of one cell.
[0079] [Supplementary Note 13] The radiation detector according to Supplementary Note 11, characterized in that a group of subpixels arranged within the range of one cell share one timer circuit, and the timer circuit is activated in response to a trigger when any of the plurality of avalanche photodiodes belonging to the subpixel group undergoes the avalanche multiplication.
[0080] [Supplementary Note 14] The radiation detector according to Supplementary Note 13, wherein the timer circuit has a plurality of modes including a first mode in which it operates for a predetermined period of time and a second mode in which it operates for a period shorter than that of the first mode, and the timer circuit determines in which of the plurality of modes it will operate in according to a result of monitoring states of the plurality of avalanche photodiodes belonging to the group of subpixels.
[0081] [Supplementary Note 15] The radiation detector according to any one of Supplementary Notes 1 to 14, wherein a radiation image is obtained based on outputs from a plurality of pixels.
[0082] [Appendix 16] A radiation imaging device comprising: a phosphor that converts radiation into visible light; an avalanche photodiode that detects the visible light; a reset switch that is capable of performing a reset operation by applying a potential to the avalanche photodiode; and control means that controls the reset switch so that the reset operation is performed in accordance with detection of avalanche multiplication in the avalanche photodiode.
[0083] The present invention is not limited to the above-described embodiments, and various modifications and variations can be made without departing from the spirit and scope of the present invention. Therefore, the following claims are appended to apprise the public of the scope of the present invention.
[0084] This application claims priority based on Japanese Patent Application No. 2024-152993, filed September 5, 2024, the entire contents of which are incorporated herein by reference.
Claims
1. A radiation detector comprising: a phosphor that converts radiation into visible light; an avalanche photodiode that detects the visible light; a reset switch that is capable of performing a reset operation by applying a potential to the avalanche photodiode; and control means that controls the reset switch so that the reset operation is performed in accordance with the detection of avalanche multiplication in the avalanche photodiode.
2. A radiation detector according to claim 1, wherein said control means controls said reset switch so that said reset operation is performed a plurality of times based on one detection of said avalanche multiplication.
3. The radiation detector according to claim 1, wherein the reset switch performs the reset operation in response to a reset clock being supplied.
4. A radiation detector as described in claim 3, characterized in that the control means supplies one reset clock to the reset switch from among a plurality of reset clocks including a first reset clock and a second reset clock having a shorter period than the first reset clock.
5. A radiation detector according to claim 4, further comprising a first clock circuit for supplying said first reset clock, and a second clock circuit for supplying said second reset clock.
6. The radiation detector of claim 4, wherein the control means supplies the second reset clock to the reset switch for a predetermined period after the avalanche multiplication is detected, and supplies the first reset clock to the reset switch for a period different from the predetermined period.
7. A radiation detector as described in claim 6, further comprising a timer circuit that is activated when avalanche multiplication occurs in the avalanche photodiode and operates only for the specified period, wherein the control means supplies the first reset clock to the reset switch while the timer circuit is not operating, and supplies the second reset clock to the reset switch while the timer circuit is operating.
8. A radiation detector according to claim 6 or 7, wherein the predetermined period is determined in accordance with the decay time of the light emitted by the phosphor.
9. The radiation detector according to claim 1, wherein a plurality of sets of the avalanche photodiode and the reset switch are arranged in an array.
10. The radiation detector according to claim 1, wherein the phosphor has a cell structure separated by partitions that block or reflect the visible light, and a plurality of phosphors are arranged in an array.
11. The radiation detector according to claim 10, wherein the phosphor cell structure is such that one cell is provided for one pixel.
12. The radiation detector according to claim 11, wherein a plurality of sets of the avalanche photodiode and the reset switch are arranged as subpixels within the range of one cell.
13. The radiation detector according to claim 11, characterized in that a group of subpixels arranged within the range of one cell share one timer circuit, and the timer circuit is activated in response to a trigger when any of the plurality of avalanche photodiodes belonging to the subpixel group undergoes avalanche multiplication.
14. The radiation detector of claim 13, wherein the timer circuit has a plurality of modes including a first mode in which it operates for a predetermined period of time and a second mode in which it operates for a period shorter than the first mode, and the timer circuit determines which of the plurality of modes to operate in depending on the result of monitoring the states of the plurality of avalanche photodiodes belonging to the group of subpixels.
15. The radiation detector according to claim 1, wherein a radiation image is obtained based on outputs from a plurality of pixels.
16. A radiation imaging device comprising: a phosphor that converts radiation into visible light; an avalanche photodiode that detects the visible light; a reset switch that is capable of performing a reset operation by applying a potential to the avalanche photodiode; and control means that controls the reset switch so that the reset operation is performed in accordance with detection of avalanche multiplication in the avalanche photodiode.
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