Image sensor, control method for image sensor, and vehicle

Abstract

An image sensor, a control method for an image sensor, and a vehicle. The image sensor comprises a pixel circuit and a functional circuit, wherein the pixel circuit comprises a pixel array, and the pixel array comprises pixel cells arranged in multiple rows and multiple columns; and the functional circuit is connected to the pixel cells in the pixel array.

Description

Image sensor, image sensor control method, and vehicle

[0001] The present application claims priority to Chinese Patent Application No. 202411273967.7, filed on September 11, 2024, Chinese Patent Application No. 202411277165.3, filed on September 11, 2024, Chinese Patent Application No. 202411275025.2, filed on September 11, 2024, and Chinese Patent Application No. 202411276610.4, filed on September 11, 2024, the contents of which are incorporated herein by reference in their entirety. TECHNICAL FIELD

[0002] The present disclosure relates to the technical field of image sensing, and in particular, to an image sensor, an image sensor control method, and a vehicle. BACKGROUND

[0003] In the related art, an image sensor processes an analog pixel signal of a row of pixel units in a pixel array in each cycle, i.e., reads out the analog pixel signal of a column of pixel units row by row and converts it into a digital pixel signal. SUMMARY

[0004] In one aspect, an image sensor is provided, including a pixel circuit and a function circuit. The pixel circuit includes a pixel array including pixel units arranged in multiple rows and multiple columns. The function circuit is connected to the pixel units in the pixel array.

[0005] In another aspect, a control method of an image sensor is provided, the image sensor including a plurality of pixel units including a plurality of photodiodes, the method including: outputting an image signal based on a target pixel readout mode, the image sensor including a plurality of pixel readout modes, at least one of an exposure time, a gain, and a number of enabled photodiodes of any two of the plurality of pixel readout modes being different, the target pixel readout mode being at least one of the plurality of pixel readout modes.

[0006] In yet another aspect, a vehicle is provided, including the image sensor described above. BRIEF DESCRIPTION OF DRAWINGS

[0007] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the related art, a brief introduction will be given to the drawings needed to be used in the embodiments description.

[0008] FIG. 1 is a structural schematic diagram of an image sensor according to some embodiments;

[0009] FIG. 2 is a schematic diagram of a pixel readout scheme according to some embodiments;

[0010] FIG. 3 is a schematic diagram of a system architecture of an image sensor according to some embodiments;

[0011] FIG. 4 is a schematic diagram of a structure of a row exchange circuit according to some embodiments;

[0012] FIG. 5 is a schematic diagram of row exchange switch control signals according to some embodiments;

[0013] FIG. 6 is a schematic diagram of a row exchange pixel readout scheme under the control signals shown in FIG. 5;

[0014] FIG. 7 is a schematic diagram of row exchange switch control signals according to some embodiments;

[0015] FIG. 8 is a schematic diagram of a row exchange pixel readout scheme under the control signals shown in FIG. 7;

[0016] FIG. 9 is a flowchart of an image signal conversion method according to some embodiments;

[0017] FIG. 10 is a schematic diagram of a structure of an image sensor according to some embodiments;

[0018] FIG. 11 is a schematic diagram of another structure of an image sensor according to some embodiments;

[0019] FIG. 12 is a schematic diagram of a structure of a first pixel unit and a first analog-to-digital converter group according to some embodiments;

[0020] FIG. 13 is a schematic diagram of a structure of a second pixel unit and a second analog-to-digital converter group according to some embodiments;

[0021] FIG. 14 is a schematic diagram of a structure of an analog-to-digital converter according to some embodiments;

[0022] FIG. 15 is a flowchart of a pixel signal conversion method according to some embodiments;

[0023] FIG. 16 is a plan view of a first substrate and a second substrate of an image sensor according to some embodiments;

[0024] FIG. 17 is a schematic diagram of a connection of a detection circuit, an image processing circuit, and a row driving circuit of an image sensor according to some embodiments;

[0025] FIG. 18 is a detection flowchart of a pulse detection sub-circuit according to some embodiments;

[0026] FIG. 19 is another detection flowchart of a pulse detection sub-circuit according to some embodiments;

[0027] FIG. 20 is a waveform diagram of a pulse command signal, a first control signal, and a detection pulse signal according to some embodiments;

[0028] FIG. 21 is a structure diagram of a pulse detection sub-circuit according to some embodiments;

[0029] FIG. 22 is a structure diagram of a conversion sub-circuit according to some embodiments;

[0030] FIG. 23 is a detection flowchart of a row selection detection sub-circuit according to some embodiments;

[0031] FIG. 24 is a structure diagram of a pixel unit of an image sensor according to some embodiments;

[0032] FIG. 25 is a partial structure diagram of an image sensor according to some embodiments;

[0033] FIG. 26 is a first flowchart of a control method of an image sensor according to some embodiments;

[0034] FIG. 27 is a second flowchart of a control method of an image sensor according to some embodiments;

[0035] FIG. 28 is a first control timing diagram of an image sensor according to some embodiments;

[0036] FIG. 29 is a second control timing diagram of an image sensor according to some embodiments;

[0037] FIG. 30 is a block diagram of a control device according to some embodiments;

[0038] FIG. 31 is a structure diagram of an image acquisition apparatus according to some embodiments;

[0039] FIG. 32 is a block diagram of a vehicle according to some embodiments.

[0040] Reference signs: 1000-vehicle; 100-image sensor; 200-pixel circuit; 300-logic circuit; 10-pixel array; 11-pixel unit column; 111-first column line; 112-second column line; 113-first pixel unit; 114-second pixel unit; 20-first analog-to-digital converter group; 30-second analog-to-digital converter group; 40-first wafer; 41-center region; 42-second connection point; 43-first connection point; 43-first connection point; 50-second wafer; 51-third connection point; 52-fourth connection point; 60-row control circuit; 61-row control line; 80-column readout and control circuit; 81-column control line; 1-flip-flop; 2-logic gate circuit; 3-buffer; Q1-first transistor; Q2-second transistor; 600-control device; 301-determination component; 302-output component; 400-image acquisition apparatus; 401-control circuit. DETAILED DESCRIPTION

[0041] The technical solutions in the embodiments of the present disclosure will be described clearly and completely below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the protection scope of the present disclosure.

[0042] The terms "first", "second", and the like in the specification and claims of the present disclosure are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be exchanged under appropriate circumstances, so that the embodiments of the present disclosure can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally a category and do not limit the number of objects, for example, the first object can be one or more.

[0043] In addition, "and / or" in the specification and claims indicates at least one of the connected objects, and the character " / " generally indicates that the front and rear associated objects are in an "or" relationship. In the description of the present disclosure, unless otherwise specified, the meaning of "multiple" is two or more.

[0044] In the description of the present disclosure, it should be understood that the terms "upper", "lower", "left", "right", "front", "back", "inner", "outer", and the like indicate the orientation or positional relationship shown in the drawings, and are only used to facilitate the description of the present disclosure and simplify the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure. Unless otherwise specified, the above orientation description can be flexibly arranged in the process of actual application under the condition of meeting the relative positional relationship shown in the drawings.

[0045] It should be noted that, in the present document, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the presence of additional identical elements in the process, method, article, or apparatus that comprises the element. Furthermore, it should be noted that the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. In addition, it should be noted that the scope of the methods and apparatus of the present embodiments are not limited by the order of the steps or the order of the components, and the present embodiments can include additional or fewer steps or components, or different orders of the steps or components, depending on the implementation.

[0046] In the description of the present disclosure, it should be noted that, unless specifically defined and limited otherwise, the terms "mount", "connected", "connection", "communicate" should be understood broadly, for example, can be fixed connection, can also be detachable connection, or integrally connected. It can be directly connected, or indirectly connected through an intermediate medium, and it can be the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present disclosure can be understood according to the specific circumstances.

[0047] In the present embodiments, the terms "comprise", "comprising", or any other variations thereof, are intended to cover non-exclusive inclusion, so that the process, article or apparatus comprising a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, article or apparatus. Without more restrictions, the element defined by the sentence "comprises a" does not exclude the presence of additional identical elements in the process, article or apparatus comprising the element.

[0048] In the present embodiments, the words "exemplary" or "for example" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "for example" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the words "exemplary" or "for example" is intended to present concepts in a concrete manner.

[0049] In the description of the specification, specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0050] Embodiments of the present disclosure are described below in detail, examples of which are shown in the drawings, wherein the same or similar notations represent the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the drawings are exemplary only, and are for the purpose of explanation of the present disclosure, and are not to be understood as limiting the present disclosure. A complementary metal-oxide semiconductor image sensor (CIS) in the related art generally converts and reads one row at a time for one frame of image during image reading, resulting in low efficiency of image conversion and reading.

[0051] Referring to FIG. 1, some embodiments of the present disclosure provide an image sensor 100, which includes oppositely arranged pixel circuit 200 and functional circuit, the functional circuit including logic circuit 300.

[0052] The pixel circuit 200 includes a pixel array 10 located in a central region of the pixel circuit 200 and a first peripheral circuit 22 located on at least one side of the pixel array 10. The first peripheral circuit 22 can be arranged around the pixel array 10. A pixel is the smallest light sensing unit of an image sensor, and the pixel array is arranged together to form the light sensing region of the image sensor. For example, referring to FIG. 1, the pixel array is an active pixel array. The pixel array described in embodiments of the present disclosure can be understood as the number of effective pixels, i.e., the pixels in the CIS that can effectively perform photoelectric conversion and output image signals, which is an important technical indicator for measuring the CIS.

[0053] The pixel circuit 200 includes a pixel array 10, and the pixel array 10 includes pixel units arranged in multiple rows and multiple columns. The logic circuit 300 includes at least two groups of analog-to-digital converters, and the pixel units in the pixel array 10 are connected to the at least two groups of analog-to-digital converters. The image sensor 100 further satisfies at least one of the following: pixel units in the same row and different columns of the pixel array 10 are connected to the at least two groups of analog-to-digital converters, and pixel units in the same column and different rows of the pixel array are connected to the at least two groups of analog-to-digital converters.

[0054] In embodiments of the present disclosure, two groups of analog-to-digital converters can be provided to simultaneously convert image data corresponding to two rows of pixel units, three groups of analog-to-digital converters can be provided to simultaneously convert image data corresponding to three rows of pixel units, four groups of analog-to-digital converters can be provided to simultaneously convert image data corresponding to four rows of pixel units, or more analog-to-digital converters can be provided, which are not limited in embodiments of the present disclosure. It should be noted that each group of analog-to-digital converters corresponds to a group of row exchange switches.

[0055] Referring to FIGS. 1-3, in the embodiments of the present disclosure, taking the logic circuit including two groups of analog-to-digital converters as an example for illustration. The logic circuit 300 includes: a first group of analog-to-digital converters 31 and a second group of analog-to-digital converters 32 arranged in parallel, a row decoder (RDEC) 33 located on one side of the first group of analog-to-digital converters 31, and a second peripheral circuit 34 located on at least one side of the first group of analog-to-digital converters, a first group of row switching switches 35, and a second group of row switching switches 36.

[0056] The row decoder 33 is electrically connected with the pixel array 10, the pixel array 10 is electrically connected with the first group of analog-to-digital converters 31 through the first group of row switching switches 35, and the pixel array 10 is electrically connected with the second group of analog-to-digital converters 32 through the second group of row switching switches 36, so that the image signals in the pixel array 10 are simultaneously output to the first group of analog-to-digital converters 31 and the second group of analog-to-digital converters 32.

[0057] The pixel circuit 200 and the logic circuit 300 are electrically connected with each other through the first peripheral circuit 22 and the second peripheral circuit 34.

[0058] In the embodiments of the present disclosure, the first group of analog-to-digital converters 31 can be composed of a group of column parallel analog-to-digital converters (ADCs), and similarly, the second group of analog-to-digital converters 32 can also be composed of a group of column parallel ADCs, each ADC corresponding to a column of pixel units.

[0059] In the embodiments of the present disclosure, in the active pixel array of the pixel chip (Pixel Wafer), the photoelectric conversion element and the pixel circuit will be designed as a two-dimensional matrix structure. The logic circuit including the analog-to-digital converter ADC is placed in the logic area of the logic chip (Logic Wafer). The vertical contacts for connecting the two chips can be arranged in the peripheral area to electrically connect the Pixel Wafer and the Logic Wafer with each other.

[0060] The image sensor provided by the present disclosure can simultaneously select two rows of pixel units and output the image signals collected by the two rows of pixel units to two groups of analog-to-digital converters, thereby at least solving the problem of low efficiency caused by outputting only one row of image signals at a time in the related art, improving the conversion and quantization speed of the image signals, and simultaneously improving the frame frequency of image refresh.

[0061] Referring to FIG. 2, the effective pixel array is read out into the column parallel ADCs (the first group of analog-to-digital converters 31 and the second group of analog-to-digital converters 32) in odd rows and even rows respectively. A simple row-by-row readout scheme is shown in FIG. 2. Each column of pixels inputs the image signal into the column parallel ADCs through two column buses. One column bus inputs the image signal output by the odd row pixels into the second group of analog-to-digital converters 32 circuit, and the other column bus inputs the image signal output by the even row pixels into the first group of analog-to-digital converters 31 circuit. Taking a 6-row 5-column pixel array as an example, the image signal output by the pixel rows Row[0], Row[2], Row[4] is converted and quantized by the first group of analog-to-digital converters 31 circuit, and the image signal output by the pixel rows Row[1], Row[3], Row[5] is converted and quantized by the second group of analog-to-digital converters 32 circuit.

[0062] The delay of the column bus output by the 0th row of pixels Row[0] to the first column-level readout circuit (Column ADC1) is t0, and the delay of the column bus output by the 1st row of pixels Row[1] to the second column-level readout circuit (Column ADC2) is t1. In a large-area image sensor, due to the asymmetry of the wiring of the image signals of the 0th row of pixels and the 1st row of pixels, t1>t0 when the image sensor is working, thereby causing unequal thermal noise, flicker noise and other noise to be introduced in the signal transmission process, and obvious row stripes exist in the image.

[0063] Referring to FIG. 3, in some embodiments, the logic circuit 300 further comprises a first group of row exchange switches 35 corresponding to the first group of analog-to-digital converters 31 and a second group of row exchange switches 36 corresponding to the second group of analog-to-digital converters 32. The first group of row exchange switches 35 are electrically connected to the pixel array 10 and the first group of analog-to-digital converters 31 respectively, and the second group of row exchange switches 36 are electrically connected to the pixel array 10 and the second group of analog-to-digital converters 32 respectively.

[0064] The row decoder 33 outputs a control signal, and the pixel array accepts the control signal to find the corresponding pixel unit and perform the reset, exposure and readout processes according to the control signal. The image signal generated in the pixel unit circuit is processed by the row exchange switch, and the row exchange switch inputs the image signals of two rows of pixels read out at the same time into different two column parallel ADC circuits for conversion and quantization.

[0065] In this way, the image signal can be selectively input into different column parallel ADCs through the row exchange switch, thereby effectively alleviating the row fixed pattern noise (FPN).

[0066] In some embodiments, the pixel array 10 includes M rows by N columns of pixel units, each column of pixel units is connected to two column buses, the first group of row exchange switches includes 2N first switches, the second group of row exchange switches includes 2N second switches, each column bus corresponds to a first switch and a second switch respectively.

[0067] The pixel units in the nth column and odd rows are connected to the 2n-1th column bus and connected to the 2n-1th first switch through the 2n-1th column bus, and the pixel units in the nth column and even rows are connected to the 2nth column bus and connected to the 2nth second switch through the 2nth column bus, 1≤n≤N.

[0068] Alternatively, the pixel units in the nth column and even rows are connected to the 2n-1th column bus and connected to the 2n-1th first switch through the 2n-1th column bus, and the pixel units in the nth column and odd rows are connected to the 2nth column bus and connected to the 2nth second switch through the 2nth column bus, 1≤n≤N.

[0069] Referring to FIG. 4, taking a 6-row 5-column pixel array as an example, the pixels in the pixel matrix are numbered according to their positions, for example, the pixel A is located at the 5th row and the 4th column. The image signals generated by the photosensitive pixel units are selectively input to the designated column parallel ADC circuit through the row exchange switch circuit module (35 or 36).

[0070] The image signals of the pixel units in each column are output to two column parallel ADC circuits through column buses, and each end of the column bus is connected to a pair of switches. The closing or opening of each pair of switches is controlled by signals with opposite phases.

[0071] In some embodiments, the nth second switch and the n+1th first switch are both controlled to be turned on or turned off by a first pulse signal, and the n+1th second switch and the nth first switch are both controlled to be turned on or turned off by a second pulse signal. The first pulse signal and the second pulse signal have opposite phases.

[0072] In some embodiments, the n+2th second switch and the n+3th first switch are both controlled to be turned on or turned off by a third pulse signal, and the n+3th second switch and the n+2th first switch are both controlled to be turned on or turned off by a fourth pulse signal. The third pulse signal and the fourth pulse signal have opposite phases, the first pulse signal and the fourth pulse signal have the same phase, and the second pulse signal and the third pulse signal have the same phase.

[0073] Referring to Fig. 5, switches s1 and s2 are controlled by a pair of phase- opposite signals Switch_S1 (corresponding to the first pulse signal above) and Switch_S2 (corresponding to the second pulse signal above); switches s3 and s4 are controlled by a pair of phase-opposite signals Switch_S3 (corresponding to the third pulse signal above) and Switch_S4 (corresponding to the fourth pulse signal above), and the control signals Switch_S1 and Switch_S4 of switches s1 and s4 are the same in phase.

[0074] The first switching control scheme is shown in Fig. 5, the row switching switches of the odd-numbered columns are controlled by the same signals when reading out the image signals of the pixel units, and the row switching switches of the even-numbered columns are controlled by the same signals when reading out the image signals of the pixel units. The image signals output by all the odd-numbered row pixel units in the same column are converted and quantized in the same column parallel ADC, and the image signals output by all the even-numbered row pixel units in the same column are converted and quantized in another column parallel ADC.

[0075] In some embodiments, a readout case is shown in Fig. 6, when switch s1 is turned on, s2 switch is turned off, s3 switch is turned off, s4 switch is turned on, the image signals output by the odd-numbered columns (corresponding to columns 1 and 3 in Fig. 6) of pixel rows Row[0], Row[2], Row[4] are converted and quantized by the second group of analog-to-digital converter 32 circuits, the image signals output by the even-numbered columns (corresponding to columns 0, 2, 4 in Fig. 6) of pixel rows Row[0], Row[2], Row[4] are converted and quantized by the first group of analog-to-digital converter 31 circuits, the image signals output by the odd-numbered columns (corresponding to columns 1 and 3 in Fig. 6) of pixel rows Row[1], Row[3], Row[5] are converted and quantized by the first group of analog-to-digital converter 31, and the image signals output by the even-numbered columns (corresponding to columns 0, 2, 4 in Fig. 6) of pixel rows Row[1], Row[3], Row[5] are converted and quantized by the second group of analog-to-digital converter 32.

[0076] The image signals outputted by the pixel units in the even columns (0, 2, 4 columns in FIG. 6) of the pixel rows Row[0], Row[2], Row[4] are inputted into the upper column parallel ADC circuit first group of analog-to-digital converters 31 through the first group of row exchange switches 35, and the image signals outputted by the pixel units in the odd columns (1 and 3 columns in FIG. 6) are inputted into the lower column parallel ADC circuit second group of analog-to-digital converters 32 through the second group of row exchange switches 36; the image signals outputted by the pixel units in the even columns (0, 2, 4 columns in FIG. 6) of the pixel rows Row[1], Row[3], Row[5] are inputted into the lower column parallel ADC circuit second group of analog-to-digital converters 32 through the second group of row exchange switches 36, and the image signals outputted by the pixel units in the odd columns (1 and 3 columns in FIG. 6) are inputted into the upper column parallel ADC circuit first group of analog-to-digital converters 31 through the first group of row exchange switches 35.

[0077] The first switch control scheme takes two rows as a group, and inputs the image signals generated by the adjacent rows of pixels into different column parallel analog-to-digital conversion circuits, thereby averaging the noise difference between the rows within the group and reducing the row fixed pattern noise (row FPN) in the pixel array.

[0078] Taking the 0th row and the 1st row as examples, due to the existence of the two column parallel ADC circuits, the image signals of the 0th row of pixels are converted and quantized by the column parallel ADC circuit first group of analog-to-digital converters 31, and the image signals of the 1st row of pixels are converted and quantized by the column parallel ADC circuit second group of analog-to-digital converters 32. The switch control scheme I performs row exchange between the adjacent columns of pixels in the same row, and selects whether to perform row exchange in the even columns or in the odd columns. For example, the paths of the image signals outputted by the even columns of the 0th row and the 1st row of pixels remain unchanged, and the paths of the image signals outputted by the odd columns of the 0th row and the 1st row of pixels are exchanged with each other. The image signals outputted by the odd columns of the 0th row of pixels are converted and quantized by the column parallel ADC circuit second group of analog-to-digital converters 32, and the image signals outputted by the odd columns of the 1st row of pixels are converted and quantized by the column parallel ADC circuit first group of analog-to-digital converters 31.

[0079] The second switch control scheme is shown in FIG. 7. After the image signals of every two rows of pixels are read out, the phase of the switch control signal is rotated by 180 degrees, and the high level becomes low level, and the low level becomes high level. For the image signals outputted by the selected rows, the column parallel analog-to-digital converters first group of analog-to-digital converters 31 or second group of analog-to-digital converters 32 are read out at intervals; the image signals of the adjacent two odd rows (for example, Row[1] and Row[3]) are read into different column parallel analog-to-digital converters, and the image signals of the adjacent two even rows (for example, Row[0] and Row[2]) are read into different column parallel analog-to-digital converters.

[0080] The image signals outputted by the upper and lower pixels in the same column in the two rows are read out simultaneously as a unit, as shown in FIG. 6 and FIG. 8. The noise in the non-ideal image signal can come from the slight mismatch that can be generated in the manufacturing process of the two-column parallel ADC, the thermal noise and flicker noise introduced in the transmission process of the image signal, etc. Therefore, the noise in different units can be quite different due to the difference in the signal transmission direction, which is indicated by different shades in FIG. 6 and FIG. 8.

[0081] The image signal generated by the upper pixel in the diamond texture unit is read out in the first group of analog-to-digital converters 31, and the image signal generated by the lower pixel is read out in the second group of analog-to-digital converters 32; the image signal generated by the upper pixel in the diagonal texture unit is read out in the second group of analog-to-digital converters 32, and the image signal generated by the lower pixel is read out in the first group of analog-to-digital converters 31.

[0082] The second switch control scheme shortens the obvious noise gap between the adjacent two columns of pixels, and further improves the imaging level.

[0083] The second switch control scheme shortens the obvious noise gap between the adjacent two columns of pixels, and further improves the imaging level.

[0084] Referring to FIG. 9, some embodiments of the present disclosure further provide a conversion method of an image signal, applied to the image sensor described above, and the content already stated will not be repeated here. For example, the conversion method of the image signal includes:

[0085] In step 901, the image signal in at least two rows of pixel units to be converted is determined according to a control signal.

[0086] In step 902, the image signal in at least two rows of pixel units is respectively output to at least two groups of analog-to-digital converters at the same time.

[0087] In step 903, the image signal in at least two rows of pixel units is converted by at least two groups of analog-to-digital converters.

[0088] For example, the conversion method of the image signal satisfies at least one of the following: the image signal in the pixel units of the same row and different columns is respectively output to at least two groups of analog-to-digital converters; and the image signal in the pixel units of the same column and different rows is respectively output to at least two groups of analog-to-digital converters.

[0089] The conversion method of the image signal provided by some embodiments of the present disclosure can at least solve the problem of low efficiency caused by the fact that only one row of image signal can be output at a time in the related art by selecting two rows of pixel units at the same time and respectively outputting the image signals collected by the two rows of pixel units to two groups of analog-to-digital converters, thereby improving the conversion and quantization speed of the image signal, and further improving the frame frequency of image refresh.

[0090] Referring to FIG. 2, the effective pixel array is read out to the column parallel ADC (the first group of analog-to-digital converters 31 and the second group of analog-to-digital converters 32) according to odd rows and even rows, and a simple row reading scheme is shown in FIG. 2. Each column of pixels inputs the image signal to the column parallel ADC through two column buses, one column bus inputs the image signal output by the odd row pixels to the circuit of the second group of analog-to-digital converters 32, and the other column bus inputs the image signal output by the even row pixels to the circuit of the first group of analog-to-digital converters 31. Taking a 6-row 5-column pixel array as an example, the image signal output by the pixel rows Row[0], Row[2], Row[4] is converted and quantized by the circuit of the first group of analog-to-digital converters 31, and the image signal output by the pixel rows Row[1], Row[3], Row[5] is converted and quantized by the circuit of the second group of analog-to-digital converters 32.

[0091] The delay of the column bus output of the 0th row pixel Row[0] to the first column-level readout circuit (Column ADC1) is t0, and the delay of the column bus output of the 1st row pixel Row[1] to the second column-level readout circuit (Column ADC2) is t1. In a large-area image sensor, due to the asymmetry of the image signal wiring of the 0th row pixel and the 1st row pixel, t1 > t0 when the image sensor is working, thereby causing unequal thermal noise, flicker noise and other noise to be introduced in the signal transmission process, and obvious row stripes exist in the image picture.

[0092] To solve this problem, a row decoder 33 is also introduced in the embodiment of the present disclosure, a control signal is output through the row decoder 33, the pixel array accepts the control signal to find the corresponding pixel unit, and the reset, exposure and readout process are performed according to the control signal. The image signal generated in the pixel unit circuit is processed by the row exchange switch, and the image signals of two rows of pixels read out at the same time are processed by the row exchange switch and input into different two column parallel ADC circuits for conversion and quantization.

[0093] In this way, the image signals can be selectively input into different column parallel ADCs through the row exchange switch, thereby effectively alleviating the row fixed pattern noise (row FPN).

[0094] For example, the conversion method of the image signal includes two control schemes.

[0095] The first control scheme will be introduced below.

[0096] In some embodiments, the step 902 can be implemented by the following steps: outputting the image signals of all odd-numbered row pixel units in the nth column to the first group of analog-to-digital converters; and outputting the image signals of all even-numbered row pixel units in the nth column to the second group of analog-to-digital converters.

[0097] In some embodiments, the step 902 can be implemented by the following steps: outputting the image signals of all odd-numbered row pixel units in the nth column to the second group of analog-to-digital converters; and outputting the image signals of all even-numbered row pixel units in the nth column to the first group of analog-to-digital converters.

[0098] In some embodiments, the step 902 can also be implemented by the following steps: outputting the image signals of all odd-numbered row pixel units in the (n+1)th column to the second group of analog-to-digital converters; and outputting the image signals of all even-numbered row pixel units in the (n+1)th column to the first group of analog-to-digital converters.

[0099] In some embodiments, the step 902 can also be implemented by the following steps: outputting the image signals of all odd rows of pixel units in the n+1th column to the first group of analog-to-digital converters; and outputting the image signals of all even rows of pixel units in the n+1th column to the second group of analog-to-digital converters.

[0100] The first switch control scheme groups every two rows as a group, and inputs the image signals generated by the adjacent column pixels in the same row into different column parallel analog-to-digital conversion circuits, thereby averaging the noise difference between rows within the group and reducing the row fixed pattern noise (row FPN) in the pixel array.

[0101] For example, the 0th row and the 1st row, due to the existence of two column parallel ADC circuits, the conventional method is that the image signals of the 0th row (Row[0]) pixel are converted and quantized by the first group of analog-to-digital converters 31 of the column parallel ADC circuit, and the image signals of the 1st row (Row[1]) pixel are converted and quantized by the second group of analog-to-digital converters 32 of the column parallel ADC circuit. The first switch control scheme provided by the embodiment of the present disclosure performs row exchange between the adjacent column pixels in the same row, and can select whether to perform row exchange in the even column or the odd column in the adjacent column. For example, referring to FIG. 6, the paths of the image signals output by the even columns of the 0th row and the 1st row remain unchanged, the even columns (0, 2, 4 columns shown in FIG. 6) of the 0th row still convert and quantize the image signals by the first group of analog-to-digital converters 31 of the column parallel ADC circuit, and the even columns (0, 2, 4 columns shown in FIG. 6) of the 1st row still convert and quantize the image signals by the second group of analog-to-digital converters 32 of the column parallel ADC circuit. However, the paths of the image signals output by the odd columns of the 0th row and the 1st row are exchanged with each other. That is, the image signals output by the odd columns (1 and 3 columns shown in FIG. 6) of the 0th row are converted and quantized by the second group of analog-to-digital converters 32 of the column parallel ADC circuit, and the image signals output by the odd columns (1 and 3 columns shown in FIG. 6) of the 1st row are converted and quantized by the first group of analog-to-digital converters 31 of the column parallel ADC circuit.

[0102] The embodiment of the present disclosure also provides a second switch control scheme, and in some embodiments, the step 902 can also be implemented by the following steps: outputting the image signals of all odd columns of pixel units in the mth row to the first group of analog-to-digital converters; and outputting the image signals of all even columns of pixel units in the mth row to the second group of analog-to-digital converters.

[0103] In some embodiments, the step 902 can also be implemented by the following steps: outputting the image signals of all odd columns of pixel units in the mth row to the second group of analog-to-digital converters; and outputting the image signals of all even columns of pixel units in the mth row to the first group of analog-to-digital converters.

[0104] In some embodiments, the step 902 can be further implemented by the following steps: outputting the image signals of all odd column pixel units in the m+1th row to the second group of analog-digital converters; and outputting the image signals of all even column pixel units in the m+1th row to the first group of analog-digital converters.

[0105] In some embodiments, the step 902 can be further implemented by the following steps: outputting the image signals of all odd column pixel units in the m+1th row to the first group of analog-digital converters; and outputting the image signals of all even column pixel units in the m+1th row to the second group of analog-digital converters.

[0106] In some embodiments, the step 902 can be further implemented by the following steps: outputting the image signals of all odd column pixel units in the m+2th row to the second group of analog-digital converters; and outputting the image signals of all even column pixel units in the m+2th row to the first group of analog-digital converters.

[0107] In some embodiments, the step 902 can be further implemented by the following steps: outputting the image signals of all odd column pixel units in the m+2th row to the first group of analog-digital converters; and outputting the image signals of all even column pixel units in the m+2th row to the second group of analog-digital converters.

[0108] In some embodiments, the step 902 can be further implemented by the following steps: outputting the image signals of all odd column pixel units in the m+3th row to the first group of analog-digital converters; and outputting the image signals of all even column pixel units in the m+3th row to the second group of analog-digital converters.

[0109] In some embodiments, the step 902 can be further implemented by the following steps: outputting the image signals of all odd column pixel units in the m+3th row to the second group of analog-digital converters; and outputting the image signals of all even column pixel units in the m+3th row to the first group of analog-digital converters.

[0110] The second switch control scheme is shown in FIG. 7. After the image signals of every two rows of image elements are read out, the phase of the switch control signal is rotated by 180 degrees, the high level becomes low level, and the low level becomes high level. Referring to FIG. 8, for the image signals output by the selected row, the column parallel analog-digital converters are read out at intervals. The image signals of the same column of adjacent two odd rows (for example, Row[1] and Row[3]) are read out into different column parallel analog-digital converters, and the image signals of the same column of adjacent two even rows (for example, Row[0] and Row[2]) are read out into different column parallel analog-digital converters.

[0111] For example, taking two adjacent rows as a group, such as Row[0] and Row[1] as the first group, and Row[2] and Row[3] as the second group, in the first group, the data of the even columns (corresponding to columns 0, 2, 4 shown in FIG. 8) of Row[0] is converted and quantized by the first group of analog-to-digital converters 31 of the column parallel ADC circuit, and the data of the odd columns (corresponding to columns 1, 3 shown in FIG. 8) of Row[0] is converted and quantized by the second group of analog-to-digital converters 32 of the column parallel ADC circuit; the data of the even columns (corresponding to columns 0, 2, 4 shown in FIG. 8) of Row[1] is converted and quantized by the second group of analog-to-digital converters 32 of the column parallel ADC circuit, and the data of the odd columns (corresponding to columns 1, 3 shown in FIG. 8) of Row[1] is converted and quantized by the first group of analog-to-digital converters 31 of the column parallel ADC circuit. In the second group, the control signal is switched, the data of the even columns (corresponding to columns 0, 2, 4 shown in FIG. 8) of Row[2] is converted and quantized by the second group of analog-to-digital converters 32 of the column parallel ADC circuit, and the data of the odd columns (corresponding to columns 1, 3 shown in FIG. 8) of Row[2] is converted and quantized by the first group of analog-to-digital converters 31 of the column parallel ADC circuit; the data of the even columns (corresponding to columns 0, 2, 4 shown in FIG. 8) of Row[3] is converted and quantized by the first group of analog-to-digital converters 31 of the column parallel ADC circuit, and the data of the odd columns (corresponding to columns 1, 3 shown in FIG. 8) of Row[3] is converted and quantized by the second group of analog-to-digital converters 32 of the column parallel ADC circuit.

[0112] In some embodiments of the present disclosure, the image sensor 100 further comprises a first controller configured to perform the conversion method of the image signal as described above.

[0113] The first controller can be a chip or a processor. For example, the processor can be a general central processing unit (CPU), a microprocessor, an application specific integrated circuit (ASIC). Alternatively, the first controller can be a programmable device, including a complex programmable logic device (CPLD), an erasable programmable logic device (EPLD), or a field programmable gate array (FPGA). The chip can be an integrated circuit (IC).

[0114] Some other embodiments of the present disclosure further provide a camera device comprising the image sensor described above, which can realize all the functions of the image sensor described above and will not be repeated here.

[0115] The image sensor provided by the embodiments of the present disclosure can also be applied to smart phones, Internet of Things, wearable devices, intelligent vehicle-mounted driving records, front and reverse images, 360° surround view images, anti-collision systems, etc., and can also be applied to security monitoring fields or medical devices.

[0116] Some other embodiments of the present disclosure further provide a vehicle comprising the camera device described above. The vehicle can realize all the functions of the camera device described above and will not be repeated here. The vehicle can be a fuel automobile, a plug-in hybrid electric vehicle or a new energy vehicle, etc., which is not limited by the present disclosure.

[0117] Referring to FIG. 10, the embodiments of the present disclosure provide an image sensor 100 comprising a pixel array 10, a plurality of first analog-to-digital converter groups 20 and a plurality of second analog-to-digital converter groups 30, each pixel cell column 11 in the pixel array 10 has a corresponding first analog-to-digital converter group 20 and a corresponding second analog-to-digital converter group 30, and each pixel cell column 11 has a corresponding first column line 111 and a second column line 112; each first pixel cell 113 in each odd row in the pixel cell column 11 is electrically connected to the corresponding first analog-to-digital converter group 20 of the pixel cell column 11 through the first column line 111; and each second pixel cell 114 in each even row in the pixel cell column 11 is electrically connected to the corresponding second analog-to-digital converter group 30 of the pixel cell column 11 through the second column line 112.

[0118] It should be noted that the image sensor can comprise one or more pixel arrays 10. The image pixels (i.e., pixel cells) can be formed in a semiconductor substrate using Complementary Metal Oxide Semiconductor (CMOS) technology or Charge-coupled Device (CCD) technology or any other suitable photosensitive device technology. The image pixels can be front side illumination (FSI) image pixels or back side illumination (BSI) image pixels. A given image pixel can comprise one or more photosensitive regions, for example, the image pixel can consist of one photodiode or a pair of split photodiodes, and all the photosensitive regions in an image pixel share the same microlens.

[0119] The pixel array 10 is an array composed of one or more pixel units, and includes one or more pixel unit columns 11 and one or more pixel unit rows.

[0120] The pixel unit is configured to collect a light signal and convert the light signal into an electrical signal, i.e., an analog pixel signal.

[0121] The first analog-digital converter group 20 includes one or more first analog-digital converters, and the second analog-digital converter group 30 includes one or more second analog-digital converters. The first analog-digital converters and the second analog-digital converters are both analog-digital converters.

[0122] The first column line 111 is electrically connected to each odd row first pixel unit 113 in the pixel unit column 11 corresponding to the first column line 111, and is also electrically connected to the first analog-digital converter group 20 of the pixel unit column 11 corresponding to the first column line 111. The second column line 112 is electrically connected to each even row second pixel unit 114 in the pixel unit column 11 corresponding to the second column line 112, and is also electrically connected to the second analog-digital converter group 30 of the pixel unit column 11 corresponding to the second column line 112.

[0123] For example, the pixel array 10 includes n pixel unit columns and m pixel unit rows, where n is a positive integer and m is a positive even number. The n pixel unit columns are A1 column, A2 column, A3 column, …, A(n-1) column, and An column, and the m pixel unit rows are B1 row, B2 row, B3 row, …, B(m-1) row, and Bm row. The A1 column has a corresponding first analog-digital converter group C1 and a corresponding second analog-digital converter group D1, and has a corresponding first column line E1 and a second column line F1. The A2 column has a corresponding first analog-digital converter group C2 and a corresponding second analog-digital converter group D2, and has a corresponding first column line E2 and a second column line F2. The A3 column has a corresponding first analog-digital converter group C3 and a corresponding second analog-digital converter group D3, and has a corresponding first column line E3 and a second column line F3. Similarly, the A(n-1) column has a corresponding first analog-digital converter group C(n-1) and a corresponding second analog-digital converter group D(n-1), and has a corresponding first column line E(n-1) and a second column line F(n-1). The An column has a corresponding first analog-digital converter group Cn and a corresponding second analog-digital converter group Dn, and has a corresponding first column line En and a second column line Fn.

[0124] The first pixel unit of each odd row in the A1 column is electrically connected to the first analog-to-digital converter group C1 corresponding to the A1 column through the first column line E1, the second pixel unit of each even row in the A1 column is electrically connected to the second analog-to-digital converter group D1 corresponding to the A1 column through the second column line F1, the first pixel unit of each odd row in the A2 column is electrically connected to the first analog-to-digital converter group C2 corresponding to the A2 column through the first column line E2, the second pixel unit of each even row in the A2 column is electrically connected to the second analog-to-digital converter group D2 corresponding to the A2 column through the second column line F2, and so on, the first pixel unit of each odd row in the A(n-1) column is electrically connected to the first analog-to-digital converter group C(n-1) corresponding to the A(n-1) column through the first column line E(n-1), the second pixel unit of each even row in the A(n-1) column is electrically connected to the second analog-to-digital converter group D(n-1) corresponding to the A(n-1) column through the second column line F(n-1), the first pixel unit of each odd row in the An column is electrically connected to the first analog-to-digital converter group Cn corresponding to the An column through the first column line En, and the second pixel unit of each even row in the An column is electrically connected to the second analog-to-digital converter group Dn corresponding to the An column through the second column line Fn.

[0125] In some embodiments, referring to FIG. 11, the row control circuit 60 (i.e., row decode and drive circuit, row decoder (RDEC)) can provide respective row control signals, such as reset, row select, charge transfer, dual conversion gain, and readout control signals, to the pixel units through row control lines 61. The column readout and control circuitry 80 reads out analog image signals from the pixel units through column control lines 81 (column lines), which can couple one or more conductive lines to each column of pixel units in the pixel array 10.

[0126] In some stages, such as during pixel readout, the row control circuit 60 can be used to select a row of pixels in the pixel array and read out image signals generated by the pixel units in the row along the column lines. The image readout circuit can receive image signals, such as analog pixel signals generated by the pixel units, transmitted by the column lines. The image readout circuit can include sample and hold circuits, analog-to-digital converters (ADCs), bias circuits, column counters, latch circuits, and other circuits. The sample and hold circuits are configured to temporarily store image signals read out from the pixel array 10, the ADCs can convert analog pixel signals received from the pixel array units into corresponding digital pixel signals, the latch circuits are configured to selectively enable or disable the column circuits, and the other circuits can generally be coupled to one or more columns and configured to control the image pixels and read out image signals from the pixel units.

[0127] In the embodiments of the present disclosure, by the first analog-to-digital converter group 20 corresponding to the pixel unit column 11, the first analog pixel signal of the first pixel unit 113 in each odd row in the pixel unit column 11 is converted into a first digital pixel signal, and by the second analog-to-digital converter group 30 corresponding to the pixel unit column 11, the second analog pixel signal of the second pixel unit 114 in each even row in the pixel unit column 11 is converted into a second digital pixel signal, it can be realized that in each cycle of the image sensor, the analog pixel signals of two rows of pixel units of the pixel array 10 are processed, compared with the prior art that the image sensor processes the analog pixel signals of one row of pixel units in the pixel array 10 in each cycle, the processing efficiency is improved.

[0128] In some embodiments, the image sensor further comprises a first wafer 40 and a second wafer 50, the pixel array 10 is arranged on the first wafer 40, and the first analog-to-digital converter group 20 and the second analog-to-digital converter group 30 are arranged on the second wafer 50.

[0129] It should be noted that the first wafer 40 is a pixel wafer (Pixel Wafer), and the second wafer 50 is a logic wafer (Logic Wafer).

[0130] In some embodiments, the image sensor adopts a back-illuminated three-dimensional stacked structure, and the first wafer 40 and the second wafer 50 are directly connected by a mixed bonding method of peripheral vertical contacts (including a first connection point 43, a second connection point 42, a third connection point 51, a fourth connection point 52, etc.). The second wafer 50 further comprises a row control circuit 60, an image readout circuit, and other related control and processing circuits, etc. The image readout circuit can provide the control and processing circuit with digital pixel signals obtained from one or more columns of pixel units.

[0131] In the embodiments of the present disclosure, by arranging the pixel array 10 on the first wafer 40 and arranging the first analog-to-digital converter group 20 and the second analog-to-digital converter group 30 on the second wafer 50, the layout area of the pixel array 10 and the layout area of the first analog-to-digital converter group 20 and the second analog-to-digital converter group 30 can be isolated from each other, and the mutual interference between the first analog-to-digital converter group 20, the second analog-to-digital converter group 30 and the pixel array 10 can be avoided.

[0132] In some embodiments, the first analog-to-digital converter group 20 and the second analog-to-digital converter group 30 are arranged on the side edges of the second wafer 50.

[0133] In the embodiments of the present disclosure, by arranging the first analog-to-digital converter group 20 and the second analog-to-digital converter group 30 on the side edges of the second wafer 50, the symmetrical layout of the first analog-to-digital converter group 20 and the second analog-to-digital converter group 30 is facilitated.

[0134] In some embodiments, the first ADC group 20 is disposed on a first side of the second wafer 50, and the second ADC group 30 is disposed on a second side of the second wafer 50, the first side being opposite to the second side.

[0135] In the embodiments of the present disclosure, the first ADC group 20 is disposed on a first side of the second wafer 50, and the second ADC group 30 is disposed on a second side of the second wafer 50, the first side being opposite to the second side, which facilitates the symmetrical layout of the first ADC group 20 and the second ADC group 30.

[0136] In some embodiments, the pixel array 10 is disposed on a central region 41 of the first wafer 40.

[0137] In the embodiments of the present disclosure, by disposing the pixel array 10 on the central region 41 of the first wafer 40, the symmetrical layout of the pixel array 10 on the first wafer 40 is facilitated.

[0138] In some embodiments, the plane of the first wafer 40 is parallel to the plane of the second wafer 50.

[0139] It should be noted that the projection of the plane of the first wafer 40 on the horizontal plane coincides with the projection of the plane of the second wafer 50 on the horizontal plane.

[0140] In the embodiments of the present disclosure, since the plane of the first wafer 40 is parallel to the plane of the second wafer 50, the regular arrangement of the first wafer 40 and the second wafer 50 is facilitated.

[0141] In some embodiments, each first column line 111 has a first connecting point 43 disposed on the first wafer 40, each second column line 112 has a second connecting point 42 disposed on the first wafer 40, each first ADC group 20 has a third connecting point 51 disposed on the second wafer 50, and each second ADC group 30 has a fourth connecting point 52 disposed on the second wafer 50. The first connecting point 43 of the first column line 111 is electrically connected to the third connecting point 51 of the first ADC group 20 corresponding to the first column line 111. The second connecting point 42 of the second column line 112 is electrically connected to the fourth connecting point 52 of the second ADC group 30 corresponding to the second column line 112.

[0142] It should be noted that the wire connecting the first connecting point 43 and the third connecting point 51 is perpendicular to the plane of the first wafer 40 and perpendicular to the plane of the second wafer 50. The wire connecting the second connecting point 42 and the fourth connecting point 52 is perpendicular to the plane of the first wafer 40 and perpendicular to the plane of the second wafer 50.

[0143] In the embodiments of the present disclosure, the first connecting point 43 of the first column line 111 is electrically connected to the third connecting point 51 of the first analog-to-digital converter group 20 corresponding to the first column line 111, so that the first pixel unit 113 in each odd row of the pixel unit column 11 on the first wafer 40 is electrically connected to the first analog-to-digital converter group 20 corresponding to the pixel unit column 11 on the second wafer 50. The second connecting point 42 of the second column line 112 is electrically connected to the fourth connecting point 52 of the second analog-to-digital converter group 30 corresponding to the second column line 112, so that the second pixel unit 114 in each even row of the pixel unit column 11 on the first wafer 40 is electrically connected to the second analog-to-digital converter group 30 corresponding to the pixel unit column 11 on the second wafer 50.

[0144] In some embodiments, the first connecting point 43 is arranged at a first boundary of a region where the pixel array 10 is located, the second connecting point 42 is arranged at a second boundary of the region where the pixel array 10 is located, and the first boundary is arranged opposite to the second boundary. The third connecting point 51 is arranged at a geometric center of a region where the first analog-to-digital converter group 20 is located, and the fourth connecting point 52 is arranged at a geometric center of a region where the second analog-to-digital converter group 30 is located.

[0145] In the embodiments of the present disclosure, by arranging the first connecting point 43 at the first boundary of the region where the pixel array 10 is located, arranging the second connecting point 42 at the second boundary of the region where the pixel array 10 is located, arranging the third connecting point 51 at the geometric center of the region where the first analog-to-digital converter group 20 is located, and arranging the fourth connecting point 52 at the geometric center of the region where the second analog-to-digital converter group 30 is located, the wires connecting the first connecting point 43 and the third connecting point 51 and the wires connecting the second connecting point 42 and the fourth connecting point 52 are arranged in an orderly manner.

[0146] In some embodiments, the first analog-to-digital converter group 20 includes two first analog-to-digital converters, and the image sensor further includes two first switches, and the first switches correspond one-to-one to the first analog-to-digital converters. The first analog-to-digital converter is electrically connected to each first pixel unit 113 in the pixel unit column 11 corresponding to the first analog-to-digital converter through the first switch corresponding to the first analog-to-digital converter.

[0147] For example, the first analog-to-digital converter is electrically connected to the first switch corresponding to the first analog-to-digital converter, and the first switch corresponding to the first analog-to-digital converter is electrically connected to each first pixel unit 113 in the pixel unit column 11 corresponding to the first analog-to-digital converter through the first column line 111.

[0148] In the embodiments of the present disclosure, the first switch of the first analog-to-digital converter can control the conduction or disconnection of the first analog-to-digital converter and each first pixel unit 113 in the pixel unit column 11 corresponding to the first analog-to-digital converter.

[0149] In some embodiments, the second analog-to-digital converter group 30 includes two second analog-to-digital converters, and the image sensor further includes two second switches corresponding to the two second analog-to-digital converters respectively. The second analog-to-digital converters are electrically connected to each second pixel unit 114 in the pixel unit column 11 corresponding to the second analog-to-digital converters through the second switches corresponding to the second analog-to-digital converters respectively.

[0150] For example, the second analog-to-digital converter is electrically connected to the second switch corresponding to the second analog-to-digital converter, and the second switch corresponding to the second analog-to-digital converter is electrically connected to each second pixel unit 114 in the pixel unit column 11 corresponding to the second analog-to-digital converter through the second column line 112.

[0151] In the embodiments of the present disclosure, the second switch of the second analog-to-digital converter can control the conduction or disconnection of the second analog-to-digital converter and each second pixel unit 114 in the pixel unit column 11 corresponding to the second analog-to-digital converter.

[0152] In some embodiments, the first analog-to-digital converter group 20 and the second analog-to-digital converter group 30 corresponding to the pixel unit column 11 work in parallel.

[0153] It should be noted that the first analog-to-digital converter group 20 and the second analog-to-digital converter group 30 corresponding to the pixel unit column 11 work in parallel, that is, the first analog-to-digital converter group 20 and the second analog-to-digital converter group 30 corresponding to the pixel unit column 11 simultaneously perform the work of converting the analog pixel signal into the digital pixel signal, for example, while the first analog-to-digital converter group 20 corresponding to the pixel unit column 11 converts the first analog pixel signal of each first pixel unit 113 in the odd row of the pixel unit column 11 into the first digital pixel signal, the second analog-to-digital converter group 30 corresponding to the pixel unit column 11 converts the second analog pixel signal of each second pixel unit 114 in the even row of the pixel unit column 11 into the second digital pixel signal.

[0154] For example, the pixel array 10 includes n pixel cell columns and m pixel cell rows, where n is a positive integer, m is a positive even number, the n pixel cell columns are respectively A1 column, A2 column, A3 column, …, A(n-1) column, An column, and the m pixel cell rows are respectively B1 row, B2 row, B3 row, …, B(m-1) row, Bm row. The A1 column has a corresponding first analog-to-digital converter group C1 and a corresponding second analog-to-digital converter group D1, the A2 column has a corresponding first analog-to-digital converter group C2 and a corresponding second analog-to-digital converter group D2, the A3 column has a corresponding first analog-to-digital converter group C3 and a corresponding second analog-to-digital converter group D3, and so on, …, the A(n-1) column has a corresponding first analog-to-digital converter group C(n-1) and a corresponding second analog-to-digital converter group D(n-1), and the An column has a corresponding first analog-to-digital converter group Cn and a corresponding second analog-to-digital converter group Dn.

[0155] In the first cycle of the image sensor, when the analog pixel signals are simultaneously converted and quantized by the analog-to-digital converter groups corresponding to all the pixel cell columns, the first analog-to-digital converter group C1 corresponding to the A1 column converts the first analog pixel signal of the first pixel cell of the B1 row in the A1 column into a first digital pixel signal, the second analog-to-digital converter group D1 corresponding to the A1 column converts the second analog pixel signal of the second pixel cell of the B2 row in the A1 column into a second digital pixel signal, the first analog-to-digital converter group C2 corresponding to the A2 column converts the first analog pixel signal of the first pixel cell of the B1 row in the A2 column into a first digital pixel signal, the second analog-to-digital converter group D2 corresponding to the A2 column converts the second analog pixel signal of the second pixel cell of the B2 row in the A2 column into a second digital pixel signal, and so on, …, the first analog-to-digital converter group C(n-1) corresponding to the A(n-1) column converts the first analog pixel signal of the first pixel cell of the B1 row in the A(n-1) column into a first digital pixel signal, the second analog-to-digital converter group D(n-1) corresponding to the A(n-1) column converts the second analog pixel signal of the second pixel cell of the B2 row in the A(n-1) column into a second digital pixel signal, the first analog-to-digital converter group Cn corresponding to the An column converts the first analog pixel signal of the first pixel cell of the B1 row in the An column into a first digital pixel signal, and the second analog-to-digital converter group Dn corresponding to the An column converts the second analog pixel signal of the second pixel cell of the B2 row in the An column into a second digital pixel signal.

[0156] In the second cycle of the image sensor, when the analog pixel signals of all the pixel units in the column are simultaneously converted and quantized by the corresponding analog-to-digital converter groups, the first analog-to-digital converter group C1 corresponding to the A1 column converts the first analog pixel signal of the first pixel unit in the B3 row in the A1 column into a first digital pixel signal, the second analog-to-digital converter group D1 corresponding to the A1 column converts the second analog pixel signal of the second pixel unit in the B4 row in the A1 column into a second digital pixel signal, the first analog-to-digital converter group C2 corresponding to the A2 column converts the first analog pixel signal of the first pixel unit in the B3 row in the A2 column into a first digital pixel signal, the second analog-to-digital converter group D2 corresponding to the A2 column converts the second analog pixel signal of the second pixel unit in the B4 row in the A2 column into a second digital pixel signal, and so on, the first analog-to-digital converter group C(n-1) corresponding to the A(n-1) column converts the first analog pixel signal of the first pixel unit in the B3 row in the A(n-1) column into a first digital pixel signal, the second analog-to-digital converter group D(n-1) corresponding to the A(n-1) column converts the second analog pixel signal of the second pixel unit in the B4 row in the A(n-1) column into a second digital pixel signal, the first analog-to-digital converter group Cn corresponding to the An column converts the first analog pixel signal of the first pixel unit in the B3 row in the An column into a first digital pixel signal, and the second analog-to-digital converter group Dn corresponding to the An column converts the second analog pixel signal of the second pixel unit in the B4 row in the An column into a second digital pixel signal.

[0157] By analogy, in the m / 2th cycle of the image sensor, when all the pixel unit column corresponding analog-to-digital converter group simultaneously converts and quantizes the analog pixel signal, the first analog-to-digital converter group C1 corresponding to the A1 column converts the first analog pixel signal of the first pixel unit in the B(m-1) row in the A1 column into the first digital pixel signal, the second analog-to-digital converter group D1 corresponding to the A1 column converts the second analog pixel signal of the second pixel unit in the Bm row in the A1 column into the second digital pixel signal, the first analog-to-digital converter group C2 corresponding to the A2 column converts the first analog pixel signal of the first pixel unit in the B(m-1) row in the A2 column into the first digital pixel signal, the second analog-to-digital converter group D2 corresponding to the A2 column converts the second analog pixel signal of the second pixel unit in the Bm row in the A2 column into the second digital pixel signal, and so on, the first analog-to-digital converter group C(n-1) corresponding to the A(n-1) column converts the first analog pixel signal of the first pixel unit in the B(m-1) row in the A(n-1) column into the first digital pixel signal, the second analog-to-digital converter group D(n-1) corresponding to the A(n-1) column converts the second analog pixel signal of the second pixel unit in the Bm row in the A(n-1) column into the second digital pixel signal, the first analog-to-digital converter group Cn corresponding to the An column converts the first analog pixel signal of the first pixel unit in the B(m-1) row in the An column into the first digital pixel signal, and the second analog-to-digital converter group Dn corresponding to the An column converts the second analog pixel signal of the second pixel unit in the Bm row in the An column into the second digital pixel signal.

[0158] In the embodiments of the present disclosure, by the first analog-to-digital converter group 20 corresponding to the pixel unit column 11, the first analog pixel signal of the first pixel unit 113 in each odd row in the pixel unit column 11 is converted into the first digital pixel signal, and by the second analog-to-digital converter group 30 corresponding to the pixel unit column 11, the second analog pixel signal of the second pixel unit 114 in each even row in the pixel unit column 11 is converted into the second digital pixel signal, so that the analog pixel signals of two rows of pixel units of the pixel array 10 can be processed in each cycle of the image sensor.

[0159] In some embodiments, each pixel unit in the pixel array 10 includes four photodiodes.

[0160] For example, each pixel unit includes four photodiodes, i.e., a first photodiode, a second photodiode, a third photodiode, and a fourth photodiode, the analog pixel signal of the pixel unit includes an analog large pixel signal and an analog small pixel signal, the first photodiode, the second photodiode, and the third photodiode in the pixel unit jointly synthesize the analog large pixel signal, and the fourth photodiode in the pixel unit collects the light signal to generate the analog small pixel signal.

[0161] The first analog large pixel signal of the first pixel unit 113 in each odd row in the pixel unit column 11 is converted into a first digital large pixel signal by one of the first analog-digital converters in the first analog-digital converter group 20 corresponding to the pixel unit column 11, the first analog small pixel signal of the first pixel unit 113 in each odd row in the pixel unit column 11 is converted into a first digital small pixel signal by another of the first analog-digital converters in the first analog-digital converter group 20 corresponding to the pixel unit column 11, the second analog large pixel signal of the second pixel unit 114 in each even row in the pixel unit column 11 is converted into a second digital large pixel signal by one of the second analog-digital converters in the second analog-digital converter group 30 corresponding to the pixel unit column 11, and the second analog small pixel signal of the second pixel unit 114 in each even row in the pixel unit column 11 is converted into a second digital small pixel signal by another of the second analog-digital converters in the second analog-digital converter group 30 corresponding to the pixel unit column 11.

[0162] In the embodiments of the present disclosure, the analog large pixel signal and the analog small pixel signal can be generated by the four photodiodes of the pixel unit.

[0163] In some embodiments, the image sensor is provided with an optical coating configured to control attenuation of light of the small pixel.

[0164] It should be noted that in the related art, titanium nitride is used to reduce the sensitivity of the photodiode to the light source, and the image information under high illumination conditions is read out, which is complex in the production process and is not conducive to mass production.

[0165] In the embodiments of the present disclosure, the image sensor is provided with an optical coating for the small pixel, and the optical coating is used to control the attenuation of light in the internal structure of the pixel unit. In the manufacturing process, the optical coating of the small pixel controls the attenuation of light, which not only facilitates the parameter adjustment of the photodiode and makes the light response consistency of the photodiode good, but also has low cost, simple process and easy control, and greatly improves the yield of finished products.

[0166] In some embodiments, the image sensor further includes a slope generator electrically connected to each first analog-digital converter group 20 and each second analog-digital converter group 30.

[0167] In the embodiments of the present disclosure, the ramp signal is provided by the ramp generator for the first analog-digital converter group 20 corresponding to the pixel unit column 11, so as to generate the first digital pixel signal according to the first analog pixel signal of the first pixel unit 113 in each odd row in the pixel unit column 11 and the ramp signal, and the ramp signal is provided by the ramp generator for the second analog-digital converter group 30 corresponding to the pixel unit column 11, so as to generate the second digital pixel signal according to the second analog pixel signal of the second pixel unit 114 in each even row in the pixel unit column 11 and the ramp signal.

[0168] In some embodiments, referring to FIG. 12, the first pixel unit 113 in one pixel unit column 11 includes a first photodiode D1a, a second photodiode D2a, a third photodiode D3a, a fourth photodiode D4a, a first switching device Q1a, a second switching device Q2a, a third switching device Q3a, a fourth switching device Q4a, a fifth switching device Q5a, a sixth switching device Q6a, a seventh switching device Q7a, an eighth switching device Q8a, a first capacitor FD1a, and a second capacitor FD2a.

[0169] The anode of the first photodiode D1a is grounded, the cathode of the first photodiode D1a is connected to the first terminal of the first switching device Q1a, the anode of the second photodiode D2a is grounded, the cathode of the second photodiode D2a is connected to the first terminal of the second switching device Q2a, the anode of the third photodiode D3a is grounded, the cathode of the third photodiode D3a is connected to the first terminal of the third switching device Q3a, the anode of the fourth photodiode D4a is grounded, the cathode of the fourth photodiode D4a is connected to the first terminal of the fourth switching device Q4a, the second terminal of the first switching device Q1a, the second terminal of the second switching device Q2a, the second terminal of the third switching device Q3a, and the second terminal of the fourth switching device Q4a are respectively connected to the control terminal of the seventh switching device Q7a, the second terminal of the first switching device Q1a, the second terminal of the second switching device Q2a, the second terminal of the third switching device Q3a, and the second terminal of the fourth switching device Q4a are respectively connected to the first terminal of the first capacitor FD1a, and the second terminal of the first capacitor FD1a is grounded.

[0170] The first end of the fifth switching device Q5a is electrically connected with the power supply, the second end of the fifth switching device Q5a is electrically connected with the first end of the sixth switching device Q6a and the first end of the second capacitor FD2a respectively, the second end of the second capacitor FD2a is grounded, the second end of the sixth switching device Q6a is electrically connected with the first end of the first capacitor FD1a and the control end of the seventh switching device Q7a respectively, the first end of the seventh switching device Q7a is electrically connected with the power supply, the second end of the seventh switching device Q7a is electrically connected with the first end of the eighth switching device Q8a, the second end of the eighth switching device Q8a is electrically connected with the first end of the first switch SW1a and the first end of the first switch SW2a through the first column line 111, the second end of the first switch SW1a is electrically connected with the first input end of the first analog-to-digital converter 21a, and the second end of the first switch SW2a is electrically connected with the first input end of the first analog-to-digital converter 22a. The first analog-to-digital converter group 20 corresponding to one pixel unit column 11 includes the first analog-to-digital converter 21a and the first analog-to-digital converter 22a.

[0171] The second input end of the first analog-to-digital converter 21a is electrically connected with the first end of the third switch SW3a, the second end of the third switch SW3a is electrically connected with the ramp signal receiving end X1, the second input end of the first analog-to-digital converter 22a is electrically connected with the first end of the third switch SW4a, the second end of the third switch SW4a is electrically connected with the ramp signal receiving end X1, and the ramp signal receiving end X1 is configured to receive the ramp signal generated by the ramp generator.

[0172] It should be noted that the control end TX1a of the first switching device Q1a is configured to receive the pulse control signal of the first switching device Q1a, the control end TX2a of the second switching device Q2a is configured to receive the pulse control signal of the second switching device Q2a, the control end TX3a of the third switching device Q3a is configured to receive the pulse control signal of the third switching device Q3a, the control end TX4a of the fourth switching device Q4a is configured to receive the pulse control signal of the fourth switching device Q4a, the control end RSTa of the fifth switching device Q5a is configured to receive the reset signal, the control end DCGa of the sixth switching device Q6a is configured to receive the switch pulse signal, and the eighth switching device Q8a is configured to receive the row selection signal.

[0173] The first pixel unit 113 in another pixel unit column 11 includes a first photodiode D1b, a second photodiode D2b, a third photodiode D3b, a fourth photodiode D4b, a first switching device Q1b, a second switching device Q2b, a third switching device Q3b, a fourth switching device Q4b, a fifth switching device Q5b, a sixth switching device Q6b, a seventh switching device Q7b, an eighth switching device Q8b, a first capacitor FD1b, and a second capacitor FD2b.

[0174] The positive electrode of the first photodiode D1b is grounded, the negative electrode of the first photodiode D1b is connected to the first terminal of the first switch device Q1b, the positive electrode of the second photodiode D2b is grounded, the negative electrode of the second photodiode D2b is connected to the first terminal of the second switch device Q2b, the positive electrode of the third photodiode D3b is grounded, the negative electrode of the third photodiode D3b is connected to the first terminal of the third switch device Q3b, the positive electrode of the fourth photodiode D4b is grounded, the negative electrode of the fourth photodiode D4b is connected to the first terminal of the fourth switch device Q4b, the second terminal of the first switch device Q1b, the second terminal of the second switch device Q2b, the second terminal of the third switch device Q3b, and the second terminal of the fourth switch device Q4b are respectively connected to the control terminal of the seventh switch device Q7b, the second terminal of the first switch device Q1b, the second terminal of the second switch device Q2b, the second terminal of the third switch device Q3b, and the second terminal of the fourth switch device Q4b are respectively connected to the first terminal of the first capacitor FD1b, and the second terminal of the first capacitor FD1b is grounded.

[0175] The first terminal of the fifth switch device Q5b is connected to the power supply, the second terminal of the fifth switch device Q5b is respectively connected to the first terminal of the sixth switch device Q6b and the first terminal of the second capacitor FD2b, the second terminal of the second capacitor FD2b is grounded, the second terminal of the sixth switch device Q6b is respectively connected to the first terminal of the first capacitor FD1b and the control terminal of the seventh switch device Q7b, the first terminal of the seventh switch device Q7b is connected to the power supply, the second terminal of the seventh switch device Q7b is connected to the first terminal of the eighth switch device Q8b, the second terminal of the eighth switch device Q8b is respectively connected to the first terminal of the first switch SW1b and the first terminal of the first switch SW2b through the first column line 111, the second terminal of the first switch SW1b is connected to the first input terminal of the first analog-to-digital converter 21b, and the second terminal of the first switch SW2b is connected to the first input terminal of the first analog-to-digital converter 22b. The first analog-to-digital converter group 20 corresponding to another pixel unit column 11 includes the first analog-to-digital converter 21b and the first analog-to-digital converter 22b.

[0176] The second input terminal of the first analog-to-digital converter 21b is connected to the first terminal of the third switch SW3b, the second terminal of the third switch SW3b is connected to the ramp signal receiving terminal X1, the second input terminal of the first analog-to-digital converter 22b is connected to the first terminal of the third switch SW4b, and the second terminal of the third switch SW4b is connected to the ramp signal receiving terminal X1.

[0177] It should be noted that the control end TX1b of the first switching device Q1b is configured to receive the pulse control signal of the first switching device Q1b, the control end TX2b of the second switching device Q2b is configured to receive the pulse control signal of the second switching device Q2b, the control end TX3b of the third switching device Q3b is configured to receive the pulse control signal of the third switching device Q3b, the control end TX4b of the fourth switching device Q4b is configured to receive the pulse control signal of the fourth switching device Q4b, the control end RSTb of the fifth switching device Q5b is configured to receive the reset signal, the control end DCGb of the sixth switching device Q6b is configured to receive the switch pulse signal, and the control end of the eighth switching device Q8b is configured to receive the row selection signal.

[0178] Referring to FIG. 13, the second pixel unit 114 in one pixel unit column 11 includes a first photodiode D1c, a second photodiode D2c, a third photodiode D3c, a fourth photodiode D4c, a first switching device Q1c, a second switching device Q2c, a third switching device Q3c, a fourth switching device Q4c, a fifth switching device Q5c, a sixth switching device Q6c, a seventh switching device Q7c, an eighth switching device Q8c, a first capacitor FD1c, and a second capacitor FD2c.

[0179] The anode of the first photodiode D1c is grounded, the cathode of the first photodiode D1c is connected to the first end of the first switching device Q1c, the anode of the second photodiode D2c is grounded, the cathode of the second photodiode D2c is connected to the first end of the second switching device Q2c, the anode of the third photodiode D3c is grounded, the cathode of the third photodiode D3c is connected to the first end of the third switching device Q3c, the anode of the fourth photodiode D4c is grounded, the cathode of the fourth photodiode D4c is connected to the first end of the fourth switching device Q4c, the second end of the first switching device Q1c, the second end of the second switching device Q2c, the second end of the third switching device Q3c, and the second end of the fourth switching device Q4c are respectively connected to the control end of the seventh switching device Q7c, the second end of the first switching device Q1c, the second end of the second switching device Q2c, the second end of the third switching device Q3c, and the second end of the fourth switching device Q4c are respectively connected to the first end of the first capacitor FD1c, and the second end of the first capacitor FD1c is grounded.

[0180] The first end of the fifth switching device Q5c is electrically connected with the power supply, the second end of the fifth switching device Q5c is electrically connected with the first end of the sixth switching device Q6c and the first end of the second capacitor FD2c respectively, the second end of the second capacitor FD2c is grounded, the second end of the sixth switching device Q6c is electrically connected with the first end of the first capacitor FD1c and the control end of the seventh switching device Q7c respectively, the first end of the seventh switching device Q7c is electrically connected with the power supply, the second end of the seventh switching device Q7c is electrically connected with the first end of the eighth switching device Q8c, the second end of the eighth switching device Q8c is electrically connected with the first end of the second switch SW1c and the first end of the second switch SW2c through the second column line 112 respectively, the second end of the second switch SW1c is electrically connected with the first input end of the second analog-to-digital converter 31c, and the second end of the second switch SW2c is electrically connected with the first input end of the second analog-to-digital converter 32c. The second analog-to-digital converter group 30 corresponding to one pixel unit column 11 includes the second analog-to-digital converter 31c and the second analog-to-digital converter 32c.

[0181] The second input end of the second analog-to-digital converter 31c is electrically connected with the first end of the fourth switch SW3c, the second end of the fourth switch SW3c is electrically connected with the slope signal receiving end X1, the second input end of the second analog-to-digital converter 32c is electrically connected with the first end of the fourth switch SW4c, the second end of the fourth switch SW4c is electrically connected with the slope signal receiving end X1, and the slope signal receiving end X1 is configured to receive a slope signal generated by a slope generator.

[0182] It should be noted that the control end TX1c of the first switching device Q1c is configured to receive a pulse control signal of the first switching device Q1c, the control end TX2c of the second switching device Q2c is configured to receive a pulse control signal of the second switching device Q2c, the control end TX3c of the third switching device Q3c is configured to receive a pulse control signal of the third switching device Q3c, the control end TX4c of the fourth switching device Q4c is configured to receive a pulse control signal of the fourth switching device Q4c, the control end RSTc of the fifth switching device Q5c is configured to receive a reset signal, the control end DCGc of the sixth switching device Q6c is configured to receive a switching pulse signal, and the eighth switching device Q8c is configured to receive a row selection signal.

[0183] The second pixel unit 114 in another pixel unit column 11 includes a first photodiode D1d, a second photodiode D2d, a third photodiode D3d, a fourth photodiode D4d, a first switching device Q1d, a second switching device Q2d, a third switching device Q3d, a fourth switching device Q4d, a fifth switching device Q5d, a sixth switching device Q6d, a seventh switching device Q7d, an eighth switching device Q8d, a first capacitor FD1d, and a second capacitor FD2d.

[0184] The positive electrode of the first photodiode D1d is grounded, the negative electrode of the first photodiode D1d is electrically connected to the first terminal of the first switch device Q1d, the positive electrode of the second photodiode D2d is grounded, the negative electrode of the second photodiode D2d is electrically connected to the first terminal of the second switch device Q2d, the positive electrode of the third photodiode D3d is grounded, the negative electrode of the third photodiode D3d is electrically connected to the first terminal of the third switch device Q3d, the positive electrode of the fourth photodiode D4d is grounded, the negative electrode of the fourth photodiode D4d is electrically connected to the first terminal of the fourth switch device Q4d, the second terminal of the first switch device Q1d, the second terminal of the second switch device Q2d, the second terminal of the third switch device Q3d, and the second terminal of the fourth switch device Q4d are respectively electrically connected to the control terminal of the seventh switch device Q7d, the second terminal of the first switch device Q1d, the second terminal of the second switch device Q2d, the second terminal of the third switch device Q3d, and the second terminal of the fourth switch device Q4d are respectively electrically connected to the first terminal of the first capacitor FD1d, and the second terminal of the first capacitor FD1d is grounded.

[0185] The first terminal of the fifth switch device Q5d is electrically connected to the power supply, the second terminal of the fifth switch device Q5d is respectively electrically connected to the first terminal of the sixth switch device Q6d and the first terminal of the second capacitor FD2d, the second terminal of the second capacitor FD2d is grounded, the second terminal of the sixth switch device Q6d is respectively electrically connected to the first terminal of the first capacitor FD1d and the control terminal of the seventh switch device Q7d, the first terminal of the seventh switch device Q7d is electrically connected to the power supply, the second terminal of the seventh switch device Q7d is electrically connected to the first terminal of the eighth switch device Q8d, the second terminal of the eighth switch device Q8d is respectively electrically connected to the first terminal of the second switch SW1d and the first terminal of the second switch SW2d through the second column line 112, the second terminal of the second switch SW1d is electrically connected to the first input terminal of the second analog-to-digital converter 31d, and the second terminal of the second switch SW2d is electrically connected to the first input terminal of the second analog-to-digital converter 32d. The second analog-to-digital converter group 30 corresponding to another pixel unit column 11 includes the second analog-to-digital converter 31d and the second analog-to-digital converter 32d.

[0186] The second input terminal of the second analog-to-digital converter 31d is electrically connected to the first terminal of the fourth switch SW3d, the second terminal of the fourth switch SW3d is electrically connected to the ramp signal receiving end X1, the second input terminal of the second analog-to-digital converter 32d is electrically connected to the first terminal of the fourth switch SW4d, and the second terminal of the fourth switch SW4d is electrically connected to the ramp signal receiving end X1.

[0187] It should be noted that the control end TX1d of the first switching device Q1d is configured to receive the pulse control signal of the first switching device Q1d, the control end TX2d of the second switching device Q2d is configured to receive the pulse control signal of the second switching device Q2d, the control end TX3d of the third switching device Q3d is configured to receive the pulse control signal of the third switching device Q3d, the control end TX4d of the fourth switching device Q4d is configured to receive the pulse control signal of the fourth switching device Q4d, the control end RSTd of the fifth switching device Q5d is configured to receive the reset signal, the control end DCGd of the sixth switching device Q6d is configured to receive the switching pulse signal, and the control end of the eighth switching device Q8d is configured to receive the row selection signal.

[0188] In some embodiments, referring to FIG. 14, the analog-to-digital converter includes a first operational amplifier 91, a second operational amplifier 92, a counter 93, a first sampling capacitor Cr1, a second sampling capacitor Cr2, a first reset switch S1, a second reset switch S2, and a third reset switch S3. The first input end 91a of the analog-to-digital converter is configured to be electrically connected with the pixel unit and receive the analog pixel signal of the pixel unit. The second input end 91b of the analog-to-digital converter is configured to be electrically connected with the slope signal receiving end X1 and receive the slope signal. The first sampling capacitor Cr1 is electrically connected with the first input end 91a of the analog-to-digital converter and collects the analog pixel signal of the pixel unit. The second sampling capacitor Cr2 is electrically connected with the second input end 91b of the analog-to-digital converter and collects the slope signal. The first input end of the first operational amplifier 91 is electrically connected with the first sampling capacitor Cr1. The second input end of the first operational amplifier 91 is electrically connected with the second sampling capacitor Cr2. The output end of the first operational amplifier 91 is electrically connected with the first input end of the second operational amplifier 92.

[0189] The second input end of the second operational amplifier 92 is configured to receive a reference voltage signal, and the output end of the second operational amplifier 92 is electrically connected with the input end of the counter 93. The reset end 93a of the counter 93 is configured to receive a counter reset signal, the clock signal end 93b of the counter 93 is configured to receive a clock signal, and the output end of the counter 93 is configured to output a digital pixel signal. The first end of the first reset switch S1 is electrically connected with the first input end of the first operational amplifier 91, and the second end of the first reset switch S1 is electrically connected with the output end of the first operational amplifier 91. The first end of the second reset switch S2 is electrically connected with the second input end of the first operational amplifier 91, and the second end of the second reset switch S2 is electrically connected with the output end of the first operational amplifier 91. The first reset switch S1 and the second reset switch S2 are configured to reset the first operational amplifier 91. The first end of the third reset switch S3 is electrically connected with the first input end of the second operational amplifier 92, and the second end of the third reset switch S3 is electrically connected with the output end of the second operational amplifier 92. The third reset switch S3 is configured to reset the second operational amplifier 92.

[0190] The row control signals are generated by the row decoding and driving circuit, including a reset signal, a switch pulse signal, a row selection signal, and a pulse control signal of the switch device. The row control signals cooperate with each other to control the on and off of the switch device (transistor) in the pixel unit, and complete the reset, exposure, and readout processes of the pixel unit. The transistor controlled by the reset signal resets the voltage of the second capacitor to the voltage of the power supply. The switch pulse signal enables the pixel unit to work in a low-gain mode or a high-gain mode. The row selection signal controls the signal output of a row of the pixel array 10. The pulse control signal controls the image signal transmission of the photodiode.

[0191] According to the embodiment of the present disclosure, the number of analog-to-digital conversion circuits is increased, so that the analog pixel signals of odd rows and even rows can be converted at the same time, and the conversion time of the analog pixel signals is shortened by one time, which means that under the same working frequency condition, the present disclosure can process more pixel signals and perform more complex operations, that is, the frame frequency of processing images is improved, and the conversion time of the column ADC is reduced. Compared with the related art, the present disclosure achieves a higher frame frequency and has more excellent working characteristics.

[0192] The four ADCs make the working efficiency of the runtime circuit one time higher than that of the related art, which means that under the same working frequency condition, the present disclosure can process more pixel signals and perform more complex operations, that is, the frame frequency of processing images is improved. The internal structure of the pixel unit uses the same four photodiodes, which can simplify the pixel structure and increase the image resolution to 4 times of the pixel structure using one photodiode and 2 times of the pixel structure using two photodiodes.

[0193] Referring to FIG. 15, the embodiment of the present disclosure further provides a conversion method of a pixel signal, applied to the aforementioned image sensor, and the method comprises:

[0194] Step 101: acquiring a first analog pixel signal of a first pixel unit and a second analog pixel signal of a second pixel unit in the pixel unit column.

[0195] The implementation manner of this step is similar to the implementation process of the aforementioned image sensor, and will not be described here again.

[0196] Step 102: converting the first analog pixel signal into a first digital pixel signal through a first analog-to-digital converter group corresponding to the pixel unit column, and converting the second analog pixel signal into a second digital pixel signal through a second analog-to-digital converter group corresponding to the pixel unit column.

[0197] The implementation manner of this step is similar to the implementation process of the aforementioned image sensor, and will not be described here again.

[0198] In some embodiments, step 101 comprises the following sub-step:

[0199] acquiring a first analog large pixel signal and a first analog small pixel signal of the first pixel unit, and acquiring a second analog large pixel signal and a second analog small pixel signal of the second pixel unit.

[0200] The implementation manner of this step is similar to the implementation process of the aforementioned image sensor, and will not be described here again.

[0201] In some embodiments, step 102 comprises:

[0202] converting the first analog large pixel signal into a first digital large pixel signal and the first analog small pixel signal into a first digital small pixel signal through the first analog-to-digital converter group, and converting the second analog large pixel signal into a second digital large pixel signal and the second analog small pixel signal into a second digital small pixel signal through the second analog-to-digital converter group.

[0203] The implementation manner of this step is similar to the implementation process of the aforementioned image sensor, and will not be described here again.

[0204] In some embodiments, the method further comprises:

[0205] generating a ramp signal through a ramp generator.

[0206] The implementation manner of this step is similar to the implementation process of the aforementioned image sensor, and will not be described here again.

[0207] Step 102 further comprises the following sub-step:

[0208] The first digital pixel signal is generated by the first analog-to-digital converter group according to the first analog pixel signal and the ramp signal, and the second digital pixel signal is generated by the second analog-to-digital converter group according to the second analog pixel signal and the ramp signal.

[0209] The implementation of this step is similar to the implementation process of the image sensor described above, and will not be described here.

[0210] The image sensor described above, or the pixel signal conversion method described above, is also provided in the camera.

[0211] The implementation process of the image sensor in the camera provided by the embodiments of the present disclosure is similar to the implementation process of the image sensor described above, and the implementation process of the pixel signal conversion method running in the camera is similar to the implementation process of the pixel signal conversion method described above, and will not be described here.

[0212] In summary, in the embodiments of the present disclosure, the first analog pixel signal of the first pixel unit 113 in each odd row in the pixel unit column 11 is converted into a first digital pixel signal by the first analog-to-digital converter group 20 corresponding to the pixel unit column 11, and the second analog pixel signal of the second pixel unit 114 in each even row in the pixel unit column 11 is converted into a second digital pixel signal by the second analog-to-digital converter group 30 corresponding to the pixel unit column 11, so that the analog pixel signals of two rows of pixel units of the pixel array 10 can be processed in each cycle of the image sensor, and compared with the prior art in which the image sensor processes the analog pixel signals of one row of pixel units in the pixel array 10 in each cycle, the processing efficiency is improved. In some embodiments of the present disclosure, the image sensor 100 further comprises a second controller configured to execute the pixel signal conversion method described above. The structure of the second controller can refer to the description of the first controller described above, and will not be described here.

[0213] In recent years, vehicles with driving assistance functions have become common. Through the driving assistance function, the scene in front of the vehicle is collected, and the vehicle lane, the vehicle driving in front of the vehicle, the pedestrian rushing to the lane, etc. are identified according to the collected image to avoid possible life and property loss.

[0214] As an important circuit unit of the driving assistance function, if the image sensor fails during operation, an incorrect image signal will be generated, and appropriate driving assistance cannot be provided, and the driving assistance function may not be able to avoid danger.

[0215] Some embodiments of the present disclosure provide an electronic device. The electronic device comprises a circuit board and an image sensor, and the circuit board is electrically connected with the image sensor.

[0216] For example, the electronic device can be (but not limited to) at least one of a mobile phone, a Global Positioning System (GPS) receiver / navigator, a camera, a camcorder, a flat panel display, a computer monitor, a car display (e.g., an odometer display, etc.), a navigator, at least one of a cockpit controller and a display, a display of a camera view (e.g., a display of a rear view camera in a vehicle), etc.

[0217] For example, the electronic device with the image sensor can be applied to the field of vehicle-mounted electronics, and can also be applied to other fields.

[0218] The application of the image sensor in the field of automobiles includes, but is not limited to, application to a reversing image assembly of a vehicle, an electronic rearview mirror assembly, a 360-degree panoramic imaging assembly, a collision avoidance system, an Advanced Driving Assistance System (ADAS), and an automatic driving system, etc.

[0219] In some embodiments, as shown in FIG. 16, the image sensor includes a first substrate, a second substrate, a pixel array, and a driving circuit. The second substrate is stacked with the first substrate, the pixel array is disposed on the first substrate and above the second substrate, and the driving circuit of the image sensor is disposed on the second substrate.

[0220] In some embodiments, as shown in FIG. 16, the first substrate includes at least one first through hole penetrating through the first substrate in a stacking direction of the first substrate and the second substrate, and the at least one first through hole is located at least one side of the pixel array. The second substrate includes at least one second through hole penetrating through the at least one first through hole in the stacking direction of the first substrate and the second substrate. The pixel array and the image processing circuit are electrically connected through the penetrating first through hole and the second through hole.

[0221] As shown in FIG. 16, the first substrate includes at least one of a first through hole TCV11, a first through hole TCV12, a first through hole TCV13, and a first through hole TCV14. Correspondingly, the second substrate includes at least one of a second through hole TCV21, a second through hole TCV22, a second through hole TCV23, and a second through hole TCV24.

[0222] In the stacking direction of the first substrate and the second substrate, the first through hole TCV11 penetrates through the second through hole TCV21, the first through hole TCV12 penetrates through the second through hole TCV22, the first through hole TCV13 penetrates through the second through hole TCV23, and the first through hole TCV14 penetrates through the second through hole TCV24.

[0223] The pixel array and the image processing circuit can be electrically connected through at least one group of through holes among the first through hole TCV11 and the second through hole TCV21, the first through hole TCV12 and the second through hole TCV22, the first through hole TCV13 and the second through hole TCV23, or the first through hole TCV14 and the second through hole TCV24.

[0224] As shown in FIG. 16, the driving circuit of the image sensor includes an image signal processing circuit (ISP), a row driving circuit, and a detection circuit. The image processing circuit, the row driving circuit, and the detection circuit are disposed on the second substrate.

[0225] The row driving circuit in the driving circuit of the image sensor is electrically connected with the pixel array, and the image signal processing circuit is further electrically connected with the detection circuit. The row driving circuit is electrically connected with the image signal processing circuit, and the row driving circuit is further electrically connected with the detection circuit.

[0226] The image signal processing circuit supplies command information for specifying a predetermined row address, and a pulse command signal for controlling the pixels specified by the address information to the row driving circuit and the row driving fault detection circuit. The row driving fault detection circuit can be the detection circuit provided in some embodiments of the present disclosure.

[0227] The row driving circuit generates a control signal to reset and accumulate the pixel control signals from each pixel in the pixel array, and read the reset level and the signal level of the pixel control signals, while the row driving circuit supplies the obtained row address information to the row driving fault detection circuit again as binary code information when outputting the pixel control signals.

[0228] The pixel array obtains the pixel control signals supplied by the row driving circuit, and controls the pixels specified by the pixel row address selection information to reset, expose, read out, and the like at the appropriate time node according to the obtained pixel control signals.

[0229] In some embodiments, the image signal processing circuit is configured to output predetermined row address command information; the predetermined row address command information is used to specify the row address of the target pixel in the pixel array.

[0230] The row driving circuit is configured to receive the predetermined row address command, select the pixel in the pixel array according to the predetermined row address command information, and output predetermined row address selection information including the row address of the selected pixel.

[0231] Based on this, the detection circuit is configured to obtain the predetermined row address command information and the predetermined row address selection information, and judge whether the predetermined row address command information and the predetermined row address selection information match.

[0232] The detection circuit judges whether the address selection function of the row driving circuit is faulty by judging whether the row address information of the target pixel specified by the image signal processing circuit and the row address information of the target pixel actually selected by the row driving circuit (the row address information in the pixel array selected by the row driving circuit) match (are the same row address information).

[0233] When the row address information specified by the image signal processing circuit and the row address information actually selected by the row driving circuit match (are the same row address information), the detection circuit judges that the address selection function of the row driving circuit is normal.

[0234] When the row address information specified by the image signal processing circuit and the row address information actually selected by the row driving circuit do not match (are different row address information), the detection circuit judges that the address selection function of the row driving circuit is abnormal.

[0235] In some embodiments, the image signal processing circuit is further configured to output a pulse command signal; the pulse command signal is used to control the pixel specified by the predetermined row address command signal.

[0236] The row driving circuit is further configured to acquire the pulse command signal output by the image signal processing circuit, and output a pixel control signal to the pixel array according to the pulse command signal; the pixel control signal is used to control the target pixel in the pixel array.

[0237] Based on this, the detection circuit is further configured to acquire the pulse command signal output by the image signal processing circuit, and acquire a first control signal used to represent the pixel control signal, generate a detection pulse signal according to the pulse command signal and the first control signal, and judge whether the detection pulse signal matches the pulse command signal.

[0238] The detection circuit judges whether the pulse output function of the row driving circuit is faulty by judging whether the pulse command signal output by the image signal processing circuit and the first control signal used to represent the pixel control signal match (whether the signal pulses of the pulse command signal and the first control signal are the same, or whether the time difference of the rising edge / falling edge of the signal pulses is within the allowable range).

[0239] When the pulse command signal output by the image signal processing circuit and the first control signal used to represent the pixel control signal match (the signal pulses of the pulse command signal and the first control signal are the same, or the time difference of the rising edge / falling edge of the signal pulses is within the allowable range), the detection circuit judges that the address pulse output function of the row driving circuit is normal.

[0240] When the pulse command signal output by the image signal processing circuit does not match the first control signal used to represent the pixel control signal output by the row driving circuit (the signal pulses of the pulse command signal and the first control signal are different, or the time difference of the rising edge / falling edge of the signal pulses is not within the allowed range), the detection circuit determines that the row driving circuit has an abnormal selection pulse output function.

[0241] In some embodiments of the related art, the pulse detection sub-circuit acquires the pulse command signal output by the image signal processing circuit and the pixel control signal output by the row driving circuit, and determines whether the pulse command signal and the pixel control signal match, and determines whether the row driving circuit has a pulse output fault based on the matching result.

[0242] In this case, because the pull-up process of the pixel control signal supplied by the row driving circuit is relatively slow, when the pulse command signal output by the image signal processing circuit and the pixel control signal output by the row driving circuit are directly compared, a relatively long glitch duration will occur, which will most likely cause a false judgment of functional safety.

[0243] Based on this, some embodiments of the present disclosure propose a pulse detection sub-circuit configured to reduce the glitch that occurs when the pulse detection sub-circuit compares, and improve the detection accuracy of the pulse detection sub-circuit.

[0244] In some embodiments, as shown in FIGS. 16 and 17, the detection circuit includes a pulse detection sub-circuit. The pulse detection sub-circuit is configured to acquire a pulse command signal from an image signal processing circuit, the pulse command signal being used to control the row driving circuit to output a pixel control signal. The pulse detection sub-circuit is further configured to acquire a first control signal, the first control signal being used to represent the pixel control signal output by the row driving circuit to a pixel array, the pixel control signal being used to control the target pixel in the pixel array to enable.

[0245] As shown in FIGS. 18 and 19, the pulse detection sub-circuit is further configured to generate a detection pulse signal according to the pulse command signal and the first control signal, and determine whether the pulse command signal matches the detection pulse signal.

[0246] The detection circuit provided by the embodiments of the present disclosure, when determining whether the pixel control signal output by the row driving circuit has a pulse output fault, first generates a detection pulse signal according to the pulse command signal output by the image signal processing circuit and the first control signal acquired to represent the pixel control signal output by the row driving circuit to the pixel array, and then compares the pulse command signal with the detection pulse signal to determine whether the pulse command signal matches the detection pulse signal.

[0247] For example, the pulse detection sub-circuit compares the pulse command signal ISP_CON outputted from the image signal processing circuit ISP with the detection pulse RST_DET to detect the pulse output fault of the pixel reset control signal RST. In this way, the possibility of false positive caused by the delay of the pull-up process of the pixel control signal (e.g., the pixel reset control signal RST) is reduced.

[0248] If the pulse command signal matches the detection pulse signal, the pulse detection sub-circuit determines that the row driving circuit outputs the correct pixel control signal. If the pulse command signal does not match the detection pulse, the pulse detection sub-circuit determines that the row driving circuit outputs the incorrect pixel control signal.

[0249] In some embodiments, as shown in FIG. 20, the waveform of the pulse command signal has a first voltage edge and a second voltage edge, and the waveform of the first control signal has a third voltage edge and a fourth voltage edge. The waveform of the detection pulse signal has a fifth voltage edge and a sixth voltage edge, the fifth voltage edge is generated according to one of the first voltage edge and the third voltage edge, and the sixth voltage edge is generated according to one of the second voltage edge and the fourth voltage edge; and the voltage edges according to which the fifth voltage edge and the sixth voltage edge are generated belong to different signals.

[0250] For example, determining whether the detection pulse signal matches the pulse command signal includes: determining whether the time difference between the first voltage edge of the pulse command signal and the fifth voltage edge of the detection pulse signal is within a first preset range to obtain a first determination result; and determining whether the time difference between the second voltage edge of the pulse command signal and the sixth voltage edge of the detection pulse signal is within the first preset range to obtain a second determination result.

[0251] Based on the first determination result and the second determination result both being match, it is determined that the detection pulse signal matches the pulse command signal. Based on at least one of the first determination result and the second determination result being mismatch, it is determined that the detection pulse signal does not match the pulse command signal.

[0252] In the case where the detection pulse signal matches the pulse command signal, a first match result is outputted to the image processing circuit; the first match result is used to represent that the pixel control signal outputted by the row driving circuit is the correct pixel control signal. In the case where the detection pulse signal does not match the pulse command signal, a second match result is outputted to the image processing circuit; the second match result is used to represent that the pixel control signal outputted by the row driving circuit is the incorrect pixel control signal, and the row driving circuit has the pulse output fault.

[0253] For example, the slope of the third voltage edge is greater than the slope of the fourth voltage edge. The fifth voltage edge is generated according to the third voltage edge, and the sixth voltage edge is generated according to the second voltage edge.

[0254] As shown in FIG. 20, the pulse detection sub-circuit can generate the detection pulse signal according to the falling edge of the pulse command signal and the falling edge of the control pulse.

[0255] As shown in FIG. 20, the pulse detection sub-circuit receives the control pulse signal supplied by the conversion sub-circuit, acquires the falling edge of the pulse command signal ISP CON provided by the image signal processing circuit for controlling the designated pixel and the falling edge of the control pulse signal SEL CON, RST CON, etc. generated by the conversion sub-circuit, and generates the detection pulse signals SEL DET, TG DET, RST DET, etc.

[0256] Since the detection pulse signal generated by the pulse detection sub-circuit is a pulse with steep rising and falling edges, the glitch in the comparison result is only caused by the delay between the falling edge of the control pulse and the rising edge of the pixel pulse command signal (the duration is about 2 ns to 3 ns), which removes the main reason for the detection failure of the pulse detection sub-circuit caused by the long rising time of the control pulse signal, effectively reduces the glitch of the comparison signal caused by the slow rising time of the control pulse signal and the delay of the row driving circuit, and improves the accuracy of the pulse detection sub-circuit.

[0257] In some embodiments, as shown in FIG. 21 and FIG. 22, the pulse detection sub-circuit includes a flip-flop 1, the first input end of the flip-flop 1 is electrically connected with the image signal processing circuit, and the second input end of the flip-flop 1 is configured to receive a first control signal. The flip-flop 1 is configured to output a detection pulse signal according to the pulse command signal output by the image processing circuit and the accepted first control signal.

[0258] For example, the flip-flop can be a D flip-flop. The D flip-flop acquires the falling edge of the pulse command signal provided by the image signal processing circuit for controlling the designated pixel and the falling edge of the control pulse generated by the conversion sub-circuit, and generates a detection pulse with steep edges.

[0259] In some embodiments, as shown in FIG. 21, the pulse detection sub-circuit further includes a logic gate circuit 2, the first input end of the logic gate circuit 2 is electrically connected with the output end of the flip-flop 1, and the second input end of the logic gate circuit 2 is electrically connected with the image signal processing circuit. The logic gate circuit 2 is configured to determine whether the pulse command signal and the detection pulse signal match according to the pulse command signal output by the image processing circuit and the detection pulse signal output by the flip-flop 1.

[0260] As shown in FIG. 21, the logic gate circuit can be an exclusive OR gate circuit. The exclusive OR gate compares the detection pulse SEL DET with the pulse command signal ISP CON provided by the image signal processing circuit for controlling the designated pixel.

[0261] In some embodiments, as shown in FIG. 21, the pulse detection sub-circuit further comprises a buffer 3, an input terminal of the buffer 3 is electrically connected with an output terminal of the logic gate circuit 2, and an output terminal of the buffer 3 is electrically connected with an input terminal of the image signal processing circuit. The buffer 3 is configured to receive the pulse command signal and the result of the determination of whether the detection pulse signal matches, and output the result to the image signal processing circuit.

[0262] As shown in FIG. 21, the logic gate circuit outputs the comparison result through the buffer circuit. The buffer provides a larger resistance and capacitance, and the buffer can further remove the burr with a duration of 2ns to 3ns in the comparison result by charging and discharging the capacitance.

[0263] In some embodiments, as shown in FIG. 21 and FIG. 22, the pixel control signal comprises a plurality of sub-control signals; the pulse detection sub-circuit comprises a plurality of pulse detection units, each pulse detection unit comprises a flip-flop 1, a logic gate circuit 2 and a buffer 3 connected in sequence. The flip-flops 1 of the plurality of pulse detection units are respectively used to receive the plurality of sub-control signals of the pixel control signal.

[0264] In some embodiments, as shown in FIG. 22, the detection circuit further comprises a conversion sub-circuit, and the pulse detection sub-circuit is connected with the conversion sub-circuit. The conversion sub-circuit is configured to obtain the pixel control signal from the row driving circuit, and perform voltage reduction processing on the pixel control signal to obtain a first control signal, and output the first control signal to the pulse detection sub-circuit. The voltage of the first control signal is lower than the voltage of the pixel control signal.

[0265] For example, the voltage reduction processing of the conversion sub-circuit on the pixel control signal can be voltage domain conversion of the conversion sub-circuit on the pixel control signal.

[0266] In some embodiments, the voltage sources of the row driving circuit and the pulse detection sub-circuit in the image sensor are different, so that the row driving circuit and the pulse detection sub-circuit are in different voltage domains. When the electrical signal flows between the row driving circuit and the pulse detection sub-circuit, voltage domain conversion needs to be performed on the electrical signal.

[0267] For example, when the row driving circuit transmits the electrical signal (such as the pixel control signal) to the pulse detection sub-circuit, the voltage of the electrical signal output by the row driving circuit needs to be converted from the voltage of the voltage domain in which the row driving circuit is located to the voltage of the voltage domain in which the pulse detection sub-circuit is located.

[0268] Voltage domain conversion refers to the process of converting the voltage level of the electrical signal output by the row driving circuit to the voltage level of the voltage domain of the pulse detection sub-circuit.

[0269] Based on the above, when the voltage sources of the row driving circuit and the pulse detection sub-circuit in the image sensor are the same, the row driving circuit and the pulse detection sub-circuit are in the same voltage domain. In this case, the electrical signal output by the row driving circuit can be directly transmitted to the pulse detection sub-circuit without voltage domain conversion. When the voltage sources of the row driving circuit and the pulse detection sub-circuit in the image sensor are different, the row driving circuit and the pulse detection sub-circuit are in different voltage domains. In this case, the electrical signal output by the row driving circuit needs to be converted in voltage domain before being transmitted to the pulse detection sub-circuit.

[0270] As shown in FIG. 22, the conversion sub-circuit includes an amplification device and a switching device.

[0271] The first end of the amplification device is connected to the ground, the second end of the amplification device is connected to the first end of the switching device, and the third end of the amplification device is connected to the row driving circuit. The amplification device is configured to receive the pixel control signal and perform voltage reduction processing on the pixel control signal.

[0272] The amplification device includes a first transistor Q1, the first pole of the first transistor Q1 is connected to the first end of the amplification device, the second pole of the first transistor Q1 is connected to the second end of the amplification device, and the control pole of the first transistor Q1 is connected to the third end of the amplification device.

[0273] The second end of the switching device is connected to the pulse detection sub-circuit, and the third end of the switching device is connected to the row driving circuit. The switching device is configured to output the pixel control signal after voltage reduction processing from the amplification device under the control of the row selection signal output by the row driving circuit. The row selection signal is used to indicate the row address of the target pixel corresponding to the pixel control signal in the pixel array.

[0274] The switching device includes a second transistor Q2, the first pole of the second transistor Q2 is connected to the first end of the switching device, the second pole of the second transistor Q2 is connected to the second end of the switching device, and the control pole of the second transistor Q2 is connected to the third end of the switching device.

[0275] In some embodiments, as shown in FIG. 22, the pixel control signal includes a plurality of sub-control signals; the conversion sub-circuit includes a plurality of converters, each converter including an amplification device and a switching device connected in series. The amplification devices of the plurality of converters are respectively used to receive a plurality of sub-control signals of the pixel control signal.

[0276] As shown in FIG. 22, the first transistor Q1 is turned on under the control of the pixel control signal output by the row driving circuit, amplifies the pixel control signal provided by the row driving circuit, and outputs the amplified pixel control signal (control pulse signal) to the first pole of the second transistor Q2.

[0277] The second transistor is turned on under the control of a row address selection signal output by the row driving circuit, and controls the output of the pulse signal to the pulse detection sub-circuit; the row address selection signal is used to indicate the row address of the pixel in the pixel array corresponding to the pixel control signal currently output by the row driving circuit.

[0278] As shown in FIG. 22, the first transistor Q1 at the lower side controls the collection of the pixel control signal output by the row driving circuit, and amplifies the pixel control signal and then outputs the amplified pixel control signal from the second electrode of the first transistor Q1 to the first electrode of the second transistor Q2. The control electrode of the second transistor Q2 at the upper side collects the row address selection signal Row-SEL output by the row driving circuit, and outputs the amplified pixel control signal (control pulse signal) obtained by the first electrode of the second transistor Q2 by row.

[0279] The conversion sub-circuit is provided with only two transistors on each current path, which can reduce power consumption and reduce the glitch phenomenon in the comparison of the pulse detection sub-circuit.

[0280] In some embodiments, as shown in FIG. 22, the first ends of the amplification devices of the plurality of converters are connected to each other. The first electrodes of the first transistors Q1 of the plurality of amplification devices are connected to each other.

[0281] In some embodiments, as shown in FIG. 22, the detection circuit further includes a biasing sub-circuit, and the output end of the biasing sub-circuit is electrically connected to the second end of the switching device of the conversion sub-circuit. The biasing sub-circuit is configured to provide a biasing current for the conversion sub-circuit.

[0282] For example, the biasing sub-circuit includes a plurality of current source devices, and the output end of each current source device is electrically connected to the second end of the switching device of one converter. The current source device is configured to output a biasing current to the converter.

[0283] The biasing circuit can provide a biasing current for the conversion sub-circuit. At the moment of data switching, completely different voltage or current outputs can generate noise in the output analog signal. The thermometer code value can control the biasing circuit to provide a suitable current gear, so as to shorten the pull-up time of the control pulse signal and reduce the error caused by the glitch in the comparison of the pulse detection sub-circuit.

[0284] For example, the biasing circuit can be a current source controlled by a thermometer code mode to provide a biasing current for the conversion sub-circuit. The biasing circuit uses the thermometer code mode to control the value of the output current of the current source corresponding to each conversion sub-circuit according to the signal transmitted by the conversion sub-circuit, so as to provide a suitable biasing current for the conversion sub-circuit.

[0285] In some embodiments, as shown in FIG19, the pulse detection sub-circuit is connected to the row driving circuit. The pulse detection sub-circuit is configured to acquire a pixel control signal from the row driving circuit and use the pixel control signal as a first control signal.

[0286] Based on the above embodiments, when the pulse detection sub-circuit performs pulse output fault detection on the row drive circuit, as shown in Figure 19, the pixel control signal output by the row drive circuit can be used as the first control signal, or as shown in Figure 18, the control pulse signal output by the conversion sub-circuit can be used as the first control signal. In actual applications, there is no limitation, and the choice can be made flexibly according to the actual application scenario.

[0287] In some embodiments, as shown in FIG23, the detection circuit further includes a row selection detection sub-circuit. The row selection detection sub-circuit is configured to obtain predetermined row address command information from the image signal processing circuit; the predetermined row address command information is used to specify the row address of a target pixel in the pixel array. The row selection detection sub-circuit is also configured to obtain predetermined row address selection information from the row driving circuit; the predetermined row address selection information is used to indicate the row address in the pixel array of the pixel selected by the row driving circuit according to the predetermined row address command information. The row selection detection sub-circuit is also configured to determine whether the predetermined row address command information and the predetermined row address selection information match.

[0288] The row selection detection sub-circuit in the fault detection circuit determines whether the command information and selection information of the predetermined row address obtained above match. If the row address command information and row address selection information match, the result is that the row address selection function of the row driving circuit is fault-free, and the row address selection function fault detection process ends. If the row address command information and row address selection information do not match, the result is that the row address selection function of the row driving circuit is faulty, and this result is fed back to the corresponding processing circuit, ending the row address selection function fault detection process.

[0289] In some embodiments, determining whether the predetermined row address command information and the predetermined row address selection information match includes: determining whether the row address of the target pixel specified by the predetermined row address command information in the pixel array and the row address of the pixel corresponding to the predetermined row address selection information in the pixel array are the same row address, and obtaining a third determination result.

[0290] When the row selection detection sub-circuit is working, it compares the command information and selection information of the predetermined row address of the original phase to ensure that there is no abnormality in the addressing function of the row drive circuit.

[0291] If the row address of the target pixel specified by the predetermined row address command information in the pixel array is the same as the row address of the pixel corresponding to the predetermined row address selection information in the pixel array, it is determined that the predetermined row address command information and the predetermined row address selection information match.

[0292] In a case where the row address of the target pixel specified by the predetermined row address command information and the row address of the pixel corresponding to the predetermined row address selection information in the pixel array are different row addresses, it is determined that the predetermined row address command information and the predetermined row address selection information do not match.

[0293] In some embodiments, determining whether the predetermined row address command information and the predetermined row address selection information match further includes: inverting the phase of the predetermined row address command information and the predetermined row address selection information; and determining whether the phase-inverted predetermined row address command information and the phase-inverted predetermined row address selection information are the same row address, to obtain a fourth determination result.

[0294] In a case where the row address of the target pixel specified by the phase-inverted predetermined row address command information and the row address of the pixel corresponding to the predetermined row address selection information in the pixel array are the same row address, it is determined that the predetermined row address command information and the predetermined row address selection information match.

[0295] In a case where the row address of the target pixel specified by the phase-inverted predetermined row address command information and the row address of the pixel corresponding to the predetermined row address selection information in the pixel array are different row addresses, it is determined that the predetermined row address command information and the predetermined row address selection information do not match.

[0296] In a case where the row address of the target pixel specified by the phase-inverted predetermined row address command information and the row address of the pixel corresponding to the predetermined row address selection information in the pixel array are the same row address, it is determined that the predetermined row address command information and the predetermined row address selection information match.

[0297] In a case where the predetermined row address command information and the predetermined row address selection information match, a third matching result is output to the image processing circuit; the third matching result is used to represent that the row address of the pixel selected by the row driving circuit according to the predetermined row address command information is a correct row address.

[0298] In a case where the predetermined row address command information and the predetermined row address selection information do not match, a fourth matching result is output to the image processing circuit; the fourth matching result is used to represent that the row address of the pixel selected by the row driving circuit according to the predetermined row address command information is an incorrect row address, and the row driving circuit has a faulty address selection.

[0299] When the row selection detection sub-circuit is working, two comparisons are performed, respectively comparing the command information and the selection information of the predetermined row address before and after phase inversion. If the row address command information and the row address selection information do not match, a result that the row address selection function of the row driving circuit has a fault is obtained, and the result is fed back to the corresponding processing circuit, and the row address selection function fault detection process is ended.

[0300] For example, the predetermined row address command information and the predetermined row address selection information can be phase-inverted by using an inverter.

[0301] The predetermined row address command information before and after phase inversion can be phase-difference 180 degrees. The predetermined row address selection information before and after phase inversion can be phase-difference 180 degrees.

[0302] In this way, when the row selection detection sub-circuit is working, the command information and the selection information of the predetermined row address before and after phase inversion are compared respectively, and the detection accuracy of the row selection detection sub-circuit to the addressing function of the row driving circuit is improved through two comparisons, and the fault misjudgment of the row selection detection sub-circuit to the addressing function of the row driving circuit is reduced.

[0303] With the development of vehicle intelligence, the use of the photographing function is becoming more and more frequent. In order to improve the shooting effect, various methods are used from the front end to the back end to achieve the required effect. For example, for the effect of a high dynamic range (High-Dynamic Range, HDR) image, the industry generally uses long and short double exposures to achieve a high dynamic range image, but the effect is not ideal.

[0304] For the convenience of understanding, the basic structure of the image sensor will be introduced first:

[0305] An image sensor is an electronic device configured to capture and convert light into an electrical signal. It is the core component of imaging devices such as digital cameras, smartphone cameras, and surveillance cameras. The main function of an image sensor is to convert an optical image into a digital image, allowing devices to capture and process image data. There are currently two main types of image sensors: Charge-Coupled Device (CCD) and Complementary Metal-Oxide-Semiconductor (CMOS) image sensors.

[0306] Working principle of CCD image sensor: CCD sensor captures light through photosensitive elements (pixels), converts light intensity into electric charge, and then transfers electric charge to the circuit for processing through charge transfer. The amount of electric charge in each pixel unit represents the intensity of light received by that pixel.

[0307] CMOS Image Sensor Working Principle: CMOS sensors integrate photodiodes and amplifiers in each pixel, allowing each pixel to independently convert light intensity into an electrical signal and be read out directly. This design enables CMOS sensors to amplify signals at each pixel, reducing noise during signal transmission.

[0308] In some embodiments, the image sensor in some embodiments of the present disclosure is a CMOS image sensor. CMOS image sensors have the following advantages:

[0309] Low Power Consumption: CMOS sensors generally consume less power than CCD sensors.

[0310] Fast Readout: Due to each pixel having its own amplifier, CMOS sensors have faster readout speeds.

[0311] Multifunctional Integration: CMOS sensors can more easily integrate other functions, such as image processing circuits, etc.

[0312] In some embodiments, the image sensor includes a pixel array, pixel circuit, row-column address logic, analog signal processing circuit, digital signal processing circuit, and control circuit.

[0313] Pixel Array: A pixel array composed of multiple pixel units. Each pixel unit contains multiple photodiodes configured to convert light signals into electrical signals.

[0314] Pixel Circuit: Each pixel unit also contains a series of circuit elements, such as amplifiers, readout circuits, and switches. These circuits are responsible for converting the current signal generated by the photodiode into a voltage signal and reading out the signal.

[0315] Row-Column Address Logic: CMOS image sensors use row-column address logic to select pixels whose signals need to be read out. By controlling the opening and closing of switches, pixels can be selected row by row for reading out.

[0316] Analog Signal Processing Circuit: Including amplifiers, analog-to-digital converters (ADC), etc., the analog signal processing circuit is configured to amplify and digitize pixel signals.

[0317] Digital Signal Processing Circuit: Including image signal processing (ISP) units, the digital signal processing circuit is configured to perform noise reduction, color correction, and other processing on digital signals.

[0318] Control circuit: controls the operation of the entire sensor, including exposure time and readout sequence, etc.

[0319] The various components of the image sensor are described in detail as follows:

[0320] In some embodiments, as shown in the embodiment of FIG. 24, a pixel cell includes four light-sensitive regions (i.e., four photodiodes). The pixel cell can also be a pixel cell containing a pair of split photodiodes.

[0321] Referring to FIG. 24, which is a schematic diagram of the structure of a pixel cell of the image sensor, transfer transistors M1, M2, M3, and M4 correspond to the transfer of photoelectrons generated by the excitation of incident light in photodiodes PD1, PD2, PD3, and PD4 to floating diffusion node FD1. Control signals TX1, TX2, TX3, and TX4 are coupled to the gates of the corresponding transfer transistors M1, M2, M3, and M4 to control the on and off of the transfer transistors by high and low levels. Reset transistor M5 is controlled by reset control signal RST coupled to the gate of M5 to reset the potentials of each FD1 and FD2 to power supply voltage VDDp in the reset stage. Gain control signal DCG is coupled to the gate of transistor M6 to control the output of the pixel circuit to be an analog image signal with high gain or low gain. RS pulse signal controls the selection of signals of a certain row of pixels, and the output pixel signal is V_pixel.

[0322] As shown in FIG. 25, switch SW1 controls the transmission of analog pixel signals and ramp signals to analog-to-digital converter Column ADC1; switch SW2 controls the transmission of analog pixel signals to analog-to-digital converter Column ADC2. AZ_CMPT1 and AZ_CMPB1 are reset signals of the analog-to-digital converters, respectively.

[0323] The three transfer transistors M1, M2, and M3 in the large pixel of the logic unit receive transfer control signals TX1, TX2, and TX3, and the small pixel transfer transistor M4 receives transfer control signal TX4. Reset transistor M5 is coupled between floating diffusion node FD2 and power supply line VDDp to reset the pixel (e.g., discharge or charge the floating diffusion node and photodiode) under the control of reset signal RST. Floating diffusion node FD1 is coupled to the gate of source follower transistor M7 and controls the conduction of M7, and selection transistor M8 is coupled between source follower transistor M7 and readout column line. Based on the floating diffusion node FD1 at the source follower transistor M7, the source follower transistor M7 and the selection transistor M8 selectively connect the output of the pixel circuit to the readout column line.

[0324] As illustrated in FIG. 25, the structure of the image sensor imaging system readout conversion circuit mainly includes a pixel structure, a switch, and an analog-to-digital converter. The low-gain reset signal and the low-gain image signal of the pixel signal are transmitted to the analog-to-digital converter through the switch, and are converted by comparison with the low-gain ramp; the high-gain reset signal and the high-gain image signal are transmitted to the analog-to-digital converter through the switch, and are converted by comparison with the high-gain ramp (FIG. 25 shows the pixel structure of the pixel signal and the corresponding readout conversion circuit). The switch SW1 controls the transmission of the analog pixel signal and the ramp signal to the analog-to-digital converter Column ADC1; the switch SW2 controls the transmission of the analog pixel signal to the analog-to-digital converter Column ADC2. AZ_CMPT1 and AZ_CMPB1 are the reset signals of the upper and lower analog-to-digital converters Column ADC1 and Column ADC2, respectively.

[0325] The pixel array is a two-dimensional array of pixel structures, having X columns of pixels and Y rows of pixels. In one embodiment, each pixel is a Complementary Metal-Oxide-Semiconductor (CMOS) imaging pixel. The pixel array can be implemented as a backside illuminated image pixel array. As illustrated, each pixel cell is arranged into a row (e.g., rows R1-Ry) and a column (e.g., columns C1-Cx) to acquire image data of a person, place, or object, which can then be used to reproduce a 2D image of the person, place, or object.

[0326] The pixel array acquires image data, which is stored as image charge within each pixel until each pixel is selected to output its image voltage on its associated readout column, prior to readout. After each pixel has acquired its image data or image charge, the image data is read out by the top readout circuit and the bottom readout circuit via the top and bottom column buses, respectively. The top readout circuit and the bottom readout circuit each include a column swap component, an analog-to-digital converter (ADC). The column swap component routes the image pixel signal on the column bus to the analog-to-digital converter.

[0327] As shown in FIG. 25, the pixel cells from the column stage are input to the top and bottom independent column swap components, respectively: one column swap component located at the top, and one column swap component located at the bottom. In some embodiments, the image data is read out by the column swap component on each column, and the read out image data is the analog voltage level on each readout column, which is then sequentially output to the analog-to-digital conversion circuit ADC.

[0328] Embodiments of the present disclosure provide a control method of an image sensor, which is described in detail as follows:

[0329] Referring to FIG. 26, the method for controlling the image sensor according to an embodiment of the present disclosure is implemented by step 012, which is described below.

[0330] Step 012: output the image signal based on the target pixel readout mode. The pixel readout modes of the image sensor include a plurality of pixel readout modes, and at least one of the exposure time, the gain, and the number of enabled photodiodes is different between any two pixel readout modes.

[0331] The pixel readout mode refers to the mode used by the pixel unit when reading out the image signal. Different pixel readout modes have at least one of the exposure time, the gain, and the number of enabled photodiodes different when reading out the image signal. That is, at least one of the exposure time, the gain, and the number of enabled photodiodes is different between any two pixel readout modes.

[0332] In this way, a plurality of different pixel readout modes can be generated by different configurations of the exposure time, the gain, and the number of enabled photodiodes.

[0333] In some embodiments, the target pixel readout mode can include one or more different pixel readout modes.

[0334] For example, the target pixel readout mode is any one of the pixel readout modes, and when reading out the image signal of the pixel unit, the pixel can be controlled to output the image signal in any one of the target pixel readout modes.

[0335] For another example, the target pixel readout mode includes a plurality of pixel readout modes, and when reading out the image signal of the pixel unit, the image signal corresponding to each pixel readout mode in the target pixel readout mode is output in each pixel readout mode in the target pixel readout mode.

[0336] The method for controlling the image sensor according to some embodiments of the present disclosure can generate pixel readout modes suitable for different shooting scenes by presetting a plurality of pixel readout modes and configuring any two pixel readout modes differently to achieve different imaging effects. The configuration of the pixel readout mode mainly includes three dimensions, namely the exposure time of the pixel unit, the gain of the pixel unit, and the number of enabled photodiodes of the pixel unit. It can be understood that any one of the exposure time, the gain, and the number of enabled photodiodes will affect the imaging effect of the pixel unit. By configuring the exposure time, the gain, and the number of enabled photodiodes, pixel readout modes suitable for different shooting scenes can be generated, so that the image sensor can output more images with different imaging effects, which is beneficial to improve the dynamic range of the synthesized HDR image and can adapt to more diverse scenes, thereby improving the imaging effect of the image sensor in various scenes.

[0337] Please refer to FIG. 27, in some embodiments, the control method further comprises:

[0338] Step 011: determining a target pixel readout mode based on a current shooting scene.

[0339] The current shooting scene includes two categories:

[0340] (1) an overexposure scene, a high-light scene, a middle-light scene, or a low-light scene;

[0341] (2) a high-dynamic scene or a low-dynamic scene.

[0342] For example, when performing scene division, the scene can be divided into an overexposure scene, a high-light scene, a middle-light scene, and a low-light scene based on the intensity of ambient light, and the ambient light intensity corresponding to each of the overexposure scene, the high-light scene, the middle-light scene, and the low-light scene gradually decreases.

[0343] It can be understood that more scenes can also be divided based on the intensity of ambient light, which is not limited in the present disclosure.

[0344] When performing scene division, the high-dynamic scene and the low-dynamic scene can also be distinguished based on the change speed of the scene, such as when the scene content changes quickly (such as shooting an animal in motion, or the shooter is in a high-speed motion state, etc.), determining that the scene is a high-dynamic scene, and when the scene content changes slowly (such as shooting scenery, a stationary object, etc.), determining that the scene is a low-dynamic scene.

[0345] It can be understood that more scenes can also be divided based on the change speed of the scene, such as when the change speed of the scene is moderate, the scene can be determined to be a medium-dynamic scene, which is not limited in the present disclosure.

[0346] After the scene division is completed based on the imaging requirements of the image sensor, the current shooting scene can be determined based on the environmental information.

[0347] In some embodiments, based on the current ambient light intensity, the current shooting scene is determined to be an overexposure scene, a high-light scene, a middle-light scene, or a low-light scene.

[0348] For example, the image sensor can evaluate the ambient light intensity according to the amount of light entering per unit time (such as the amount of light entering per unit time and the ambient light intensity are proportional); or, the image acquisition device in which the image sensor is installed is provided with an ambient light sensor, and the ambient light sensor can detect the ambient light intensity. Based on the detected current ambient light intensity, the current shooting scene can be determined to be an overexposure scene, a high-light scene, a middle-light scene, or a low-light scene.

[0349] For another example, the image sensor can evaluate the ambient light intensity according to the amount of light entering per unit time, so as to determine that the current shooting scene is an overexposure scene, a high-light scene, a middle-light scene, or a low-light scene.

[0350] In some embodiments, the current shooting scene is determined to be a high dynamic scene or a low dynamic scene based on a current scene change speed.

[0351] For example, the scene change speed can be determined according to the number of different images in a plurality of continuous images collected within a unit time (for example, within 3 seconds). The greater the number, the faster the scene change speed, and vice versa, so that the current shooting scene is determined to be a high dynamic scene or a low dynamic scene according to the current scene change speed.

[0352] Two images are different, which means that the similarity between the two images is less than a preset similarity.

[0353] In some embodiments, the pixel readout mode includes a first mode, a second mode, a third mode, and a fourth mode.

[0354] The number of enabled photodiodes in the first mode, the second mode, and the fourth mode (large pixel) is greater than the number of enabled photodiodes in the third mode (small pixel), the exposure time in the first mode, the second mode, and the third mode (long exposure) is greater than the exposure time in the fourth mode (short exposure), and the gain in the second mode, the third mode, and the fourth mode (low gain) is less than the gain in the first mode (high gain).

[0355] Based on the length of the exposure time, it can be divided into two categories: long exposure and very short exposure.

[0356] In some embodiments, the exposure time corresponding to the long exposure is N times the exposure time corresponding to the very short exposure, and N is greater than 1. For example, N is any value in the interval [9, 11].

[0357] Based on the size of the gain, it can be divided into two categories of gain: high gain and low gain.

[0358] Based on the number of enabled photodiodes, the pixel unit can be divided into large pixels or small pixels. The number of enabled photodiodes in the large pixel mode is greater than the number of enabled photodiodes in the small pixel mode.

[0359] In some embodiments, the pixel unit includes 4 photodiodes, the number of enabled photodiodes in the large pixel mode is 4, and the number of enabled photodiodes in the small pixel mode is 1, 2, or 3.

[0360] Alternatively, the number of enabled photodiodes in the large pixel mode is 3, and the number of enabled photodiodes in the small pixel mode is 1 or 2.

[0361] Alternatively, the number of enabled photodiodes in the large pixel mode is 2, and the number of enabled photodiodes in the small pixel mode is 1.

[0362] In this way, the number of photoelectric diodes enabled in the mode of large pixels is greater than the number of photoelectric diodes enabled in the mode of small pixels, so that different ambient light intensity scenes can be adapted to.

[0363] It can be understood that, in order to reduce the complexity of the circuit, the sum of the number of photoelectric diodes enabled in the mode of large pixels and the number of photoelectric diodes enabled in the mode of small pixels is the total number of photoelectric diodes, so as to realize shunt control, simplify circuit design, and reduce the difficulty of circuit control. For example, the number of photoelectric diodes enabled in the mode of large pixels and the number of photoelectric diodes enabled in the mode of small pixels are 3 and 1 respectively.

[0364] In some embodiments, in order to reduce the amount of light entering the photoelectric diode in the mode of small pixels, the photoelectric diode can also be covered with an attenuation film to reduce the amount of light entering the photoelectric diode.

[0365] That is, the first mode is a large pixel, high gain, long exposure pixel readout mode; the second mode is a large pixel, low gain, long exposure pixel readout mode; the third mode is a small pixel, low gain, long exposure pixel readout mode; and the fourth mode is a large pixel, low gain, very short exposure pixel readout mode.

[0366] In some embodiments, the relationship between the target pixel readout mode and the current shooting scene is as follows:

[0367] When the target pixel readout mode is the first mode, in a scene of at least one of low brightness and low dynamic, a better imaging effect can be achieved.

[0368] When the target pixel readout mode is the second mode, in a scene of at least one of medium brightness and low dynamic, not only a better imaging effect can be achieved, but also noise caused by gain can be avoided.

[0369] When the target pixel readout mode is the third mode, in a scene of at least one of high brightness and low dynamic, overexposure problem can be avoided, not only a better imaging effect can be achieved, but also noise caused by gain can be avoided.

[0370] When the target pixel readout mode is the fourth mode, in a scene of at least one of overexposure and high dynamic, when the image signal is read out, the artifacts of the image generated by the image signal can be reduced, and in the case of very short exposure time, the exposure time is shortened, so as to reduce power consumption.

[0371] In some embodiments, the target pixel readout mode includes a first mode, a second mode, a third mode and a fourth mode, and the corresponding image signals are read out in sequence based on the first mode, the second mode, the third mode and the fourth mode respectively to generate the HDR image. In this way, the HDR image is synthesized by the image signals of the above four modes, so as to improve the imaging effect in the case of expanding the dynamic range.

[0372] In some embodiments, the control timing corresponding to different pixel readout modes is different.

[0373] The photodiode is enabled when the corresponding enable signal is high.

[0374] The gain of the image signal is controlled by the corresponding gain control signal, and the image signal corresponds to high gain when the gain control signal is low.

[0375] The exposure time of the pixel unit is controlled by the enable signal and the reset signal of the corresponding photodiode, and the exposure time of the pixel unit is determined based on the interval of the enable signal and the reset signal.

[0376] In the first mode, the enable signals of the first number of photodiodes remain high for a preset time length, the gain control signal is low, and the exposure time is the first time length.

[0377] In the second mode, the enable signals of the first number of photodiodes are high, the gain control signal is high, and the exposure time is the first time length.

[0378] In the third mode, the enable signals of the second number of photodiodes are high, the gain control signal is high, and the exposure time is the second time length, the second number is less than the first number, and the second time length is greater than the first time length.

[0379] In the fourth mode, the enable signals of the first number of photodiodes are high, the gain control signal is high, and the exposure time is the third time length, the third time length is less than the first time length.

[0380] For example, please refer to FIG. 25 and FIG. 28, FIG. 28 is the control timing when the target pixel readout mode includes the first mode to the fourth mode.

[0381] First, introduce each signal in the control timing:

[0382] The RS signal is a row selection control signal, and the output pixel signal is V_pixel.

[0383] RST is a reset signal, the reset transistor M5 is controlled by the reset control signal RST coupled to the gate of M5, and the potential of each floating diffusion node is reset to the power supply voltage VDDp in the reset stage.

[0384] DCG is a gain control signal, coupled to the gate of transistor M6 to control the pixel circuit to output an analog image signal with high gain (corresponding to low level) or low gain (corresponding to high level).

[0385] The control signals TX1, TX2, TX3, TX4 are coupled to the gates of the corresponding transmission transistors M1, M2, M3, M4 to control the on and off of the analog switch tube by high and low levels.

[0386] SW1 is the switch control signal of switch SW1, which controls the transmission of analog pixel signals and ramp signals to the analog-to-digital converter Column ADC1.

[0387] SW2 is the switch control signal of switch SW2, which controls the transmission of analog pixel signals to the analog-to-digital converter Column ADC1.

[0388] AZ_CMPT1 and AZ_CMPB1 are the reset signals of the upper and lower analog-to-digital converters Column ADC1 and Column ADC2, respectively.

[0389] Please refer to Figure 29, since the exposure stage is located before the pixel readout mode, the exposure time is explained as follows:

[0390] Figure 29, ROWA represents the row address switching control signal; RST and TX are consistent with the explanation in Figure 28, which will not be repeated here; READOUT represents the control signal for reading out the pixel signal, which is high when reading out from the pixel unit to the analog-to-digital converter. In Figure 29, the two high levels represent the pixel unit outputting the pixel reset signal and the image signal of the pixel in turn.

[0391] The exposure time of the nth pixel unit is from time a to time b, and the analog pixel signal of the (n-a)th pixel unit is read out after time b. The row address switching operation is performed at time b, and the exposure readout row address selection information is only controlled by the signal ROWA.

[0392] In this way, the exposure stage EXP and the readout stage READ are controlled by the same address line (corresponding to the control signal ROWA), which is more concise and can save area and power consumption.

[0393] For the LPDL at the bottom of FIG. 28, the second mode is currently in a large pixel, low gain, and long exposure, the LPDH represents the first mode currently in a large pixel, high gain, and long exposure, the SPD represents the third mode currently in a small pixel, low gain, and long exposure, and the LPDS represents the fourth mode currently in a large pixel, low gain, and very short exposure.

[0394] In the first mode LPDH, the enable signals of the first number of photodiodes (i.e., TX1, TX2, and TX3) are set to be high in a preset time length, the gain control signal is low, and the interval between the reset signal RST and TX1, TX2, and TX3 is determined to be the first time length.

[0395] In the second mode LPDL, the enable signals of the first number of photodiodes (i.e., TX1, TX2, and TX3) are set to be high, the gain control signal is high, and the interval between the reset signal RST and TX1, TX2, and TX3 is determined to be the first time length.

[0396] In the third mode SPD, the enable signals of the second number of photodiodes (i.e., TX4) are set to be high, the gain control signal is high, and the interval between the reset signal RST and TX4 is determined to be the second time length, which is greater than the first time length (i.e., in the small pixel mode, the exposure time length can be appropriately increased), and the second number is less than the first number.

[0397] In the fourth mode LPDS, the enable signals of the first number of photodiodes (i.e., TX1, TX2, and TX3) are set to be high, the gain control signal is high, and the interval between the reset signal RST and TX1, TX2, and TX3 is determined to be the third time length, which is less than the first time length.

[0398] In this way, the pixel readout mode can be accurately controlled by controlling the control signals of the control timing.

[0399] In some embodiments, the image sensor further includes a first analog-to-digital converter and a second analog-to-digital converter, both of which are connected to the pixel unit to collect the image signals output by the pixel unit. The first analog-to-digital converter and the second analog-to-digital converter cooperate to make full use of the two analog-to-digital converters, improve the pixel readout efficiency, and thus read out four images with different gains through the four readout modes of the pixel unit, and combine the four images into a high dynamic range image.

[0400] For example, referring to FIG. 28, it can be seen from the control timing diagram of a single pixel unit that the first analog-to-digital converter ADC1 and the second analog-to-digital converter ADC2 do not work at the same time, and the first analog-to-digital converter ADC1 and the second analog-to-digital converter ADC2 can simultaneously sample different pixel units. For the same pixel unit, four frames of images with different gains can be read out through four readout modes of the pixel unit, and the four frames of images are combined into a high dynamic range image.

[0401] In this way, through reasonable control timing design and parallel work of the two analog-to-digital converters, the frame rate of the image sensor can be improved, and the frame rate of the image sensor can be greater than or equal to 60 frames per second (FPS).

[0402] Please continue to refer to FIGS. 25 and 28. The following describes the readout process of the image signal of the present disclosure, taking the example that the pixel unit includes four photodiodes and two ADCs are used for sampling.

[0403] As shown in FIG. 28, the large-pixel long-exposure signal, the small-pixel long-exposure signal, and the large-pixel very-short-exposure signal are sequentially read out in time. The readout control timing of the three kinds of pixel signals can be flexibly applied according to actual needs. For example, the small-pixel signal exposure readout can not be performed under normal or darker light conditions; the large-pixel very-short-exposure signal can not be read out when the image quality is not significantly affected by the motion distortion and artifacts related to flicker in the image of a non-moving object or the image.

[0404] At time t0, the reset signal RST is at a high level, the transmission control signals TX1, TX2, and TX3 are at a pulse high level, the gain control signal DCG is at a high level, and the pixel circuit is in a reset stage. At this time, the charge storage node in the pixel unit can be reset to the power supply voltage level (such as VDDp), the selection signal changes from a low level to a high level, and the pixel unit outputs the reset signal in the second mode. The switch SW_1 is turned on, and the pixel reset signal is input to the left plate of the sampling capacitor of the analog-to-digital converter Column ADC1. The analog-to-digital converter reset signal AZ_CMPT1 resets the comparator input end, i.e., the right plate of the sampling capacitor, to a fixed voltage value. The ramp signal V_ramp rises by a fixed voltage value at a certain time and then slopes down. When the voltages at the comparator input ends are equal, the voltage at the comparator output changes from a high level to a low level, and the counter stops counting. At this time, the large-pixel low-gain reset signal conversion and quantization of the pixel are completed.

[0405] At time t1, the gain control signal DCG changes from high level to low level, at this time the pixel unit outputs the reset signal in the first mode; the switch SW_1 is disconnected, SW_2 is turned on, the pixel reset signal is input to the left plate of the sampling capacitor of the analog-to-digital converter Column ADC2, the analog-to-digital converter reset signal AZ_CMPB1 resets the right plate of the sampling capacitor to a fixed voltage value. The ramp signal V_ramp rises by a fixed voltage value at a certain time and then slopes down, when the voltages at the two input terminals of the comparator are equal, the output voltage of the comparator changes from high level to low level, the counter stops counting, at this time the large pixel high gain reset signal of the pixel is converted and quantized.

[0406] At time t2, the transmission control signals TX1, TX2 and TX3 change from low level to high level, the three transmission transistors M1, M2 and M3 in the large pixel are turned on, and the large pixel high gain image signal is output to the analog-to-digital converter Column ADC2 (the conversion is completed in the lower column level analog-to-digital converter). At time t3, the ramp signal begins to decline, when the pixel image signal is equal to the ramp signal, that is, the voltages at the two input terminals of the comparator are equal, the output signal of the comparator changes from high level to low level, the counter stops counting, and the difference between the reset signal and the image signal under high conversion gain is obtained by subtracting the reset count value, the conversion and quantization of the signal are completed, that is, the image quantization value under the high conversion gain of the related double sampling of the large pixel.

[0407] At time t4, the gain conversion signal changes from low level to high level, the transmission control signals TX1, TX2 and TX3 change from low level to high level, the three transmission transistors M1, M2 and M3 in the large pixel are turned on, at this time the pixel unit outputs the image signal in the second mode; the switch SW_2 is closed, SW_1 is turned on, the pixel image signal is input to the left plate of the sampling capacitor of the analog-to-digital converter Column ADC1, the analog-to-digital converter image signal AZ_CMPT1 resets the right plate of the sampling capacitor to a fixed voltage value. The ramp signal V_ramp rises by a fixed voltage value at a certain time and then slopes down, when the voltages at the two input terminals of the comparator are equal, the output voltage of the comparator changes from high level to low level, the counter stops counting, and the difference between the reset signal and the image signal under low conversion gain is obtained by subtracting the reset count value, the conversion and quantization of the signal are completed, that is, the image quantization value under the low conversion gain of the related double sampling of the large pixel.

[0408] Next, at time t5, the third mode is entered, the row select signal RS changes from high to low, the reset signal RST changes from low to high, the small pixel transfer transistor control signal TX4 inputs a high level pulse, and the pixel circuit is in a reset stage. At this time, the charge storage node in the pixel unit is reset to a power supply voltage level (e.g., VDDp). Subsequently, the row select signal changes from low to high, at time t6, RST changes from high to low, the switch SW_2 is turned on, the pixel reset signal is input to the left plate of the sampling capacitor of the analog-to-digital converter Column ADC2, and the analog-to-digital converter reset signal AZ_CMPB1 resets the right plate of the sampling capacitor, i.e., the comparator input, to a fixed voltage value. After the ramp signal V_ramp rises by a fixed voltage value, AZ_CMPB1 is disconnected, the ramp begins to fall, when the voltages at the comparator inputs are equal, the comparator output voltage changes from high to low, the counter stops counting and stores its count value, and the conversion and quantization of the small pixel reset signal of the pixel end.

[0409] The control signal TX4 of the small pixel signal transfer transistor inputs a high level pulse, the transfer transistor M4 in the small pixel is turned on, and the small pixel image signal is output to the analog-to-digital converter Column ADC2 (conversion is completed in the lower column level analog-to-digital converter). At time t7, after the ramp signal V_ramp rises by a fixed voltage value, the ramp begins to fall, when the pixel signal is equal to the ramp signal, i.e., the voltages at the two inputs of the comparator are equal, the comparator output signal changes from high to low, the counter stops counting and stores its count value, the difference between the image signal and the reset signal of the small pixel is obtained, the conversion and quantization of the signal are completed, and the correlated double sampling image quantization value of the small pixel is obtained.

[0410] Further, at time t8, the image signal of the very short exposure of the large pixel is read out (i.e., the fourth mode is entered), the reset signal RST changes from low to high, the transfer control signals TX1, TX2, and TX3 change from low to high, the three transfer transistors M1, M2, and M3 in the large pixel are turned on, and the pixel unit outputs the reset signal of the very short exposure of the large pixel at this time. The switch SW_2 is closed, SW_1 is turned on, the pixel signal is input to the left plate of the sampling capacitor of the analog-to-digital converter Column ADC1, and the analog-to-digital converter image signal AZ_CMPT1 resets the right plate of the sampling capacitor, i.e., the comparator input, to a fixed voltage value. At time t9, the reset signal RST changes from high to low, after the ramp signal V_ramp rises by a fixed voltage value, AZ_CMPB1 is disconnected, the ramp begins to fall, when the voltages at the comparator inputs are equal, the comparator output voltage changes from high to low, the counter stops counting and stores its count value, and the reset signal of the very short exposure of the large pixel is obtained.

[0411] Subsequently, the transmission control signals TX1, TX2, TX3 change from low to high, and the three transmission transistors M1, M2, M3 in the large pixel are turned on, and the large pixel image signal is output to the analog-to-digital converter Column ADC1 (conversion is completed in the upper column-level analog-to-digital converter). At time t10, the ramp signal starts to decrease, and when the pixel image signal is equal to the ramp signal, that is, the voltages at the two input terminals of the comparator are equal, the output signal of the comparator changes from high to low, the counter stops counting and stores the count value, and the difference between the image signal of the very short exposure large pixel and the reset signal is obtained, and the conversion and quantization of the signal are completed, that is, the image quantization value of the very short exposure large pixel is obtained.

[0412] In this way, the image signals in the first mode to the fourth mode can be quickly obtained.

[0413] According to the method described in the above embodiment, the disclosure embodiment also provides a control device 600 configured to perform the steps in the control method of the image sensor. Please refer to FIG. 30, the control device 600 includes:

[0414] The determination component 301 determines the target pixel readout mode based on the current shooting scene;

[0415] The output component 302 outputs the image signal based on the target pixel readout mode, the pixel readout modes of the image sensor include a plurality of pixel readout modes, at least one of the exposure time, the gain and the number of enabled photodiodes of any two pixel readout modes is different, and the target pixel readout mode is at least one of the plurality of pixel readout modes.

[0416] It should be noted that the details of each module unit in the control device 600 described above have been described in detail in the embodiment of the control method of the image sensor, and will not be described here.

[0417] In the disclosure embodiment, the term "module" or "unit" refers to a computer program or a part of a computer program with a predetermined function, and works with other related parts to achieve a predetermined target, and can be implemented entirely or partially by using software, hardware (such as a processing circuit or a memory) or a combination thereof. Similarly, one processor (or multiple processors or memories) can be used to implement one or more modules or units. In addition, each module or unit can be a part of an overall module or unit that includes the functions of the module or unit.

[0418] In some embodiments, the control device in the disclosure embodiment can be implemented in a hardware manner, such as an image acquisition device or a component in the image acquisition device, for example, an integrated circuit or a chip; the control device can also be implemented in a software manner, such as an application installed in the image acquisition device.

[0419] In some embodiments, referring to FIG. 31, the image acquisition device 400 includes a control circuit 401 and the image sensor 100. The control circuit 401 is configured to implement the various processes of the embodiments of the control method of the image sensor 100 described above, and achieve the same technical effects. To avoid repetition, details are not described here.

[0420] In some embodiments, the control circuit 401 can be implemented by a digital circuit.

[0421] Referring to FIG. 32, some embodiments of the present disclosure provide a vehicle 1000, which includes the image acquisition device 400 of any of the embodiments described above. That is, the image acquisition device 400 can be arranged on the vehicle 1000, such as on the body of the vehicle 1000, inside the vehicle 1000, etc.

[0422] The vehicle 1000 can be an electric vehicle, a gasoline vehicle, a hybrid vehicle, a range-extended vehicle, etc.

[0423] In the above embodiments, the description of each embodiment has its own focus, and the parts not described in detail in a certain embodiment can be referred to the relevant description of other embodiments.

[0424] It can be understood that in the specific embodiments of the present disclosure, data related to the identity or characteristics of the user is involved, and when the above embodiments are applied to specific products or technologies, the user's permission or consent is required, and the collection, use and processing of relevant data need to comply with relevant laws, regulations and standards in the relevant region.

[0425] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. An image sensor, comprising: a pixel circuit comprising a pixel array, the pixel array comprising pixel cells arranged in a plurality of rows and a plurality of columns; and a functional circuit connected to the pixel cells in the pixel array. The functional circuit comprises a logic circuit comprising at least two groups of analog-to-digital converters; the image sensor further satisfies at least one of the following:

2. The image sensor of claim 1, wherein, pixel cells of the same row and different columns of the pixel array are connected to the at least two groups of analog-to-digital converters, and the pixel cells of the same column and different rows of the pixel array are connected to the at least two groups of analog-to-digital converters. The logic circuit further comprises:

3. The image sensor of claim 2, wherein, at least two groups of row exchange switches corresponding to the at least two groups of analog-to-digital converters.

4. The image sensor of claim 3, wherein the at least two groups of row exchange switches comprise a first group of row exchange switches and a second group of row exchange switches; the at least two groups of analog-to-digital converters comprise a first group of analog-to-digital converters and a second group of analog-to-digital converters; wherein the pixel array is electrically connected to the first group of analog-to-digital converters through the first group of row exchange switches, and the pixel array is electrically connected to the second group of analog-to-digital converters through the second group of row exchange switches, the first group of row exchange switches is arranged at the side of the first row of the pixel array, and the second group of row exchange switches is arranged at the side of the last row of the pixel array. The pixel array comprises M rows and N columns of pixel cells, each column of pixel cells in the N columns of pixel cells is connected to the first group of row exchange switches and the second group of row exchange switches through two column buses respectively.

5. The image sensor of claim 4, wherein, The first group of row exchange switches comprises 2N first switches, and the second group of row exchange switches comprises 2N second switches, each column bus corresponds to a first switch and a second switch respectively.

6. The image sensor of claim 5, wherein, The pixel cells of the nth column and odd rows are connected to the 2nth-1 column bus and connected to the 2nth-1 first switch through the 2nth-1 column bus, and the pixel cells of the nth column and even rows are connected to the 2nth column bus and connected to the 2nth second switch through the 2nth column bus, 1≤n≤N.

7. The image sensor of claim 6, wherein, The pixel cells of the nth column and even rows are connected to the 2nth-1 column bus and connected to the 2nth-1 first switch through the 2nth-1 column bus, and the pixel cells of the nth column and odd rows are connected to the 2nth column bus and connected to the 2nth second switch through the 2nth column bus, 1≤n≤N.

8. The image sensor of claim 6, wherein, The nth second switch and the nth+1 first switch are controlled to be turned on or turned off through a first pulse signal, and the nth+1 second switch and the nth first switch are controlled to be turned on or turned off through a second pulse signal; wherein the phases of the first pulse signal and the second pulse signal are opposite.

9. The image sensor of claim 6, wherein, ​ 10. The image sensor of claim 9, wherein, The nth+2 second switch and the nth+3 first switch are controlled to be turned on or turned off by a third pulse signal, and the nth+3 second switch and the nth+2 first switch are controlled to be turned on or turned off by a fourth pulse signal; wherein the phase of the third pulse signal and the fourth pulse signal is opposite, the phase of the first pulse signal and the fourth pulse signal is the same, and the phase of the second pulse signal and the third pulse signal is the same.

11. The image sensor of any of claims 2-10, further comprising: A first controller configured to: determine image signals in at least two rows of pixel units to be converted according to a control signal; output the image signals in the at least two rows of pixel units to at least two groups of analog-to-digital converters at the same time, respectively; convert the image signals in the at least two rows of pixel units by the at least two groups of analog-to-digital converters; wherein the image sensor further satisfies at least one of: the image signals in the pixel units of the same row and different columns are output to the at least two groups of analog-to-digital converters, respectively; and the image signals in the pixel units of the same column and different rows are output to the at least two groups of analog-to-digital converters, respectively.

12. The image sensor of claim 11, wherein, The outputting of the image signals in the at least two rows of pixel units to at least two groups of analog-to-digital converters at the same time, respectively, includes at least one of: the image signals in the pixel units of the same row and different columns are output to the at least two groups of analog-to-digital converters, respectively; and the image signals in the pixel units of the same column and different rows are output to the at least two groups of analog-to-digital converters, respectively. The outputting of the image signals in the pixel units of the same column and different rows to the at least two groups of analog-to-digital converters, respectively, includes:

13. The image sensor of claim 12, wherein, outputting the image signals of all odd-numbered rows of the pixel units in the nth column to a first group of analog-to-digital converters; outputting the image signals of all even-numbered rows of the pixel units in the nth column to a second group of analog-to-digital converters. The outputting of the image signals in the pixel units of the same column and different rows to the at least two groups of analog-to-digital converters, respectively, includes:

14. The image sensor of claim 13, wherein, outputting the image signals of all odd-numbered rows of the pixel units in the nth+1 column to the second group of analog-to-digital converters; outputting the image signals of all even-numbered rows of the pixel units in the nth+1 column to the first group of analog-to-digital converters. The outputting of the image signals in the pixel units of the same column and different rows to the at least two groups of analog-to-digital converters, respectively, includes:

15. The image sensor of claim 12, wherein, outputting the image signals of all even-numbered rows of the pixel units in the nth column to a first group of analog-to-digital converters; outputting the image signals of all odd-numbered rows of the pixel units in the nth column to a second group of analog-to-digital converters. The outputting of the image signals in the pixel units of the same column and different rows to the at least two groups of analog-to-digital converters, respectively, includes:

16. The image sensor of claim 15, wherein, outputting the image signals of all even-numbered rows of the pixel units in the nth+1 column to the second group of analog-to-digital converters; outputting the image signals of all odd-numbered rows of the pixel units in the nth+1 column to the first group of analog-to-digital converters. The outputting of the image signals in the pixel units of the same row and different columns to the at least two groups of analog-to-digital converters, respectively, includes:

17. The image sensor of claim 12, wherein, ​ outputting the image signals of all odd-numbered column pixel units in the mth row to a first group of analog-digital converters; outputting the image signals of all even-numbered column pixel units in the mth row to a second group of analog-digital converters.

18. The image sensor of claim 17, wherein, the image signals in the same row and different columns of pixel units are respectively output to the at least two groups of analog-digital converters, comprising: outputting the image signals of all odd-numbered column pixel units in the m+1th row to the second group of analog-digital converters; outputting the image signals of all even-numbered column pixel units in the m+1th row to the first group of analog-digital converters.

19. The image sensor of claim 18, wherein, the image signals in the same row and different columns of pixel units are respectively output to the at least two groups of analog-digital converters, comprising: outputting the image signals of all odd-numbered column pixel units in the m+2th row to the first group of analog-digital converters; outputting the image signals of all even-numbered column pixel units in the m+2th row to the second group of analog-digital converters.

20. The image sensor of claim 19, wherein, the image signals in the same row and different columns of pixel units are respectively output to the at least two groups of analog-digital converters, comprising: outputting the image signals of all odd-numbered column pixel units in the m+3th row to the second group of analog-digital converters; outputting the image signals of all even-numbered column pixel units in the m+3th row to the first group of analog-digital converters.

21. The image sensor of claim 12, wherein, the image signals in the same row and different columns of pixel units are respectively output to the at least two groups of analog-digital converters, comprising: outputting the image signals of all odd-numbered column pixel units in the mth row to a second group of analog-digital converters; outputting the image signals of all even-numbered column pixel units in the mth row to a first group of analog-digital converters.

22. The image sensor of claim 21, wherein, the image signals in the same row and different columns of pixel units are respectively output to the at least two groups of analog-digital converters, comprising: outputting the image signals of all odd-numbered column pixel units in the m+1th row to the first group of analog-digital converters; outputting the image signals of all even-numbered column pixel units in the m+1th row to the second group of analog-digital converters.

23. The image sensor of claim 22, wherein, the image signals in the same row and different columns of pixel units are respectively output to the at least two groups of analog-digital converters, comprising: outputting the image signals of all odd-numbered column pixel units in the m+2th row to the first group of analog-digital converters; outputting the image signals of all even-numbered column pixel units in the m+2th row to the second group of analog-digital converters.

24. The image sensor of claim 23, wherein, the image signals in the same row and different columns of pixel units are respectively output to the at least two groups of analog-digital converters, comprising: outputting the image signals of all odd-numbered column pixel units in the m+3th row to the second group of analog-digital converters; outputting the image signals of all even-numbered column pixel units in the m+3th row to the first group of analog-digital converters.

25. The image sensor of any one of claims 2-10, for use in a camera device.

26. The image sensor of claim 1, wherein, The functional circuit includes a plurality of first analog-to-digital converter groups (20) and a plurality of second analog-to-digital converter groups (30), each pixel unit column (11) in the pixel array (10) has a corresponding first analog-to-digital converter group (20) and a corresponding second analog-to-digital converter group (30), and each pixel unit column (11) has a corresponding first column line (111) and a corresponding second column line (112); Each first pixel unit (113) in each odd row in the pixel unit column (11) is electrically connected to the corresponding first analog-to-digital converter group (20) of the pixel unit column (11) through the first column line (111); and each second pixel unit (114) in each even row in the pixel unit column (11) is electrically connected to the corresponding second analog-to-digital converter group (30) of the pixel unit column (11) through the second column line (112).

27. The image sensor of claim 26, further comprising a first wafer (40) and a second wafer (50), the pixel array (10) is disposed on the first wafer (40), and the plurality of first analog-to-digital converter groups (20) and the plurality of second analog-to-digital converter groups (30) are disposed on the second wafer (50).

28. The image sensor of claim 27, wherein, The plurality of first analog-to-digital converter groups (20) and the plurality of second analog-to-digital converter groups (30) are respectively disposed on the peripheral side edges of the second wafer (50).

29. The image sensor of claim 28, wherein, The plurality of first analog-to-digital converter groups (20) are disposed on a first side edge of the second wafer (50), and the plurality of second analog-to-digital converter groups (30) are disposed on a second side edge of the second wafer (50), the first side edge and the second side edge are oppositely disposed.

30. The image sensor of any of claims 27-29, wherein, The pixel array (10) is disposed in a central region (41) of the first wafer (40).

31. The image sensor of any of claims 27-30, wherein, The plane of the first wafer (40) is parallel to the plane of the second wafer (50).

32. The image sensor of any of claims 27-31, wherein, The first column line (111) has a first connection point (43) disposed on the first wafer (40), the second column line (112) has a second connection point (42) disposed on the first wafer (40), each first analog-to-digital converter group (20) in the plurality of first analog-to-digital converter groups (20) has a third connection point (51) disposed on the second wafer (50), and each second analog-to-digital converter group (30) in the plurality of second analog-to-digital converter groups (30) has a fourth connection point (52) disposed on the second wafer (50); The first connection point (43) of the first column line (111) is electrically connected to the third connection point (51) of the corresponding first analog-to-digital converter group (20) of the first column line (111); The second connection point (42) of the second column line (112) is electrically connected to the fourth connection point (52) of the corresponding second analog-to-digital converter group (30) of the second column line (112).

33. The image sensor of claim 32, wherein, The first connection point (43) is arranged at a first boundary of a region where the pixel array (10) is located, and the second connection point (42) is arranged at a second boundary of the region where the pixel array (10) is located, the first boundary being arranged opposite to the second boundary; The third connection point (51) is arranged at a geometric center position of a region where the first analog-to-digital converter group (20) is located, and the fourth connection point (52) is arranged at a geometric center position of a region where the second analog-to-digital converter group (30) is located.

34. The image sensor of any of claims 26-33, wherein, Each of the plurality of first analog-to-digital converter groups (20) includes two first analog-to-digital converters, and the image sensor further includes two first switches corresponding to the two first analog-to-digital converters, respectively. Any one of the two first analog-to-digital converters is electrically connected to the first pixel unit (113) of each odd row in the pixel unit column (11) corresponding to the first analog-to-digital converter through the first switch corresponding to the first analog-to-digital converter.

35. The image sensor of any of claims 26-34, wherein, Each of the plurality of second analog-to-digital converter groups (30) includes two second analog-to-digital converters, and the image sensor further includes two second switches corresponding to the two second analog-to-digital converters, respectively. Any one of the two second analog-to-digital converters is electrically connected to the second pixel unit (114) of each even row in the pixel unit column (11) corresponding to the second analog-to-digital converter through the second switch corresponding to the second analog-to-digital converter.

36. The image sensor of any of claims 26-35, wherein, The first analog-to-digital converter group (20) and the second analog-to-digital converter group (30) corresponding to the pixel unit column (11) work in parallel.

37. The image sensor of any of claims 26-36, wherein, Each pixel unit in the pixel array (10) includes four photodiodes.

38. The image sensor of any one of claims 26-37, further comprising a ramp generator electrically connected to each of the plurality of first analog-to-digital converter groups and the plurality of second analog-to-digital converter groups, respectively.

39. The image sensor of any of claims 26-38, wherein, The image sensor is provided with an optical coating configured to control the attenuation of light of small pixels.

40. The image sensor of any one of claims 26-39, further comprising a second controller configured to: obtain a first analog pixel signal of the first pixel unit and a second analog pixel signal of the second pixel unit in the pixel unit column; convert the first analog pixel signal into a first digital pixel signal through the first analog-to-digital converter group corresponding to the pixel unit column, and convert the second analog pixel signal into a second digital pixel signal through the second analog-to-digital converter group corresponding to the pixel unit column.

41. The image sensor of claim 40, wherein, The obtaining of the first analog pixel signal of the first pixel unit and the second analog pixel signal of the second pixel unit in the pixel unit column includes: acquire a first analog large pixel signal and a first analog small pixel signal of the first pixel unit, and acquire a second analog large pixel signal and a second analog small pixel signal of the second pixel unit.

42. The image sensor of claim 41, wherein, The first analog pixel signal is converted into a first digital pixel signal by a first analog-to-digital converter group corresponding to the pixel unit column, and the second analog pixel signal is converted into a second digital pixel signal by a second analog-to-digital converter group corresponding to the pixel unit column, including: The first analog large pixel signal is converted into a first digital large pixel signal and the first analog small pixel signal is converted into a first digital small pixel signal by the first analog-to-digital converter group, and the second analog large pixel signal is converted into a second digital large pixel signal and the second analog small pixel signal is converted into a second digital small pixel signal by the second analog-to-digital converter group.

43. The image sensor of any one of claims 40-42, wherein the controller is further configured to: generate a ramp signal by a ramp generator; The first analog pixel signal is converted into a first digital pixel signal by a first analog-to-digital converter group corresponding to the pixel unit column, and the second analog pixel signal is converted into a second digital pixel signal by a second analog-to-digital converter group corresponding to the pixel unit column, including: The first digital pixel signal is generated by the first analog-to-digital converter group according to the first analog pixel signal and the ramp signal, and the second digital pixel signal is generated by the second analog-to-digital converter group according to the second analog pixel signal and the ramp signal.

44. The image sensor of any one of claims 26-43, for a camera.

45. The image sensor of claim 1, wherein, The functional circuit includes a driving circuit, and the driving circuit includes: image signal processing circuitry configured to output a pulse command signal; a row driving circuit electrically connected with the pixel array and the image signal processing circuitry, respectively, and configured to acquire the pulse command signal output by the image signal processing circuitry, and output a pixel control signal to the pixel array according to the pulse command signal, the pixel control signal being used to control a target pixel in the pixel array to be enabled; and detection circuitry electrically connected with the image signal processing circuitry, configured to acquire the pulse command signal output by the image signal processing circuitry, and acquire a first control signal used to represent the pixel control signal, generate a detection pulse signal according to the pulse command signal and the first control signal, and determine whether the detection pulse signal matches the pulse command signal.

46. The image sensor of claim 45, wherein the image signal processing circuitry is further configured to output predetermined row address command information; the predetermined row address command information being used to specify a row address of a target pixel in the pixel array. The row driving circuit is further configured to receive the predetermined row address command, and select pixels in the pixel array according to the predetermined row address command information, and output predetermined row address selection information including row addresses of the selected pixels; The detection circuit is further configured to acquire the predetermined row address command information and the predetermined row address selection information, and determine whether the predetermined row address command information and the predetermined row address selection information match.

47. The image sensor of claim 45 or 46, further comprising: a first substrate; and a second substrate stacked with the first substrate; the pixel array is arranged in a central region of the first substrate and directly above the second substrate; the driving circuit is arranged on the second substrate.

48. The image sensor of any of claims 45-47, wherein, The detection circuit comprises: a pulse detection sub-circuit configured to acquire a pulse command signal from the image signal processing circuit, the pulse command signal being used to control the row driving circuit to output a pixel control signal; the pulse detection sub-circuit is further configured to acquire a first control signal, the first control signal being used to represent the pixel control signal output by the row driving circuit to the pixel array, the pixel control signal being used to control a target pixel in the pixel array to enable; the pulse detection sub-circuit is further configured to generate a detection pulse signal according to the pulse command signal and the first control signal, and determine whether the pulse command signal and the detection pulse signal match.

49. The image sensor of claim 48, wherein, The waveform of the pulse command signal has a first voltage edge and a second voltage edge, and the waveform of the first control signal has a third voltage edge and a fourth voltage edge; the waveform of the detection pulse signal has a fifth voltage edge, and the fifth voltage edge is generated according to one of the first voltage edge and the third voltage edge.

50. The image sensor of claim 49, wherein, The slope of the third voltage edge is greater than the slope of the fourth voltage edge, and the fifth voltage edge is generated according to the third voltage edge.

51. The image sensor of claim 49 or 50, wherein, The waveform of the detection pulse signal further has a sixth voltage edge, and the sixth voltage edge is generated according to one of the second voltage edge and the fourth voltage edge; and the voltage edges according to which the fifth voltage edge and the sixth voltage edge are generated belong to different signals.

52. The image sensor of claim 51, wherein, The slope of the third voltage edge is greater than the slope of the fourth voltage edge, and the sixth voltage edge is generated according to the second voltage edge.

53. The image sensor of claim 51 or 52, wherein, The determination of whether the detection pulse signal and the pulse command signal match comprises: determining whether a time difference between the first voltage edge of the pulse command signal and the fifth voltage edge of the detection pulse signal is within a first preset range, to obtain a first determination result.

54. The image sensor of claim 53, wherein, The determination of whether the detection pulse signal and the pulse command signal match further comprises: determining whether a time difference between the second voltage edge of the pulse command signal and the sixth voltage edge of the detection pulse signal is within the first preset range, to obtain a second determination result; based on the first determination result and the second determination result both being match, it is determined that the detection pulse signal and the pulse command signal match; determining that the detection pulse signal and the pulse command signal are not matched based on at least one of the first determination result and the second determination result being not matched.

55. The image sensor of claim 54, wherein, outputting a first matching result to the image processing circuit in a case where the detection pulse signal and the pulse command signal are matched; the first matching result being used to represent that the pixel control signal output by the row driving circuit is the correct pixel control signal; outputting a second matching result to the image processing circuit in a case where the detection pulse signal and the pulse command signal are not matched; the second matching result being used to represent that the pixel control signal output by the row driving circuit is the incorrect pixel control signal.

56. The image sensor of any of claims 48-55, wherein, The pulse detection sub-circuit comprises: a flip-flop, a first input end of the flip-flop being electrically connected with the image signal processing circuit, and a second input end of the flip-flop being configured to receive the first control signal; the flip-flop being configured to output the detection pulse signal according to the pulse command signal output by the image processing circuit and the received first control signal.

57. The image sensor of claim 56, wherein, The pulse detection sub-circuit further comprises: a logic gate circuit, a first input end of the logic gate circuit being electrically connected with an output end of the flip-flop, and a second input end of the logic gate circuit being electrically connected with the image signal processing circuit; the logic gate circuit being configured to determine whether the pulse command signal and the detection pulse signal are matched according to the pulse command signal output by the image processing circuit and the detection pulse signal output by the flip-flop.

58. The image sensor of claim 57, wherein, The pulse detection sub-circuit further comprises: a buffer, an input end of the buffer being electrically connected with an output end of the logic gate circuit, and an output end of the buffer being electrically connected with an input end of the image signal processing circuit; the buffer being configured to receive a determination result of whether the pulse command signal and the detection pulse signal are matched and output the determination result to the image signal processing circuit.

59. The image sensor of claim 58, wherein, The pixel control signal comprises a plurality of sub-control signals; The pulse detection sub-circuit comprises a plurality of pulse detection units, each pulse detection unit of the plurality of pulse detection units comprising the flip-flop, the logic gate circuit and the buffer which are electrically connected in sequence; the flip-flops of the plurality of pulse detection units are respectively used to receive the plurality of sub-control signals of the pixel control signal.

60. The image sensor of any of claims 48-59, wherein, The detection circuit further comprises: a conversion sub-circuit, the pulse detection sub-circuit being connected with the conversion sub-circuit; the conversion sub-circuit being configured to acquire the pixel control signal from the row driving circuit, perform voltage reduction processing on the pixel control signal to obtain the first control signal, and output the first control signal to the pulse detection sub-circuit; the voltage of the first control signal being lower than the voltage of the pixel control signal.

61. The image sensor of claim 60, wherein, The conversion sub-circuit comprises an amplifying device and a switching device; The first end of the amplification device is connected with a ground terminal, the second end of the amplification device is connected with the first end of the switching device, and the third end of the amplification device is connected with the row driving circuit; the amplification device is configured to receive the pixel control signal and perform voltage reduction processing on the pixel control signal; The second end of the switching device is connected with the pulse detection sub-circuit, and the third end of the switching device is connected with the row driving circuit; the switching device is configured to output the pixel control signal after voltage reduction processing from the amplification device under the control of a row selection signal output by the row driving circuit; the row selection signal is used to indicate the row address of the target pixel corresponding to the pixel control signal in the pixel array.

62. The image sensor of claim 61, wherein, The amplification device includes a first transistor, a first electrode of the first transistor is connected to the first end of the amplification device, a second electrode of the first transistor is connected to the second end of the amplification device, and a control electrode of the first transistor is connected to the third end of the amplification device; The switching device includes a second transistor, a first electrode of the second transistor is connected to the first end of the switching device, a second electrode of the second transistor is connected to the second end of the switching device, and a control electrode of the second transistor is connected to the third end of the switching device.

63. The image sensor of claim 61 or 62, wherein, The pixel control signal includes a plurality of sub-control signals; The conversion sub-circuit includes a plurality of converters, each of the plurality of converters includes the amplification device and the switching device connected in series; The plurality of sub-control signals of the pixel control signal received by the amplification devices of the plurality of converters.

64. The image sensor of any one of claims 60-63, the detection circuit further comprising: a biasing sub-circuit, an output terminal of the biasing sub-circuit is electrically connected with the second end of the switching device of the conversion sub-circuit; the biasing sub-circuit is configured to provide a biasing current for the conversion sub-circuit.

65. The image sensor of claim 64, wherein, The biasing sub-circuit includes a plurality of current source devices, an output terminal of each of the plurality of current source devices is electrically connected with the second end of the switching device of one of the plurality of converters; the current source device is configured to output the biasing current to the converter.

66. The image sensor of any of claims 48-65, wherein, The pulse detection sub-circuit is connected with the row driving circuit; the pulse detection sub-circuit is configured to acquire the pixel control signal from the row driving circuit, and take the pixel control signal as the first control signal.

67. The image sensor of any one of claims 48-66, the detection circuit further comprising: a row selection detection sub-circuit configured to acquire predetermined row address command information from the image signal processing circuit; the predetermined row address command information is used to specify the row address of the target pixel in the pixel array; the row selection detection sub-circuit is further configured to acquire predetermined row address selection information from the row driving circuit; the predetermined row address selection information is used to indicate the row address of the pixel selected by the row driving circuit according to the predetermined row address command information in the pixel array; The row selection detection sub-circuit is further configured to determine whether the predetermined row address command information and the predetermined row address selection information match.

68. The image sensor of claim 67, wherein, The determination of whether the predetermined row address command information and the predetermined row address selection information match includes: determining whether the row address of the target pixel specified by the predetermined row address command information and the row address of the pixel corresponding to the predetermined row address selection information in the pixel array are the same row address, to obtain a third determination result.

69. The image sensor of claim 68, wherein, The determination of whether the predetermined row address command information and the predetermined row address selection information match further includes: inverting the phases of the predetermined row address command information and the predetermined row address selection information; determining whether the predetermined row address command information and the predetermined row address selection information after phase inversion are the same row address, to obtain a fourth determination result; determining that the predetermined row address command information and the predetermined row address selection information match based on the third determination result and the fourth determination result both being match; determining that the predetermined row address command information and the predetermined row address selection information do not match based on at least one of the third determination result and the fourth determination result being mismatch.

70. The image sensor of claim 69, wherein, outputting a third matching result to the image processing circuit in the case that the predetermined row address command information and the predetermined row address selection information match; the third matching result is used to represent that the row address of the pixel selected by the row driving circuit according to the predetermined row address command information is a correct row address in the pixel array; outputting a fourth matching result to the image processing circuit in the case that the predetermined row address command information and the predetermined row address selection information do not match; the fourth matching result is used to represent that the row address of the pixel selected by the row driving circuit according to the predetermined row address command information is an incorrect row address in the pixel array.

71. The image sensor of any one of claims 45-70, for use in an electronic device, the electronic device further comprising a circuit board in electrical connection with the image sensor.

72. A method of controlling an image sensor, wherein, The image sensor includes a plurality of pixel units, the pixel units including a plurality of photodiodes, and the method includes: outputting an image signal based on a target pixel readout mode, wherein the image sensor includes a plurality of pixel readout modes, at least one of an exposure time, a gain, and a number of enabled photodiodes of any two of the plurality of pixel readout modes being different, and the target pixel readout mode is at least one of the plurality of pixel readout modes.

73. The control method of the image sensor of claim 72, further comprising: determining the target pixel readout mode based on a current shooting scene, the current shooting scene including at least one of: an overexposure scene, a high-light scene, a medium-light scene, or a low-light scene; and a high-dynamic scene or a low-dynamic scene.

74. The method of controlling an image sensor according to claim 72 or 73, wherein, The pixel readout mode includes a first mode, a second mode, a third mode, and a fourth mode.

75. The control method of the image sensor of claim 74, further satisfying at least one of: The number of the photodiodes enabled in the first mode, the second mode and the fourth mode is greater than the number of the photodiodes enabled in the third mode; The exposure time in the first mode, the second mode and the third mode is greater than the exposure time in the fourth mode; and The gain of the second mode, the third mode and the fourth mode is less than the gain of the first mode.

76. The method of controlling an image sensor according to claim 75, wherein, The image signal is output based on the target pixel readout mode, including: The corresponding image signal is output based on the first mode, the second mode, the third mode and the fourth mode in sequence.

77. The method of controlling the image sensor according to any one of claims 74-76, satisfying one of: The pixel unit includes 4 photodiodes, the number of the photodiodes enabled in the first mode, the second mode and the fourth mode is 4, and the number of the photodiodes enabled in the third mode is 1, 2 or 3; The number of the photodiodes enabled in the first mode, the second mode and the fourth mode is 3, and the number of the photodiodes enabled in the third mode is 1 or 2; or The number of the photodiodes enabled in the first mode, the second mode and the fourth mode is 2, and the number of the photodiodes enabled in the third mode is 1.

78. The method of controlling an image sensor according to any one of claims 74-76, wherein, The exposure time in the first mode, the second mode and the third mode is N times of the exposure time in the fourth mode, and the N is greater than 1.

79. The method of controlling the image sensor according to claim 74 or 75, wherein, In a scene of at least one of overexposure and high dynamic, the target pixel readout mode includes the fourth mode; In a scene of at least one of high brightness and low dynamic, the target pixel readout mode includes the third mode; In a scene of at least one of medium brightness and low dynamic, the target pixel readout mode includes the second mode; In a scene of at least one of low brightness and low dynamic, the target pixel readout mode includes the first mode.

80. The method of controlling an image sensor according to claim 74, wherein, The image signal is output based on the target pixel readout mode, including: The corresponding image signal is output in each pixel readout mode in the target pixel readout mode.

81. The method of controlling an image sensor according to any one of claims 74-80, wherein, The photodiode is controlled by a corresponding enable signal, the photodiode is enabled when the enable signal is high; the gain of the image signal is controlled by a corresponding gain control signal, the image signal corresponds to high gain when the gain control signal is low; the exposure time of the pixel unit is controlled by the enable signal and a reset signal of the corresponding photodiode, and the exposure time of the pixel unit is determined based on the interval of the enable signal and the reset signal.

82. The method of controlling an image sensor according to claim 81, wherein, In the first mode, the enable signal of the first number of the photodiodes remains high within a preset time length, the gain control signal is low, and the exposure time is a first time length.

83. The method of controlling an image sensor according to claim 81, wherein, In the second mode, the enable signal of each of the first number of the photodiodes is high, the gain control signal is high, and the exposure time is a first length.

84. The method of controlling an image sensor according to claim 81, wherein, In the third mode, the enable signal of each of a second number of the photodiodes is high, the gain control signal is high, and the exposure time is a second length, the second number being less than the first number of the photodiodes enabled in the first mode, and the second length being greater than the first length of the exposure in the first mode.

85. The method of controlling an image sensor according to claim 81, wherein, In the fourth mode, the enable signal of each of the first number of the photodiodes is high, the gain control signal is high, and the exposure time is a third length, the third length being less than the first length of the exposure in the first mode.

86. The method of controlling an image sensor according to any one of claims 72-85, wherein, The image sensor further comprises a first analog-to-digital converter and a second analog-to-digital converter, each connected to the pixel unit to collect the image signal output by the pixel unit.

87. The method of controlling an image sensor according to any one of claims 72-86, for use in an image acquisition device further comprising a control circuit configured to perform the method of controlling an image sensor.

88. A vehicle comprising the camera according to claim 25, or the image acquisition device according to claim 87.

Images