Pixel circuit, display apparatus, and driving method

Abstract

The present disclosure provides a pixel circuit, a display apparatus, and a driving method. The pixel circuit comprises: a light-emitting device; a driving transistor, coupled to the light-emitting device, and configured to generate, on the basis of a data voltage signal, a driving current for driving the light-emitting device to emit light; a first control circuit, coupled to a first node and a set electrode of the driving transistor, and configured to control, in response to a signal of a first control signal terminal, the first node to be connected to the set electrode of the driving transistor, the set electrode being a gate of the driving transistor or a second electrode of the driving transistor; a data writing circuit, coupled to the first node, and configured to provide, in response to a signal of a scanning signal terminal, a data voltage signal of the data signal terminal to the first node; a coupling control circuit, coupled to the first node and the gate of the driving transistor, and configured to couple a signal of the first node to the gate of the driving transistor; a second control circuit, coupled to the gate and the second electrode of the driving transistor, and configured to control, in response to a signal of a second control signal terminal, the gate of the driving transistor to be connected to the second electrode of the driving transistor; and a first light-emitting control circuit, coupled to the second electrode of the driving transistor and the light-emitting device, and configured to connect, in response to a signal of a first light-emitting control signal terminal, the second electrode of the driving transistor to the light-emitting device.

Description

Pixel circuit, display device and driving method

[0001] Cross-reference to related applications

[0002] The present application claims priority to the Chinese patent application No. 202411320561.X, filed on September 20, 2024, and entitled “Pixel circuit, display device and driving method”, the entire content of which is incorporated herein by reference. TECHNICAL FIELD

[0003] The present disclosure relates to the technical field of display, and in particular, to a pixel circuit, a display device and a driving method. BACKGROUND

[0004] Organic Light Emitting Diode (OLED), Quantum Dot Light Emitting Diodes (QLED), Micro Light Emitting Diode (Micro LED), Mini Light Emitting Diode (Mini LED) and other light emitting devices have the advantages of self-luminescence and low energy consumption, and are one of the hotspots in the field of current display device application research. Pixel circuits are used in general display devices to drive light emitting devices to emit light. SUMMARY

[0005] The pixel circuit provided by the embodiments of the present disclosure comprises:

[0006] a light emitting device;

[0007] a driving transistor coupled with the light emitting device and configured to generate a driving current for driving the light emitting device to emit light according to a data voltage signal;

[0008] a first control circuit coupled with a first node and a set pole of the driving transistor and configured to control the first node and the set pole of the driving transistor to be turned on in response to a signal of a first control signal end; the set pole is a gate of the driving transistor or a second pole of the driving transistor;

[0009] a data writing circuit coupled with the first node and configured to provide the data voltage signal of a data signal end to the first node in response to a signal of a scanning signal end;

[0010] a coupling control circuit coupled with the first node and the gate of the driving transistor and configured to couple the signal of the first node to the gate of the driving transistor.

[0011] The second control circuit is coupled with the gate of the driving transistor and the second electrode of the driving transistor, and is configured to control the gate of the driving transistor and the second electrode of the driving transistor to be conductive in response to a signal of a second control signal terminal;

[0012] The first light-emitting control circuit is coupled with the second electrode of the driving transistor and the light-emitting device, and is configured to control the second electrode of the driving transistor and the light-emitting device to be conductive in response to a signal of a first light-emitting control signal terminal.

[0013] In some possible implementation manners, the first control circuit includes a first transistor.

[0014] The gate of the first transistor is coupled with the first control signal terminal, the first electrode of the first transistor is coupled with the first node, and the second electrode of the first transistor is coupled with the set electrode of the driving transistor.

[0015] In some possible implementation manners, a material of the active layer of the first transistor is low-temperature polysilicon material.

[0016] In some possible implementation manners, the second control circuit includes a second transistor.

[0017] The gate of the second transistor is coupled with the second control signal terminal, the first electrode of the second transistor is coupled with the gate of the driving transistor, and the second electrode of the second transistor is coupled with the second electrode of the driving transistor.

[0018] In some possible implementation manners, a material of the active layer of the second transistor is metal-oxide semiconductor material.

[0019] In some possible implementation manners, the coupling control circuit includes:

[0020] The first coupling control circuit is coupled with the first node and a second node, and is configured to couple a signal of the first node to the second node.

[0021] The second coupling control circuit is coupled with the second node and the gate of the driving transistor, and is configured to couple a signal of the second node to the gate of the driving transistor.

[0022] In some possible implementation manners, the first coupling control circuit includes a first capacitor.

[0023] A first electrode of the first capacitor is coupled with the first node, and a second electrode of the first capacitor is coupled with the second node.

[0024] In some possible implementations, the second coupling control circuit includes a second capacitor;

[0025] A first electrode of the second capacitor is coupled with the second node, and a second electrode of the second capacitor is coupled with the gate of the driving transistor.

[0026] In some possible implementations, the display panel further includes a third control circuit;

[0027] The third control circuit is coupled with the second node and configured to provide a signal of a reference voltage signal terminal to the second node in response to a signal of a third control signal terminal.

[0028] In some possible implementations, the third control circuit includes a third transistor;

[0029] A gate of the third transistor is coupled with the third control signal terminal, a first electrode of the third transistor is coupled with the second node, and a second electrode of the third transistor is coupled with the reference voltage signal terminal.

[0030] In some possible implementations, a material of an active layer of the third transistor is metal oxide semiconductor material.

[0031] In some possible implementations, the data writing circuit includes a fourth transistor;

[0032] A gate of the fourth transistor is coupled with the scan signal terminal, a first electrode of the fourth transistor is coupled with the data signal terminal, and a second electrode of the fourth transistor is coupled with the first node.

[0033] In some possible implementations, the first light emitting control circuit includes a fifth transistor;

[0034] A gate of the fifth transistor is coupled with the first light emitting control signal terminal, a first electrode of the fifth transistor is coupled with the second electrode of the driving transistor, and a second electrode of the fifth transistor is coupled with the light emitting device.

[0035] In some possible implementations, the display panel further includes a first initialization circuit coupled with the first node and configured to provide a signal of a first initialization signal terminal to the first node in response to a signal of a first reset signal terminal.

[0036] In some possible implementations, the first initialization circuit includes a sixth transistor;

[0037] A gate of the sixth transistor is coupled with the first reset signal terminal, a first electrode of the sixth transistor is coupled with the first node, and a second electrode of the sixth transistor is coupled with the first initialization signal terminal.

[0038] In some possible implementation manners, the display device further includes a second initialization circuit coupled to the light emitting device and configured to provide a signal of a second initialization signal terminal to the light emitting device in response to a signal of a second reset signal terminal.

[0039] In some possible implementation manners, the second initialization circuit includes a seventh transistor.

[0040] A gate of the seventh transistor is coupled to the second reset signal terminal, a first electrode of the seventh transistor is coupled to the light emitting device, and a second electrode of the seventh transistor is coupled to the second initialization signal terminal.

[0041] In some possible implementation manners, the display device further includes a third initialization circuit coupled to the first electrode of the driving transistor and configured to provide a signal of a third initialization signal terminal to the first electrode of the driving transistor in response to a signal of a third reset signal terminal.

[0042] In some possible implementation manners, the third initialization circuit includes an eighth transistor.

[0043] A gate of the eighth transistor is coupled to the third reset signal terminal, a first electrode of the eighth transistor is coupled to the first electrode of the driving transistor, and a second electrode of the eighth transistor is coupled to the third initialization signal terminal.

[0044] In some possible implementation manners, the display device further includes a second light emitting control circuit coupled to the first electrode of the driving transistor and configured to provide a signal of a first power supply terminal to the first electrode of the driving transistor in response to a signal of a second light emitting control signal terminal.

[0045] In some possible implementation manners, the second light emitting control circuit includes a ninth transistor.

[0046] A gate of the ninth transistor is coupled to the second light emitting control signal terminal, a first electrode of the ninth transistor is coupled to the first power supply terminal, and a second electrode of the ninth transistor is coupled to the first electrode of the driving transistor.

[0047] The display device provided by the embodiments of the present disclosure includes the pixel circuit.

[0048] The display device provided by the embodiments of the present disclosure includes the pixel circuit.

[0049] In the initialization phase, the first control circuit controls the first node and the set terminal of the driving transistor to be conductive in response to a signal of the first control signal terminal; the second control circuit controls the gate terminal of the driving transistor and the second terminal of the driving transistor to be conductive in response to a signal of the second control signal terminal; and the first light emitting control circuit controls the second terminal of the driving transistor and the light emitting device to be conductive in response to a signal of the first light emitting control signal terminal.

[0050] In the threshold voltage compensation phase, the second control circuit controls the gate terminal of the driving transistor and the second terminal of the driving transistor to be conductive in response to a signal of the second control signal terminal.

[0051] In the data writing phase, the data writing circuit provides the data voltage signal of the data signal terminal to the first node in response to a signal of the scanning signal terminal; the second control circuit controls the gate terminal of the driving transistor and the second terminal of the driving transistor to be conductive in response to a signal of the second control signal terminal; and the coupling control circuit couples the signal of the first node to the gate terminal of the driving transistor.

[0052] In the light emitting phase, the first light emitting control circuit controls the second terminal of the driving transistor and the light emitting device to be conductive in response to a signal of the first light emitting control signal terminal. BRIEF DESCRIPTION OF DRAWINGS

[0053] FIG. 1 is a structural schematic diagram of a pixel circuit according to some embodiments of the present disclosure;

[0054] FIG. 2 is another structural schematic diagram of a pixel circuit according to some embodiments of the present disclosure;

[0055] FIG. 3 is yet another structural schematic diagram of a pixel circuit according to some embodiments of the present disclosure;

[0056] FIG. 4 is a timing diagram of some signals according to some embodiments of the present disclosure;

[0057] FIG. 5 is a flowchart of a driving method of a pixel circuit according to some embodiments of the present disclosure;

[0058] FIG. 6 is yet another structural schematic diagram of a pixel circuit according to some embodiments of the present disclosure;

[0059] FIG. 7 is another timing diagram of some signals according to some embodiments of the present disclosure;

[0060] FIG. 8 is yet another structural schematic diagram of a pixel circuit according to some embodiments of the present disclosure;

[0061] FIG. 9 is yet another structural schematic diagram of a pixel circuit according to some embodiments of the present disclosure;

[0062] FIG. 10 is another signal timing diagram provided by an embodiment of the present disclosure;

[0063] FIG. 11 is another structural schematic diagram of a pixel circuit provided by an embodiment of the present disclosure;

[0064] FIG. 12 is another signal timing diagram provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0065] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all the embodiments. And the embodiments in the present disclosure and the features in the embodiments can be combined with each other without conflict. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort belong to the scope of protection of the present disclosure.

[0066] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood as the common meanings of the technical terms or scientific terms by those of ordinary skill in the art to which the present disclosure belongs. The terms "first", "second" and similar terms used in the present disclosure do not represent any order, quantity or importance, but are only used to distinguish different components. The terms "include" or "contain" and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, without excluding other elements or objects. The terms "connect" or "connected" and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0067] It should be noted that the sizes and shapes of the figures in the drawings do not reflect the true proportions, but only serve to illustrate the content of the present disclosure. And the same or similar reference numbers represent the same or similar elements or elements with the same or similar functions throughout.

[0068] The display device provided by the embodiments of the present disclosure includes a display panel, the display area of the display panel includes a plurality of pixel units arranged in an array, and each pixel unit includes a plurality of sub-pixels. For example, each pixel unit includes a red sub-pixel, a green sub-pixel and a blue sub-pixel, so that red, green and blue can be mixed to realize color display. Alternatively, the pixel unit can include a red sub-pixel, a green sub-pixel, a blue sub-pixel and a white sub-pixel, so that red, green, blue and white can be mixed to realize color display. Of course, in actual applications, the light-emitting color of the sub-pixels in the pixel unit can be designed and determined according to the actual application environment, which is not limited herein.

[0069] In the embodiments of the present disclosure, each sub-pixel includes a pixel circuit, and the pixel circuit includes a driving transistor and a light emitting device to control the light emitting device to emit light, so that the display panel realizes the function of picture display. Due to process and device aging, etc., the threshold voltage Vth of the driving transistor for driving the light emitting device to emit light is not uniform, which causes the current flowing through different light emitting devices to change, resulting in uneven display brightness, thereby affecting the display effect of the entire image.

[0070] Generally, the components in the pixel circuit can be detected by array test (AT). For example, the data signal end in the pixel circuit is connected with a detection device (for example, a current sensor), and the current at the data signal end is detected to determine whether the pixel circuit meets the requirements. If the value of the current detected by the data signal end is less than or equal to a preset value, the requirements are met. The preset value can be selected according to the actual situation. For example, if the requirements of the pixel circuit are high, the preset value can be small, and if the requirements of the pixel circuit are low, the preset value can be large.

[0071] In the prior art, for the separated pixel circuit, the gate of the driving transistor in the pixel circuit cannot be directly detected, so that it is not possible to determine whether the driving transistor is abnormal, and the pixel circuit cannot be repaired immediately, which may result in that after the preparation process of the pixel circuit is completed (for example, the preparation of the light emitting device), it is found that the pixel circuit cannot work normally, which leads to cost waste, and further leads to high preparation cost of the display panel.

[0072] To solve the above problems, the pixel circuit provided in the embodiments of the present disclosure includes:

[0073] a light emitting device;

[0074] a driving transistor T0, coupled with the light emitting device L, configured to generate a driving current for driving the light emitting device L to emit light according to a data voltage signal;

[0075] a first control circuit 10, coupled with the first node N1 and a set electrode of the driving transistor T0, configured to control the first node N1 and the set electrode of the driving transistor T0 to be conductive in response to a signal of a first control signal end CS1; the set electrode is a second electrode of the driving transistor T0;

[0076] a data writing circuit 20, coupled with the first node N1, configured to provide a data voltage signal of a data signal end DA to the first node N1 in response to a signal of a scanning signal end SS1;

[0077] a coupling control circuit 30, coupled with the first node N1 and a gate of the driving transistor T0, configured to couple the signal of the first node N1 to the gate of the driving transistor T0.

[0078] The second control circuit 40 is coupled with the gate of the driving transistor T0 and the second electrode of the driving transistor T0, and is configured to control the gate of the driving transistor T0 and the second electrode of the driving transistor T0 to be conductive in response to a signal of the second control signal end CS2.

[0079] The first light-emitting control circuit 50 is coupled with the second electrode of the driving transistor T0 and the light-emitting device L, and is configured to control the second electrode of the driving transistor T0 and the light-emitting device L to be conductive in response to a signal of the first light-emitting control signal end EM1.

[0080] The mutual cooperation of the first control circuit, the data writing circuit, the coupling control circuit, the second control circuit, and the first light-emitting control circuit can directly detect the gate of the driving transistor, i.e., directly detect the gate of the driving transistor through array testing, and can also test each component in the pixel circuit through array testing, thereby realizing yield monitoring for the pixel circuit, reducing the risk of loss, avoiding cost waste, and further reducing the influence of process fluctuation on display effect.

[0081] In addition, the mutual cooperation of the first control circuit, the data writing circuit, the coupling control circuit, the second control circuit, and the first light-emitting control circuit realizes separate threshold voltage compensation of the driving transistor and data voltage signal writing, so that the threshold voltage compensation time of the driving transistor can not be limited by data voltage signal writing, and the threshold voltage compensation process can be performed for a long time, which is beneficial to the stability of the threshold voltage of the driving transistor, thereby realizing high frame rate display and avoiding the influence of threshold voltage drift of the driving transistor on the light-emitting of the light-emitting device, and improving the picture quality of high frame rate display.

[0082] In some embodiments of the present disclosure, as shown in the figure, the driving transistor T0 can be set as a P-type transistor; wherein the first electrode of the driving transistor T0 can be its source electrode, the second electrode of the driving transistor T0 can be its drain electrode, and when the driving transistor T0 is in a saturation state, the current flows from the source electrode to the drain electrode of the driving transistor T0. Of course, the driving transistor T0 can also be set as an N-type transistor, which is not limited here.

[0083] In the embodiments of the present disclosure, as shown in FIG. 1, the first electrode of the light emitting device L can be coupled with the second electrode of the driving transistor T0 through the first light emitting control circuit 50. The second electrode of the light emitting device L can be coupled with the second power supply end VSS. In some examples, the first electrode of the light emitting device L can be the anode thereof, and the second electrode can be the cathode thereof. For example, the light emitting device L can include at least one of a Micro Light Emitting Diode (Micro LED), an Organic Light Emitting Diode (OLED), and a Quantum Dot Light Emitting Diodes (QLED). For example, the light emitting device L can include an anode, a light emitting layer, and a cathode which are arranged in a stack. Further, the light emitting layer can further include a hole injection layer, a hole transport layer, an electron transport layer, an electron injection layer, and the like. In actual applications, the specific structure of the light emitting device L can be designed according to the actual application environment, which is not limited herein.

[0084] In the embodiments of the present disclosure, as shown in FIG. 2, the coupling control circuit 30 includes a first coupling control circuit 301 and a second coupling control circuit 302; wherein the first coupling control circuit 301 is coupled with the first node N1 and the second node N2, and is configured to couple the signal of the first node N1 to the second node N2; the second coupling control circuit 302 is coupled with the second node N2 and the gate of the driving transistor T0, and is configured to couple the signal of the second node N2 to the gate of the driving transistor T0.

[0085] In the embodiments of the present disclosure, as shown in FIG. 3, the first coupling control circuit 301 includes a first capacitor C1; wherein the first electrode of the first capacitor C1 is coupled with the first node N1, and the second electrode of the first capacitor C1 is coupled with the second node N2.

[0086] In the embodiments of the present disclosure, as shown in FIG. 3, the second coupling control circuit 302 includes a second capacitor C2; wherein the first electrode of the second capacitor C2 is coupled with the second node N2, and the second electrode of the second capacitor C2 is coupled with the gate of the driving transistor T0.

[0087] In the embodiments of the present disclosure, as shown in FIG. 3, the first control circuit 10 includes a first transistor T1; wherein the gate of the first transistor T1 is coupled with the first control signal end CS1, the first electrode of the first transistor T1 is coupled with the first node N1, and the second electrode of the first transistor T1 is coupled with the set electrode of the driving transistor T0.

[0088] Exemplarily, the first transistor T1 can be turned on under the control of an effective level of the first control signal transmitted by the first control signal end CS1, and can be turned off under the control of an ineffective level of the first control signal. Exemplarily, the first transistor T1 is set as a P-type transistor, and the effective level of the first control signal is a low level and the ineffective level of the first control signal is a high level. Alternatively, the first transistor T1 is set as an N-type transistor, and the effective level of the first control signal is a high level and the ineffective level of the first control signal is a low level.

[0089] In the embodiment of the present disclosure, the material of the active layer of the first transistor T1 is a low temperature poly-silicon material.

[0090] It should be noted that the low temperature poly-silicon (LTPS) material has high mobility as the active layer of the transistor and can be made thinner and smaller, has lower power consumption, etc. In the specific implementation, the material of the active layer of the first transistor T1 is set as a low temperature poly-silicon material. In this way, the first transistor T1 can be set as an LTPS transistor, so that the pixel circuit has high mobility and can be made thinner and smaller, has lower power consumption, etc.

[0091] In the embodiment of the present disclosure, as shown in FIG. 3, the second control circuit 20 includes a second transistor T2; wherein the gate of the second transistor T2 is coupled with the second control signal end CS2, the first pole of the second transistor T2 is coupled with the gate of the driving transistor T0, and the second pole of the second transistor T2 is coupled with the second pole of the driving transistor T0.

[0092] Exemplarily, the second transistor T2 can be turned on under the control of an effective level of the second control signal transmitted by the second control signal end CS2, and can be turned off under the control of an ineffective level of the second control signal. Exemplarily, the second transistor T2 is set as a P-type transistor, and the effective level of the second control signal is a low level and the ineffective level of the second control signal is a high level. Alternatively, the second transistor T2 is set as an N-type transistor, and the effective level of the second control signal is a high level and the ineffective level of the second control signal is a low level.

[0093] In the embodiment of the present disclosure, the material of the active layer of the second transistor T2 is a metal oxide semiconductor material.

[0094] It should be noted that the transistor with the metal oxide semiconductor material as the active layer has a small leakage current, and therefore, in some embodiments of the present disclosure, the material of the active layer of the second transistor T2 can also include a metal oxide semiconductor material, for example, can be IGZO (Indium Gallium Zinc Oxide), and of course, can also be other metal oxide semiconductor materials, which are not limited herein. In this way, the second transistor T2 can be set as an oxide transistor (Oxide Thin Film Transistor) to reduce the leakage current of the pixel circuit.

[0095] In the embodiments of the present disclosure, as shown in FIG. 3, the third control circuit 60 is further included; the third control circuit 60 is coupled with the second node N2 and is configured to provide a signal of the reference voltage signal end Vref to the second node N2 in response to a signal of the third control signal end CS3.

[0096] In the embodiments of the present disclosure, as shown in FIG. 3, the third control circuit 60 includes a third transistor T3; the gate of the third transistor T3 is coupled with the third control signal end CS3, the first pole of the third transistor T3 is coupled with the second node N2, and the second pole of the third transistor T3 is coupled with the reference voltage signal end Vref.

[0097] Exemplarily, the third transistor T3 can be turned on under the control of the effective level of the third control signal transmitted by the third control signal end CS3, and can be turned off under the control of the invalid level of the third control signal. Exemplarily, the third transistor T3 is set as a P-type transistor, and the effective level of the third control signal is low, and the invalid level of the third control signal is high. Alternatively, the third transistor T3 is set as an N-type transistor, and the effective level of the third control signal is high, and the invalid level of the third control signal is low.

[0098] Exemplarily, the second control signal end CS2 and the third control signal end CS3 can load the same signal, and such a setting simplifies the line arrangement, reduces the wiring difficulty, and saves space.

[0099] Exemplarily, the reference voltage signal end Vref and the first power supply end VDD can load the same signal, and such a setting simplifies the line arrangement, reduces the wiring difficulty, and saves space.

[0100] In the embodiments of the present disclosure, the material of the active layer of the third transistor T3 is a metal oxide semiconductor material.

[0101] It should be noted that the transistor with the metal oxide semiconductor material as the active layer has a small leakage current, and therefore, in some embodiments of the present disclosure, the material of the active layer of the third transistor T3 can also include a metal oxide semiconductor material, for example, can be IGZO (Indium Gallium Zinc Oxide), and of course, can also be other metal oxide semiconductor materials, which are not limited herein. In this way, the third transistor T3 can be set as an oxide transistor (Oxide Thin Film Transistor), so as to reduce the leakage current of the pixel circuit.

[0102] In the embodiment of the present disclosure, as shown in FIG. 3, the data writing circuit 20 includes a fourth transistor T4; a gate of the fourth transistor T4 is coupled with the scanning signal end SS1, a first pole of the fourth transistor T4 is coupled with the data signal end DA, and a second pole of the fourth transistor T4 is coupled with the first node N1.

[0103] For example, the fourth transistor T4 can be turned on under the control of the effective level of the scanning signal transmitted by the scanning signal end SS1, and can be turned off under the control of the invalid level of the scanning signal. For example, the fourth transistor T4 is set as a P-type transistor, and the effective level of the scanning signal is low, and the invalid level of the scanning signal is high. Alternatively, the fourth transistor T4 is set as an N-type transistor, and the effective level of the scanning signal is high, and the invalid level of the scanning signal is low.

[0104] In the embodiment of the present disclosure, as shown in FIG. 3, the first light emitting control circuit 50 includes a fifth transistor T5; a gate of the fifth transistor T5 is coupled with the first light emitting control signal end EM1, a first pole of the fifth transistor T5 is coupled with the second pole of the driving transistor T0, and a second pole of the fifth transistor T5 is coupled with the light emitting device L.

[0105] For example, the fifth transistor T5 can be turned on under the control of the effective level of the first light emitting control signal transmitted by the first light emitting control signal end EM1, and can be turned off under the control of the invalid level of the first light emitting control signal. For example, the fifth transistor T5 is set as a P-type transistor, and the effective level of the first light emitting control signal is low, and the invalid level of the first light emitting control signal is high. Alternatively, the fifth transistor T5 is set as an N-type transistor, and the effective level of the first light emitting control signal is high, and the invalid level of the first light emitting control signal is low.

[0106] In the embodiment of the present disclosure, as shown in FIG. 3, further comprising a first initialization circuit 70 coupled with the first node N1 and configured to provide a signal of a first initialization signal end Vinit1 to the first node N1 in response to a signal of a first reset signal end RE1.

[0107] In the embodiment of the present disclosure, as shown in FIG. 3, the first initialization circuit 70 comprises a sixth transistor T6; wherein the gate of the sixth transistor T6 is coupled with the first reset signal terminal RE1, the first pole of the sixth transistor T6 is coupled with the first node N1, and the second pole of the sixth transistor T6 is coupled with the first initialization signal terminal Vinit1.

[0108] For example, the first reset signal terminal RE1 and the first light-emitting control signal terminal EM1 can load the same signal, which simplifies the circuit arrangement, reduces the wiring difficulty, and saves space.

[0109] For example, the sixth transistor T6 can be turned on under the control of the effective level of the first reset signal transmitted by the first reset signal terminal RE1, and can be turned off under the control of the invalid level of the first reset signal. For example, the sixth transistor T6 is set as a P-type transistor, and the effective level of the first reset signal is low, and the invalid level of the first reset signal is high. Alternatively, the sixth transistor T6 is set as an N-type transistor, and the effective level of the first reset signal is high, and the invalid level of the first reset signal is low.

[0110] In the embodiment of the present disclosure, as shown in FIG. 3, the second initialization circuit 80 is further coupled with the light-emitting device L and configured to provide the signal of the second initialization signal terminal Vinit2 to the light-emitting device L in response to the signal of the second reset signal terminal RE2.

[0111] In the embodiment of the present disclosure, as shown in FIG. 3, the second initialization circuit 80 comprises a seventh transistor T7; wherein the gate of the seventh transistor T7 is coupled with the second reset signal terminal RE2, the first pole of the seventh transistor T7 is coupled with the light-emitting device L, and the second pole of the seventh transistor T7 is coupled with the second initialization signal terminal Vinit2.

[0112] For example, the seventh transistor T7 can be turned on under the control of the effective level of the second reset signal transmitted by the second reset signal terminal RE2, and can be turned off under the control of the invalid level of the second reset signal. For example, the seventh transistor T7 is set as a P-type transistor, and the effective level of the second reset signal is low, and the invalid level of the second reset signal is high. Alternatively, the seventh transistor T7 is set as an N-type transistor, and the effective level of the second reset signal is high, and the invalid level of the second reset signal is low.

[0113] For example, the second transistor T2 and the third transistor T3 can be oxide transistors, and the driving transistor T0, the first transistor T1, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 can be LTPS transistors. In this way, by combining the LTPS transistors and the oxide transistors, the LTPO pixel driving circuit is prepared by combining the two processes of preparing the transistors, so that the gate leakage current of the driving transistor T0 is small, and the power consumption is low.

[0114] In the embodiments of the present disclosure, the first power supply end VDD can be configured to load a constant first power supply voltage vdd, and the first power supply voltage vdd is generally positive. In addition, the second power supply end VSS can load a constant second power supply voltage vss, and the second power supply voltage vss can generally be a ground voltage or a negative value. In actual applications, the specific values of the first power supply voltage vdd and the second power supply voltage vss can be designed and determined according to the actual application environment, which is not limited here.

[0115] In the embodiments of the present disclosure, as shown in FIG. 4, the driving method of the pixel circuit provided in the embodiments of the present disclosure includes an initialization stage F1, a threshold voltage compensation stage F2, a data writing stage F3 and a light emitting stage F4.

[0116] As shown in FIG. 5, the method can include the following steps:

[0117] In the initialization stage, the first control circuit controls the first node and the set electrode of the driving transistor to be conductive in response to the signal of the first control signal end; the second control circuit controls the gate of the driving transistor and the second electrode of the driving transistor to be conductive in response to the signal of the second control signal end; and the first light emitting control circuit controls the second electrode of the driving transistor and the light emitting device to be conductive in response to the signal of the first light emitting control signal end.

[0118] In the threshold voltage compensation stage, the second control circuit controls the gate of the driving transistor and the second electrode of the driving transistor to be conductive in response to the signal of the second control signal end.

[0119] In the data writing stage, the data writing circuit provides the data voltage signal of the data signal end to the first node in response to the signal of the scanning signal end; the second control circuit controls the gate of the driving transistor and the second electrode of the driving transistor to be conductive in response to the signal of the second control signal end; and the coupling control circuit couples the signal of the first node to the gate of the driving transistor.

[0120] In the light emitting stage, the first light emitting control circuit controls the second electrode of the driving transistor and the light emitting device to be conductive in response to the signal of the first light emitting control signal end.

[0121] As shown in FIG. 4, the driving method of the pixel circuit provided in the embodiment of the present disclosure further includes a reset stage F5 between the threshold voltage compensation stage F2 and the light emitting stage F4. In the reset stage F5, the second initialization circuit provides the second initialization signal end with a signal in response to a signal of the second reset signal end.

[0122] The working process of the pixel circuit provided in the embodiment of the present disclosure will be described below by taking the pixel circuit shown in FIG. 3 as an example and in combination with the signal timing diagram shown in FIG. 4.

[0123] In the embodiment of the present disclosure, as shown in FIG. 4, cs1 represents the first control signal of the first control signal end CS1, cs2 represents the second control signal of the second control signal end CS2, cs3 represents the third control signal of the third control signal end CS3, ss1 represents the scanning signal of the scanning signal end SS1, em1 represents the first light emitting control signal of the first light emitting control signal end EM1, re1 represents the first reset signal of the first reset signal end RE1, and re2 represents the second reset signal of the second reset signal end RE2.

[0124] In addition, the initialization stage F1, the threshold voltage compensation stage F2, the data writing stage F3, the reset stage F5 and the light emitting stage F4 in one display frame 1H are selected.

[0125] In the initialization stage F1, the first transistor T1 is turned on under the low level control of the first control signal cs1, the second transistor T2 is turned on under the high level control of the second control signal cs2, the third transistor T3 is turned on under the high level control of the third control signal cs3, the fourth transistor T4 is turned off under the high level control of the scanning signal ss1, the fifth transistor T5 is turned on under the low level control of the first light emitting control signal em1, the sixth transistor T6 is turned on under the low level control of the first reset signal re1, and the seventh transistor T7 is turned off under the high level control of the second reset signal re2. The turned-on sixth transistor T6 provides the signal of the first initialization signal terminal Vinit1 to the first node N1, and thus the voltage value VN1 of the first node is vini1, where vini1 represents the voltage value of the signal of the first initialization signal terminal Vinit1. The turned-on first transistor T1 controls the first node N1 and the second electrode of the driving transistor T0 to be conductive, and thus the voltage value of the second electrode of the driving transistor T0 is vini1. The turned-on second transistor T2 controls the gate of the driving transistor T0 and the second electrode of the driving transistor T0 to be conductive, and thus the voltage value of the gate of the driving transistor T0 is vini1. The turned-on fifth transistor T5 controls the second electrode of the driving transistor T0 and the light emitting device L to be conductive. The turned-on third transistor T3 provides the signal of the reference voltage signal terminal Vref to the second node N2, and thus the voltage value VN2 of the second node is vref, where vref represents the voltage value of the signal of the reference voltage signal terminal Vref.

[0126] In the threshold voltage compensation stage F2, the first transistor T1 is turned off under the high level control of the first control signal cs1, the second transistor T2 is turned on under the high level control of the second control signal cs2, the third transistor T3 is turned on under the high level control of the third control signal cs3, the fourth transistor T4 is turned off under the high level control of the scanning signal ss1, the fifth transistor T5 is turned off under the high level control of the first light emitting control signal em1, the sixth transistor T6 is turned off under the high level control of the first reset signal re1, and the seventh transistor T7 is turned on under the low level control of the second reset signal re2. The turned-on second transistor T2 controls the gate of the driving transistor T0 and the second electrode of the driving transistor T0 to be conductive. The turned-on third transistor T3 provides the signal of the reference voltage signal terminal Vref to the second node N2. Thus, the voltage values of the gate and the second electrode of the driving transistor T0 are both vdd+vth, where vdd represents the voltage value of the signal of the first power supply terminal, and vth represents the threshold voltage of the driving transistor T0. The turned-on seventh transistor T7 provides the signal of the second initialization signal terminal Vinit2 to the light emitting device L.

[0127] In the data writing stage F3, the first transistor T1 is turned off under the high level control of the first control signal cs1, the second transistor T2 is turned on under the high level control of the second control signal cs2, the third transistor T3 is turned on under the high level control of the third control signal cs3, the fourth transistor T4 is turned on under the low level control of the scanning signal ss1, the fifth transistor T5 is turned off under the high level control of the first light emitting control signal em1, the sixth transistor T6 is turned off under the high level control of the first reset signal re1, and the seventh transistor T7 is turned off under the high level control of the second reset signal re2. The turned-on second transistor T2 controls the gate of the driving transistor T0 and the second electrode of the driving transistor T0 to be turned on; the turned-on third transistor T3 provides the signal of the reference voltage signal end Vref to the second node N2; the turned-on fourth transistor T4 provides the data voltage signal of the data signal end DA to the first node N1; the first capacitor C1 couples the signal of the first node N1 to the second node N2, and the second capacitor C2 couples the signal of the second node N2 to the gate of the driving transistor T0.

[0128] In the reset stage F5, the first transistor T1 is turned off under the high level control of the first control signal cs1, the second transistor T2 is turned off under the low level control of the second control signal cs2, the third transistor T3 is turned off under the low level control of the third control signal cs3, the fourth transistor T4 is turned off under the high level control of the scanning signal ss1, the fifth transistor T5 is turned off under the high level control of the first light emitting control signal em1, the sixth transistor T6 is turned off under the high level control of the first reset signal re1, and the seventh transistor T7 is turned on under the low level control of the second reset signal re2. The turned-on seventh transistor T7 provides the signal of the second initialization signal end Vinit2 to the light emitting device L.

[0129] In the light emitting stage F4, the first transistor T1 is turned off under the high level control of the first control signal cs1, the second transistor T2 is turned off under the low level control of the second control signal cs2, the third transistor T3 is turned off under the low level control of the third control signal cs3, the fourth transistor T4 is turned off under the high level control of the scanning signal ss1, the fifth transistor T5 is turned on under the low level control of the first light emitting control signal em1, the sixth transistor T6 is turned on under the low level control of the first reset signal re1, and the seventh transistor T7 is turned off under the high level control of the second reset signal re2. The turned-on sixth transistor T6 provides the signal of the first initialization signal end Vinit1 to the first node N1; the turned-on fifth transistor T5 turns on the second electrode of the driving transistor T0 and the light emitting device L; the driving transistor T0 generates a driving current which charges the anode of the light emitting device L until the light emitting device L stably emits light.

[0130] The embodiment of the present disclosure provides another structural schematic diagram of the pixel driving circuit, as shown in FIG. 6, which is a variation of the implementation in the above embodiment. The following only describes the difference between the present embodiment and the above embodiment, and the same parts are not described here.

[0131] In the embodiment of the present disclosure, as shown in FIG. 6, the gate of the driving transistor T0 is set; the second electrode of the first transistor T1 is coupled with the gate of the driving transistor T0.

[0132] In the embodiment of the present disclosure, the material of the active layer of the first transistor T1 is metal oxide semiconductor material.

[0133] It should be noted that the leakage current of the transistor with metal oxide semiconductor material as the active layer is small, so in order to reduce the leakage current, in the embodiment of the present disclosure, the material of the active layer of the first transistor T1 can also include metal oxide semiconductor material, for example, it can be IGZO (Indium Gallium Zinc Oxide), and of course, it can also be other metal oxide semiconductor material, which is not limited here. In this way, the first transistor T1 can be set as an oxide transistor (Oxide Thin Film Transistor) to reduce the leakage current of the pixel circuit.

[0134] For example, the first transistor T1, the second transistor T2, and the third transistor T3 can be set as oxide transistors, and the driving transistor T0, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be set as LTPS transistors. In this way, by combining the processes of preparing the two kinds of transistors to prepare the LTPO pixel driving circuit of low-temperature polysilicon oxide, the leakage current of the gate of the driving transistor T0 is small, and the power consumption is low.

[0135] The following describes the working process of the pixel circuit provided by the embodiment of the present disclosure by taking the pixel circuit shown in FIG. 6 as an example and combining the signal timing diagram shown in FIG. 7.

[0136] In the embodiment of the present disclosure, as shown in FIG. 7, cs1 represents the first control signal of the first control signal end CS1, cs2 represents the second control signal of the second control signal end CS2, cs3 represents the third control signal of the third control signal end CS3, ss1 represents the scanning signal of the scanning signal end SS1, em1 represents the first light-emitting control signal of the first light-emitting control signal end EM1, re1 represents the first reset signal of the first reset signal end RE1, and re2 represents the second reset signal of the second reset signal end RE2.

[0137] And, select a display frame 1H in the initialization stage F1, threshold voltage compensation stage F2, data write stage F3, reset stage F5 and light-emitting stage F4.

[0138] In the initialization stage F1, the first transistor T1 is turned on under the high level control of the first control signal cs1, the second transistor T2 is turned on under the high level control of the second control signal cs2, the third transistor T3 is turned on under the high level control of the third control signal cs3, the fourth transistor T4 is turned off under the high level control of the scanning signal ss1, the fifth transistor T5 is turned on under the low level control of the first light-emitting control signal em1, the sixth transistor T6 is turned on under the low level control of the first reset signal re1, and the seventh transistor T7 is turned off under the high level control of the second reset signal re2. The turned-on sixth transistor T6 provides the signal of the first initialization signal terminal Vinit1 to the first node N1, so the voltage value VN1 of the first node is vini1; the turned-on first transistor T1 controls the first node N1 and the gate of the driving transistor T0 to be turned on, so the voltage value of the gate of the driving transistor T0 is vini1; the turned-on second transistor T2 controls the gate of the driving transistor T0 and the second electrode of the driving transistor T0 to be turned on, so the voltage value of the second electrode of the driving transistor T0 is vini1; the turned-on fifth transistor T5 controls the second electrode of the driving transistor T0 and the light-emitting device L to be turned on; and the turned-on third transistor T3 provides the signal of the reference voltage signal terminal Vref to the second node N2, so the voltage value VN2 of the second node is vref.

[0139] In the threshold voltage compensation stage F2, the first transistor T1 is turned off under the low level control of the first control signal cs1, the second transistor T2 is turned on under the high level control of the second control signal cs2, the third transistor T3 is turned on under the high level control of the third control signal cs3, the fourth transistor T4 is turned off under the high level control of the scanning signal ss1, the fifth transistor T5 is turned off under the high level control of the first light-emitting control signal em1, the sixth transistor T6 is turned off under the high level control of the first reset signal re1, and the seventh transistor T7 is turned on under the low level control of the second reset signal re2. The turned-on second transistor T2 controls the gate of the driving transistor T0 and the second electrode of the driving transistor T0 to be turned on; the turned-on third transistor T3 provides the signal of the reference voltage signal terminal Vref to the second node N2; then, the voltage values of the gate and the second electrode of the driving transistor T0 are both vdd+vth; and the turned-on seventh transistor T7 provides the signal of the second initialization signal terminal Vinit2 to the light-emitting device L.

[0140] In the data writing stage F3, the first transistor T1 is turned off under the low level control of the first control signal cs1, the second transistor T2 is turned on under the high level control of the second control signal cs2, the third transistor T3 is turned on under the high level control of the third control signal cs3, the fourth transistor T4 is turned on under the low level control of the scanning signal ss1, the fifth transistor T5 is turned off under the high level control of the first light emitting control signal em1, the sixth transistor T6 is turned off under the high level control of the first reset signal re1, and the seventh transistor T7 is turned off under the high level control of the second reset signal re2. The turned-on second transistor T2 controls the gate of the driving transistor T0 and the second electrode of the driving transistor T0 to be turned on; the turned-on third transistor T3 provides the signal of the reference voltage signal end Vref to the second node N2; the turned-on fourth transistor T4 provides the data voltage signal of the data signal end DA to the first node N1; the first capacitor C1 couples the signal of the first node N1 to the second node N2, and the second capacitor C2 couples the signal of the second node N2 to the gate of the driving transistor T0.

[0141] In the reset stage F5, the first transistor T1 is turned off under the low level control of the first control signal cs1, the second transistor T2 is turned off under the low level control of the second control signal cs2, the third transistor T3 is turned off under the low level control of the third control signal cs3, the fourth transistor T4 is turned off under the high level control of the scanning signal ss1, the fifth transistor T5 is turned off under the high level control of the first light emitting control signal em1, the sixth transistor T6 is turned off under the high level control of the first reset signal re1, and the seventh transistor T7 is turned on under the low level control of the second reset signal re2. The turned-on seventh transistor T7 provides the signal of the second initialization signal end Vinit2 to the light emitting device L.

[0142] In the light emitting stage F4, the first transistor T1 is turned off under the low level control of the first control signal cs1, the second transistor T2 is turned off under the low level control of the second control signal cs2, the third transistor T3 is turned off under the low level control of the third control signal cs3, the fourth transistor T4 is turned off under the high level control of the scanning signal ss1, the fifth transistor T5 is turned on under the low level control of the first light emitting control signal em1, the sixth transistor T6 is turned on under the low level control of the first reset signal re1, and the seventh transistor T7 is turned off under the high level control of the second reset signal re2. The turned-on sixth transistor T6 provides the signal of the first initialization signal end Vinit1 to the first node N1; the turned-on fifth transistor T5 turns on the second electrode of the driving transistor T0 and the light emitting device L; the driving transistor T0 generates a driving current which charges the anode of the light emitting device L until the light emitting device L stably emits light.

[0143] The embodiment of the present disclosure provides another structure diagram of the pixel driving circuit, as shown in Fig. 8, which is a variation of the above embodiment. The following only describes the difference between the present embodiment and the above embodiment, and the same parts are not described here.

[0144] In the embodiment of the present disclosure, as shown in Fig. 8, it further includes a third initialization circuit 90, which is coupled with the first electrode of the driving transistor T0 and configured to provide a signal of a third initialization signal terminal Vinit3 to the first electrode of the driving transistor T0 in response to a signal of a third reset signal terminal RE3.

[0145] In the embodiment of the present disclosure, as shown in Fig. 9, the third initialization circuit 90 includes an eighth transistor T8, wherein the gate of the eighth transistor T8 is coupled with the third reset signal terminal RE3, the first electrode of the eighth transistor T8 is coupled with the first electrode of the driving transistor T0, and the second electrode of the eighth transistor T8 is coupled with the third initialization signal terminal Vinit3.

[0146] For example, the eighth transistor T8 can be turned on under the control of the effective level of the third reset signal transmitted by the third reset signal terminal RE3, and can be turned off under the control of the invalid level of the third reset signal. For example, the eighth transistor T8 is set as a P-type transistor, and the effective level of the third reset signal is low, and the invalid level of the third reset signal is high. Alternatively, the eighth transistor T8 is set as an N-type transistor, and the effective level of the third reset signal is high, and the invalid level of the third reset signal is low.

[0147] For example, the second reset signal terminal RE2 and the third reset signal terminal RE3 can load the same signal, which simplifies the layout of the circuit, reduces the wiring difficulty, and saves space.

[0148] In the embodiment of the present disclosure, as shown in Fig. 8, it further includes a second light-emitting control circuit 100, which is coupled with the first electrode of the driving transistor T0 and configured to provide a signal of a first power supply terminal VDD to the first electrode of the driving transistor T0 in response to a signal of a second light-emitting control signal terminal EM2.

[0149] In the embodiment of the present disclosure, as shown in Fig. 9, the second light-emitting control circuit 100 includes a ninth transistor T9, wherein the gate of the ninth transistor T9 is coupled with the second light-emitting control signal terminal EM2, the first electrode of the ninth transistor T9 is coupled with the first power supply terminal VDD, and the second electrode of the ninth transistor T9 is coupled with the first electrode of the driving transistor T0.

[0150] Exemplarily, the ninth transistor T9 can be turned on under the control of an active level of the second light-emitting control signal transmitted by the second light-emitting control signal end EM2, and can be turned off under the control of an inactive level of the second light-emitting control signal. Exemplarily, the ninth transistor T9 is set as a P-type transistor, and the active level of the second light-emitting control signal is a low level, and the inactive level of the second light-emitting control signal is a high level. Alternatively, the ninth transistor T9 is set as an N-type transistor, and the active level of the second light-emitting control signal is a high level, and the inactive level of the second light-emitting control signal is a low level.

[0151] Exemplarily, the second transistor T2 and the third transistor T3 can be set as oxide transistors, and the driving transistor T0, the first transistor T1, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 can be set as LTPS transistors. In this way, by combining the LTPS transistor and the oxide transistor, the LTPO pixel driving circuit of low-temperature polysilicon oxide is prepared by combining the two processes of preparing the transistors, so that the gate leakage current of the driving transistor T0 is small, and the power consumption is low.

[0152] Next, taking the pixel circuit shown in FIG. 9 as an example, the working process of the pixel circuit provided in the embodiment of the present disclosure is described in combination with the signal timing diagram shown in FIG. 10.

[0153] In the embodiment of the present disclosure, as shown in FIG. 10, cs1 represents the first control signal of the first control signal end CS1, cs2 represents the second control signal of the second control signal end CS2, cs3 represents the third control signal of the third control signal end CS3, ss1 represents the scanning signal of the scanning signal end SS1, em1 represents the first light-emitting control signal of the first light-emitting control signal end EM1, em2 represents the second light-emitting control signal of the second light-emitting control signal end EM2, re1 represents the first reset signal of the first reset signal end RE1, re2 represents the second reset signal of the second reset signal end RE2, and re3 represents the third reset signal of the third reset signal end RE3.

[0154] In addition, the initialization stage F1, the threshold voltage compensation stage F2, the data writing stage F3, the reset stage F5 and the light-emitting stage F4 in one display frame 1H are selected.

[0155] In the initialization stage F1, the first transistor T1 is turned on under the low level control of the first control signal cs1, the second transistor T2 is turned on under the high level control of the second control signal cs2, the third transistor T3 is turned on under the high level control of the third control signal cs3, the fourth transistor T4 is turned off under the high level control of the scanning signal ss1, the fifth transistor T5 is turned on under the low level control of the first light emitting control signal em1, the sixth transistor T6 is turned on under the low level control of the first reset signal re1, the seventh transistor T7 is turned off under the high level control of the second reset signal re2, the eighth transistor T8 is turned off under the high level control of the third reset signal re3, and the ninth transistor T9 is turned off under the high level control of the second light emitting control signal em2. The turned-on sixth transistor T6 provides the signal of the first initialization signal terminal Vinit1 to the first node N1, so the voltage value VN1 of the first node is vini1; the turned-on first transistor T1 controls the first node N1 and the second electrode of the driving transistor T0 to be turned on, so the voltage value of the second electrode of the driving transistor T0 is vini1; the turned-on second transistor T2 controls the gate of the driving transistor T0 and the second electrode of the driving transistor T0 to be turned on, so the voltage value of the gate of the driving transistor T0 is vini1; the turned-on fifth transistor T5 controls the second electrode of the driving transistor T0 and the light emitting device L to be turned on; and the turned-on third transistor T3 provides the signal of the reference voltage signal terminal Vref to the second node N2, so the voltage value VN2 of the second node is vref.

[0156] In the threshold voltage compensation stage F2, the first transistor T1 is turned off under the high level control of the first control signal cs1, the second transistor T2 is turned on under the high level control of the second control signal cs2, the third transistor T3 is turned on under the high level control of the third control signal cs3, the fourth transistor T4 is turned off under the high level control of the scanning signal ss1, the fifth transistor T5 is turned off under the high level control of the first light emitting control signal em1, the sixth transistor T6 is turned off under the high level control of the first reset signal re1, the seventh transistor T7 is turned on under the low level control of the second reset signal re2, the eighth transistor T8 is turned on under the low level control of the third reset signal re3, and the ninth transistor T9 is turned on under the low level control of the second light emitting control signal em2. The turned-on second transistor T2 controls the gate of the driving transistor T0 and the second electrode of the driving transistor T0 to be turned on; the turned-on third transistor T3 provides the signal of the reference voltage signal end Vref to the second node N2; then, the voltage values of the gate and the second electrode of the driving transistor T0 are both vdd+vth; the turned-on seventh transistor T7 provides the signal of the second initialization signal end Vinit2 to the light emitting device L; the turned-on eighth transistor T8 provides the signal of the third initialization signal end Vinit3 to the first electrode of the driving transistor T0; and the turned-on ninth transistor T9 provides the signal of the first power supply end VDD to the first electrode of the driving transistor T0.

[0157] In the data writing stage F3, the first transistor T1 is turned off under the high level control of the first control signal cs1, the second transistor T2 is turned on under the high level control of the second control signal cs2, the third transistor T3 is turned on under the high level control of the third control signal cs3, the fourth transistor T4 is turned on under the low level control of the scanning signal ss1, the fifth transistor T5 is turned off under the high level control of the first light emitting control signal em1, the sixth transistor T6 is turned off under the high level control of the first reset signal re1, the seventh transistor T7 is turned off under the high level control of the second reset signal re2, the eighth transistor T8 is turned off under the high level control of the third reset signal re3, and the ninth transistor T9 is turned on under the low level control of the second light emitting control signal em2. The turned-on second transistor T2 controls the gate of the driving transistor T0 and the second electrode of the driving transistor T0 to be turned on; the turned-on third transistor T3 provides the signal of the reference voltage signal end Vref to the second node N2; the turned-on fourth transistor T4 provides the data voltage signal of the data signal end DA to the first node N1; the first capacitor C1 couples the signal of the first node N1 to the second node N2, and the second capacitor C2 couples the signal of the second node N2 to the gate of the driving transistor T0; the turned-on ninth transistor T9 provides the signal of the first power supply end VDD to the first electrode of the driving transistor T0.

[0158] In the reset stage F5, the first transistor T1 is turned off under the high level control of the first control signal cs1, the second transistor T2 is turned off under the low level control of the second control signal cs2, the third transistor T3 is turned off under the low level control of the third control signal cs3, the fourth transistor T4 is turned off under the high level control of the scanning signal ss1, the fifth transistor T5 is turned off under the high level control of the first light emitting control signal em1, the sixth transistor T6 is turned off under the high level control of the first reset signal re1, the seventh transistor T7 is turned on under the low level control of the second reset signal re2, the eighth transistor T8 is turned on under the low level control of the third reset signal re3, and the ninth transistor T9 is turned off under the low level control of the second light emitting control signal em2. The turned-on seventh transistor T7 provides the signal of the second initialization signal terminal Vinit2 to the light emitting device L, and the turned-on eighth transistor T8 provides the signal of the third initialization signal terminal Vinit3 to the first electrode of the driving transistor T0.

[0159] In the light emitting stage F4, the first transistor T1 is turned off under the high level control of the first control signal cs1, the second transistor T2 is turned off under the low level control of the second control signal cs2, the third transistor T3 is turned off under the low level control of the third control signal cs3, the fourth transistor T4 is turned off under the high level control of the scanning signal ss1, the fifth transistor T5 is turned on under the low level control of the first light emitting control signal em1, the sixth transistor T6 is turned on under the low level control of the first reset signal re1, the seventh transistor T7 is turned off under the high level control of the second reset signal re2, the eighth transistor T8 is turned off under the high level control of the third reset signal re3, and the ninth transistor T9 is turned on under the low level control of the second light emitting control signal em2. The turned-on sixth transistor T6 provides the signal of the first initialization signal terminal Vinit1 to the first node N1, the turned-on ninth transistor T9 provides the signal of the first power supply terminal VDD to the first electrode of the driving transistor T0, the turned-on fifth transistor T5 turns on the second electrode of the driving transistor T0 and the light emitting device L, and the driving transistor T0 generates a driving current which charges the anode of the light emitting device L until the light emitting device L stably emits light.

[0160] The present disclosure provides still another structure diagram of the pixel driving circuit, as shown in FIG. 11, which is a variation of the above-mentioned embodiment. The differences between the present embodiment and the above-mentioned embodiment are described below, and the same parts are not described herein.

[0161] In the present embodiment, as shown in FIG. 11, the gate electrode of the driving transistor T0 is set as the setting electrode, and the second electrode of the first transistor T1 is coupled to the gate electrode of the driving transistor T0.

[0162] In the embodiment of the present disclosure, the material of the active layer of the first transistor T1 is metal oxide semiconductor material.

[0163] It should be noted that the metal oxide semiconductor material has a small leakage current as the active layer of the transistor, and therefore, in order to reduce the leakage current, in the embodiment of the present disclosure, the material of the active layer of the first transistor T1 can also include metal oxide semiconductor material, for example, can be IGZO (Indium Gallium Zinc Oxide), and of course, can also be other metal oxide semiconductor material, which is not limited herein. In this way, the first transistor T1 can be set as an oxide transistor (Oxide Thin Film Transistor), so as to reduce the leakage current of the pixel circuit.

[0164] For example, the first transistor T1, the second transistor T2, and the third transistor T3 can be set as oxide transistors, and the driving transistor T0, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 can be set as LTPS transistors. In this way, by combining the LTPS transistor and the oxide transistor, which are two processes for preparing the transistor, the LTPO pixel driving circuit of low temperature polysilicon oxide can be prepared, so as to reduce the leakage current of the gate of the driving transistor T0 and reduce the power consumption.

[0165] Next, taking the pixel circuit shown in FIG. 11 as an example, the working process of the pixel circuit provided in the embodiment of the present disclosure is described in combination with the signal timing diagram shown in FIG. 12.

[0166] In the embodiment of the present disclosure, as shown in FIG. 12, cs1 represents the first control signal of the first control signal end CS1, cs2 represents the second control signal of the second control signal end CS2, cs3 represents the third control signal of the third control signal end CS3, ss1 represents the scanning signal of the scanning signal end SS1, em1 represents the first light-emitting control signal of the first light-emitting control signal end EM1, em2 represents the second light-emitting control signal of the second light-emitting control signal end EM2, re1 represents the first reset signal of the first reset signal end RE1, re2 represents the second reset signal of the second reset signal end RE2, and re3 represents the third reset signal of the third reset signal end RE3.

[0167] In addition, the initialization stage F1, the threshold voltage compensation stage F2, the data writing stage F3, the reset stage F5, and the light-emitting stage F4 in one display frame 1H are selected.

[0168] In the initialization stage F1, the first transistor T1 is turned on under the high level control of the first control signal cs1, the second transistor T2 is turned on under the high level control of the second control signal cs2, the third transistor T3 is turned on under the high level control of the third control signal cs3, the fourth transistor T4 is turned off under the high level control of the scanning signal ss1, the fifth transistor T5 is turned on under the low level control of the first light emitting control signal em1, the sixth transistor T6 is turned on under the low level control of the first reset signal re1, the seventh transistor T7 is turned off under the high level control of the second reset signal re2, the eighth transistor T8 is turned off under the high level control of the third reset signal re3, and the ninth transistor T9 is turned off under the high level control of the second light emitting control signal em2. The turned-on sixth transistor T6 provides the signal of the first initialization signal terminal Vinit1 to the first node N1, so the voltage value VN1 of the first node is vini1; the turned-on first transistor T1 controls the first node N1 and the second electrode of the driving transistor T0 to be turned on, so the voltage value of the second electrode of the driving transistor T0 is vini1; the turned-on second transistor T2 controls the gate of the driving transistor T0 and the second electrode of the driving transistor T0 to be turned on, so the voltage value of the gate of the driving transistor T0 is vini1; the turned-on fifth transistor T5 controls the second electrode of the driving transistor T0 and the light emitting device L to be turned on; and the turned-on third transistor T3 provides the signal of the reference voltage signal terminal Vref to the second node N2, so the voltage value VN2 of the second node is vref.

[0169] In the threshold voltage compensation stage F2, the first transistor T1 is turned off under the low level control of the first control signal cs1, the second transistor T2 is turned on under the high level control of the second control signal cs2, the third transistor T3 is turned on under the high level control of the third control signal cs3, the fourth transistor T4 is turned off under the high level control of the scanning signal ss1, the fifth transistor T5 is turned off under the high level control of the first light emitting control signal em1, the sixth transistor T6 is turned off under the high level control of the first reset signal re1, the seventh transistor T7 is turned on under the low level control of the second reset signal re2, the eighth transistor T8 is turned on under the low level control of the third reset signal re3, and the ninth transistor T9 is turned on under the low level control of the second light emitting control signal em2. The turned-on second transistor T2 controls the gate of the driving transistor T0 and the second electrode of the driving transistor T0 to be turned on; the turned-on third transistor T3 provides the signal of the reference voltage signal end Vref to the second node N2; then, the voltage values of the gate and the second electrode of the driving transistor T0 are both vdd+vth; the turned-on seventh transistor T7 provides the signal of the second initialization signal end Vinit2 to the light emitting device L; the turned-on eighth transistor T8 provides the signal of the third initialization signal end Vinit3 to the first electrode of the driving transistor T0; and the turned-on ninth transistor T9 provides the signal of the first power supply end VDD to the first electrode of the driving transistor T0.

[0170] In the data writing stage F3, the first transistor T1 is turned off under the low level control of the first control signal cs1, the second transistor T2 is turned on under the high level control of the second control signal cs2, the third transistor T3 is turned on under the high level control of the third control signal cs3, the fourth transistor T4 is turned on under the low level control of the scanning signal ss1, the fifth transistor T5 is turned off under the high level control of the first light emitting control signal em1, the sixth transistor T6 is turned off under the high level control of the first reset signal re1, the seventh transistor T7 is turned off under the high level control of the second reset signal re2, the eighth transistor T8 is turned off under the high level control of the third reset signal re3, and the ninth transistor T9 is turned on under the low level control of the second light emitting control signal em2. The turned-on second transistor T2 controls the gate of the driving transistor T0 and the second electrode of the driving transistor T0 to be turned on; the turned-on third transistor T3 provides the signal of the reference voltage signal end Vref to the second node N2; the turned-on fourth transistor T4 provides the data voltage signal of the data signal end DA to the first node N1; the first capacitor C1 couples the signal of the first node N1 to the second node N2, and the second capacitor C2 couples the signal of the second node N2 to the gate of the driving transistor T0; the turned-on ninth transistor T9 provides the signal of the first power supply end VDD to the first electrode of the driving transistor T0.

[0171] In the reset stage F5, the first transistor T1 is turned off under the low level control of the first control signal cs1, the second transistor T2 is turned off under the low level control of the second control signal cs2, the third transistor T3 is turned off under the low level control of the third control signal cs3, the fourth transistor T4 is turned off under the high level control of the scanning signal ss1, the fifth transistor T5 is turned off under the high level control of the first light emitting control signal em1, the sixth transistor T6 is turned off under the high level control of the first reset signal re1, the seventh transistor T7 is turned on under the low level control of the second reset signal re2, the eighth transistor T8 is turned on under the low level control of the third reset signal re3, and the ninth transistor T9 is turned off under the low level control of the second light emitting control signal em2. The turned-on seventh transistor T7 provides the signal of the second initialization signal terminal Vinit2 to the light emitting device L, and the turned-on eighth transistor T8 provides the signal of the third initialization signal terminal Vinit3 to the first electrode of the driving transistor T0.

[0172] In the light emitting stage F4, the first transistor T1 is turned off under the low level control of the first control signal cs1, the second transistor T2 is turned off under the low level control of the second control signal cs2, the third transistor T3 is turned off under the low level control of the third control signal cs3, the fourth transistor T4 is turned off under the high level control of the scanning signal ss1, the fifth transistor T5 is turned on under the low level control of the first light emitting control signal em1, the sixth transistor T6 is turned on under the low level control of the first reset signal re1, the seventh transistor T7 is turned off under the high level control of the second reset signal re2, the eighth transistor T8 is turned off under the high level control of the third reset signal re3, and the ninth transistor T9 is turned on under the low level control of the second light emitting control signal em2. The turned-on sixth transistor T6 provides the signal of the first initialization signal terminal Vinit1 to the first node N1, the turned-on ninth transistor T9 provides the signal of the first power supply terminal VDD to the first electrode of the driving transistor T0, the turned-on fifth transistor T5 turns on the second electrode of the driving transistor T0 and the light emitting device L, and the driving transistor T0 generates a driving current which charges the anode of the light emitting device L until the light emitting device L stably emits light.

[0173] The above is only an example to illustrate the specific structure of each circuit in the pixel circuit provided by the embodiment of the present application, and the specific structure of the above-mentioned circuit is not limited to the above-mentioned structure provided by the embodiment of the present application, but can also be other structures known by those skilled in the art, which are all within the protection scope of the present application and are not limited here.

[0174] Based on the same disclosure concept, the display device provided by the embodiments of the present disclosure also includes the display panel provided by the embodiments of the present disclosure. The display device solves the problem in the same principle as the display panel, and therefore the implementation of the display device can refer to the implementation of the display panel, and the repeated parts will not be described here.

[0175] In the implementation, the display device can be any product or component with display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like. Other essential components of the display device are well understood by those skilled in the art, and will not be described here, and should not be considered as a limitation on the present disclosure.

[0176] Although the preferred embodiments of the present disclosure have been described, those skilled in the art can make further changes and modifications to the embodiments once they know the basic inventive concept. Therefore, the appended claims are intended to be interpreted as including all the preferred embodiments and all the changes and modifications falling within the scope of the present disclosure.

[0177] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if these modifications and variations of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent technologies, the present disclosure also intends to include these modifications and variations.

Claims

1. A pixel circuit, wherein, The application relates to a light emitting device, a driving transistor, a first control circuit, a first node, a setting pole of the driving transistor, a first control signal terminal, a data signal terminal, a scanning signal terminal, a second control circuit, a second control signal terminal, a gate of the driving transistor, a second pole of the driving transistor, a first light emitting control circuit, a second node, a reference voltage signal terminal, and a third control circuit. The application relates to a light emitting device, a driving transistor, a first control circuit, a first node, a setting pole of the driving transistor, a first control signal terminal, a data signal terminal, a scanning signal terminal, a second control circuit, a second control signal terminal, a gate of the driving transistor, a second pole of the driving transistor, a first light emitting control circuit, a second node, a reference voltage signal terminal, and a third control circuit. The application relates to a light emitting device, a driving transistor, a first control circuit, a first node, a setting pole of the driving transistor, a first control signal terminal, a data signal terminal, a scanning signal terminal, a second control circuit, a second control signal terminal, a gate of the driving transistor, a second pole of the driving transistor, a first light emitting control circuit, a second node, a reference voltage signal terminal, and a third control circuit. The application relates to a light emitting device, a driving transistor, a first control circuit, a first node, a setting pole of the driving transistor, a first control signal terminal, a data signal terminal, a scanning signal terminal, a second control circuit, a second control signal terminal, a gate of the driving transistor, a second pole of the driving transistor, a first light emitting control circuit, a second node, a reference voltage signal terminal, and a third control circuit. The application relates to a light emitting device, a driving transistor, a first control circuit, a first node, a setting pole of the driving transistor, a first control signal terminal, a data signal terminal, a scanning signal terminal, a second control circuit, a second control signal terminal, a gate of the driving transistor, a second pole of the driving transistor, a first light emitting control circuit, a second node, a reference voltage signal terminal, and a third control circuit. The application relates to a light emitting device, a driving transistor, a first control circuit, a first node, a setting pole of the driving transistor, a first control signal terminal, a data signal terminal, a scanning signal terminal, a second control circuit, a second control signal terminal, a gate of the driving transistor, a second pole of the driving transistor, a first light emitting control circuit, a second node, a reference voltage signal terminal, and a third control circuit. The application relates to a light emitting device, a driving transistor, a first control circuit, a first node, a setting pole of the driving transistor, a first control signal terminal, a data signal terminal, a scanning signal terminal, a second control circuit, a second control signal terminal, a gate of the driving transistor, a second pole of the driving transistor, a first light emitting control circuit, a second node, a reference voltage signal terminal, and a third control circuit. The application relates to a light emitting device, a driving transistor, a first control circuit, a first node, a setting pole of the driving transistor, a first control signal terminal, a data signal terminal, a scanning signal terminal, a second control circuit, a second control signal terminal, a gate of the driving transistor, a second pole of the driving transistor, a first light emitting control circuit, a second node, a reference voltage signal terminal, and a third control circuit. The application relates to a light emitting device, a driving transistor, a first control circuit, a first node, a setting pole of the driving transistor, a first control signal terminal, a data signal terminal, a scanning signal terminal, a second control circuit, a second control signal terminal, a gate of the driving transistor, a second pole of the driving transistor, a first light emitting control circuit, a second node, a reference voltage signal terminal, and a third control circuit.

2. The pixel circuit of claim 1, wherein, The application relates to a light emitting device, a driving transistor, a first control circuit, a first node, a setting pole of the driving transistor, a first control signal terminal, a data signal terminal, a scanning signal terminal, a second control circuit, a second control signal terminal, a gate of the driving transistor, a second pole of the driving transistor, a first light emitting control circuit, a second node, a reference voltage signal terminal, and a third control circuit. The application relates to a light emitting device, a driving transistor, a first control circuit, a first node, a setting pole of the driving transistor, a first control signal terminal, a data signal terminal, a scanning signal terminal, a second control circuit, a second control signal terminal, a gate of the driving transistor, a second pole of the driving transistor, a first light emitting control circuit, a second node, a reference voltage signal terminal, and a third control circuit.

3. The pixel circuit of claim 2, wherein, The application relates to a light emitting device, a driving transistor, a first control circuit, a first node, a setting pole of the driving transistor, a first control signal terminal, a data signal terminal, a scanning signal terminal, a second control circuit, a second control signal terminal, a gate of the driving transistor, a second pole of the driving transistor, a first light emitting control circuit, a second node, a reference voltage signal terminal, and a third control circuit.

4. The pixel circuit of claim 1, wherein, The application relates to a light emitting device, a driving transistor, a first control circuit, a first node, a setting pole of the driving transistor, a first control signal terminal, a data signal terminal, a scanning signal terminal, a second control circuit, a second control signal terminal, a gate of the driving transistor, a second pole of the driving transistor, a first light emitting control circuit, a second node, a reference voltage signal terminal, and a third control circuit. The application relates to a light emitting device, a driving transistor, a first control circuit, a first node, a setting pole of the driving transistor, a first control signal terminal, a data signal terminal, a scanning signal terminal, a second control circuit, a second control signal terminal, a gate of the driving transistor, a second pole of the driving transistor, a first light emitting control circuit, a second node, a reference voltage signal terminal, and a third control circuit.

5. The pixel circuit of claim 4, wherein, The application relates to a light emitting device, a driving transistor, a first control circuit, a first node, a setting pole of the driving transistor, a first control signal terminal, a data signal terminal, a scanning signal terminal, a second control circuit, a second control signal terminal, a gate of the driving transistor, a second pole of the driving transistor, a first light emitting control circuit, a second node, a reference voltage signal terminal, and a third control circuit.

6. The pixel circuit of any one of claims 1-5, wherein, The application relates to a light emitting device, a driving transistor, a first control circuit, a first node, a setting pole of the driving transistor, a first control signal terminal, a data signal terminal, a scanning signal terminal, a second control circuit, a second control signal terminal, a gate of the driving transistor, a second pole of the driving transistor, a first light emitting control circuit, a second node, a reference voltage signal terminal, and a third control circuit. The application relates to a light emitting device, a driving transistor, a first control circuit, a first node, a setting pole of the driving transistor, a first control signal terminal, a data signal terminal, a scanning signal terminal, a second control circuit, a second control signal terminal, a gate of the driving transistor, a second pole of the driving transistor, a first light emitting control circuit, a second node, a reference voltage signal terminal, and a third control circuit. The application relates to a light emitting device, a driving transistor, a first control circuit, a first node, a setting pole of the driving transistor, a first control signal terminal, a data signal terminal, a scanning signal terminal, a second control circuit, a second control signal terminal, a gate of the driving transistor, a second pole of the driving transistor, a first light emitting control circuit, a second node, a reference voltage signal terminal, and a third control circuit.

7. The pixel circuit of claim 6, wherein, The application relates to a light emitting device, a driving transistor, a first control circuit, a first node, a setting pole of the driving transistor, a first control signal terminal, a data signal terminal, a scanning signal terminal, a second control circuit, a second control signal terminal, a gate of the driving transistor, a second pole of the driving transistor, a first light emitting control circuit, a second node, a reference voltage signal terminal, and a third control circuit. The application relates to a light emitting device, a driving transistor, a first control circuit, a first node, a setting pole of the driving transistor, a first control signal terminal, a data signal terminal, a scanning signal terminal, a second control circuit, a second control signal terminal, a gate of the driving transistor, a second pole of the driving transistor, a first light emitting control circuit, a second node, a reference voltage signal terminal, and a third control circuit.

8. The pixel circuit of claim 6, wherein, The application relates to a light emitting device, a driving transistor, a first control circuit, a first node, a setting pole of the driving transistor, a first control signal terminal, a data signal terminal, a scanning signal terminal, a second control circuit, a second control signal terminal, a gate of the driving transistor, a second pole of the driving transistor, a first light emitting control circuit, a second node, a reference voltage signal terminal, and a third control circuit. The application relates to a light emitting device, a driving transistor, a first control circuit, a first node, a setting pole of the driving transistor, a first control signal terminal, a data signal terminal, a scanning signal terminal, a second control circuit, a second 9. The pixel circuit of any of claims 6-8, wherein, ​ ​ ​ 10. The pixel circuit of claim 9, wherein, ​ A gate of the third transistor is coupled with the third control signal terminal, a first electrode of the third transistor is coupled with the second node, and a second electrode of the third transistor is coupled with the reference voltage signal terminal.

11. The pixel circuit of claim 10, wherein, A material of an active layer of the third transistor is metal oxide semiconductor material.

12. The pixel circuit of any of claims 1-11, wherein, The data writing circuit comprises a fourth transistor. A gate of the fourth transistor is coupled with the scan signal terminal, a first electrode of the fourth transistor is coupled with the data signal terminal, and a second electrode of the fourth transistor is coupled with the first node.

13. The pixel circuit of claim 1, wherein, The first light emitting control circuit comprises a fifth transistor. A gate of the fifth transistor is coupled with the first light emitting control signal terminal, a first electrode of the fifth transistor is coupled with the second electrode of the driving transistor, and a second electrode of the fifth transistor is coupled with the light emitting device.

14. The pixel circuit of any one of claims 1-13, wherein, Further comprising a first initialization circuit coupled with the first node and configured to provide a signal of a first initialization signal terminal to the first node in response to a signal of a first reset signal terminal.

15. The pixel circuit of claim 14, wherein, The first initialization circuit comprises a sixth transistor. A gate of the sixth transistor is coupled with the first reset signal terminal, a first electrode of the sixth transistor is coupled with the first node, and a second electrode of the sixth transistor is coupled with the first initialization signal terminal.

16. The pixel circuit of any one of claims 1-15, wherein, Further comprising a second initialization circuit coupled with the light emitting device and configured to provide a signal of a second initialization signal terminal to the light emitting device in response to a signal of a second reset signal terminal.

17. The pixel circuit of claim 16, wherein, The second initialization circuit comprises a seventh transistor. A gate of the seventh transistor is coupled with the second reset signal terminal, a first electrode of the seventh transistor is coupled with the light emitting device, and a second electrode of the seventh transistor is coupled with the second initialization signal terminal.

18. The pixel circuit of any of claims 1-17, wherein, Further comprising a third initialization circuit coupled with the first electrode of the driving transistor and configured to provide a signal of a third initialization signal terminal to the first electrode of the driving transistor in response to a signal of a third reset signal terminal.

19. The pixel circuit of claim 18, wherein, The third initialization circuit comprises an eighth transistor. A gate of the eighth transistor is coupled with the third reset signal terminal, a first electrode of the eighth transistor is coupled with the first electrode of the driving transistor, and a second electrode of the eighth transistor is coupled with the third initialization signal terminal.

20. The pixel circuit of any of claims 1-19, wherein, Further comprising: A second light emitting control circuit coupled with the first electrode of the driving transistor and configured to provide a signal of a first power supply terminal to the first electrode of the driving transistor in response to a signal of a second light emitting control signal terminal.

21. The pixel circuit of claim 20, wherein, The second light emitting control circuit comprises a ninth transistor. A gate of the ninth transistor is coupled with the second light emitting control signal terminal, a first electrode of the ninth transistor is coupled with the first power supply terminal, and a second electrode of the ninth transistor is coupled with the first electrode of the driving transistor.

22. A display device comprising: The pixel circuit comprises any one of claims 1-21.

23. A driving method of a pixel circuit according to any one of claims 1 to 21, wherein The pixel circuit comprises: An initialization stage, a threshold voltage compensation stage, a data writing stage, and a light emitting stage. In the initialization stage, the first control circuit controls the first node and the set pole of the driving transistor to be conductive in response to a signal of the first control signal terminal; the second control circuit controls the gate of the driving transistor and the second pole of the driving transistor to be conductive in response to a signal of the second control signal terminal; and the first light emitting control circuit controls the second pole of the driving transistor and the light emitting device to be conductive in response to a signal of the first light emitting control signal terminal. In the threshold voltage compensation stage, the second control circuit controls the gate of the driving transistor and the second pole of the driving transistor to be conductive in response to a signal of the second control signal terminal. In the data writing stage, the data writing circuit provides the data voltage signal of the data signal terminal to the first node in response to a signal of the scanning signal terminal. The second control circuit controls the gate of the driving transistor and the second pole of the driving transistor to be conductive in response to a signal of the second control signal terminal. The coupling control circuit couples the signal of the first node to the gate of the driving transistor. In the light emitting stage, the first light emitting control circuit controls the second pole of the driving transistor and the light emitting device to be conductive in response to a signal of the first light emitting control signal terminal.

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