Shift register and driving method therefor, gate driver circuit, and display device

Abstract

A shift register and a driving method therefor, a gate driver circuit, and a display device. The shift register may comprise a control sub-circuit and an output sub-circuit. The control sub-circuit is electrically connected to a signal input terminal, a first clock signal terminal, a first node, and a second node, and is configured to provide a signal to the first node or the second node under control of signals at the signal input terminal and the first clock signal terminal. The output sub-circuit is electrically connected to the first node, the second node, at least one power signal terminal, and at least one output signal terminal, and is configured to provide a signal to the at least one output signal terminal under control of signals at the first node, the second node, and the at least one power signal terminal. The duration of an effective level signal provided by the output sub-circuit is greater than the cycle duration of a signal provided by the first clock signal terminal.

Description

Shift register and driving method thereof, gate driving circuit and display device TECHNICAL FIELD

[0001] The present disclosure relates to, but is not limited to, display technology, in particular to a shift register and driving method thereof, a gate driving circuit and a display device. BACKGROUND

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diodes (QLED) are active light-emitting display devices, which have the advantages of self-luminous, wide viewing angle, high contrast, low power consumption, extremely high response speed, light and thin, bendable and low cost. With the continuous development of display technology, flexible display devices using OLED or QLED as light-emitting devices and controlled by Thin Film Transistor (TFT) have become the mainstream products in the current display field.

[0003] SUMMARY

[0004] The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of protection of the claims.

[0005] In a first aspect, an embodiment of the present disclosure provides a shift register, comprising: a control sub-circuit and an output sub-circuit;

[0006] The control sub-circuit is electrically connected with a signal input end, a first clock signal end, a first node and a second node respectively, and is configured to provide a signal to the first node or the second node under the control of signals at the signal input end and the first clock signal end;

[0007] The output sub-circuit is electrically connected with the first node, the second node, at least one power signal end and at least one output signal end respectively, and is configured to provide a signal to the at least one output signal end under the control of signals at the first node, the second node and the at least one power signal end;

[0008] The duration of the effective level signal provided by the output sub-circuit is greater than the cycle duration of the signal provided by the first clock signal end.

[0009] In some possible implementation manners, the control sub-circuit comprises a first control sub-circuit, and the first control sub-circuit is further electrically connected with a first power end and a second power end;

[0010] Alternatively,

[0011] The control sub-circuit comprises a second control sub-circuit, and the second control sub-circuit is further electrically connected with the first power supply end, the second power supply end and the third power supply end.

[0012] Or,

[0013] The control sub-circuit comprises a third control sub-circuit, and the third control sub-circuit is further electrically connected with the first power supply end.

[0014] In some possible implementation manners, the first control sub-circuit comprises a third transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor and a third capacitor.

[0015] The control electrode of the third transistor is electrically connected with the first clock signal end, the first electrode of the third transistor is electrically connected with the signal input end, and the second electrode of the third transistor is electrically connected with the second node.

[0016] The control electrode of the fifth transistor is electrically connected with the third node, the first electrode of the fifth transistor is electrically connected with the second power supply end, and the second electrode of the fifth transistor is electrically connected with the fourth node.

[0017] The control electrode of the sixth transistor is electrically connected with the signal input end, the first electrode of the sixth transistor is electrically connected with the fourth node, and the second electrode of the sixth transistor is electrically connected with the first power supply end.

[0018] The control electrode of the seventh transistor is electrically connected with the signal input end, the first electrode of the seventh transistor is electrically connected with the third node, and the second electrode of the seventh transistor is electrically connected with the first power supply end.

[0019] The control electrode of the eighth transistor is electrically connected with the first clock signal end, the first electrode of the eighth transistor is electrically connected with the fourth node, and the second electrode of the eighth transistor is electrically connected with the first node.

[0020] The third capacitor comprises a first plate and a second plate, the first plate of the third capacitor is electrically connected with the first clock signal end, and the second plate of the third capacitor is electrically connected with the third node.

[0021] In some possible implementation manners, the first control sub-circuit comprises a third transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor and a ninth transistor.

[0022] The control electrode of the third transistor is electrically connected with the first clock signal end, the first electrode of the third transistor is electrically connected with the signal input end, and the second electrode of the third transistor is electrically connected with the second node.

[0023] The control electrode of the fifth transistor is electrically connected with the fifth node, the first electrode of the fifth transistor is electrically connected with the second power supply end, and the second electrode of the fifth transistor is electrically connected with the fourth node.

[0024] The control electrode of the sixth transistor is electrically connected with the signal input end, the first electrode of the sixth transistor is electrically connected with the fourth node, and the second electrode of the sixth transistor is electrically connected with the first power supply end;

[0025] The control electrode of the seventh transistor is electrically connected with the signal input end, the first electrode of the seventh transistor is electrically connected with the sixth node, and the second electrode of the seventh transistor is electrically connected with the first power supply end;

[0026] The control electrode of the eighth transistor is electrically connected with the first clock signal end, the first electrode of the eighth transistor is electrically connected with the fourth node, and the second electrode of the eighth transistor is electrically connected with the first node;

[0027] The control electrode of the ninth transistor is electrically connected with the first clock signal end, the first electrode of the ninth transistor is electrically connected with the fifth node, and the second electrode of the ninth transistor is electrically connected with the sixth node.

[0028] In some possible implementation manners, the third control sub-circuit comprises a third transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor and a third capacitor;

[0029] The control electrode of the third transistor is electrically connected with the first clock signal end, the first electrode of the third transistor is electrically connected with the signal input end, and the second electrode of the third transistor is electrically connected with the second node;

[0030] The control electrode of the fifth transistor is electrically connected with the third node, the first electrode of the fifth transistor is electrically connected with the first clock signal end, and the second electrode of the fifth transistor is electrically connected with the fourth node;

[0031] The control electrode of the sixth transistor is electrically connected with the signal input end, the first electrode of the sixth transistor is electrically connected with the fourth node, and the second electrode of the sixth transistor is electrically connected with the first power supply end;

[0032] The control electrode of the seventh transistor is electrically connected with the signal input end, the first electrode of the seventh transistor is electrically connected with the third node, and the second electrode of the seventh transistor is electrically connected with the first power supply end;

[0033] The control electrode of the eighth transistor is electrically connected with the first clock signal end, the first electrode of the eighth transistor is electrically connected with the fourth node, and the second electrode of the eighth transistor is electrically connected with the first node;

[0034] The third capacitor comprises a first plate and a second plate, the first plate of the third capacitor is electrically connected with the first clock signal end, and the second plate of the third capacitor is electrically connected with the third node.

[0035] In some possible implementation manners, the third control sub-circuit comprises a third transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor and a ninth transistor;

[0036] The control electrode of the third transistor is electrically connected with the first clock signal end, the first electrode of the third transistor is electrically connected with the signal input end, and the second electrode of the third transistor is electrically connected with the second node;

[0037] The control electrode of the fifth transistor is electrically connected with the fifth node, the first electrode of the fifth transistor is electrically connected with the first clock signal end, and the second electrode of the fifth transistor is electrically connected with the fourth node;

[0038] The control electrode of the sixth transistor is electrically connected with the signal input end, the first electrode of the sixth transistor is electrically connected with the fourth node, and the second electrode of the sixth transistor is electrically connected with the first power supply end;

[0039] The control electrode of the seventh transistor is electrically connected with the signal input end, the first electrode of the seventh transistor is electrically connected with the sixth node, and the second electrode of the seventh transistor is electrically connected with the first power supply end;

[0040] The control electrode of the eighth transistor is electrically connected with the first clock signal end, the first electrode of the eighth transistor is electrically connected with the fourth node, and the second electrode of the eighth transistor is electrically connected with the first node;

[0041] The control electrode of the ninth transistor is electrically connected with the first clock signal end, the first electrode of the ninth transistor is electrically connected with the fifth node, and the second electrode of the ninth transistor is electrically connected with the sixth node.

[0042] In some possible implementation manners, the first control sub-circuit comprises a third transistor, a fifth transistor, a sixth transistor, a seventh transistor and a third capacitor;

[0043] The control electrode of the third transistor is electrically connected with the first clock signal end, the first electrode of the third transistor is electrically connected with the signal input end, and the second electrode of the third transistor is electrically connected with the second node;

[0044] The control electrode of the fifth transistor is electrically connected with the third node, the first electrode of the fifth transistor is electrically connected with the second power supply end, and the second electrode of the fifth transistor is electrically connected with the first node;

[0045] The control electrode of the sixth transistor is electrically connected with the second node, the first electrode of the sixth transistor is electrically connected with the first node, and the second electrode of the sixth transistor is electrically connected with the first power supply end;

[0046] The control electrode of the seventh transistor is electrically connected with the signal input end, the first electrode of the seventh transistor is electrically connected with the third node, and the second electrode of the seventh transistor is electrically connected with the first power supply end;

[0047] The third capacitor comprises a first plate and a second plate, the first plate of the third capacitor is electrically connected with the first clock signal end, and the second plate of the third capacitor is electrically connected with the third node.

[0048] In some possible implementation manners, the fifth transistor is a P-type transistor.

[0049] In some possible implementation manners, the first control sub-circuit includes a third transistor, a fifth transistor, a sixth transistor and an eighth transistor.

[0050] The control electrode of the third transistor is electrically connected with the first clock signal terminal, the first electrode of the third transistor is electrically connected with the signal input terminal, and the second electrode of the third transistor is electrically connected with the second node.

[0051] The control electrode of the fifth transistor is electrically connected with the signal input terminal, the first electrode of the fifth transistor is electrically connected with the second power supply terminal, and the second electrode of the fifth transistor is electrically connected with the fourth node.

[0052] The control electrode of the sixth transistor is electrically connected with the signal input terminal, the first electrode of the sixth transistor is electrically connected with the fourth node, and the second electrode of the sixth transistor is electrically connected with the first power supply terminal.

[0053] The control electrode of the eighth transistor is electrically connected with the first clock signal terminal, the first electrode of the eighth transistor is electrically connected with the fourth node, and the second electrode of the eighth transistor is electrically connected with the first node.

[0054] In some possible implementation manners, the third control sub-circuit includes a third transistor, a fifth transistor, a sixth transistor and an eighth transistor, the fifth transistor is a double-gate transistor and includes a first control electrode and a second control electrode.

[0055] The control electrode of the third transistor is electrically connected with the first clock signal terminal, the first electrode of the third transistor is electrically connected with the signal input terminal, and the second electrode of the third transistor is electrically connected with the second node.

[0056] The first control electrode of the fifth transistor is electrically connected with the signal input terminal, the second control electrode of the fifth transistor is electrically connected with the third power supply terminal, the first electrode of the fifth transistor is electrically connected with the second power supply terminal, and the second electrode of the fifth transistor is electrically connected with the fourth node.

[0057] The control electrode of the sixth transistor is electrically connected with the signal input terminal, the first electrode of the sixth transistor is electrically connected with the fourth node, and the second electrode of the sixth transistor is electrically connected with the first power supply terminal.

[0058] The control electrode of the eighth transistor is electrically connected with the first clock signal terminal, the first electrode of the eighth transistor is electrically connected with the fourth node, and the second electrode of the eighth transistor is electrically connected with the first node.

[0059] In some possible implementation manners, the signals of the second power supply terminal and the third power supply terminal are low-level signals, and the voltage value of the third power supply terminal is less than or equal to the voltage value of the second power supply terminal.

[0060] In some possible implementation manners, the fifth transistor is an N-type transistor.

[0061] In some possible implementation manners, the control sub-circuit is further electrically connected with the second clock signal terminal and the first power supply terminal, and is configured to provide a signal of the first power supply terminal to the second node under control of signals of the first node and the second clock signal terminal.

[0062] In some possible implementation manners, the control sub-circuit further includes a tenth transistor and an eleventh transistor.

[0063] The control electrode of the tenth transistor is electrically connected with the first node, the first electrode of the tenth transistor is electrically connected with the first power supply terminal, and the second electrode of the tenth transistor is electrically connected with the seventh node; the control electrode of the eleventh transistor is electrically connected with the second clock signal terminal, the first electrode of the eleventh transistor is electrically connected with the seventh node, and the second electrode of the eleventh transistor is electrically connected with the second node.

[0064] Or,

[0065] The control electrode of the tenth transistor is electrically connected with the second clock signal terminal, the first electrode of the tenth transistor is electrically connected with the first node, and the second electrode of the tenth transistor is electrically connected with the seventh node; the control electrode of the eleventh transistor is electrically connected with the second node, the first electrode of the eleventh transistor is electrically connected with the seventh node, and the second electrode of the eleventh transistor is electrically connected with the first power supply terminal.

[0066] In some possible implementation manners, the at least one power supply signal terminal includes a fourth power supply terminal and a fifth power supply terminal, and the at least one output signal terminal includes a signal output terminal.

[0067] The output sub-circuit is configured to provide a signal of the fourth power supply terminal or the fifth power supply terminal to the signal output terminal under control of signals of the first node and the second node.

[0068] In some possible implementation manners, the output sub-circuit includes a first transistor, a second transistor, a fourth transistor, a first capacitor and a second capacitor.

[0069] The control electrode of the first transistor is electrically connected with the first node, the first electrode of the first transistor is electrically connected with the fourth power supply terminal, and the second electrode of the first transistor is electrically connected with the signal output terminal.

[0070] The control electrode of the second transistor is electrically connected with the eighth node, the first electrode of the second transistor is electrically connected with the signal output terminal, and the second electrode of the second transistor is electrically connected with the fifth power supply terminal.

[0071] The control electrode of the fourth transistor is electrically connected with the fifth power supply terminal, the first electrode of the fourth transistor is electrically connected with the second node, and the second electrode of the fourth transistor is electrically connected with the eighth node.

[0072] The first capacitor comprises a first plate and a second plate, the first plate of the first capacitor is electrically connected with the eighth node, and the second plate of the first capacitor is electrically connected with the signal output end;

[0073] The second capacitor comprises a first plate and a second plate, the first plate of the second capacitor is electrically connected with the first node, and the second plate of the second capacitor is electrically connected with the fourth power supply end.

[0074] In some possible implementation manners, the at least one power supply signal end comprises a fourth power supply end, a fifth power supply end, a sixth power supply end and an eighth power supply end, and the at least one output signal end comprises a signal output end and a cascade output end;

[0075] The output sub-circuit is configured to provide, under the control of signals of the first node and the second node, a signal of the sixth power supply end or the eighth power supply end to the signal output end and a signal of the fourth power supply end or the fifth power supply end to the cascade output end.

[0076] In some possible implementation manners, the output sub-circuit comprises a first transistor, a second transistor, a fourth transistor, a twelfth transistor, a thirteenth transistor, a first capacitor and a second capacitor;

[0077] The control electrode of the first transistor is electrically connected with the first node, the first electrode of the first transistor is electrically connected with the fourth power supply end, and the second electrode of the first transistor is electrically connected with the cascade output end;

[0078] The control electrode of the second transistor is electrically connected with the eighth node, the first electrode of the second transistor is electrically connected with the cascade output end, and the second electrode of the second transistor is electrically connected with the fifth power supply end;

[0079] The control electrode of the fourth transistor is electrically connected with the fifth power supply end, the first electrode of the fourth transistor is electrically connected with the second node, and the second electrode of the fourth transistor is electrically connected with the eighth node;

[0080] The control electrode of the twelfth transistor is electrically connected with the first node, the first electrode of the twelfth transistor is electrically connected with the sixth power supply end, and the second electrode of the twelfth transistor is electrically connected with the signal output end;

[0081] The control electrode of the thirteenth transistor is electrically connected with the eighth node, the first electrode of the thirteenth transistor is electrically connected with the signal output end, and the second electrode of the thirteenth transistor is electrically connected with the eighth power supply end;

[0082] The first capacitor comprises a first plate and a second plate, the first plate of the first capacitor is electrically connected with the eighth node, and the second plate of the first capacitor is electrically connected with the cascade output end;

[0083] The second capacitor comprises a first plate and a second plate, the first plate of the second capacitor is electrically connected with the first node, and the second plate of the second capacitor is electrically connected with the fourth power supply end.

[0084] In some possible implementation manners, the output sub-circuit comprises a first transistor, a second transistor, a fourth transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a first capacitor, a second capacitor and a fourth capacitor.

[0085] The control electrode of the first transistor is electrically connected with the first node, the first electrode of the first transistor is electrically connected with the fourth power supply end, and the second electrode of the first transistor is electrically connected with the cascade output end.

[0086] The control electrode of the second transistor is electrically connected with the eighth node, the first electrode of the second transistor is electrically connected with the cascade output end, and the second electrode of the second transistor is electrically connected with the fifth power supply end.

[0087] The control electrode of the fourth transistor is electrically connected with the fifth power supply end, the first electrode of the fourth transistor is electrically connected with the second node, and the second electrode of the fourth transistor is electrically connected with the eighth node.

[0088] The control electrode of the twelfth transistor is electrically connected with the ninth node, the first electrode of the twelfth transistor is electrically connected with the sixth power supply end, and the second electrode of the twelfth transistor is electrically connected with the signal output end.

[0089] The control electrode of the thirteenth transistor is electrically connected with the second node, the first electrode of the thirteenth transistor is electrically connected with the signal output end, and the second electrode of the thirteenth transistor is electrically connected with the eighth power supply end.

[0090] The control electrode of the fourteenth transistor is electrically connected with the fifth power supply end, the first electrode of the fourteenth transistor is electrically connected with the first node, and the second electrode of the fourteenth transistor is electrically connected with the ninth node.

[0091] The first capacitor comprises a first plate and a second plate, the first plate of the first capacitor is electrically connected with the eighth node, and the second plate of the first capacitor is electrically connected with the cascade output end.

[0092] The second capacitor comprises a first plate and a second plate, the first plate of the second capacitor is electrically connected with the first node, and the second plate of the second capacitor is electrically connected with the fourth power supply end.

[0093] The fourth capacitor comprises a first plate and a second plate, the first plate of the fourth capacitor is electrically connected with the ninth node, and the second plate of the fourth capacitor is electrically connected with the signal output end.

[0094] In some possible implementation manners, the shift register further comprises a reset sub-circuit.

[0095] The reset sub-circuit is electrically connected with the reset signal end, the first node and the seventh power supply end respectively, and is configured to provide a signal of the seventh power supply end to the first node under control of a signal of the reset signal end.

[0096] In some possible implementation manners, the reset sub-circuit includes a fifteenth transistor.

[0097] The control electrode of the fifteenth transistor is electrically connected with the reset signal end, the first electrode of the fifteenth transistor is electrically connected with the seventh power supply end, and the second electrode of the fifteenth transistor is electrically connected with the first node.

[0098] In a second aspect, the embodiments of the present disclosure provide a gate drive circuit, including: a plurality of cascaded shift registers as described in any of the embodiments of the first aspect, at least one output signal end of at least one stage of shift registers includes: a signal output end;

[0099] The signal output end of the i-th stage of shift registers is electrically connected with the signal input end of the i+L-th stage of shift registers, 1≤i≤M-L, M is the total number of stages of the shift registers, M≥1, and L is a positive integer greater than or equal to 1.

[0100] In a third aspect, the embodiments of the present disclosure provide a display device, including a display area and a non-display area, the display area is provided with pixel drive circuits arranged in an array, and the non-display area is provided with a gate drive circuit as described in any of the embodiments of the second aspect, the pixel drive circuit includes at least one light-emitting control transistor.

[0101] At least one light-emitting control transistor in the pixel drive circuit of at least one row is electrically connected with at least one stage of shift registers in the gate drive circuit.

[0102] In some possible implementation manners, the control sub-circuit is electrically connected with the signal input end and the first clock signal end respectively, and the display device further includes: an initial signal line, a first clock signal line and a second clock signal line.

[0103] The signal input end of at least one stage of shift registers is electrically connected with the initial signal line, the first clock signal end is electrically connected with one of the first clock signal line and the second clock signal line, and the signal lines connected with the first clock signal ends of adjacent shift registers are different.

[0104] In some possible implementation manners, the control sub-circuit is electrically connected with the signal input end and the first clock signal end respectively, and the display device further includes: an initial signal line, a first clock signal line, a second clock signal line, a third clock signal line and a fourth clock signal line.

[0105] The signal input end of at least one stage of shift registers is electrically connected with the initial signal line.

[0106] The first clock signal end of the 4M-3 stage shift register is electrically connected with the first clock signal line.

[0107] The first clock signal end of the 4M-2 stage shift register is electrically connected with the second clock signal line.

[0108] The first clock signal end of the 4M-1 stage shift register is electrically connected with the third clock signal line.

[0109] The first clock signal end of the 4M stage shift register is electrically connected with the fourth clock signal line.

[0110] Wherein, M is the total number of stages of the shift register, and M≥1.

[0111] In a fourth aspect, the embodiments of the present disclosure provide a driving method of a shift register, configured to drive the shift register of any of the embodiments of the first aspect, and the method comprises:

[0112] The control sub-circuit provides a signal to the first node or the second node under the control of the signals at the signal input end and the first clock signal end;

[0113] The output sub-circuit provides a signal to the at least one output signal end under the control of the signals at the first node, the second node and the at least one power signal end;

[0114] The duration of the valid level signal provided by the output sub-circuit is greater than the cycle duration of the signal provided by the first clock signal end.

[0115] Other aspects can become apparent from a review of the drawings and detailed description.

[0116] SUMMARY

[0117] The accompanying drawings are included to provide a further understanding of the technical solutions of the present disclosure, and constitute a part of the specification, and are used together with the embodiments of the present disclosure to explain the technical solutions of the present disclosure, and do not constitute a limitation on the technical solutions of the present disclosure.

[0118] FIG. 1 is a structural schematic diagram of a shift register provided by an example embodiment of the present disclosure;

[0119] FIG. 2 is an equivalent circuit diagram of a control sub-circuit provided by an example embodiment;

[0120] FIG. 3 is an equivalent circuit diagram of a control sub-circuit provided by an example embodiment;

[0121] FIG. 4 is an equivalent circuit diagram of a control sub-circuit provided by an example embodiment;

[0122] FIG. 5 is an equivalent circuit diagram of a control sub-circuit provided by an example embodiment;

[0123] Figure 6 is an equivalent circuit diagram of a control sub-circuit according to an example embodiment;

[0124] Figure 7 is an equivalent circuit diagram of a control sub-circuit according to an example embodiment;

[0125] Figure 8 is an equivalent circuit diagram of a control sub-circuit according to an example embodiment;

[0126] Figure 9A is an equivalent circuit diagram of a control sub-circuit according to an example embodiment;

[0127] Figure 9B is an equivalent circuit diagram of a control sub-circuit according to an example embodiment;

[0128] Figure 10 is an equivalent circuit diagram of an output sub-circuit according to an example embodiment;

[0129] Figure 11 is an equivalent circuit diagram of an output sub-circuit according to an example embodiment;

[0130] Figure 12 is an equivalent circuit diagram of an output sub-circuit according to an example embodiment;

[0131] Figure 13 is an equivalent circuit diagram of a shift register according to an example embodiment;

[0132] Figure 14 is a timing diagram of the shift register of Figure 13;

[0133] Figure 15 is an equivalent circuit diagram of a shift register according to an example embodiment;

[0134] Figure 16A is an equivalent circuit diagram of a shift register according to an example embodiment;

[0135] Figure 16B is an equivalent circuit diagram of a shift register according to an example embodiment;

[0136] Figure 17A is an equivalent circuit diagram of a shift register according to an example embodiment;

[0137] Figure 17B is an equivalent circuit diagram of a shift register according to an example embodiment;

[0138] Figure 18 is an equivalent circuit diagram of a shift register according to an example embodiment;

[0139] Figure 19 is an equivalent circuit diagram of a shift register according to an example embodiment;

[0140] Figure 20A is an equivalent circuit diagram of a shift register according to an example embodiment;

[0141] Figure 20B is an equivalent circuit diagram of a shift register according to an example embodiment;

[0142] FIG. 21A is an equivalent circuit diagram of a shift register according to an example embodiment;

[0143] FIG. 21B is an equivalent circuit diagram of a shift register according to an example embodiment;

[0144] FIG. 22 is an equivalent circuit diagram of a shift register according to an example embodiment;

[0145] FIG. 23A is an equivalent circuit diagram of a shift register according to an example embodiment;

[0146] FIG. 23B is an equivalent circuit diagram of a shift register according to an example embodiment;

[0147] FIG. 24 is an equivalent circuit diagram of a reset sub-circuit according to an example embodiment;

[0148] FIG. 25 is a structural circuit diagram of a display device according to an example embodiment;

[0149] FIG. 26 is an output timing diagram of a multi-stage shift register according to an example embodiment;

[0150] FIG. 27 is a structural circuit diagram of a display device according to an example embodiment;

[0151] FIG. 28 is an output timing diagram of a multi-stage shift register according to an example embodiment.

[0152] DETAILED DESCRIPTION

[0153] In order to make the objects, technical solutions and advantages of the present disclosure clearer, below will be specifically described with reference to the drawings. It should be noted that the embodiments can be implemented in a variety of different forms. One skilled in the art can easily understand that the manner and content can be changed into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the content described in the following embodiments. The embodiments in the present disclosure and the features in the embodiments can be combined with each other arbitrarily without conflict. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits the detailed description of some known functions and known components. The drawings of the embodiments of the present disclosure only involve the structures related to the embodiments of the present disclosure, and other structures can be referred to the generally designed structures

[0154] The scale of the drawings in this disclosure can be used as a reference in the actual process, but is not limited thereto. For example, the width-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted as needed. The number of pixels in the display substrate and the number of sub-pixels in each pixel are also not limited to the number shown in the drawings. The drawings described in this disclosure are only schematic diagrams, and one embodiment of this disclosure is not limited to the shapes or values shown in the drawings.

[0155] In this specification, ordinal terms such as "first", "second", and "third" are used to avoid confusion among components, and are not intended to limit in terms of numbers.

[0156] In this specification, in order to facilitate the description and simplify the description, words indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to describe the positional relationship of the components with reference to the drawings, and are not intended to indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on this disclosure. The positional relationship of the components is appropriately changed according to the direction of describing each component. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0157] In this specification, unless explicitly defined and limited otherwise, the terms "mount", "connected", and "connected" should be broadly understood. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate piece, or communication between two elements. For those skilled in the art, the specific meaning of the above terms in this disclosure can be understood according to the specific circumstances.

[0158] In this specification, a transistor refers to an element including at least a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region where current mainly flows.

[0159] In this specification, the first electrode can be a drain electrode, and the second electrode can be a source electrode, or the first electrode can be a source electrode, and the second electrode can be a drain electrode. In the case of using a transistor with opposite polarity or in the case of changing the current direction in the circuit operation, the functions of "source electrode" and "drain electrode" are sometimes exchanged with each other. Therefore, in this specification, "source electrode" and "drain electrode" can be exchanged with each other.

[0160] In the present specification, "electrically connected" includes a case where components are connected through an element having some electrical action. The element having some electrical action is not particularly limited as long as it can transmit and receive an electrical signal between the components to be connected. Examples of the element having some electrical action include not only electrodes and wiring but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0161] In the present specification, "parallel" means a state where the angle formed by two straight lines is -10° or more and 10° or less, and thus, a state where the angle is -5° or more and 5° or less is also included. In addition, "perpendicular" means a state where the angle formed by two straight lines is 80° or more and 100° or less, and thus, a state where the angle is 85° or more and 95° or less is also included.

[0162] In the present specification, "film" and "layer" can be replaced with each other. For example, "a conductive layer" can be replaced with "a conductive film". Similarly, "an insulating film" can be replaced with "an insulating layer".

[0163] In the present specification, "disposed in the same layer" means that two (or more) structures are patterned by the same patterning process, and the materials thereof can be the same or different. For example, the materials of the precursors for forming the plurality of structures disposed in the same layer are the same, and the finally formed materials can be the same or different.

[0164] In the present specification, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon is not strictly a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, but can be an approximate triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, and can have some small deformation due to a tolerance, can have a rounded corner, an arc edge, and deformation, and the like.

[0165] In the present disclosure, "about" means not strictly limited to the boundary, and allows values within a range of process and measurement errors.

[0166] The current display device uses a cascade driving circuit to generate a scanning signal, but the current cascade driving circuit output mode is relatively single and cannot meet the display requirements.

[0167] FIG. 1 is a structural schematic diagram of a shift register provided by an example embodiment of the present disclosure, as shown in FIG. 1, the shift register can include a control sub-circuit and an output sub-circuit.

[0168] The control sub-circuit is electrically connected with a signal input end IN, a first clock signal end CLK1, a first node N1, and a second node N2, respectively, and is configured to provide a signal to the first node N1 or the second node N2 under the control of signals of the signal input end IN and the first clock signal end CLK1.

[0169] The output sub-circuit is electrically connected with the first node N1, the second node N2, at least one power signal terminal Vn and at least one output signal terminal Gn respectively, and is configured to provide a signal to the at least one output signal terminal Gn under the control of signals of the first node N1, the second node N2 and the at least one power signal terminal Vn; and the length of the effective level signal provided by the output sub-circuit is greater than the length of a period of the signal provided by the first clock signal terminal.

[0170] The effective level signal provided by the output sub-circuit refers to a high level signal output by the shift register in one working process, wherein the working process includes the P1 stage to the P4 stage. In combination with the timing diagram shown in FIG. 14, in the P2 stage and the P3 stage, the high level signal provided by the output sub-circuit to the signal output terminal OUT can be the effective level signal provided by the output sub-circuit. The length of one period of the signal provided by the first clock terminal 1H can be the sum of the length of one high level signal and the length of an adjacent low level signal. The length of the effective level signal shown in FIG. 14 is about 3H, the length of the effective level signal shown in FIG. 26 is about 1.5H, and the length of the effective level signal shown in FIG. 28 is about 3H.

[0171] In an exemplary embodiment, the signal of the first clock signal terminal CLK1 can be a periodic pulse signal.

[0172] In an exemplary embodiment, as shown in FIG. 1, the shift register can further include a reset sub-circuit electrically connected with the reset signal terminal RST, the first node N1 and the seventh power terminal V7 respectively, and configured to provide the signal of the seventh power terminal V7 to the first node N1 under the control of the signal of the reset signal terminal RST.

[0173] In an exemplary embodiment, the signal of the seventh power terminal V7 is a low level signal, and the reset sub-circuit provides the signal of the seventh power terminal V7 to the first node N1 under the control of the signal of the reset signal terminal RST, so as to initialize the first node N1.

[0174] In the embodiments of the present disclosure, the control sub-circuit can provide a signal to the first node or the second node under the control of the signals of the signal input terminal and the first clock signal terminal, the reset sub-circuit can provide the signal of the seventh power terminal to the first node under the control of the signal of the reset signal terminal, and the output sub-circuit can provide a signal to the at least one output signal terminal under the control of the signals of the first node, the second node and the at least one power signal terminal. By providing the signal to the at least one output signal terminal under the control of the signals of the signal input terminal and the first clock signal terminal, the signal output of the shift register is realized, and the positive and negative of the pulse of the signal on the signal input terminal can determine the positive and negative of the pulse of the output signal of the shift register.

[0175] In an example embodiment, the control sub-circuit can comprise a first control sub-circuit, and the first control sub-circuit is further electrically connected with the first power terminal V1 and the second power terminal V2.

[0176] FIG. 2 is an equivalent circuit diagram of the control sub-circuit according to an example embodiment. As shown in FIG. 2, the first control sub-circuit is further electrically connected with the first power terminal V1 and the second power terminal V2, and the first control sub-circuit can comprise a third transistor T3, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a third capacitor C3.

[0177] In an example embodiment, as shown in FIG. 2, the control electrode of the third transistor T3 is electrically connected with the first clock signal terminal CLK1, the first electrode of the third transistor T3 is electrically connected with the signal input terminal IN, and the second electrode of the third transistor T3 is electrically connected with the second node N2; the control electrode of the fifth transistor T5 is electrically connected with the third node N3, the first electrode of the fifth transistor T5 is electrically connected with the second power terminal V2, and the second electrode of the fifth transistor T5 is electrically connected with the fourth node N4; the control electrode of the sixth transistor T6 is electrically connected with the signal input terminal IN, the first electrode of the sixth transistor T6 is electrically connected with the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected with the first power terminal V1; the control electrode of the seventh transistor T7 is electrically connected with the signal input terminal IN, the first electrode of the seventh transistor T7 is electrically connected with the third node N3, and the second electrode of the seventh transistor T7 is electrically connected with the first power terminal V1; the control electrode of the eighth transistor T8 is electrically connected with the first clock signal terminal CLK1, the first electrode of the eighth transistor T8 is electrically connected with the fourth node N4, and the second electrode of the eighth transistor T8 is electrically connected with the first node N1; the third capacitor C3 comprises a first plate C31 and a second plate C32, the first plate C31 of the third capacitor is electrically connected with the first clock signal terminal CLK1, and the second plate C32 of the third capacitor is electrically connected with the third node N3.

[0178] In an example embodiment, as shown in FIG. 2, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are P-type transistors.

[0179] In an example embodiment, the signal of the first power terminal V1 is a high-level signal, and the signal of the second power terminal V2 is a low-level signal.

[0180] An example structure of the control sub-circuit is shown in FIG. 2. It is easy for those skilled in the art to understand that the implementation of the control sub-circuit is not limited thereto.

[0181] Fig. 3 is an equivalent circuit diagram of the control sub-circuit according to an example embodiment. As shown in Fig. 3, the first control sub-circuit is also electrically connected with a first power supply end V1 and a second power supply end V2. The first control sub-circuit can include a third transistor T3, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8 and a ninth transistor T9.

[0182] In an example embodiment, as shown in Fig. 3, the control electrode of the third transistor T3 is electrically connected with the first clock signal end CLK1, the first electrode of the third transistor T3 is electrically connected with the signal input end IN, and the second electrode of the third transistor T3 is electrically connected with the second node N2. The control electrode of the fifth transistor T5 is electrically connected with the fifth node N5, the first electrode of the fifth transistor T5 is electrically connected with the second power supply end V2, and the second electrode of the fifth transistor T5 is electrically connected with the fourth node N4. The control electrode of the sixth transistor T6 is electrically connected with the signal input end IN, the first electrode of the sixth transistor T6 is electrically connected with the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected with the first power supply end V1. The control electrode of the seventh transistor T7 is electrically connected with the signal input end IN, the first electrode of the seventh transistor T7 is electrically connected with the sixth node N6, and the second electrode of the seventh transistor T7 is electrically connected with the first power supply end V1. The control electrode of the eighth transistor T8 is electrically connected with the first clock signal end CLK1, the first electrode of the eighth transistor T8 is electrically connected with the fourth node N4, and the second electrode of the eighth transistor T8 is electrically connected with the first node N1. The control electrode of the ninth transistor T9 is electrically connected with the first clock signal end CLK1, the first electrode of the ninth transistor T9 is electrically connected with the fifth node N5, and the second electrode of the ninth transistor T9 is electrically connected with the sixth node N6.

[0183] In an example embodiment, as shown in Fig. 3, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 are P-type transistors.

[0184] In an example embodiment, the signal of the first power supply end V1 is a high-level signal, and the signal of the second power supply end V2 is a low-level signal.

[0185] An example structure of the control sub-circuit is shown in Fig. 3. It is easy for those skilled in the art to understand that the implementation of the control sub-circuit is not limited to this.

[0186] In an example embodiment, the control sub-circuit can include a third control sub-circuit, which is also electrically connected with the first power supply end V1.

[0187] Fig. 4 is an equivalent circuit diagram of the control sub-circuit according to an example embodiment. As shown in Fig. 4, the third control sub-circuit is also electrically connected to the first power supply end V1. The third control sub-circuit can include a third transistor T3, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a third capacitor C3.

[0188] In an example embodiment, as shown in Fig. 4, the control electrode of the third transistor T3 is electrically connected to the first clock signal end CLK1, the first electrode of the third transistor T3 is electrically connected to the signal input end IN, and the second electrode of the third transistor T3 is electrically connected to the second node N2. The control electrode of the fifth transistor T5 is electrically connected to the third node N3, the first electrode of the fifth transistor T5 is electrically connected to the first clock signal end CLK1, and the second electrode of the fifth transistor T5 is electrically connected to the fourth node N4. The control electrode of the sixth transistor T6 is electrically connected to the signal input end IN, the first electrode of the sixth transistor T6 is electrically connected to the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected to the first power supply end V1. The control electrode of the seventh transistor T7 is electrically connected to the signal input end IN, the first electrode of the seventh transistor T7 is electrically connected to the third node N3, and the second electrode of the seventh transistor T7 is electrically connected to the first power supply end V1. The control electrode of the eighth transistor T8 is electrically connected to the first clock signal end CLK1, the first electrode of the eighth transistor T8 is electrically connected to the fourth node N4, and the second electrode of the eighth transistor T8 is electrically connected to the first node N1. The third capacitor C3 includes a first plate C31 and a second plate C32. The first plate C31 of the third capacitor is electrically connected to the first clock signal end CLK1, and the second plate C32 of the third capacitor is electrically connected to the third node N3.

[0189] In an example embodiment, as shown in Fig. 4, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are P-type transistors.

[0190] In an example embodiment, the signal of the first power supply end V1 is a high-level signal.

[0191] An example structure of the control sub-circuit is shown in Fig. 4. It is easy for those skilled in the art to understand that the implementation of the control sub-circuit is not limited to this.

[0192] Fig. 5 is an equivalent circuit diagram of the control sub-circuit according to an example embodiment. As shown in Fig. 5, the third control sub-circuit is also electrically connected to the first power supply end V1. The third control sub-circuit can include a third transistor T3, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9.

[0193] In an example embodiment, as shown in FIG. 5, the control electrode of the third transistor T3 is electrically connected with the first clock signal terminal CLK1, the first electrode of the third transistor T3 is electrically connected with the signal input terminal IN, and the second electrode of the third transistor T3 is electrically connected with the second node N2; the control electrode of the fifth transistor T5 is electrically connected with the fifth node N5, the first electrode of the fifth transistor T5 is electrically connected with the first clock signal terminal CLK1, and the second electrode of the fifth transistor T5 is electrically connected with the fourth node N4; the control electrode of the sixth transistor T6 is electrically connected with the signal input terminal IN, the first electrode of the sixth transistor T6 is electrically connected with the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected with the first power supply terminal V1; the control electrode of the seventh transistor T7 is electrically connected with the signal input terminal IN, the first electrode of the seventh transistor T7 is electrically connected with the sixth node N6, and the second electrode of the seventh transistor T7 is electrically connected with the first power supply terminal V1; the control electrode of the eighth transistor T8 is electrically connected with the first clock signal terminal CLK1, the first electrode of the eighth transistor T8 is electrically connected with the fourth node N4, and the second electrode of the eighth transistor T8 is electrically connected with the first node N1; the control electrode of the ninth transistor T9 is electrically connected with the first clock signal terminal CLK1, the first electrode of the ninth transistor T9 is electrically connected with the fifth node N5, and the second electrode of the ninth transistor T9 is electrically connected with the sixth node N6.

[0194] In an example embodiment, as shown in FIG. 5, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 are P-type transistors.

[0195] In an example embodiment, the signal of the first power supply terminal V1 is a high-level signal.

[0196] An example structure of the control sub-circuit is shown in FIG. 5. It is easy for those skilled in the art to understand that the implementation of the control sub-circuit is not limited to this.

[0197] FIG. 6 is an equivalent circuit diagram of the control sub-circuit provided in an example embodiment. As shown in FIG. 6, the first control sub-circuit is further electrically connected with the first power supply terminal V1 and the second power supply terminal V2, and the first control sub-circuit comprises the third transistor T3, the fifth transistor T5, the sixth transistor T6 and the eighth transistor T8.

[0198] In an example embodiment, as shown in FIG. 6, the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CLK1, the first electrode of the third transistor T3 is electrically connected to the signal input terminal IN, and the second electrode of the third transistor T3 is electrically connected to the second node N2; the control electrode of the fifth transistor T5 is electrically connected to the signal input terminal IN, the first electrode of the fifth transistor T5 is electrically connected to the second power supply terminal V2, and the second electrode of the fifth transistor T5 is electrically connected to the fourth node N4; the control electrode of the sixth transistor T6 is electrically connected to the signal input terminal IN, the first electrode of the sixth transistor T6 is electrically connected to the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected to the first power supply terminal V1; the control electrode of the eighth transistor T8 is electrically connected to the first clock signal terminal CLK1, the first electrode of the eighth transistor T8 is electrically connected to the fourth node N4, and the second electrode of the eighth transistor T8 is electrically connected to the first node N1.

[0199] In an example embodiment, as shown in FIG. 6, the fifth transistor T5 is an N-type transistor, and the third transistor T3, the sixth transistor T6, and the eighth transistor T8 are P-type transistors.

[0200] In an example embodiment, the signal of the first power supply terminal V1 is a high-level signal, and the signal of the second power supply terminal V2 is a low-level signal.

[0201] An example structure of the control sub-circuit is shown in FIG. 6. It is easy for those skilled in the art to understand that the implementation of the control sub-circuit is not limited to this.

[0202] In an example embodiment, the control sub-circuit can include a second control sub-circuit, and the second control sub-circuit is also electrically connected to the first power supply terminal V1, the second power supply terminal V2, and the third power supply terminal V3.

[0203] FIG. 7 is an equivalent circuit diagram of the control sub-circuit provided by an example embodiment. As shown in FIG. 7, the second control sub-circuit is also electrically connected to the first power supply terminal V1, the second power supply terminal V2, and the third power supply terminal V3, and the second control sub-circuit includes: the third transistor T3, the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8, the fifth transistor T5 is a double-gate transistor, and includes a first control electrode and a second control electrode.

[0204] In an example embodiment, as shown in FIG. 7, the control electrode of the third transistor T3 is electrically connected with the first clock signal terminal CLK1, the first electrode of the third transistor T3 is electrically connected with the signal input terminal IN, and the second electrode of the third transistor T3 is electrically connected with the second node N2; the first control electrode of the fifth transistor T5 is electrically connected with the signal input terminal IN, the second control electrode of the fifth transistor T5 is electrically connected with the third power supply terminal V3, the first electrode of the fifth transistor T5 is electrically connected with the second power supply terminal V2, and the second electrode of the fifth transistor T5 is electrically connected with the fourth node N4; the control electrode of the sixth transistor T6 is electrically connected with the signal input terminal IN, the first electrode of the sixth transistor T6 is electrically connected with the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected with the first power supply terminal V1; the control electrode of the eighth transistor T8 is electrically connected with the first clock signal terminal CLK1, the first electrode of the eighth transistor T8 is electrically connected with the fourth node N4, and the second electrode of the eighth transistor T8 is electrically connected with the first node N1.

[0205] In an example embodiment, as shown in FIG. 7, the fifth transistor T5 is an N-type transistor, and the third transistor T3, the sixth transistor T6 and the eighth transistor T8 are P-type transistors.

[0206] In an example embodiment, the signal of the first power supply terminal V1 is a high-level signal, the signal of the second power supply terminal V2 is a low-level signal, and the signal of the third power supply terminal V3 is a low-level signal.

[0207] In an example embodiment, the voltage value of the third power supply terminal V3 is less than or equal to the voltage value of the second power supply terminal V2.

[0208] An example structure of the control sub-circuit is shown in FIG. 7. It is easy for those skilled in the art to understand that the implementation of the control sub-circuit is not limited to this.

[0209] FIG. 8 is an equivalent circuit diagram of the control sub-circuit provided in an example embodiment. As shown in FIG. 8, the first control sub-circuit is further electrically connected with the first power supply terminal V1 and the second power supply terminal V2, and the first control sub-circuit can include the third transistor T3, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the third capacitor C3.

[0210] In an example embodiment, as shown in FIG. 8, the control electrode of the third transistor T3 is electrically connected with the first clock signal terminal CLK1, the first electrode of the third transistor T3 is electrically connected with the signal input terminal IN, and the second electrode of the third transistor T3 is electrically connected with the second node N2; the control electrode of the fifth transistor T5 is electrically connected with the third node N3, the first electrode of the fifth transistor T5 is electrically connected with the second power supply terminal V2, and the second electrode of the fifth transistor T5 is electrically connected with the first node N1; the control electrode of the sixth transistor T6 is electrically connected with the second node N2, the first electrode of the sixth transistor T6 is electrically connected with the first node N1, and the second electrode of the sixth transistor T6 is electrically connected with the first power supply terminal V1; the control electrode of the seventh transistor T7 is electrically connected with the signal input terminal IN, the first electrode of the seventh transistor T7 is electrically connected with the third node N3, and the second electrode of the seventh transistor T7 is electrically connected with the first power supply terminal V1; the third capacitor C3 includes a first plate C31 and a second plate C32, the first plate C31 of the third capacitor is electrically connected with the first clock signal terminal CLK1, and the second plate C32 of the third capacitor is electrically connected with the third node N3.

[0211] In an example embodiment, as shown in FIG. 8, the third transistor T3, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are P-type transistors.

[0212] In an example embodiment, the signal of the first power supply terminal V1 is a high-level signal, and the signal of the second power supply terminal V2 is a low-level signal.

[0213] An example structure of the control sub-circuit is shown in FIG. 8. It is easy for those skilled in the art to understand that the implementation of the control sub-circuit is not limited to this.

[0214] In an example embodiment, the control sub-circuit is further electrically connected with the second clock signal terminal CLK2 and the first power supply terminal V1, and is configured to provide the signal of the first power supply terminal V1 to the second node N2 under the control of the signal of the first node N1 and the second clock signal terminal CLK2.

[0215] In an example embodiment, the signal of the first power supply terminal V1 is a high-level signal.

[0216] In the embodiments of the present disclosure, the control sub-circuit can provide the signal of the first power supply terminal V1 to the second node N2 under the control of the signal of the first node N1 and the second clock signal terminal CLK2, thereby increasing the anti-noise capability of the second node N2.

[0217] FIG. 9A is an equivalent circuit diagram of the control sub-circuit provided by an example embodiment, and FIG. 9B is an equivalent circuit diagram of the control sub-circuit provided by an example embodiment. As shown in FIG. 9A and FIG. 9B, the control sub-circuit can further include a tenth transistor T10 and an eleventh transistor T11.

[0218] In an example embodiment, as shown in FIG. 9A, the control electrode of the tenth transistor T10 is electrically connected with the first node N1, the first electrode of the tenth transistor T10 is electrically connected with the first power supply end V1, and the second electrode of the tenth transistor T10 is electrically connected with the seventh node N7; the control electrode of the eleventh transistor T11 is electrically connected with the second clock signal end CLK2, the first electrode of the eleventh transistor T11 is electrically connected with the seventh node N7, and the second electrode of the eleventh transistor T11 is electrically connected with the second node N2.

[0219] In an example embodiment, as shown in FIG. 9B, the control electrode of the tenth transistor T10 is electrically connected with the second clock signal end CLK2, the first electrode of the tenth transistor T10 is electrically connected with the first node N1, and the second electrode of the tenth transistor T10 is electrically connected with the seventh node N7; the control electrode of the eleventh transistor T11 is electrically connected with the second node N2, the first electrode of the eleventh transistor T11 is electrically connected with the seventh node N7, and the second electrode of the eleventh transistor T11 is electrically connected with the first power supply end V1.

[0220] In an example embodiment, as shown in FIGS. 9A and 9B, the tenth transistor T10 and the eleventh transistor T11 are P-type transistors.

[0221] In the embodiments of the present disclosure, the tenth transistor T10 and the eleventh transistor T11 form the anti-noise circuit, and the anti-noise capability of the second node N2 is increased.

[0222] In the embodiments of the present disclosure, only the anti-noise circuit formed by the tenth transistor T10 and the eleventh transistor T11 based on the control sub-circuit shown in FIG. 2 is exemplified, and the implementation manners of the anti-noise circuit formed by the tenth transistor T10 and the eleventh transistor T11 based on the control sub-circuits shown in FIGS. 3 to 8 are the same as or similar to those, which are not limited and elaborated herein.

[0223] An example structure of the control sub-circuit is shown in FIGS. 9A and 9B. It is easy for those skilled in the art to understand that the implementation manner of the control sub-circuit is not limited thereto.

[0224] In an example embodiment, the at least one power supply signal end can include a fourth power supply end V4 and a fifth power supply end V5, and the at least one output signal end can include a signal output end OUT; an output sub-circuit is configured to provide the signal of the fourth power supply end V4 or the fifth power supply end V5 to the signal output end OUT under the control of the signals of the first node N1 and the second node N2.

[0225] In an example embodiment, the signal of the fourth power supply end V4 is a high-level signal, and the signal of the fifth power supply end V5 is a low-level signal.

[0226] In an example embodiment, the fourth power supply terminal V4 and the first power supply terminal V1 can be the same signal terminal, and the fifth power supply terminal V5 and the second power supply terminal V2 can be the same signal terminal.

[0227] FIG. 10 is an equivalent circuit diagram of an output sub-circuit according to an example embodiment. As shown in FIG. 10, the output sub-circuit can include a first transistor T1, a second transistor T2, a fourth transistor T4, a first capacitor C1, and a second capacitor C2.

[0228] In an example embodiment, as shown in FIG. 10, the control electrode of the first transistor T1 is electrically connected to the first node N1, the first electrode of the first transistor T1 is electrically connected to the fourth power supply terminal V4, and the second electrode of the first transistor T1 is electrically connected to the signal output terminal OUT; the control electrode of the second transistor T2 is electrically connected to the eighth node N8, the first electrode of the second transistor T2 is electrically connected to the signal output terminal OUT, and the second electrode of the second transistor T2 is electrically connected to the fifth power supply terminal V5; the control electrode of the fourth transistor T4 is electrically connected to the fifth power supply terminal V5, the first electrode of the fourth transistor T4 is electrically connected to the second node N2, and the second electrode of the fourth transistor T4 is electrically connected to the eighth node N8; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected to the eighth node N8, and the second plate C12 of the first capacitor is electrically connected to the signal output terminal OUT; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected to the first node N1, and the second plate C22 of the second capacitor is electrically connected to the first power supply terminal V1.

[0229] In an example embodiment, as shown in FIG. 10, the first transistor T1, the second transistor T2, and the fourth transistor T4 are P-type transistors.

[0230] An example structure of the output sub-circuit is shown in FIG. 10. It is easily understood by those skilled in the art that the implementation of the output sub-circuit is not limited thereto.

[0231] In an example embodiment, the at least one power supply signal terminal includes a fourth power supply terminal V4, a fifth power supply terminal V5, a sixth power supply terminal V6, and an eighth power supply terminal V8, the at least one output signal terminal includes a signal output terminal OUT and a cascade output terminal CR, and the output sub-circuit is configured to provide the signal of the sixth power supply terminal V6 or the eighth power supply terminal V8 to the signal output terminal OUT and provide the signal of the fourth power supply terminal V4 or the fifth power supply terminal V5 to the cascade output terminal CR under the control of the signals at the first node N1 and the second node N2.

[0232] In an example embodiment, the signal of the fourth power supply end V4 is a high level signal, the signal of the fifth power supply end V5 is a low level signal, the signal of the sixth power supply end V6 is a high level signal, and the signal of the eighth power supply end V8 is a low level signal.

[0233] In an example embodiment, the fourth power supply end V4 and the first power supply end V1 can be the same signal end, and the fifth power supply end V5 and the second power supply end V2 can be the same signal end.

[0234] FIG. 11 is an equivalent circuit diagram of an output sub-circuit according to an example embodiment. As shown in FIG. 11, the output sub-circuit can include a first transistor T1, a second transistor T2, a fourth transistor T4, a twelfth transistor T12, a thirteenth transistor T13, a first capacitor C1, and a second capacitor C2.

[0235] In an example embodiment, as shown in FIG. 11, the control electrode of the first transistor T1 is electrically connected with the first node N1, the first electrode of the first transistor T1 is electrically connected with the fourth power supply end V4, and the second electrode of the first transistor T1 is electrically connected with the cascade output end CR; the control electrode of the second transistor T2 is electrically connected with the eighth node N8, the first electrode of the second transistor T2 is electrically connected with the cascade output end CR, and the second electrode of the second transistor T2 is electrically connected with the fifth power supply end V5; the control electrode of the fourth transistor T4 is electrically connected with the fifth power supply end V5, the first electrode of the fourth transistor T4 is electrically connected with the second node N2, and the second electrode of the fourth transistor T4 is electrically connected with the eighth node N8; the control electrode of the twelfth transistor T12 is electrically connected with the first node N1, the first electrode of the twelfth transistor T12 is electrically connected with the sixth power supply end V6, and the second electrode of the twelfth transistor T12 is electrically connected with the signal output end OUT; the control electrode of the thirteenth transistor T13 is electrically connected with the eighth node N8, the first electrode of the thirteenth transistor T13 is electrically connected with the signal output end OUT, and the second electrode of the thirteenth transistor T13 is electrically connected with the eighth power supply end V8; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected with the eighth node N8, and the second plate C12 of the first capacitor is electrically connected with the cascade output end CR; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected with the first node N1, and the second plate C22 of the second capacitor is electrically connected with the fourth power supply end V4.

[0236] In an example embodiment, as shown in FIG. 11, the first transistor T1, the second transistor T2, the fourth transistor T4, the twelfth transistor T12, and the thirteenth transistor T13 are P-type transistors.

[0237] An example structure of the output sub-circuit is shown in FIG. 11. It is easy for those skilled in the art to understand that the implementation of the output sub-circuit is not limited thereto.

[0238] Fig. 12 is an equivalent circuit diagram of an output sub-circuit according to an example embodiment. As shown in Fig. 12, the output sub-circuit can include a first transistor T1, a second transistor T2, a fourth transistor T4, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a first capacitor C1, a second capacitor C2, and a fourth capacitor C4.

[0239] In an example embodiment, a control electrode of the first transistor T1 is electrically connected with the first node N1, a first electrode of the first transistor T1 is electrically connected with the fourth power supply end V4, and a second electrode of the first transistor T1 is electrically connected with the cascade output end CR; a control electrode of the second transistor T2 is electrically connected with the eighth node N8, a first electrode of the second transistor T2 is electrically connected with the cascade output end CR, and a second electrode of the second transistor T2 is electrically connected with the fifth power supply end V5; a control electrode of the fourth transistor T4 is electrically connected with the fifth power supply end V5, a first electrode of the fourth transistor T4 is electrically connected with the second node N2, and a second electrode of the fourth transistor T4 is electrically connected with the eighth node N8; a control electrode of the twelfth transistor T12 is electrically connected with the ninth node N9, a first electrode of the twelfth transistor T12 is electrically connected with the sixth power supply end V6, and a second electrode of the twelfth transistor T12 is electrically connected with the signal output end OUT; a control electrode of the thirteenth transistor T13 is electrically connected with the second node N2, a first electrode of the thirteenth transistor T13 is electrically connected with the signal output end OUT, and a second electrode of the thirteenth transistor T13 is electrically connected with the eighth power supply end V8; a control electrode of the fourteenth transistor T14 is electrically connected with the fifth power supply end V5, a first electrode of the fourteenth transistor T14 is electrically connected with the first node N1, and a second electrode of the fourteenth transistor T14 is electrically connected with the ninth node N9; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected with the eighth node N8, and the second plate C12 of the first capacitor is electrically connected with the cascade output end CR; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected with the first node N1, and the second plate C22 of the second capacitor is electrically connected with the fourth power supply end V4; the fourth capacitor C4 includes a first plate C41 and a second plate C42, the first plate C41 of the fourth capacitor is electrically connected with the ninth node N9, and the second plate C42 of the fourth capacitor is electrically connected with the signal output end OUT.

[0240] In an example embodiment, as shown in Fig. 12, the first transistor T1, the second transistor T2, the fourth transistor T4, the twelfth transistor T12, the thirteenth transistor T13, and the fourteenth transistor T14 are P-type transistors.

[0241] An example structure of the output sub-circuit is shown in Fig. 12. It is easy for those skilled in the art to understand that the implementation of the output sub-circuit is not limited to this.

[0242] Figure 13 is an equivalent circuit diagram of a shift register according to an example embodiment. As shown in Figure 13, the at least one power signal terminal includes a fourth power terminal V4 and a fifth power terminal V5, the at least one output signal terminal includes a signal output terminal OUT, the control sub-circuit includes a third transistor T3, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a third capacitor C3, and the output sub-circuit includes a first transistor T1, a second transistor T2, a fourth transistor T4, a first capacitor C1, and a second capacitor C2.

[0243] In an example embodiment, a control electrode of the first transistor T1 is electrically connected with the first node N1, a first electrode of the first transistor T1 is electrically connected with the fourth power supply end V4, and a second electrode of the first transistor T1 is electrically connected with the signal output end OUT; a control electrode of the second transistor T2 is electrically connected with the eighth node N8, a first electrode of the second transistor T2 is electrically connected with the signal output end OUT, and a second electrode of the second transistor T2 is electrically connected with the fifth power supply end V5; a control electrode of the third transistor T3 is electrically connected with the first clock signal end CLK1, a first electrode of the third transistor T3 is electrically connected with the signal input end IN, and a second electrode of the third transistor T3 is electrically connected with the second node N2; a control electrode of the fourth transistor T4 is electrically connected with the fifth power supply end V5, a first electrode of the fourth transistor T4 is electrically connected with the second node N2, and a second electrode of the fourth transistor T4 is electrically connected with the eighth node N8; a control electrode of the fifth transistor T5 is electrically connected with the third node N3, a first electrode of the fifth transistor T5 is electrically connected with the second power supply end V2, and a second electrode of the fifth transistor T5 is electrically connected with the fourth node N4; a control electrode of the sixth transistor T6 is electrically connected with the signal input end IN, a first electrode of the sixth transistor T6 is electrically connected with the fourth node N4, and a second electrode of the sixth transistor T6 is electrically connected with the first power supply end V1; a control electrode of the seventh transistor T7 is electrically connected with the signal input end IN, a first electrode of the seventh transistor T7 is electrically connected with the third node N3, and a second electrode of the seventh transistor T7 is electrically connected with the first power supply end V1; a control electrode of the eighth transistor T8 is electrically connected with the first clock signal end CLK1, a first electrode of the eighth transistor T8 is electrically connected with the fourth node N4, and a second electrode of the eighth transistor T8 is electrically connected with the first node N1; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected with the eighth node N8, and the second plate C12 of the first capacitor is electrically connected with the signal output end OUT; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected with the first node N1, and the second plate C22 of the second capacitor is electrically connected with the fourth power supply end V4; the third capacitor C3 includes a first plate C31 and a second plate C32, the first plate C31 of the third capacitor is electrically connected with the first clock signal end CLK1, and the second plate C32 of the third capacitor is electrically connected with the third node N3.

[0244] In an example embodiment, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are P-type transistors.

[0245] In an example embodiment, a signal of the first power supply end V1 is a high-level signal, and a signal of the second power supply end V2 is a low-level signal.

[0246] In an example embodiment, the signal of the fourth power supply terminal V4 is a high level signal, and the signal of the fifth power supply terminal V5 is a low level signal.

[0247] In an example embodiment, the fourth power supply terminal V4 and the first power supply terminal V1 can be the same signal terminal, and the fifth power supply terminal V5 and the second power supply terminal V2 can be the same signal terminal.

[0248] An example structure of the shift register is shown in FIG. 13. It is easy for those skilled in the art to understand that the implementation of the shift register is not limited to this.

[0249] FIG. 14 is a working timing diagram of the shift register provided in FIG. 13. The working process of the first stage shift register exemplified by FIG. 13 is described below. The signal of the signal input terminal IN is the signal of the initial signal line STV, and the working process of the shift register can include:

[0250] The first stage P1: the signal of the signal input terminal IN is a high level signal, the signal of the first clock signal terminal CLK1 is a high level signal, the third node N3 maintains a high level signal, the second node N2 and the eighth node N8 maintain a low level signal, the fourth node N4 and the first node N1 maintain a high level signal, and the signal output terminal OUT outputs a low voltage signal.

[0251] The second stage P2: the signal of the signal input terminal IN is a high level signal, the seventh transistor T7 and the sixth transistor T6 are turned off, and the voltage of the third node N3 changes with the signal of the first clock signal terminal CLK1; when the signal of the first clock signal terminal CLK1 is a low level signal, the voltage of the third node N3 is lowered by the signal of the first clock signal terminal CLK1, the fifth transistor T5 is turned on, the low voltage signal of the second power supply terminal V2 is written to the fourth node N4, the eighth transistor T8 is turned on, the signals of the fourth node N4 and the first node N1 change from a high level signal to a low level signal, the first transistor T1 is turned on, the high level signal of the fourth power supply terminal V4 is written to the signal output terminal OUT, and the signal output terminal OUT outputs a high level signal. When the signal of the first clock signal terminal CLK1 is a high level signal, the voltage of the third node N3 is lowered by the signal of the first clock signal terminal CLK1, and the fifth transistor T5 is turned off; the eighth transistor T8 is turned off, and the first node N1 maintains a low level signal under the action of the second capacitor C2, the first transistor T1 is turned on, the high level signal of the fourth power supply terminal V4 is written to the signal output terminal OUT, and the signal output terminal OUT outputs a high level signal.

[0252] The third stage P3: the signal of the signal input terminal IN is low signal, the seventh transistor T7 and the sixth transistor T6 are turned on respectively, the signal of the first power supply terminal V1 is written into the third node N3 and charges the third capacitor C3, and the signal of the first power supply terminal V1 is written into the fourth node N4; since the first power supply terminal V1 is high signal, the signals of the third node N3 and the fourth node N4 are high signal respectively. The signal of the first clock signal terminal CLK1 is high signal, the eighth transistor T8 is disconnected, the first node N1 maintains low signal under the action of the second capacitor C2, the first transistor T1 is turned on, the high signal of the fourth power supply terminal V4 is written into the signal output terminal OUT, and the signal output terminal OUT outputs high signal.

[0253] The fourth stage P4: the signal of the signal input terminal IN is low signal, the sixth transistor T6 and the seventh transistor T7 are turned on, the signals of the third node N3 and the fourth node N4 are high signal respectively. The signal of the first clock signal terminal CLK1 is low signal, the eighth transistor T8 is turned on, the high signal of the fourth node N4 is written into the first node N1, the first node N1 changes from low signal to high signal, and the first transistor T1 is disconnected. The third transistor T3 is turned on, the fourth transistor T4 is turned on since the fifth power supply terminal V5 is low signal, and the low signal of the signal input terminal IN is written into the second node N2 and the eighth node N8 respectively. The eighth node N8 is low signal, the second transistor T2 is turned on, and the signal of the fifth power supply terminal V5 is written into the signal output terminal OUT; since the fifth power supply terminal V5 is low signal, the signal output terminal OUT outputs low signal. Since the signal output terminal OUT changes from high signal to low signal, the eighth node N8 is continuously pulled down in this stage by the coupling effect of the first capacitor C1, the voltage is lower than the voltage of the fifth power supply terminal V5, the fourth transistor T4 enters the cut-off state at this time, the low voltage of the eighth node N8 is maintained, so as to ensure that the second transistor T2 is continuously opened and the signal output terminal OUT outputs no step.

[0254] The working processes of the shift registers in the following embodiments are similar to the above, and the following embodiments will not be described in detail.

[0255] FIG. 15 is an equivalent circuit diagram of a shift register provided by an exemplary embodiment, as shown in FIG. 15, the at least one power supply signal terminal includes: the fourth power supply terminal V4 and the fifth power supply terminal V5, the at least one output signal terminal includes: the signal output terminal OUT, the control sub-circuit includes: the third transistor T3, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9, and the output sub-circuit includes: the first transistor T1, the second transistor T2, the fourth transistor T4, the first capacitor C1 and the second capacitor C2.

[0256] In an example embodiment, as shown in FIG. 15, the control electrode of the first transistor T1 is electrically connected with the first node N1, the first electrode of the first transistor T1 is electrically connected with the fourth power supply end V4, and the second electrode of the first transistor T1 is electrically connected with the signal output end OUT; the control electrode of the second transistor T2 is electrically connected with the eighth node N8, the first electrode of the second transistor T2 is electrically connected with the signal output end OUT, and the second electrode of the second transistor T2 is electrically connected with the fifth power supply end V5; the control electrode of the third transistor T3 is electrically connected with the first clock signal end CLK1, the first electrode of the third transistor T3 is electrically connected with the signal input end IN, and the second electrode of the third transistor T3 is electrically connected with the second node N2; the control electrode of the fourth transistor T4 is electrically connected with the fifth power supply end V5, the first electrode of the fourth transistor T4 is electrically connected with the second node N2, and the second electrode of the fourth transistor T4 is electrically connected with the eighth node N8; the control electrode of the fifth transistor T5 is electrically connected with the fifth node N5, the first electrode of the fifth transistor T5 is electrically connected with the first clock signal end CLK1 or the second power supply end V2, and the second electrode of the fifth transistor T5 is electrically connected with the fourth node N4; the control electrode of the sixth transistor T6 is electrically connected with the signal input end IN, the first electrode of the sixth transistor T6 is electrically connected with the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected with the first power supply end V1; the control electrode of the seventh transistor T7 is electrically connected with the signal input end IN, the first electrode of the seventh transistor T7 is electrically connected with the sixth node N6, and the second electrode of the seventh transistor T7 is electrically connected with the first power supply end V1; the control electrode of the eighth transistor T8 is electrically connected with the first clock signal end CLK1, the first electrode of the eighth transistor T8 is electrically connected with the fourth node N4, and the second electrode of the eighth transistor T8 is electrically connected with the first node N1; the control electrode of the ninth transistor T9 is electrically connected with the first clock signal end CLK1, the first electrode of the ninth transistor T9 is electrically connected with the fifth node N5, and the second electrode of the ninth transistor T9 is electrically connected with the sixth node N6; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected with the eighth node N8, and the second plate C12 of the first capacitor is electrically connected with the signal output end OUT; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected with the first node N1, and the second plate C22 of the second capacitor is electrically connected with the fourth power supply end V4.

[0257] In an example embodiment, as shown in FIG. 15, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are P-type transistors.

[0258] In an example embodiment, the signal of the first power supply end V1 is a high-level signal, and the signal of the second power supply end V2 is a low-level signal.

[0259] In an example embodiment, the signal of the fourth power supply terminal V4 is a high level signal, and the signal of the fifth power supply terminal V5 is a low level signal.

[0260] In an example embodiment, the fourth power supply terminal V4 and the first power supply terminal V1 can be the same signal terminal, and the fifth power supply terminal V5 and the second power supply terminal V2 can be the same signal terminal.

[0261] An example structure of the shift register is shown in FIG. 15. It is easy for those skilled in the art to understand that the implementation of the shift register is not limited to this.

[0262] FIG. 16A is an equivalent circuit diagram of the shift register provided by an example embodiment. As shown in FIG. 16A, the at least one power supply signal terminal includes a fourth power supply terminal V4, a fifth power supply terminal V5, a sixth power supply terminal V6, and an eighth power supply terminal V8, the at least one output signal terminal includes a signal output terminal OUT and a cascade output terminal CR, the control sub-circuit includes a third transistor T3, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a third capacitor C3, and the output sub-circuit includes a first transistor T1, a second transistor T2, a fourth transistor T4, a twelfth transistor T12, a thirteenth transistor T13, a first capacitor C1, and a second capacitor C2.

[0263] In an example embodiment, as shown in FIG. 16A, the control electrode of the first transistor T1 is electrically connected with the first node N1, the first electrode of the first transistor T1 is electrically connected with the fourth power supply end V4, and the second electrode of the first transistor T1 is electrically connected with the cascade output end CR; the control electrode of the second transistor T2 is electrically connected with the eighth node N8, the first electrode of the second transistor T2 is electrically connected with the cascade output end CR, and the second electrode of the second transistor T2 is electrically connected with the fifth power supply end V5; the control electrode of the third transistor T3 is electrically connected with the first clock signal end CLK1, the first electrode of the third transistor T3 is electrically connected with the signal input end IN, and the second electrode of the third transistor T3 is electrically connected with the second node N2; the control electrode of the fourth transistor T4 is electrically connected with the fifth power supply end V5, the first electrode of the fourth transistor T4 is electrically connected with the second node N2, and the second electrode of the fourth transistor T4 is electrically connected with the eighth node N8; the control electrode of the fifth transistor T5 is electrically connected with the third node N3, the first electrode of the fifth transistor T5 is electrically connected with the first clock signal end CLK1 or the second power supply end V2, and the second electrode of the fifth transistor T5 is electrically connected with the fourth node N4; the control electrode of the sixth transistor T6 is electrically connected with the signal input end IN, the first electrode of the sixth transistor T6 is electrically connected with the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected with the first power supply end V1; the control electrode of the seventh transistor T7 is electrically connected with the signal input end IN, the first electrode of the seventh transistor T7 is electrically connected with the third node N3, and the second electrode of the seventh transistor T7 is electrically connected with the first power supply end V1; the control electrode of the eighth transistor T8 is electrically connected with the first clock signal end CLK1, the first electrode of the eighth transistor T8 is electrically connected with the fourth node N4, and the second electrode of the eighth transistor T8 is electrically connected with the first node N1; the control electrode of the twelfth transistor T12 is electrically connected with the first node N1, the first electrode of the twelfth transistor T12 is electrically connected with the sixth power supply end V6, and the second electrode of the twelfth transistor T12 is electrically connected with the signal output end OUT; the control electrode of the thirteenth transistor T13 is electrically connected with the eighth node N8, the first electrode of the thirteenth transistor T13 is electrically connected with the signal output end OUT, and the second electrode of the thirteenth transistor T13 is electrically connected with the eighth power supply end V8; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected with the eighth node N8, and the second plate C12 of the first capacitor is electrically connected with the cascade output end CR; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected with the first node N1, and the second plate C22 of the second capacitor is electrically connected with the fourth power supply end V4; the third capacitor C3 includes a first plate C31 and a second plate C32, the first plate C31 of the third capacitor is electrically connected with the first clock signal end CLK1, and the second plate C32 of the third capacitor is electrically connected with the third node N3.

[0264] In an example embodiment, as shown in FIG. 16A, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the twelfth transistor T12, and the thirteenth transistor T13 are P-type transistors.

[0265] In an example embodiment, the signal of the first power terminal V1 is a high-level signal, and the signal of the second power terminal V2 is a low-level signal.

[0266] In an example embodiment, the signal of the fourth power terminal V4 is a high-level signal, the signal of the fifth power terminal V5 is a low-level signal, the signal of the sixth power terminal V6 is a high-level signal, and the signal of the eighth power terminal V8 is a low-level signal.

[0267] In an example embodiment, the fourth power terminal V4 and the first power terminal V1 can be the same signal terminal, and the fifth power terminal V5 and the second power terminal V2 can be the same signal terminal.

[0268] An example structure of the shift register is shown in FIG. 16A. It is easy for those skilled in the art to understand that the implementation of the shift register is not limited to this.

[0269] FIG. 16B is an equivalent circuit diagram of the shift register provided in an example embodiment. As shown in FIG. 16B, at least one power signal terminal includes a fourth power terminal V4, a fifth power terminal V5, a sixth power terminal V6, and an eighth power terminal V8, at least one output signal terminal includes a signal output terminal OUT and a cascade output terminal CR, a control sub-circuit includes a third transistor T3, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a third capacitor C3, and an output sub-circuit includes a first transistor T1, a second transistor T2, a fourth transistor T4, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a first capacitor C1, a second capacitor C2, and a fourth capacitor C4.

[0270] In an example embodiment, as shown in FIG. 16B, the control electrode of the first transistor T1 is electrically connected with the first node N1, the first electrode of the first transistor T1 is electrically connected with the fourth power supply end V4, and the second electrode of the first transistor T1 is electrically connected with the cascade output end CR; the control electrode of the second transistor T2 is electrically connected with the eighth node N8, the first electrode of the second transistor T2 is electrically connected with the cascade output end CR, and the second electrode of the second transistor T2 is electrically connected with the fifth power supply end V5; the control electrode of the third transistor T3 is electrically connected with the first clock signal end CLK1, the first electrode of the third transistor T3 is electrically connected with the signal input end IN, and the second electrode of the third transistor T3 is electrically connected with the second node N2; the control electrode of the fourth transistor T4 is electrically connected with the fifth power supply end V5, the first electrode of the fourth transistor T4 is electrically connected with the second node N2, and the second electrode of the fourth transistor T4 is electrically connected with the eighth node N8; the control electrode of the fifth transistor T5 is electrically connected with the third node N3, the first electrode of the fifth transistor T5 is electrically connected with the first clock signal end CLK1 or the second power supply end V2, and the second electrode of the fifth transistor T5 is electrically connected with the fourth node N4; the control electrode of the sixth transistor T6 is electrically connected with the signal input end IN, the first electrode of the sixth transistor T6 is electrically connected with the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected with the first power supply end V1; the control electrode of the seventh transistor T7 is electrically connected with the signal input end IN, the first electrode of the seventh transistor T7 is electrically connected with the third node N3, and the second electrode of the seventh transistor T7 is electrically connected with the first power supply end V1; the control electrode of the eighth transistor T8 is electrically connected with the first clock signal end CLK1, the first electrode of the eighth transistor T8 is electrically connected with the fourth node N4, and the second electrode of the eighth transistor T8 is electrically connected with the first node N1; the control electrode of the twelfth transistor T12 is electrically connected with the ninth node N9, the first electrode of the twelfth transistor T12 is electrically connected with the sixth power supply end V6, and the second electrode of the twelfth transistor T12 is electrically connected with the signal output end OUT; the control electrode of the thirteenth transistor T13 is electrically connected with the second node N2, the first electrode of the thirteenth transistor T13 is electrically connected with the signal output end OUT, and the second electrode of the thirteenth transistor T13 is electrically connected with the eighth power supply end V8; the control electrode of the fourteenth transistor T14 is electrically connected with the fifth power supply end V5, the first electrode of the fourteenth transistor T14 is electrically connected with the first node N1, and the second electrode of the fourteenth transistor T14 is electrically connected with the ninth node N9; the first capacitor C1 comprises a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected with the eighth node N8, and the second plate C12 of the first capacitor is electrically connected with the cascade output end CR; the second capacitor C2 comprises a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected with the first node N1, and the second plate C22 of the second capacitor is electrically connected with the fourth power supply end V4.The third capacitor C3 includes a first plate C31 and a second plate C32, the first plate C31 of the third capacitor is electrically connected with the first clock signal terminal CLK1, and the second plate C32 of the third capacitor is electrically connected with the third node N3; the fourth capacitor C4 includes a first plate C41 and a second plate C42, the first plate C41 of the fourth capacitor is electrically connected with the ninth node N9, and the second plate C42 of the fourth capacitor is electrically connected with the signal output terminal OUT.

[0271] In an example embodiment, as shown in FIG. 16B, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the twelfth transistor T12, the thirteenth transistor T13 and the fourteenth transistor T14 are P-type transistors.

[0272] In an example embodiment, the signal of the first power terminal V1 is a high-level signal, and the signal of the second power terminal V2 is a low-level signal.

[0273] In an example embodiment, the signal of the fourth power terminal V4 is a high-level signal, the signal of the fifth power terminal V5 is a low-level signal, the signal of the sixth power terminal V6 is a high-level signal, and the signal of the eighth power terminal V8 is a low-level signal.

[0274] In an example embodiment, the fourth power terminal V4 and the first power terminal V1 can be the same signal terminal, and the fifth power terminal V5 and the second power terminal V2 can be the same signal terminal.

[0275] An example structure of the shift register is shown in FIG. 16B. It is easy for those skilled in the art to understand that the implementation of the shift register is not limited to this.

[0276] FIG. 17A is an equivalent circuit diagram of a shift register provided by an example embodiment. As shown in FIG. 17A, at least one power signal terminal includes a fourth power terminal V4, a fifth power terminal V5, a sixth power terminal V6 and an eighth power terminal V8, at least one output signal terminal includes a signal output terminal OUT and a cascade output terminal CR, a control sub-circuit includes a third transistor T3, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8 and a ninth transistor T9, and an output sub-circuit includes a first transistor T1, a second transistor T2, a fourth transistor T4, a twelfth transistor T12, a thirteenth transistor T13, a first capacitor C1 and a second capacitor C2.

[0277] In an example embodiment, as shown in FIG. 17A, the control electrode of the first transistor T1 is electrically connected with the first node N1, the first electrode of the first transistor T1 is electrically connected with the fourth power supply end V4, and the second electrode of the first transistor T1 is electrically connected with the cascade output end CR; the control electrode of the second transistor T2 is electrically connected with the eighth node N8, the first electrode of the second transistor T2 is electrically connected with the cascade output end CR, and the fifth power supply end V5 of the second transistor T2 is electrically connected; the control electrode of the third transistor T3 is electrically connected with the first clock signal end CLK1, the first electrode of the third transistor T3 is electrically connected with the signal input end IN, and the second electrode of the third transistor T3 is electrically connected with the second node N2; the control electrode of the fourth transistor T4 is electrically connected with the fifth power supply end V5, the first electrode of the fourth transistor T4 is electrically connected with the second node N2, and the second electrode of the fourth transistor T4 is electrically connected with the eighth node N8; the control electrode of the fifth transistor T5 is electrically connected with the fifth node N5, the first electrode of the fifth transistor T5 is electrically connected with the first clock signal end CLK1 or the second power supply end V2, and the second electrode of the fifth transistor T5 is electrically connected with the fourth node N4; the control electrode of the sixth transistor T6 is electrically connected with the signal input end IN, the first electrode of the sixth transistor T4 is electrically connected with the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected with the first power supply end V1; the control electrode of the seventh transistor T7 is electrically connected with the signal input end IN, the first electrode of the seventh transistor T7 is electrically connected with the sixth node N6, and the second electrode of the seventh transistor T7 is electrically connected with the first power supply end V1; the control electrode of the eighth transistor T8 is electrically connected with the first clock signal end CLK1, the first electrode of the eighth transistor T8 is electrically connected with the fourth node N4, and the second electrode of the eighth transistor T8 is electrically connected with the first node N1; the control electrode of the ninth transistor T9 is electrically connected with the first clock signal end CLK1, the first electrode of the ninth transistor T9 is electrically connected with the fifth node N5, and the second electrode of the ninth transistor T9 is electrically connected with the sixth node N6; the control electrode of the twelfth transistor T12 is electrically connected with the first node N1, the first electrode of the twelfth transistor T12 is electrically connected with the sixth power supply end V6, and the second electrode of the twelfth transistor T12 is electrically connected with the signal output end OUT; the control electrode of the thirteenth transistor T13 is electrically connected with the eighth node N8, the first electrode of the thirteenth transistor T13 is electrically connected with the signal output end OUT, and the second electrode of the thirteenth transistor T13 is electrically connected with the eighth power supply end V8; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected with the eighth node N8, and the second plate C12 of the first capacitor is electrically connected with the cascade output end CR; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected with the first node N1, and the second plate C22 of the second capacitor is electrically connected with the fourth power supply end V4.

[0278] In an example embodiment, as shown in FIG. 17A, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the twelfth transistor T12, and the thirteenth transistor T13 are P-type transistors.

[0279] In an example embodiment, the signal of the first power terminal V1 is a high-level signal, and the signal of the second power terminal V2 is a low-level signal.

[0280] In an example embodiment, the signal of the fourth power terminal V4 is a high-level signal, the signal of the fifth power terminal V5 is a low-level signal, the signal of the sixth power terminal V6 is a high-level signal, and the signal of the eighth power terminal V8 is a low-level signal.

[0281] In an example embodiment, the fourth power terminal V4 and the first power terminal V1 can be the same signal terminal, and the fifth power terminal V5 and the second power terminal V2 can be the same signal terminal.

[0282] An example structure of the shift register is shown in FIG. 17A. It is easy for those skilled in the art to understand that the implementation of the shift register is not limited to this.

[0283] FIG. 17B is an equivalent circuit diagram of the shift register provided in an example embodiment. As shown in FIG. 17B, the at least one power signal terminal includes the fourth power terminal V4, the fifth power terminal V5, the sixth power terminal V6, and the eighth power terminal V8, the at least one output signal terminal includes the signal output terminal OUT and the cascade output terminal CR, the control sub-circuit includes the third transistor T3, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9, and the output sub-circuit includes the first transistor T1, the second transistor T2, the fourth transistor T4, the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor T14, the first capacitor C1, the second capacitor C2, and the fourth capacitor C4.

[0284] In an example embodiment, as shown in FIG. 17B, the control electrode of the first transistor T1 is electrically connected with the first node N1, the first electrode of the first transistor T1 is electrically connected with the fourth power supply end V4, and the second electrode of the first transistor T1 is electrically connected with the cascade output end CR; the control electrode of the second transistor T2 is electrically connected with the eighth node N8, the first electrode of the second transistor T2 is electrically connected with the cascade output end CR, and the fifth power supply end V5 of the second transistor T2 is electrically connected; the control electrode of the third transistor T3 is electrically connected with the first clock signal end CLK1, the first electrode of the third transistor T3 is electrically connected with the signal input end IN, and the second electrode of the third transistor T3 is electrically connected with the second node N2; the control electrode of the fourth transistor T4 is electrically connected with the fifth power supply end V5, the first electrode of the fourth transistor T4 is electrically connected with the second node N2, and the second electrode of the fourth transistor T4 is electrically connected with the eighth node N8; the control electrode of the fifth transistor T5 is electrically connected with the fifth node N5, the first electrode of the fifth transistor T5 is electrically connected with the first clock signal end CLK1 or the second power supply end V2, and the second electrode of the fifth transistor T5 is electrically connected with the fourth node N4; the control electrode of the sixth transistor T6 is electrically connected with the signal input end IN, the first electrode of the sixth transistor T4 is electrically connected with the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected with the first power supply end V1; the control electrode of the seventh transistor T7 is electrically connected with the signal input end IN, the first electrode of the seventh transistor T7 is electrically connected with the sixth node N6, and the second electrode of the seventh transistor T7 is electrically connected with the first power supply end V1; the control electrode of the eighth transistor T8 is electrically connected with the first clock signal end CLK1, the first electrode of the eighth transistor T8 is electrically connected with the fourth node N4, and the second electrode of the eighth transistor T8 is electrically connected with the first node N1; the control electrode of the ninth transistor T9 is electrically connected with the first clock signal end CLK1, the first electrode of the ninth transistor T9 is electrically connected with the fifth node N5, and the second electrode of the ninth transistor T9 is electrically connected with the sixth node N6; the control electrode of the twelfth transistor T12 is electrically connected with the ninth node N9, the first electrode of the twelfth transistor T12 is electrically connected with the sixth power supply end V6, and the second electrode of the twelfth transistor T12 is electrically connected with the signal output end OUT; the control electrode of the thirteenth transistor T13 is electrically connected with the second node N2, the first electrode of the thirteenth transistor T13 is electrically connected with the signal output end OUT, and the second electrode of the thirteenth transistor T13 is electrically connected with the eighth power supply end V8; the control electrode of the fourteenth transistor T14 is electrically connected with the fifth power supply end V5, the first electrode of the fourteenth transistor T14 is electrically connected with the first node N1, and the second electrode of the fourteenth transistor T14 is electrically connected with the ninth node N9; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected with the eighth node N8, and the second plate C12 of the first capacitor is electrically connected with the cascade output end CR.The second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected with the first node N1, and the second plate C22 of the second capacitor is electrically connected with the fourth power terminal V4. The fourth capacitor C4 includes a first plate C41 and a second plate C42, the first plate C41 of the fourth capacitor is electrically connected with the ninth node N9, and the second plate C42 of the fourth capacitor is electrically connected with the signal output terminal OUT.

[0285] In an example embodiment, as shown in FIG. 17B, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the twelfth transistor T12, the thirteenth transistor T13 and the fourteenth transistor T14 are P-type transistors.

[0286] In an example embodiment, the signal of the first power terminal V1 is a high-level signal, and the signal of the second power terminal V2 is a low-level signal.

[0287] In an example embodiment, the signal of the fourth power terminal V4 is a high-level signal, the signal of the fifth power terminal V5 is a low-level signal, the signal of the sixth power terminal V6 is a high-level signal, and the signal of the eighth power terminal V8 is a low-level signal.

[0288] In an example embodiment, the fourth power terminal V4 and the first power terminal V1 can be the same signal terminal, and the fifth power terminal V5 and the second power terminal V2 can be the same signal terminal.

[0289] An example structure of the shift register is shown in FIG. 17B. It is easy for those skilled in the art to understand that the implementation of the shift register is not limited to this.

[0290] FIG. 18 is an equivalent circuit diagram of a shift register provided in an example embodiment. As shown in FIG. 18, the at least one power signal terminal includes a fourth power terminal V4 and a fifth power terminal V5, the at least one output signal terminal includes a signal output terminal OUT, the control sub-circuit includes a third transistor T3, a fifth transistor T5, a sixth transistor T6 and an eighth transistor T8, and the output sub-circuit includes a first transistor T1, a second transistor T2, a fourth transistor T4, a first capacitor C1 and a second capacitor C2.

[0291] In an example embodiment, as shown in FIG. 18, the control electrode of the first transistor T1 is electrically connected to the first node N1, the first electrode of the first transistor T1 is electrically connected to the fourth power supply terminal V4, and the second electrode of the first transistor T1 is electrically connected to the signal output terminal OUT; the control electrode of the second transistor T2 is electrically connected to the eighth node N8, the first electrode of the second transistor T2 is electrically connected to the signal output terminal OUT, and the second electrode of the second transistor T2 is electrically connected to the fifth power supply terminal V5; the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CLK1, the first electrode of the third transistor T3 is electrically connected to the signal input terminal IN, and the second electrode of the third transistor T3 is electrically connected to the second node N2; the control electrode of the fourth transistor T4 is electrically connected to the fifth power supply terminal V5, the first electrode of the fourth transistor T4 is electrically connected to the second node N2, and the second electrode of the fourth transistor T4 is electrically connected to the eighth node N8; the control electrode of the fifth transistor T5 is electrically connected to the signal input terminal IN, the first electrode of the fifth transistor T5 is electrically connected to the second power supply terminal V2, and the second electrode of the fifth transistor T5 is electrically connected to the fourth node N4; the control electrode of the sixth transistor T6 is electrically connected to the signal input terminal IN, the first electrode of the sixth transistor T6 is electrically connected to the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected to the first power supply terminal V1; the control electrode of the eighth transistor T8 is electrically connected to the first clock signal terminal CLK1, the first electrode of the eighth transistor T8 is electrically connected to the fourth node N4, and the second electrode of the eighth transistor T8 is electrically connected to the first node N1; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected to the eighth node N8, and the second plate C12 of the first capacitor is electrically connected to the signal output terminal OUT; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate of the second capacitor is electrically connected to the first node N1, and the second plate of the second capacitor is electrically connected to the fourth power supply terminal V4.

[0292] In an example embodiment, as shown in FIG. 18, the fifth transistor T5 is an N-type transistor, and the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the sixth transistor T6, and the eighth transistor T8 are P-type transistors.

[0293] In an example embodiment, the signal of the first power supply terminal V1 is a high-level signal, and the signal of the second power supply terminal V2 is a low-level signal.

[0294] In an example embodiment, the signal of the fourth power supply terminal V4 is a high-level signal, and the signal of the fifth power supply terminal V5 is a low-level signal.

[0295] An example structure of the shift register is shown in FIG. 18. It is easy for those skilled in the art to understand that the implementation of the shift register is not limited to this.

[0296] Figure 19 is an equivalent circuit diagram of a shift register according to an example embodiment. As shown in Figure 19, the at least one power signal terminal includes a fourth power terminal V4 and a fifth power terminal V5, the at least one output signal terminal includes a signal output terminal OUT, the control sub-circuit includes a third transistor T3, a fifth transistor T5, a sixth transistor T6 and an eighth transistor T8, and the output sub-circuit includes a first transistor T1, a second transistor T2, a fourth transistor T4, a first capacitor C1 and a second capacitor C2.

[0297] In an example embodiment, as shown in Figure 19, the control electrode of the first transistor T1 is electrically connected to the first node N1, the first electrode of the first transistor T1 is electrically connected to the fourth power terminal V4, and the second electrode of the first transistor T1 is electrically connected to the signal output terminal OUT; the control electrode of the second transistor T2 is electrically connected to the eighth node N8, the first electrode of the second transistor T2 is electrically connected to the signal output terminal OUT, and the second electrode of the second transistor T2 is electrically connected to the fifth power terminal V5; the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CLK1, the first electrode of the third transistor T3 is electrically connected to the signal input terminal IN, and the second electrode of the third transistor T3 is electrically connected to the second node N2; the control electrode of the fourth transistor T4 is electrically connected to the fifth power terminal V5, the first electrode of the fourth transistor T4 is electrically connected to the second node N2, and the second electrode of the fourth transistor T4 is electrically connected to the eighth node N8; the fifth transistor T5 is a double-gate transistor and includes a first control electrode and a second control electrode, the first control electrode of the fifth transistor T5 is electrically connected to the signal input terminal IN, the second control electrode of the fifth transistor T5 is electrically connected to the third power terminal V3, the first electrode of the fifth transistor T5 is electrically connected to the second power terminal V2, and the second electrode of the fifth transistor T5 is electrically connected to the fourth node N4; the control electrode of the sixth transistor T6 is electrically connected to the signal input terminal IN, the first electrode of the sixth transistor T6 is electrically connected to the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected to the first power terminal V1; the control electrode of the eighth transistor T8 is electrically connected to the first clock signal terminal CLK1, the first electrode of the eighth transistor T8 is electrically connected to the fourth node N4, and the second electrode of the eighth transistor T8 is electrically connected to the first node N1; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected to the eighth node N8, and the second plate C12 of the first capacitor is electrically connected to the signal output terminal OUT; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate of the second capacitor is electrically connected to the first node N1, and the second plate of the second capacitor is electrically connected to the fourth power terminal V4.

[0298] In an example embodiment, as shown in FIG. 18, the fifth transistor T5 is an N-type transistor, and the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the sixth transistor T6, and the eighth transistor T8 are P-type transistors.

[0299] In an example embodiment, the signal of the first power terminal V1 is a high-level signal, the signal of the second power terminal V2 is a low-level signal, and the signal of the third power terminal V3 is a low-level signal.

[0300] In an example embodiment, the voltage value of the third power terminal V3 is less than or equal to the voltage value of the second power terminal V2.

[0301] In an example embodiment, the signal of the fourth power terminal V4 is a high-level signal, and the signal of the fifth power terminal V5 is a low-level signal.

[0302] In an example embodiment, the fourth power terminal V4 and the first power terminal V1 can be the same signal terminal, and the fifth power terminal V5 and the second power terminal V2 can be the same signal terminal.

[0303] An example structure of the shift register is shown in FIG. 19. It is easy for those skilled in the art to understand that the implementation of the shift register is not limited to this.

[0304] FIG. 20A is an equivalent circuit diagram of the shift register provided in an example embodiment. As shown in FIG. 20A, the at least one power signal terminal includes a fourth power terminal V4, a fifth power terminal V5, a sixth power terminal V6, and an eighth power terminal V8, the at least one output signal terminal includes a signal output terminal OUT and a cascade output terminal CR, the control sub-circuit includes a third transistor T3, a fifth transistor T5, a sixth transistor T6, and an eighth transistor T8, and the output sub-circuit includes a first transistor T1, a second transistor T2, a fourth transistor T4, a twelfth transistor T12, a thirteenth transistor T13, a first capacitor C1, and a second capacitor C2.

[0305] In an example embodiment, as shown in FIG. 20A, the control electrode of the first transistor T1 is electrically connected with the first node N1, the first electrode of the first transistor T1 is electrically connected with the fourth power supply end V4, and the second electrode of the first transistor T1 is electrically connected with the cascade output end CR; the control electrode of the second transistor T2 is electrically connected with the eighth node N8, the first electrode of the second transistor T2 is electrically connected with the cascade output end CR, and the second electrode of the second transistor T2 is electrically connected with the fifth power supply end V5; the control electrode of the third transistor T3 is electrically connected with the first clock signal end CLK1, the first electrode of the third transistor T3 is electrically connected with the signal input end IN, and the second electrode of the third transistor T3 is electrically connected with the second node N2; the control electrode of the fourth transistor T4 is electrically connected with the fifth power supply end V5, the first electrode of the fourth transistor T4 is electrically connected with the second node N2, and the second electrode of the fourth transistor T4 is electrically connected with the eighth node N8; the control electrode of the fifth transistor T5 is electrically connected with the signal input end IN, the first electrode of the fifth transistor T5 is electrically connected with the second power supply end V2, and the second electrode of the fifth transistor T5 is electrically connected with the fourth node N4; the control electrode of the sixth transistor T6 is electrically connected with the signal input end IN, the first electrode of the sixth transistor T6 is electrically connected with the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected with the first power supply end V1; the control electrode of the eighth transistor T8 is electrically connected with the first clock signal end CLK1, the first electrode of the eighth transistor T8 is electrically connected with the fourth node N4, and the second electrode of the eighth transistor T8 is electrically connected with the first node N1; the control electrode of the twelfth transistor T12 is electrically connected with the first node N1, the first electrode of the twelfth transistor T12 is electrically connected with the sixth power supply end V6, and the second electrode of the twelfth transistor T12 is electrically connected with the signal output end OUT; the control electrode of the thirteenth transistor T13 is electrically connected with the eighth node N8, the first electrode of the thirteenth transistor T13 is electrically connected with the signal output end OUT, and the second electrode of the thirteenth transistor T13 is electrically connected with the eighth power supply end V8; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected with the eighth node N8, and the second plate C12 of the first capacitor is electrically connected with the cascade output end CR; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected with the first node N1, and the second plate C22 of the second capacitor is electrically connected with the fourth power supply end V4.

[0306] In an example embodiment, as shown in FIG. 20A, the fifth transistor is an N-type transistor, and the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the sixth transistor T6, the eighth transistor T8, the twelfth transistor T12, and the thirteenth transistor T13 are P-type transistors.

[0307] In an example embodiment, the signal of the first power supply end V1 is a high-level signal, and the signal of the second power supply end V2 is a low-level signal.

[0308] In an example embodiment, the signal of the fourth power supply terminal V4 is a high level signal, the signal of the fifth power supply terminal V5 is a low level signal, the signal of the sixth power supply terminal V6 is a high level signal, and the signal of the eighth power supply terminal V8 is a low level signal.

[0309] In an example embodiment, the fourth power supply terminal V4 and the first power supply terminal V1 can be the same signal terminal, and the fifth power supply terminal V5 and the second power supply terminal V2 can be the same signal terminal.

[0310] An example structure of the shift register is shown in FIG. 20A. It is easy for those skilled in the art to understand that the implementation of the shift register is not limited to this.

[0311] FIG. 20B is an equivalent circuit diagram of the shift register provided in an example embodiment. As shown in FIG. 20B, the at least one power supply signal terminal includes a fourth power supply terminal V4, a fifth power supply terminal V5, a sixth power supply terminal V6, and an eighth power supply terminal V8, the at least one output signal terminal includes a signal output terminal OUT and a cascade output terminal CR, the control sub-circuit includes a third transistor T3, a fifth transistor T5, a sixth transistor T6, and an eighth transistor T8, and the output sub-circuit includes a first transistor T1, a second transistor T2, a fourth transistor T4, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a first capacitor C1, a second capacitor C2, and a fourth capacitor C4.

[0312] In an example embodiment, as shown in FIG. 20B, the control electrode of the first transistor T1 is electrically connected with the first node N1, the first electrode of the first transistor T1 is electrically connected with the fourth power supply end V4, and the second electrode of the first transistor T1 is electrically connected with the cascade output end CR; the control electrode of the second transistor T2 is electrically connected with the eighth node N8, the first electrode of the second transistor T2 is electrically connected with the cascade output end CR, and the second electrode of the second transistor T2 is electrically connected with the fifth power supply end V5; the control electrode of the third transistor T3 is electrically connected with the first clock signal end CLK1, the first electrode of the third transistor T3 is electrically connected with the signal input end IN, and the second electrode of the third transistor T3 is electrically connected with the second node N2; the control electrode of the fourth transistor T4 is electrically connected with the fifth power supply end V5, the first electrode of the fourth transistor T4 is electrically connected with the second node N2, and the second electrode of the fourth transistor T4 is electrically connected with the eighth node N8; the control electrode of the fifth transistor T5 is electrically connected with the signal input end IN, the first electrode of the fifth transistor T5 is electrically connected with the second power supply end V2, and the second electrode of the fifth transistor T5 is electrically connected with the fourth node N4; the control electrode of the sixth transistor T6 is electrically connected with the signal input end IN, the first electrode of the sixth transistor T6 is electrically connected with the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected with the first power supply end V1; the control electrode of the eighth transistor T8 is electrically connected with the first clock signal end CLK1, the first electrode of the eighth transistor T8 is electrically connected with the fourth node N4, and the second electrode of the eighth transistor T8 is electrically connected with the first node N1; the control electrode of the twelfth transistor T12 is electrically connected with the ninth node N9, the first electrode of the twelfth transistor T12 is electrically connected with the sixth power supply end V6, and the second electrode of the twelfth transistor T12 is electrically connected with the signal output end OUT; the control electrode of the thirteenth transistor T13 is electrically connected with the second node N2, the first electrode of the thirteenth transistor T13 is electrically connected with the signal output end OUT, and the second electrode of the thirteenth transistor T13 is electrically connected with the eighth power supply end V8; the control electrode of the fourteenth transistor T14 is electrically connected with the fifth power supply end V5, the first electrode of the fourteenth transistor T14 is electrically connected with the first node N1, and the second electrode of the fourteenth transistor T14 is electrically connected with the ninth node N9; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected with the eighth node N8, and the second plate C12 of the first capacitor is electrically connected with the cascade output end CR; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected with the first node N1, and the second plate C22 of the second capacitor is electrically connected with the fourth power supply end V4; the fourth capacitor C4 includes a first plate C41 and a second plate C42, the first plate C41 of the fourth capacitor is electrically connected with the ninth node N9, and the second plate C42 of the fourth capacitor is electrically connected with the signal output end OUT.

[0313] In an example embodiment, as shown in FIG. 20B, the fifth transistor is an N-type transistor, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the sixth transistor T6, the eighth transistor T8, the twelfth transistor T12, the thirteenth transistor T13 and the fourteenth transistor T14 are P-type transistors.

[0314] In an example embodiment, the signal of the first power supply end V1 is a high level signal, and the signal of the second power supply end V2 is a low level signal.

[0315] In an example embodiment, the signal of the fourth power supply end V4 is a high level signal, the signal of the fifth power supply end V5 is a low level signal, the signal of the sixth power supply end V6 is a high level signal, and the signal of the eighth power supply end V8 is a low level signal.

[0316] In an example embodiment, the fourth power supply end V4 and the first power supply end V1 can be the same signal end, and the fifth power supply end V5 and the second power supply end V2 can be the same signal end.

[0317] An example structure of the shift register is shown in FIG. 20B. It is easy for those skilled in the art to understand that the implementation of the shift register is not limited to this.

[0318] FIG. 21A is an equivalent circuit diagram of a shift register provided by an example embodiment. As shown in FIG. 21A, at least one power supply signal end includes: a fourth power supply end V4, a fifth power supply end V5, a sixth power supply end V6 and an eighth power supply end V8, at least one output signal end includes: a signal output end OUT and a cascade output end CR, a control sub-circuit includes: a third transistor T3, a fifth transistor T5, a sixth transistor T6 and an eighth transistor T8, and an output sub-circuit includes: a first transistor T1, a second transistor T2, a fourth transistor T4, a twelfth transistor T12, a thirteenth transistor T13, a first capacitor C1 and a second capacitor C2.

[0319] In an example embodiment, as shown in FIG. 21A, the control electrode of the first transistor T1 is electrically connected with the first node N1, the first electrode of the first transistor T1 is electrically connected with the fourth power supply end V4, and the second electrode of the first transistor T1 is electrically connected with the cascade output end CR; the control electrode of the second transistor T2 is electrically connected with the eighth node N8, the first electrode of the second transistor T2 is electrically connected with the cascade output end CR, and the second electrode of the second transistor T2 is electrically connected with the fifth power supply end V5; the control electrode of the third transistor T3 is electrically connected with the first clock signal end CLK1, the first electrode of the third transistor T3 is electrically connected with the signal input end IN, and the second electrode of the third transistor T3 is electrically connected with the second node N2; the control electrode of the fourth transistor T4 is electrically connected with the fifth power supply end V5, the first electrode of the fourth transistor T4 is electrically connected with the second node N2, and the second electrode of the fourth transistor T4 is electrically connected with the eighth node N8; the fifth transistor T5 is a double-gate transistor, the first control electrode of the fifth transistor T5 is electrically connected with the signal input end IN, the second control electrode of the fifth transistor T5 is electrically connected with the third power supply end V3, the first electrode of the fifth transistor T5 is electrically connected with the second power supply end V2, and the second electrode of the fifth transistor T5 is electrically connected with the fourth node N4; the control electrode of the sixth transistor T6 is electrically connected with the signal input end IN, the first electrode of the sixth transistor T6 is electrically connected with the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected with the first power supply end V1; the control electrode of the eighth transistor T8 is electrically connected with the first clock signal end CLK1, the first electrode of the eighth transistor T8 is electrically connected with the fourth node N4, and the second electrode of the eighth transistor T8 is electrically connected with the first node N1; the control electrode of the twelfth transistor T12 is electrically connected with the first node N1, the first electrode of the twelfth transistor T12 is electrically connected with the sixth power supply end V6, and the second electrode of the twelfth transistor T12 is electrically connected with the signal output end OUT; the control electrode of the thirteenth transistor T13 is electrically connected with the eighth node N8, the first electrode of the thirteenth transistor T13 is electrically connected with the signal output end OUT, and the second electrode of the thirteenth transistor T13 is electrically connected with the eighth power supply end V8; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected with the eighth node N8, and the second plate C12 of the first capacitor is electrically connected with the cascade output end CR; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected with the first node N1, and the second plate C22 of the second capacitor is electrically connected with the fourth power supply end V4.

[0320] In an example embodiment, as shown in FIG. 21A, the fifth transistor is an N-type transistor, and the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the sixth transistor T6, the eighth transistor T8, the twelfth transistor T12, and the thirteenth transistor T13 are P-type transistors.

[0321] In an example embodiment, the signal of the first power terminal V1 is a high level signal, the signal of the second power terminal V2 is a low level signal, and the signal of the third power terminal V3 is a low level signal.

[0322] In an example embodiment, the voltage of the third power terminal V3 is less than or equal to the voltage of the second power terminal V2.

[0323] In an example embodiment, the signal of the fourth power terminal V4 is a high level signal, the signal of the fifth power terminal V5 is a low level signal, the signal of the sixth power terminal V6 is a high level signal, and the signal of the eighth power terminal V8 is a low level signal.

[0324] In an example embodiment, the fourth power terminal V4 and the first power terminal V1 can be the same signal terminal, and the fifth power terminal V5 and the second power terminal V2 can be the same signal terminal.

[0325] An example structure of the shift register is shown in FIG. 21A. It is easy for those skilled in the art to understand that the implementation of the shift register is not limited to this.

[0326] FIG. 21B is an equivalent circuit diagram of the shift register provided in an example embodiment. As shown in FIG. 21B, the at least one power signal terminal includes a fourth power terminal V4, a fifth power terminal V5, a sixth power terminal V6, and an eighth power terminal V8, the at least one output signal terminal includes a signal output terminal OUT and a cascade output terminal CR, the control sub-circuit includes a third transistor T3, a fifth transistor T5, a sixth transistor T6, and an eighth transistor T8, and the output sub-circuit includes a first transistor T1, a second transistor T2, a fourth transistor T4, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a first capacitor C1, a second capacitor C2, and a fourth capacitor C4.

[0327] In an example embodiment, as shown in FIG. 21B, the control electrode of the first transistor T1 is electrically connected with the first node N1, the first electrode of the first transistor T1 is electrically connected with the fourth power supply end V4, and the second electrode of the first transistor T1 is electrically connected with the cascade output end CR; the control electrode of the second transistor T2 is electrically connected with the eighth node N8, the first electrode of the second transistor T2 is electrically connected with the cascade output end CR, and the second electrode of the second transistor T2 is electrically connected with the fifth power supply end V5; the control electrode of the third transistor T3 is electrically connected with the first clock signal end CLK1, the first electrode of the third transistor T3 is electrically connected with the signal input end IN, and the second electrode of the third transistor T3 is electrically connected with the second node N2; the control electrode of the fourth transistor T4 is electrically connected with the fifth power supply end V5, the first electrode of the fourth transistor T4 is electrically connected with the second node N2, and the second electrode of the fourth transistor T4 is electrically connected with the eighth node N8; the fifth transistor T5 is a double-gate transistor, the first control electrode of the fifth transistor T5 is electrically connected with the signal input end IN, the second control electrode of the fifth transistor T5 is electrically connected with the third power supply end V3, the first electrode of the fifth transistor T5 is electrically connected with the second power supply end V2, and the second electrode of the fifth transistor T5 is electrically connected with the fourth node N4; the control electrode of the sixth transistor T6 is electrically connected with the signal input end IN, the first electrode of the sixth transistor T6 is electrically connected with the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected with the first power supply end V1; the control electrode of the eighth transistor T8 is electrically connected with the first clock signal end CLK1, the first electrode of the eighth transistor T8 is electrically connected with the fourth node N4, and the second electrode of the eighth transistor T8 is electrically connected with the first node N1; the control electrode of the twelfth transistor T12 is electrically connected with the ninth node N9, the first electrode of the twelfth transistor T12 is electrically connected with the sixth power supply end V6, and the second electrode of the twelfth transistor T12 is electrically connected with the signal output end OUT; the control electrode of the thirteenth transistor T13 is electrically connected with the second node N2, the first electrode of the thirteenth transistor T13 is electrically connected with the signal output end OUT, and the second electrode of the thirteenth transistor T13 is electrically connected with the eighth power supply end V8; the control electrode of the fourteenth transistor T14 is electrically connected with the fifth power supply end V5, the first electrode of the fourteenth transistor T14 is electrically connected with the first node N1, and the second electrode of the fourteenth transistor T14 is electrically connected with the ninth node N9; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected with the eighth node N8, and the second plate C12 of the first capacitor is electrically connected with the cascade output end CR; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected with the first node N1, and the second plate C22 of the second capacitor is electrically connected with the fourth power supply end V4; the fourth capacitor C4 includes a first plate C41 and a second plate C42, the first plate C41 of the fourth capacitor is electrically connected with the ninth node N9, and the second plate C42 of the fourth capacitor is electrically connected with the signal output end OUT.

[0328] In an example embodiment, as shown in FIG. 21B, the fifth transistor is an N-type transistor, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the sixth transistor T6, the eighth transistor T8, the twelfth transistor T12, the thirteenth transistor T13 and the fourteenth transistor T14 are P-type transistors.

[0329] In an example embodiment, the signal of the first power supply end V1 is a high-level signal, the signal of the second power supply end V2 is a low-level signal, and the signal of the third power supply end V3 is a low-level signal.

[0330] In an example embodiment, the voltage value of the third power supply end V3 is less than or equal to the voltage value of the second power supply end V2.

[0331] In an example embodiment, the signal of the fourth power supply end V4 is a high-level signal, the signal of the fifth power supply end V5 is a low-level signal, the signal of the sixth power supply end V6 is a high-level signal, and the signal of the eighth power supply end V8 is a low-level signal.

[0332] In an example embodiment, the fourth power supply end V4 and the first power supply end V1 can be the same signal end, and the fifth power supply end V5 and the second power supply end V2 can be the same signal end.

[0333] An example structure of the shift register is shown in FIG. 21B. It is easy for those skilled in the art to understand that the implementation of the shift register is not limited to this.

[0334] FIG. 22 is an equivalent circuit diagram of a shift register provided by an example embodiment. As shown in FIG. 22, at least one power supply signal end includes a fourth power supply end V4 and a fifth power supply end V5, at least one output signal end includes a signal output end OUT, a control sub-circuit includes a third transistor T3, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and a third capacitor C3, and an output sub-circuit includes a first transistor T1, a second transistor T2, a fourth transistor T4, a first capacitor C1 and a second capacitor C2.

[0335] In an example embodiment, as shown in FIG. 22, the control electrode of the first transistor T1 is electrically connected with the first node N1, the first electrode of the first transistor T1 is electrically connected with the fourth power supply end V4, and the second electrode of the first transistor T1 is electrically connected with the signal output end OUT; the control electrode of the second transistor T2 is electrically connected with the eighth node N8, the first electrode of the second transistor T2 is electrically connected with the signal output end OUT, and the second electrode of the second transistor T2 is electrically connected with the fifth power supply end V5; the control electrode of the third transistor T3 is electrically connected with the first clock signal end CLK1, the first electrode of the third transistor T3 is electrically connected with the signal input end IN, and the second electrode of the third transistor T3 is electrically connected with the second node N2; the control electrode of the fourth transistor T4 is electrically connected with the fifth power supply end V5, the first electrode of the fourth transistor T4 is electrically connected with the second node N2, and the second electrode of the fourth transistor T4 is electrically connected with the eighth node N8; the control electrode of the fifth transistor T5 is electrically connected with the third node N3, the first electrode of the fifth transistor T5 is electrically connected with the second power supply end V2, and the second electrode of the fifth transistor T5 is electrically connected with the first node N1; the control electrode of the sixth transistor T6 is electrically connected with the second node N2, the first electrode of the sixth transistor T6 is electrically connected with the first node N1, and the second electrode of the sixth transistor T6 is electrically connected with the first power supply end V1; the control electrode of the seventh transistor T7 is electrically connected with the signal input end IN, the first electrode of the seventh transistor T7 is electrically connected with the third node N3, and the second electrode of the seventh transistor T7 is electrically connected with the first power supply end V1; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected with the eighth node N8, and the second plate C12 of the first capacitor is electrically connected with the signal output end OUT; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected with the first node N1, and the second plate C22 of the second capacitor is electrically connected with the fourth power supply end V4; the third capacitor C3 includes a first plate C31 and a second plate C32, the first plate C31 of the third capacitor is electrically connected with the first clock signal end CLK1, and the second plate C32 of the third capacitor is electrically connected with the third node N3.

[0336] In an example embodiment, as shown in FIG. 22, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are P-type transistors.

[0337] In an example embodiment, the signal of the first power supply end V1 is a high-level signal, and the signal of the second power supply end V2 is a low-level signal.

[0338] In an example embodiment, the signal of the fourth power supply end V4 is a high-level signal, and the signal of the fifth power supply end V5 is a low-level signal.

[0339] In an example embodiment, the fourth power supply terminal V4 and the first power supply terminal V1 can be the same signal terminal, and the fifth power supply terminal V5 and the second power supply terminal V2 can be the same signal terminal.

[0340] An example structure of the shift register is shown in FIG. 22. It is easily understood by those skilled in the art that the implementation of the shift register is not limited to this.

[0341] FIG. 23A is an equivalent circuit diagram of the shift register provided in an example embodiment. As shown in FIG. 23A, the at least one power supply signal terminal includes a fourth power supply terminal V4, a fifth power supply terminal V5, a sixth power supply terminal V6, and an eighth power supply terminal V8, the at least one output signal terminal includes a signal output terminal OUT and a cascade output terminal CR, the control sub-circuit includes a third transistor T3, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a third capacitor C3, and the output sub-circuit includes a first transistor T1, a second transistor T2, a fourth transistor T4, a twelfth transistor T12, a thirteenth transistor T13, a first capacitor C1, and a second capacitor C2.

[0342] In an example embodiment, as shown in FIG. 23A, the control electrode of the first transistor T1 is electrically connected with the first node N1, the first electrode of the first transistor T1 is electrically connected with the fourth power supply end V4, and the second electrode of the first transistor T1 is electrically connected with the cascade output end CR; the control electrode of the second transistor T2 is electrically connected with the eighth node N8, the first electrode of the second transistor T2 is electrically connected with the cascade output end CR, and the second electrode of the second transistor T2 is electrically connected with the fifth power supply end V5; the control electrode of the third transistor T3 is electrically connected with the first clock signal end CLK1, the first electrode of the third transistor T3 is electrically connected with the signal input end IN, and the second electrode of the third transistor T3 is electrically connected with the second node N2; the control electrode of the fourth transistor T4 is electrically connected with the fifth power supply end V5, the first electrode of the fourth transistor T4 is electrically connected with the second node N2, and the second electrode of the fourth transistor T4 is electrically connected with the eighth node N8; the control electrode of the fifth transistor T5 is electrically connected with the third node N3, the first electrode of the fifth transistor T5 is electrically connected with the second power supply end V2, and the second electrode of the fifth transistor T5 is electrically connected with the first node N1; the control electrode of the sixth transistor T6 is electrically connected with the second node N2, the first electrode of the sixth transistor T6 is electrically connected with the first node N1, and the second electrode of the sixth transistor T6 is electrically connected with the first power supply end V1; the control electrode of the seventh transistor T7 is electrically connected with the signal input end IN, the first electrode of the seventh transistor T7 is electrically connected with the third node N3, and the second electrode of the seventh transistor T7 is electrically connected with the first power supply end V1; the control electrode of the twelfth transistor T12 is electrically connected with the first node N1, the first electrode of the twelfth transistor T12 is electrically connected with the sixth power supply end V6, and the second electrode of the twelfth transistor T12 is electrically connected with the signal output end OUT; the control electrode of the thirteenth transistor T13 is electrically connected with the eighth node N8, the first electrode of the thirteenth transistor T13 is electrically connected with the signal output end OUT, and the second electrode of the thirteenth transistor T13 is electrically connected with the eighth power supply end V8; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected with the eighth node N8, and the second plate C12 of the first capacitor is electrically connected with the cascade output end CR; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected with the first node N1, and the second plate C22 of the second capacitor is electrically connected with the fourth power supply end V4; the third capacitor C3 includes a first plate C31 and a second plate C32, the first plate C31 of the third capacitor is electrically connected with the first clock signal end CLK1, and the second plate C32 of the third capacitor is electrically connected with the third node N3.

[0343] In an example embodiment, as shown in FIG. 23A, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the twelfth transistor T12, and the thirteenth transistor T13 are P-type transistors.

[0344] In an example embodiment, the signal of the first power terminal V1 is a high level signal, and the signal of the second power terminal V2 is a low level signal.

[0345] In an example embodiment, the signal of the fourth power terminal V4 is a high level signal, the signal of the fifth power terminal V5 is a low level signal, the signal of the sixth power terminal V6 is a high level signal, and the signal of the eighth power terminal V8 is a low level signal.

[0346] In an example embodiment, the fourth power terminal V4 and the first power terminal V1 can be the same signal terminal, and the fifth power terminal V5 and the second power terminal V2 can be the same signal terminal.

[0347] An example structure of the shift register is shown in FIG. 23A. It is easy for those skilled in the art to understand that the implementation of the shift register is not limited to this.

[0348] FIG. 23B is an equivalent circuit diagram of the shift register provided in an example embodiment. As shown in FIG. 23B, the at least one power signal terminal includes a fourth power terminal V4, a fifth power terminal V5, a sixth power terminal V6, and an eighth power terminal V8, the at least one output signal terminal includes a signal output terminal OUT and a cascade output terminal CR, the control sub-circuit includes a third transistor T3, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a third capacitor C3, and the output sub-circuit includes a first transistor T1, a second transistor T2, a fourth transistor T4, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a first capacitor C1, a second capacitor C2, and a fourth capacitor C4.

[0349] In an example embodiment, as shown in FIG. 23B, the control electrode of the first transistor T1 is electrically connected with the first node N1, the first electrode of the first transistor T1 is electrically connected with the fourth power supply end V4, and the second electrode of the first transistor T1 is electrically connected with the cascade output end CR; the control electrode of the second transistor T2 is electrically connected with the eighth node N8, the first electrode of the second transistor T2 is electrically connected with the cascade output end CR, and the second electrode of the second transistor T2 is electrically connected with the fifth power supply end V5; the control electrode of the third transistor T3 is electrically connected with the first clock signal end CLK1, the first electrode of the third transistor T3 is electrically connected with the signal input end IN, and the second electrode of the third transistor T3 is electrically connected with the second node N2; the control electrode of the fourth transistor T4 is electrically connected with the fifth power supply end V5, the first electrode of the fourth transistor T4 is electrically connected with the second node N2, and the second electrode of the fourth transistor T4 is electrically connected with the eighth node N8; the control electrode of the fifth transistor T5 is electrically connected with the third node N3, the first electrode of the fifth transistor T5 is electrically connected with the second power supply end V2, and the second electrode of the fifth transistor T5 is electrically connected with the first node N1; the control electrode of the sixth transistor T6 is electrically connected with the second node N2, the first electrode of the sixth transistor T6 is electrically connected with the first node N1, and the second electrode of the sixth transistor T6 is electrically connected with the first power supply end V1; the control electrode of the seventh transistor T7 is electrically connected with the signal input end IN, the first electrode of the seventh transistor T7 is electrically connected with the third node N3, and the second electrode of the seventh transistor T7 is electrically connected with the first power supply end V1; the control electrode of the twelfth transistor T12 is electrically connected with the ninth node N9, the first electrode of the twelfth transistor T12 is electrically connected with the sixth power supply end V6, and the second electrode of the twelfth transistor T12 is electrically connected with the signal output end OUT; the control electrode of the thirteenth transistor T13 is electrically connected with the second node N2, the first electrode of the thirteenth transistor T13 is electrically connected with the signal output end OUT, and the second electrode of the thirteenth transistor T13 is electrically connected with the eighth power supply end V8; the control electrode of the fourteenth transistor T14 is electrically connected with the fifth power supply end V5, the first electrode of the fourteenth transistor T14 is electrically connected with the first node N1, and the second electrode of the fourteenth transistor T14 is electrically connected with the ninth node N9; the first capacitor C1 comprises a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected with the eighth node N8, and the second plate C12 of the first capacitor is electrically connected with the cascade output end CR; the second capacitor C2 comprises a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected with the first node N1, and the second plate C22 of the second capacitor is electrically connected with the fourth power supply end V4; the third capacitor C3 comprises a first plate C31 and a second plate C32, the first plate C31 of the third capacitor is electrically connected with the first clock signal end CLK1, and the second plate C32 of the third capacitor is electrically connected with the third node N3.The fourth capacitor C4 includes a first plate C41 and a second plate C42. The first plate C41 of the fourth capacitor is electrically connected to the ninth node N9. The second plate C42 of the fourth capacitor is electrically connected to the signal output terminal OUT.

[0350] In an example embodiment, as shown in FIG. 23B, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the twelfth transistor T12, the thirteenth transistor T13, and the fourteenth transistor T14 are P-type transistors.

[0351] In an example embodiment, the signal of the first power supply terminal V1 is a high-level signal, and the signal of the second power supply terminal V2 is a low-level signal.

[0352] In an example embodiment, the signal of the fourth power supply terminal V4 is a high-level signal, the signal of the fifth power supply terminal V5 is a low-level signal, the signal of the sixth power supply terminal V6 is a high-level signal, and the signal of the eighth power supply terminal V8 is a low-level signal.

[0353] In an example embodiment, the fourth power supply terminal V4 and the first power supply terminal V1 can be the same signal terminal, and the fifth power supply terminal V5 and the second power supply terminal V2 can be the same signal terminal.

[0354] An example structure of the shift register is shown in FIG. 23B. It is easily understood by those skilled in the art that the implementation of the shift register is not limited to this.

[0355] FIG. 24 is an equivalent circuit diagram of a reset sub-circuit provided by an example embodiment. As shown in FIG. 24, the reset sub-circuit includes a fifteenth transistor T15.

[0356] In an example embodiment, as shown in FIG. 24, the control electrode of the fifteenth transistor T15 is electrically connected to the reset signal terminal RST. The first electrode of the fifteenth transistor T15 is electrically connected to the seventh power supply terminal V7. The second electrode of the fifteenth transistor T15 is electrically connected to the first node N1.

[0357] In an example embodiment, the signal of the seventh power supply terminal V7 is a low-level signal.

[0358] An example structure of the reset sub-circuit is shown in FIG. 24. It is easily understood by those skilled in the art that the implementation of the reset sub-circuit is not limited to this.

[0359] The disclosure embodiments also provide a gate drive circuit, including: a plurality of cascaded shift registers, at least one output signal terminal of at least one level of the shift registers includes: a signal output terminal;

[0360] The signal output end of the i-th stage shift register is electrically connected with the signal input end of the i+L-th stage shift register, 1≤i≤M-L, M is the total stage number of the shift register, M≥1, and L is a positive integer greater than or equal to 1.

[0361] The shift register is the shift register provided by any one of the foregoing embodiments, and has similar implementation principles and implementation effects, which will not be described here again.

[0362] The display device provided by the embodiment of the present disclosure also includes a display area and a non-display area, the display area is provided with pixel driving circuits arranged in an array, the non-display area is provided with a gate driving circuit, the pixel driving circuit includes at least one light-emitting control transistor, and at least one light-emitting control transistor in at least one row of pixel driving circuits is electrically connected with at least one stage of shift registers in the gate driving circuit.

[0363] The gate driving circuit is the gate driving circuit provided by any one of the foregoing embodiments, and has similar implementation principles and implementation effects, which will not be described here again.

[0364] FIG. 25 is a structural circuit diagram of a display device provided by an exemplary embodiment, as shown in FIG. 25, the control sub-circuit is electrically connected with the signal input end IN and the first clock signal end CLK1 respectively, and the display device further includes an initial signal line STV, a first clock signal line CK1 and a second clock signal line CK2; the signal input end IN of at least one stage of shift registers is electrically connected with the initial signal line STV, the first clock signal end CLK1 is electrically connected with one of the first clock signal line CK1 and the second clock signal line CK2, and the signal lines connected with the first clock signal ends CLK1 of adjacent shift registers are different.

[0365] FIG. 26 is an output timing diagram of a multi-stage shift register provided by an exemplary embodiment, as shown in FIG. 26, the signal input end IN of the first stage shift register is electrically connected with the initial signal line STV, the signal output end of the i-th stage shift register is electrically connected with the signal input end of the i+1-th stage shift register, the first clock signal end CLK1 of at least one stage of shift registers is electrically connected with one of the first clock signal line CK1 and the second clock signal line CK2, and the timing diagram shown in FIG. 26 can be output, so as to realize the shift of the output signal.

[0366] Fig. 27 is a structural circuit diagram of a display device according to an example embodiment. As shown in Fig. 27, the control sub-circuit is electrically connected to the signal input end IN and the first clock signal end CLK1 respectively. The display device further comprises an initial signal line STV, a first clock signal line CK1, a second clock signal line CK2, a third clock signal line CK3, and a fourth clock signal line CK4. The signal input end IN of the at least one stage of shift register is electrically connected to the initial signal line STV. The first clock signal end CLK1 of the 4M-3 stage of shift register is electrically connected to the first clock signal line CK1. The first clock signal end CLK1 of the 4M-2 stage of shift register is electrically connected to the second clock signal line CK2. The first clock signal end CLK1 of the 4M-1 stage of shift register is electrically connected to the third clock signal line CK3. The first clock signal end CLK1 of the 4M stage of shift register is electrically connected to the fourth clock signal line CK4. Wherein, M is the total number of stages of shift register, and M≥1.

[0367] Fig. 28 is an output timing diagram of a multi-stage shift register according to an example embodiment. As shown in Fig. 28, the signal input end IN of the first stage of shift register is electrically connected to the initial signal line STV. The signal output end of the i stage of shift register is electrically connected to the signal input end of the i+2 stage of shift register. The first clock signal end CLK1 of the 4M-3 stage of shift register is electrically connected to the first clock signal line CK1. The first clock signal end CLK1 of the 4M-2 stage of shift register is electrically connected to the second clock signal line CK2. The first clock signal end CLK1 of the 4M-1 stage of shift register is electrically connected to the third clock signal line CK3. The first clock signal end CLK1 of the 4M stage of shift register is electrically connected to the fourth clock signal line CK4. The timing diagram shown in Fig. 28 can be output, and the shift of the output signal is realized.

[0368] The disclosure further provides a driving method of a shift register configured to drive the shift register. The driving method of the shift register can comprise:

[0369] The control sub-circuit provides signals to the first node or the second node under the control of signals at the signal input end and the first clock signal end.

[0370] The output sub-circuit provides signals to the at least one output signal end under the control of signals at the first node, the second node, and the at least one power signal end.

[0371] The duration of the valid level signal provided by the output sub-circuit is greater than the period of the signal provided by the first clock signal end.

[0372] The shift register is the shift register provided by any one of the preceding example embodiments, and has similar principles and effects, which will not be described here again.

[0373] The drawings in the present disclosure only involve the structures related to the embodiments of the present disclosure, and other structures can be referred to the general design.

[0374] For clarity, the thickness and dimensions of the layers or microstructures are exaggerated in the drawings used to describe the embodiments of the present disclosure. It can be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "under" another element, it can be "directly" on or under the other element, or an intervening element can also be present.

[0375] Although the embodiments disclosed in the present disclosure are as above, the content described is only the embodiments adopted for the convenience of understanding the present disclosure, and is not intended to limit the present disclosure. Any person skilled in the art of the present disclosure can make any modification and change in the form and details without departing from the spirit and scope of the present disclosure, but the patent protection scope of the present disclosure shall be subject to the scope defined by the appended claims.

Claims

1. A shift register comprising: The control sub-circuit and the output sub-circuit; The control sub-circuit is electrically connected with the signal input end, the first clock signal end, the first node and the second node respectively, and is configured to provide a signal to the first node or the second node under the control of signals of the signal input end and the first clock signal end; The output sub-circuit is electrically connected with the first node, the second node, at least one power signal end and at least one output signal end respectively, and is configured to provide a signal to the at least one output signal end under the control of signals of the first node, the second node and the at least one power signal end. The duration of the effective level signal provided by the output sub-circuit is greater than the cycle duration of the signal provided by the first clock signal end.

2. The shift register of claim 1, wherein, The control sub-circuit comprises a first control sub-circuit, and the first control sub-circuit is further electrically connected with the first power end and the second power end. Alternatively, The control sub-circuit comprises a second control sub-circuit, and the second control sub-circuit is further electrically connected with the first power end, the second power end and the third power end.

3. The shift register of claim 2, wherein, The first control sub-circuit comprises a third transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor and a third capacitor. The control electrode of the third transistor is electrically connected with the first clock signal end, the first electrode of the third transistor is electrically connected with the signal input end, and the second electrode of the third transistor is electrically connected with the second node. The control electrode of the fifth transistor is electrically connected with the third node, the first electrode of the fifth transistor is electrically connected with the second power end, and the second electrode of the fifth transistor is electrically connected with the fourth node. The control electrode of the sixth transistor is electrically connected with the signal input end, the first electrode of the sixth transistor is electrically connected with the fourth node, and the second electrode of the sixth transistor is electrically connected with the first power end. The control electrode of the seventh transistor is electrically connected with the signal input end, the first electrode of the seventh transistor is electrically connected with the third node, and the second electrode of the seventh transistor is electrically connected with the first power end. The control electrode of the eighth transistor is electrically connected with the first clock signal end, the first electrode of the eighth transistor is electrically connected with the fourth node, and the second electrode of the eighth transistor is electrically connected with the first node. The third capacitor comprises a first plate and a second plate, the first plate of the third capacitor is electrically connected with the first clock signal end, and the second plate of the third capacitor is electrically connected with the third node.

4. The shift register of claim 2, wherein, The first control sub-circuit comprises a third transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor and a ninth transistor. The control electrode of the third transistor is electrically connected with the first clock signal end, the first electrode of the third transistor is electrically connected with the signal input end, and the second electrode of the third transistor is electrically connected with the second node. The control electrode of the fifth transistor is electrically connected with the fifth node, the first electrode of the fifth transistor is electrically connected with the second power end, and the second electrode of the fifth transistor is electrically connected with the fourth node. The control electrode of the sixth transistor is electrically connected with the signal input end, the first electrode of the sixth transistor is electrically connected with the fourth node, and the second electrode of the sixth transistor is electrically connected with the first power end. The control electrode of the seventh transistor is electrically connected with the signal input end, the first electrode of the seventh transistor is electrically connected with the sixth node, and the second electrode of the seventh transistor is electrically connected with the first power end. The control electrode of the eighth transistor is electrically connected with the first clock signal terminal, the first electrode of the eighth transistor is electrically connected with the fourth node, and the second electrode of the eighth transistor is electrically connected with the first node; The control electrode of the ninth transistor is electrically connected with the first clock signal terminal, the first electrode of the ninth transistor is electrically connected with the fifth node, and the second electrode of the ninth transistor is electrically connected with the sixth node.

5. The shift register of claim 2, wherein, The first control sub-circuit comprises a third transistor, a fifth transistor, a sixth transistor, a seventh transistor and a third capacitor; The control electrode of the third transistor is electrically connected with the first clock signal terminal, the first electrode of the third transistor is electrically connected with the signal input terminal, and the second electrode of the third transistor is electrically connected with the second node; The control electrode of the fifth transistor is electrically connected with the third node, the first electrode of the fifth transistor is electrically connected with the second power supply terminal, and the second electrode of the fifth transistor is electrically connected with the first node; The control electrode of the sixth transistor is electrically connected with the second node, the first electrode of the sixth transistor is electrically connected with the first node, and the second electrode of the sixth transistor is electrically connected with the first power supply terminal; The control electrode of the seventh transistor is electrically connected with the signal input terminal, the first electrode of the seventh transistor is electrically connected with the third node, and the second electrode of the seventh transistor is electrically connected with the first power supply terminal; The third capacitor comprises a first plate and a second plate, the first plate of the third capacitor is electrically connected with the first clock signal terminal, The second plate of the third capacitor is electrically connected with the third node.

6. The shift register of any one of claims 3 to 5, wherein, The fifth transistor is a P-type transistor.

7. The shift register of claim 2, wherein, The second control sub-circuit comprises a third transistor, a fifth transistor, a sixth transistor and an eighth transistor; The control electrode of the third transistor is electrically connected with the first clock signal terminal, the first electrode of the third transistor is electrically connected with the signal input terminal, and the second electrode of the third transistor is electrically connected with the second node; The control electrode of the fifth transistor is electrically connected with the signal input terminal, the first electrode of the fifth transistor is electrically connected with the second power supply terminal, and the second electrode of the fifth transistor is electrically connected with the fourth node; The control electrode of the sixth transistor is electrically connected with the signal input terminal, the first electrode of the sixth transistor is electrically connected with the fourth node, and the second electrode of the sixth transistor is electrically connected with the first power supply terminal; The control electrode of the eighth transistor is electrically connected with the first clock signal terminal, the first electrode of the eighth transistor is electrically connected with the fourth node, and the second electrode of the eighth transistor is electrically connected with the first node.

8. The shift register of claim 2, wherein, The second control sub-circuit comprises a third transistor, a fifth transistor, a sixth transistor and an eighth transistor, the fifth transistor is a double-gate transistor and comprises a first control electrode and a second control electrode; The control electrode of the third transistor is electrically connected with the first clock signal terminal, the first electrode of the third transistor is electrically connected with the signal input terminal, and the second electrode of the third transistor is electrically connected with the second node; The first control electrode of the fifth transistor is electrically connected with the signal input terminal, the second control electrode of the fifth transistor is electrically connected with the third power supply terminal, the first electrode of the fifth transistor is electrically connected with the second power supply terminal, and the second electrode of the fifth transistor is electrically connected with the fourth node; The control electrode of the sixth transistor is electrically connected with the signal input terminal, the first electrode of the sixth transistor is electrically connected with the fourth node, and the second electrode of the sixth transistor is electrically connected with the first power supply terminal; The control electrode of the eighth transistor is electrically connected with the first clock signal terminal, the first electrode of the eighth transistor is electrically connected with the fourth node, and the second electrode of the eighth transistor is electrically connected with the first node.

9. The shift register of claim 8, wherein, The signals of the second power supply terminal and the third power supply terminal are low-level signals, and the voltage value of the third power supply terminal is less than or equal to the voltage value of the second power supply terminal.

10. The shift register of claim 7 or 8, wherein, The fifth transistor is an N-type transistor.

11. The shift register of claim 1, wherein, The control sub-circuit is further electrically connected with the second clock signal terminal and the first power supply terminal, and is configured to provide the signal of the first power supply terminal to the second node under the control of the signals of the first node and the second clock signal terminal.

12. The shift register of claim 11, wherein, The control sub-circuit further comprises a tenth transistor and an eleventh transistor. The control electrode of the tenth transistor is electrically connected with the first node, the first electrode of the tenth transistor is electrically connected with the first power supply terminal, and the second electrode of the tenth transistor is electrically connected with the seventh node; the control electrode of the eleventh transistor is electrically connected with the second clock signal terminal, the first electrode of the eleventh transistor is electrically connected with the seventh node, and the second electrode of the eleventh transistor is electrically connected with the second node. Or, The control electrode of the tenth transistor is electrically connected with the second clock signal terminal, the first electrode of the tenth transistor is electrically connected with the first node, and the second electrode of the tenth transistor is electrically connected with the seventh node; the control electrode of the eleventh transistor is electrically connected with the second node, the first electrode of the eleventh transistor is electrically connected with the seventh node, and the second electrode of the eleventh transistor is electrically connected with the first power supply terminal.

13. The shift register of claim 1, wherein, The at least one power supply signal terminal comprises a fourth power supply terminal and a fifth power supply terminal, and the at least one output signal terminal comprises a signal output terminal. The output sub-circuit is configured to provide the signal of the fourth power supply terminal or the fifth power supply terminal to the signal output terminal under the control of the signals of the first node and the second node.

14. The shift register of claim 13, wherein, The output sub-circuit comprises a first transistor, a second transistor, a fourth transistor, a first capacitor and a second capacitor. The control electrode of the first transistor is electrically connected with the first node, the first electrode of the first transistor is electrically connected with the fourth power supply terminal, and the second electrode of the first transistor is electrically connected with the signal output terminal. The control electrode of the second transistor is electrically connected with the eighth node, the first electrode of the second transistor is electrically connected with the signal output terminal, and the second electrode of the second transistor is electrically connected with the fifth power supply terminal. The control electrode of the fourth transistor is electrically connected with the fifth power supply terminal, the first electrode of the fourth transistor is electrically connected with the second node, and the second electrode of the fourth transistor is electrically connected with the eighth node. The first capacitor comprises a first plate and a second plate, the first plate of the first capacitor is electrically connected with the eighth node, and the second plate of the first capacitor is electrically connected with the signal output terminal. The second capacitor comprises a first plate and a second plate, the first plate of the second capacitor is electrically connected with the first node, and the second plate of the second capacitor is electrically connected with the fourth power supply terminal. The at least one power supply signal terminal comprises a fourth power supply terminal, a fifth power supply terminal, a sixth power supply terminal and an eighth power supply terminal, and the at least one output signal terminal comprises a signal output terminal and a cascade output terminal.

15. The shift register of claim 1, wherein, The output sub-circuit is configured to provide the signal of the sixth power supply terminal or the eighth power supply terminal to the signal output terminal and provide the signal of the fourth power supply terminal or the fifth power supply terminal to the cascade output terminal under the control of the signals of the first node and the second node. ​ 16. The shift register of claim 15, wherein, The output sub-circuit comprises a first transistor, a second transistor, a fourth transistor, a twelfth transistor, a thirteenth transistor, a first capacitor and a second capacitor; The control electrode of the first transistor is electrically connected with the first node, the first electrode of the first transistor is electrically connected with the fourth power supply end, and the second electrode of the first transistor is electrically connected with the cascade output end; The control electrode of the second transistor is electrically connected with the eighth node, the first electrode of the second transistor is electrically connected with the cascade output end, and the second electrode of the second transistor is electrically connected with the fifth power supply end; The control electrode of the fourth transistor is electrically connected with the fifth power supply end, the first electrode of the fourth transistor is electrically connected with the second node, and the second electrode of the fourth transistor is electrically connected with the eighth node; The control electrode of the twelfth transistor is electrically connected with the first node, the first electrode of the twelfth transistor is electrically connected with the sixth power supply end, and the second electrode of the twelfth transistor is electrically connected with the signal output end; The control electrode of the thirteenth transistor is electrically connected with the eighth node, the first electrode of the thirteenth transistor is electrically connected with the signal output end, and the second electrode of the thirteenth transistor is electrically connected with the eighth power supply end; The first capacitor comprises a first plate and a second plate, the first plate of the first capacitor is electrically connected with the eighth node, and the second plate of the first capacitor is electrically connected with the cascade output end; The second capacitor comprises a first plate and a second plate, the first plate of the second capacitor is electrically connected with the first node, and the second plate of the second capacitor is electrically connected with the fourth power supply end.

17. The shift register of claim 15, wherein, The output sub-circuit comprises a first transistor, a second transistor, a fourth transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a first capacitor, a second capacitor and a fourth capacitor; The control electrode of the first transistor is electrically connected with the first node, the first electrode of the first transistor is electrically connected with the fourth power supply end, and the second electrode of the first transistor is electrically connected with the cascade output end; The control electrode of the second transistor is electrically connected with the eighth node, the first electrode of the second transistor is electrically connected with the cascade output end, and the second electrode of the second transistor is electrically connected with the fifth power supply end; The control electrode of the fourth transistor is electrically connected with the fifth power supply end, the first electrode of the fourth transistor is electrically connected with the second node, and the second electrode of the fourth transistor is electrically connected with the eighth node; The control electrode of the twelfth transistor is electrically connected with the ninth node, the first electrode of the twelfth transistor is electrically connected with the sixth power supply end, and the second electrode of the twelfth transistor is electrically connected with the signal output end; The control electrode of the thirteenth transistor is electrically connected with the second node, the first electrode of the thirteenth transistor is electrically connected with the signal output end, and the second electrode of the thirteenth transistor is electrically connected with the eighth power supply end; The control electrode of the fourteenth transistor is electrically connected with the fifth power supply end, the first electrode of the fourteenth transistor is electrically connected with the first node, and the second electrode of the fourteenth transistor is electrically connected with the ninth node; The first capacitor comprises a first plate and a second plate, the first plate of the first capacitor is electrically connected with the eighth node, and the second plate of the first capacitor is electrically connected with the cascade output end; The second capacitor comprises a first plate and a second plate, the first plate of the second capacitor is electrically connected with the first node, and the second plate of the second capacitor is electrically connected with the fourth power supply end. The fourth capacitor comprises a first plate and a second plate, the first plate of the fourth capacitor is electrically connected with the ninth node, and the second plate of the fourth capacitor is electrically connected with the signal output end.

18. The shift register of claim 1, wherein, The shift register further comprises a reset sub-circuit. The reset sub-circuit is electrically connected with the reset signal end, the first node and the seventh power supply end respectively, and is configured to provide the signal of the seventh power supply end to the first node under the control of the signal of the reset signal end.

19. The shift register of claim 18, wherein, The reset sub-circuit comprises a fifteenth transistor. The control electrode of the fifteenth transistor is electrically connected with the reset signal end, the first electrode of the fifteenth transistor is electrically connected with the seventh power supply end, and the second electrode of the fifteenth transistor is electrically connected with the first node.

20. A gate drive circuit comprising: A plurality of cascaded shift registers as claimed in any one of claims 1 to 19, at least one output signal end of at least one stage of shift register comprises a signal output end; The signal output end of the i-th stage of shift register is electrically connected with the signal input end of the i+L-th stage of shift register, 1≤i≤M-L, M is the total number of stages of shift register, M≥1, and L is a positive integer greater than or equal to 1.

21. A display device comprising a display area and a non-display area, the display area being provided with pixel driving circuits arranged in an array, and the non-display area being provided with the gate driving circuit of claim 20, the pixel driving circuit comprising at least one light-emitting control transistor; At least one stage of shift register in the gate driving circuit is electrically connected with at least one light-emitting control transistor in at least one row of pixel driving circuits.

22. The display device according to claim 21, wherein, The control sub-circuit is electrically connected with the signal input end and the first clock signal end respectively, and the display device further comprises an initial signal line, a first clock signal line and a second clock signal line; The signal input end of at least one stage of shift register is electrically connected with the initial signal line, the first clock signal end is electrically connected with one of the first clock signal line and the second clock signal line, and the signal lines connected with the first clock signal ends of adjacent shift registers are different.

23. The display device according to claim 21, wherein, The control sub-circuit is electrically connected with the signal input end and the first clock signal end respectively, and the display device further comprises an initial signal line, a first clock signal line, a second clock signal line, a third clock signal line and a fourth clock signal line; The signal input end of at least one stage of shift register is electrically connected with the initial signal line; The first clock signal end of the 4M-3-th stage of shift register is electrically connected with the first clock signal line; The first clock signal end of the 4M-2-th stage of shift register is electrically connected with the second clock signal line; The first clock signal end of the 4M-1-th stage of shift register is electrically connected with the third clock signal line; The first clock signal end of the 4M-th stage of shift register is electrically connected with the fourth clock signal line; Wherein, M is the total number of stages of shift register, M≥1.

24. A driving method of a shift register, configured to drive the shift register of any one of claims 1 to 19, the method comprising: The control sub-circuit provides signals to the first node or the second node under the control of the signals of the signal input end and the first clock signal end; The output sub-circuit provides a signal to at least one output signal terminal under the control of signals at the first node, the second node and at least one power signal terminal; and the duration of the effective level signal provided by the output sub-circuit is greater than the period of the signal provided by the first clock signal terminal.

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