Compilation method, compilation apparatus, readable medium, electronic device, and program product

Abstract

The present application relates to the technical field of computers and discloses a compilation method, a compilation apparatus, a readable medium, an electronic device, and a program product. The compilation method provided in embodiments of the present application can determine, by means of a defined access identifier and / or an access identifier, first instructions that satisfy a first processing condition, and perform merging processing and / or deletion processing on the first instructions. The compilation method reduces the risk of errors in instruction merging and / or deletion while reducing the number of memory access instructions, thereby reducing the risk of program runtime errors.

Description

Compilation method, compilation device, readable medium, electronic equipment and program product

[0001] The present application claims priority to the Chinese patent application No. 202411345298.X, filed on September 24, 2024, and entitled "Compilation method, compilation device, readable medium, electronic equipment and program product", the whole content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the technical field of computer, in particular to a compilation method, a compilation device, a readable medium, an electronic equipment and a program product. BACKGROUND

[0003] In the process of running the program of an application (APP), an electronic equipment, such as a processor of a computer, usually needs to read data from the memory and / or write data into the memory.

[0004] However, since the speed of the processor processing data is much higher than the read / write speed of the memory data, the processor needs to spend a lot of time waiting for the required data to be read from the memory and / or written into the memory in the process of running the application, thereby affecting the efficiency of the processor running the application. SUMMARY

[0005] The present application aims to provide a compilation method, a compilation device, a readable medium, an electronic equipment and a program product.

[0006] The first aspect of the present application provides a compilation method, comprising: obtaining a first source program, wherein the first source program comprises composite type data, the composite type data comprises first member data, the first member data comprises a first access identifier, and the first access identifier is used to indicate that the first member data is accessed only through a first access manner; determining at least two first instructions satisfying a first processing condition from a plurality of memory access instructions corresponding to the first source program, wherein the first processing condition comprises that the first instruction is an instruction accessing the first member data through the first access manner, and the types of the at least two first instructions are the same; performing first processing on the at least two first instructions, and obtaining a first target code file.

[0007] It can be understood that if the same type of memory access instruction is directly combined and / or deleted without considering whether there is an intersection between the memory spaces of the memory access instructions, although the number of memory access instructions can be reduced, it may cause the problem of incorrect combination and / or incorrect deletion, thereby affecting the running of the application.

[0008] In the embodiment of the present application, before the source program is compiled, for example, in the program design stage (or coding stage), a program developer configures an access identifier for each member data of a composite type data in the source program, and the access identifier is used to indicate an access manner of the member data. For example, the composite type data includes first member data, and the first member data includes a first access modifier (for example, _unique_), which is used to indicate that the first member data is accessed only through a first access manner. In the compiling stage, at least two first type of memory access instructions (first instructions) that meet a first processing condition are determined from a plurality of memory access instructions corresponding to the first source program, and then, the first instructions are processed, and an executable file (first object code file) is obtained.

[0009] It can be understood that the compiling method provided by the embodiment of the present application can determine the first instructions that meet the first processing condition through the defined access identifier, and the first instructions are merged and / or deleted. The compiling method reduces the number of memory access instructions, reduces the risk of incorrect merging and / or incorrect deletion of instructions, and further reduces the risk of program running errors.

[0010] In a possible implementation of the first aspect, the plurality of memory access instructions corresponding to the first source program are determined by the following method: generating a first intermediate representation based on the first source program, wherein the first intermediate representation includes a plurality of instructions; and determining the plurality of memory access instructions from the plurality of instructions in the first intermediate representation.

[0011] In a possible implementation of the first aspect, the first member data is accessed through the first access manner, including: the first member data is accessed through a first variable, or the first member data is accessed through a first type of variable.

[0012] In a possible implementation of the first aspect, the first processing condition further includes that the at least two first instructions are consecutive memory access instructions.

[0013] In a possible implementation of the first aspect, the composite type data further includes second member data, and the second member data does not include the first access identifier, there is at least one second instruction between the at least two first instructions, and the first processing condition further includes that the second instruction is a memory access instruction that does not access the second member data through the first access manner.

[0014] In a possible implementation of the first aspect, the composite type data further includes second member data, and the second member data includes a second access identifier, and there is at least one second instruction between the at least two first instructions, where the second access identifier is used to indicate that the second member data is accessed by an access mode different from the first access mode, and the first processing condition further includes that the second instruction is an access instruction for accessing the second member data by the second access mode, where the second access mode is an access mode different from the first access mode.

[0015] In a possible implementation of the first aspect, the type corresponding to the first instruction is a read operation instruction, and the first processing condition further includes at least one of the following: the first instruction is a read operation instruction, and the second instruction is a write operation instruction; or the first instruction is a write operation instruction, and the second instruction is a read operation instruction.

[0016] In the embodiments of the present application, the first instruction and the second instruction are access instructions of different types.

[0017] In a possible implementation of the first aspect, the first source program further includes a relevance identifier of a variable, and the relevance identifier is used to indicate whether there is another variable that has an intersection with a storage space corresponding to the variable; and the method further includes: determining, based on the relevance identifier in the first source program, at least two third instructions in the plurality of access instructions corresponding to the first source program that do not satisfy the first processing condition and satisfy a second processing condition, where the second processing condition includes that the at least two third instructions correspond to a third variable, there is at least one fourth instruction corresponding to a fourth variable between the at least two third instructions, and the storage space corresponding to the fourth variable does not have an intersection with the storage space corresponding to the third variable; performing the first processing on the plurality of third instructions, and obtaining the first target code file.

[0018] In the embodiments of the present application, before the source program is compiled, a program developer can also configure a relevance identifier for each variable in the source program, where the relevance identifier is used to indicate whether a memory space (storage space) corresponding to the variable coincides, so that the compiling device can further determine, based on the relevance identifier, whether the access instruction satisfies the second processing condition, to further reduce the number of access instructions, during the compiling stage.

[0019] It can be understood that the compiling method provided in the application can configure the correlation identifier in the source program by defining the correlation identifier, and the correlation identifier is used to indicate whether the memory space (storage space) corresponding to the variable coincides. In the compiling stage, based on the correlation identifier of each variable in the source program, at least two third instructions in the plurality of memory access instructions corresponding to the first source program and satisfying the second processing condition are determined, and then the first processing is performed on the at least two third instructions, and an executable file (first target code file) is obtained. In this way, the number of memory access instructions can be further reduced, so that the running efficiency of the application program corresponding to the source program is improved.

[0020] In a possible implementation of the first aspect, the correlation identifier is used to indicate whether there is another variable whose storage space intersects with the storage space corresponding to the variable, and the correlation identifier includes: the storage space corresponding to the variable with the same correlation identifier does not intersect.

[0021] In a possible implementation of the first aspect, the storage space corresponding to the fourth variable does not intersect with the storage space corresponding to the third variable, and the correlation identifier of the fourth variable corresponding to the fourth instruction is the same as the correlation identifier of the third variable corresponding to the third instruction.

[0022] In a possible implementation of the first aspect, the number of memory access instructions in the first target code file is less than the number of memory access instructions in the second target code file, and the second target code file is a target code file obtained by not performing the first processing on the memory access instructions.

[0023] In a possible implementation of the first aspect, the first processing includes at least one of the following: a merging processing and a deletion processing.

[0024] In a possible implementation of the first aspect, corresponding to the first processing including the merging processing, the first processing condition further includes: the storage space accessed by each first instruction is continuous storage space, or the data stored in the storage space accessed by each first instruction corresponds to the same variable.

[0025] In a possible implementation of the first aspect, the merging processing includes: merging a plurality of first instructions satisfying the first processing condition into one fifth instruction, and the storage space accessed by the fifth instruction includes the storage space accessed by the plurality of first instructions.

[0026] In a possible implementation of the first aspect, the merging processing further includes: merging a plurality of first instructions satisfying the processing condition into a plurality of sixth instructions, the storage space accessed by the sixth instruction includes the storage space accessed by the plurality of first instructions, and the number of the sixth instructions is less than the number of the first instructions.

[0027] In a possible implementation of the first aspect, the deleting processing includes: in a case where there are M seventh instructions of the same type and accessing the first storage space in the first intermediate representation, and storage spaces accessed by other instructions between the M seventh instructions have no intersection with storage spaces accessed by the seventh instructions, deleting N seventh instructions, where M is an integer greater than 1, and N is a positive integer less than M.

[0028] In a possible implementation of the first aspect, the type of the seventh instruction is a read operation instruction, there is an eighth instruction of reading data in the first storage space to a second storage space in the N seventh instructions, the second storage space is different from storage spaces to which data in the first storage space is read by M-N seventh instructions other than the N seventh instructions in the M seventh instructions, and address information of the second storage space in a ninth instruction of reading data in the second storage space is replaced by address information of a storage space to which data in the first storage space is read by any one of the M-N seventh instructions, where the ninth instruction is an instruction in the first intermediate representation after the eighth instruction and before a next instruction of writing data to the second storage space, and the address information of the storage space includes a register name.

[0029] In the embodiment, the instruction m is a read operation instruction of reading data in the storage space P (the first storage space) to the register R0, the instruction n is a read operation instruction of reading data in the storage space P to the register R1 (the second storage space), and the instruction n is deleted, and then the register R1 in each instruction in the first intermediate representation after the instruction n and before a next instruction of writing data to the register R1 is replaced by the register R0, so that the semantics in the first intermediate representation is correct.

[0030] In a possible implementation of the first aspect, if the first instruction is a write operation instruction, the deleting processing includes: deleting N seventh instructions in the first M-1 seventh instructions of the M seventh instructions.

[0031] In the embodiment, the deleting processing includes: retaining a last executed seventh instruction of the plurality of seventh instructions, and deleting at least one seventh instruction other than the last executed seventh instruction of the plurality of seventh instructions.

[0032] In a possible implementation of the first aspect, the first target code file is obtained by: performing first processing on the at least two first instructions to obtain a second intermediate representation, where a number of the first instructions in the second intermediate representation is less than a number of the first instructions in the first intermediate representation; and generating the first target code file based on the second intermediate representation.

[0033] It can be understood that the compiling method provided in the first aspect of the present application can determine the memory access instructions satisfying the first processing condition and the second processing condition through the defined access identifier and the correlation identifier, and can reduce the number of memory access instructions through the merging and / or deleting processing of the memory access instructions satisfying the conditions, thereby improving the running efficiency of the application program corresponding to the source program, and reducing the risk of error merging and / or error deleting, and further reducing the risk of program running errors.

[0034] The second aspect of the present application provides a compiling method, comprising: obtaining a first source program, wherein the first source program comprises a correlation identifier of a variable, and the storage spaces corresponding to the variables with the same correlation identifier do not have an intersection; determining at least two first instructions satisfying a first processing condition from a plurality of memory access instructions corresponding to the first source program based on the correlation identifier in the first source program, wherein the first processing condition comprises that the at least two first instructions correspond to a first variable, there is at least one second instruction corresponding to a second variable between the at least two first instructions, and the correlation identifier of the second variable is the same as the correlation identifier of the first variable; and performing first processing on the at least two first instructions, and obtaining a first target code file.

[0035] It can be understood that if the same type of memory access instructions accessing the memory space of a continuous address are directly merged without considering whether the memory spaces accessed by other types of memory access instructions between the merged memory access instructions coincide with the memory space accessed by the merged memory access instructions, although the number of memory access instructions can be reduced, the problem of error merging may be caused, thereby affecting the running of the application program.

[0036] In the embodiments of the present application, before the source program is compiled, for example, in the program design stage (or coding stage), the program developer configures the correlation identifier of each variable in the source program, and the correlation identifier is used to indicate whether the memory space (storage space) corresponding to the variable coincides. In the compiling stage, the instructions in the source program are converted into intermediate representations, and the plurality of first type memory access instructions (first instructions) satisfying the processing condition (for example, the merging condition) in the intermediate representations are determined based on the correlation identifier of each variable in the source program, then the plurality of first instructions are merged, and based on the merged intermediate representations, an executable file (first target code file) is obtained.

[0037] It can be understood that the compiling method provided in the application can determine the coincidence relationship of the memory spaces corresponding to the variables through the defined correlation identifier, thereby determining the first instructions satisfying the merging condition and merging the first instructions, so as to reduce the risk of error merging and further reduce the risk of program running error. In addition, in the case where the correlation identifier of the variable does not indicate that the memory spaces corresponding to the variables must not coincide, the first instructions satisfying the merging condition can be further determined based on the access identifier of the member data in each composite data type variable in the source program, and the first instructions are merged, so that the number of memory access instructions can be further reduced, thereby improving the running efficiency of the application program corresponding to the source program.

[0038] The third aspect of the application provides a compiling device, comprising: an acquisition module configured to acquire a first source program, wherein the first source program comprises composite type data, the composite type data comprises first member data, the first member data comprises a first access identifier, and the first access identifier is used to indicate that the first member data is accessed only through a first access manner; an optimization module configured to determine at least two first instructions satisfying a first processing condition from a plurality of memory access instructions corresponding to the first source program, wherein the first processing condition comprises that the first instructions are instructions for accessing the first member data through the first access manner, and the types of the at least two first instructions are the same; the optimization module is further configured to perform first processing on the at least two first instructions; and a code generation module configured to obtain a first target code file.

[0039] In a possible implementation of the third aspect, the acquisition module is further configured to acquire the first source program, wherein the first source program comprises a correlation identifier of a variable, and the correlation identifier is used to indicate whether there is another variable having an intersection with the storage space corresponding to the variable; the optimization module is further configured to determine, based on the correlation identifier in the first source program, at least two third instructions in the plurality of memory access instructions corresponding to the first source program that do not satisfy the first processing condition and satisfy a second processing condition, wherein the second processing condition comprises that the at least two third instructions correspond to third variables, there is at least one fourth instruction corresponding to fourth variables between the at least two third instructions, and the storage space corresponding to the fourth variables does not have an intersection with the storage space corresponding to the third variables; the optimization module is further configured to perform the first processing on the at least two third instructions; and the code generation module is further configured to obtain the first target code file.

[0040] The fourth aspect of the present application provides a compiling device, comprising: an obtaining module, configured to obtain a first source program, wherein the first source program comprises a correlation identifier of a variable, and storage spaces corresponding to variables with the same correlation identifier do not have an intersection; an optimization module, configured to determine at least two first instructions satisfying a first processing condition from a plurality of memory access instructions corresponding to the first source program based on the correlation identifier in the first source program, wherein the first processing condition comprises: the at least two first instructions correspond to a first variable, there is at least one second instruction corresponding to a second variable between the at least two first instructions, and the correlation identifier of the second variable is the same as the correlation identifier of the first variable; the optimization module is further configured to perform first processing on the at least two first instructions; and a code generation module, configured to obtain a first target code file.

[0041] The fifth aspect of the present application provides a readable medium, wherein the readable medium stores instructions, and the instructions are configured to enable an electronic device to perform any one of the methods in the first aspect and the second aspect when the instructions are executed on the electronic device.

[0042] The sixth aspect of the present application provides an electronic device, comprising a memory, configured to store instructions executed by one or more processors of the electronic device, and a processor, which is one of the processors of the electronic device, and is configured to perform any one of the methods in the first aspect and the second aspect.

[0043] The seventh aspect of the present application provides a program product, wherein the program product comprises instructions, and the instructions are configured to enable an electronic device to implement any one of the methods in the first aspect and the second aspect when the instructions are executed on the electronic device. BRIEF DESCRIPTION OF DRAWINGS

[0044] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings needed to be used in the description of the specific embodiments or the prior art. Obviously, the drawings described below are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0045] FIG. 1 shows a schematic diagram of a conversion process of converting a program source code into an executable file according to an embodiment of the present application;

[0046] FIG. 2 shows a schematic diagram of a memory access process according to an embodiment of the present application;

[0047] FIG. 3A shows a schematic diagram of data interaction between a processor and a memory according to an embodiment of the present application;

[0048] FIG. 3B shows a comparison schematic diagram of an access process according to an embodiment of the present application;

[0049] FIG. 3C shows a schematic diagram of an access process according to an embodiment of the present application;

[0050] FIGS. 4A-4D show schematic diagrams of an error merging scenario according to an embodiment of the present application;

[0051] FIG. 5 shows a flowchart of a compiling method according to an embodiment of the present application;

[0052] FIG. 6 shows a flowchart of a compiling method based on access identification according to an embodiment of the present application;

[0053] FIG. 7 shows a flowchart of a compiling method based on access identification and correlation identification according to an embodiment of the present application;

[0054] FIG. 8 shows a flowchart of a compiling method based on variable correlation identification according to an embodiment of the present application;

[0055] FIG. 9 shows a flowchart of a compiling method based on correlation identification and access identification according to an embodiment of the present application;

[0056] FIG. 10 shows a structural diagram of a compiling apparatus according to an embodiment of the present application;

[0057] FIG. 11 shows a hardware structural diagram of a compiling apparatus according to an embodiment of the present application. DETAILED DESCRIPTION

[0058] The illustrative embodiments of the present application include, but are not limited to, a compiling method, a compiling apparatus, a readable medium, an electronic device, and a program product.

[0059] To make the objectives, technical solutions, and advantages of the present application clearer, the technical solutions in the embodiments of the present application will be described in detail below with reference to the drawings.

[0060] Before introducing the technical solutions involved in the embodiments of the present application, some terms contained in the embodiments of the present application will be explained.

[0061] (1) Variable

[0062] In computer programming, a variable is an identifier used to store data, for example, a variable name can represent the first address of a memory space storing data. Each variable has an associated data type, including but not limited to basic data types such as integer (int), floating point number (float), character (char), string (string), and Boolean (boolean), and composite data types such as array (array), structure (struct), and class (class).

[0063] The definition of a variable of a basic data type is as follows: data type variable name. For example, int a indicates that the variable a corresponds to an integer data.

[0064] The definition of a variable of a composite data type (or composite type data) is as follows: composite data type composite data name {member list} composite data variable name. For example, struct Student{char name; int age; float score;} student1 indicates that the structure variable student1 of the structure Student is defined, and the structure variable includes multiple member data: the character type member data name, the integer type member data age, and the floating point type member data score.

[0065] (2) Pointer variable

[0066] A variable storing an address is called a pointer variable, and the pointer variable is a special variable.

[0067] The form of defining a pointer variable is as follows: data type * variable name. For example, int * p indicates that the pointer variable p has the variable name p, and the data in the memory space (hereinafter referred to as the memory space) corresponding to the address stored by the pointer variable p is an integer data. The pointer variable can be used to access the memory space corresponding to a variable of a basic data type or a variable of a composite data type.

[0068] For example, the elements in an array are accessed by a pointer. Assuming that the character array is char array, the pointer variable char * ptr can be defined. For example, *(ptr) indicates accessing the first element of the array array, *(ptr+1) indicates accessing the second element of the array array, and so on.

[0069] For another example, the member data in a structure is accessed by a pointer. For the structure variable struct Student{char name; int age; float score;} student1, the pointer variable struct Student * pStudent can be defined, and pStudent = & student1 indicates accessing the structure variable student1. For example, the member data age of the structure variable student1 is accessed by any one of the following forms: student1.age, (*pStudent).age, and pStudent->age.

[0070] (3) Formal parameter: When defining a function, the variables in the parentheses after the function name are called formal parameters, which are simply referred to as formal parameters. Formal parameters are variables used in function definition, and formal parameters are virtual variables without specific values. Formal parameters are used to receive the values passed by actual parameters during function calls and perform calculations based on the values passed by actual parameters. Formal parameters are only instantiated (allocated memory space) during function calls, and are automatically destroyed after the function call is completed. That is, formal parameters are only valid during function execution.

[0071] (4) Actual parameter: When calling a function, the parameters in the parentheses after the function name are called actual parameters, which are simply referred to as actual parameters. Actual parameters are variables used during function calls, and have specific values, which are used to pass the values of actual parameters to the formal parameters of the called function. The form of actual parameters includes but is not limited to: constants, variables, expressions, functions, etc. Regardless of the form of the actual parameter, the actual parameter must have a specific value when the function is called, so that the specific value of the actual parameter can be passed to the formal parameter when the function is called. For example, if the actual parameter is an expression, each variable in the expression must have a specific value to obtain the value of the expression. Or for example, if the actual parameter is a function, each parameter of the function must have a specific value to obtain the function value.

[0072] For example, refer to the following code:

[0073] Among them, the function of the add function is to calculate the sum of the values of the parameters x and y. Parameters x and y are formal parameters, and parameters a and b are actual parameters.

[0074] (5) Compilation: Compilation is the conversion of source code (or source program, program source code) written in one programming language (hereinafter referred to as the original language) into target code of another programming language (hereinafter referred to as the target language), such as a binary executable file. Among them, the complexity of the original language is higher than that of the target language. For example, the original language can be a high-level language such as Pascal, C, C++, C#, Java, etc.; the target language can be an assembly language or a machine language. Among them, the code of the machine language can be the object code of the target machine (such as the device running the code of the machine language), which can also be referred to as machine code or machine code.

[0075] In order to facilitate understanding, the following takes the original language as a high-level language and the target language as a machine language as an example to explain the process of converting the source program into an executable file that can be executed by the processor (i.e. the program compilation process).

[0076] FIG. 1 shows a schematic diagram of a conversion process of converting a source program into an executable file according to an embodiment of the present application. As shown in FIG. 1, the conversion process of converting a source program into an executable file includes the following stages:

[0077] 1. Compilation stage: a compiler in a compilation device obtains a source program, performs lexical analysis, syntax analysis, semantic analysis, etc. on the source program, generates an intermediate representation (IR, or intermediate code), and performs optimization (such as instruction merging, etc.) on the intermediate representation, to obtain an assembly code file. The form of the intermediate representation includes but is not limited to postfix representation, graph representation, three-address code, and low level virtual machine (LLVM) intermediate representation, etc.

[0078] For example, taking the original language as C language and the target language as machine language as an example. Assuming that the source program is:

[0079] The memory access instruction corresponding to the swap function in the intermediate representation can be in the following form:

[0080] Load1B@addr1; / / read a byte of data from the memory space whose starting address pointed by the pointer variable p is addr1

[0081] Load1B@addr2; / / read a byte of data from the memory space whose starting address pointed by the pointer variable q is addr2

[0082] Store1B@addr1; / / write a byte of data to the memory space whose starting address pointed by the pointer variable q is addr1

[0083] Store1B@addr2; / / write a byte of data to the memory space whose starting address pointed by the pointer variable q is addr2

[0084] Wherein, addr1 and addr2 are virtual addresses (VA). When the executable file is run, the processor of the running device converts the virtual address into a physical address (PA), that is, allocates an available physical memory space, and sends the physical address to the processor core in the processor, and the processor core controls the data bus to read / write (memory access) data to the memory space corresponding to the physical address.

[0085] It can be understood that the pointer variable p and the pointer variable q are formal parameters of the swap function. The life cycle of the pointer variable p and the pointer variable q is only during the running of the swap function, that is, the pointer variable p and the pointer variable q are local variables, and the memory space pointed to by the pointer variable p and the pointer variable q needs to be determined by the processor when the processor runs the machine instruction corresponding to the swap function. That is, the address information of the memory space corresponding to the pointer variable p and the pointer variable q cannot be determined in the compilation stage, and the address information of the memory space corresponding to the pointer variable p and the pointer variable q needs to be determined in the processor execution stage.

[0086] 2. Assembly stage: the assembler of the compiling device obtains the assembly code file generated by the compiler, and converts the assembly instructions in the assembly code file into machine instructions (for example, 01 sequence), and generates an object file.

[0087] 3. Linking stage: since there may be a case that the object file calls a function in a library file or other file, the linker of the compiling device needs to connect the related object file generated by the assembler, and connect with the library file, to generate an executable file, so that the processor of the running device runs the generated executable file.

[0088] It can be understood that the compiling device and the running device can be the same device, or can be different devices.

[0089] The compiling method provided in the embodiments of the present application can be applied to a compiler or a device with a program compiling function.

[0090] The compiler in the embodiments of the present application includes, but is not limited to, a GNU compiler collection (GCC), a low level virtual machine (LLVM), and the like.

[0091] The device in the embodiments of the present application can be a terminal device, for example, a mobile phone, a smart television, a wearable device, a tablet computer, a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a wireless terminal in an unmanned vehicle, a wireless terminal in a remote surgery, a wireless terminal in a smart power grid, a wireless terminal in a smart home, and the like. The device can also be a physical server or a cloud device, or a virtual machine (VM) based on a general physical server combined with network function virtualization (NFV) technology, which refers to a complete computer system that is simulated by software, runs in a completely isolated environment, and has complete hardware system functions. The electronic device can also be a server cluster composed of multiple servers, or a cloud computing service center.

[0092] The embodiments of the present application do not make any limitation on the specific types of the compiler and the device.

[0093] For ease of description, the embodiments of the present application are described in detail below by taking the original language as a high-level language and the target language as a machine language as an example.

[0094] As described above, since the speed of the processor of the running device in processing data is much higher than the read-write speed of the memory data, the processor needs to spend a lot of time waiting for the required data to be read from the memory and / or written to the memory in the process of running the executable file corresponding to the application program, thereby affecting the efficiency of the processor in running the application program.

[0095] Therefore, in order to improve the efficiency of the processor in running the application program, the same type of memory access instruction (for example, a read operation instruction or a write operation instruction) in the intermediate representation that accesses a continuous memory space can be merged during the compilation stage of the source program corresponding to the application program, and the executable file is obtained based on the merged intermediate representation.

[0096] It can be understood that, since the executable file is obtained based on the merged intermediate representation, the memory access instruction in the executable file is also the merged memory access instruction. Compared with the case where no merging processing is performed, the number of memory access instructions in the executable file obtained after the merging processing is performed is reduced, that is, the number of memory access requests sent by the processor to the memory is reduced, thereby improving the access efficiency, reducing the waiting time of the processor, and thus improving the efficiency of the processor in running the application program.

[0097] For example, it is assumed that the fun function is as follows:

[0098] int fun(int A[3], int B[3]) {

[0099] …

[0100] B[1] = A[0];

[0101] B[2] = A[1] + A[2];

[0102] …

[0103] }

[0104] wherein array A and array B are two formal parameters of the function fun.

[0105] Taking the instructions B[1] = A[0] and B[2] = A[1] + A[2] in the function fun as an example, referring to the memory access process diagram shown in FIG. 2, the intermediate representation can include 5 memory access instructions, which are sequentially sorted according to the execution order as follows:

[0106] ① read operation instruction Load1B@VA0 for reading the first element A[0] in array A;

[0107] ② write operation instruction Store1B@VB1 for writing data into the second element in array B;

[0108] ③ read operation instruction Load1B@VA1 for reading data in the second element A[1] in array A;

[0109] ④ read operation instruction Load1B@VA2 for reading data in the third element in array A;

[0110] ⑤ write operation instruction Store1B@VB2 for writing data into the third element in array B.

[0111] wherein VA0 is the virtual address corresponding to A[0], VA1 is the virtual address corresponding to A[1], VA2 is the virtual address corresponding to A[2], VB1 is the virtual address corresponding to B[1], and VB2 is the virtual address corresponding to B[2].

[0112] It can be understood that the addresses of the memory spaces corresponding to the elements in array A are continuous, and the addresses of the memory spaces corresponding to the elements in array B are also continuous.

[0113] Continuing to refer to the memory access process diagram shown in FIG. 2, since the instruction Load1B@VA0, the instruction Load1B@VA1, and the instruction Load1B@VA2 are all read operation instructions and the addresses of the memory spaces accessed correspondingly are continuous, the instruction Load1B@VA0, the instruction Load1B@VA1, and the instruction Load1B@VA2 can be merged into a new read operation instruction Load3B@VA0, which is used to read the first element A[0], the second element A[1], and the third element A[2] in the array A.

[0114] It can be understood that since the instruction Store1B@VB1 and the instruction Store1B@VB2 are both write operation instructions and the addresses of the memory spaces accessed correspondingly are continuous, the instruction Store1B@VB1 and the instruction Store1B@VB2 can be merged into a new write operation instruction Store2B@VB1, which is used to write data into the memory spaces corresponding to the second element B[1] and the third element B[2] in the array B.

[0115] Since the processor and the memory interact with each other through a bus, the processor needs to convert a virtual address into a corresponding physical address in the memory before reading data from the memory or writing data into the memory, and then send the physical address and control signals to the memory, so that the memory finds the corresponding physical address and sends the data in the memory space corresponding to the physical address to the processor or stores the data sent by the processor into the memory space corresponding to the physical address. For example, refer to the data interaction diagram between the processor and the memory shown in FIG. 3A.

[0116] As shown in FIG. 3A, the processor and the memory are connected through a bus, which includes a control bus, an address bus, and a data bus. The process of executing a memory access instruction by the processor includes: the physical core of the processor sends a virtual address to the memory management unit, the memory management unit converts the virtual address into a physical address and sends the physical address to the memory. Moreover, if the memory access instruction is a read operation instruction, the physical core of the processor sends a control signal indicating reading data to the memory through the control bus; after receiving the physical address and the control signal indicating reading data, the memory sends the data in the memory space corresponding to the physical address to the cache of the processor through the data bus. If the memory access instruction is a write operation instruction, the physical core of the processor sends a control signal indicating writing data to the memory through the control bus and sends the data to be written to the memory through the data bus; after receiving the physical address, the data to be written, and the control signal indicating writing data, the memory stores the data to be written into the memory space corresponding to the physical address.

[0117] It can be understood that the merged post-processor only needs to implement the functions of the above three read operation instructions through a new read operation instruction Load3B@VA0, thereby reducing the number of memory accesses of the processor, reducing the waiting time of the processor, and further improving the efficiency of the processor in running the executable file.

[0118] For example, in combination with the memory access instructions shown in FIG. 2, reference is made to the comparison diagram of the access process shown in FIG. 3B. As shown in FIG. 3B, the execution process of the memory access instructions before instruction merging includes:

[0119] 1. The processor sends the physical address corresponding to VA0, the control signal for reading data, etc. to the memory.

[0120] 2. The memory sends the data in the memory unit corresponding to the physical address corresponding to VA0 to the processor.

[0121] 3. The processor sends the physical address corresponding to VB1, the control signal for writing data, the data to be written, etc. to the memory.

[0122] 4. The processor sends the physical address corresponding to VA1, the control signal for reading data, etc. to the memory.

[0123] 5. The memory sends the data in the memory unit corresponding to the physical address corresponding to VA1 to the processor.

[0124] 6. The processor sends the physical address corresponding to VA2, the control signal for reading data, etc. to the memory.

[0125] 7. The memory sends the data in the memory unit corresponding to the physical address corresponding to VA2 to the processor.

[0126] 8. The processor sends the physical address corresponding to VB2, the control signal for writing data, the data to be written, etc. to the memory.

[0127] The execution process of the memory access instructions after instruction merging includes:

[0128] 1’. The processor sends the physical address corresponding to VA0, the control signal for reading data in three memory units, etc. to the memory.

[0129] 2’. The memory sends the data in the memory space starting from the physical address corresponding to VA0 to the processor.

[0130] 3’. The processor sends the physical address corresponding to VB1, the control signal for writing data, the data to be written, etc. to the memory.

[0131] It can be understood that after the instruction merging is performed, the processor only needs to send the physical address corresponding to the to-be-read data, the control signal, etc. to the memory once, and send the physical address corresponding to the to-be-written data, the control signal, etc. to the memory once, the number of times of sending the physical address and the control signal to the memory is reduced, and thus the time for reading data and writing data is shortened.

[0132] However, since the memory space is allocated when the processor runs the executable file, the compiling device cannot obtain the related information of the memory space corresponding to the formal parameter array A and the array B of the fun function in the compiling stage.

[0133] In some cases, referring to the schematic diagram of the access process shown in FIG. 3C, the formal parameter array A and the array B of the fun function can correspond to the same actual parameter array N, that is, the memory spaces corresponding to the array A and the array B are the same. For example, as shown in FIG. 3C, the virtual address VA0 corresponding to A[0] is the same as the physical address PA0, the virtual address VA1 corresponding to A[1] and the virtual address VB1 corresponding to B[1] are the same as the same physical address PA1, and the virtual address VA2 corresponding to A[2] and the virtual address VB2 corresponding to B[2] are the same as the same physical address PA2. The memory spaces accessed by the read operation instruction Load1B@VA1 and the write operation instruction Store1B@VB1 have an intersection, for example, both are the memory space 1, and the read operation instruction Load1B@VA1 is executed after the write operation instruction Store1B@VB1, that is, write-after-read. The memory spaces accessed by the read operation instruction Load1B@VA2 and the write operation instruction Store1B@VB2 have an intersection, for example, both are the memory space 2, and the write operation instruction Store1B@VB2 is executed after the read operation instruction Load1B@VA2, that is, read-after-write.

[0134] In some cases, if the data read from the memory space 1 by the read operation instruction Load1B@VA1 is the data written into the memory space 1 by the processor through the write operation instruction Store1B@VB1. After the above instruction merging is performed, the execution order of the instructions can be changed, for example, the new read operation instruction Load3B@VA0 is executed first, and then the write operation instruction Store2B@VB1 is executed, which can cause the data read from the memory space 1 by the processor to be the data that is not expected to be obtained, that is, the data written into the memory space 1 by the processor through the write operation instruction Store2B@VB1, and thus cause the program to run incorrectly, and even cause the application to run abnormally or crash.

[0135] In some cases, if there is a write operation instruction Store1B@VC1 (not shown in the figure) between the write operation instruction Store1B@VB1 and the write operation instruction Store1B@VB2, and the write operation instruction Store1B@VB2 is executed after the write operation instruction Store1B@VC1, i.e., write-after-write, if the memory space accessed by the write operation instruction Store1B@VC1 intersects with the memory space accessed by the write operation instruction Store1B@VB1 and / or the write operation instruction Store1B@VB2, the execution order of the write operation instruction Store1B@VB1 and the write operation instruction Store1B@VB2 may be changed if the write operation instruction Store1B@VB1 and the write operation instruction Store1B@VB2 are combined, which may cause program running errors, and even cause application running exceptions or crashes.

[0136] For example, referring to the error combination scenario shown in FIGS. 4A-4D. As shown in FIG. 4A, the mobile phone 10 is running a video application and displays a user interface 10a of the video application. If a video switching operation is detected, e.g., the up-swipe operation shown in FIG. 4A, the processor of the mobile phone 10 needs to run the video switching process of the video application, e.g., obtain video data of another video, perform picture rendering, etc. If the memory access instructions in the program corresponding to the video switching process of the video application running on the mobile phone 10 are combined incorrectly, e.g., without considering whether the memory space accessed by the write operation instruction between the combined read operation instructions intersects with the memory space accessed by the combined read operation instructions, the video application may run abnormally. For example, a user interface 10b shown in FIG. 4B displaying “loading failed” is displayed. For another example, an abnormal white screen interface 10c shown in FIG. 4C is displayed. For another example, a desktop 10d of the mobile phone 10 shown in FIG. 4D is displayed, i.e., the video application ends running, etc.

[0137] It can be understood that if the same type of memory access instructions accessing continuous memory spaces are combined according to the above method without considering whether the memory space accessed by the other type of memory access instruction between the combined memory access instructions intersects with the memory space accessed by the combined memory access instructions, although the number of memory access instructions can be reduced, the above-mentioned incorrect combination problem may occur, which affects the running of the application program.

[0138] However, since the memory space is allocated when the processor runs the executable file, the compiler cannot allocate memory space for each variable in the source program in the compilation stage. Therefore, the compiler cannot obtain the related information of the memory space accessed by each memory access instruction, and cannot determine whether the memory spaces accessed by multiple memory access instructions intersect.

[0139] Therefore, an embodiment of the present application provides a compilation method, in which:

[0140] Before the source program is compiled, for example, in the program design stage (or coding stage), a program developer configures a correlation identifier for each variable in the source program, which indicates whether the memory space corresponding to the variable has an intersection.

[0141] In some embodiments, variables corresponding to memory spaces that definitely have no intersection can be marked with the same first-type correlation identifier, or variables corresponding to memory spaces that possibly have an intersection can be marked with different first-type correlation identifiers, so that the compilation stage can determine whether the memory spaces corresponding to the memory access instructions have an intersection based on the first-type correlation identifiers of the variables.

[0142] For example, for the fun function described above, if the developer knows that array A and array B are definitely not the same array, the same first-type correlation identifier, for example, no_alias<0>, can be marked for array A and array B. If the developer cannot determine whether array A and array B are definitely not the same array, different first-type correlation identifiers can be marked for array A and array B, for example, no_alias<1> is used for array A and no_alias<2> is used for array B.

[0143] In other embodiments, variables corresponding to memory spaces that possibly have an intersection can also be marked with the same second-type correlation identifier, or variables corresponding to memory spaces that definitely have no intersection can be marked with different second-type correlation identifiers, so that the compilation stage can determine whether the memory spaces corresponding to the memory access instructions have an intersection based on the second-type correlation identifiers of the variables.

[0144] For example, for the fun function described above, if the developer knows that array A and array B are definitely not the same array, different second-type correlation identifiers can be marked for array A and array B, for example, alias<0> is used for array A and alias<1> is used for array B. If the developer cannot determine whether array A and array B are definitely not the same array, the same second-type correlation identifier can be marked for array A and array B, for example, alias<2> is used for array A and array B.

[0145] In the compilation stage, the compiler converts the instructions in the source program into an intermediate representation, and based on the correlation identifiers of the variables in the source program, a plurality of first-type memory access instructions (hereinafter referred to as first instructions) in the intermediate representation that satisfy a merging condition are taken as a plurality of to-be-merged instructions. Then, the to-be-merged instructions are merged, and based on the intermediate representation after the merging processing, an executable file is obtained.

[0146] In some embodiments, the plurality of first instructions can correspond to variables of a plurality of different basic data types.

[0147] The merging condition can be that the types of the plurality of first instructions are same, the memory space addresses accessed by the plurality of first instructions are continuous, the plurality of first instructions are continuous memory access instructions, and the correlation identifiers of the plurality of variables corresponding to the plurality of first instructions indicate that there is no intersection between the memory spaces corresponding to the plurality of variables.

[0148] The merging condition can also be that the types of the plurality of first instructions are same, the memory space addresses accessed by the plurality of first instructions are continuous, the correlation identifiers of the plurality of variables corresponding to the plurality of first instructions indicate that there is no intersection between the memory spaces corresponding to the plurality of variables, and there is at least one second instruction between the plurality of first instructions, the correlation identifier of the variable corresponding to the second instruction indicates that there is no intersection between the memory space corresponding to the variable of the second instruction and the memory spaces corresponding to the variables of the first instructions.

[0149] If the first instruction is a read operation instruction, the merging condition can also be that the types of the plurality of first instructions are same, the memory space addresses accessed by the plurality of first instructions are continuous, the correlation identifiers of the plurality of variables corresponding to the plurality of first instructions indicate that there is no intersection between the memory spaces corresponding to the plurality of variables, and there is at least one second instruction between the plurality of first instructions, the type of the second instruction is different from the type of the first instruction, and the correlation identifier of the variable corresponding to the second instruction indicates that there is no intersection between the memory space corresponding to the variable of the second instruction and the memory spaces corresponding to the variables of the first instructions.

[0150] In some embodiments, the plurality of first instructions can also correspond to variables of the same composite data type.

[0151] The merging condition can be that the types of the plurality of first instructions are same, the memory space addresses accessed by the plurality of first instructions are continuous, the variables corresponding to the plurality of first instructions are the first variable, there is at least one second instruction between the plurality of first instructions, and the correlation identifier of the second variable corresponding to the second instruction indicates that there is no intersection between the memory space corresponding to the second variable and the memory space corresponding to the first variable.

[0152] If the first instruction is a read operation instruction, the merging condition can also be that the types of the plurality of first instructions are same, the memory space addresses accessed by the plurality of first instructions are continuous, the variables corresponding to the plurality of first instructions are the first variable, there is at least one second instruction between the plurality of first instructions, the type of the second instruction is different from the type of the first instruction, and the correlation identifier of the second variable corresponding to the second instruction indicates that there is no intersection between the memory space corresponding to the second variable and the memory space corresponding to the first variable.

[0153] In some embodiments, when the correlation identifier of the variable is the first type of correlation identifier, the compiling device can acquire the first type of correlation identifier of the variable in the source program.

[0154] If the first-type correlation identifiers of multiple variables in the source program are the same, the compiling device can determine that the memory spaces corresponding to the multiple variables with the same first-type correlation identifiers do not have intersection. The continuous first instructions of the memory spaces accessed by the variables with the same first-type correlation identifiers and with continuous addresses are determined as the to-be-merged instructions; or, the first instructions of the multiple first instructions of the memory spaces accessed by the variables with different first-type correlation identifiers and with continuous addresses, which have the same correlation identifier as the variables corresponding to the second instructions between the multiple first instructions, are determined as the to-be-merged instructions.

[0155] If the first-type correlation identifiers of the variables in the source program are different, the electronic device cannot determine whether the memory spaces corresponding to the multiple variables with different first-type correlation identifiers have intersection, and cannot determine the to-be-merged instructions.

[0156] In some other embodiments, when the correlation identifier of a variable is the aforementioned second-type correlation identifier, the compiling device can acquire the second-type correlation identifier of the variable in the source program.

[0157] If the second-type correlation identifiers of multiple variables in the source program are different, the compiling device can determine that the memory spaces corresponding to the multiple variables with different second-type correlation identifiers do not have intersection. The continuous first instructions of the memory spaces accessed by the variables with different second-type correlation identifiers and with continuous addresses are determined as the to-be-merged instructions; or, the first instructions of the multiple first instructions of the memory spaces accessed by the variables with different first-type correlation identifiers and with continuous addresses, which have different correlation identifiers as the variables corresponding to the second instructions between the multiple first instructions, are determined as the to-be-merged instructions.

[0158] If the second-type correlation identifiers of the variables in the source program are the same, the compiling electronic device cannot determine whether the memory spaces corresponding to the multiple variables with the same second-type correlation identifiers have intersection, and cannot determine the to-be-merged instructions.

[0159] For example, if the memory space I accessed by the read operation instruction I is adjacent to the memory space II accessed by the read operation instruction II, and there is a write operation instruction III between the read operation instruction I and the read operation instruction II, the memory space III accessed by the write operation instruction III does not have intersection with the memory space I and the memory space II, the read operation instruction I and the read operation instruction II can be merged into a new read operation instruction I', and the memory space accessed by the read operation instruction I' is the memory space I and the memory space II.

[0160] For example, if memory space III accessed by the write operation instruction III is adjacent to memory space IV accessed by the write operation instruction IV, and there is a read operation instruction V between the write operation instruction III and the write operation instruction IV, and memory space V accessed by the read operation instruction V has no intersection with memory space III and memory space IV, the write operation instruction III and the write operation instruction IV can be merged into a new write operation instruction III', and the memory space accessed by the write operation instruction III' is memory space III and memory space IV.

[0161] It can be understood that the compiling method provided by the embodiments of the present application can make the compiler determine whether the to-be-merged instructions accessing the memory space of continuous addresses can be merged through the correlation identifier in the source program by defining and using the correlation identifier, thereby reducing the risk of error merging and further reducing the risk of program running errors.

[0162] Specifically, the compiling stage can include:

[0163] First, the code in the source program is converted into an intermediate representation, wherein the source program includes the correlation identifier of a variable.

[0164] Second, multiple memory access instructions of the same type accessing the memory space of continuous addresses in the intermediate representation are taken as multiple target instructions.

[0165] Then, the correlation identifier of each variable in the source program is obtained, the coincidence relationship of the memory space corresponding to each variable is determined based on the correlation identifier of each variable, and it is judged whether there is to-be-merged instruction satisfying the merging condition in the multiple target instructions based on the coincidence relationship of the memory space, and the to-be-merged instruction is merged.

[0166] It can be understood that if the variables corresponding to the first to-be-merged instruction and the second to-be-merged instruction are both the first variable, for example, corresponding to the same composite data type variable, that is, the memory space accessed by the first to-be-merged instruction and the second to-be-merged instruction has no intersection (i.e., the addresses are not related). And if the first to-be-merged instruction and the second to-be-merged instruction are continuous memory access instructions, that is, there is no other memory access instruction between the first to-be-merged instruction and the second to-be-merged instruction, the first to-be-merged instruction and the second to-be-merged instruction can be merged.

[0167] In some embodiments, taking the to-be-merged instruction as a read operation instruction as an example, if the variables corresponding to the first to-be-merged instruction and the second to-be-merged instruction are the first variable, and there is a write operation instruction between the first to-be-merged instruction and the second to-be-merged instruction, and the first type correlation identifier of the second variable corresponding to the write operation instruction is the same as the first type correlation identifier of the first variable, the first to-be-merged instruction and the second to-be-merged instruction can be merged.

[0168] Exemplarily, taking 5 access instructions shown in FIG. 2 as an example: read operation instruction Load1B@VA0, write operation instruction Store1B@VB1, read operation instruction Load1B@VA1, read operation instruction Load1B@VA2, and write operation instruction Store1B@VB2, VA0 is a virtual address corresponding to A[0], VA1 is a virtual address corresponding to A[1], VA2 is a virtual address corresponding to A[2], and VB1 is a virtual address corresponding to B[1], and VB2 is a virtual address corresponding to B[2].

[0169] In some embodiments, it is assumed that the correlation identifier of array A is a first type of correlation identifier no_alias<0>, and the correlation identifier of array B is also a first type of correlation identifier no_alias<0>.

[0170] Since the addresses of the memory spaces corresponding to the first element A[0], the second element A[1], and the third element A[2] of array A are continuous, VA0, VA1, and VA2 are continuous addresses, and the read operation instruction Load1B@VA0, the read operation instruction Load1B@VA1, and the read operation instruction Load1B@VA2 can be regarded as to-be-merged instructions. Then, whether there are instructions that can be merged in the to-be-merged instructions can be determined based on the correlation identifiers of the variables corresponding to the to-be-merged instructions.

[0171] There is a write operation instruction Store1B@VB1 between the read operation instruction Load1B@VA0 and the read operation instruction Load1B@VA1, and the variable array A corresponding to the read operation instruction Load1B@VA0 and the read operation instruction Load1B@VA1 has the same first type of correlation identifier as the variable array B corresponding to the write operation instruction Store1B@VB1, and there is no intersection between the memory spaces corresponding to array A and array B, that is, there is no intersection between the memory spaces accessed by the read operation instruction Load1B@VA0, the read operation instruction Load1B@VA1, and the write operation instruction Store1B@VB1, and therefore the read operation instruction Load1B@VA0 and the read operation instruction Load1B@VA1 can be merged.

[0172] There is no write operation instruction between the read operation instruction Load1B@VA1 and the read operation instruction Load1B@VA2, that is, the read operation instruction Load1B@VA1 and the read operation instruction Load1B@VA2 are continuous access instructions, and therefore the read operation instruction Load1B@VA1 and the read operation instruction Load1B@VA2 can be merged.

[0173] Therefore, the read operation instruction Load1B@VA0, the read operation instruction Load1B@VA1, and the read operation instruction Load1B@VA2 can be merged into a read operation instruction Load3B@VA0.

[0174] Since the addresses of the memory spaces corresponding to the second element B[1] and the third element B[2] of the array B are continuous, VB1 and VB2 are continuous addresses, and the write operation instruction Store1B@VB1 and the write operation instruction Store1B@VB2 can be taken as to-be-merged instructions. Then, whether there is a mergable instruction in the to-be-merged instructions can be determined based on the correlation identifiers of the variables corresponding to the to-be-merged instructions.

[0175] The write operation instruction Store1B@VB1 and the write operation instruction Store1B@VB2 exist between the read operation instruction Load1B@VA1 and the read operation instruction Load1B@VA2, and the variable array B corresponding to the write operation instruction Store1B@VB1 and the write operation instruction Store1B@VB2 has the same first-type correlation identifier as the variable array A corresponding to the read operation instruction Load1B@VA1 and the read operation instruction Load1B@VA2, and there is no intersection between the memory spaces corresponding to the array A and the array B, that is, there is no intersection between the memory spaces accessed by the write operation instruction Store1B@VB1 and the write operation instruction Store1B@VB2 and the read operation instruction Load1B@VA1 and the read operation instruction Load1B@VA2, and the write operation instruction Store1B@VB1 and the write operation instruction Store1B@VB2 can be merged into a write operation instruction Store2B@VB1.

[0176] In some other embodiments, it is assumed that the correlation identifier of the array A is the first-type correlation identifier no_alias<0>, and the correlation identifier of the array B is the first-type correlation identifier no_alias<1>.

[0177] Since the addresses of the memory spaces corresponding to the first element A[0], the second element A[1], and the third element A[2] of the array A are continuous, VA0, VA1, and VA2 are continuous addresses, and the read operation instruction Load1B@VA0, the read operation instruction Load1B@VA1, and the read operation instruction Load1B@VA2 can be taken as to-be-merged instructions. Then, whether there is a mergable instruction in the to-be-merged instructions can be determined based on the correlation identifiers of the variables corresponding to the to-be-merged instructions.

[0178] There is a write operation instruction Store1B@VB1 between the read operation instruction Load1B@VA0 and the read operation instruction Load1B@VA1, and the first type of correlation identifier of the variable array A corresponding to the read operation instruction Load1B@VA0 and the read operation instruction Load1B@VA1 is different from the first type of correlation identifier of the variable array B corresponding to the write operation instruction Store1B@VB1. The memory space corresponding to the array A and the memory space corresponding to the array B can have an intersection, that is, the memory space accessed by the write operation instruction Store1B@VB1 can have an intersection with the memory space accessed by the read operation instruction Load1B@VA0 and / or the memory space accessed by the read operation instruction Load1B@VA1. Then, the read operation instruction Load1B@VA0 and the read operation instruction Load1B@VA1 cannot be merged.

[0179] There is no write operation instruction between the read operation instruction Load1B@VA1 and the read operation instruction Load1B@VA2, that is, the read operation instruction Load1B@VA1 and the read operation instruction Load1B@VA2 are consecutive memory access instructions. Then, the read operation instruction Load1B@VA1 and the read operation instruction Load1B@VA2 can be merged.

[0180] Therefore, the read operation instruction Load1B@VA1 and the read operation instruction Load1B@VA2 can be merged into a read operation instruction Load2B@VA1.

[0181] Since the addresses of the memory spaces corresponding to the second element B[1] and the third element B[2] of the array B are consecutive, VB1 and VB2 are consecutive addresses, and the write operation instruction Store1B@VB1 and the write operation instruction Store1B@VB2 can be taken as to-be-merged instructions. Then, whether there is a mergeable instruction in the to-be-merged instructions can be determined based on the correlation identifier of the variable corresponding to the to-be-merged instruction.

[0182] The read operation instruction Load1B@VA1 and the read operation instruction Load1B@VA2 are between the write operation instruction Store1B@VB1 and the write operation instruction Store1B@VB2, and the first type of correlation identifier of the variable array B corresponding to the write operation instruction Store1B@VB1 and the write operation instruction Store1B@VB2 is different from the variable array A corresponding to the read operation instruction Load1B@VA1 and the read operation instruction Load1B@VA2. The memory space corresponding to the array A and the memory space corresponding to the array B can have an intersection, that is, the write operation instruction Store1B@VB1 and / or the write operation instruction Store1B@VB2 can have an intersection with the memory space accessed by the read operation instruction Load1B@VA1 and / or the read operation instruction Load1B@VA2. Therefore, the write operation instruction Store1B@VB1 and the write operation instruction Store1B@VB2 cannot be merged.

[0183] It can be understood that the compiling method provided by the embodiments of the present application can determine the coincidence relationship of the memory spaces corresponding to the variables through the defined correlation identifier, thereby determining the to-be-merged instructions and merging the to-be-merged instructions. The compiling method reduces the number of memory access instructions and reduces the risk of incorrect merging of instructions, thereby reducing the risk of program running errors.

[0184] In some embodiments, before the source program is compiled, the program developer can also perform access identification on the member data in the variables (for example, structure variables) of each composite data type in the source program, so that the compiling device can further determine whether the memory access instructions corresponding to the variables whose correlation identifiers do not indicate that the memory spaces corresponding to the variables must not have an intersection can be merged based on the access identifier in the compiling stage, so as to further reduce the number of memory access instructions.

[0185] The access identifier includes a first access identifier. The member data identified by the first access identifier (or a first access modifier) can only be accessed through the variable of the composite data type corresponding to the member data.

[0186] In some embodiments, the access identifier can also include a second access identifier (or a second access modifier) indicating that the member data can be accessed through the variable of the composite data type corresponding to the member data, or through the variable of another data type other than the variable of the composite data type corresponding to the member data, for example, through the pointer variable of the data type corresponding to the member data.

[0187] For example, for a structure variable s1 defined as struct S{_unique_int a; _unique_int b; _shared_int c;} s1, where _unique_ is the first access modifier and _shared_ is the second access modifier. The member data a and the member data b can only be accessed by a variable of the S type, for example, a pointer variable of the S type struct S* ptr, ptr = &s1, is used to access the member data a and the member data b of the structure variable s1. For example, the member data a of the structure variable s1 can be accessed by any of s1.a, (*ptr).a, ptr->a.

[0188] In some embodiments, in the case that the first type of dependency of the second variable corresponding to the second instruction between the plurality of first instructions is different from the first type of dependency of the first variable corresponding to the plurality of first instructions:

[0189] If the first variable is used to access the member data of the first compound data type variable, that is, the data stored in the memory space corresponding to the first variable is the member data of the first compound data type variable.

[0190] If the access identifier corresponding to the member data accessed by the first variable is the first access modifier, and the first variable is a variable of the first compound data type, and the second variable corresponding to the second instruction is not a variable of the first compound data type, it is determined that the plurality of first instructions can be combined.

[0191] For example, for a structure variable struct S{_unique_int a; _unique_int b; _shared_int c;} s1, a pointer variable struct S* ptr1 and a pointer variable int* ptr2 are defined.

[0192] If there is an instruction in the source program:

[0193] *(ptr2+1) = ptr1->a;

[0194] *(ptr2+2) = ptr1->b;

[0195] The corresponding intermediate representation can be referred to as follows:

[0196] Load1B@ptr1;

[0197] Store1B@ptr2+1;

[0198] Load1B@ptr1+1;

[0199] Store1B@ptr2+2;

[0200] The following describes the process of determining whether the read operation instruction Load1B@ptr1 and the read operation instruction Load1B@ptr1+1 can be merged based on the data types of the pointer variable ptr1 and the pointer variable ptr2 and the access identifiers of the member data accessed by the pointer variable ptr1 and the pointer variable ptr2 in the compilation phase, taking the read operation instruction Load1B@ptr1 and the read operation instruction Load1B@ptr1+1 as examples.

[0201] For example, the data accessed by the read operation instruction Load1B@ptr1 and the read operation instruction Load1B@ptr1+1 is the member data a and the member data b of the structure s1, the access identifiers of the member data a and the member data b are the first access modifier (_unique_), the data type of the pointer variable ptr1 is the data type (S) corresponding to the structure s1, and the data type of the pointer variable ptr2 is the integer type (int).

[0202] It can be understood that, since the access identifiers of the member data a and the member data b are the first access modifier (_unique), the member data a and the member data b can only be accessed by the variable of the data type corresponding to the structure s1. The write operation instruction Store1B@ptr2+1 is accessed by the integer pointer variable ptr2, and thus the pointer variable ptr2 cannot access the member data a and the member data b. That is, the write operation instruction Store1B@ptr2+1 is definitely not an operation of writing data to the memory space storing the member data a and / or the member data b, the memory space corresponding to the pointer variable ptr2 and the memory space corresponding to the pointer variable ptr1 definitely have no intersection, and the read operation instruction Load1B@ptr1 and the read operation instruction Load1B@ptr1+1 corresponding to the pointer variable ptr1 can be merged.

[0203] It can be understood that, by defining the access identifier, it can be determined whether the memory access instructions of the plurality of member data in the variable of the composite data type can be merged, thereby reducing the number of accesses to the memory by the processor, and further improving the efficiency of the processor in running the executable file.

[0204] It can be understood that the above only takes the first instruction as an example of the two first type of memory access instructions accessing adjacent memory space, and describes the method of determining whether the first instruction can be merged. In other embodiments, the first instruction can be a plurality of first type of memory access instructions accessing contiguous memory space. If there is no second instruction between any two adjacent first instructions in the plurality of first instructions, the plurality of first instructions can be merged. It can be understood that each two adjacent first instructions in the plurality of first instructions can be determined respectively, and the first instructions that can be merged are added to the set of instructions to be merged, and then the first instructions in the set of instructions to be merged are merged. The specific process of determining whether the first instruction can be merged is not limited in the present application.

[0205] Exemplarily, FIG. 5 shows a flowchart of a compiling method according to an embodiment of the present application. It can be understood that the execution subject of the flowchart shown in FIG. 5 is the electronic device 100. The electronic device 100 can be a compiling device, or a device including a compiler, or a device including a compiling apparatus. In order to simplify the description, the execution subject will not be repeatedly described when introducing the flowchart shown in FIG. 5.

[0206] As shown in FIG. 5, the flowchart includes but is not limited to:

[0207] S501: Obtain a first source program.

[0208] In some embodiments, the first source program includes an access identifier of the composite type data and the member data of the composite type data, and the access identifier is used to indicate an access manner of the member data.

[0209] For example, the composite type data includes a first member data, and the first member data includes a first access modifier (for example, _unique_), which is used to indicate that the first member data is accessed only through a first access manner. For example, the member data identified by the first access modifier can be accessed only through a variable (a first variable or a variable of a first type) of a composite data type corresponding to the member data.

[0210] For another example, the composite type data further includes a second member data, and the second member data does not include the first access modifier, but includes a second access modifier (for example, _shared_), which is used to indicate that the second member data is not accessed through the first access manner. For example, the member data identified by the second access modifier can be accessed through a variable of a composite data type corresponding to the member data, or through a variable of another type except the variable of the composite data type corresponding to the member data, for example, through a pointer variable of the data type corresponding to the member data.

[0211] It can be understood that the above only takes the first access modifier and the second access modifier as an example to describe the access identifier, and in other embodiments, the access identifier can also be in other forms, which are not limited in the present application.

[0212] In other embodiments, the first source program includes a relevance identifier of a variable, and the storage spaces corresponding to the variables with the same relevance identifier do not have an intersection.

[0213] It can be understood that the relevance identifier of the variable is used to indicate whether there is another variable corresponding to the identified variable whose memory space has an intersection. That is, the relevance identifier of the variable is used to indicate whether there is an intersection between the memory spaces corresponding to multiple variables. Among them, the intersection between the memory spaces corresponding to multiple variables includes but is not limited to: the memory spaces corresponding to multiple variables completely coincide; the memory spaces corresponding to multiple variables partially coincide; there is a containing relationship between the memory spaces corresponding to multiple variables, that is, the memory space corresponding to a certain variable contains the memory space corresponding to another variable, etc. The present application does not make specific limitations.

[0214] It can be understood that if the marked variable is a pointer variable, the memory space corresponding to the variable is the memory space pointed to by the pointer variable, that is, the coincidence relationship of the memory space pointed to by the pointer variable can be determined through the relevance identifier of the pointer variable. If the marked variable is a non-pointer variable, the memory space corresponding to the non-pointer variable is the memory space storing the non-pointer variable, that is, the coincidence relationship of the memory space storing the non-pointer variable can be determined through the relevance identifier of the non-pointer variable.

[0215] S502: Determine at least two first instructions satisfying a first processing condition from a plurality of memory access instructions corresponding to the first source program.

[0216] In some embodiments, the electronic device 100 generates a first intermediate representation based on the first source program, wherein the first intermediate representation includes a plurality of instructions; determines a plurality of memory access instructions from the plurality of instructions in the first intermediate representation, and determines at least two first instructions satisfying a first processing condition from the plurality of memory access instructions.

[0217] Among them, the form of the first intermediate representation includes but is not limited to: postfix representation, graph representation, three-address code, bottom virtual machine intermediate representation, assembly code representation form, etc.

[0218] In some embodiments, the first processing condition can be that the first instruction is an instruction for accessing the first member data through the first access manner, and the types of the at least two first instructions are the same.

[0219] In some embodiments, the first processing condition further comprises: the at least two first instructions are consecutive memory access instructions, or there is at least one second instruction between the at least two first instructions.

[0220] That is, the first processing condition can be: the first instruction is an instruction for accessing the first member data by the first access manner, and the at least two first instructions are of the same type, and the at least two first instructions are consecutive memory access instructions; or the first instruction is an instruction for accessing the first member data by the first access manner, and the at least two first instructions are of the same type, and there is at least one second instruction between the at least two first instructions.

[0221] In other embodiments, if the composite type data further comprises second member data, and the second member data does not comprise the first access identifier, and there is at least one second instruction between the at least two first instructions, the first processing condition can further be: the first instruction is an instruction for accessing the first member data by the first access manner, and the at least two first instructions are of the same type, and the second instruction is a memory access instruction that does not access the second member data by the first access manner.

[0222] In some embodiments, if the type of the first instruction is a read operation instruction, the first processing condition further comprises that the types of the first instruction and the second instruction are different. That is, the first instruction is a read operation instruction, and the second instruction is a write operation instruction; or the first instruction is a write operation instruction, and the second instruction is a read operation instruction.

[0223] S503: performing first processing on the at least two first instructions, and obtaining a first target code file.

[0224] In some embodiments, the electronic device 100 can directly generate the first target code file based on the first intermediate representation.

[0225] In other embodiments, the electronic device 100 can also perform first processing on the plurality of first instructions to obtain a second intermediate representation, and convert the second intermediate representation into target code to obtain the first target code file.

[0226] It can be understood that the first processing includes but is not limited to merging processing, deletion processing, and other processing modes. The processing mode of the first processing will be described in detail below, and the present application will not be repeated here.

[0227] It can be understood that the number of memory access instructions in the first target code file is less than the number of memory access instructions in the second target code file, and the second target code file is a target code file obtained by not performing first processing on the memory access instructions.

[0228] It can be understood that, in some embodiments, if the first processing condition is determined based on the access identifier from the first source program corresponding to the plurality of memory access instructions, the electronic device 100 can further determine at least two third instructions in the plurality of memory access instructions corresponding to the first source program that do not satisfy the first processing condition and satisfy a second processing condition based on the correlation identifier, perform the first processing on the at least two third instructions, and obtain the first target code file. The second processing condition can be that the at least two third instructions correspond to a third variable, there is at least one fourth instruction corresponding to a fourth variable between the at least two third instructions, and the storage space corresponding to the fourth variable does not intersect with the storage space corresponding to the third variable.

[0229] It can be understood that, in some embodiments, if the first processing condition is determined based on the access identifier from the first source program corresponding to the plurality of memory access instructions, the electronic device 100 can further determine at least two third instructions in the plurality of memory access instructions corresponding to the first source program that do not satisfy the first processing condition and satisfy a second processing condition based on the correlation identifier, perform the first processing on the at least two third instructions, and obtain the first target code file. The second processing condition can be that the at least two third instructions correspond to a third variable, there is at least one fourth instruction corresponding to a fourth variable between the at least two third instructions, and the storage space corresponding to the fourth variable does not intersect with the storage space corresponding to the third variable.

[0230] It can be understood that, in some embodiments, if the first processing condition is determined based on the access identifier from the first source program corresponding to the plurality of memory access instructions, the electronic device 100 can further determine at least two third instructions in the plurality of memory access instructions corresponding to the first source program that do not satisfy the first processing condition and satisfy a second processing condition based on the correlation identifier, perform the first processing on the at least two third instructions, and obtain the first target code file. The second processing condition can be that the at least two third instructions correspond to a third variable, there is at least one fourth instruction corresponding to a fourth variable between the at least two third instructions, and the storage space corresponding to the fourth variable does not intersect with the storage space corresponding to the third variable.

[0231] In order to better understand the technical solutions of the embodiments of the present application, some technical solutions of the present application will be described in detail below with reference to the accompanying drawings.

[0232] Embodiment 1

[0233] The embodiments of the present application also provide a compiling method, which determines memory access instructions satisfying a processing condition based on access identifiers of member data in variables of each composite data type in a source program, and performs merging and / or deletion on the memory access instructions satisfying the condition to reduce the number of memory access instructions.

[0234] Exemplarily, FIG. 6 shows a flowchart of a compiling method based on access identifiers according to an embodiment of the present application. It can be understood that the execution subject of the flowchart shown in FIG. 6 is the electronic device 100. The electronic device 100 can be a compiling device, a device including a compiler, or a device including a compiling apparatus. In order to simplify the description, the execution subject will not be repeatedly described when introducing the flowchart shown in FIG. 6.

[0235] As shown in FIG. 6, the flow includes but is not limited to:

[0236] S601: Obtain a first source program, wherein the first source program includes an access identifier of member data of a composite data type, and the access identifier is used to indicate an access manner of the member data.

[0237] The access identifier of the member data of the composite type data is used to indicate the access manner of the member data.

[0238] In some embodiments, the access identifier can be a first access modifier. The member data identified by the first access modifier (for example, _unique_) can be accessed only by a first access manner. For example, the member data identified by the first access modifier can be accessed only by a variable of a composite data type to which the member data corresponds. Or for example, the member data identified by the first access modifier can be accessed only by a variable to which the member data corresponds.

[0239] In other embodiments, the access identifier can be a first access modifier (for example, _unique_) and a second access modifier (for example, _shared_). The member data identified by the second access modifier can be accessed by a variable of a composite data type to which the member data corresponds, or by a variable of another type other than the variable of the composite data type to which the member data corresponds, for example, by a pointer variable of a data type to which the member data corresponds.

[0240] For example, the composite type data includes first member data, and the first member data includes a first access modifier. The composite type data further includes second member data, and the second member data does not include the first access modifier, for example, includes a second access modifier.

[0241] Exemplarily, it is assumed that the source program includes a definition of a composite data type s_type:

[0242] typedef struct{

[0243] _unique_UINT32a;

[0244] _unique_UINT32b;

[0245] _shared_UINT32c

[0032] ;

[0246] }s_type;

[0247] The s_type type structure variable includes a 32-bit integer type member data a, a 32-bit integer type member data b, and a 32-bit integer type member data array c, and the array c includes 32 elements. The member data a and the member data b can be accessed only through the s_type type pointer variable, and the member data array c can be accessed through the 32-bit integer type pointer variable.

[0248] It can be understood that the above only takes the first access modifier and the second access modifier as an example to describe the access identifier, and in other embodiments, the access identifier can also be in other forms, which are not limited in the application.

[0249] It can be understood that the above only takes the first access way as an example to describe the technical solutions in the embodiments of the application, that is, the first member data is accessed through the first type of variable. It can be understood that the first access way can also be to access the first member data through the variable corresponding to the member data identified by the first access modifier, that is, to access the first member data through the first variable. For example, in some embodiments, if the access modifier corresponding to the 32-bit integer type member data array c is the first access modifier, the member data c or the elements in the member data c can only be accessed through s_type.c or through the same pointer variable (for example, ptrC). The application does not make any limitation.

[0250] S602: converting the first source program into a first intermediate representation, wherein the first intermediate representation includes a plurality of instructions, and each instruction has a corresponding variable.

[0251] The form of the first intermediate representation includes but is not limited to: postfix representation, graph representation, three-address code, bottom virtual machine intermediate representation, assembly code representation form, etc.

[0252] Exemplarily, it is assumed that the source program includes the definition of the function foo:

[0253] UINT32 foo (s_type *ptrA, UINT32 *ptrB) {

[0254] ptrB[0] = ptrA->a;

[0255] ptrB[1] = ptrA->b;

[0256] …

[0257] }

[0258] The foo function includes two formal parameters: a pointer variable ptrA of the s_type type and a pointer variable ptrB of the 32-bit integer data type.

[0259] The ptrB[0] = ptrA->a and ptrB[1] = ptrA->b in the foo function are converted into the intermediate representation as follows:

[0260] Load4B@ptrA;

[0261] Store4B@ptrB;

[0262] Load4B@ptrA+1;

[0263] Store4B@ptrB+1;

[0264] S603: Based on the access identifier of the member data of the composite data type in the first source program, a plurality of first instructions that satisfy a first processing condition are determined from the plurality of memory access instructions of the first intermediate representation.

[0265] In some embodiments, the first processing condition can be that the types of the plurality of first instructions are the same, the plurality of first instructions are instructions that access the first member data through the first access manner, and the plurality of first instructions are consecutive memory access instructions.

[0266] In some embodiments, if the composite type data further includes second member data, and the second member data does not include the first access identifier, and there is at least one second instruction between the at least two first instructions, the first processing condition can further be that the types of the plurality of first instructions are the same, the first instruction is a memory access instruction that accesses the first member data through the first access manner, and the second instruction is a memory access instruction that does not access the second member data through the first access manner.

[0267] In some embodiments, if the first instruction corresponds to a read operation instruction, the first processing condition can further be that the types of the plurality of first instructions are the same, the plurality of first instructions are instructions that access the first member data through the first access manner, the plurality of first instructions are consecutive memory access instructions, and the types of the first instruction and the second instruction are different; or the types of the plurality of first instructions are the same, the first instruction is a memory access instruction that accesses the first member data through the first access manner, the second instruction is a memory access instruction that does not access the second member data through the first access manner, and the types of the first instruction and the second instruction are different.

[0268] For example, if the first variable corresponding to the first instruction is used to access the first member data of the first composite data, the data type of the second variable corresponding to the second instruction between the plurality of first instructions is a data type different from the first composite data type, and the access identifier of the first member data accessed by the first instruction is the first access modifier, the electronic device 100 can determine that the plurality of first instructions can be merged.

[0269] For example, taking the intermediate representation corresponding to the above foo function as an example, the pointer variable ptrA corresponding to the read operation instruction Load4B@ptrA and the read operation instruction Load4B@ptrA+1 is used to access the member data a and the member data b in the structure of the s_type type, and the access identifiers of the member data a and the member data b are both the first access modifier. Moreover, the data type of the pointer variable ptrA corresponding to the read operation instruction Load4B@ptrA and the read operation instruction Load4B@ptrA+1 is the s_type type. The data type of the pointer variable ptrB corresponding to the write operation instruction Store4B@ptrB between the read operation instruction Load4B@ptrA and the read operation instruction Load4B@ptrA+1 is a 32-bit integer. Therefore, it can be determined that the memory space accessed by the write operation instruction Store4B@ptrB and the memory space accessed by the read operation instruction Load4B@ptrA and / or the read operation instruction Load4B@ptrA+1 do not exist intersection. The electronic device 100 can determine that the read operation instruction Load4B@ptrA and the read operation instruction Load4B@ptrA+1 can be merged, for example, the merged read operation instruction Load8B@ptrA can be obtained.

[0270] S604: Perform first processing on the plurality of first instructions, and obtain a first target code file.

[0271] It can be understood that the first processing includes but is not limited to merging processing, deleting processing and the like. The processing mode of the first processing will be described in detail below, and the present application will not be repeated here.

[0272] Specifically, reference can be made to the related description in S503 described above, and the present application will not be repeated here.

[0273] It can be understood that the compiling method provided by the embodiments of the present application can determine the first instruction satisfying the first processing condition through the defined access identifier, and merge and / or delete the first instruction. The compiling method reduces the number of memory access instructions, reduces the risk of incorrect merging and / or incorrect deletion of instructions, and further reduces the risk of program running errors.

[0274] Embodiment 2

[0275] The embodiment of the present application further provides a compiling method, based on the access identifier of the member data of each composite data type in the source program and the correlation identifier of the variables, determines the memory access instruction satisfying the processing condition, and merges and / or deletes the memory access instruction satisfying the processing condition, so as to further reduce the number of memory access instructions.

[0276] Exemplarily, FIG. 7 shows a flowchart of a compiling method based on an access identifier and a correlation identifier according to the embodiment of the present application. It can be understood that the execution subject of the flowchart shown in FIG. 7 is the electronic device 100. In order to simplify the description, the execution subject will not be repeatedly described in the following introduction of the flowchart shown in FIG. 7.

[0277] As shown in FIG. 7, the flowchart includes but is not limited to the following steps.

[0278] S701: Obtain a first source program, wherein the first source program includes the correlation identifier of a variable and the access identifier of the member data of a composite type data.

[0279] The correlation identifier of the variable is used to indicate whether there is another variable corresponding to the identified variable and having an intersection with the memory space.

[0280] The intersection between the memory spaces corresponding to the plurality of variables includes but is not limited to: the memory spaces corresponding to the plurality of variables completely coincide; the memory spaces corresponding to the plurality of variables partially coincide; the memory spaces corresponding to the plurality of variables have a containing relationship, i.e., the memory space corresponding to a certain variable contains the memory space corresponding to another variable, etc. The present application does not make a specific limitation on this.

[0281] In some embodiments, the correlation identifier can be the aforementioned first type of correlation identifier, the memory spaces corresponding to the variables having the same first type of correlation identifier do not have an intersection, and the coincidence relationship of the memory spaces corresponding to the variables having different first type of correlation identifiers is unknown, i.e., there can be an intersection or there can not be an intersection.

[0282] In other embodiments, the correlation identifier can also be the aforementioned second type of correlation identifier, the coincidence relationship of the memory spaces corresponding to the variables having the same second type of correlation identifier is unknown, i.e., there can be an intersection or there can not be an intersection, and the memory spaces corresponding to the variables having different second type of correlation identifiers do not have an intersection.

[0283] It can be understood that if the marked variable is a pointer variable, the memory space corresponding to the variable is the memory space pointed to by the pointer variable, i.e., the coincidence relationship of the memory space pointed to by the pointer variable can be determined through the relevance identifier of the pointer variable. If the marked variable is a non-pointer variable, the memory space corresponding to the non-pointer variable is the memory space storing the non-pointer variable, i.e., the coincidence relationship of the memory space storing the non-pointer variable can be determined through the relevance identifier of the non-pointer variable.

[0284] It can be understood that the above only takes the first type of relevance identifier and the second type of relevance identifier as examples to describe the relevance identifier, and in other embodiments, the relevance identifier can also be in other forms, which is not limited in the present application.

[0285] In some embodiments, the access identifier of the member data of the composite type data is used to indicate the access mode of the member data. The access identifier can refer to the above description in FIG. 5, which will not be repeated here.

[0286] Exemplarily, it is assumed that the source program includes the definition of a composite data type s_type:

[0287] typedef struct{

[0288] UINT32a;

[0289] UINT32b;

[0290] UINT32c

[0032] ;

[0291] }s_type;

[0292] Wherein, the structure variable of the s_type type includes the member data a of the 32-bit integer data type, the member data b of the 32-bit integer data type, and the member data array c of the 32-bit integer data type, and the array c includes 32 elements.

[0293] It is assumed that the source program includes the definition of a function foo:

[0294] UINT32foo(s_type*no_alias<0>ptrA,UINT32*no_alias<0>ptrB){

[0295] ptrB[0]=ptrA->a;

[0296] ptrB[1]=ptrA->b;

[0297] …

[0298] }

[0299] The foo function includes two formal parameters: a pointer variable ptrA of the s_type type and a pointer variable ptrB of the 32-bit integer data type. The correlation identifier of the pointer variable ptrA is the first correlation identifier no_alias<0>, and the correlation identifier of the pointer variable ptrB is the first correlation identifier no_alias<0>.

[0300] S702: converting the first source program into a first intermediate representation, where the first intermediate representation includes a plurality of instructions, and each instruction has a corresponding variable.

[0301] The form of the first intermediate representation includes but is not limited to: postfix representation, graph representation, three-address code, bottom virtual machine intermediate representation, assembly code representation form, etc.

[0302] For example, taking the foo function in S701 above as an example, ptrB[0] = ptrA->a and ptrB[1] = ptrA->b in the foo function are converted into the intermediate representation as follows:

[0303] Load4B@ptrA;

[0304] Store4B@ptrB;

[0305] Load4B@ptrA+1;

[0306] Store4B@ptrB+1.

[0307] S703: determining a plurality of first instructions satisfying a first processing condition based on the access identifier of the member data of the composite type data in the first source program, and determining a plurality of third instructions satisfying a second processing condition based on the correlation identifier of the variable in the first source program.

[0308] In some embodiments, the electronic device 100 determines, based on the access identifier of the member data of the composite type data in the first source program, a plurality of first instructions satisfying a first processing condition from a plurality of instructions of the first intermediate representation. The first processing condition and the determination method of the first instruction can be referred to the related description in the above FIG. 5, which will not be repeated here.

[0309] In some embodiments, the electronic device 100 determines, based on the correlation identifier of the variable in the first source program, a plurality (at least two) of third instructions not satisfying the first processing condition and satisfying the second processing condition from the plurality of instructions of the first intermediate representation.

[0310] In some embodiments, the second processing condition can be that the plurality of third instructions correspond to a third variable, there is at least one fourth instruction corresponding to a fourth variable between the plurality of third instructions, and the memory space corresponding to the fourth variable does not intersect with the memory space corresponding to the third variable.

[0311] In other embodiments, the second processing condition can also be that the plurality of third instructions are of the same type, the variable corresponding to the plurality of third instructions is the third variable, there is at least one fourth instruction between the plurality of third instructions, and the memory space corresponding to the fourth variable does not intersect with the memory space corresponding to the third variable.

[0312] In other embodiments, the third instruction corresponds to a read operation instruction, and the second processing condition can also be that the plurality of third instructions are of the same type, the variable corresponding to the plurality of third instructions is the third variable, there is at least one fourth instruction between the plurality of third instructions, the type of the fourth instruction is different from the type of the third instruction, and the memory space corresponding to the fourth variable does not intersect with the memory space corresponding to the third variable.

[0313] It can be understood that whether the memory spaces of the variables intersect can be determined based on the correlation identifier of the variable. The correlation identifier can be a first type of correlation identifier or a second type of correlation identifier, which will not be described herein.

[0314] For example, taking the intermediate representation corresponding to the foo function described above as an example, there is a write operation instruction Store4B@ptrB between the read operation instruction Load4B@ptrA and the read operation instruction Load4B@ptrA+1. The member data a accessed by the read operation instruction Load4B@ptrA and the member data b accessed by the read operation instruction Load4B@ptrA+1 do not include access modifiers. Therefore, the electronic device 100 cannot determine whether the read operation instruction Load4B@ptrA and the read operation instruction Load4B@ptrA+1 can be merged based on the access identifier of the member data of the composite type data.

[0315] In other embodiments, in the case that the first instruction cannot be determined to be merged based on the access identifier of the member data of the composite type data described above, the electronic device 100 can further determine the third instruction that can be merged based on the correlation identifier of the variable.

[0316] Still taking the intermediate representation corresponding to the foo function above as an example, the correlation identifier of the variable ptrA corresponding to the read operation instruction Load4B@ptrA is the first type of correlation identifier no_alias<0>, and the correlation identifier of the variable ptrA corresponding to the read operation instruction Load4B@ptrA+1 is the first type of correlation identifier no_alias<0>. That is, the variable corresponding to the read operation instruction Load4B@ptrA and the variable corresponding to the read operation instruction Load4B@ptrA+1 have the same first type of correlation identifier, and the memory space accessed by the read operation instruction Load4B@ptrA and the memory space accessed by the read operation instruction Load4B@ptrA+1 do not overlap.

[0317] The read operation instruction Load4B@ptrA and the read operation instruction Load4B@ptrA+1 have the write operation instruction Store4B@ptrB therebetween, and the correlation identifier of the variable ptrB corresponding to the write operation instruction Store4B@ptrB is the first type of correlation identifier no_alias<0>. That is, the variable corresponding to the write operation instruction Store4B@ptrB, the variable corresponding to the read operation instruction Load4B@ptrA, and the variable corresponding to the read operation instruction Load4B@ptrA+1 have the same first type of correlation identifier. The memory space accessed by the write operation instruction Store4B@ptrB does not overlap with the memory space accessed by the read operation instruction Load4B@ptrA and / or the memory space accessed by the read operation instruction Load4B@ptrA+1, and the electronic device 100 can determine that the read operation instruction Load4B@ptrA and the read operation instruction Load4B@ptrA+1 can be merged.

[0318] S704: performing first processing on the plurality of first instructions and the plurality of third instructions respectively, and obtaining a first target code file.

[0319] In some embodiments, the electronic device 100 can perform first processing on the plurality of first instructions and the plurality of third instructions respectively, and directly generate a first target code file.

[0320] In other embodiments, the electronic device 100 can also perform first processing on the plurality of first instructions and the plurality of third instructions respectively, obtain a second intermediate representation, and convert the second intermediate representation into a target code to obtain a first target code file.

[0321] For example, if the original language corresponding to the source program is a high-level language, and the target language file is a machine language, the electronic device 100 generates an assembly instruction file based on the intermediate representation after performing first processing, and then performs assembly, linking, and other processes on the assembly instruction file to obtain an executable file, i.e., a target code file.

[0322] Or for example, if the source program corresponds to an assembly language, and the target language file is a machine language, the electronic device 100 generates an executable file, i.e., a target code file, based on the intermediate representation after the first processing.

[0323] Or for example, if the source program corresponds to a high-level language, and the target language is an assembly language, the electronic device 100 generates an assembly instruction file, i.e., a target code file, based on the intermediate representation after the first processing.

[0324] It can be understood that the first processing includes but is not limited to merging processing, deletion processing and other processing modes.

[0325] In the following, the first processing mode and the first processing condition are further described by taking the memory access instruction subjected to the first processing as an example, which is the first instruction satisfying the first processing condition.

[0326] In some embodiments, the first processing corresponds to merging processing, and the first processing condition further includes that the memory space accessed by the first instruction is a continuous memory space. That is, the merging condition can be that the memory space accessed by the plurality of first instructions is continuous, the types of the plurality of first instructions are the same, the memory space addresses accessed by the plurality of first instructions are continuous, and the plurality of first instructions are instructions for accessing the first member data by the first access mode.

[0327] For example, assuming that the virtual address corresponding to the first element A[0] of the array A is VA0, and the virtual address corresponding to the second element A[1] of the array A is VA1, the read operation instruction Load1B@VA0 and the read operation instruction Load1B@VA1 access continuous memory space. Then the compiling device can merge the read operation instruction Load1B@VA0 and the read operation instruction Load1B@VA1 into a new read operation instruction Load2B@VA0.

[0328] In other embodiments, if the composite type data further includes second member data, and the second member data does not include the first access identifier, and there is at least one second instruction between the at least two first instructions, and the first processing corresponds to merging processing, the first processing condition further includes that the memory space accessed by the plurality of first instructions is data corresponding to the same variable stored in the memory. That is, the merging condition can be that the types of the plurality of first instructions are the same, the memory space accessed by the plurality of first instructions is data corresponding to the same variable stored in the memory, the first instruction is a memory access instruction for accessing the first member data by the first access mode, and the second instruction is a memory access instruction for not accessing the second member data by the first access mode.

[0329] For example, assuming that the first element A[0] of the array A corresponds to a virtual address VA0, and the third element A[2] of the array A corresponds to a virtual address VA2, the read operation instruction Load1B@VA0 and the read operation instruction Load1B@VA2 access the data stored in the memory space corresponding to the same variable, i.e., the array A. Then, the compiling device can combine the read operation instruction Load1B@VA0 and the read operation instruction Load1B@VA2 into a new read operation instruction Load3B@VA0.

[0330] It can be understood that, in the embodiments of the present application, in addition to the memory access instructions accessing the continuous memory space can be combined, the memory access instructions accessing the non-continuous memory space but storing the data corresponding to the same variable can also be combined, so that the number of memory access instructions can be further reduced, thereby improving the running efficiency of the application program corresponding to the source program.

[0331] The combining processing can be: combining the multiple first instructions satisfying the first processing condition into one fifth instruction, and the memory space accessed by the fifth instruction including the memory spaces accessed by the multiple first instructions. For example, the memory space accessed by the fifth instruction is the set of the memory spaces accessed by the multiple first instructions.

[0332] Alternatively, the combining processing can also be: combining the multiple first instructions satisfying the processing condition into multiple sixth instructions, the memory space accessed by the sixth instruction including the memory spaces accessed by the multiple first instructions, and the number of the sixth instructions being less than the number of the first instructions.

[0333] In some embodiments, corresponding to the first processing being the deleting processing, the first processing can be: in the case that there are M seventh instructions of the same type and accessing the first memory space in the first intermediate representation, and the memory spaces accessed by the other instructions between the M seventh instructions have no intersection with the memory space accessed by the seventh instruction, deleting N seventh instructions, where M is an integer greater than 1, and N is a positive integer less than M.

[0334] In some embodiments, if the type of the seventh instruction is a read operation instruction, there is an eighth instruction in the N seventh instructions that reads data in the first storage space to a second storage space, and the second storage space is different from the storage space to which data in the first storage space is read by the M-N seventh instructions other than the N seventh instructions in the M seventh instructions, the address information of the second storage space in a ninth instruction that reads data in the second storage space can be replaced by the address information of the storage space to which data in the first storage space is read by any one of the M-N seventh instructions, where the ninth instruction is an instruction in the first intermediate representation after the eighth instruction and before the next instruction that writes data to the second storage space, and the address information of the storage space includes a register name; or, the data read by a tenth instruction that reads data in the second storage space can be replaced by data in the first storage space, where the tenth instruction is an instruction in the first intermediate representation after the eighth instruction and before the next instruction that writes data to the second storage space.

[0335] For example, instruction m is a read operation instruction that reads data in memory space P (the first storage space) to register R0, instruction n is a read operation instruction that reads data in memory space P to register R1 (the second storage space), and instruction n is deleted, then register R1 in each instruction in the first intermediate representation after instruction n and before the next instruction that writes data to register R1 needs to be replaced by register R0, so that the semantics in the first intermediate representation is correct.

[0336] In some embodiments, if the first instruction is a write operation instruction, the deletion processing can be that N seventh instructions in the first M-1 seventh instructions in the M seventh instructions are deleted. That is, the last executed seventh instruction in the plurality of seventh instructions is retained, and at least one seventh instruction other than the last executed seventh instruction in the plurality of seventh instructions is deleted.

[0337] In summary, the compiling method provided by the embodiments of the present application can determine the first instruction that meets the merging condition based on the access identifier of the member data in each variable of each composite data type in the source program, and determine the third instruction that meets the merging condition through the correlation identifier, so as to determine the coincidence relationship of the memory space corresponding to the variable, thereby reducing the number of memory access instructions.

[0338] Embodiment 3

[0339] The embodiments of the present application also provide a compiling method that determines the memory access instruction that meets the processing condition based on the correlation identifier of the variable in the source program, and merges and / or deletes the memory access instruction that meets the condition, so as to reduce the number of memory access instructions.

[0340] Exemplarily, FIG. 8 shows a flowchart of a compiling method based on variable correlation identification according to an embodiment of the present application. It can be understood that the execution subject of the flowchart shown in FIG. 8 is the electronic device 100. The electronic device 100 can be a compiling device, or a device including a compiler, or a device including a compiling apparatus. For the sake of simplicity, the execution subject will not be repeatedly described below when introducing the flowchart shown in FIG. 8.

[0341] As shown in FIG. 8, the flowchart includes but is not limited to the following steps.

[0342] S801: obtaining a first source program, wherein the first source program includes a correlation identification of a variable.

[0343] The correlation identification of the variable is used to indicate whether there is another variable corresponding to the identified variable, which has an intersection with the memory space of the identified variable. That is, the correlation identification of the variable is used to indicate whether there is an intersection between the memory spaces corresponding to multiple variables. The original language corresponding to the first source program includes but is not limited to a high-level language, an assembly language, etc.

[0344] In some embodiments, the correlation identification can be the aforementioned first type of correlation identification. The memory spaces corresponding to the variables with the same first type of correlation identification have no intersection, and the intersection relationship of the memory spaces corresponding to the variables with different first type of correlation identification is unknown, i.e., there can be an intersection or there can be no intersection.

[0345] In other embodiments, the correlation identification can also be the aforementioned second type of correlation identification. The intersection relationship of the memory spaces corresponding to the variables with the same second type of correlation identification is unknown, i.e., there can be an intersection or there can be no intersection, and the memory spaces corresponding to the variables with different second type of correlation identification have no intersection.

[0346] It can be understood that the above only takes the first type of correlation identification and the second type of correlation identification as examples to illustrate the correlation identification. In other embodiments, the correlation identification can also be in other forms, which are not limited by the present application.

[0347] S802: converting the first source program into a first intermediate representation, wherein the first intermediate representation includes multiple instructions, and the instructions have corresponding variables.

[0348] The form of the first intermediate representation includes but is not limited to a postfix representation, a graph representation, a three-address code, a bottom virtual machine intermediate representation, an assembly code representation form, etc.

[0349] S803: determining, based on the correlation identification of the variable in the first source program, multiple first instructions in the multiple instructions of the first intermediate representation that satisfy a first processing condition.

[0350] In some embodiments, the first processing condition can be that the types of the plurality of first instructions are the same, the plurality of first instructions correspond to a first variable, and the plurality of first instructions are consecutive memory access instructions.

[0351] In other embodiments, the first processing condition can also be that the types of the plurality of first instructions are the same, the plurality of first instructions correspond to a first variable, there is at least one second instruction between the plurality of first instructions, and a memory space of a second variable corresponding to the second instruction does not intersect with a memory space of the first variable corresponding to the plurality of first instructions.

[0352] In other embodiments, the first processing condition can also be that the types of the plurality of first instructions are the same, the plurality of first instructions correspond to a first variable, there is at least one second instruction between the plurality of first instructions, the type of the second instruction is different from the type of the first instruction, and a memory space of a second variable corresponding to the second instruction does not intersect with a memory space of the first variable corresponding to the plurality of first instructions.

[0353] It can be understood that whether the memory spaces of the variables intersect can be determined based on a correlation identifier of the variables. The correlation identifier can be a first type of correlation identifier or a second type of correlation identifier, which will not be described herein.

[0354] S804: performing first processing on the plurality of first instructions to obtain a first target code file.

[0355] In some embodiments, the electronic device 100 can directly generate the first target code file based on the intermediate representation.

[0356] In other embodiments, the electronic device 100 can also obtain a second intermediate representation after performing the first processing on the plurality of first instructions, and convert the second intermediate representation into a target code to obtain the first target code file.

[0357] It can be understood that the first processing includes, but is not limited to, merging processing, deletion processing, and the like.

[0358] In some embodiments, corresponding to the first processing being merging processing, the first processing condition further includes that the memory space accessed by the first instruction is a continuous memory space. That is, the merging condition can be that the types of the plurality of first instructions are the same, the memory space accessed by the plurality of first instructions is continuous, there is at least one second instruction between the plurality of first instructions, the type of the second instruction is different from the type of the first instruction, and a memory space of a second variable corresponding to the second instruction does not intersect with a memory space of a first variable corresponding to the plurality of first instructions.

[0359] In some embodiments, the first processing corresponds to a merging processing, and the processing condition further comprises that the memory spaces accessed by the plurality of first instructions are memory spaces storing data corresponding to a same variable. That is, the merging condition can be that the types of the plurality of first instructions are the same, the memory spaces accessed by the plurality of first instructions are memory spaces storing data corresponding to a same variable, there are at least one second instruction between the plurality of first instructions, the type of the second instruction is different from the first instructions, and the memory space of a second variable corresponding to the second instruction does not intersect with the memory space of a first variable corresponding to the plurality of first instructions.

[0360] In some embodiments, the merging processing can be that the plurality of first instructions satisfying the processing condition are merged into one third instruction, and the memory space accessed by the third instruction comprises the memory spaces accessed by the plurality of first instructions. For example, the memory space accessed by the third instruction is a set of the memory spaces accessed by the plurality of first instructions.

[0361] Alternatively, the merging processing can also be that the plurality of first instructions satisfying the processing condition are merged into a plurality of fourth instructions, the memory space accessed by the fourth instructions comprises the memory spaces accessed by the plurality of first instructions, and the number of the fourth instructions is less than the number of the first instructions.

[0362] In some embodiments, the first processing corresponds to a deleting processing, and the processing condition further comprises that the memory spaces accessed by the first instructions are the same memory space. That is, the merging condition can be that the types of the M first instructions are the same, the memory spaces accessed by the M first instructions are the same, there are at least one second instruction between the M first instructions, the type of the second instruction is different from the first instructions, and the memory space of a second variable corresponding to the second instruction does not intersect with the memory space of a first variable corresponding to the plurality of first instructions. Wherein, M is an integer greater than 1.

[0363] In some embodiments, the deleting processing can be that N first instructions are deleted, wherein N is a positive integer less than M.

[0364] In some embodiments, if the first instruction is a read operation instruction and the second instruction is a write operation instruction, the deleting processing can be that there is a fifth instruction in the N first instructions that reads data in a first memory space to a second memory space, the second memory space is different from the memory space to which data in the first memory space is read by the M-N first instructions other than the N first instructions in the M first instructions; and the address information of the second memory space in a sixth instruction that reads data in the second memory space is replaced by the address information of the memory space to which data in the first memory space is read by any one of the M-N first instructions, wherein the sixth instruction is an instruction in the first intermediate representation after the fifth instruction and before the next instruction that writes data to the second memory space, and the address information of the memory space comprises a register name.

[0365] In some embodiments, if the first instruction is a write operation instruction and the second instruction is a read operation instruction, the deleting processing can be: deleting N first instructions in the first M first instructions. That is, the last executed first instruction in the plurality of first instructions is retained, and at least one first instruction other than the last executed first instruction in the plurality of first instructions is deleted.

[0366] It can be understood that the number of memory access instructions (for example, the first instruction) in the first target code file is less than the number of memory access instructions (for example, the first instruction) in the second target code file, and the second target code file is not subjected to the first processing.

[0367] It can be understood that the compiling method provided by the embodiments of the present application can determine the coincidence relationship of the memory space corresponding to the variable through the defined correlation identifier, thereby determining the first instruction that meets the merging condition and merging and / or deleting the first instruction. The compiling method reduces the number of memory access instructions while reducing the risk of incorrect merging of instructions, thereby reducing the risk of program running errors.

[0368] Embodiment 4

[0369] The embodiments of the present application also provide a compiling method. In the case where the correlation identifier of the variable in the foregoing embodiment 3 does not indicate that the memory space corresponding to the variable must not coincide, the first instruction that meets the merging condition is determined based on the access identifier of the member data in each composite data type variable in the source program, and the first instruction is merged to further reduce the number of memory access instructions.

[0370] Exemplarily, FIG. 9 shows a flowchart of a compiling method based on a correlation identifier and an access identifier according to an embodiment of the present application. It can be understood that the execution subject of the flowchart shown in FIG. 9 is the electronic device 100. In order to simplify the description, the execution subject will not be repeatedly described in the following introduction of the flowchart shown in FIG. 9.

[0371] As shown in FIG. 9, the flowchart includes but is not limited to the following steps:

[0372] S901: obtaining a first source program, wherein the first source program includes a correlation identifier of a variable and an access identifier of member data of a composite type data.

[0373] Specifically, the correlation identifier of the variable and the access identifier of the member data of the composite type data can refer to the related description in S501 in FIG. 5 described above, and the present application will not be repeated here.

[0374] S902: converting the first source program into a first intermediate representation, wherein the first intermediate representation includes a plurality of instructions, and the instructions have corresponding variables.

[0375] The form of the first intermediate representation includes, but is not limited to, postfix representation, graph representation, three-address code, bottom virtual machine intermediate representation, assembly code representation form, and the like.

[0376] For example, it is assumed that the source program includes the definition of a function foo:

[0377] UINT32 foo (s_type *no_alias<0> ptrA, UINT32 *no_alias<1> ptrB) {

[0378] ptrB[0] = ptrA->a;

[0379] ptrB[1] = ptrA->b;

[0380] …

[0381] }

[0382] The foo function includes two formal parameters: a pointer variable ptrA of the s_type type and a pointer variable ptrB of the 32-bit integer data type. The correlation identifier of the pointer variable ptrA is the first correlation identifier no_alias<0>, and the correlation identifier of the pointer variable ptrB is the first correlation identifier no_alias<1>.

[0383] The ptrB[0] = ptrA->a and ptrB[1] = ptrA->b in the foo function are converted into the intermediate representation as follows:

[0384] Load4B @ptrA;

[0385] Store4B @ptrB;

[0386] Load4B @ptrA+1;

[0387] Store4B @ptrB+1;

[0388] S903: Determine a plurality of first instructions satisfying a first processing condition based on the correlation identifier of the variable in the first source program, and determine a plurality of third instructions satisfying a second processing condition based on the access identifier of the member data of the composite type data in the first source program.

[0389] In some embodiments, the electronic device 100 determines, based on the correlation identifier of the variable in the first source program, a plurality of first instructions satisfying a first processing condition from a plurality of instructions of the first intermediate representation. The first processing condition and the determination method of the first instruction can be specifically referred to the related description in the above FIG. 8, which will not be repeated here.

[0390] In some embodiments, the electronic device 100 determines, based on the access identifier of the member data of the composite type data in the first source program, that there are at least two third instructions in the plurality of instructions of the first intermediate representation that do not satisfy the first processing condition and satisfy a second processing condition.

[0391] In some embodiments, the second processing condition can be that the types of the plurality of third instructions are the same, the plurality of third instructions are instructions that access the first member data by the first access manner, and the plurality of third instructions are consecutive memory access instructions.

[0392] In other embodiments, if the composite type data further includes second member data, and the second member data does not include the first access identifier, and there is at least one second instruction between the at least two first instructions, the second processing condition can be that the first instruction is an instruction that accesses the first member data by the first access manner, and the types of the at least two first instructions are the same, and the second instruction is a memory access instruction that does not access the second member data by the first access manner.

[0393] For example, in some embodiments, the electronic device 100 determines, based on the correlation identifier of the variable, whether there are first instructions that can be combined in the plurality of instructions of the first intermediate representation.

[0394] For example, taking the intermediate representation corresponding to the above-mentioned foo function as an example, the correlation identifier of the variable ptrA corresponding to the read operation instruction Load4B@ptrA is the first type of correlation identifier no_alias<0>, and the correlation identifier of the variable ptrA corresponding to the read operation instruction Load4B@ptrA+1 is the first type of correlation identifier no_alias<0>. That is, the variable corresponding to the read operation instruction Load4B@ptrA and the variable corresponding to the read operation instruction Load4B@ptrA+1 have the same first type of correlation identifier, and the memory space accessed by the read operation instruction Load4B@ptrA and the memory space accessed by the read operation instruction Load4B@ptrA+1 do not overlap.

[0395] The write operation instruction Store4B@ptrB corresponds to the variable ptrB, and the correlation identifier of the variable ptrB is the first correlation identifier no_alias<1>. That is, the variable corresponding to the write operation instruction Store4B@ptrB and the variables corresponding to the read operation instructions Load4B@ptrA and Load4B@ptrA+1 have different first correlation identifiers. The memory space accessed by the write operation instruction Store4B@ptrB may overlap with the memory space accessed by the read operation instruction Load4B@ptrA and / or the memory space accessed by the read operation instruction Load4B@ptrA+1. Therefore, the electronic device 100 cannot determine whether the read operation instruction Load4B@ptrA and the read operation instruction Load4B@ptrA+1 can be combined based on the correlation identifier of the variable.

[0396] It can be understood that if the correlation identifier of the variable ptrB corresponding to the write operation instruction Store4B@ptrB is also the first correlation identifier no_alias<0>, it indicates that the memory space accessed by the write operation instruction Store4B@ptrB does not overlap with the memory space accessed by the read operation instruction Load4B@ptrA and the memory space accessed by the read operation instruction Load4B@ptrA+1. Therefore, it can be determined that the read operation instruction Load4B@ptrA and the read operation instruction Load4B@ptrA+1 can be combined.

[0397] In some embodiments, the electronic device 100 can further determine the third instructions that can be combined based on the access identifier of the member data of the composite type data, in a case that the first instructions that cannot be determined to be combined based on the correlation identifier of the variable.

[0398] For example, in some embodiments, if the third variable corresponding to the third instruction is used to access the member data of the variable of the first composite data type, the data type of the fourth variable corresponding to the fourth instruction between the plurality of third instructions is different from the first composite data type, and the access identifier of the first member data accessed by the third instruction is the first access modifier, the electronic device 100 can determine that the plurality of third instructions can be combined.

[0399] For example, still taking the intermediate representation corresponding to the foo function as an example, the electronic device 100 cannot determine whether the read operation instruction Load4B@ptrA and the read operation instruction Load4B@ptrA+1 can be combined based on the correlation identifier of the variable. The pointer variable ptrA corresponding to the read operation instruction Load4B@ptrA and the read operation instruction Load4B@ptrA+1 is used to access the member data a and the member data b in the structure of the s_type type, and the access identifiers of the member data a and the member data b are both the first access modifier. Moreover, the data type of the pointer variable ptrA corresponding to the read operation instruction Load4B@ptrA and the read operation instruction Load4B@ptrA+1 is the s_type type. The data type of the pointer variable ptrB corresponding to the write operation instruction Store4B@ptrB between the read operation instruction Load4B@ptrA and the read operation instruction Load4B@ptrA+1 is a 32-bit integer. Therefore, it can be determined that the memory space accessed by the write operation instruction Store4B@ptrB does not certainly coincide with the memory space accessed by the read operation instruction Load4B@ptrA and / or the read operation instruction Load4B@ptrA+1. The electronic device 100 can determine that the read operation instruction Load4B@ptrA and the read operation instruction Load4B@ptrA+1 can be combined, for example, the combined read operation instruction Load8B@ptrA can be obtained.

[0400] It can be understood that the above only takes the correlation identifier of the variable as the first type of correlation identifier as an example for description, and in some other embodiments, the correlation identifier of the variable can also be the second type of correlation identifier or other forms of correlation identifier. The present application does not make specific limitation on this.

[0401] S904: respectively performing first processing on the plurality of first instructions and the plurality of third instructions, and obtaining a first target code file.

[0402] In some embodiments, the electronic device 100 can directly generate the first target code file based on the intermediate representation.

[0403] In some other embodiments, the electronic device 100 can also combine the plurality of first instructions to obtain a second intermediate representation, and convert the second intermediate representation into a target code to obtain the first target code file.

[0404] It can be understood that the above only takes the merging of the memory access instructions meeting the merging condition as an example to describe the compiling method provided by the embodiments of the present application. In other embodiments, the compiling method provided by the embodiments of the present application can also delete the memory access instructions meeting the deletion condition. The deletion condition can be that the types of the plurality of first instructions are the same, the memory spaces accessed by the plurality of first instructions are the same, the plurality of third instructions are instructions for accessing the first member data by using the first access manner, and the plurality of third instructions are continuous memory access instructions; or the types of the plurality of first instructions are the same, the memory spaces accessed by the plurality of first instructions are the same, the first instruction is an instruction for accessing the first member data by using the first access manner, and the types of at least two first instructions are the same, and the second instruction is a memory access instruction that does not access the second member data by using the first access manner. The method of performing the deletion processing can refer to the related description of the deletion processing in the above FIG. 7, and the present application will not be repeated here. In other embodiments, the compiling method provided by the embodiments of the present application can also perform the first processing on other first instructions meeting the first condition, which is not limited by the present application.

[0405] In summary, the compiling method provided by the embodiments of the present application can determine the coincidence relationship of the memory spaces corresponding to the variables through the defined correlation identifier, thereby determining the first instructions meeting the merging condition and merging the first instructions, which reduces the risk of incorrect merging and further reduces the risk of program running errors. Moreover, when the correlation identifier of the variable does not indicate that the memory spaces corresponding to the variables must not coincide, the first instructions meeting the merging condition are determined based on the access identifiers of the member data in the variables of each composite data type in the source program, and the first instructions are merged to further reduce the number of memory access instructions.

[0406] It can be understood that the plurality of instructions in each of the above embodiments can be a plurality of memory access instructions, the number of the plurality of first instructions is an integer greater than 1, that is, at least two first instructions, and the number of the plurality of third instructions is an integer greater than 1, that is, at least two third instructions, which will not be repeated here.

[0407] The embodiments of the present application also provide a compiling device. Exemplarily, FIG. 10 shows a structural schematic diagram of a compiling device 1000 according to the embodiments of the present application. As shown in FIG. 10, the device 1000 includes:

[0408] The obtaining module 1001 is configured to obtain a source program, where the source program includes an access identifier (or an access modifier) of member data of a composite type data. In some embodiments, the source program further includes a dependency identifier of a variable. The optimization module 1002 is configured to obtain the source program from the obtaining module 1001, convert the source program into a first intermediate representation, and determine, based on the dependency identifier of the variable in the source program and / or the access identifier of the member data of the composite type data, whether a memory access instruction in the first intermediate representation can be subjected to first processing, and perform the first processing on the memory access instruction that can be subjected to the first processing. The first processing includes, but is not limited to, a merging processing, a deletion processing, and the like.

[0409] In some embodiments, the optimization module 1002 can obtain, through an interface, related semantic information of the access identifier and the dependency identifier, and determine, based on the dependency identifier of the variable in the source program and / or the access identifier of the member data of the composite type data, and the related semantic information of the access identifier and the dependency identifier, whether the memory access instruction in the first intermediate representation can be subjected to the first processing, that is, whether the first processing condition and / or the second processing condition are met.

[0410] In some embodiments, the access identifier is used to indicate an access manner of the member data. For example, the member data identified by a first access modifier (for example, unique) can be accessed only through a variable (a first variable or a variable of a first type) of a composite data type corresponding to the member data. Or for example, the member data identified by a second access modifier (for example, shared) can be accessed through a variable of the composite data type corresponding to the member data, or through a variable of another type other than the variable of the composite data type corresponding to the member data, for example, through a pointer variable of the data type corresponding to the member data.

[0411] It can be understood that if there is a memory access instruction for accessing second member data through a variable of a non-composite data type between two memory access instructions for accessing first member data through a variable of a composite data type, and the first member data includes the first access modifier and the second member data does not include the first access modifier (for example, includes the second access modifier), the optimization module 1002 can determine that the first member data and the second member data are different member data, that is, there is no intersection between the memory spaces corresponding to the first member data and the second member data. Further, the optimization module 1002 can determine that the two memory access instructions for accessing the first member data through the variable of the composite data type meet the first processing condition (or the second processing condition).

[0412] In some embodiments, the dependency identifier of a variable is used to indicate whether there is another variable whose memory space intersects with the memory space corresponding to the identified variable. That is, the dependency identifier of a variable is used to indicate whether there is an intersection between the memory spaces corresponding to multiple variables. The intersection between the memory spaces corresponding to multiple variables includes, but is not limited to, the memory spaces corresponding to multiple variables completely overlap, the memory spaces corresponding to multiple variables partially overlap, the memory spaces corresponding to multiple variables have a containing relationship, i.e., the memory space corresponding to a variable contains the memory space corresponding to another variable, and the like. The present application does not make a specific limitation on this.

[0413] It can be understood that if there is a memory access instruction corresponding to a second variable (e.g., an instruction for accessing the second variable or an instruction for accessing data through the second variable) between two memory access instructions corresponding to a first variable (e.g., an instruction for accessing the first variable or an instruction for accessing data through the first variable), and the dependency identifier of the first variable and the dependency identifier of the second variable indicate that there is no intersection between the memory space corresponding to the first variable and the memory space corresponding to the second variable, the optimization module 1002 can determine that the two memory access instructions corresponding to the first variable satisfy the first processing condition (or the second processing condition).

[0414] It can be understood that the first processing (e.g., the merging processing and / or the deleting processing) of the memory access instructions satisfying the first processing condition and / or the second processing condition can effectively reduce the number of memory access instructions, thereby improving the running efficiency of the application program corresponding to the source program. At the same time, judging whether there is a memory access instruction satisfying the first processing condition and / or the second processing condition in the memory access instructions of the source program based on the access identifier and / or the dependency identifier can reduce the risk of incorrect merging and / or incorrect deleting, thereby reducing the risk of program errors.

[0415] The code generation module 1003 is configured to obtain the first intermediate representation after the first processing of the optimization module 1002, and generate a target code file (as a first target code file) based on the first intermediate representation, such as an executable file. For example, in some embodiments, the obtaining module 1001 is configured to obtain a first source program, wherein the first source program includes a composite type data, the composite type data includes a first member data, and the first member data includes a first access identifier, the first access identifier is used to indicate that the first member data is accessed only through a first access manner. The optimization module 1002 is configured to determine at least two first instructions satisfying a first processing condition from a plurality of memory access instructions corresponding to the first source program, wherein the first processing condition includes that the first instruction is an instruction for accessing the first member data through the first access manner, and the types of the at least two first instructions are the same; and is further configured to perform the first processing on the at least two first instructions. The code generation module 1003 is configured to obtain the first target code file.

[0416] In some embodiments, the obtaining module 1001 is configured to obtain a first source program, wherein the first source program comprises a correlation identifier of a variable, and the correlation identifier is used to indicate whether there is another variable corresponding to the variable and having an intersection with a storage space of the variable. The optimization module 1002 is configured to determine, based on the correlation identifier in the first source program, at least two third instructions from a plurality of memory access instructions corresponding to the first source program, the at least two third instructions not satisfying a first processing condition and satisfying a second processing condition, wherein the second processing condition comprises that the at least two third instructions correspond to a third variable, there is at least one fourth instruction corresponding to a fourth variable between the at least two third instructions, and the storage space of the fourth variable has no intersection with the storage space of the third variable; and perform the first processing on the plurality of third instructions.

[0417] For example, in some embodiments, the obtaining module 1001 is configured to obtain a first source program, wherein the first source program comprises a correlation identifier of a variable, and variables having the same correlation identifier correspond to storage spaces that have no intersection. The optimization module 1002 is configured to determine, based on the correlation identifier in the first source program, at least two first instructions from a plurality of memory access instructions corresponding to the first source program, the at least two first instructions satisfying a first processing condition, wherein the first processing condition comprises that the at least two first instructions correspond to a first variable, there is at least one second instruction corresponding to a second variable between the at least two first instructions, and the correlation identifier of the second variable is the same as the correlation identifier of the first variable; and perform the first processing on the at least two first instructions. The code generation module 1003 is configured to obtain a first target code file.

[0418] In some embodiments, the obtaining module 1001 is configured to obtain a first source program, wherein the first source program comprises a composite type data, the composite type data comprises a first member data, and the first member data comprises a first access identifier, and the first access identifier is used to indicate that the first member data is accessed only through a first access manner. The optimization module 1002 is configured to determine, from a plurality of memory access instructions corresponding to the first source program, at least two third instructions not satisfying a first processing condition and satisfying a second processing condition, wherein the second processing condition comprises that the third instruction is an instruction for accessing the first member data through the first access manner, and the types of the at least two third instructions are the same; and perform the first processing on the plurality of third instructions.

[0419] It should be understood that the compiling apparatus 1000 herein is embodied in the form of functional modules. The term "unit" herein can refer to an application specific integrated circuit (ASIC), an electronic circuit, a processor (for example, a shared processor, a dedicated processor, or a group processor, etc.) and a memory for executing one or more software or firmware programs, a combination logic circuit, and / or other suitable components supporting the described functions. For example, if the compiling apparatus 1000 is a compiler, the obtaining module 1001 can be a compiler front end, the optimizing module 1002 can be a compiler optimizer, and the code generation module 1003 can be a compiler back end.

[0420] In some embodiments, the compiling apparatus 1000 can be configured to perform the respective processes corresponding to the above-described method embodiments, and thus details are not repeated herein.

[0421] Exemplarily, FIG. 11 shows a schematic diagram of a hardware structure of a compiling apparatus 1000 according to an embodiment of the present application.

[0422] As shown in FIG. 11, the compiling apparatus 1000 includes one or more (only one is shown in the figure) processors 110, a memory 120, a communication interface 130, and a bus 140. The processor 110, the memory 120, and the communication interface 130 are communicatively connected to each other through the bus 140.

[0423] The processor 110 can include one or more processing units, such as a central processing unit (CPU), a microprocessor, a graphics processing unit (GPU), an application specific integrated circuit, etc., configured to execute related programs to implement the functions required by the modules in the compiling apparatus according to the embodiments of the present application, or to execute the compiling method according to the method embodiments of the present application.

[0424] The memory 120 can include one or more memories for storing data or one or more application programs. The memory can be a read only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). For example, in some embodiments, the memory 120 can store a source program, which includes the correlation identification of a variable and the access identification of the member data of a composite type data.

[0425] In some embodiments, if the processor is a CPU, the corresponding memory 120 is main memory. In some embodiments, if the processor 110 is a GPU, the corresponding memory 120 can be video memory.

[0426] The processor 110 can also be an integrated circuit chip having a processing capability of signals. In the implementation process, various steps of the compiling method of the present application can be completed by instructions in the form of software in the processor 110. The processor 110 described above can also be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit, a field programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component. The disclosed methods, steps and logic block diagrams in the embodiments of the present application can be implemented or executed. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor. The steps of the method disclosed in combination with the embodiments of the present application can be directly embodied as a hardware coding processor for execution, or a combination of hardware and software modules in the coding processor for execution. The software module can be located in a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium in the art. The storage medium is located in the memory 120, and the processor 110 reads the information in the memory 120, and combines the hardware to complete the functions required by the units included in the compiling device in the embodiments of the present application, or executes the compiling method of the method embodiments of the present application.

[0427] The communication interface 130 is used to realize the communication between the compiling device 1000 and other devices or communication networks. The communication interface 130 can include wired or wireless communication interfaces, so that the electronic device 100 can access the Internet through wired or wireless means, and obtain data from other devices or send data to other devices based on the Internet.

[0428] The bus 140 is used to connect the processor 110, the memory 120, the communication interface 130 and other possible modules or circuits.

[0429] It should be understood that the structure of the compiling device 1000 shown in FIG. 11 is only an example, and in other embodiments, the compiling device 1000 can include more or fewer modules, which are not limited herein.

[0430] The embodiment of the present application further provides a computer readable storage medium, and the computer readable storage medium stores at least one instruction, at least one program, a code set or an instruction set, which are loaded by a processor and executed to implement the method provided by each method embodiment.

[0431] The embodiment of the present application further provides a program product, and the program product includes instructions, which, when executed by equipment, can enable the equipment to implement the method provided by the embodiment of the present application.

[0432] In some cases, the disclosed embodiments can be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments can also be implemented as instructions carried by or stored on one or more transitory or non-transitory machine-readable (e.g., computer-readable) media, which can be read and executed by one or more processors. For example, the instructions can be distributed over the network or by other computer readable media. Thus, a machine-readable medium can include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer), including without limitation, floppy diskettes, optical disks, optical fiber disks, magnetic disk storage media, read only memory (ROM), random access memory (RAM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), magnetic or optical cards, flash memory, or tangible, machine-readable storage used in the transmission of information over the Internet with a propagated signal in electronic, optical, or other form. Accordingly, a machine-readable medium includes any type of tangible, machine-readable medium suitable for storing or transmitting electronic instructions or information in a form readable by a machine (e.g., a computer).

[0433] In the drawings, some structural or methodological features can be shown in a particular arrangement and / or order. However, it should be understood that such a particular arrangement and / or order can not be required. Rather, in some embodiments, these features can be arranged in a different manner and / or order than shown in the illustrative drawings. Additionally, inclusion of structural or methodological features in a particular figure does not imply that such features are required in all embodiments, and in some embodiments, these features can not be included or can be combined with other features.

[0434] It should be noted that each unit / module mentioned in each device embodiment of the present application is a logical unit / module, and in physical, one logical unit / module can be a physical unit / module, or a part of a physical unit / module, or be realized in a combination of multiple physical unit / modules, and the physical realization of these logical units / modules is not the most important, and the combination of functions implemented by these logical units / modules is the key to solving the technical problems proposed in the present application. In addition, in order to highlight the innovative part of the present application, the above-mentioned device embodiments of the present application do not introduce the units / modules which are not closely related to solving the technical problems proposed in the present application, which does not mean that the above-mentioned device embodiments do not have other units / modules.

[0435] It should be noted that in the examples and description of the present patent, the relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. Without more limitations, the element defined by the statement "including one" does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0436] Although the present application has been illustrated and described with reference to certain preferred embodiments thereof, it should be understood by those skilled in the art that various changes in form and details can be made therein without departing from the spirit and scope of the present application.

Claims

1. A method of compiling, characterized by, The method comprises: obtaining a first source program, wherein the first source program comprises composite type data, the composite type data comprises first member data, the first member data comprises a first access identifier, and the first access identifier is used to indicate that the first member data is accessed only through a first access mode; determining at least two first instructions satisfying a first processing condition from a plurality of memory access instructions corresponding to the first source program, wherein the first processing condition comprises that the first instructions are instructions for accessing the first member data through the first access mode, and the at least two first instructions are of the same type; performing first processing on the at least two first instructions, and obtaining a first target code file.

2. The method of claim 1, wherein, The plurality of memory access instructions corresponding to the first source program are determined by the following method: generating a first intermediate representation based on the first source program, wherein the first intermediate representation comprises a plurality of instructions; determining the plurality of memory access instructions from the plurality of instructions in the first intermediate representation.

3. The method of claim 1, wherein, The accessing the first member data through the first access mode comprises: accessing the first member data through a first variable, or accessing the first member data through a first type of variable.

4. The method of claim 1, wherein, The first processing condition further comprises: The at least two first instructions are consecutive memory access instructions.

5. The method of claim 1, wherein, The composite type data further comprises second member data, the second member data does not comprise the first access identifier, there is at least one second instruction between the at least two first instructions, and The first processing condition further comprises: The second instruction is a memory access instruction that does not access the second member data through the first access mode.

6. The method of claim 5, wherein, Corresponding to the type of the first instruction is a read operation instruction, and the first processing condition further comprises at least one of the following: The first instruction is a read operation instruction, and the second instruction is a write operation instruction; The first instruction is a write operation instruction, and the second instruction is a read operation instruction.

7. The method of claim 1, wherein, The first source program further comprises a relevance identifier of a variable, the relevance identifier is used to indicate whether there is another variable intersecting with a storage space corresponding to the variable; and The method further comprises: determining at least two third instructions not satisfying the first processing condition and satisfying a second processing condition from the plurality of memory access instructions corresponding to the first source program based on the relevance identifier in the first source program, wherein the second processing condition comprises: The at least two third instructions correspond to a third variable, there is at least one fourth instruction corresponding to a fourth variable between the at least two third instructions, and a storage space corresponding to the fourth variable does not intersect with a storage space corresponding to the third variable; performing the first processing on the plurality of third instructions, and obtaining the first target code file.

8. The method of claim 7, wherein, The relevance identifier used to indicate whether there is another variable intersecting with a storage space corresponding to the variable comprises: Variables with the same relevance identifier correspond to storage spaces that do not intersect.

9. The method of claim 8, wherein, The storage space corresponding to the fourth variable does not intersect with the storage space corresponding to the third variable, comprising: The correlation identifier of the fourth variable corresponding to the fourth instruction is the same as the correlation identifier of the third variable corresponding to the third instruction.

10. The method of claim 1, wherein, The number of memory access instructions in the first target code file is less than the number of memory access instructions in a second target code file, and the second target code file is a target code file obtained by not performing the first processing on the memory access instructions.

11. The method of claim 1, wherein, The first processing includes at least one of the following: a merging processing, a deletion processing.

12. The method of claim 11, wherein, Corresponding to the first processing including the merging processing, the first processing condition further includes: The storage space accessed by each of the first instructions is a continuous storage space, or The data stored in the storage space accessed by each of the first instructions corresponds to the same variable.

13. The method of claim 2, wherein, The first target code file is obtained by: performing the first processing on the at least two first instructions to obtain a second intermediate representation, wherein the number of the first instructions in the second intermediate representation is less than the number of the first instructions in the first intermediate representation; and generating the first target code file based on the second intermediate representation.

14. A method of compiling, characterized by, It includes: obtaining a first source program, wherein the first source program includes a correlation identifier of a variable, and the storage space corresponding to the variables with the same correlation identifier does not have an intersection; determining at least two first instructions satisfying a first processing condition from a plurality of memory access instructions corresponding to the first source program based on the correlation identifier in the first source program, wherein the first processing condition includes: the at least two first instructions correspond to a first variable, there is at least one second instruction corresponding to a second variable between the at least two first instructions, and the correlation identifier of the second variable is the same as the correlation identifier of the first variable; and performing the first processing on the at least two first instructions to obtain a first target code file.

15. A compiling apparatus characterized by comprising: It includes: an obtaining module configured to obtain a first source program, wherein the first source program includes composite type data, the composite type data includes first member data, and the first member data includes a first access identifier, the first access identifier being used to indicate that the first member data is accessed only through a first access manner; an optimization module configured to determine at least two first instructions satisfying a first processing condition from a plurality of memory access instructions corresponding to the first source program, wherein the first processing condition includes that the first instructions are instructions for accessing the first member data through the first access manner, and the types of the at least two first instructions are the same; the optimization module is further configured to perform the first processing on the at least two first instructions; and a code generation module configured to obtain a first target code file.

16. A readable medium characterized by The readable medium stores instructions, and the instructions are executed on the electronic device to cause the electronic device to perform the method in any one of claims 1 to 14.

17. An electronic device, comprising: It includes: a memory configured to store instructions executed by one or more processors of an electronic device, and a processor, which is one of the processors of the electronic device, is configured to perform the method in any one of claims 1 to 14.

18. A program product, characterized by The program product comprises instructions which, when executed on an electronic device, cause the electronic device to perform the method of any of claims 1 to 14.

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