Pixel driving circuit and driving method therefor, and display device

Abstract

A pixel driving circuit and a driving method therefor, and a display device. The pixel driving circuit comprises: a first control sub-circuit, a second control sub-circuit, a third control sub-circuit, and a drive sub-circuit. The first control sub-circuit is configured to, under the control of a signal of at least one of a first scanning signal line (Gate1), a fourth scanning signal line (Gate4), and a fifth scanning signal line (Gate5), provide a signal of a data signal line (Data) to a fourth node (N4), control a signal of a fifth node (N5) by means of the signal of the fourth node (N4), and provide the signal of the fifth node (N5) to a first node (N1) and a third node (N3). The second control sub-circuit is configured to, under the control of a signal of at least one of a second scanning signal line (Gate2) and a third scanning signal line (Gate3), provide a signal of a second reference signal line (REF2) to a second node (N2), provide a signal of a first reference signal line (REF1) to the fourth node (N4), provide a signal of a first initial signal line (INIT1) to the fifth node (N5), and provide a signal of a second initial signal line (INIT2) to a sixth node (N6).

Description

Pixel driving circuit and its driving method, display device

[0001] This application claims priority to Chinese Patent Application No. 202411391068.7, filed on September 30, 2024, entitled "Pixel Driving Circuit and Driving Method Thereof, Display Device", the contents of which are to be understood as incorporated herein by reference. Technical Field

[0002] This disclosure relates to, but is not limited to, the field of display technology, specifically to a pixel driving circuit and its driving method, and a display device. Background Technology

[0003] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0005] In a first aspect, this disclosure provides a pixel driving circuit configured to drive a light-emitting device to emit light, comprising: a first control sub-circuit, a second control sub-circuit, a third control sub-circuit, and a driving sub-circuit;

[0006] The first control sub-circuit is electrically connected to the first scan signal line, the fourth scan signal line, the fifth scan signal line, the data signal line, the first node, the third node, the fourth node, and the fifth node, respectively. It is configured to provide the data signal line to the fourth node under the control of the signal of at least one of the first scan signal line, the fourth scan signal line, and the fifth scan signal line, control the signal of the fifth node through the signal of the fourth node, and provide the signal of the fifth node to the first node and the third node.

[0007] The second control sub-circuit is electrically connected to the second scan signal line, the third scan signal line, the first initial signal line, the second initial signal line, the first reference signal line, the second reference signal line, the second node, the fourth node, the fifth node, and the sixth node, respectively. It is configured to provide the second reference signal line to the second node, the first reference signal line to the fourth node, the first initial signal line to the fifth node, and the second initial signal line to the sixth node under the control of the signal of at least one of the second scan signal line and the third scan signal line.

[0008] The third control sub-circuit is electrically connected to the first light-emitting signal line, the second light-emitting signal line, the first power supply line, the second node, the third node, and the sixth node, respectively. It is configured to provide the first power supply line signal to the second node and the third node signal to the sixth node under the control of the signals of the first light-emitting signal line and the second light-emitting signal line.

[0009] The driving sub-circuit is electrically connected to the first node, the second node and the third node respectively, and is configured to provide a driving signal to the third node;

[0010] The light-emitting device is electrically connected to the sixth node and the second power line, respectively.

[0011] In an exemplary embodiment, the first control sub-circuit includes: a write sub-circuit, a first storage sub-circuit, a connection sub-circuit, and a second storage sub-circuit;

[0012] The writing sub-circuit is electrically connected to the first scan signal line, the data signal line and the fourth node respectively, and is configured to provide the data signal line signal to the fourth node under the control of the signal of the first scan signal line.

[0013] The first storage sub-circuit, which is electrically connected to the fourth node and the fifth node respectively, is configured to store the voltage difference between the signals of the fourth node and the fifth node;

[0014] The connected sub-circuit is electrically connected to the fourth scan signal line, the fifth scan signal line, the first node, the third node, and the fifth node, respectively, and is configured to provide the signal of the fifth node to the third node under the control of the signal of the fifth scan signal line, and to provide the signal of the fifth node to the first node under the control of the signal of the fourth scan signal line.

[0015] The second storage sub-circuit is electrically connected to the first node and the first power line, respectively, and is configured to store the voltage difference between the signals of the first node and the first power line.

[0016] In an exemplary embodiment, the write sub-circuit includes a fourth transistor, the first storage sub-circuit includes a first capacitor, the second storage sub-circuit includes a second capacitor, at least one of the first and second capacitors includes a first electrode and a second electrode, and the communication sub-circuit includes a second transistor and an eighth transistor.

[0017] The control electrode of the second transistor is electrically connected to the fifth scan signal line, the first electrode of the second transistor is electrically connected to the fifth node, and the second electrode of the second transistor is electrically connected to the third node.

[0018] The control electrode of the fourth transistor is electrically connected to the first scan signal line, the first electrode of the fourth transistor is electrically connected to the data signal line, and the second electrode of the fourth transistor is electrically connected to the fourth node.

[0019] The control electrode of the eighth transistor is electrically connected to the fourth scan signal line, the first electrode of the eighth transistor is electrically connected to the fifth node, and the second electrode of the eighth transistor is electrically connected to the first node.

[0020] The first plate of the first capacitor is electrically connected to the fifth node, and the second plate of the first capacitor is electrically connected to the fourth node.

[0021] The first plate of the second capacitor is electrically connected to the first node, and the second plate of the second capacitor is electrically connected to the first power line.

[0022] In an exemplary embodiment, the second control sub-circuit includes: a first sub-circuit, a second sub-circuit, a third sub-circuit, and a fourth sub-circuit;

[0023] The first sub-circuit is electrically connected to the second scan signal line, the first initial signal line and the fifth node respectively, and is configured to provide the signal of the first initial signal line to the fifth node under the control of the signal of the second scan signal line.

[0024] The second sub-circuit is electrically connected to the third scan signal line, the first reference signal line, and the fourth node, respectively, and is configured to provide the signal of the first reference signal line to the fourth node under the control of the signal of the third scan signal line;

[0025] The third sub-circuit is electrically connected to the second scan signal line, the second reference signal line, and the second node, and is configured to provide the second reference signal line to the second node under the control of the signal of the second scan signal line.

[0026] The fourth sub-circuit is electrically connected to the second scan signal line, the second initial signal line, and the sixth node, respectively, and is configured to provide the signal of the second initial signal line to the sixth node under the control of the signal of the second scan signal line.

[0027] In an exemplary embodiment, the first sub-circuit includes a first transistor, the second sub-circuit includes a seventh transistor, the third sub-circuit includes a ninth transistor, and the fourth sub-circuit includes a tenth transistor.

[0028] The control electrode of the first transistor is electrically connected to the second scan signal line, the first electrode of the first transistor is electrically connected to the first initial signal line, and the second electrode of the first transistor is electrically connected to the fifth node.

[0029] The control electrode of the seventh transistor is electrically connected to the third scan signal line, the first electrode of the seventh transistor is electrically connected to the first reference signal line, and the second electrode of the seventh transistor is electrically connected to the fourth node.

[0030] The control electrode of the ninth transistor is electrically connected to the second scan signal line, the first electrode of the ninth transistor is electrically connected to the second reference signal line, and the second electrode of the ninth transistor is electrically connected to the second node.

[0031] The control electrode of the tenth transistor is electrically connected to the second scan signal line, the first electrode of the tenth transistor is electrically connected to the second initial signal line, and the second electrode of the tenth transistor is electrically connected to the sixth node.

[0032] In an exemplary embodiment, the first control sub-circuit includes: a second transistor, a fourth transistor, an eighth transistor, a first capacitor, and a second capacitor, at least one of the first capacitor and the second capacitor includes: a first electrode and a second electrode; the second control sub-circuit includes: a first transistor, a seventh transistor, a ninth transistor, and a tenth transistor; the third control sub-circuit includes: a fifth transistor and a sixth transistor; and the driving sub-circuit includes: a third transistor.

[0033] The control electrode of the first transistor is electrically connected to the second scan signal line, the first electrode of the first transistor is electrically connected to the first initial signal line, and the second electrode of the first transistor is electrically connected to the fifth node.

[0034] The control electrode of the second transistor is electrically connected to the fifth scan signal line, the first electrode of the second transistor is electrically connected to the fifth node, and the second electrode of the second transistor is electrically connected to the third node.

[0035] The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node.

[0036] The control electrode of the fourth transistor is electrically connected to the first scan signal line, the first electrode of the fourth transistor is electrically connected to the data signal line, and the second electrode of the fourth transistor is electrically connected to the fourth node.

[0037] The control electrode of the fifth transistor is electrically connected to the first light-emitting signal line, the first electrode of the fifth transistor is electrically connected to the first power supply line, and the second electrode of the fifth transistor is electrically connected to the second node.

[0038] The control electrode of the sixth transistor is electrically connected to the second light-emitting signal line, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the sixth node.

[0039] The control electrode of the seventh transistor is electrically connected to the third scan signal line, the first electrode of the seventh transistor is electrically connected to the first reference signal line, and the second electrode of the seventh transistor is electrically connected to the fourth node.

[0040] The control electrode of the eighth transistor is electrically connected to the fourth scan signal line, the first electrode of the eighth transistor is electrically connected to the fifth node, and the second electrode of the eighth transistor is electrically connected to the first node.

[0041] The control electrode of the ninth transistor is electrically connected to the second scan signal line, the first electrode of the ninth transistor is electrically connected to the second reference signal line, and the second electrode of the ninth transistor is electrically connected to the second node.

[0042] The control electrode of the tenth transistor is electrically connected to the second scan signal line, the first electrode of the tenth transistor is electrically connected to the second initial signal line, and the second electrode of the tenth transistor is electrically connected to the sixth node.

[0043] The first plate of the first capacitor is electrically connected to the fifth node, and the second plate of the first capacitor is electrically connected to the fourth node.

[0044] The first plate of the second capacitor is electrically connected to the first node, and the second plate of the second capacitor is electrically connected to the first power line.

[0045] The fifth scanning signal line and the first light-emitting signal line are the same signal line.

[0046] The transistor type of the eighth transistor is different from the transistor type of at least one of the first to seventh transistors, the ninth transistor, and the tenth transistor;

[0047] The eighth transistor is an N-type transistor.

[0048] In a second aspect, this disclosure also provides a display device, including: a substrate and a plurality of sub-pixels arranged in an array on the substrate, wherein at least one of the plurality of sub-pixels includes: the aforementioned pixel driving circuit.

[0049] In an exemplary embodiment, for at least one row of sub-pixels, two adjacent sub-pixels of at least one sub-pixel include: a first adjacent sub-pixel and a second adjacent sub-pixel;

[0050] The structure of the pixel driving circuit of at least one sub-pixel is at least partially symmetrical to the structure of the pixel driving circuit of the first adjacent sub-pixel along a straight line extending in the second direction, and the structure of the pixel driving circuit of at least one sub-pixel is at least partially the same as the structure of the pixel driving circuit of the second adjacent sub-pixel.

[0051] In an exemplary embodiment, it further includes: a plurality of data signal lines, one of which extends along a second direction;

[0052] The pixel driving circuit for at least one sub-pixel includes: a second transistor, a third transistor, and a sixth transistor;

[0053] At least one data signal line does not overlap with the orthographic projections on the substrate of the first and second poles of at least one of the second, third, and sixth transistors in the pixel driving circuit of at least one sub-pixel;

[0054] At least one data signal line does not overlap with the orthographic projection of the control electrode of the third transistor in the pixel driving circuit of at least one sub-pixel on the substrate.

[0055] In an exemplary embodiment, when the fifth scan signal line of at least one pixel driving circuit is the same signal line as the first light emission signal line, the display device further includes: multiple first initial signal lines, multiple second initial signal lines, multiple first reference signal lines, multiple second reference signal lines, multiple first scan signal lines, multiple second scan signal lines, multiple third scan signal lines, multiple fourth scan signal lines, multiple first light emission signal lines, and multiple second light emission signal lines;

[0056] At least a portion of at least one of the following multiple first initial signal lines, multiple second initial signal lines, multiple first reference signal lines, multiple second reference signal lines, multiple first scan signal lines, multiple second scan signal lines, multiple third scan signal lines, multiple fourth scan signal lines, multiple first light emission signal lines, and multiple second light emission signal lines extends along a first direction, which intersects with the second direction.

[0057] The pixel driving circuit for at least one sub-pixel includes: a first transistor, a ninth transistor, and a tenth transistor;

[0058] The pixel driving circuit of at least one sub-pixel is electrically connected to two second scan signal lines. The control electrode of the first transistor in the pixel driving circuit of at least one sub-pixel is electrically connected to the first second scan signal line of the two second scan signal lines connected to the pixel driving circuit of at least one sub-pixel. The control electrode of at least one of the ninth and tenth transistors in the pixel driving circuit of at least one sub-pixel is electrically connected to the first second scan signal line of the two second scan signal lines connected to the pixel driving circuit of at least one sub-pixel.

[0059] The orthographic projections of the first reference signal line, the third scan signal line, the first scan signal line, the first second scan signal line, the fourth scan signal line, the first light emission signal line, the second light emission signal line, the first second scan signal line, and the second reference signal line on the substrate, connected to the pixel driving circuit of at least one sub-pixel, are arranged sequentially along a second direction.

[0060] The orthographic projection of the first initial signal line on the substrate is located between the orthographic projection of the first scan signal line on the substrate and the orthographic projection of the fourth scan signal line on the substrate, and at least partially overlaps with the orthographic projection of the first second scan signal line on the substrate.

[0061] The orthographic projection of the second initial signal line on the substrate is located between the orthographic projection of the second emitting signal line on the substrate and the orthographic projection of the second reference signal line on the substrate, and at least partially overlaps with the orthographic projection of the second second scan signal line on the substrate.

[0062] In an exemplary embodiment, the pixel driving circuit of at least one sub-pixel includes: a first capacitor and a second capacitor;

[0063] For a pixel driving circuit of at least one sub-pixel, the orthographic projection of the first capacitor on the substrate is located between the orthographic projection of at least one of the first second scan signal line and the first initial signal line connected to the pixel driving circuit on the substrate and the orthographic projection of the fourth scan signal line on the substrate.

[0064] The orthographic projection of the second capacitor on the substrate lies between the orthographic projection of the first light-emitting signal line connected to the pixel driving circuit on the substrate and the orthographic projection of the second light-emitting signal line on the substrate.

[0065] In an exemplary embodiment, it further includes: a plurality of first power lines, one of which extends along a second direction;

[0066] At least one data signal line includes: a plurality of first data connection portions and a plurality of second data connection portions, the plurality of first data connection portions and the plurality of second data connection portions being alternately arranged, and at least one of the first data connection portions and the second data connection portions extending along a second direction;

[0067] For the data signal line connected to the pixel driving circuit of at least one sub-pixel, the orthographic projection of the first data connection portion on the substrate at least partially overlaps with the orthographic projection of at least one of the following signal lines on the substrate: the first reference signal line, the third scan signal line, the first scan signal line, the first second scan signal line, the first initial signal line, the fourth scan signal line, the first light emission signal line, the power connection line, and at least one of the first and second capacitors in the pixel driving circuit of at least one sub-pixel.

[0068] The orthographic projection of the second data connection portion on the substrate at least partially overlaps with the orthographic projection of at least one of the following signal lines on the substrate: the second light-emitting signal line, the second scanning signal line, the second initial signal line, and the second reference signal line.

[0069] The length of the first data connection part along the first direction is greater than the length of the second data connection part along the first direction.

[0070] In an exemplary embodiment, it further includes: multiple data signal lines, multiple first power supply lines, multiple first initial signal lines, multiple second initial signal lines, multiple first reference signal lines, multiple second reference signal lines, multiple first scan signal lines, multiple second scan signal lines, multiple third scan signal lines, multiple fourth scan signal lines, multiple first light emission signal lines, and multiple second light emission signal lines;

[0071] The display device further includes: a circuit structure layer disposed on a substrate, the circuit structure layer including: a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer stacked sequentially on the substrate; and a pixel driving circuit for at least one sub-pixel including: at least one P-type transistor, at least one N-type transistor and at least one capacitor, the at least one capacitor including: a first electrode plate and a second electrode plate.

[0072] The first semiconductor layer includes: an active pattern of at least one P-type transistor located in a pixel driving circuit of at least one sub-pixel;

[0073] The first conductive layer includes at least: a second scan signal line, a first light emission signal line, and a first electrode of at least one capacitor and a control electrode of at least one P-type transistor located in the pixel driving circuit of at least one sub-pixel;

[0074] The second conductive layer includes at least: the second plate of at least one capacitor located in the pixel driving circuit of at least one sub-pixel and the first control electrode of at least one N-type transistor;

[0075] The second semiconductor layer includes at least: an active pattern of at least one N-type transistor located in the pixel driving circuit of at least one sub-pixel;

[0076] The third conductive layer includes at least: a first initial signal line, a second reference signal line, and a second control electrode of an eighth transistor located in the pixel driving circuit of at least one sub-pixel;

[0077] The fourth conductive layer includes at least: a first reference signal line, a first scan signal line, a third scan signal line, a fourth scan signal line, a second light emission signal line, a second initial signal line, and a first and second electrode of at least one transistor of a pixel driving circuit located in at least one sub-pixel;

[0078] The fifth conductive layer pattern may include at least: data signal lines and first power lines.

[0079] In an exemplary embodiment, the circuit structure layer further includes: a light-shielding layer located on the side of the first semiconductor layer near the substrate, the light-shielding layer including: a light-shielding structure located at at least one sub-pixel;

[0080] The light-shielding structure located at at least one sub-pixel includes: a first light-shielding part, a second light-shielding part, a first light-shielding connecting part, a second light-shielding connecting part, and a third light-shielding connecting part. The first light-shielding connecting part, the first light-shielding part, the second light-shielding connecting part, the second light-shielding part, and the third light-shielding connecting part are arranged sequentially along a second direction. The first light-shielding part is connected to the first light-shielding connecting part and the second light-shielding connecting part, respectively. The second light-shielding part is connected to the second light-shielding connecting part and the third light-shielding connecting part, respectively.

[0081] At least one of the first light-shielding connecting portion, the second light-shielding connecting portion, and the third light-shielding connecting portion extends along the second direction;

[0082] At least one of the first and second light-shielding portions has a length along the first direction that is greater than the length along the first direction of at least one of the light-shielding connecting portions from the first to the third light-shielding connecting portions.

[0083] The pixel driving circuit for at least one sub-pixel includes: a first capacitor and a second capacitor, wherein the first capacitor and the second capacitor include a first electrode plate and a second electrode plate.

[0084] The orthographic projection of the first light-shielding part of the light-shielding structure located at least one sub-pixel onto the substrate at least partially overlaps with the orthographic projection of at least one of the first and second plates of the first capacitor onto the substrate.

[0085] The orthographic projection of the second light-shielding portion of the light-shielding structure located at least one sub-pixel onto the substrate at least partially overlaps with the orthographic projection of at least one of the first and second plates of the second capacitor onto the substrate.

[0086] In an exemplary embodiment, it further includes at least one of a plurality of power connection lines located in the fourth conductive layer and a plurality of reference connection lines located in the fifth conductive layer;

[0087] One of the plurality of power connection lines extends along a first direction, and one of the plurality of reference connection lines extends along a second direction;

[0088] At least one power connection line is electrically connected to at least one of a plurality of first power lines, and at least one reference connection line is electrically connected to at least one of a plurality of first reference signal lines.

[0089] The orthographic projection of at least one power connection line on the substrate is located between the orthographic projection of at least one first light-emitting signal line on the substrate and the orthographic projection of at least one second light-emitting signal line on the substrate, and at least partially overlaps with the orthographic projection of the second capacitor in the pixel driving circuit of at least one sub-pixel on the substrate.

[0090] At least one reference connection line is located between the first power line connected to the pixel driving circuit of at least one sub-pixel and the first power line connected to the pixel driving circuit of the first adjacent sub-pixel, and the center line of the at least one reference connection line extending along the first direction is on the same straight line as the axis of symmetry of the pixel driving circuit of at least one sub-pixel and the pixel driving circuit of the first adjacent sub-pixel.

[0091] At least one reference connection line is located between the data signal line connected to the pixel driving circuit of at least one sub-pixel and the first power supply line connected to the pixel driving circuit of the first adjacent sub-pixel.

[0092] Thirdly, this disclosure also provides a driving method for a pixel driving circuit, configured as the aforementioned pixel driving circuit, the method comprising:

[0093] The first control sub-circuit, under the control of at least one of the first scan signal line, the fourth scan signal line, and the fifth scan signal line, provides the data signal line signal to the fourth node, controls the signal of the fifth node through the signal of the fourth node, and provides the signal of the fifth node to the first node and the third node.

[0094] Under the control of at least one of the second scan signal line and the third scan signal line, the second control sub-circuit provides the signal of the second reference signal line to the second node, the signal of the first reference signal line to the fourth node, the signal of the first initial signal line to the fifth node, and the signal of the second initial signal line to the sixth node.

[0095] The third control sub-circuit, under the control of the signals from the first and second light-emitting signal lines, provides the first power line signal to the second node and the third node signal to the sixth node;

[0096] The driver sub-circuit provides a drive signal to the third node.

[0097] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.

[0098] Overview of the attached figures

[0099] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0100] Figure 1 is a schematic diagram of the pixel driving circuit provided in an embodiment of this disclosure;

[0101] Figure 2 is a schematic diagram of the structure of a first control sub-circuit provided in an exemplary embodiment;

[0102] Figure 3 is the equivalent circuit diagram of the first control sub-circuit provided in Figure 2;

[0103] Figure 4 is a schematic diagram of the structure of a second control sub-circuit provided in an exemplary embodiment;

[0104] Figure 5 is the equivalent circuit diagram of the second control sub-circuit provided in Figure 4;

[0105] Figure 6 shows the equivalent circuit diagram of the driving sub-circuit and the third control sub-circuit;

[0106] Figure 7 is an equivalent circuit diagram of the pixel driving circuit provided in an exemplary embodiment;

[0107] Figure 8 is the driving timing diagram of the pixel driving circuit provided in Figure 7 in the refresh frame;

[0108] Figure 9 is the driving timing diagram of the pixel de-working circuit provided in Figure 7 in the frame holding mode;

[0109] Figure 10 is a schematic diagram of the structure of the display substrate provided in an embodiment of this disclosure;

[0110] Figure 11 is a schematic diagram of a portion of the film layers in Figure 10;

[0111] Figure 12 is a schematic diagram of a portion of the film layers in Figure 10;

[0112] Figure 13 is a schematic diagram of the light-shielding layer pattern formed in Figure 10;

[0113] Figure 14 is a schematic diagram of the pattern of the first semiconductor layer in Figure 10;

[0114] Figure 15 is a schematic diagram after the first semiconductor layer pattern is formed in Figure 10;

[0115] Figure 16 is a schematic diagram of the first conductive layer pattern in Figure 10;

[0116] Figure 17 is a schematic diagram after the first conductive layer pattern in Figure 10 is formed;

[0117] Figure 18 is a schematic diagram of the second conductive layer pattern in Figure 10;

[0118] Figure 19 is a schematic diagram after the second conductive layer pattern is formed in Figure 10;

[0119] Figure 20 is a schematic diagram of the pattern of the second semiconductor layer in Figure 10;

[0120] Figure 21 is a schematic diagram after the second semiconductor layer pattern is formed in Figure 10;

[0121] Figure 22 is a schematic diagram of the third conductive layer pattern in Figure 10;

[0122] Figure 23 is a schematic diagram after the third conductive layer pattern is formed in Figure 10;

[0123] Figure 24 is a schematic diagram after the sixth insulating layer pattern is formed in Figure 10;

[0124] Figure 25 is a schematic diagram of the fourth conductive layer pattern in Figure 10;

[0125] Figure 26 is a schematic diagram after the fourth conductive layer pattern is formed in Figure 10;

[0126] Figure 27 is a schematic diagram after the first planarization layer pattern in Figure 10 is formed;

[0127] Figure 28 is a schematic diagram of the fifth conductive layer pattern in Figure 10;

[0128] Figure 29 is a schematic diagram of the fifth conductive layer pattern formed in Figure 10.

[0129] Detailed Explanation

[0130] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to with reference to general designs.

[0131] In the accompanying drawings, the size of the constituent elements, the thickness of the layers, or the area are sometimes exaggerated for clarity. Therefore, one aspect of this disclosure is not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0132] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0133] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0134] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0135] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0136] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0137] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0138] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0139] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0140] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0141] In OLED display products, the compensation process of the pixel driving circuit often occurs during the data writing process, resulting in a short compensation time for the pixel driving circuit and reducing its reliability.

[0142] To address this, this disclosure provides a pixel driving circuit that separates the compensation process from the data writing process.

[0143] Figure 1 is a schematic diagram of the pixel driving circuit provided in an embodiment of this disclosure. As shown in Figure 1, the pixel driving circuit provided in this embodiment is configured to drive the light-emitting device L to emit light. The pixel driving circuit includes: a first control sub-circuit, a second control sub-circuit, a third control sub-circuit, and a driving sub-circuit.

[0144] As shown in Figure 1, the first control sub-circuit is electrically connected to the first scan signal line Gate1, the fourth scan signal line Gate4, the fifth scan signal line Gate5, the data signal line Data, the first power supply line VDD, the first node N1, the third node N3, the fourth node N4, and the fifth node N5, respectively. It is configured to provide the data signal line Data to the fourth node N4 under the control of the signal of at least one of the first scan signal line Gate1, the fourth scan signal line Gate4, and the fifth scan signal line Gate5, control the signal of the fifth node N5 through the signal of the fourth node N4, and provide the signal of the fifth node N5 to the first node N1 and the third node N3.

[0145] As shown in Figure 1, the second control sub-circuit is electrically connected to the second scan signal line Gate2, the third scan signal line Gate3, the first initial signal line INIT1, the second initial signal line INIT2, the first reference signal line REF1, the second reference signal line REF2, the second node N2, the fourth node N4, the fifth node N5, and the sixth node N6, respectively. It is configured to provide the signal of the second reference signal line REF2 to the second node N2, the signal of the first reference signal line REF1 to the fourth node N4, the signal of the first initial signal line INIT1 to the fifth node N5, and the signal of the second initial signal line INIT2 to the sixth node N6, under the control of the signal of at least one of the second scan signal lines Gate2 and Gate3.

[0146] As shown in Figure 1, the third control sub-circuit is electrically connected to the first light-emitting signal line EM1, the second light-emitting signal line EM2, the first power supply line VDD, the second node N2, the third node N3, and the sixth node N6, respectively. It is configured to provide the first power supply line VDD signal to the second node N2 and the third node N3 signal to the sixth node N6 under the control of the signals of the first light-emitting signal line EM1 and the second light-emitting signal line EM2.

[0147] As shown in Figure 1, the driving sub-circuit is electrically connected to the first node N1, the second node N2 and the third node N3 respectively, and is configured to provide a driving signal to the third node N3.

[0148] As shown in Figure 1, the light-emitting device L is electrically connected to the sixth node N6 and the second power line VSS.

[0149] In an exemplary embodiment, the voltage value of the signal on the first initial signal line INIT1 is constant and is a DC signal; the voltage value of the signal on the first initial signal line INIT1 can be -3V. In an exemplary embodiment, a DC signal can be one in which neither the magnitude nor the direction of the signal changes with time.

[0150] In an exemplary embodiment, the voltage value of the signal on the second initial signal line INIT2 is constant and is a DC signal; the voltage value of the signal on the second initial signal line INIT2 can be 0V.

[0151] In an exemplary embodiment, the voltage values ​​of the signals on the first reference signal line REF1 and the second reference signal line REF2 are constant and are DC signals.

[0152] In an exemplary embodiment, the first power line VDD continuously provides a high-level signal, and the second power line VSS continuously provides a low-level signal.

[0153] In an exemplary embodiment, the light-emitting device L may include a current-driven device, such as a current-driven light-emitting diode, like a micro light-emitting diode (Micro LED), a mini light-emitting diode (Mini LED), an organic light-emitting diode (OLED), or a quantum light-emitting diode (QLED). The typical size (e.g., length) of a Micro LED can be less than 100 μm, for example, 10 μm to 50 μm. The typical size (e.g., length) of a Mini LED can be approximately 100 μm to 300 μm, for example, 120 μm to 260 μm.

[0154] In an exemplary embodiment, the light-emitting device L may be an organic light-emitting diode (OLED), including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode). Exemplarily, the anode of the light-emitting device L is electrically connected to a sixth node N6, and the cathode of the light-emitting device L is electrically connected to a second power line VSS.

[0155] In an exemplary embodiment, the organic light-emitting layer may include stacked hole injection layer (HIL), hole transport layer (HTL), electron block layer (EBL), emitting layer (EML), hole block layer (HBL), electron transport layer (ETL), and electron injection layer (EIL). In this exemplary embodiment, the hole injection layers of all sub-pixels may be a common layer connected together, the electron injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the hole block layers of all sub-pixels may be a common layer connected together, and the emitting layers of adjacent sub-pixels may have a small overlap or may be isolated. Similarly, the electron block layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0156] The pixel driving circuit provided in this embodiment can be disposed in a display substrate employing high / low frame rate switching technology. The display substrate may include a first driving mode and a second driving mode, wherein the refresh rate of the first driving mode is lower than the refresh rate of the second driving mode. For example, the refresh rate of the first driving mode may be 1Hz-60Hz, and the refresh rate of the second driving mode may be 60Hz-480Hz.

[0157] In an exemplary embodiment, the first driving mode may be referred to as a low-frequency driving mode, and the second driving mode may be referred to as a high-frequency driving mode. In an exemplary embodiment, the refresh rate refers to the number of times the display substrate refreshes data per second. The refresh rate of the first driving mode set for the same display substrate is fixed, while the refresh rate of the first driving mode set for different display substrates may be different. The refresh rate of the display substrate in the first driving mode can range from 1Hz to 60Hz; for example, the refresh rate in the first driving mode can be approximately 10Hz, and the refresh rate in the second driving mode can be 120Hz.

[0158] In an exemplary embodiment, the content displayed on the display substrate includes multiple display frames. In a first driving mode, the display frames include a refresh frame and at least one hold frame. In a second driving mode, the display frames include only a refresh frame.

[0159] The pixel driving circuit disclosed herein can operate normally in refresh frames and hold frames to ensure normal display on the display substrate.

[0160] The pixel driving circuit provided in this disclosure, through the cooperation of the first control sub-circuit, the second control sub-circuit, and the third control sub-circuit, enables the threshold compensation stage of the pixel driving circuit to be independent of the data writing stage, thereby extending the compensation time of the pixel driving circuit and improving the reliability of the pixel driving circuit.

[0161] In an exemplary embodiment, FIG2 is a schematic diagram of the structure of a first control sub-circuit provided in an exemplary embodiment. As shown in FIG2, the first control sub-circuit includes: a write sub-circuit, a first storage sub-circuit, a connection sub-circuit, and a second storage sub-circuit.

[0162] As shown in Figure 2, the write sub-circuit is electrically connected to the first scan signal line Gate1, the data signal line Data, and the fourth node N4, respectively. It is configured to provide the data signal line Data to the fourth node N4 under the control of the signal of the first scan signal line Gate1.

[0163] As shown in Figure 2, the first storage sub-circuit is electrically connected to the fourth node N4 and the fifth node N5 respectively, and is configured to store the voltage difference between the signals of the fourth node N4 and the fifth node N5.

[0164] As shown in Figure 2, the connected sub-circuit is electrically connected to the fourth scan signal line Gate4, the fifth scan signal line Gate5, the first node N1, the third node N3, and the fifth node N5, respectively. It is configured to provide the signal of the fifth node N5 to the third node N3 under the control of the signal of the fifth scan signal line Gate5, and to provide the signal of the fifth node N5 to the first node N1 under the control of the signal of the fourth scan signal line Gate4.

[0165] As shown in Figure 2, the second storage sub-circuit is electrically connected to the first node N1 and the first power line VDD, respectively, and is configured to store the voltage difference between the signals of the first node N1 and the first power line VDD.

[0166] In an exemplary embodiment, the signal received by the fifth scanning signal line Gate5 may be the same as the signal received by the first light-emitting signal line EM1. For example, the fifth scanning signal line Gate5 and the first light-emitting signal line EM1 may be the same signal line.

[0167] In an exemplary embodiment, FIG3 is an equivalent circuit diagram of the first control sub-circuit provided in FIG2. As shown in FIG3, the connected sub-circuit includes: a second transistor T2 and an eighth transistor T8. The control electrode of the second transistor T2 is electrically connected to the fifth scan signal line Gate5, the first electrode of the second transistor T2 is electrically connected to the fifth node N5, and the second electrode of the second transistor T2 is electrically connected to the third node N3; the control electrode of the eighth transistor T8 is electrically connected to the fourth scan signal line Gate4, the first electrode of the eighth transistor T8 is electrically connected to the fifth node N5, and the second electrode of the eighth transistor T8 is electrically connected to the first node N1.

[0168] In this disclosure, the eighth transistor T8 can be configured such that when the eighth transistor is in the off state, the fifth node N5 and the first node N1 are spaced apart, thereby reducing the influence of the fifth node N5 on the first node N1.

[0169] In an exemplary embodiment, as shown in FIG3, the write sub-circuit includes a fourth transistor T4. The control electrode of the fourth transistor T4 is electrically connected to the first scan signal line Gate1, the first electrode of the fourth transistor T4 is electrically connected to the data signal line Data, and the second electrode of the fourth transistor T4 is electrically connected to the fourth node N4. The fourth transistor T4 can be referred to as the write transistor.

[0170] In an exemplary embodiment, as shown in FIG3, the first storage sub-circuit includes a first capacitor C1. The first capacitor C1 includes a first plate C11 and a second plate C12. The first plate C11 of the first capacitor C1 is electrically connected to the fifth node N5, and the second plate C12 of the first capacitor C1 is electrically connected to the fourth node N4.

[0171] In an exemplary embodiment, as shown in FIG3, the second storage sub-circuit includes a second capacitor C2. The second capacitor C2 includes a first plate C21 and a second plate C22, wherein the first plate C21 of the second capacitor C2 is electrically connected to the first node N1, and the second plate C22 of the second capacitor C2 is electrically connected to the first power line VDD.

[0172] The inclusion of the second capacitor C2 in this disclosure ensures the stability of the signal at the first node N1, thereby improving the reliability of the pixel driving circuit.

[0173] Figure 3 shows an exemplary structure of the first control sub-circuit. It will be readily understood by those skilled in the art that the implementation of the first control sub-circuit is not limited to this.

[0174] In an exemplary embodiment, FIG4 is a schematic diagram of the structure of a second control sub-circuit provided in an exemplary embodiment. As shown in FIG4, the second control sub-circuit includes: a first sub-circuit, a second sub-circuit, a third sub-circuit, and a fourth sub-circuit.

[0175] In an exemplary embodiment, as shown in FIG4, the first sub-circuit is electrically connected to the second scan signal line Gate2, the first initial signal line INIT1 and the fifth node N5 respectively, and is configured to provide the signal of the first initial signal line INIT1 to the fifth node N5 under the control of the signal of the second scan signal line Gate2.

[0176] In an exemplary embodiment, as shown in FIG4, the second sub-circuit is electrically connected to the third scan signal line Gate3, the first reference signal line REF1 and the fourth node N4 respectively, and is configured to provide the signal of the first reference signal line REF1 to the fourth node N4 under the control of the signal of the third scan signal line Gate3.

[0177] In an exemplary embodiment, as shown in FIG4, the third sub-circuit is electrically connected to the second scan signal line Gate2, the second reference signal line REF2, and the second node N2, respectively, and is configured to provide the signal of the second reference signal line REF2 to the second node N2 under the control of the signal of the second scan signal line Gate2.

[0178] In an exemplary embodiment, as shown in FIG4, the fourth sub-circuit is electrically connected to the second scan signal line Gate2, the second initial signal line INIT2 and the sixth node N6 respectively, and is configured to provide the signal of the second initial signal line INIT2 to the sixth node N6 under the control of the signal of the second scan signal line Gate2.

[0179] In an exemplary embodiment, FIG5 is an equivalent circuit diagram of the second control sub-circuit provided in FIG4. As shown in FIG5, the first sub-circuit includes a first transistor T1. The control electrode of the first transistor T1 is electrically connected to the second scan signal line Gate2, the first electrode of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected to the fifth node N5. The first transistor T1 can be referred to as the first initialization transistor.

[0180] In an exemplary embodiment, as shown in FIG5, the second sub-circuit includes a seventh transistor T7. The control electrode of the seventh transistor T7 is electrically connected to the third scan signal line Gate3, the first electrode of the seventh transistor T7 is electrically connected to the first reference signal line REF1, and the second electrode of the seventh transistor T7 is electrically connected to the fourth node N4.

[0181] In an exemplary embodiment, as shown in FIG5, the third sub-circuit includes a ninth transistor T9. The control electrode of the ninth transistor T9 is electrically connected to the second scan signal line Gate2, the first electrode of the ninth transistor T9 is electrically connected to the second reference signal line REF2, and the second electrode of the ninth transistor T9 is electrically connected to the second node N2. The ninth transistor T9 can be referred to as a bias transistor.

[0182] The configuration of the ninth transistor T9 in this disclosure can increase the voltage difference between the control electrode and the first electrode of the third transistor, which can make the third transistor T3 (also the driving transistor) be in a bias state for a certain period of time, thereby improving the hysteresis phenomenon.

[0183] In an exemplary embodiment, as shown in FIG5, the fourth sub-circuit includes a tenth transistor T10. The control electrode of the tenth transistor T10 is electrically connected to the second scan signal line Gate2, the first electrode of the tenth transistor T10 is electrically connected to the second initial signal line INIT2, and the second electrode of the tenth transistor T10 is electrically connected to the sixth node N6. The tenth transistor T10 can be referred to as the second initialization transistor.

[0184] Figure 5 shows an exemplary structure of the second control sub-circuit. It will be readily understood by those skilled in the art that the implementation of the second control sub-circuit is not limited to this.

[0185] In an exemplary embodiment, FIG6 is an equivalent circuit diagram of the driving sub-circuit and the third control sub-circuit. As shown in FIG6, the driving sub-circuit includes a third transistor T3. The control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3. The third transistor T3 can be referred to as the driving transistor, and the third transistor T3 determines the driving current flowing between the first power line VDD and the second power line VSS based on the potential difference between its control electrode and its second electrode.

[0186] Figure 6 shows an exemplary structure of the driver sub-circuit. It will be readily understood by those skilled in the art that the implementation of the driver sub-circuit is not limited to this.

[0187] In an exemplary embodiment, as shown in FIG6, the third control sub-circuit includes a fifth transistor T5 and a sixth transistor T6. The control electrode of the fifth transistor T5 is electrically connected to the first light-emitting signal line EM1, the first electrode of the fifth transistor T5 is electrically connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2. The control electrode of the sixth transistor T6 is electrically connected to the second light-emitting signal line EM2, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the sixth node N6. The fifth transistor T5 can be referred to as the first light-emitting transistor, and the sixth transistor T6 can be referred to as the second light-emitting transistor. When the signals of the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are at valid levels, the fifth transistor T5 and the sixth transistor T6 cause the light-emitting device to emit light by forming a driving current path between the first power supply line VDD and the second power supply line VSS.

[0188] Figure 6 illustrates an exemplary structure of the third control sub-circuit. It will be readily understood by those skilled in the art that the implementation of the third control sub-circuit is not limited to this.

[0189] Figure 7 is an equivalent circuit diagram of a pixel driving circuit provided in an exemplary embodiment. As shown in Figure 7, the first control sub-circuit includes: a second transistor T2, a fourth transistor T4, an eighth transistor T8, a first capacitor C1, and a second capacitor C2. At least one of the first capacitor C1 and the second capacitor C2 includes: a first electrode and a second electrode. The second control sub-circuit includes: a first transistor T1, a seventh transistor T7, a ninth transistor T9, and a tenth transistor T10. The third control sub-circuit includes: a fifth transistor T5 and a sixth transistor T6. The driving sub-circuit includes: a third transistor T3. Specifically, the control electrode of the first transistor T1 is electrically connected to the second scan signal line Gate2, the first electrode of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected to the fifth node N5; the control electrode of the second transistor T2 is electrically connected to the fifth scan signal line Gate5, the first electrode of the second transistor T2 is electrically connected to the fifth node N5, and the second electrode of the second transistor T2 is electrically connected to the third node N3; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the first scan signal line Gate1, the first electrode of the fourth transistor T4 is electrically connected to the data signal line Data, and the second electrode of the fourth transistor T4 is electrically connected to the fourth node N4. The control electrode of the fifth transistor T5 is electrically connected to the first light-emitting signal line EM1, the first electrode of the fifth transistor T5 is electrically connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2; the control electrode of the sixth transistor T6 is electrically connected to the second light-emitting signal line EM2, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the sixth node N6; the control electrode of the seventh transistor T7 is electrically connected to the third scan signal line Gate3, the first electrode of the seventh transistor T7 is electrically connected to the first reference signal line REF1, and the second electrode of the seventh transistor T7 is electrically connected to the fourth node N4; the control electrode of the eighth transistor T8 is electrically connected to the fourth scan signal line Gate4, the first electrode of the eighth transistor T8 is electrically connected to the fifth node N5, and the second electrode of the eighth transistor T8 is electrically connected to the first node N1.The control electrode of the ninth transistor T9 is electrically connected to the second scan signal line Gate2, the first electrode of the ninth transistor T9 is electrically connected to the second reference signal line REF2, and the second electrode of the ninth transistor T9 is electrically connected to the second node N2; the control electrode of the tenth transistor T10 is electrically connected to the second scan signal line Gate2, the first electrode of the tenth transistor T10 is electrically connected to the second initial signal line INIT2, and the second electrode of the tenth transistor T10 is electrically connected to the sixth node N6; the first plate C11 of the first capacitor C1 is electrically connected to the fifth node N5, and the second plate C12 of the first capacitor C1 is electrically connected to the fourth node N4; the first plate C21 of the second capacitor C2 is electrically connected to the first node N1, and the second plate C22 of the second capacitor C2 is electrically connected to the first power supply line VDD.

[0190] Based on their characteristics, transistors can be classified into N-type transistors and P-type transistors. When a transistor is P-type, its on-state voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage), and its off-state voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage). When a transistor is N-type, its on-state voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage), and its off-state voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage).

[0191] In an exemplary embodiment, the N-type transistor can be an oxide thin-film transistor. The active layer of the oxide thin-film transistor is made of oxide semiconductor. Oxide thin-film transistors have advantages such as low leakage current, uniform film formation, good transistor hysteresis characteristics, and low manufacturing cost.

[0192] In an exemplary embodiment, the P-type transistor can be a low-temperature polycrystalline silicon transistor. Low-temperature polycrystalline silicon transistors have advantages such as high mobility and fast charging.

[0193] In an exemplary embodiment, the transistor type of the eighth transistor T8 is different from the transistor type of at least one of the first transistors T1 to the seventh transistor T7, the ninth transistor T9, and the tenth transistor T10.

[0194] In an exemplary embodiment, the eighth transistor T8 is an N-type transistor. The fact that the eighth transistor T8 is an N-type transistor can prevent leakage current flowing from the first node N1, ensure the stability of the signal at the first node N1, improve the performance of the pixel driving circuit, reduce the power consumption of the pixel driving circuit, and prevent flickering on the display substrate where the pixel driving circuit is located, thereby improving the display effect of the display substrate.

[0195] In an exemplary embodiment, at least one of the first transistor T1 to the seventh transistor T7, the ninth transistor T9, and the tenth transistor T10 may be a P-type transistor.

[0196] In an exemplary embodiment, when the pixel driving circuit includes P-type transistors and N-type transistors, that is, low-temperature polycrystalline silicon transistors and oxide transistors are integrated on a display substrate to form a display substrate combining low-temperature polycrystalline silicon and oxide (LTPO), the advantages of both can be utilized to achieve low-frequency driving, reduce power consumption, and improve display quality.

[0197] Figure 8 is the driving timing diagram of the pixel driving circuit provided in Figure 7 in the refresh frame, and Figure 9 is the driving timing diagram of the pixel driving circuit provided in Figure 7 in the hold frame. Figures 8 and 9 are illustrated using the example that in the pixel driving circuit of Figure 7, the eighth transistor T8 is an N-type transistor, at least one of the first transistors T1 to the seventh transistor T7, the ninth transistor T9, and the tenth transistor T10 is a P-type transistor, and the signal received by the fifth scan signal line Gate5 is the same as the signal received by the first light emission signal line EM1.

[0198] As shown in Figure 8, during the refresh frame, the time period when the signal of the first light-emitting signal line EM1 is an effective level signal includes: a first time period t1 and a second time period t2, with the first time period t1 occurring before the second time period t2.

[0199] In an exemplary embodiment, as shown in FIG8, the signal of the first scan signal line Gate1 is at an effective level signal between a first time period t1 and a second time period t2. An effective level signal on a signal line means that the transistor connected to the signal line is in a conducting state, where the transistor connected to the signal line includes the signal line being connected to the control electrode of the transistor.

[0200] In an exemplary embodiment, as shown in FIG8, the time periods during which the signal of the second scan signal line Gate2 is an effective level signal include: a third time period t3 and a fourth time period t4. The third time period t3 occurs before the first time period t1, and the fourth time period t4 occurs between the first time period t1 and the second time period t2.

[0201] In an exemplary embodiment, as shown in FIG8, the time period during which the signal of the third scan signal line Gate3 is at an effective level overlaps at least partially with at least one of the first time period t1 and the third time period t3. Exemplarily, the start time of the time period during which the signal of the third scan signal line Gate3 is at an effective level is later than the start time of the third time period t3 and earlier than the end time of the third time period t3, and the end time of the time period during which the signal of the third scan signal line Gate3 is at an effective level is earlier than the start time of the time period during which the signal of the first scan signal line Gate1 is at an effective level.

[0202] In an exemplary embodiment, as shown in FIG8, the time period during which the signal of the fourth scan signal line Gate4 is at an effective level overlaps at least partially with at least one of the first time period t1 and the third time period t3. The start time of the time period during which the signal of the fourth scan signal line Gate4 is at an effective level is later than the start time of the third time period t3, but earlier than the start time of the time period during which the signal of the third scan signal line Gate3 is at an effective level. The end time of the time period during which the signal of the fourth scan signal line Gate4 is at an effective level is later than the end time of the time period during which the signal of the first scan signal line Gate1 is at an effective level, but earlier than the start time of the fourth time period t4.

[0203] In an exemplary embodiment, as shown in FIG8, the time during which the signal of the second light-emitting signal line EM2 is an effective level signal at least partially overlaps with the second time period t2.

[0204] The exemplary embodiments of this disclosure are described below using the operation of the pixel driving circuit illustrated in FIG7. As shown in FIG7 and FIG8, the operation of the pixel driving circuit provided in FIG7 during the refresh frame may include:

[0205] In the first stage (P1), the initialization stage, the signals of the first scan signal line (Gate1), the third scan signal line (Gate3), the fourth scan signal line (Gate4), the fifth scan signal line (Gate5), the first light-emitting signal line (EM1), and the second light-emitting signal line (EM2) are high-level signals, while the signal of the second scan signal line (Gate2) is low-level. The first transistor (T1), the eighth transistor (T8), the ninth transistor (T9), and the tenth transistor (T10) are turned on, while the second transistor (T2), the fourth transistor (T4), the fifth transistor (T5), the sixth transistor (T6), and the seventh transistor (T7) are turned off.

[0206] The first transistor T1 is turned on, and the signal from the first initial signal line INIT1 is written to the fifth node N5, initializing the fifth node N5 and clearing its charge. The eighth transistor T8 is turned on, and the signal from the fifth node N5 is written to the first node N1, initializing the first node N1 and clearing its charge. The ninth transistor T9 is turned on, and the signal from the second reference signal line REF is written to the second node. The tenth transistor T10 is turned on, and the signal from the second initial signal line INIT2 is written to the sixth node N6, initializing the sixth node N6 and clearing its charge.

[0207] In this phase, the voltage value V of the signal at the first node N1 N1 =Vinit1, the voltage value V of the signal at the second node N2. N2 =Vref2, the voltage value V of the signal at the fifth node N5. N5 =Vinit1, the voltage value V of the signal at the sixth node N6. N6 =Vinit2, where Vinit1 is the voltage value of the first initial signal line INIT1, Vinit2 is the voltage value of the second initial signal line INIT2, and Vref2 is the voltage value of the second reference signal line REF2.

[0208] In the second stage, P2, the threshold compensation stage, the signals of the first scan signal line Gate1, the second scan signal line Gate2, the fourth scan signal line Gate4, and the second light-emitting signal line EM2 are high-level signals, while the signals of the third scan signal line Gate3, the fifth scan signal line Gate5, and the first light-emitting signal line EM1 are low-level signals. The second transistor T2, the fifth transistor T5, the seventh transistor T7, and the eighth transistor T8 are turned on, while the first transistor T1, the fourth transistor T4, the sixth transistor T6, the ninth transistor T9, and the tenth transistor T10 are turned off.

[0209] When the seventh transistor T7 is turned on, the signal of the first reference signal line REF1 is written to the fourth node N4. The second transistor T2, the fifth transistor T5, and the eighth transistor T8 are turned on, and the signal of the first power line VDD is written to the first node N1 through the turned-on fifth transistor T5, the second node N2, the turned-on third transistor T3, the third node N3, the turned-on second transistor T2, the fifth node N5, and the turned-on eighth transistor T8, until the voltage value of the signal at the first node N1 satisfies V... N1 =Vdd+Vth, where Vdd is the voltage value of the signal on the first power line VDD, and Vth is the threshold voltage of the third transistor T3.

[0210] In this phase, the voltage value V of the signal at the first node N1 N1 =Vdd + Vth, where V is the voltage value of the signal at the second node N2.N2 =Vdd, the voltage value V of the signal at the third node N3. N3 =Vdd + Vth, the voltage value V of the signal at the fourth node N4. N4 =Vref1, the voltage value V of the signal at the fifth node N5. N5 =Vdd+Vth, where Vref1 is the voltage value of the signal on the first reference signal line REF1.

[0211] In the third stage (P3), the data writing stage, the signals of the second scan signal line (Gate2), the third scan signal line (Gate3), the fourth scan signal line (Gate4), the fifth scan signal line (Gate5), the first light-emitting signal line (EM1), and the second light-emitting signal line (EM2) are high-level signals, while the signal of the first scan signal line (Gate1) is low-level. The fourth transistor (T4) and the eighth transistor (T8) are turned on. The first transistor (T1), the second transistor (T2), the fifth transistor (T5), the sixth transistor (T6), the seventh transistor (T7), the eighth transistor (T8), the ninth transistor (T9), and the tenth transistor (T10) are turned off.

[0212] The fourth transistor T4 is turned on, and the data signal on the data signal line Data is written to the fourth node N4. Because the signal at the fourth node N4 has changed, the signal at the fifth node N5 also changes due to the action of the first capacitor C1. The voltage value V of the signal at the fifth node N5... N5 =Vdd+Vth+α(Vdata-Vref1), 0<α<1, Vdata is the voltage value of the data signal on the data signal line, the eighth transistor T8 is turned on, and the signal of the fifth node N5 is written to the first node N1.

[0213] In this phase, the voltage value V of the signal at the first node N1 N1 =Vdd + Vth + α(Vdata - Vref1), where V is the voltage value of the signal at the fourth node N4. N4 =Vdata, the voltage value V of the signal at the fifth node N5. N5 =Vdd+Vth+α(Vdata-Vref1).

[0214] In the fourth stage, P4, the bias stage, the signals of the first scan signal line Gate1, the third scan signal line Gate3, the fifth scan signal line Gate5, the first light emission signal line EM1, and the second light emission signal line EM2 are high-level signals, while the signals of the second scan signal line Gate2 and the fourth scan signal line Gate4 are low-level signals. The first transistor T1, the ninth transistor T9, and the tenth transistor T10 are turned on, while the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0215] The first transistor T1 is turned on, and the signal of the first initial signal line INIT1 is written to the fifth node N5. Since the eighth transistor T8 is turned off, the first node N1 retains the signal from the previous stage and is not affected by the signal of the fifth node N5. The ninth transistor T9 is turned on, and the signal of the second reference signal line REF is written to the second node N2. Since the voltage value of the signal at the first node N1 is Vdd + Vth + α(Vdata - Vref1), the signal of the second reference signal line written to the second node N2 in this stage can bias the third transistor T3, making the third transistor T3 in a biased state. The tenth transistor T10 is turned on, and the signal of the second initial signal line INIT2 is written to the sixth node N6, initializing the sixth node N6 and clearing the charge of the sixth node N6.

[0216] In this phase, the voltage value V of the signal at the first node N1 N1 =Vdd + Vth + α(Vdata - Vref1), where V is the voltage value of the signal at the second node N2. N2 =Vref2, the voltage value V of the signal at the fifth node N5. N5 =Vinit1, the voltage value V of the signal at the sixth node N6. N6 =Vinit2.

[0217] In the fifth stage (P5), the light-emitting stage, the signals on the first scan signal line (Gate1), the second scan signal line (Gate2), and the third scan signal line (Gate3) are high-level signals, while the signals on the fourth scan signal line (Gate4), the fifth scan signal line (Gate5), the first light-emitting signal line (EM1), and the second light-emitting signal line (EM2) are low-level signals. The second transistor (T2), the fifth transistor (T5), and the sixth transistor (T6) are turned on.

[0218] When the fifth transistor T5 and the sixth transistor T6 are turned on, the power supply voltage output from the first power line VDD provides driving current to the sixth node N6 (which is also the first terminal of the light-emitting device L) through the turned-on fifth transistor T5, the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on sixth transistor T6, so as to drive the light-emitting device L to emit light.

[0219] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and its second electrode. Since the voltage of the signal at the first node N1 satisfies V... N1 =Vdd + Vth + α(Vdata - Vref1), the voltage value of the signal at the second node N2 satisfies V N2 =Vdd.

[0220] Therefore, the drive current I of the third transistor T3 is:

[0221] I = K * (Vgs - Vth) 2

[0222] =K*[Vdd+Vth+α(Vdata-Vref1)–Vdd-Vth] 2

[0223] =K*[α(Vdata-Vref1)] 2

[0224] Where I is the driving current flowing through the third transistor T3, which is the driving current driving the light-emitting device L, K is a constant related to the process and design of the pixel driving circuit, and Vgs is the voltage difference between the control electrode and the first electrode of the third transistor T3.

[0225] As shown in Figure 9, during the hold frame, at least one of the first scan signal line Gate1, the third scan signal line Gate3, and the fourth scan signal line Gate4 continuously has an invalid signal level.

[0226] As shown in Figures 7 and 9, the pixel driving circuit provided in Figure 7 can include the following during the frame holding process:

[0227] In the sixth stage (P6), the bias holding stage, the signals of the first scan signal line Gate1, the third scan signal line Gate3, the fifth scan signal line Gate5, the first light emission signal line EM1, and the second light emission signal line EM2 are high-level signals, while the signals of the second scan signal line Gate2 and the fourth scan signal line Gate4 are low-level signals. The first transistor T1, the ninth transistor T9, and the tenth transistor T10 are turned on, while the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0228] The first transistor T1 is turned on, and the signal of the first initial signal line INIT1 is written to the fifth node N5. Since the eighth transistor T8 is turned off, the first node N1 retains the signal from the previous stage and is not affected by the signal of the fifth node N5. The ninth transistor T9 is turned on, and the signal of the second reference signal line REF is written to the second node N2. Since the voltage value of the signal at the first node N1 is Vdd + Vth + α(Vdata - Vref1), the signal of the second reference signal line written to the second node N2 in this stage can bias the third transistor T3, making the third transistor T3 in a biased state. The tenth transistor T10 is turned on, and the signal of the second initial signal line INIT2 is written to the sixth node N6, initializing the sixth node N6 and clearing the charge of the sixth node N6.

[0229] In the seventh stage (P7), the light-emitting stage, the signals on the first scan signal line Gate1, the second scan signal line Gate2, and the third scan signal line Gate3 are high-level signals, while the signals on the fourth scan signal line Gate4, the fifth scan signal line Gate5, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are low-level signals. The second transistor T2, the fifth transistor T5, and the sixth transistor T6 are turned on.

[0230] When the fifth transistor T5 and the sixth transistor T6 are turned on, the power supply voltage output from the first power line VDD provides driving current to the sixth node N6 (which is also the first terminal of the light-emitting device L) through the turned-on fifth transistor T5, the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on sixth transistor T6, so as to drive the light-emitting device L to emit light.

[0231] Analysis of the pixel driving circuit's operation reveals that the threshold compensation stage and data writing stage of the pixel driving circuit provided in this disclosure are set independently. The threshold compensation time depends on the duration of the first time period when the first light-emitting signal line is at an effective level. The pixel driving circuit provided in this disclosure can extend the threshold compensation time, resulting in more thorough threshold compensation. This not only improves the display effect of the display substrate but also helps maintain the stability of the threshold voltage of the third transistor, significantly reducing image retention and further enhancing the display effect of the display substrate.

[0232] This disclosure also provides a driving method for a pixel driving circuit, configured as the pixel driving circuit provided in any of the foregoing embodiments. The driving method for the pixel driving circuit may include the following steps:

[0233] Step 100: Under the control of at least one of the first scan signal line, the fourth scan signal line, and the fifth scan signal line, the first control sub-circuit provides the data signal line signal to the fourth node, controls the signal of the fifth node through the signal of the fourth node, and provides the signal of the fifth node to the first node and the third node.

[0234] Step 200: Under the control of at least one of the second scan signal line and the third scan signal line, the second control sub-circuit provides the signal of the second reference signal line to the second node, the signal of the first reference signal line to the fourth node, the signal of the first initial signal line to the fifth node, and the signal of the second initial signal line to the sixth node.

[0235] Step 300: Under the control of the signals from the first and second light-emitting signal lines, the third control sub-circuit provides the first power line signal to the second node and the third node signal to the sixth node.

[0236] Step 400: The driving sub-circuit provides a driving signal to the third node.

[0237] Figure 10 is a schematic diagram of the structure of a display substrate provided in an embodiment of this disclosure. As shown in Figure 10, an embodiment of this disclosure also provides a display device, which includes a display substrate. The display substrate includes a base and a plurality of sub-pixels arranged in an array on the base. At least one of the plurality of sub-pixels includes a pixel driving circuit provided in any of the preceding embodiments. Figure 10 illustrates an example with a row of three columns of pixel driving circuits, where at least one pixel driving circuit is connected to the same signal line as the first light-emitting signal line.

[0238] In an exemplary embodiment, as shown in FIG10, for at least one row of sub-pixels, the two adjacent sub-pixels of at least one sub-pixel include: a first adjacent sub-pixel and a second adjacent sub-pixel. The structure of the pixel driving circuit of at least one sub-pixel is at least partially symmetrical to the structure of the pixel driving circuit of the first adjacent sub-pixel along a straight line extending in the second direction D2, and the structure of the pixel driving circuit of at least one sub-pixel is at least partially the same as the structure of the pixel driving circuit of the second adjacent sub-pixel. In FIG10, the pixel driving circuit of at least one sub-pixel is P2, the pixel driving circuit of the first adjacent sub-pixel is P1, and the pixel driving circuit of the second adjacent sub-pixel is P3.

[0239] In an exemplary embodiment, as shown in FIG10, the display device further includes: a plurality of data signal lines Data, one of which extends along a second direction D2.

[0240] In an exemplary embodiment, for at least one row of sub-pixels, the multiple data signal lines Data connected to the pixel driving circuit of at least one sub-pixel and the multiple data signal lines Data connected to the pixel driving circuit of the first adjacent sub-pixel are symmetrically arranged along a straight line extending in a second direction, and the multiple data signal lines Data connected to the pixel driving circuit of at least one sub-pixel and the multiple data signal lines Data connected to the pixel driving circuit of the second adjacent sub-pixel have the same structure.

[0241] In an exemplary embodiment, FIG11 is a partial schematic diagram of the film layer in FIG10. Referring to FIGS. 10 and 11, the pixel driving circuit for at least one sub-pixel includes: a second transistor T2, a third transistor, and a sixth transistor T6. At least one data signal line Data does not overlap with the orthographic projections on the substrate of the first and second electrodes of at least one of the second transistors T2, T3, and T6 in the pixel driving circuit for at least one sub-pixel; at least one data signal line Data does not overlap with the orthographic projection on the substrate of the control electrode of the third transistor in the pixel driving circuit for at least one sub-pixel. The third transistor in FIGS. 10 and 11 is covered by a second capacitor.

[0242] The fact that at least one data signal line Data in this disclosure does not overlap with the orthographic projections of the first and second electrodes of at least one of the second transistors T2, T3, and T6 in the pixel driving circuit of at least one sub-pixel on the substrate can avoid the influence of the data signal line on the signal of the fourth node in the pixel driving circuit, thus ensuring the stability of the signal of the fourth node in the pixel driving circuit and improving the reliability of the pixel driving circuit.

[0243] The fact that at least one data signal line Data in this disclosure does not overlap with the orthographic projection of the control electrode of the third transistor T3 in the pixel driving circuit of at least one sub-pixel on the substrate can avoid the influence of the data signal line on the signal of the first node in the pixel driving circuit, thus ensuring the stability of the signal of the first node in the pixel driving circuit and improving the reliability of the pixel driving circuit.

[0244] In an exemplary embodiment, as shown in FIG10, the display device further includes: a plurality of second scan signal lines Gate2, the plurality of second scan signal lines Gate2 extending at least partially along a first direction D1, the first direction D1 intersecting with a second direction D2.

[0245] As shown in Figure 11, the pixel driving circuit for at least one sub-pixel includes: a first transistor T1, a ninth transistor T9, and a tenth transistor T10.

[0246] Referring to Figures 10 and 11, the pixel driving circuit of at least one sub-pixel is electrically connected to two second scan signal lines Gate2. The control electrode of the first transistor T1 in the pixel driving circuit of at least one sub-pixel is electrically connected to the first second scan signal line Gate2 of the two second scan signal lines Gate2 connected to the pixel driving circuit of at least one sub-pixel. The control electrode of at least one of the ninth transistor T9 and the tenth transistor T10 in the pixel driving circuit of at least one sub-pixel is electrically connected to the first second scan signal line Gate2 of the two second scan signal lines Gate2 connected to the pixel driving circuit of at least one sub-pixel.

[0247] In an exemplary embodiment, as shown in Figures 10 and 11, the display device further includes: multiple first initial signal lines INIT1, multiple second initial signal lines INIT2, multiple first reference signal lines REF1, multiple second reference signal lines REF2, multiple first scan signal lines Gate1, multiple third scan signal lines Gate3, multiple fourth scan signal lines Gate4, multiple first light emission signal lines EM1, and multiple second light emission signal lines EM2.

[0248] In an exemplary embodiment, at least a portion of at least one of the following signal lines extends along a first direction D1: a plurality of first initial signal lines INIT1, a plurality of second initial signal lines INIT2, a plurality of first reference signal lines REF1, a plurality of second reference signal lines REF2, a plurality of first scan signal lines Gate1, a plurality of third scan signal lines Gate3, a plurality of fourth scan signal lines Gate4, a plurality of first light emission signal lines EM1, and a plurality of second light emission signal lines EM2.

[0249] In an exemplary embodiment, the orthographic projections of the first reference signal line REF1, the third scan signal line Gate3, the first scan signal line Gate1, the first second scan signal line Gate2, the fourth scan signal line Gate4, the first light emission signal line EM1, the second light emission signal line EM2, the first second scan signal line Gate2, and the second reference signal line REF2 on the substrate, connected to the pixel driving circuit of at least one sub-pixel, are arranged sequentially along the second direction D2.

[0250] In an exemplary embodiment, the orthographic projection of the first initial signal line INIT1 on the substrate is located between the orthographic projection of the first scan signal line Gate1 on the substrate and the orthographic projection of the fourth scan signal line Gate4 on the substrate, and at least partially overlaps with the orthographic projection of the first second scan signal line Gate2 on the substrate.

[0251] In an exemplary embodiment, the orthographic projection of the second initial signal line INIT2 on the substrate is located between the orthographic projection of the second light-emitting signal line EM2 on the substrate and the orthographic projection of the second reference signal line REF2 on the substrate, and at least partially overlaps with the orthographic projection of the second second scan signal line Gate2 on the substrate.

[0252] In an exemplary embodiment, as shown in Figures 10 and 11, the pixel driving circuit for at least one sub-pixel includes: a first capacitor C1 and a second capacitor C2; for the pixel driving circuit for at least one sub-pixel, the orthographic projection of the first capacitor C1 on the substrate is located between the orthographic projection of at least one of the first second scan signal line Gate2 and the first initial signal line INIT1 connected to the pixel driving circuit on the substrate and the orthographic projection of the fourth scan signal line Gate4 on the substrate.

[0253] In an exemplary embodiment, as shown in Figures 10 and 11, the orthographic projection of the second capacitor C2 on the substrate is located between the orthographic projection of the first light-emitting signal line EM1 connected to the pixel driving circuit on the substrate and the orthographic projection of the second light-emitting signal line EM2 on the substrate.

[0254] In an exemplary embodiment, as shown in FIG10, the display device may further include: a plurality of first power lines VDD, one of which of the plurality of first power lines VDD extends along a second direction D2.

[0255] In an exemplary embodiment, for at least one row of sub-pixels, the first power line connected to the pixel driving circuit of at least one sub-pixel and the first power line connected to the pixel driving circuit of the first adjacent sub-pixel are symmetrically arranged in a straight line extending along a second direction, and the first power line connected to the pixel driving circuit of at least one sub-pixel and the first power line connected to the pixel driving circuit of the second adjacent sub-pixel have the same structure.

[0256] In an exemplary embodiment, as shown in FIG10, at least one data signal line Data includes: a plurality of first data connection portions DA and a plurality of second data connection portions DB, the plurality of first data connection portions DA and the plurality of second data connection portions DB are alternately arranged, and at least one connection portion of the first data connection portion DA and the second data connection portion DB extends along the second direction D2.

[0257] In an exemplary embodiment, as shown in FIG10, for the data signal line Data connected to the pixel driving circuit of at least one sub-pixel, the orthographic projection of the first data connection portion DA on the substrate at least partially overlaps with the orthographic projection of at least one signal line among the first reference signal line REF1, the third scan signal line Gate3, the first scan signal line Gate1, the first second scan signal line Gate2, the first initial signal line INIT1, the fourth scan signal line Gate4, the first light emission signal line EM1, the power connection line, and at least one capacitor among the first capacitor C1 and the second capacitor C2 in the pixel driving circuit of at least one sub-pixel.

[0258] In an exemplary embodiment, as shown in FIG10, the orthographic projection of the second data connection portion DB on the substrate at least partially overlaps with the orthographic projection of at least one of the following signal lines on the substrate: the second light-emitting signal line EM2, the second scan signal line, the second initial signal line INIT2, and the second reference signal line REF2.

[0259] In an exemplary embodiment, as shown in FIG10, the length of the first data connection portion DA along the first direction D1 is greater than the length of the second data connection portion DB along the first direction D1.

[0260] In an exemplary embodiment, the display device further includes: a circuit structure layer disposed on a substrate, the circuit structure layer including: a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer sequentially stacked on the substrate.

[0261] In an exemplary embodiment, the pixel driving circuit for at least one sub-pixel includes: at least one P-type transistor, at least one N-type transistor, and at least one capacitor, wherein the at least one capacitor includes: a first plate and a second plate. Exemplarily, the at least one P-type transistor includes: first transistor T1 to seventh transistor T7, ninth transistor T9, and tenth transistor T10; the at least one N-type transistor includes: eighth transistor T8; and the at least one capacitor includes: a first capacitor and a second capacitor.

[0262] In an exemplary embodiment, the first semiconductor layer includes an active pattern of at least one P-type transistor located in a pixel driving circuit of at least one sub-pixel.

[0263] In an exemplary embodiment, the first conductive layer includes at least: a second scan signal line Gate2, a first light emission signal line EM1, and a first electrode plate of at least one capacitor and a control electrode of at least one P-type transistor located in the pixel driving circuit of at least one sub-pixel.

[0264] In an exemplary embodiment, the second conductive layer includes at least: a second plate of at least one capacitor located in the pixel driving circuit of at least one sub-pixel and a first control electrode of at least one N-type transistor.

[0265] In an exemplary embodiment, the second semiconductor layer includes at least an active pattern of at least one N-type transistor located in a pixel driving circuit of at least one sub-pixel.

[0266] In an exemplary embodiment, the third conductive layer includes at least: a first initial signal line INIT1, a second reference signal line REF2, and a second control electrode of an eighth transistor located in a pixel driving circuit of at least one sub-pixel.

[0267] In an exemplary embodiment, the fourth conductive layer includes at least: a first reference signal line REF1, a first scan signal line Gate1, a third scan signal line Gate3, a fourth scan signal line Gate4, a second light emission signal line EM2, a second initial signal line INIT2, and a first and second pole of at least one transistor of a pixel driving circuit located at at least one sub-pixel.

[0268] In an exemplary embodiment, the fifth conductive layer pattern may include at least: a data signal line Data and a first power line VDD.

[0269] In an exemplary embodiment, FIG12 is a second schematic diagram of a portion of the film layer in FIG10. As shown in FIG12, the circuit structure layer further includes: a light-shielding layer located on the side of the first semiconductor layer near the substrate, the light-shielding layer including: a light-shielding structure located in at least one sub-pixel. For clarity, at least one capacitor in the last sub-pixel is not shown in FIG12.

[0270] For at least one row of sub-pixels, as shown in Figure 12, the light-shielding structure of at least one sub-pixel is symmetrically arranged with the light-shielding structure of the first adjacent sub-pixel along a straight line extending in the second direction, and the light-shielding structure of at least one sub-pixel is at least partially the same as the light-shielding structure of the second adjacent sub-pixel.

[0271] As shown in Figure 12, the light-shielding structure located at at least one sub-pixel includes: a first light-shielding part SL1, a second light-shielding part SL2, a first light-shielding connecting part SL3, a second light-shielding connecting part SL4, and a third light-shielding connecting part SL5. The first light-shielding connecting part SL3, the first light-shielding part SL1, the second light-shielding connecting part SL4, the second light-shielding part SL2, and the third light-shielding connecting part SL5 are arranged sequentially along the second direction D2. The first light-shielding part SL1 is connected to the first light-shielding connecting part SL3 and the second light-shielding connecting part SL4, and the second light-shielding part SL2 is connected to the second light-shielding connecting part SL4 and the third light-shielding connecting part SL5, respectively.

[0272] As shown in Figure 12, at least one of the first light-shielding connecting part SL3, the second light-shielding connecting part SL4 and the third light-shielding connecting part SL5 extends along the second direction D2.

[0273] As shown in Figure 12, the length of at least one of the first light-shielding part SL1 and the second light-shielding part SL2 along the first direction D1 is greater than the length of at least one of the light-shielding connecting parts from the first light-shielding connecting part to the third light-shielding connecting part SL5 along the first direction D1.

[0274] In an exemplary embodiment, as shown in FIG12, the second light-shielding portions in the light-shielding structures of adjacent sub-pixels located in the same row are connected to each other.

[0275] In an exemplary embodiment, as shown in FIG12, the pixel driving circuit of at least one sub-pixel includes: a first capacitor C1 and a second capacitor C2, wherein the first capacitor C1 and the second capacitor C2 include a first electrode plate and a second electrode plate.

[0276] In an exemplary embodiment, as shown in FIG12, the orthographic projection of the first light-shielding portion SL1 of the light-shielding structure located at at least one sub-pixel on the substrate at least partially overlaps with the orthographic projection of at least one of the first plates C11 and the second plates C12 of the first capacitor C1 on the substrate.

[0277] In an exemplary embodiment, as shown in FIG12, the orthographic projection of the second light-shielding portion SL2 of the light-shielding structure located at least one sub-pixel onto the substrate at least partially overlaps with the orthographic projection of at least one of the first electrode plates C21 and the second electrode plate C22 of the second capacitor C2 onto the substrate.

[0278] In an exemplary embodiment, as shown in FIG10, the display device further includes: a plurality of power connection lines VDL located in the fourth conductive layer, wherein one of the plurality of power connection lines VDL extends along the first direction D1.

[0279] In an exemplary embodiment, as shown in FIG10, at least one power connection line VDL is electrically connected to at least one of the plurality of first power lines VDD.

[0280] In an exemplary embodiment, as shown in FIG10, the orthographic projection of at least one power connection line on the substrate is located between the orthographic projection of at least one first light-emitting signal line EM1 on the substrate and the orthographic projection of at least one second light-emitting signal line EM2 on the substrate, and at least partially overlaps with the orthographic projection of the second capacitor C2 in the pixel driving circuit of at least one sub-pixel on the substrate.

[0281] In an exemplary embodiment, multiple first power lines VDD and multiple power connection lines VDL form an interconnected mesh structure, which can ensure that the signals of the first power lines in the multiple pixel driving circuits in the display substrate are consistent, and can ensure the display uniformity of the display substrate.

[0282] In an exemplary embodiment, as shown in FIG10, the display device further includes: a plurality of reference connection lines REFCL located in the fifth conductive layer, one of the plurality of reference connection lines REFCL extending along the second direction D2.

[0283] In an exemplary embodiment, as shown in FIG10, at least one reference connection line REFCL is electrically connected to at least one of the plurality of first reference signal lines REF1.

[0284] In an exemplary embodiment, multiple first reference signal lines REF1 and multiple reference connection lines REFCL form an interconnected mesh structure, which can ensure that the signals of the first reference signal lines in multiple pixel driving circuits in the display substrate are consistent, and can ensure the display uniformity of the display substrate.

[0285] In an exemplary embodiment, as shown in FIG10, at least one reference connection line is located between the first power line VDD connected to the pixel driving circuit of at least one sub-pixel and the first power line VDD connected to the pixel driving circuit of the first adjacent sub-pixel, and the center line of the at least one reference connection line extending along the first direction D1 is on the same straight line as the axis of symmetry of the pixel driving circuit of at least one sub-pixel and the pixel driving circuit of the first adjacent sub-pixel.

[0286] In an exemplary embodiment, as shown in FIG10, at least one reference connection line is located between the data signal line Data connected to the pixel driving circuit of at least one sub-pixel and the first power supply line VDD connected to the pixel driving circuit of the first adjacent sub-pixel.

[0287] In an exemplary embodiment, the display substrate can be a low-temperature polycrystalline oxide (LTPO) display substrate.

[0288] The structure of a display substrate is illustrated below using an example of the fabrication process of the display substrate. The "patterning process" described in this disclosure includes depositing a film layer, coating photoresist, mask exposure, development, etching, and photoresist stripping. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying and spin coating; and etching can be performed using any one or more of dry etching and wet etching. A "thin film" refers to a thin film of a certain material fabricated on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are set in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process.

[0289] Figures 13 to 29 are schematic diagrams illustrating the fabrication process of a display substrate provided in an exemplary embodiment. Figures 13 to 29 are illustrated using a three-row pixel driving circuit as an example.

[0290] The fabrication process of the display substrate provided in this disclosure may include, as shown in Figures 13 to 29:

[0291] (1) Forming a light-shielding layer pattern. In an exemplary embodiment, forming a light-shielding layer pattern includes: depositing a light-shielding film on a substrate, and patterning the light-shielding film through a patterning process to form a light-shielding layer pattern, as shown in FIG13. FIG13 is a schematic diagram of FIG10 after the light-shielding layer pattern is formed.

[0292] In an exemplary embodiment, as shown in FIG13, the light-shielding layer pattern may include a light-shielding structure located at at least one sub-pixel.

[0293] In an exemplary embodiment, for sub-pixels in the same row, the light-shielding structure of at least one sub-pixel is at least partially symmetrical with respect to the light-shielding structure of the first adjacent sub-pixel with respect to a straight line extending along the second direction D2, and the light-shielding structure of at least one sub-pixel in the same row is at least partially the same as the light-shielding structure of the second adjacent sub-pixel.

[0294] In an exemplary embodiment, the light-shielding structure located at at least one sub-pixel includes: a first light-shielding portion SL1, a second light-shielding portion SL2, a first light-shielding connecting portion SL3, a second light-shielding connecting portion SL4, and a third light-shielding connecting portion SL5. The first light-shielding connecting portion SL3, the first light-shielding portion SL1, the second light-shielding connecting portion SL4, the second light-shielding portion SL2, and the third light-shielding connecting portion SL5 are arranged sequentially along a second direction D2. The first light-shielding portion SL1 is connected to both the first light-shielding connecting portion SL3 and the second light-shielding connecting portion SL4, and the second light-shielding portion SL2 is connected to both the second light-shielding connecting portion SL4 and the third light-shielding connecting portion SL5.

[0295] In an exemplary embodiment, the first light-shielding portion SL1 and the second light-shielding portion SL2 are rectangular in shape. At least one of the first light-shielding connecting portion SL3, the second light-shielding connecting portion SL4, and the third light-shielding connecting portion SL5 extends along the second direction D2.

[0296] In an exemplary embodiment, the second light-shielding portion SL2 in the light-shielding structure located in adjacent sub-pixels in the same row is connected.

[0297] In an exemplary embodiment, for the same column of sub-pixels, the first light-shielding connection portion SL3 in the light-shielding structure of at least one row of sub-pixels is connected to the third light-shielding connection portion SL5 in the light-shielding structure of the previous row of sub-pixels, and the third light-shielding connection portion SL5 in the light-shielding structure of at least one row of sub-pixels is connected to the first light-shielding connection portion SL3 in the light-shielding structure of the next row of sub-pixels.

[0298] In an exemplary embodiment, at least one of the first light-shielding portion SL1 and the second light-shielding portion SL2 has a length along the first direction D1 that is greater than the length along the first direction D1 of at least one of the first light-shielding connecting portions SL3 to the third light-shielding connecting portion SL5.

[0299] (2) Forming a first semiconductor layer pattern. In an exemplary embodiment, forming a first semiconductor layer pattern may include: sequentially depositing a first insulating film and a first semiconductor film on a substrate, and patterning the first semiconductor film by a patterning process to form a first insulating layer covering the substrate and a first semiconductor layer pattern disposed on the first insulating layer, as shown in Figures 14 and 15. Figure 14 is a schematic diagram of the first semiconductor layer pattern in Figure 10, and Figure 15 is a schematic diagram of the first semiconductor layer pattern after it has been formed in Figure 10.

[0300] In an exemplary embodiment, as shown in Figures 14 and 15, the first semiconductor layer pattern may include at least: an active pattern 11 of a first transistor, an active pattern 21 of a second transistor, an active pattern 31 of a third transistor, an active pattern 41 of a fourth transistor, an active pattern 51 of a fifth transistor, an active pattern 61 of a sixth transistor, an active pattern 71 of a seventh transistor, an active pattern 91 of a ninth transistor, and an active pattern 101 of a tenth transistor located in at least one sub-pixel.

[0301] In an exemplary embodiment, for the same row of sub-pixels, the active pattern of at least one transistor of at least one sub-pixel is at least partially symmetrical with respect to the active pattern of at least one transistor of a first adjacent sub-pixel with respect to a straight line extending along the second direction D2, and the active pattern of at least one transistor of at least one sub-pixel is at least partially the same as the active pattern of at least one transistor of a second adjacent sub-pixel.

[0302] In an exemplary embodiment, the orthographic projection of the light-shielding structure of at least one sub-pixel onto the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor in the pixel driving circuit of at least one sub-pixel onto the substrate. Exemplarily, the orthographic projection of the second light-shielding portion of the light-shielding structure of at least one sub-pixel onto the substrate at least partially overlaps with the orthographic projection of the active pattern of the third transistor in the pixel driving circuit of at least one sub-pixel onto the substrate.

[0303] In an exemplary embodiment, for the same sub-pixel, the active patterns 21 of the second transistor, 31 of the third transistor, 51 of the fifth transistor, 61 of the sixth transistor, 91 of the ninth transistor, and 101 of the tenth transistor are an integral structure. The active patterns 41 of the fourth transistor and 71 of the seventh transistor are an integral structure. The active pattern 11 of the first transistor is set separately.

[0304] In an exemplary embodiment, for a pixel driving circuit of at least one row of sub-pixels, the integrated structure of the active pattern 21 of the second transistor, the active pattern 31 of the third transistor, the active pattern 51 of the fifth transistor, the active pattern 61 of the sixth transistor, the active pattern 91 of the ninth transistor, and the active pattern 101 of the tenth transistor is arranged along the second direction D2 with the integrated structure of the active pattern 41 of the fourth transistor and the active pattern 71 of the seventh transistor. The integrated structure of the active pattern 41 of the fourth transistor and the active pattern 71 of the seventh transistor is located on the side of the integrated structure of the active pattern 21 of the second transistor, the active pattern 31 of the third transistor, the active pattern 51 of the fifth transistor, the active pattern 61 of the sixth transistor, the active pattern 91 of the ninth transistor, and the active pattern 101 of the tenth transistor closer to the previous row of sub-pixels. The active pattern 11 of the first transistor is located between the integrated structure of the active pattern 41 of the fourth transistor and the active pattern 71 of the seventh transistor and the integrated structure of the active pattern 21 of the second transistor, the active pattern 31 of the third transistor, the active pattern 51 of the fifth transistor, the active pattern 61 of the sixth transistor, the active pattern 91 of the ninth transistor and the active pattern 101 of the tenth transistor.

[0305] In an exemplary embodiment, in the first direction D1, the active pattern 51 of the fifth transistor and the active pattern 91 of the ninth transistor may be located on the same side of the active pattern 31 of the third transistor, and the active patterns 21 of the second transistor, 61 of the sixth transistor, and 101 of the tenth transistor may be located on the same side of the active pattern 31 of the third transistor, while the active patterns 51 of the fifth transistor and 61 of the sixth transistor may be located on different sides of the active pattern 31 of the third transistor. In the second direction D2, the active patterns 11 of the first transistor, 21 of the second transistor, 41 of the fourth transistor, 51 of the fifth transistor, and 71 of the seventh transistor are located on the side of the active pattern 31 of the third transistor in the pixel driving circuit of this sub-pixel that is close to the pixel driving circuit of the previous row of sub-pixels, and the active patterns 61 of the sixth transistor, 91 of the ninth transistor, and 101 of the tenth transistor may be located on the side of the pixel driving circuit of at least one row of sub-pixels that is close to the pixel driving circuit of the next row of sub-pixels. At least one row of active pattern 71 of the seventh transistor is located on the side of active pattern 41 of the fourth transistor near the next row of sub-pixels.

[0306] In an exemplary embodiment, for the same sub-pixel, the active pattern 51 of the fifth transistor and the active pattern 91 of the ninth transistor are arranged along the second direction D2, and the active pattern 21 of the second transistor, the active pattern 61 of the sixth transistor and the active pattern 101 of the tenth transistor are arranged sequentially along the second direction D2.

[0307] In an exemplary embodiment, the shape of the active pattern 31 of the third transistor may be an inverted "Ω" shape.

[0308] In an exemplary embodiment, the active pattern 11 of the first transistor is in a "one" shape.

[0309] In an exemplary embodiment, the active patterns 21 of the second transistor, 41 of the fourth transistor, 51 of the fifth transistor, 61 of the sixth transistor, 91 of the ninth transistor, and 101 of the tenth transistor are in an "I" shape.

[0310] In an exemplary embodiment, the active pattern 71 of the seventh transistor may be in a polyline shape and at least partially extend along the second direction D2.

[0311] In an exemplary embodiment, the active pattern of each transistor may include a first region, a second region, and a channel region located between the first region and the second region. In an exemplary embodiment, for the pixel driving circuit of at least one sub-pixel, the first region 31-1 of the active pattern 31 of the third transistor may simultaneously serve as the second region 51-2 of the active pattern 51 of the fifth transistor and the second region 91-2 of the active pattern 91 of the ninth transistor. The second region 31-2 of the active pattern 31 of the third transistor may serve as the second region 21-2 of the active pattern of the second transistor and the first region 61-1 of the active pattern 61 of the sixth transistor. The second region 41-2 of the active pattern 41 of the fourth transistor may serve as the second region 71-2 of the active pattern 71 of the seventh transistor. The second region 61-2 of the active pattern 61 of the sixth transistor may serve as the second region 101-2 of the active pattern 101 of the tenth transistor. The first region 11-1 and the second region 11-2 of the active pattern 11 of the first transistor, the first region 41-1 of the active pattern 41 of the fourth transistor, the first region 51-1 of the active pattern 51 of the fifth transistor, the first region 71-1 of the active pattern 71 of the seventh transistor, the first region 91-1 of the active pattern 91 of the ninth transistor, and the first region of the active pattern 101 of the tenth transistor may be separately provided.

[0312] In an exemplary embodiment, the first region 101-1 of the active pattern 101 of the tenth transistor in the pixel driving circuit of at least one sub-pixel and the pixel driving circuit of the first adjacent sub-circuit may be the same region.

[0313] (3) Forming a first conductive layer pattern. In an exemplary embodiment, forming a first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on a substrate on which the aforementioned pattern is formed; patterning the second insulating film and the first conductive film using a patterning process to form a second insulating layer pattern and a first conductive layer pattern located on the second insulating layer, as shown in Figures 16 and 17. Figure 16 is a schematic diagram of the first conductive layer pattern in Figure 10, and Figure 17 is a schematic diagram of Figure 10 after the first conductive layer pattern has been formed. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0314] In an exemplary embodiment, as shown in Figures 16 and 17, the first conductive layer pattern may include: a second scan signal line Gate2, a first light-emitting signal line EM1, and a first electrode C11 of a first capacitor, a second electrode C21 of a second capacitor, a control electrode 11 of a first transistor, a control electrode 22 of a second transistor, a control electrode 32 of a third transistor, a control electrode 42 of a fourth transistor, a control electrode 52 of a fifth transistor, a control electrode 62 of a sixth transistor, a control electrode 72 of a seventh transistor, a control electrode 92 of a ninth transistor, and a control electrode 102 of a tenth transistor.

[0315] In an exemplary embodiment, for sub-pixels in the same row, the first plate C11 of the first capacitor, the second plate C21 of the second capacitor, the control electrode 11 of the first transistor, the control electrode 22 of the second transistor, the control electrode 32 of the third transistor, the control electrode 42 of the fourth transistor, the control electrode 52 of the fifth transistor, the control electrode 62 of the sixth transistor, the control electrode 72 of the seventh transistor, the control electrode 92 of the ninth transistor, and the control electrode 102 of the tenth transistor in the pixel driving circuit of at least one sub-pixel are relative to the first plate C11 of the first capacitor, the second plate C21 of the second capacitor, the control electrode 11 of the first transistor, the control electrode 22 of the second transistor, the control electrode 32 of the third transistor, the control electrode 42 of the fourth transistor, the control electrode 52 of the fifth transistor, the control electrode 62 of the sixth transistor, the control electrode 72 of the seventh transistor, the control electrode 92 of the ninth transistor, and the control electrode 102 of the tenth transistor in the pixel driving circuit of the first adjacent sub-pixel relative to the first plate C11 of the first capacitor, the second plate C21 of the second capacitor, the control electrode 11 of the first transistor, the control electrode 22 of the second transistor, the control electrode 32 of the third transistor, the control electrode 42 of the fourth transistor, the control electrode 52 of the fifth transistor, the control electrode 62 of the sixth transistor, the control electrode 72 of the seventh transistor, the control electrode 92 of the ninth transistor, and the control electrode 102 of the tenth transistor along the second direction. The straight line extending from D2 is at least partially symmetrically arranged, and the first plate C11 of the first capacitor, the second plate C21 of the second capacitor, the control electrode 11 of the first transistor, the control electrode 22 of the second transistor, the control electrode 32 of the third transistor, the control electrode 42 of the fourth transistor, the control electrode 52 of the fifth transistor, the control electrode 62 of the sixth transistor, the control electrode 72 of the seventh transistor, the control electrode 92 of the ninth transistor, and the control electrode 102 of the tenth transistor in the pixel driving circuit of the adjacent sub-pixel of the human body have at least partially identical structures to the first plate C11 of the first capacitor, the second plate C21 of the second capacitor, the control electrode 11 of the first transistor, the control electrode 22 of the second transistor, the control electrode 32 of the third transistor, the control electrode 42 of the fourth transistor, the control electrode 52 of the fifth transistor, the control electrode 62 of the sixth transistor, the control electrode 72 of the seventh transistor, the control electrode 92 of the ninth transistor, and the control electrode 102 of the tenth transistor in the pixel driving circuit of the adjacent sub-pixel of the human body.

[0316] In an exemplary embodiment, the second scan signal line Gate2 connected to the pixel driving circuit of at least one row of sub-pixels includes two lines.

[0317] For at least one row of sub-pixels, the first second scan signal line Gate2, the first light emission signal line EM1, and the second second scan signal line Gate2 connected to the pixel driving circuit are arranged sequentially along the second direction D2, and the first second scan signal line Gate2 is located on the side of the first light emission signal line EM1 closer to the previous row of sub-pixels, and the second second scan signal line Gate2 is located on the side of the first light emission signal line EM1 closer to the next row of sub-pixels.

[0318] In an exemplary embodiment, the shape of the first second scan signal line Gate2 can be a line shape in which the main body extends along the first direction D1. The area where the first second scan signal line Gate2, to which the pixel driving circuit of at least one row of sub-pixels is connected, overlaps with the active pattern of the first transistor can be the control electrode 12 of the first transistor.

[0319] In an exemplary embodiment, the shape of the second second scan signal line Gate2 can be a line shape in which the main body extends along the first direction D1. The area where the second second scan signal line Gate2, to which the pixel driving circuit of at least one row of sub-pixels is connected, overlaps with the active pattern of the ninth transistor can be the control electrode 92 of the ninth transistor, and the area where the second second scan signal line Gate2, to which the pixel driving circuit of at least one row of sub-pixels is connected, overlaps with the active pattern of the tenth transistor can be the control electrode 102 of the tenth transistor.

[0320] In an exemplary embodiment, the shape of the first light-emitting signal line EM1 can be a line shape in which the main body extends along the first direction D1. The area where the first light-emitting signal line EM1 connected to the pixel driving circuit of at least one row of sub-pixels overlaps with the active pattern of the second transistor serves as the control electrode 22 of the second transistor, and the area where the first light-emitting signal line EM1 connected to the pixel driving circuit of at least one row overlaps with the active pattern of the fifth transistor serves as the control electrode 52 of the fifth transistor.

[0321] In an exemplary embodiment, for at least one sub-pixel, the first electrode C11 of the first capacitor in the pixel driving circuit is located between the first second scan signal line Gate2 and the first light-emitting signal line EM1 connected to the pixel driving circuit. The first electrode C11 of the first capacitor can be rectangular in shape, and the corners of the rectangle can be chamfered. The orthographic projection of the first electrode C11 of the first capacitor on the substrate at least partially overlaps with the orthographic projection of the first light-shielding part of the light-shielding structure on the substrate. Exemplarily, the orthographic projection of the first electrode C11 of the first capacitor on the substrate is within the range of the orthographic projection of the first light-shielding part of the light-shielding structure on the substrate.

[0322] In an exemplary embodiment, for at least one sub-pixel, the first electrode C21 of the second capacitor in the pixel driving circuit is located between the second second scan signal line Gate2 and the first light-emitting signal line EM1 connected to the pixel driving circuit. The first electrode C21 of the second capacitor can be rectangular in shape, and the corners of the rectangle can be chamfered. The orthographic projection of the first electrode C21 of the second capacitor on the substrate at least partially overlaps with the orthographic projection of the second light-shielding part of the light-shielding structure on the substrate. Exemplarily, the orthographic projection of the first electrode C21 of the second capacitor on the substrate is within the range of the orthographic projection of the second light-shielding part of the light-shielding structure on the substrate.

[0323] In an exemplary embodiment, in at least one sub-pixel, the first plate C21 of the second capacitor of the pixel driving circuit can serve as the control electrode 32 of the third transistor.

[0324] In an exemplary embodiment, in at least one sub-pixel, the control electrode 42 of the fourth transistor is separately provided and is shaped like a horizontally flipped "7".

[0325] In an exemplary embodiment, the control electrode 62 of the sixth transistor is separately disposed in at least one sub-pixel. The control electrode 62 of the sixth transistor is strip-shaped and extends along the first direction D1.

[0326] In an exemplary embodiment, the control electrode of the sixth transistor of the pixel driving circuit of at least one sub-pixel and the pixel driving circuit of the first adjacent sub-pixel is the same electrode.

[0327] In an exemplary embodiment, the control electrode 72 of the seventh transistor is separately disposed in at least one sub-pixel. The control electrode 72 of the seventh transistor is strip-shaped and extends along the first direction D1.

[0328] In an exemplary embodiment, the control electrode of the seventh transistor of the pixel driving circuit of at least one sub-pixel and the pixel driving circuit of the first adjacent sub-pixel is the same electrode.

[0329] In an exemplary embodiment, the second scanning signal line Gate2 and the first light-emitting signal line EM1 can be designed with equal width or non-equal width, and can be straight lines or broken lines. This not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between the signal lines. This disclosure does not limit the scope of the invention.

[0330] In an exemplary embodiment, after forming the first conductive layer pattern, the first conductive layer can be used as a shield to conduct the first semiconductor layer. The first semiconductor layer in the area shielded by the first conductive layer forms the channel regions of the first to seventh transistors and the ninth transistor. The first semiconductor layer in the area not shielded by the first conductive layer is conducted, that is, the first region and the second region of at least one of the first to seventh transistors, the ninth transistor, and the tenth transistor are both conducted. After conducting, the first region of the active pattern of the third transistor (which is also the second region of the active pattern of the fifth transistor and the second region of the ninth transistor) is multiplexed as the first electrode 33 of the third transistor (which is also the second electrode 54 of the fifth transistor and the second electrode 94 of the ninth transistor), and the second region of the active pattern of the third transistor (which is also the second region of the active pattern of the second transistor and the first region of the active pattern of the sixth transistor) is multiplexed as the second electrode 34 of the third transistor (which is also the second electrode 24 of the second transistor and the first electrode 63 of the sixth transistor).

[0331] In an exemplary embodiment, the control electrode of the first transistor is disposed across the active pattern of the first transistor, the control electrode of the second transistor is disposed across the active pattern of the second transistor, the control electrode of the third transistor is disposed across the active pattern of the third transistor, the control electrode of the fourth transistor is disposed across the active pattern of the fourth transistor, the control electrode of the fifth transistor is disposed across the active pattern of the fifth transistor, the control electrode of the sixth transistor is disposed across the active pattern of the sixth transistor, the control electrode of the seventh transistor is disposed across the active pattern of the seventh transistor, the control electrode of the ninth transistor is disposed across the active pattern of the ninth transistor, and the control electrode of the tenth transistor is disposed across the active pattern of the tenth transistor. That is, the extension direction of the control electrode of at least one transistor is perpendicular to the extension direction of the active pattern.

[0332] (4) Forming a second conductive layer pattern. In an exemplary embodiment, forming a second conductive layer pattern may include: sequentially depositing a third insulating film and a second conductive film on a substrate on which the aforementioned pattern is formed; patterning the third insulating film and the second conductive film using a patterning process to form a third insulating layer pattern and a second conductive layer pattern located on the third insulating layer, as shown in Figures 18 and 19. Figure 18 is a schematic diagram of the second conductive layer pattern in Figure 10, and Figure 19 is a schematic diagram of the second conductive layer pattern after it has been formed in Figure 10. In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0333] In an exemplary embodiment, as shown in Figures 18 and 19, the second conductive layer pattern may include: the second electrode C12 of the first capacitor, the second electrode C22 of the second capacitor, and the first control electrode 82A of the eighth transistor located in the pixel driving circuit of at least one sub-pixel.

[0334] In an exemplary embodiment, for sub-pixels in the same row, the second plate C12 of the first capacitor, the second plate C22 of the second capacitor, and the first control electrode 82A of the eighth transistor in the pixel driving circuit of at least one sub-pixel are at least partially symmetrically arranged with respect to a straight line extending along the second direction D2. The structures of the second plate C12 of the first capacitor, the second plate C22 of the second capacitor, and the first control electrode 82A of the eighth transistor in the pixel driving circuit of at least one sub-pixel are at least partially identical to those of the second plate C12 of the first capacitor, the second plate C22 of the second capacitor, and the first control electrode 82A of the eighth transistor in the pixel driving circuit of the second adjacent sub-pixel.

[0335] In an exemplary embodiment, the main outline of the second electrode plate C12 of the first capacitor can be rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the second electrode plate C12 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate of the first capacitor on the substrate. The second electrode plate C12 of the first capacitor is provided with a first opening H1, which can be rectangular in shape and located in the middle of the second electrode plate C12, so that the second electrode plate C12 of the first capacitor forms a ring structure. The first opening H1 exposes the third insulating layer covering the first electrode plate of the first capacitor, and the orthographic projection of the first electrode plate of the first capacitor on the substrate covers the orthographic projection of the first opening H1 on the substrate. In an exemplary embodiment, the first opening H1 exposes the first electrode plate of the first capacitor, so that the second electrode of the subsequently formed first transistor (which is also the first electrode of the second transistor and the first electrode of the eighth transistor) is connected to the first electrode plate of the first capacitor.

[0336] In an exemplary embodiment, the second plate C22 of the second capacitor includes a capacitor body portion C22A and a capacitor connection portion C22B. The capacitor body portion C22A and the capacitor connection portion C22B are arranged along a first direction D1 and are connected to each other.

[0337] In an exemplary embodiment, the main body outline of the capacitor body C22 of the second electrode C22 of the second capacitor can be rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the capacitor body C22 of the second electrode C22 on the substrate at least partially overlaps with the orthographic projection of the first electrode C22 of the second capacitor on the substrate. The capacitor body C22A of the second electrode C22 of the second capacitor is provided with a second opening H2. The shape of the second opening H2 can be rectangular and can be located in the middle of the second electrode C22 of the second capacitor, so that the second electrode C22 of the second capacitor forms a ring structure. The second opening H2 exposes the third insulating layer covering the first electrode of the second capacitor, and the orthographic projection of the first electrode of the second capacitor on the substrate includes the orthographic projection of the second opening H2 on the substrate. In an exemplary embodiment, the second opening H2 exposes the first electrode of the second capacitor, so that the second electrode of the subsequently formed second transistor is connected to the first electrode of the second capacitor (which is also the control electrode of the third transistor).

[0338] In an exemplary embodiment, the second plate C22 of the second capacitor of the pixel driving circuit of adjacent sub-pixels located in the same row is electrically connected.

[0339] In an exemplary embodiment, the capacitor body portion of the second plate of the second capacitor in the pixel driving circuit of at least one sub-pixel is connected to the capacitor body portion of the second plate of the second capacitor in the pixel driving circuit of the first adjacent sub-pixel, and the capacitor connection portion of the second plate of the second capacitor in the pixel driving circuit of at least one sub-pixel is connected to the capacitor connection portion of the second plate of the second capacitor in the pixel driving circuit of the second adjacent sub-pixel.

[0340] In an exemplary embodiment, the first control electrode 82A of the eighth transistor is provided separately. The first control electrode 82A of the eighth transistor is located between the second plate of the first capacitor and the second plate of the second capacitor. The first control electrode 82A of the eighth transistor is strip-shaped and extends along the first direction D1.

[0341] In an exemplary embodiment, for at least one sub-pixel, the orthographic projection of the first control electrode 82A of the eighth transistor in the pixel driving circuit onto the substrate at least partially overlaps with the orthographic projection of the second light-shielding connection portion in the light-shielding structure onto the substrate.

[0342] (5) Forming a second semiconductor layer pattern. In an exemplary embodiment, forming a second semiconductor layer pattern may include: on the substrate on which the aforementioned pattern is formed, including: sequentially depositing a fourth insulating film and a second semiconductor film on the substrate, and patterning the fourth insulating film and the second semiconductor film by a patterning process to form a fourth insulating layer pattern and a second semiconductor layer pattern located on a third insulating layer, as shown in Figures 20 and 21. Figure 20 is a schematic diagram of the second semiconductor layer pattern in Figure 10, and Figure 21 is a schematic diagram of the second semiconductor layer pattern after it is formed in Figure 10.

[0343] In an exemplary embodiment, as shown in Figures 20 and 21, the second semiconductor layer pattern may include an active pattern 81 of an eighth transistor of a pixel driving circuit located at at least one sub-pixel.

[0344] In an exemplary embodiment, for sub-pixels in the same row, the active pattern of the eighth transistor of the pixel driving circuit of at least one sub-pixel is at least partially symmetrical with respect to the active pattern of the eighth transistor of the pixel driving circuit of the first adjacent sub-pixel with respect to a straight line extending along the second direction. The active pattern of the eighth transistor of the pixel driving circuit of at least one sub-pixel has at least partially the same structure as the active pattern of the eighth transistor of the pixel driving circuit of the second adjacent sub-pixel.

[0345] In an exemplary embodiment, as shown in Figures 20 and 21, the active pattern 81 of the eighth transistor is in the shape of an "I".

[0346] In an exemplary embodiment, the active pattern of each transistor may include a first region, a second region, and a channel region located between the first and second regions. In an exemplary embodiment, for a pixel driving circuit of at least one sub-pixel, the first region 81-1 and the second region 81-2 of the active pattern 81 of the eighth transistor are separately configured.

[0347] In an exemplary embodiment, the active pattern 81 of the eighth transistor is disposed across the first control electrode of the eighth transistor.

[0348] (6) Forming a third conductive layer pattern. In an exemplary embodiment, forming a second semiconductor layer pattern may include: sequentially depositing a fifth insulating film and a third conductive film on a substrate on which the aforementioned pattern is formed; patterning the fifth insulating film and the third conductive film using a patterning process to form a fifth insulating layer pattern and a third conductive layer pattern located on the fifth insulating layer, as shown in Figures 22 and 23. Figure 22 is a schematic diagram of the third conductive layer pattern in Figure 10, and Figure 23 is a schematic diagram of Figure 10 after the third conductive layer pattern has been formed. In an exemplary embodiment, the third conductive layer may be referred to as a third gate metal (GATE3) layer.

[0349] In an exemplary embodiment, as shown in Figures 22 and 23, the third conductive layer pattern may include: a first initial signal line INIT1, a second reference signal line REF2, and a second control electrode 82B of an eighth transistor located in a pixel driving circuit of at least one sub-pixel.

[0350] In an exemplary embodiment, for sub-pixels in the same row, the second control electrode of the eighth transistor of the pixel driving circuit of at least one sub-pixel is at least partially symmetrically arranged with respect to the second control electrode of the eighth transistor of the pixel driving circuit of the first adjacent sub-pixel with respect to a straight line extending along the second direction. The structure of the second control electrode of the eighth transistor of the pixel driving circuit of at least one sub-pixel is at least partially the same as that of the second control electrode of the eighth transistor of the pixel driving circuit of the second adjacent sub-pixel.

[0351] In an exemplary embodiment, the shape of the first initial signal line INIT1 can be a line shape in which the main body extends along the first direction D1. The orthographic projection of the first initial signal line INIT1 on the substrate is located on the side where the orthographic projection of the main body of the first second scan signal line on the substrate is away from the orthographic projection of the first light-emitting signal line on the substrate.

[0352] In an exemplary embodiment, the shape of the second reference signal line REF2 can be a line shape in which the main body extends along the first direction D1. The orthographic projection of the second reference signal line REF2 on the substrate is located on the side where the orthographic projection of the main body of the second scan signal line on the substrate is away from the orthographic projection of the first light-emitting signal line on the substrate.

[0353] In an exemplary embodiment, the second control electrode 82B of the eighth transistor is provided separately. The second control electrode 82B of the eighth transistor is strip-shaped and extends along the first direction D1.

[0354] In an exemplary embodiment, the orthographic projection of the second control electrode 82B of the eighth transistor onto the substrate at least partially overlaps with the orthographic projection of the first control electrode of the eighth transistor onto the substrate. Exemplarily, this overlaps within the range of the orthographic projections of the second control electrode 82B and the first control electrode of the eighth transistor onto the substrate.

[0355] In an exemplary embodiment, the first initial signal line and the second reference signal line can be designed with equal width or with non-equal width, and can be straight lines or broken lines. This not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between the signal lines. This disclosure does not limit the scope of the invention.

[0356] (7) Forming a sixth insulating layer pattern includes: depositing a sixth insulating film on a substrate on which the aforementioned pattern has been formed, and patterning the sixth insulating film by a patterning process to form a sixth insulating layer pattern covering the aforementioned pattern. The sixth insulating layer has multiple via patterns, as shown in Figure 24. Figure 24 is a schematic diagram of the formation of the sixth insulating layer pattern in Figure 10.

[0357] In an exemplary embodiment, as shown in FIG24, the plurality of vias in the sixth insulating layer pattern include at least: a first via V1 to a twenty-third via V23 located in the pixel driving circuit of at least one sub-pixel.

[0358] In an exemplary embodiment, for at least one row of sub-pixels, the tenth via V10 of the pixel driving circuit of at least one sub-pixel is the same via as the tenth via V10 of the pixel driving circuit of the first adjacent sub-pixel.

[0359] In an exemplary embodiment, for at least one row of sub-pixels, the thirteenth via V13 of the pixel driving circuit of at least one sub-pixel is the same via as the thirteenth via V13 of the pixel driving circuit of the first adjacent sub-pixel.

[0360] In an exemplary embodiment, the orthographic projection of the first via V1 onto the substrate is within the orthographic projection range of the first region of the active pattern of the first transistor onto the substrate. The fifth, fourth, third, and second insulating layers within the first via V1 are etched away, exposing the surface of the first region of the active layer of the first transistor. The first via V1 is configured to allow the first electrode of the subsequently formed first transistor to be connected to the first region of the active layer of the first transistor through the via.

[0361] In an exemplary embodiment, the orthographic projection of the second via V2 onto the substrate is within the orthographic projection of the second region of the active pattern of the first transistor onto the substrate. The fifth, fourth, third, and second insulating layers within the second via V2 are etched away, exposing the surface of the second region of the active pattern of the first transistor. The second via V2 is configured to allow the second terminal of the subsequently formed first transistor (which is also the first terminal of the second transistor and the first terminal of the eighth transistor) to be connected to the second region of the active pattern of the first transistor through the via.

[0362] In an exemplary embodiment, the orthographic projection of the third via V3 onto the substrate is within the orthographic projection of the first region of the active pattern of the second transistor onto the substrate. The fifth, fourth, third, and second insulating layers within the third via V3 are etched away, exposing the surface of the first region of the active pattern of the second transistor. The third via V3 is configured to allow the second electrode of the subsequently formed first transistor (which is also the first electrode of the second transistor and the first electrode of the eighth transistor) to be connected to the first region of the active pattern of the second transistor through the via.

[0363] In an exemplary embodiment, the orthographic projection of the fourth via V4 onto the substrate is within the orthographic projection of the first region of the active pattern of the fourth transistor onto the substrate. The fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer within the fourth via V4 are etched away, exposing the surface of the first region of the active pattern of the fourth transistor. The fourth via V4 is configured to allow the first electrode of the subsequently formed fourth transistor to be connected to the first region of the active pattern of the fourth transistor through the via.

[0364] In an exemplary embodiment, the orthographic projection of the fifth via V5 onto the substrate lies within the orthographic projection of the second region of the active pattern of the fourth transistor (which is also the second region of the active pattern of the seventh transistor) onto the substrate. The fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer within the fifth via V5 are etched away, exposing the surface of the second region of the active pattern of the fourth transistor (which is also the second region of the active pattern of the seventh transistor). The fifth via V5 is configured to allow the second electrode of the subsequently formed fourth transistor (which is also the second electrode of the seventh transistor) to be connected to the second region of the active pattern of the fourth transistor (which is also the second region of the active pattern of the seventh transistor) through the via.

[0365] In an exemplary embodiment, the orthographic projection of the sixth via V6 onto the substrate is within the orthographic projection of the first region of the active pattern of the fifth transistor onto the substrate. The fifth, fourth, third, and second insulating layers within the sixth via V6 are etched away, exposing the surface of the first region of the active pattern of the fifth transistor. The sixth via V6 is configured to allow the first electrode of the subsequently formed fifth transistor to be connected to the first region of the active pattern of the fifth transistor through the via.

[0366] In an exemplary embodiment, the orthogonal projection of the seventh via V7 onto the substrate lies within the orthogonal projection of the second region of the active pattern of the sixth transistor (which is also the second region of the active pattern of the tenth transistor) onto the substrate. The fifth, fourth, third, and second insulating layers within the seventh via V7 are etched away, exposing the surface of the second region of the active pattern of the sixth transistor (which is also the second region of the active pattern of the tenth transistor). The seventh via V7 is configured to allow the second electrode of the subsequently formed sixth transistor (which is also the second electrode of the tenth transistor) to be connected to the second region of the active pattern of the sixth transistor (which is also the second region of the active pattern of the tenth transistor) through the via.

[0367] In an exemplary embodiment, the orthographic projection of the eighth via V8 onto the substrate is within the orthographic projection of the first region of the active pattern of the seventh transistor onto the substrate. The fifth, fourth, third, and second insulating layers within the eighth via V8 are etched away, exposing the surface of the first region of the active pattern of the seventh transistor. The eighth via V8 is configured to allow the first electrode of the subsequently formed seventh transistor to be connected to the first region of the active pattern of the seventh transistor through the via.

[0368] In an exemplary embodiment, the orthographic projection of the ninth via V9 onto the substrate is within the range of the orthographic projection of the first region of the active pattern of the ninth transistor onto the substrate. The fifth, fourth, third, and second insulating layers within the ninth via V9 are etched away, exposing the surface of the first region of the active pattern of the ninth transistor. The ninth via V9 is configured to allow the first electrode of the subsequently formed ninth transistor to be connected to the first region of the active pattern of the ninth transistor through the via.

[0369] In an exemplary embodiment, the orthographic projection of the tenth via V10 onto the substrate is within the orthographic projection range of the first region of the active pattern of the tenth transistor onto the substrate. The fifth, fourth, third, and second insulating layers within the tenth via V10 are etched away, exposing the surface of the first region of the active pattern of the tenth transistor. The tenth via V10 is configured to allow the first electrode of the subsequently formed tenth transistor to be connected to the first region of the active pattern of the tenth transistor through the via.

[0370] In an exemplary embodiment, the orthogonal projection of the eleventh via V11 onto the substrate is within the range of the orthogonal projection of the control electrode of the fourth transistor onto the substrate. The fifth, fourth, and third insulating layers within the eleventh via V11 are etched away, exposing the surface of the control electrode of the fourth transistor. The eleventh via V11 is configured to allow the subsequently formed first scan signal line to be connected to the control electrode of the fourth transistor through the via.

[0371] In an exemplary embodiment, the orthogonal projection of the twelfth via V12 onto the substrate is within the range of the orthogonal projection of the control electrode of the sixth transistor onto the substrate. The fifth, fourth, and third insulating layers within the twelfth via V12 are etched away, exposing the surface of the control electrode of the sixth transistor. The twelfth via V12 is configured to allow a subsequently formed second light-emitting signal line to be connected to the control electrode of the sixth transistor through the via.

[0372] In an exemplary embodiment, the orthogonal projection of the thirteenth via V13 onto the substrate is within the range of the orthogonal projection of the control electrode of the seventh transistor onto the substrate. The fifth, fourth, and third insulating layers within the thirteenth via V13 are etched away, exposing the surface of the control electrode of the seventh transistor. The thirteenth via V13 is configured to allow the subsequently formed third scan signal line to be connected to the control electrode of the seventh transistor through the via.

[0373] In an exemplary embodiment, the orthographic projection of the fourteenth via V14 on the substrate is located within the orthographic projection of the first electrode plate of the first capacitor on the substrate. The fifth, fourth, and third insulating layers within the fourteenth via V14 are etched away, exposing the surface of the first electrode plate of the first capacitor. The fourteenth via V14 is configured to allow the second electrode of the subsequently formed first transistor (which is also the first electrode of the second transistor and the first electrode of the eighth transistor) to be connected to the first electrode plate of the first capacitor through the via.

[0374] In an exemplary embodiment, the orthographic projection of the fifteenth via V15 onto the substrate is located within the orthographic projection of the first electrode of the second capacitor (which is also the control electrode of the third transistor) onto the substrate. The fifth, fourth, and third insulating layers within the fifteenth via V15 are etched away, exposing the surface of the first electrode of the second capacitor (which is also the control electrode of the third transistor). The fifteenth via V15 is configured to allow the second electrode of the subsequently formed eighth transistor to be connected to the first electrode of the second capacitor (which is also the control electrode of the third transistor) through the via.

[0375] In an exemplary embodiment, the orthogonal projection of the sixteenth via V16 onto the substrate is within the range of the orthogonal projection of the first control electrode of the eighth transistor onto the substrate. The fifth and fourth insulating layers within the sixteenth via V16 are etched away, exposing the surface of the first control electrode of the eighth transistor. The sixteenth via V16 is configured to allow the subsequently formed fourth scan signal line to be connected to the first control electrode of the eighth transistor through the via.

[0376] In an exemplary embodiment, the orthographic projection of the seventeenth via V17 onto the substrate is within the range of the orthographic projection of the second plate of the first capacitor onto the substrate. The fifth and fourth insulating layers within the seventeenth via V17 are etched away, exposing the surface of the second plate of the first capacitor. The seventeenth via V17 is configured to allow the second electrode of the subsequently formed fourth transistor (which is also the second electrode of the seventh transistor) to be connected to the second plate of the first capacitor through the via.

[0377] In an exemplary embodiment, the orthographic projection of the eighteenth via V18 on the substrate is within the range of the orthographic projection of the second plate of the second capacitor on the substrate. The fifth and fourth insulating layers within the eighteenth via V18 are etched away, exposing the surface of the second plate of the second capacitor. The eighteenth via V18 is configured to allow a subsequently formed power connection line to be connected to the second plate of the second capacitor through the via.

[0378] In an exemplary embodiment, the orthographic projection of the nineteenth via V19 onto the substrate is within the orthographic projection of the first region of the active pattern of the eighth transistor onto the substrate. The fifth insulating layer within the nineteenth via V19 is etched away, exposing the surface of the first region of the active pattern of the eighth transistor. The nineteenth via V19 is configured to allow the second terminal of the subsequently formed first transistor (which is also the first terminal of the second transistor and the first terminal of the eighth transistor) to be connected to the first region of the active pattern of the eighth transistor through the via.

[0379] In an exemplary embodiment, the orthographic projection of the twentieth via V20 onto the substrate is within the orthographic projection of the second region of the active pattern of the eighth transistor onto the substrate. The fifth insulating layer within the twentieth via V20 is etched away, exposing the surface of the second region of the active pattern of the eighth transistor. The twentieth via V20 is configured to allow the second electrode of the subsequently formed eighth transistor to be connected to the second region of the active pattern of the eighth transistor through the via.

[0380] In an exemplary embodiment, the orthogonal projection of the 21st via V21 onto the substrate is within the range of the orthogonal projection of the second control electrode of the 8th transistor onto the substrate. The 21st via V21 exposes the surface of the second control electrode of the 8th transistor. The 22nd via V22 is configured to allow the subsequently formed fourth scan signal line to be connected to the second control electrode of the 8th transistor through the via.

[0381] In an exemplary embodiment, the orthographic projection of the 22nd via V22 on the substrate is within the range of the orthographic projection of the first initial signal line on the substrate. The 22nd via V22 exposes the surface of the first initial signal line. The 22nd via V22 is configured to allow the first electrode of the subsequently formed first transistor to be connected to the first initial signal line through the via.

[0382] In an exemplary embodiment, the orthographic projection of the 23rd via V23 onto the substrate is within the range of the orthographic projection of the second reference signal line onto the substrate. The 23rd via V23 exposes the surface of the second reference signal line. The 23rd via V23 is configured to allow the first electrode of the subsequently formed ninth transistor to be connected to the second reference signal line through the via.

[0383] (8) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming a fourth conductive layer pattern may include: depositing a fourth conductive film on a substrate on which the aforementioned pattern is formed, and patterning the fourth conductive film using a patterning process to form a fourth conductive layer pattern, as shown in Figures 25 and 26. Figure 25 is a schematic diagram of the fourth conductive layer pattern in Figure 10, and Figure 26 is a schematic diagram of the fourth conductive layer pattern after it has been formed in Figure 10.

[0384] In an exemplary embodiment, as shown in Figures 25 and 26, the fourth conductive layer pattern may include: a first reference signal line REF1, a first scan signal line Gate1, a third scan signal line Gate3, a fourth scan signal line Gate4, a second light emission signal line EM2, a second initial signal line INIT2, and a power connection line VDL. The first pole 13 and the second pole 14 of the first transistor of the pixel driving circuit of at least one sub-pixel, the first pole 23 of the second transistor, the first pole 43 and the second pole 44 of the fourth transistor, the first pole 53 of the fifth transistor, the second pole 64 of the sixth transistor, the first pole 73 and the second pole 74 of the seventh transistor, the first pole 83 and the second pole 84 of the eighth transistor, the first pole 93 of the ninth transistor, and the first pole 103 and the second pole 104 of the tenth transistor.

[0385] In an exemplary embodiment, for sub-pixels in the same row, the first pole 13 and second pole 14 of the first transistor, the first pole 23 of the second transistor, the first pole 43 and second pole 44 of the fourth transistor, the first pole 53 of the fifth transistor, the second pole 64 of the sixth transistor, the first pole 73 and second pole 74 of the seventh transistor, the first pole 83 and second pole 84 of the eighth transistor, the first pole 93 of the ninth transistor, and the first pole 103 and second pole 104 of the tenth transistor in the pixel driving circuit of at least one sub-pixel are relative to the first pole 13 and second pole 14 of the first transistor, the first pole 23 of the second transistor, the first pole 43 and second pole 44 of the fourth transistor, the first pole 53 of the fifth transistor, the second pole 64 of the sixth transistor, the first pole 73 and second pole 74 of the seventh transistor, the first pole 83 and second pole 84 of the eighth transistor, the first pole 93 of the ninth transistor, and the first pole 103 and second pole 104 of the tenth transistor in the pixel driving circuit of the first adjacent sub-pixel. The straight lines extending toward D2 are at least partially symmetrically arranged, and the first pole 13 and second pole 14 of the first transistor, the first pole 23 of the second transistor, the first pole 43 and second pole 44 of the fourth transistor, the first pole 53 of the fifth transistor, the second pole 64 of the sixth transistor, the first pole 73 and second pole 74 of the seventh transistor, the first pole 83 and second pole 84 of the eighth transistor, the first pole 93 of the ninth transistor, and the first pole 103 and second pole 104 of the tenth transistor in the pixel driving circuit of at least one sub-pixel are at least partially identical in structure to the first pole 13 and second pole 14 of the first transistor, the first pole 23 of the second transistor, the first pole 43 and second pole 44 of the fourth transistor, the first pole 53 of the fifth transistor, the second pole 64 of the sixth transistor, the first pole 73 and second pole 74 of the seventh transistor, the first pole 83 and second pole 84 of the eighth transistor, the first pole 93 of the ninth transistor, and the first pole 103 and second pole 104 of the tenth transistor.

[0386] In an exemplary embodiment, the shape of the first reference signal line REF1 can be a line shape in which the main body extends along the first direction D1. The orthographic projection of the first reference signal line REF1 on the substrate is located on the side of the orthographic projection of the third scan signal line Gate3 on the substrate away from the orthographic projection of the first scan signal line Gate1 on the substrate. The area where the first reference signal line REF1 overlaps with the first region of the active pattern of the seventh transistor can serve as the first electrode 73 of the seventh transistor. The first electrode 73 of the seventh transistor is connected to the first region of the active pattern of the seventh transistor through an eighth via.

[0387] In an exemplary embodiment, the shape of the third scan signal line Gate3 can be a line shape in which the main body extends along the first direction D1. The orthographic projection of the third scan signal line Gate3 on the substrate lies between the orthographic projection of the first reference signal line REF1 on the substrate and the orthographic projection of the first scan signal line Gate1 on the substrate. The third scan signal line Gate3 is connected to the control electrode of the seventh transistor through a thirteenth via.

[0388] In an exemplary embodiment, the shape of the first scan signal line Gate1 can be a line shape in which the main body extends along the first direction D1. The orthographic projection of the first scan signal line Gate1 on the substrate lies between the orthographic projection of the third scan signal line Gate3 on the substrate and the orthographic projection of the first initial signal line INIT1 on the substrate. The first scan signal line Gate1 is connected to the control electrode of the fourth transistor through an eleventh via.

[0389] In an exemplary embodiment, the shape of the fourth scan signal line Gate4 can be a line shape in which the main body extends along the first direction D1. The orthographic projection of the fourth scan signal line Gate4 on the substrate is located between the orthographic projection of the first initial signal line on the substrate and the orthographic projection of the first light-emitting signal line on the substrate. The fourth scan signal line Gate4 is connected to the first control electrode of the eighth transistor through the sixteenth via and to the second control electrode of the eighth transistor through the twenty-first via.

[0390] In an exemplary embodiment, the power connection line VDL can be a line shape in which the main body extends along the first direction D1. The orthographic projection of the power connection line VDL on the substrate lies between the orthographic projections of the first light-emitting signal line and the second light-emitting signal line on the substrate, and at least partially overlaps with the orthographic projection of the second capacitor in the pixel driving circuit of at least one sub-pixel on the substrate. The power connection line VDL is connected to the second plate of the second capacitor through an eighteenth via.

[0391] In an exemplary embodiment, the shape of the second light-emitting signal line EM2 can be a line shape in which the main body extends along the first direction D1. The orthographic projection of the second light-emitting signal line EM2 on the substrate lies between the orthographic projection of the power connection line VDL on the substrate and the orthographic projection of the second second scan signal line on the substrate. The second light-emitting signal line EM2 is connected to the control electrode of the sixth transistor through the twelfth via.

[0392] In an exemplary embodiment, the shape of the second initial signal line INIT2 can be a line shape in which the main body extends along the first direction D1. The orthographic projection of the second initial signal line INIT2 on the substrate at least partially overlaps with the orthographic projection of the second second scan signal line on the substrate, and is located between the orthographic projection of the second light-emitting signal line EM2 on the substrate and the orthographic projection of the second reference signal line on the substrate. The area where the second initial signal line INIT2 overlaps with the first region of the active pattern of the tenth transistor can serve as the first electrode 103 of the tenth transistor. The first electrode 103 of the tenth transistor is connected to the first region of the active pattern of the tenth transistor through a tenth via.

[0393] In an exemplary embodiment, the first reference signal line REF1, the first scan signal line Gate1, the third scan signal line Gate3, the fourth scan signal line Gate4, the second light emission signal line EM2, the second initial signal line INIT2, and the power connection line VDL can be designed with equal width or with non-equal width, and can be straight lines or broken lines. This not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the signal lines. This disclosure does not limit the scope of the invention.

[0394] In an exemplary embodiment, the first electrode 13 of the first transistor of the pixel driving circuit of at least one sub-pixel is the same electrode as the first electrode 13 of the first transistor of the pixel driving circuit of the first adjacent sub-pixel.

[0395] In an exemplary embodiment, the first electrode 103 of the tenth transistor of the pixel driving circuit of at least one sub-pixel is the same electrode as the first electrode 103 of the tenth transistor of the pixel driving circuit of the first adjacent sub-pixel.

[0396] In an exemplary embodiment, the first electrode 13 of the first transistor is separately disposed and is shaped as a strip extending at least partially along the first direction D1. The first electrode 13 of the first transistor is connected to the first region of the active layer of the first transistor through a first via and is electrically connected to the first initial signal line through a twenty-second via.

[0397] In an exemplary embodiment, the second electrode 14 of the first transistor, the first electrode 23 of the second transistor, and the first electrode 83 of the eighth transistor are an integral structure, and are strip-shaped extending at least partially along the second direction D2. The second electrode 14 of the first transistor (which is also the first electrode 23 of the second transistor and the first electrode 83 of the eighth transistor) is connected to the second region of the active pattern of the first transistor through a second via, to the first region of the active pattern of the second transistor through a third via, to the first plate of the first capacitor through a fourteenth via, and to the second region of the active pattern of the eighth transistor through a nineteenth via.

[0398] In an exemplary embodiment, the first electrode 43 of the fourth transistor is separately disposed and is strip-shaped extending along the first direction D1. The first electrode 43 of the fourth transistor is connected to the first region of the active layer of the fourth transistor through a fourth via.

[0399] In an exemplary embodiment, the second electrode 44 of the fourth transistor and the second electrode 74 of the seventh transistor are an integral structure, and are strip-shaped extending along the first direction D1. The second electrode 44 of the fourth transistor (which is also the second electrode 74 of the seventh transistor) is connected to the second region of the active pattern of the fourth transistor (which is also the second region of the active pattern of the seventh transistor) through a fifth via, and is connected to the second plate of the first capacitor through a seventeen-via.

[0400] In an exemplary embodiment, the first electrode 53 of the fifth transistor is separately provided and is in the shape of a strip extending at least partially along the first direction D1. The first electrode 53 of the fifth transistor is connected to the first region of the active layer of the fifth transistor through a sixth via and is electrically connected to the second plate of the capacitor through an eleventh via.

[0401] In an exemplary embodiment, the second electrode 64 of the sixth transistor (also the second electrode 104 of the tenth transistor) is shaped as a line extending along the second direction D2, and the second electrode 64 of the sixth transistor (also the second electrode 104 of the tenth transistor) is connected to the second region of the active pattern of the sixth transistor (also the second region of the active pattern of the tenth transistor) through a seventh via.

[0402] In an exemplary embodiment, the second electrode 84 of the eighth transistor is separately provided and is in the shape of a strip extending at least partially along the second direction D2. The second electrode 84 of the eighth transistor is connected to the first plate of the second capacitor (which is also the control electrode of the third transistor) through the fifteenth via and to the second region of the active pattern of the eighth transistor through the twentieth via.

[0403] In an exemplary embodiment, the first electrode 93 of the ninth transistor is separately provided and is in the shape of a strip extending at least partially along the first direction D1. The first electrode 93 of the ninth transistor is connected to the first region of the active pattern of the ninth transistor through the ninth via and is electrically connected to the second reference signal line through the twenty-third via.

[0404] (9) Forming a first planarization layer pattern. In an exemplary embodiment, forming a first planarization layer pattern may include: depositing a seventh insulating film on a substrate on which the aforementioned pattern is formed, patterning the seventh insulating film using a patterning process to form a seventh insulating layer, coating the first planarization film on the seventh insulating layer, and patterning the first planarization film using a patterning process to form a first planarization layer pattern covering the aforementioned pattern. The first planarization layer has a plurality of via patterns, as shown in FIG27, which is a schematic diagram of FIG10 after the formation of the first planarization layer pattern.

[0405] In an exemplary embodiment, as shown in FIG27, the plurality of via patterns on the first planarization layer pattern include: the twenty-fourth via V24 to the twenty-eighth via V28.

[0406] In an exemplary embodiment, the orthographic projection of the 24th via V24 onto the substrate is within the range of the orthographic projection of the first electrode of the fourth transistor onto the substrate. The seventh insulating layer within the 24th via V24 is etched away, exposing the surface of the first electrode of the fourth transistor. The 24th via V24 is configured to allow subsequently formed data signal lines to be connected to the first electrode of the fourth transistor through the via.

[0407] In an exemplary embodiment, the orthographic projection of the 25th via V25 onto the substrate is within the range of the orthographic projection of the first electrode of the fifth transistor onto the substrate. The seventh insulating layer within the 25th via V25 is etched away, exposing the surface of the first electrode of the fifth transistor. The 25th via V25 is configured to allow a subsequently formed first power line to be connected to the first electrode of the fifth transistor through the via.

[0408] In an exemplary embodiment, the orthographic projection of the 26th via V26 onto the substrate is within the range of the orthographic projection of the second electrode of the sixth transistor (which is also the second electrode of the tenth transistor) onto the substrate. The seventh insulating layer within the 26th via V26 is etched away, exposing the surface of the second electrode of the sixth transistor (which is also the second electrode of the tenth transistor). The 26th via V26 is configured to allow the subsequently formed anode connection electrode to be connected to the second electrode of the sixth transistor (which is also the second electrode of the tenth transistor) through the via.

[0409] In an exemplary embodiment, the orthographic projection of the 27th via V27 onto the substrate is within the range of the orthographic projection of the first reference connection line onto the substrate. The seventh insulating layer within the 27th via V27 is etched away, exposing the surface of the first reference connection line. The 27th via V27 is configured to allow subsequently formed reference connection lines to be connected to the first reference connection line through the via.

[0410] In an exemplary embodiment, the orthographic projection of the 28th via V28 on the substrate is within the range of the orthographic projection of the power connection line on the substrate. The seventh insulating layer within the 28th via V28 is etched away, exposing the surface of the power connection line. The 28th via V28 is configured to allow a subsequently formed first power line to be connected to the power connection line through the via.

[0411] (10) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming a fifth conductive layer pattern may include: depositing a fifth conductive thin film on a substrate on which the aforementioned pattern is formed, and patterning the fifth conductive thin film by a patterning process to form a fifth conductive layer pattern, as shown in Figures 28 and 29. Figure 28 is a schematic diagram of the fifth conductive layer pattern in Figure 10, and Figure 29 is a schematic diagram of the fifth conductive layer pattern after it is formed in Figure 10.

[0412] In an exemplary embodiment, as shown in Figures 28 and 29, the fifth conductive layer pattern may include at least: a data signal line Data, a first power line VDD, a reference connection line REFCL, and an anode connection electrode AL located in at least one sub-pixel.

[0413] In an exemplary embodiment, for sub-pixels in the same row, the data signal line Data connected to the pixel driving circuit of at least one sub-pixel is at least partially symmetrical to the data signal line Data connected to the first adjacent sub-pixel with respect to a straight line extending along the second direction D2. The data signal line Data connected to the pixel driving circuit of at least one sub-pixel has at least partially the same structure as the data signal line Data connected to the second adjacent sub-pixel.

[0414] In an exemplary embodiment, the data signal line Data can be a line shape in which the main body extends along the second direction D2, and is electrically connected to the first electrode of the fourth transistor through the twenty-fourth via.

[0415] In an exemplary embodiment, for sub-pixels in the same row, the first power line VDD connected to the pixel driving circuit of at least one sub-pixel is at least partially symmetrical to the first power line VDD connected to the first adjacent sub-pixel with respect to a straight line extending along the second direction D2. The first power line VDD connected to the pixel driving circuit of at least one sub-pixel has at least partially the same structure as the first power line VDD connected to the second adjacent sub-pixel.

[0416] In an exemplary embodiment, the data signal line VDD can be a line shape in which the main body extends along the second direction D2. The data signal line VDD is electrically connected to the first electrode of the fifth transistor through the twenty-fifth via and to the power connection line through the twenty-eighth via.

[0417] In an exemplary embodiment, the orthographic projection of the data signal line VDD on the substrate at least partially overlaps with the orthographic projection of at least one of the first and second capacitors on the substrate.

[0418] In an exemplary embodiment, the data signal line includes: a plurality of first data connection portions DA and a plurality of second data connection portions DB. The plurality of first data connection portions DA and the plurality of second data connection portions DB are alternately arranged. At least one of the first data connection portions DA and the second data connection portions DB extends along a second direction D2.

[0419] In an exemplary embodiment, the length of the first data connection portion DA along the first direction D1 is greater than the length of the second data connection portion DB along the first direction D1.

[0420] In an exemplary embodiment, the orthographic projection of the first data connection portion DA on the substrate at least partially overlaps with the orthographic projection of at least one of the following signal lines on the substrate: the first reference signal line, the third scan signal line, the first scan signal line, the first second scan signal line, the first initial signal line, the fourth scan signal line, the first light emission signal line, and the power connection line.

[0421] In an exemplary embodiment, the orthographic projection of the first data connection portion DA on the substrate at least partially overlaps with the orthographic projection of at least one of the first and second capacitors on the substrate.

[0422] In an exemplary embodiment, the orthographic projection of the second data connection portion DB on the substrate at least partially overlaps with the orthographic projection of at least one of the following signal lines on the substrate: the second light-emitting signal line, the second scanning signal line, the second initial signal line, and the second reference signal line.

[0423] In an exemplary embodiment, the reference connection line REFCL can be a line shape in which the main body extends along the second direction D2. The reference connection line REFCL is electrically connected to the first reference signal line through a twenty-seventh via.

[0424] In an exemplary embodiment, at least one reference connection line is located between the first power line connected to the pixel driving circuit of at least one sub-pixel and the first power line connected to the pixel driving circuit of the first adjacent sub-pixel, and the center line of the at least one reference connection line extending along the first direction is on the same straight line as the axis of symmetry of the pixel driving circuit of at least one sub-pixel and the pixel driving circuit of the first adjacent sub-pixel.

[0425] In an exemplary embodiment, at least one reference connection line is located between the data signal line connected to the pixel driving circuit of at least one sub-pixel and the first power supply line connected to the pixel driving circuit of the second adjacent sub-pixel.

[0426] In an exemplary embodiment, the anode connection electrode AL is a strip shape that extends at least partially along the first direction D1, and is electrically connected to the second electrode of the sixth transistor (which is also the second electrode of the tenth transistor) through the twenty-sixth via.

[0427] At this point, the circuit structure layer is fabricated on the substrate. In a plane parallel to the display substrate, the circuit structure layer may include multiple pixel driving circuits and multiple signal lines connected to the pixel driving circuits. In a plane perpendicular to the display substrate, the circuit structure layer may be disposed on the substrate. The pixel driving circuit for at least one sub-pixel includes at least one P-type transistor, at least one N-type transistor, and at least one capacitor, the capacitor including a first electrode and a second electrode.

[0428] The pixel driving circuit layer may include a light-shielding layer, a first insulating layer, a first semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a second semiconductor layer, a fifth insulating layer, a third conductive layer, a sixth insulating layer, a fourth conductive layer, a seventh insulating layer, a first planarization layer, and a fifth conductive layer, which are sequentially disposed on the substrate. The first semiconductor layer may include at least an active pattern of at least one P-type transistor. The first conductive layer may include at least a second scan signal line, a first light-emitting signal line, a control electrode of at least one P-type transistor, and a first electrode of at least one capacitor. The second conductive layer may include at least a second electrode of at least one capacitor and a first control electrode of at least one N-type transistor. The second semiconductor layer may include at least an active pattern of at least one N-type transistor. The third conductive layer may include at least a first initial signal line, a second reference signal line, and a second control electrode of at least one N-type transistor. The fourth conductive layer may include at least a first reference signal line, a first scan signal line, a third scan signal line, a fourth scan signal line, a second light-emitting signal line, a second initial signal line, and a power connection line located at the first and second electrodes of at least one transistor in the pixel driving circuit of at least one sub-pixel. The fifth conductive layer may include at least a data signal line, a first power line, a reference connection line, and an anode connection electrode. The power connection line is connected to the first power line through a via, and the reference connection line is connected to the first reference signal line through a via.

[0429] In an exemplary embodiment, the first semiconductor layer may be an amorphous silicon layer or a polycrystalline silicon layer.

[0430] In an exemplary embodiment, the second semiconductor layer may be a metal oxide layer. The metal oxide layer may be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon and indium and tin, or an oxide containing indium or gallium and zinc. The metal oxide layer may be a single layer, a double layer, or a multilayer.

[0431] In an exemplary embodiment, at least one of the light-shielding layer and the first to fifth conductive layers can be made of a metallic material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or a conductive alloy material, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. For example, the material used to fabricate the first conductive layer may include molybdenum.

[0432] In an exemplary embodiment, the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer, the sixth insulating layer, and the seventh insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer.

[0433] In an exemplary embodiment, the first planarization layer may be made of an organic material.

[0434] In an exemplary embodiment, after the circuit structure layer is fabricated, a light-emitting structure layer is fabricated on the circuit structure layer. The fabrication process of the light-emitting structure layer may include the following operations.

[0435] On the substrate with the aforementioned pattern, an anodic conductive film is deposited, and the anodic conductive film is patterned using a patterning process to form an anodic conductive layer pattern disposed on a second planarization layer. On the substrate with the aforementioned pattern, a pixel definition film is deposited, and the pixel definition film is patterned using a patterning process to form a pixel definition layer pattern that exposes the anodic conductive layer pattern. On the substrate with the pixel definition layer pattern, an organic light-emitting material is coated, and the organic light-emitting material is patterned using a patterning process to form an organic structure layer pattern. On the substrate with the organic material layer pattern, a cathode conductive film is deposited, and the cathode conductive film is patterned using a patterning process to form a cathode conductive layer.

[0436] At this point, the luminescent structure layer has been successfully fabricated on the substrate.

[0437] In an exemplary embodiment, the anode conductive layer includes at least the anodes of a plurality of light-emitting devices.

[0438] In an exemplary embodiment, the anode conductive layer adopts a single-layer structure, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or it can adopt a multi-layer composite structure, such as ITO / Ag / ITO.

[0439] In an exemplary embodiment, the organic structure layer may include at least an organic light-emitting layer of a light-emitting device.

[0440] In an exemplary embodiment, the cathode conductive layer may include at least the cathodes of a plurality of light-emitting devices.

[0441] In an exemplary embodiment, the cathode layer can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or the aforementioned conductive alloy materials, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. Exemplarily, the fourth conductive layer can be a three-layer stacked structure formed of titanium, aluminum, and titanium.

[0442] In an exemplary embodiment, the subsequent preparation process may include: forming an encapsulation structure layer on the cathode conductive layer. The encapsulation structure layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers to ensure that external moisture cannot enter the light-emitting structure layer.

[0443] The display substrate described in this embodiment can be used in display products of any resolution.

[0444] In an exemplary embodiment, the display device can be any product or component with display function, such as electronic paper, OLED panel, active-matrix organic light emitting diode (AMOLED) panel, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, etc.

[0445] The accompanying drawings in this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in general design.

[0446] For clarity, the thickness and dimensions of layers or microstructures are enlarged in the accompanying drawings used to describe embodiments of this disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “below” another element, the element may be located “directly” on or “below” the other element, or there may be intermediate elements present.

[0447] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. A pixel driving circuit configured to drive a light-emitting device to emit light, comprising: The system comprises a first control sub-circuit, a second control sub-circuit, a third control sub-circuit, and a drive sub-circuit. The first control sub-circuit is electrically connected to the first scan signal line, the fourth scan signal line, the fifth scan signal line, the data signal line, the first node, the third node, the fourth node, and the fifth node, respectively. It is configured to provide the data signal line to the fourth node under the control of the signal of at least one of the first scan signal line, the fourth scan signal line, and the fifth scan signal line, control the signal of the fifth node through the signal of the fourth node, and provide the signal of the fifth node to the first node and the third node. The second control sub-circuit is electrically connected to the second scan signal line, the third scan signal line, the first initial signal line, the second initial signal line, the first reference signal line, the second reference signal line, the second node, the fourth node, the fifth node, and the sixth node, respectively. It is configured to provide the second reference signal line to the second node, the first reference signal line to the fourth node, the first initial signal line to the fifth node, and the second initial signal line to the sixth node under the control of the signal of at least one of the second scan signal line and the third scan signal line. The third control sub-circuit is electrically connected to the first light-emitting signal line, the second light-emitting signal line, the first power supply line, the second node, the third node, and the sixth node, respectively. It is configured to provide the first power supply line signal to the second node and the third node signal to the sixth node under the control of the signals of the first light-emitting signal line and the second light-emitting signal line. The driving sub-circuit is electrically connected to the first node, the second node and the third node respectively, and is configured to provide a driving signal to the third node; The light-emitting device is electrically connected to the sixth node and the second power line, respectively.

2. The pixel driving circuit according to claim 1, wherein, The first control sub-circuit includes: a write sub-circuit, a first storage sub-circuit, a connection sub-circuit, and a second storage sub-circuit; The writing sub-circuit is electrically connected to the first scan signal line, the data signal line and the fourth node respectively, and is configured to provide the data signal line signal to the fourth node under the control of the signal of the first scan signal line. The first storage sub-circuit, which is electrically connected to the fourth node and the fifth node respectively, is configured to store the voltage difference between the signals of the fourth node and the fifth node; The connected sub-circuit is electrically connected to the fourth scan signal line, the fifth scan signal line, the first node, the third node, and the fifth node, respectively, and is configured to provide the signal of the fifth node to the third node under the control of the signal of the fifth scan signal line, and to provide the signal of the fifth node to the first node under the control of the signal of the fourth scan signal line. The second storage sub-circuit is electrically connected to the first node and the first power line, respectively, and is configured to store the voltage difference between the signals of the first node and the first power line.

3. The pixel driving circuit according to claim 2, wherein, The write sub-circuit includes a fourth transistor; the first storage sub-circuit includes a first capacitor; the second storage sub-circuit includes a second capacitor; at least one of the first and second capacitors includes a first electrode and a second electrode; the communication sub-circuit includes a second transistor and an eighth transistor. The control electrode of the second transistor is electrically connected to the fifth scan signal line, the first electrode of the second transistor is electrically connected to the fifth node, and the second electrode of the second transistor is electrically connected to the third node. The control electrode of the fourth transistor is electrically connected to the first scan signal line, the first electrode of the fourth transistor is electrically connected to the data signal line, and the second electrode of the fourth transistor is electrically connected to the fourth node. The control electrode of the eighth transistor is electrically connected to the fourth scan signal line, the first electrode of the eighth transistor is electrically connected to the fifth node, and the second electrode of the eighth transistor is electrically connected to the first node. The first plate of the first capacitor is electrically connected to the fifth node, and the second plate of the first capacitor is electrically connected to the fourth node. The first plate of the second capacitor is electrically connected to the first node, and the second plate of the second capacitor is electrically connected to the first power line.

4. The pixel driving circuit according to claim 1, wherein, The second control sub-circuit includes: a first sub-circuit, a second sub-circuit, a third sub-circuit, and a fourth sub-circuit; The first sub-circuit is electrically connected to the second scan signal line, the first initial signal line and the fifth node respectively, and is configured to provide the signal of the first initial signal line to the fifth node under the control of the signal of the second scan signal line. The second sub-circuit is electrically connected to the third scan signal line, the first reference signal line, and the fourth node, respectively, and is configured to provide the signal of the first reference signal line to the fourth node under the control of the signal of the third scan signal line; The third sub-circuit is electrically connected to the second scan signal line, the second reference signal line, and the second node, and is configured to provide the second reference signal line to the second node under the control of the signal of the second scan signal line. The fourth sub-circuit is electrically connected to the second scan signal line, the second initial signal line, and the sixth node, respectively, and is configured to provide the signal of the second initial signal line to the sixth node under the control of the signal of the second scan signal line.

5. The pixel driving circuit according to claim 4, wherein, The first sub-circuit includes a first transistor, the second sub-circuit includes a seventh transistor, the third sub-circuit includes a ninth transistor, and the fourth sub-circuit includes a tenth transistor. The control electrode of the first transistor is electrically connected to the second scan signal line, the first electrode of the first transistor is electrically connected to the first initial signal line, and the second electrode of the first transistor is electrically connected to the fifth node. The control electrode of the seventh transistor is electrically connected to the third scan signal line, the first electrode of the seventh transistor is electrically connected to the first reference signal line, and the second electrode of the seventh transistor is electrically connected to the fourth node. The control electrode of the ninth transistor is electrically connected to the second scan signal line, the first electrode of the ninth transistor is electrically connected to the second reference signal line, and the second electrode of the ninth transistor is electrically connected to the second node. The control electrode of the tenth transistor is electrically connected to the second scan signal line, the first electrode of the tenth transistor is electrically connected to the second initial signal line, and the second electrode of the tenth transistor is electrically connected to the sixth node.

6. The pixel driving circuit according to claim 1, wherein, The first control sub-circuit includes: a second transistor, a fourth transistor, an eighth transistor, a first capacitor, and a second capacitor. At least one of the first and second capacitors includes: a first electrode and a second electrode. The second control sub-circuit includes: a first transistor, a seventh transistor, a ninth transistor, and a tenth transistor. The third control sub-circuit includes: a fifth transistor and a sixth transistor. The driving sub-circuit includes: a third transistor. The control electrode of the first transistor is electrically connected to the second scan signal line, the first electrode of the first transistor is electrically connected to the first initial signal line, and the second electrode of the first transistor is electrically connected to the fifth node. The control electrode of the second transistor is electrically connected to the fifth scan signal line, the first electrode of the second transistor is electrically connected to the fifth node, and the second electrode of the second transistor is electrically connected to the third node. The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node. The control electrode of the fourth transistor is electrically connected to the first scan signal line, the first electrode of the fourth transistor is electrically connected to the data signal line, and the second electrode of the fourth transistor is electrically connected to the fourth node. The control electrode of the fifth transistor is electrically connected to the first light-emitting signal line, the first electrode of the fifth transistor is electrically connected to the first power supply line, and the second electrode of the fifth transistor is electrically connected to the second node. The control electrode of the sixth transistor is electrically connected to the second light-emitting signal line, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the sixth node. The control electrode of the seventh transistor is electrically connected to the third scan signal line, the first electrode of the seventh transistor is electrically connected to the first reference signal line, and the second electrode of the seventh transistor is electrically connected to the fourth node. The control electrode of the eighth transistor is electrically connected to the fourth scan signal line, the first electrode of the eighth transistor is electrically connected to the fifth node, and the second electrode of the eighth transistor is electrically connected to the first node. The control electrode of the ninth transistor is electrically connected to the second scan signal line, the first electrode of the ninth transistor is electrically connected to the second reference signal line, and the second electrode of the ninth transistor is electrically connected to the second node. The control electrode of the tenth transistor is electrically connected to the second scan signal line, the first electrode of the tenth transistor is electrically connected to the second initial signal line, and the second electrode of the tenth transistor is electrically connected to the sixth node. The first plate of the first capacitor is electrically connected to the fifth node, and the second plate of the first capacitor is electrically connected to the fourth node. The first plate of the second capacitor is electrically connected to the first node, and the second plate of the second capacitor is electrically connected to the first power line. The fifth scanning signal line and the first light-emitting signal line are the same signal line; The transistor type of the eighth transistor is different from the transistor type of at least one of the first to seventh transistors, the ninth transistor, and the tenth transistor; The eighth transistor is an N-type transistor.

7. A display device, comprising: The substrate and a plurality of sub-pixels arranged in an array on the substrate, wherein at least one of the plurality of sub-pixels includes: a pixel driving circuit as described in any one of claims 1 to 6.

8. The display device according to claim 7, wherein, For at least one row of sub-pixels, at least one sub-pixel has two adjacent sub-pixels, including: the first adjacent sub-pixel and the second adjacent sub-pixel; The structure of the pixel driving circuit of at least one sub-pixel is at least partially symmetrical to the structure of the pixel driving circuit of the first adjacent sub-pixel along a straight line extending in the second direction, and the structure of the pixel driving circuit of at least one sub-pixel is at least partially the same as the structure of the pixel driving circuit of the second adjacent sub-pixel.

9. The display device according to claim 8, further comprising: Multiple data signal lines, one of which extends along a second direction; The pixel driving circuit for at least one sub-pixel includes: a second transistor, a third transistor, and a sixth transistor; At least one data signal line does not overlap with the orthographic projections on the substrate of the first and second poles of at least one of the second, third, and sixth transistors in the pixel driving circuit of at least one sub-pixel; At least one data signal line does not overlap with the orthographic projection of the control electrode of the third transistor in the pixel driving circuit of at least one sub-pixel on the substrate.

10. The display device according to claim 8, wherein, When the fifth scan signal line of at least one pixel driving circuit is the same signal line as the first light emission signal line, the display device further includes: multiple first initial signal lines, multiple second initial signal lines, multiple first reference signal lines, multiple second reference signal lines, multiple first scan signal lines, multiple second scan signal lines, multiple third scan signal lines, multiple fourth scan signal lines, multiple first light emission signal lines, and multiple second light emission signal lines; At least a portion of at least one of the following multiple first initial signal lines, multiple second initial signal lines, multiple first reference signal lines, multiple second reference signal lines, multiple first scan signal lines, multiple second scan signal lines, multiple third scan signal lines, multiple fourth scan signal lines, multiple first light emission signal lines, and multiple second light emission signal lines extends along a first direction, which intersects with the second direction. The pixel driving circuit for at least one sub-pixel includes: a first transistor, a ninth transistor, and a tenth transistor; The pixel driving circuit of at least one sub-pixel is electrically connected to two second scan signal lines. The control electrode of the first transistor in the pixel driving circuit of at least one sub-pixel is electrically connected to the first second scan signal line of the two second scan signal lines connected to the pixel driving circuit of at least one sub-pixel. The control electrode of at least one of the ninth and tenth transistors in the pixel driving circuit of at least one sub-pixel is electrically connected to the first second scan signal line of the two second scan signal lines connected to the pixel driving circuit of at least one sub-pixel. The orthographic projections of the first reference signal line, the third scan signal line, the first scan signal line, the first second scan signal line, the fourth scan signal line, the first light emission signal line, the second light emission signal line, the first second scan signal line, and the second reference signal line on the substrate, connected to the pixel driving circuit of at least one sub-pixel, are arranged sequentially along a second direction. The orthographic projection of the first initial signal line on the substrate is located between the orthographic projection of the first scan signal line on the substrate and the orthographic projection of the fourth scan signal line on the substrate, and at least partially overlaps with the orthographic projection of the first second scan signal line on the substrate. The orthographic projection of the second initial signal line on the substrate is located between the orthographic projection of the second emitting signal line on the substrate and the orthographic projection of the second reference signal line on the substrate, and at least partially overlaps with the orthographic projection of the second second scan signal line on the substrate.

11. The display device according to claim 10, wherein, The pixel driving circuit for at least one sub-pixel includes: First capacitor and second capacitor; For a pixel driving circuit of at least one sub-pixel, the orthographic projection of the first capacitor on the substrate is located between the orthographic projection of at least one of the first second scan signal line and the first initial signal line connected to the pixel driving circuit on the substrate and the orthographic projection of the fourth scan signal line on the substrate. The orthographic projection of the second capacitor on the substrate lies between the orthographic projection of the first light-emitting signal line connected to the pixel driving circuit on the substrate and the orthographic projection of the second light-emitting signal line on the substrate.

12. The display device according to claim 10, further comprising: Multiple first power lines, one of which extends along a second direction; At least one data signal line includes: a plurality of first data connection portions and a plurality of second data connection portions, the plurality of first data connection portions and the plurality of second data connection portions being alternately arranged, and at least one of the first data connection portions and the second data connection portions extending along a second direction; For the data signal line connected to the pixel driving circuit of at least one sub-pixel, the orthographic projection of the first data connection portion on the substrate at least partially overlaps with the orthographic projection of at least one of the following signal lines on the substrate: the first reference signal line, the third scan signal line, the first scan signal line, the first second scan signal line, the first initial signal line, the fourth scan signal line, the first light emission signal line, the power connection line, and at least one of the first and second capacitors in the pixel driving circuit of at least one sub-pixel. The orthographic projection of the second data connection portion on the substrate at least partially overlaps with the orthographic projection of at least one of the following signal lines on the substrate: the second light-emitting signal line, the second scanning signal line, the second initial signal line, and the second reference signal line. The length of the first data connection part along the first direction is greater than the length of the second data connection part along the first direction.

13. The display device according to claim 7, further comprising: Multiple data signal lines, multiple first power supply lines, multiple first initial signal lines, multiple second initial signal lines, multiple first reference signal lines, multiple second reference signal lines, multiple first scan signal lines, multiple second scan signal lines, multiple third scan signal lines, multiple fourth scan signal lines, multiple first light emission signal lines, and multiple second light emission signal lines; The display device further includes: a circuit structure layer disposed on a substrate, the circuit structure layer including: a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer stacked sequentially on the substrate; and a pixel driving circuit for at least one sub-pixel including: at least one P-type transistor, at least one N-type transistor and at least one capacitor, the at least one capacitor including: a first electrode plate and a second electrode plate. The first semiconductor layer includes: an active pattern of at least one P-type transistor located in a pixel driving circuit of at least one sub-pixel; The first conductive layer includes at least: a second scan signal line, a first light emission signal line, and a first electrode of at least one capacitor and a control electrode of at least one P-type transistor located in the pixel driving circuit of at least one sub-pixel; The second conductive layer includes at least: the second plate of at least one capacitor located in the pixel driving circuit of at least one sub-pixel and the first control electrode of at least one N-type transistor; The second semiconductor layer includes at least: an active pattern of at least one N-type transistor located in the pixel driving circuit of at least one sub-pixel; The third conductive layer includes at least: a first initial signal line, a second reference signal line, and a second control electrode of an eighth transistor located in the pixel driving circuit of at least one sub-pixel; The fourth conductive layer includes at least: a first reference signal line, a first scan signal line, a third scan signal line, a fourth scan signal line, a second light emission signal line, a second initial signal line, and a first and second electrode of at least one transistor of a pixel driving circuit located in at least one sub-pixel; The fifth conductive layer pattern may include at least: data signal lines and first power lines.

14. The apparatus according to claim 13, wherein, The circuit structure layer further includes: a light-shielding layer located on the side of the first semiconductor layer near the substrate, the light-shielding layer including: a light-shielding structure located at at least one sub-pixel; The light-shielding structure located at at least one sub-pixel includes: a first light-shielding part, a second light-shielding part, a first light-shielding connecting part, a second light-shielding connecting part, and a third light-shielding connecting part. The first light-shielding connecting part, the first light-shielding part, the second light-shielding connecting part, the second light-shielding part, and the third light-shielding connecting part are arranged sequentially along a second direction. The first light-shielding part is connected to the first light-shielding connecting part and the second light-shielding connecting part, respectively. The second light-shielding part is connected to the second light-shielding connecting part and the third light-shielding connecting part, respectively. At least one of the first light-shielding connecting portion, the second light-shielding connecting portion, and the third light-shielding connecting portion extends along the second direction; At least one of the first and second light-shielding portions has a length along the first direction that is greater than the length along the first direction of at least one of the light-shielding connecting portions from the first to the third light-shielding connecting portions. The pixel driving circuit for at least one sub-pixel includes: a first capacitor and a second capacitor, wherein the first capacitor and the second capacitor include a first electrode plate and a second electrode plate. The orthographic projection of the first light-shielding part of the light-shielding structure located at least one sub-pixel onto the substrate at least partially overlaps with the orthographic projection of at least one of the first and second plates of the first capacitor onto the substrate. The orthographic projection of the second light-shielding portion of the light-shielding structure located at least one sub-pixel onto the substrate at least partially overlaps with the orthographic projection of at least one of the first and second plates of the second capacitor onto the substrate.

15. The display device according to claim 13, further comprising: At least one of the multiple power connection lines located in the fourth conductive layer and the multiple reference connection lines located in the fifth conductive layer; One of the plurality of power connection lines extends along a first direction, and one of the plurality of reference connection lines extends along a second direction; At least one power connection line is electrically connected to at least one of a plurality of first power lines, and at least one reference connection line is electrically connected to at least one of a plurality of first reference signal lines. The orthographic projection of at least one power connection line on the substrate is located between the orthographic projection of at least one first light-emitting signal line on the substrate and the orthographic projection of at least one second light-emitting signal line on the substrate, and at least partially overlaps with the orthographic projection of the second capacitor in the pixel driving circuit of at least one sub-pixel on the substrate. At least one reference connection line is located between the first power line connected to the pixel driving circuit of at least one sub-pixel and the first power line connected to the pixel driving circuit of the first adjacent sub-pixel, and the center line of the at least one reference connection line extending along the first direction is on the same straight line as the axis of symmetry of the pixel driving circuit of at least one sub-pixel and the pixel driving circuit of the first adjacent sub-pixel. At least one reference connection line is located between the data signal line connected to the pixel driving circuit of at least one sub-pixel and the first power supply line connected to the pixel driving circuit of the first adjacent sub-pixel.

16. A method for driving a pixel driving circuit, configured to drive the pixel driving circuit as claimed in any one of claims 1 to 6, the method comprising: The first control sub-circuit, under the control of at least one of the first scan signal line, the fourth scan signal line, and the fifth scan signal line, provides the data signal line signal to the fourth node, controls the signal of the fifth node through the signal of the fourth node, and provides the signal of the fifth node to the first node and the third node. Under the control of at least one of the second scan signal line and the third scan signal line, the second control sub-circuit provides the signal of the second reference signal line to the second node, the signal of the first reference signal line to the fourth node, the signal of the first initial signal line to the fifth node, and the signal of the second initial signal line to the sixth node. The third control sub-circuit, under the control of the signals from the first and second light-emitting signal lines, provides the first power line signal to the second node and the third node signal to the sixth node; The driver sub-circuit provides a drive signal to the third node.

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