Display panel and display apparatus

Abstract

A display panel (PNL) and a display apparatus, relating to the technical field of display. The display panel (PNL) comprises sub-pixels (PIX) and pixel driving circuits (PDC) used for driving the sub-pixels (PIX), wherein the pixel driving circuits (PDC) each comprise a driving transistor (T5) used for generating a driving current, the driving transistor (T5) being a metal oxide transistor. Each driving transistor (T5) comprises a plurality of sub-driving transistors (ST5) successively connected in series, top gates of the sub-driving transistors (ST5) being electrically connected to each other. The display quality of the display panel (PNL) is improved.

Description

Display panel and display device

[0001] Cross-reference to related applications

[0002] The present disclosure claims priority to the Chinese patent application No. 202411354307.1, filed on September 26, 2024, and entitled "Display panel and display device", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present disclosure relates to the technical field of display, in particular, to a display panel and a display device. BACKGROUND

[0004] Full metal oxide backplane gradually replaces low-temperature polysilicon (LTPS) backplane due to its low leakage current, low cost, and simple preparation process. However, in the pixel driving circuit, the length of the channel region of the driving transistor is too long, resulting in too many interface defects of the semiconductor, increasing the hysteresis effect of the driving transistor, thereby affecting the display quality of the display panel.

[0005] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0006] The purpose of the present disclosure is to overcome the shortcomings of the prior art, and to provide a display panel and a display device to improve the display quality of the display panel.

[0007] According to one aspect of the present disclosure, a display panel is provided, comprising a sub-pixel and a pixel driving circuit for driving the sub-pixel; wherein the pixel driving circuit comprises a driving transistor for generating a driving current; the driving transistor is a metal oxide transistor; the driving transistor comprises a plurality of sub-driving transistors connected in series; the top gates of each of the sub-driving transistors are electrically connected to each other.

[0008] In an embodiment of the present disclosure, the display panel further comprises a substrate, a transistor layer, and a pixel layer which are sequentially stacked;

[0009] The transistor layer comprises a semiconductor layer and a second gate layer which are sequentially stacked on one side of the substrate;

[0010] The channel region of each sub-driving transistor is located in the semiconductor layer;

[0011] The top gate of each sub-driving transistor is located in the second gate layer, and the extension direction of the top gate of each sub-driving transistor is perpendicular to the length direction of the channel region of the sub-driving transistor.

[0012] At least one end of the top gate of each of the sub-driving transistors is electrically connected to each other through a connection structure located in the second gate layer.

[0013] In an embodiment of the present disclosure, the transistor layer further comprises a first gate layer; the first gate layer is located between the substrate and the semiconductor layer.

[0014] The first gate layer has a plurality of conductive structures corresponding to the driving transistors one by one, the conductive structures are electrically connected to the second poles of the corresponding driving transistors, and the orthographic projection of the conductive structures on the substrate covers at least the orthographic projection of the channel region of each of the sub-driving transistors of the corresponding driving transistor on the substrate.

[0015] In an embodiment of the present disclosure, the length of the channel region of each of the sub-driving transistors is the same.

[0016] In an embodiment of the present disclosure, in the same pixel driving circuit, the number of sub-driving transistors is two.

[0017] Both ends of the top gate of each of the two sub-driving transistors are electrically connected to each other through a connection structure located in the second gate layer.

[0018] In an embodiment of the present disclosure, the transistor layer further comprises a first gate layer arranged between the semiconductor layer and the substrate, the second pole of the driving transistor is electrically connected to the conductive structure arranged in the first gate layer, and the orthographic projection of the conductive structure on the substrate covers at least the orthographic projection of the channel region of each of the sub-driving transistors on the substrate.

[0019] In an embodiment of the present disclosure, the display panel further comprises a source-drain metal layer arranged on the side of the second gate layer away from the substrate, the source-drain metal layer is provided with a connection part corresponding to the pixel driving circuit, the connection part is electrically connected to the conductive structure and the second pole of the driving transistor through a via; a part of the via exposes at least part of the area of the second pole of the driving transistor, and a part of the via exposes at least part of the area of the conductive structure.

[0020] In an embodiment of the present disclosure, in the same pixel driving circuit, the number of sub-driving transistors is three or more.

[0021] The driving transistor is not provided with a conductive structure.

[0022] Alternatively, the second pole of the driving transistor is not electrically connected to the conductive structure.

[0023] In an embodiment of the present disclosure, the pixel driving circuit further comprises a storage capacitor, and the storage capacitor comprises a first electrode plate arranged on the second gate layer, and the first electrode plate serves as a connection structure.

[0024] In the same pixel driving circuit, one end of the top gate of each sub-driving transistor is electrically connected to each other through the first electrode plate.

[0025] In an embodiment of the present disclosure, the pixel driving circuit further comprises a storage capacitor, and the storage capacitor comprises a first electrode plate arranged on the second gate layer; in the same pixel driving circuit, the second gate layer is provided with two connection structures; and the first electrode plate serves as one of the connection structures.

[0026] In the same pixel driving circuit, one end of the top gate of at least one sub-driving transistor is electrically connected through the first electrode plate, and the other end of the top gate of each sub-driving transistor is electrically connected to each other through the connection structure.

[0027] In an embodiment of the present disclosure, the display panel further comprises a source-drain metal layer arranged on the side of the second gate layer away from the substrate, and the source-drain metal layer is provided with a connection part corresponding to each pixel driving circuit.

[0028] The pixel driving circuit further comprises a storage capacitor and a gate reset transistor; in the same pixel driving circuit, the storage capacitor comprises a first electrode plate arranged on the second gate layer and a second electrode plate arranged on the source-drain metal layer; one end of the top gate of the gate reset transistor is electrically connected to one of the sub-driving transistors through the corresponding connection part; and along the column direction, the orthographic projection of the connection part on the substrate and the orthographic projection of the second electrode plate on the substrate are located on both sides of the orthographic projection of the channel region of each sub-driving transistor on the substrate.

[0029] In an embodiment of the present disclosure, the display panel further comprises a first gate layer and a source-drain metal layer; wherein the first gate layer is arranged on the side of the semiconductor layer away from the second gate layer, and the source-drain metal layer is arranged on the side of the second gate layer away from the substrate.

[0030] The source-drain metal layer is provided with a driving power supply voltage trace for loading a driving power supply voltage, and the driving power supply voltage trace extends along the column direction.

[0031] The first gate layer is provided with a driving power supply voltage auxiliary trace extending along the row direction, and the driving power supply voltage auxiliary trace is electrically connected to the driving power supply voltage trace.

[0032] In an embodiment of the present disclosure, the display panel further comprises a first gate layer and a source-drain metal layer; wherein the first gate layer is arranged on a side of the semiconductor layer away from the second gate layer, and the source-drain metal layer is arranged on a side of the second gate layer away from the substrate.

[0033] The first gate layer is provided with an initialization voltage trace for loading an initialization voltage, the initialization voltage trace extending in a row direction; the source-drain metal layer is provided with a connecting part corresponding to the pixel driving circuit; and the pixel driving circuit further comprises an electrode reset transistor.

[0034] The connecting part is electrically connected to the initialization voltage trace and the first electrode of the electrode reset transistor through a via hole; a part of the via hole exposes at least a part of the initialization voltage trace, and a part of the via hole exposes at least a part of the first electrode of the electrode reset transistor.

[0035] In an embodiment of the present disclosure, each transistor in the pixel driving circuit is a metal oxide transistor.

[0036] According to another aspect of the present disclosure, a display device is provided, comprising the display panel described above.

[0037] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0038] The accompanying drawings, which are incorporated into and form part of the specification, illustrate embodiments consistent with the present disclosure and, together with the specification, serve to explain the principles of the present disclosure. It is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0039] FIG. 1 is a schematic diagram of a display panel in an embodiment of the present disclosure.

[0040] FIG. 2 is a schematic diagram of a display panel in an embodiment of the present disclosure.

[0041] FIG. 3 is a schematic diagram of a driving transistor in an embodiment of the present disclosure.

[0042] FIG. 4 is a schematic diagram of a display panel in an embodiment of the present disclosure.

[0043] FIG. 5 is a schematic diagram of a pixel driving circuit in an embodiment of the present disclosure.

[0044] FIG. 6 is a schematic diagram of a pixel driving circuit in an embodiment of the present disclosure, intended to illustrate the positional relationship of each transistor in the first gate layer, the semiconductor layer, the second gate layer, and the source-drain metal layer with the signal lines.

[0045] FIG. 7 is a schematic diagram of a pixel driving circuit in an embodiment of the present disclosure, intended to illustrate the positional relationship of each transistor in the first gate layer, the semiconductor layer, and the second gate layer with the signal lines.

[0046] FIG. 8 is a schematic diagram of a pixel driving circuit in an embodiment of the present disclosure, intended to illustrate the positional relationship of each transistor in the semiconductor layer and the second gate layer with the signal lines.

[0047] FIG. 9 is a schematic diagram of a first gate layer in an embodiment of the present disclosure.

[0048] FIG. 10 is a schematic diagram of a semiconductor layer in an embodiment of the present disclosure.

[0049] FIG. 11 is a schematic diagram of a second gate layer in an embodiment of the present disclosure.

[0050] FIG. 12 is a schematic diagram of a source-drain metal layer in an embodiment of the present disclosure.

[0051] FIG. 13 is a schematic diagram of a pixel driving circuit in an embodiment of the present disclosure, intended to illustrate the positional relationship of each transistor in the first gate layer, the semiconductor layer, the second gate layer, and the source-drain metal layer with the signal lines.

[0052] FIG. 14 is a schematic diagram of a pixel driving circuit in an embodiment of the present disclosure, intended to illustrate the positional relationship of each transistor in the first gate layer, the semiconductor layer, and the second gate layer with the signal lines.

[0053] FIG. 15 is a schematic diagram of a pixel driving circuit in an embodiment of the present disclosure, intended to illustrate the positional relationship of each transistor in the semiconductor layer and the second gate layer with the signal lines.

[0054] FIG. 16 is a schematic diagram of a first gate layer in an embodiment of the present disclosure.

[0055] FIG. 17 is a schematic diagram of a semiconductor layer in an embodiment of the present disclosure.

[0056] FIG. 18 is a schematic diagram of a second gate layer in an embodiment of the present disclosure.

[0057] FIG. 19 is a schematic diagram of a source-drain metal layer in an embodiment of the present disclosure.

[0058] FIG. 20 is a schematic diagram of a pixel driving circuit in one embodiment of the present disclosure, intended to illustrate the positional relationship of each transistor in the first gate layer, the semiconductor layer, the second gate layer, and the source-drain metal layer with the signal lines.

[0059] FIG. 21 is a schematic diagram of a pixel driving circuit in one embodiment of the present disclosure, intended to illustrate the positional relationship of each transistor in the first gate layer, the semiconductor layer, and the second gate layer with the signal lines.

[0060] FIG. 22 is a schematic diagram of a pixel driving circuit in one embodiment of the present disclosure, intended to illustrate the positional relationship of each transistor in the semiconductor layer and the second gate layer with the signal lines.

[0061] FIG. 23 is a schematic diagram of the first gate layer in one embodiment of the present disclosure.

[0062] FIG. 24 is a schematic diagram of the semiconductor layer in one embodiment of the present disclosure.

[0063] FIG. 25 is a schematic diagram of the second gate layer in one embodiment of the present disclosure.

[0064] FIG. 26 is a schematic diagram of the source-drain metal layer in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0065] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings. Example embodiments, may, however, be implemented in many different forms and should not be construed as limited to the implementations set forth herein; rather, these implementations are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. Like reference numerals refer to like elements throughout the figures, and thus a detailed description of the same will not be repeated. In addition, the drawings are only schematic and are non-limiting.

[0066] Although relative terms such as "upper", "lower", etc. are used herein to describe one component's relationship to another component as the figure is oriented, such terminology is used for convenience only and is not limiting. It is to be understood that, if the figure were inverted, the described component would then be at the lower side. As used herein, the term "on" or "under" includes "directly on" or "directly under" and "indirectly on" or "indirectly under". As used herein, the term "directly on" means that there are no intermediate elements between the elements that are directly on one another. As used herein, the term "indirectly on" means that there are one or more intermediate elements between the elements that are indirectly on one another.

[0067] The terms "one", "a", "an", "the", and "at least one" are used to indicate that "one or more" of the identified element / s, component / s, etc. is / are present; the terms "including" and "having" are used to indicate an open-ended inclusion of the elements, component / s, etc. listed, and that additional elements / component / s are not precluded; the terms "first", "second", and "third", etc. are used only as labels, and do not imply any orderedness or numerical limitation on their objects.

[0068] In the embodiments of the present disclosure, a thin film transistor includes an active layer, a gate insulating layer, and a gate which are stacked. The active layer is located in a semiconductor layer, and the active layer includes a channel region and a source and a drain which are respectively located on both sides of the channel region. The channel region retains a semiconductor property, and the source and the drain are both conductive. In the embodiments of the present disclosure, the functions of the "source" and the "drain" are sometimes exchanged with each other, i.e., the "source" and the "drain" can be exchanged with each other, in the case of using a transistor with opposite polarity or in the case of changing the current direction in the operation of a circuit. In the embodiments of the present disclosure, for any one transistor, one of the "source" and the "drain" is referred to as a first electrode of the transistor, and the other is referred to as a second electrode of the transistor. In the embodiments of the present disclosure, at least part of a signal has a high level and a low level; one of the high level and the low level can be a gate-on level of the signal, which can turn on a controlled transistor; the other of the high level and the low level can be a gate-off level of the signal, which can turn off the controlled transistor. For example, for a signal for controlling a P-type transistor, which can be loaded to a control terminal of the P-type transistor, the gate-on level of the signal is the low level, and the gate-off level of the signal is the high level. For another example, for a signal for controlling an N-type transistor, which can be loaded to a control terminal of the N-type transistor, the gate-on level of the signal is the high level, and the gate-off level of the signal is the low level.

[0069] The structural layer A is located on the side of the structural layer B away from the substrate, which can be understood as that the structural layer A is formed on the side of the structural layer B away from the substrate. When the structural layer B is a patterned structure, part of the structure of the structural layer A can also be located at the same physical height as the structural layer B or below the physical height of the structural layer B, wherein the substrate is the height reference.

[0070] In an embodiment of the present disclosure, any one transistor can have a "top gate" and a "bottom gate", so that any one transistor can be a dual-gate transistor. The "top gate" of one transistor is located on the side of the semiconductor layer of the transistor away from the substrate; the "bottom gate" of one transistor is located between the semiconductor layer of the transistor and the substrate.

[0071] The display device according to embodiments of the present disclosure can be a television, a computer screen, a smart phone, a smart watch screen, or other types of display devices.

[0072] The display panel PNL according to embodiments of the present disclosure includes a display area AA and a peripheral area BB located at least one side of the display area AA. The display area AA of the display panel PNL includes an array of display units. Each display unit includes a sub-pixel PIX and a pixel driving circuit PDC for driving the sub-pixel PIX. The display panel PNL includes a plurality of scan lines GL arranged along a row direction DH in the display area AA, each scan line GL is arranged one-to-one corresponding to each display unit row; each pixel driving circuit PDC of the corresponding display unit row is connected to the scan line GL. The display panel PNL includes a plurality of data lines DL arranged along a column direction DV in the display area AA, each data line DL is arranged one-to-one corresponding to each display unit column; each pixel driving circuit PDC of the corresponding display unit column is connected to the data line DL. In this way, the pixel driving circuit PDC of each display unit is connected to one scan line GL and one data line DL. When a selection signal is loaded on the scan line GL, the data voltage loaded on the data line DL can be loaded to the pixel driving circuit PDC, so that the pixel driving circuit PDC can control the brightness of the sub-pixel PIX according to the written driving voltage.

[0073] Optionally, the sub-pixel PIX can be a current-driven self-luminous element, for example, can be any one of OLED, PLED, QLED, Micro LED, Mini LED, etc. In this embodiment, the sub-pixel PIX can include sub-pixels PIX of multiple different colors, for example, red sub-pixels for emitting red light, green sub-pixels for emitting green light, and blue sub-pixels for emitting blue light. It can be understood that in other embodiments of the present disclosure, the sub-pixels PIX in the display area AA can also have sub-pixels PIX of other colors (for example, yellow sub-pixels for emitting yellow light, cyan sub-pixels for emitting cyan light, white sub-pixels for emitting white light, etc.).

[0074] The display panel PNL according to embodiments of the present disclosure will be described in detail below in combination with the structure of each film layer in the display panel PNL:

[0075] FIG. 2 is a schematic diagram of a film layer structure of a display panel PNL according to an embodiment of the present disclosure. Referring to FIG. 2, in some embodiments of the present disclosure, the display panel PNL includes a driving layer DRL and a pixel layer PIXL which are sequentially stacked on the substrate SBT;

[0076] Optionally, the substrate SBT can be a substrate SBT of inorganic material, a substrate SBT of organic material, or a composite substrate of a substrate SBT of inorganic material and a substrate SBT of organic material. For example, in some embodiments of the present disclosure, the material of the substrate SBT can be a glass material such as soda lime glass, quartz glass, sapphire glass, etc.

[0077] In some other embodiments of the present disclosure, the material of the substrate SBT can be polymethyl methacrylate, polyvinyl alcohol, polyvinyl phenol, polyether sulfone, polyimide, polyamide, polyacetal, polycarbonate, polyethylene terephthalate, polyethylene naphthalate, or a combination thereof. In some other embodiments of the present disclosure, the substrate SBT can also be a flexible substrate, for example, the material of the substrate SBT can include polyimide.

[0078] Optionally, in the driving layer DRL, any one pixel driving circuit can include a thin film transistor and a storage capacitor CST (not shown in the drawings). Further, the thin film transistor can be a top-gate thin film transistor, a bottom-gate thin film transistor, or a dual-gate thin film transistor; the material of the active layer of the thin film transistor can be amorphous silicon semiconductor material, low-temperature polysilicon semiconductor material, metal oxide semiconductor material, organic semiconductor material, carbon nanotube semiconductor material, or other types of semiconductor material; and the thin film transistor can be an N-type thin film transistor or a P-type thin film transistor.

[0079] It can be understood that the types of any two transistors among the transistors in the pixel driving circuit can be the same or different. For example, in some embodiments, in one pixel driving circuit, some transistors can be N-type transistors and some transistors can be P-type transistors. For another example, in some other embodiments, in one pixel driving circuit, the material of the active layer of some transistors can be low-temperature polysilicon semiconductor material and the material of the active layer of some transistors can be metal oxide semiconductor material. In some embodiments of the present disclosure, the thin film transistor is a low-temperature polysilicon transistor. In some other embodiments of the present disclosure, some thin film transistors are low-temperature polysilicon transistors and some thin film transistors are metal oxide transistors.

[0080] Optionally, the pixel driving circuit PDC comprises at least a data write transistor, a driving transistor and a storage capacitor, and a gate of the driving transistor can be electrically connected with one of the electrode plates of the storage capacitor. A source of the data write transistor can be electrically connected with the data line DL, and a gate of the data write transistor can be electrically connected with the scan line GL. The pixel driving circuit PDC is configured such that when a scan signal is loaded on the scan line GL, the data write transistor is turned on, and then a driving voltage on the data line DL is written to the gate of the driving transistor and the storage capacitor. The driving voltage can be maintained by the storage capacitor after the data write transistor is turned off. The driving transistor is capable of outputting a driving current to drive the sub-pixel PIX to emit light under the control of the voltage on the gate thereof. It can be understood that the pixel driving circuit PDC of the embodiments of the present disclosure can further comprise other transistors or capacitors to make the pixel driving circuit PDC have better driving performance. For example, the pixel driving circuit PDC can be a 7T1C (7 thin film transistors and one storage capacitor), 8T1C (8 thin film transistors and one storage capacitor) or other architecture of pixel driving circuit.

[0081] Optionally, referring to FIG. 2, the driving layer DRL can include a buffer layer (e.g., the first buffer layer Buff1 and the second buffer layer Buff2 shown in FIG. 2) stacked on the substrate base plate SBT, a metal light-blocking layer BSM disposed between the first buffer layer Buff1 and the substrate base plate SBT, a semiconductor layer SCL (e.g., a low-temperature polysilicon semiconductor layer and a metal oxide semiconductor layer) in the pixel layer PIXL, a gate insulating layer (e.g., the first gate insulating layer GI1, the second gate insulating layer GI2, and the third gate insulating layer GI3 shown in FIG. 2), a gate layer (e.g., the first gate layer GT1 and the second gate layer GT2 shown in FIG. 2), an interlayer dielectric layer ILD, a source-drain metal layer SD (e.g., the first source-drain metal layer SD1 and the second source-drain metal layer SD2 shown in FIG. 2), a planarization layer (e.g., the first planarization layer PLN1 and the second planarization layer PLN2 shown in FIG. 2), and the like. Each thin-film transistor and the storage capacitor CST (not specifically labeled in the drawings of the present application) can be formed by the semiconductor layer, the gate insulating layer, the gate layer, the interlayer dielectric layer ILD, the source-drain metal layer, and the like. Of course, other film layers can also be used. The positional relationship of each film layer can be determined according to the film layer structure of the thin-film transistor. Further, the semiconductor layer can be used to form the active layer of the transistor (including the first electrode, the second electrode, and the channel region of the transistor) and, if necessary, can be made conductive to form part of the wiring or a conductive structure. The first source-drain metal layer SD1 can be used to form the scanning signal wiring. The gate layer can be used to form one or more of the gate layer wiring such as the reset control signal wiring, the light-emitting control signal wiring, and the like, to form the gate electrode of the transistor, and to form part or all of the electrode plate of the storage capacitor CST. The source-drain metal layer can be used to form the data line, the driving power voltage wiring, and the like, and to form part of the electrode plate of the storage capacitor CST.

[0082] Of course, in other embodiments of the present disclosure, the driving layer DRL can also include other film layers as needed, such as a metal light-blocking layer BSM between the semiconductor layer and the substrate base plate SBT, and the like. Any one of the above-mentioned semiconductor layer, gate layer, source-drain metal layer, and the like can also be multi-layered as needed, such as two different semiconductor layers in the driving layer DRL, or two or three source-drain metal layers or two or three gate layers. Accordingly, the insulating film layers in the driving layer DRL (such as the gate insulating layer, the interlayer dielectric layer ILD, the planarization layer, and the like) can be adaptively increased or decreased, or new insulating film layers can be added as needed.

[0083] Optionally, the pixel layer PIXL can include a pixel electrode layer PEL, an emission functional layer EL and a common electrode layer COML which are sequentially stacked. The pixel electrode layer PEL has a plurality of pixel electrodes PE in the display area of the display panel. The pixel definition layer PDL has a plurality of through pixel openings corresponding to the plurality of pixel electrodes PE, and any one pixel opening exposes at least a partial region of the corresponding pixel electrode PE. For example, the pixel definition layer PDL covers the edges of the pixel electrode PE and exposes at least a partial internal region of the pixel electrode PE, so that the pixel definition layer PDL can effectively define the actual effective region (the region directly connected to the emission functional layer EL) of the pixel electrode, and further define the light-emitting region and light-emitting area of the sub-pixel. The common electrode layer COML covers the emission functional layer EL as a common electrode. The pixel electrode PE and the common electrode layer COML provide carriers such as electrons and holes to the emission functional layer EL, so that the emission functional layer EL emits light. The part of the emission functional layer EL between the pixel electrode and the common electrode layer COML can serve as a light-emitting functional unit of the sub-pixel. The pixel electrode PE, the common electrode layer COML and the light-emitting functional unit form a light-emitting element of the sub-pixel. One of the pixel electrode PE and the common electrode layer COML serves as an anode of the sub-pixel, and the other serves as a cathode of the sub-pixel.

[0084] In this example, the display panel is an OLED (organic light-emitting diode) display panel. The emission functional layer EL can include an organic light-emitting layer, and can include one or more of a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer. Further, the organic light-emitting layer can include a light-emitting layer host material and a light-emitting layer guest material, which can be a fluorescent dopant or a phosphorescent dopant, and in particular can be a thermally activated delayed fluorescence material.

[0085] It can be understood that the display panel can also be other types of display panels, such as a QLED display panel, a QD-OLED display panel, or other types of display panels.

[0086] Referring to FIG. 2, the display panel can further include a thin film encapsulation layer TFE, which can be disposed on the surface of the pixel layer PIXL away from the substrate SBT, and can include inorganic encapsulation layers and organic encapsulation layers which are alternately stacked. The inorganic encapsulation layer can effectively block external moisture and oxygen, preventing water and oxygen from invading the pixel layer PIXL and causing the materials in the pixel layer PIXL to age. Optionally, the edges of the inorganic encapsulation layer can be located in the peripheral area. The organic encapsulation layer is located between two adjacent inorganic encapsulation layers to achieve planarization and reduce stress between the inorganic encapsulation layers. The edges of the organic encapsulation layer can be located between the edges of the display area and the edges of the inorganic encapsulation layer.

[0087] Exemplarily, the thin film encapsulation layer TFE includes a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer (not specifically shown in the drawings) stacked in sequence on the side of the pixel layer PI XL away from the substrate SBT. The first inorganic encapsulation layer covers the display area and extends to the outside of the barrier wall; the organic encapsulation layer covers the display area and extends to the inside of the barrier wall; and the second inorganic encapsulation layer covers the organic encapsulation layer and extends to the outside of the barrier wall. On the outside of the barrier wall, the second inorganic encapsulation layer is in contact with the first inorganic encapsulation layer. In this way, the organic encapsulation layer is enclosed by the first inorganic encapsulation layer and the second inorganic encapsulation layer, and the stress on the first inorganic encapsulation layer and the second inorganic encapsulation layer is balanced. The first inorganic encapsulation layer and the second inorganic encapsulation layer enclose the organic encapsulation layer and isolate the organic encapsulation layer from water and oxygen. Of course, in other embodiments of the present disclosure, the display panel can also not be provided with a thin film encapsulation layer TFE, but other ways to encapsulate and protect the pixel layer.

[0088] In some embodiments of the present disclosure, the display panel can further include a touch metal layer (not specifically shown in the drawings), which can be arranged on the side of the thin film transistor away from the pixel layer PI XL, so that the display panel has a touch function.

[0089] In this embodiment, referring to FIG. 2, the driving layer DRL can further include a transistor layer TL, a first source-drain metal layer SD1, and a second source-drain metal layer SD2; the transistor layer TL is a combination of various film layers arranged between the substrate SBT and the first source-drain metal layer SD1, which can form various thin film transistors required by the pixel driving circuit.

[0090] In the related art, the low-temperature polysilicon backplane has a complex preparation process and expensive equipment, such as the ELA process (laser annealing process), which increases the cost of the display panel. Therefore, the industry uses a full metal oxide backplane to replace the low-temperature polysilicon backplane to reduce the cost of the display panel. At present, the mobility of the metal oxide transistor is gradually increasing from the traditional 10 cm2·V-1·s-1, which has a good development prospect.

[0091] In the related art, in order to facilitate the development of full gray scale, the channel region of the driving transistor in the pixel driving circuit PDC is designed as a continuous "one-dimensional" long channel. However, as the length of the channel region increases, the semiconductor will generate more interface defects, making the semiconductor of the driving transistor more likely to capture electrons, resulting in a decrease in the carrier concentration, a decrease in the on-state capability of the driving transistor, a positive bias of the threshold voltage, an increase in the hysteresis effect and stress (such as positive bias temperature stress (PBTS)) of the driving transistor, and an impact on the display quality of the display panel PNL (for example, the display panel has a bright flicker or residual image).

[0092] To solve the above problems, the display panel PNL is provided. Referring to FIG. 1, FIG. 3, and FIG. 5, the display panel PNL includes a sub-pixel PIX and a pixel driving circuit PDC for driving the sub-pixel PIX. The pixel driving circuit PDC includes a driving transistor T5 for generating a driving current. The driving transistor T5 is a metal oxide transistor. The driving transistor T5 includes a plurality of sub-driving transistors ST5 connected in series. The top gates of the sub-driving transistors ST5 are electrically connected to each other. In an example, referring to FIG. 7, the driving transistor T5 includes two sub-driving transistors ST5 connected in series. In another example, referring to FIG. 14 and FIG. 21, the driving transistor T5 includes three or four sub-driving transistors ST5 connected in series.

[0093] In this way, the driving transistor T5 includes a plurality of sub-driving transistors ST5 connected in series. The channel region of the driving transistor T5 is composed of the channel regions ST5A of the plurality of sub-driving transistors. Since the interface defects of the channel region increase with the length of the channel region, and the interface defects of the channel region ST5A of a single sub-driving transistor are less, the interface defects of the channel region of the driving transistor T5 composed of the channel regions ST5A of the plurality of sub-driving transistors are less than the interface defects of the long channel of the continuous “linear” in the related art. This is conducive to improving the concentration of carriers, reducing the stress and hysteresis effect of the driving transistor T5, and improving the display quality of the display panel PNL.

[0094] In an embodiment of the present disclosure, referring to FIG. 4 and FIG. 7, the display panel PNL further includes a substrate substrate SBT, a transistor layer TL, and a pixel layer PXL stacked in sequence. The transistor layer TL includes a semiconductor layer SCL and a second gate layer GT2 stacked in sequence on one side of the substrate SBT. The channel region ST5A of each sub-driving transistor is located in the semiconductor layer SCL. The top gate of each sub-driving transistor ST5 is located in the second gate layer GT2, and the extension direction of the top gate of each sub-driving transistor ST5 is perpendicular to the length direction of the channel region ST5A of the sub-driving transistor. At least one end of the top gate of each sub-driving transistor ST5 is electrically connected to each other through a connection structure CS in the second gate layer GT2. In an example, referring to FIG. 14, one end of the top gate of each sub-driving transistor ST5 is electrically connected to each other through the connection structure CS in the second gate layer GT2. In another example, referring to FIG. 7, both ends of the top gate of each sub-driving transistor ST5 are electrically connected to each other through the connection structure CS in the second gate layer GT2. In this way, the top gates of the sub-driving transistors ST5 are electrically connected to each other through the connection structure CS, so as to realize the driving transistor T5 composed of the sub-driving transistors ST5.

[0095] In an embodiment of the present disclosure, referring to FIG. 4, FIG. 6, FIG. 7 and FIG. 9, the transistor layer TL further comprises a first gate layer GT1. The first gate layer GT1 is located between the substrate base plate SBT and the semiconductor layer SCL. The first gate layer GT1 has a plurality of conductive structures BS corresponding to the driving transistor T5, the conductive structure BS is electrically connected with the second electrode of the corresponding driving transistor T5, and the orthogonal projection of the conductive structure BS on the substrate base plate SBT covers at least the orthogonal projection of the channel region ST5A of each sub-driving transistor of the corresponding driving transistor T5 on the substrate base plate SBT. Since the driving transistor T5 is a metal oxide transistor, the second electrode of the driving transistor T5 is the source electrode of the driving transistor T5. By electrically connecting the conductive structure BS and the second electrode of the driving transistor T5, the conductive structure BS serves as the bottom gate of the driving transistor T5, which is conducive to improving the saturation characteristics of the driving transistor T5; for example, when the source-drain voltage of the driving transistor T5 changes, the driving current changes less than 1%, and the light-emitting gray scale of the sub-pixel PIX changes within two gray scales, which is conducive to the development of full gray scale. At the same time, the conductive structure BS as the bottom gate of the driving transistor T5 can shield light for the driving transistor T5 to reduce the photo-generated current effect of the driving transistor T5, reduce the threshold voltage drift of the driving transistor T5, and improve the display quality of the display panel PNL.

[0096] In an embodiment of the present disclosure, the lengths of the channel regions ST5A of the sub-driving transistors are the same. In this way, the lengths of the channel regions ST5A of the sub-driving transistors are within a reasonable range, which is conducive to reducing the interface defects of the channel regions ST5A of the sub-driving transistors, thereby further reducing the interface defects of the channel regions of the driving transistor T5, reducing the hysteresis effect and stress of the driving transistor T5, and improving the display quality of the display panel PNL. In other embodiments of the present disclosure, the lengths of the channel regions ST5A of the sub-driving transistors can be different.

[0097] In an embodiment of the present disclosure, referring to FIG. 6 and FIG. 7, in the same pixel driving circuit PDC, the number of sub-driving transistors ST5 is two. In other words, the channel region of the driving transistor T5 includes two channel regions ST5A of sub-driving transistors which are electrically connected in sequence.

[0098] In an embodiment of the present disclosure, referring to FIGS. 6 and 7, the two ends of the top gate of the two sub-driving transistors ST5 are electrically connected to each other through the connection structure CS located in the second gate layer GT2. In other words, a gap is left between the top gates of the two sub-driving transistors ST5, and the two ends of the top gates of the two sub-driving transistors ST5 are electrically connected to each other through the connection structure CS. In this way, the electrical connection between the top gates of the two adjacent sub-driving transistors ST5 is achieved, and the two sub-driving transistors ST5 are combined to form a driving transistor T5.

[0099] In an embodiment of the present disclosure, referring to FIGS. 4, 6, 7 and 9, the transistor layer TL further includes a first gate layer GT1 disposed between the semiconductor layer SCL and the substrate substrate SBT. The second electrode of the driving transistor T5 is electrically connected to the conductive structure BS disposed in the first gate layer GT1, and the orthogonal projection of the conductive structure BS on the substrate substrate SBT at least covers the orthogonal projection of the channel region ST5A of each sub-driving transistor on the substrate substrate SBT. By electrically connecting the conductive structure BS and the source electrode of the driving transistor T5, the conductive structure BS serves as the bottom gate of the driving transistor T5, which is beneficial to improve the saturation characteristics of the driving transistor T5; for example, when the source-drain voltage of the driving transistor T5 changes, the driving current changes less than 1%, the luminous gray scale of the sub-pixel PIX changes within two gray scales, which is convenient for the development of full gray scale. At the same time, the conductive structure BS as the bottom gate of the driving transistor T5 can shield the light for the channel region of the driving transistor T5, so as to reduce the photo-generated current effect of the driving transistor T5, reduce the threshold voltage drift of the driving transistor T5, and improve the display quality of the display panel PNL.

[0100] In an embodiment of the present disclosure, referring to FIG. 4, FIG. 6 and FIG. 12, the display panel PNL further comprises a source-drain metal layer SD arranged on the side of the second gate layer GT2 away from the substrate SBT. The source-drain metal layer SD is provided with a connection part corresponding to the pixel driving circuit PDC, which is electrically connected to the conductive structure BS and the second electrode of the driving transistor T5 through a via. Part of the via exposes at least part of the area of the second electrode of the driving transistor T5, and part of the via exposes at least part of the area of the conductive structure BS. The connection part is a fifth connection part MA5, and the fifth connection part MA5 is provided with a tenth upper via area HB10. In the same pixel driving circuit PDC, the orthographic projection of the conductive structure BS on the substrate SBT and the orthographic projection of the second electrode of the driving transistor T5 on the substrate SBT respectively overlap with the orthographic projection of the tenth upper via area HB10 of the corresponding fifth connection part MA5 on the substrate SBT. In this way, the conductive structure BS in the first gate layer GT1 and the second electrode of the driving transistor T5 in the semiconductor layer SCL are electrically connected through a via, which realizes the electrical connection between the conductive structure BS and the second electrode of the driving transistor T5, reduces the number of vias, saves the wiring space occupied by the vias, and is conducive to improving the pixel density.

[0101] It should be noted that in the drawings of the present disclosure, the via area has a metal material, and the white circles on the wiring in the drawings only represent the position of the via area on the wiring, and not a via on the wiring.

[0102] In an embodiment of the present disclosure, in the same pixel driving circuit PDC, the number of sub-driving transistors ST5 is three or more. In an example, referring to FIG. 14, the number of sub-driving transistors ST5 in the same pixel driving circuit PDC is three. In another example, referring to FIG. 21, the number of sub-driving transistors ST5 in the same pixel driving circuit PDC is four. In other embodiments of the present disclosure, the number of sub-driving transistors ST5 in the same pixel driving circuit PDC can be five, six, seven, and the like.

[0103] In an embodiment of the present disclosure, the driving transistor T5 is not provided with a conductive structure BS, so that the driving transistor T5 is a top-gate transistor, which is conducive to improving the switching rate of the driving transistor T5.

[0104] In an embodiment of the present disclosure, the driving transistor T5 has a conductive structure BS as a bottom gate of the driving transistor T5, and the second electrode of the driving transistor T5 is not electrically connected with the conductive structure BS. On the one hand, the conductive structure BS makes the driving transistor T5 a double-gate transistor, which facilitates to improve the control accuracy of the driving current; on the other hand, the conductive structure BS can shield light for the channel region of the driving transistor T5, so as to reduce the photo-generated current effect of the driving transistor T5, and make the driving transistor T5 more stable.

[0105] In an embodiment of the present disclosure, referring to FIGS. 5 and 14, the pixel driving circuit PDC further includes a storage capacitor CST. The storage capacitor CST includes a first electrode plate EP1 disposed on the second gate layer GT2, and the first electrode plate EP1 serves as a connection structure CS. In the same pixel driving circuit PDC, one end of the top gate of each sub-driving transistor ST5 is electrically connected with each other through the first electrode plate EP1, and one end of the top gate of each sub-driving transistor ST5 is not connected, so that there is a gap between the top gates of the adjacent two sub-driving transistors ST5. In this way, the top gates of each sub-driving transistor ST5 are electrically connected through the first electrode plate EP1, so as to facilitate to realize that each sub-driving transistor ST5 constitutes a driving transistor T5.

[0106] In an embodiment of the present disclosure, referring to FIGS. 5, 6 and 20, the pixel driving circuit PDC further includes a storage capacitor CST. The storage capacitor CST includes a first electrode plate EP1 disposed on the second gate layer GT2. In the same pixel driving circuit PDC, the second gate layer GT2 is provided with two connection structures CS, and the first electrode plate EP1 serves as one of the connection structures CS. In the same pixel driving circuit PDC, one end of the top gate of at least one sub-driving transistor ST5 is electrically connected through the first electrode plate EP1, and the other end of the top gate of each sub-driving transistor ST5 is electrically connected with each other through the connection structure CS. In an example, referring to FIG. 21, one end of the top gate of one sub-driving transistor ST5 is electrically connected through the first electrode plate EP1. In another example, referring to FIG. 7, one end of the top gate of two sub-driving transistors ST5 is electrically connected through the first electrode plate EP1. In other examples, one end of the top gate of three or each sub-driving transistor ST5 is electrically connected through the first electrode plate EP1. In this way, each sub-driving transistor ST5 constitutes a driving transistor T5.

[0107] In an embodiment of the present disclosure, referring to FIGS. 4, 5, 6 and 12, the display panel PNL further comprises a source-drain metal layer SD arranged on the side of the second gate layer GT2 away from the substrate SBT. The source-drain metal layer SD is provided with a connection portion corresponding to each pixel driving circuit PDC, which is a fourth connection portion MA4. The pixel driving circuit PDC further comprises a storage capacitor CST and a gate reset transistor T1. In the same pixel driving circuit PDC, the storage capacitor CST comprises a first electrode plate EP1 arranged on the second gate layer GT2 and a second electrode plate EP2 arranged on the source-drain metal layer SD. The second electrode of the gate reset transistor T1 is electrically connected to one end of the top gate of one of the sub-driving transistors ST5 through the corresponding fourth connection portion MA4. In the column direction DV, the orthogonal projection of the fourth connection portion MA4 on the substrate SBT and the orthogonal projection of the second electrode plate EP2 on the substrate SBT are located on both sides of the orthogonal projection of the channel region ST5A of each sub-driving transistor on the substrate SBT. In this way, the second electrode of the gate reset transistor T1 and the top gate of the threshold compensation transistor T3 are electrically connected through the fourth connection portion MA4.

[0108] In an embodiment of the present disclosure, referring to FIGS. 4, 6, 7 and 12, the display panel PNL further comprises a first gate layer GT1 and a source-drain metal layer SD. The first gate layer GT1 is arranged on the side of the semiconductor layer SCL away from the second gate layer GT2, and the source-drain metal layer SD is arranged on the side of the second gate layer GT2 away from the substrate SBT. The source-drain metal layer SD is provided with a driving power supply voltage wire VDDL for loading a driving power supply voltage VDD, and the driving power supply voltage wire VDDL extends in the column direction DV. The first gate layer GT1 is provided with a driving power supply voltage auxiliary wire VDDLX extending in the row direction DH, and the driving power supply voltage auxiliary wire VDDLX is electrically connected to the driving power supply voltage wire VDDL. In this way, the driving power supply voltage VDD can be meshed through the driving power supply voltage auxiliary wire VDDLX and the driving power supply voltage wire VDDL, which is beneficial to improving the display uniformity of the display panel PNL.

[0109] In an embodiment of the present disclosure, referring to 4, FIG. 6 and FIG. 12, the display panel PNL further comprises a first gate layer GT1 and a source-drain metal layer SD; wherein the first gate layer GT1 is arranged on the side of the semiconductor layer SCL away from the second gate layer GT2, and the source-drain metal layer SD is arranged on the side of the second gate layer GT2 away from the substrate SBT; the first gate layer GT1 is provided with an initialization voltage trace VIL for loading an initialization voltage Vinit, and the initialization voltage trace VIL extends along the row direction DH; the source-drain metal layer SD is provided with a connection part corresponding to the pixel driving circuit PDC; the connection part is a first connection part MA1, and the first connection part MA1 is provided with a first upper via hole region HB1. The pixel driving circuit PDC further comprises an electrode reset transistor T2; the connection part is electrically connected with the initialization voltage trace VIL and the first electrode of the electrode reset transistor T2 through a via hole; part of the via hole exposes at least part of the area of the initialization voltage trace VIL, and part of the via hole exposes at least part of the area of the first electrode of the electrode reset transistor T2.

[0110] In an embodiment of the present disclosure, each transistor in the pixel driving circuit PDC is a metal oxide transistor, so as to reduce the generation of leakage current. At the same time, compared with a low-temperature polysilicon display panel, a metal oxide display panel can reduce the cost.

[0111] The basic principle of the pixel driving circuit is described below by taking the equivalent circuit diagram of the pixel driving circuit PDC of the 7T1C (7 transistors and 1 capacitor) shown in FIG. 5 as an example:

[0112] The pixel driving circuit PDC shown in FIG. 5 comprises an initialization voltage trace VIL for loading an initialization voltage Vinit, a reset control signal trace RSTL for loading a reset control signal RST, an emission control signal trace EML for loading an emission control signal EM, a first scan signal trace GN1L for loading a first scan signal GN1, a second scan signal trace GN2L for loading a second scan signal GN2, a driving power voltage trace VDDL for loading a driving power voltage VDD, a data line DL for loading a data signal Data, a gate reset transistor T1, an electrode reset transistor T2, a threshold compensation transistor T3, a first emission control transistor T4, a driving transistor T5, a second emission control transistor T6, a data writing transistor T7, a storage capacitor CST, a first node N1, a second node N2, a third node N3, and a fourth node N4.

[0113] The gate reset transistor T1, the electrode reset transistor T2, the threshold compensation transistor T3, the first light emitting control transistor T4, the driving transistor T5, the second light emitting control transistor T6, and the data writing transistor T7 are N-type transistors, and the channel regions are metal oxide semiconductor materials, so as to reduce the leakage current of the first node N1.

[0114] The first electrode of the gate reset transistor T1 is electrically connected with the driving power voltage wire VDDL, the second electrode of the gate reset transistor T1 is electrically connected with the first node N1, and the gate of the gate reset transistor T1 is electrically connected with the second scan signal wire GN2L. The gate reset transistor T1 is used to load the driving power voltage VDD to the first node N1 in response to the gating level of the second scan signal GN2.

[0115] The first electrode of the electrode reset transistor T2 is electrically connected with the initialization voltage wire VIL, the second electrode of the electrode reset transistor T2 is electrically connected with the fourth node N4, and the gate of the electrode reset transistor T2 is electrically connected with the reset control signal wire RSTL. The electrode reset transistor T2 is used to load the initialization voltage Vinit to the fourth node N4 in response to the gating level of the reset control signal RST.

[0116] The first electrode of the threshold compensation transistor T3 is electrically connected with the first node N1, the second electrode of the threshold compensation transistor T3 is electrically connected with the second node N2, and the gate of the threshold compensation transistor T3 is electrically connected with the first scan signal wire GN1L. The threshold compensation transistor T3 is used to connect the first node N1 and the second node N2 in response to the gating level of the first scan signal GN1.

[0117] The first electrode of the first light emitting control transistor T4 is electrically connected with the driving power voltage wire VDDL, the second electrode of the first light emitting control transistor T4 is electrically connected with the second node N2, and the gate of the first light emitting control transistor T4 is electrically connected with the light emitting control signal wire EML. The first light emitting control transistor T4 is used to load the driving power voltage VDD to the second node N2 in response to the gating level of the light emitting control signal EM.

[0118] The first electrode of the driving transistor T5 is electrically connected with the second node N2, the second electrode of the driving transistor T5 is electrically connected with the third node N3, and the gate of the driving transistor T5 is electrically connected with the first node N1. The driving transistor T5 is used to generate a driving current under the voltage control of the first node N1.

[0119] The first electrode of the second light-emitting control transistor T6 is electrically connected with the third node N3, the second electrode of the second light-emitting control transistor T6 is electrically connected with the fourth node N4, and the gate of the second light-emitting control transistor T6 is electrically connected with the light-emitting control signal wire EML. The second light-emitting control transistor T6 is used to connect the third node N3 and the fourth node N4 in response to the gating level of the light-emitting control signal EM.

[0120] The first electrode of the data writing transistor T7 is electrically connected with the data line DL, the second electrode of the data writing transistor T7 is electrically connected with the third node N3, and the gate of the data writing transistor T7 is electrically connected with the first scanning signal wire GN1L. The data writing transistor T7 is used to load the data signal Data to the third node N3 in response to the gating level of the first scanning signal GN1.

[0121] It should be noted that, in some embodiments, the gates of the first light-emitting control transistor T4 and the second light-emitting control transistor T6 can be loaded with different light-emitting control signals EM, that is, the gating level of the light-emitting control signal EM can be loaded to the gate of the first light-emitting control transistor T4 first, and then loaded to the gate of the second light-emitting control transistor T6; or, the gating level of the light-emitting control signal EM can be loaded to the gate of the second light-emitting control transistor T6 first, and then loaded to the gate of the first light-emitting control transistor T4. In adjacent two pixel driving circuits PDC in a pixel driving circuit column, the second scanning signal GN2 loaded to the next pixel driving circuit PDC is the first scanning signal GN1 loaded to the previous pixel driving circuit PDC.

[0122] The pixel electrode of the sub-pixel PIX is electrically connected with the fourth node N4 (not shown in the drawings of the present application), and the common electrode is used to load the reference power supply voltage VSS.

[0123] The storage capacitor CST includes a first electrode plate EP1 and a second electrode plate EP2. The first electrode plate EP1 is electrically connected with the first node N1, and the second electrode plate EP2 is electrically connected with the fourth node N4. It should be noted that, in the pixel driving circuit PDC shown in FIG. 5, the wires of various signals are not shown, and only various signals are shown.

[0124] The positions of various transistors in the driving layer DRL and the distribution of various signal wires in the 7T1C pixel driving circuit shown in FIG. 5 will be described in detail below in combination with three examples (wherein the driving layer DRL includes the first gate layer GT1, the semiconductor layer SCL, the second gate layer GT2, and the source-drain metal layer SD which are sequentially stacked on the substrate SBT, and the channel region length of the driving transistor T5 is 12 μm):

[0125] In the first example, referring to FIGS. 6, 7 and 9, the first gate layer GT1 is provided with a driving power voltage auxiliary wire VDDLX, a conductive structure BS, and an initialization voltage wire VIL. The driving power voltage auxiliary wire VDDLX extends along the row direction DH and is used to load a driving power voltage VDD to the first electrode of the gate reset transistor T1 and the first electrode of the first light emitting control transistor T4, and the ninth lower via hole area HA9 is arranged on the driving power voltage auxiliary wire VDDLX. The initialization voltage wire VIL extends along the row direction DH and is used to load an initialization voltage Vinit to the first electrode of the electrode reset transistor T2, and the first lower main via hole area HA1A is arranged on the initialization voltage wire VIL. The conductive structure BS includes a first conductive part BS1 extending along the column direction DV and a second conductive part BS2 extending along the row direction DH, the first conductive part BS1 and the second conductive part BS2 are integrally connected, and the tenth lower main via hole area HA10A is arranged on the first conductive part BS1; the orthogonal projection of the second conductive part BS2 on the substrate SBT covers the orthogonal projection of the channel region of the driving transistor T5 on the substrate SBT to form a bottom gate of the driving transistor T5. Along the column direction DV, the orthogonal projection of the conductive structure BS on the substrate SBT is located between the orthogonal projection of the driving power voltage auxiliary wire VDDLX on the substrate SBT and the orthogonal projection of the initialization voltage wire VIL on the substrate SBT.

[0126] Referring to FIG. 10, the semiconductor layer SCL is provided with the active layers of the gate reset transistor T1, the electrode reset transistor T2, the threshold compensation transistor T3, the first light emitting control transistor T4, the driving transistor T5, the second light emitting control transistor T6, and the data writing transistor T7, and the first lower sub via hole area HA1B, the second lower via hole area HA2, the fourth lower via hole area HA4, the fifth lower via hole area HA5, the seventh lower via hole area HA7, the eighth lower via hole area HA8, and the tenth lower sub via hole area HA10B. Along the column direction DV, the channel region of the gate reset transistor T1A, the channel region of the threshold compensation transistor T3A, the channel region of the driving transistor T5, and the channel region of the first light emitting control transistor T4A are sequentially arranged, and the channel region of the data writing transistor T7A, the channel region of the driving transistor T5, the channel region of the second light emitting control transistor T6A, and the channel region of the electrode reset transistor T2A are sequentially arranged. Along the row direction DH, the channel region of the driving transistor T5 is located between the channel region of the threshold compensation transistor T3A and the channel region of the data writing transistor T7A, and the channel region of the driving transistor T5 is located between the channel region of the first light emitting control transistor T4A and the channel region of the second light emitting control transistor T6A.

[0127] The channel region of the driving transistor T5 includes two sub-channel regions ST5A of sub-driving transistors.

[0128] Referring to FIGS. 6, 7, 8, 10 and 11, the second gate layer GT2 is provided with the first scan signal wire GN1L, the second scan signal wire GN2L, the connection structure CS, the top gate of the driving transistor T5, the first electrode plate EP1, the light-emitting control signal wire EML, the reset control signal wire RSTL, and the sixth lower via hole area HA6. Among them, the first scan signal wire GN1L, the second scan signal wire GN2L, the light-emitting control signal wire EML, and the reset control signal wire RSTL all extend along the row direction DH; along the column direction DV, the second scan signal wire GN2L, the first scan signal wire GN1L, the light-emitting control signal wire EML, and the reset control signal wire RSTL are arranged in sequence. The orthographic projection of the first scan signal wire GN1L on the substrate SBT overlaps the orthographic projection of the channel region T3A of the threshold compensation transistor on the substrate SBT and the orthographic projection of the channel region T7A of the data writing transistor on the substrate SBT, respectively, to form the gate of the threshold compensation transistor T3 and the data writing transistor T7. The orthographic projection of the second scan signal wire GN2L on the substrate SBT overlaps the orthographic projection of the channel region T1A of the gate reset transistor on the substrate SBT, to form the gate of the gate reset transistor T1. The orthographic projection of the light-emitting control signal wire EML on the substrate SBT overlaps the orthographic projection of the channel region T4A of the first light-emitting control transistor on the substrate SBT and the orthographic projection of the channel region T6A of the second light-emitting control transistor on the substrate SBT, respectively, to form the gate of the first light-emitting control transistor T4 and the second light-emitting control transistor T6. The orthographic projection of the reset control signal wire RSTL on the substrate SBT overlaps the orthographic projection of the channel region T2A of the electrode reset transistor on the substrate SBT, to form the gate of the electrode reset transistor T2.

[0129] The driving transistor T5 includes two sub-driving transistors ST5 connected in sequence. The top gates of the two sub-driving transistors ST5 extend along the column direction DV, the length direction of the channel regions ST5A of the two sub-driving transistors is parallel to the row direction DH, and the length of the channel regions ST5A of the two sub-driving transistors is 6 μm, that is, the width of the top gates of the two sub-driving transistors ST5 is 6 μm; the orthogonal projection of the two sub-driving transistors ST5 on the substrate SBT overlaps the orthogonal projection of the channel regions ST5A of the corresponding sub-driving transistors on the substrate SBT. The number of the connection structures CS is two, the first electrode plate EP1 is one of the connection structures CS, so that one end of the top gates of the two sub-driving transistors ST5 is electrically connected through the first electrode plate EP1; the other connection structure CS electrically connects the other end of the top gates of the two sub-driving transistors ST5, so that the channel regions ST5A of the two sub-driving transistors form the channel region of the driving transistor T5, and the top gates of the two sub-driving transistors ST5 form the top gate of the driving transistor T5.

[0130] Along the column direction DV, the orthogonal projection of the connection structure CS away from the first electrode plate EP1 on the substrate SBT and the orthogonal projection of the first electrode plate EP1 on the substrate SBT are located on both sides of the orthogonal projection of the top gate of the driving transistor T5 on the substrate SBT, and the orthogonal projection of the connection structure CS away from the first electrode plate EP1 on the substrate SBT and the orthogonal projection of the first electrode plate EP1 on the substrate SBT are both located between the orthogonal projection of the first scan signal wire GN1L on the substrate SBT and the orthogonal projection of the light-emitting control signal wire EML on the substrate SBT; the connection structure CS away from the first electrode plate EP1 is provided with a sixth lower via region HA6. In this way, the connection structure CS away from the first electrode plate EP1 can provide a larger via space for the sixth lower via region HA6.

[0131] Referring to FIG. 12, the source-drain metal layer SD is provided with a first connection part MA1, a second connection part MA2, a third connection part MA3, a fourth connection part MA4, a fifth connection part MA5, a first upper via region HB1, a second upper via region HB2, a third upper via region HB3, a fourth upper via region HB4, a fifth upper via region HB5, a sixth upper via region HB6, a seventh upper via region HB7, an eighth upper via region HB8, a ninth upper via region HB9, a tenth upper via region HB10, a second electrode plate EP2, a driving power supply voltage wire VDDL, and a data line DL.

[0132] The first connection part MA1 is provided with a first upper via hole area HB1. The first upper via hole area HB1 and the first lower main via hole area HA1A overlap and are electrically connected through a via hole; the first upper via hole area HB1 and the first lower auxiliary via hole area HA1B overlap and are electrically connected through a via hole. On the one hand, the initialization voltage Vinit is loaded to the first electrode of the electrode reset transistor T2; on the other hand, the initialization voltage VIL and the first electrode of the electrode reset transistor T2 are electrically connected through the via hole (the first upper via hole area HB1) provided on the first connection part MA1, the number of via holes is reduced, the wiring space is saved, and the difficulty of the punching process is reduced.

[0133] The second connection part MA2 is provided with a second upper via hole area HB2 and a third upper via hole area HB3. The second connection part MA2 includes an integral horizontal segment and a vertical segment. The horizontal segment is provided with the second upper via hole area HB2 away from one end of the vertical segment, the second upper via hole area HB2 and the second lower via hole area HA2 overlap and are electrically connected through a via hole; the third upper via hole area HB3 is provided at the position where the horizontal segment is connected with the vertical segment, and the third upper via hole area HB3 is used for connecting the pixel electrode of the sub-pixel PIX; the vertical segment is electrically connected with the second electrode plate EP2 away from one end of the horizontal segment. In this way, the electrical connection between the second electrode plate EP2, the sub-pixel PIX, the second electrode of the electrode reset transistor T2, and the second electrode of the second light-emitting control transistor T6 is realized.

[0134] The third connection part MA3 is provided with a fourth upper via hole area HB4 and a ninth upper via hole area HB9. The fourth upper via hole area HB4 and the fourth lower via hole area HA4 overlap and are electrically connected through a via hole to realize the loading of the driving power voltage VDD to the first electrode of the gate reset transistor T1. The ninth upper via hole area HB9 and the ninth lower via hole area HA9 overlap and are electrically connected through a via hole to realize the loading of the driving power voltage VDD from the driving power voltage wire VDDL to the driving power voltage auxiliary wire VDDLX, which is convenient for the gridding of the driving power voltage VDD and improves the display uniformity of the display panel PNL.

[0135] The fourth connection part MA4 is provided with a fifth upper via hole area HB5 and a sixth upper via hole area HB6. The fifth upper via hole area HB5 and the fifth lower via hole area HA5 overlap and are electrically connected through a via hole. The sixth upper via hole area HB6 and the sixth lower via hole area HA6 overlap and are electrically connected through a via hole. In this way, the fourth connection part MA4 realizes the electrical connection between the second electrode of the gate reset transistor T1, the second electrode of the threshold compensation transistor T3, the gate electrode of the driving transistor T5, and the first electrode plate EP1.

[0136] The tenth upper via region HB10 is arranged on the fifth connection portion MA5. The tenth upper via region HB10 and the tenth lower main via region HA10A overlap and are electrically connected by a via. The tenth upper via region HB10 and the tenth lower auxiliary via region HA10B overlap and are electrically connected by a via. On the one hand, the conductive structure BS is electrically connected to the source of the driving transistor T5, which is conducive to improving the saturation characteristics of the driving transistor T5 (for example, when the source-drain voltage of the driving transistor T5 changes, the driving current changes less than 1%, and the luminous gray scale changes within two gray scales). On the other hand, the electrical connection between the conductive structure BS and the source of the driving transistor T5 is realized by arranging one via (the tenth upper via region HB10) on the fifth connection portion MA5, which reduces the number of vias, saves the wiring space, and reduces the difficulty of the punching process.

[0137] The seventh upper via region HB7 is arranged on the driving power supply voltage wire VDDL. The seventh upper via region HB7 and the seventh lower via region HA7 overlap and are electrically connected by a via to load the driving power supply voltage VDD to the first electrode of the first light-emitting control transistor T4.

[0138] The eighth upper via region HB8 is arranged on the data line DL. The eighth upper via region HB8 and the eighth lower via region HA8 overlap and are electrically connected by a via to load the data signal Data to the first electrode of the data writing transistor T7.

[0139] The driving power supply voltage wire VDDL and the data line DL both extend along the column direction DV. Along the row direction DH, the driving power supply voltage wire VDDL and the data line DL are located on both sides of the second electrode plate EP2.

[0140] Referring to FIGS. 6, 10, 11, and 12, the orthogonal projection of the fifth connection portion MA5 on the substrate substrate SBT does not overlap the orthogonal projection of the second gate layer GT2 on the substrate substrate SBT to avoid punching a via on the second gate layer GT2. The orthogonal projection of the data line DL on the substrate substrate SBT only overlaps the orthogonal projection of the first electrode of the data writing transistor T7 on the substrate substrate SBT. The orthogonal projection of the driving power supply voltage wire VDDL on the substrate substrate SBT only overlaps the orthogonal projection of the first electrode of the gate reset transistor T1 on the substrate substrate SBT.

[0141] Therefore, the driving transistor T5 includes two sub-driving transistors ST5 connected in series, so that the channel region of the driving transistor T5 is composed of the channel regions ST5A of the two sub-driving transistors connected in series, and the length of each channel region ST5A of the sub-driving transistor is 6 μm. Compared with the continuous "one-word" long channel of 12 μm in the related art, the interface defects of the channel region of the driving transistor T5 composed of the channel regions ST5A of the two sub-driving transistors are reduced, which is beneficial to improve the concentration of carriers, reduce the stress and hysteresis effect of the driving transistor T5, and improve the display quality of the display panel PNL.

[0142] In the second example, referring to FIGS. 13-19, the difference between this example and the first example is that the first gate layer GT1 does not provide the conductive structure BS, and correspondingly, the source-drain metal layer SD does not provide the fifth connection part MA5 and the tenth upper via hole region HB10. Therefore, by removing the conductive structure BS and the fifth connection part MA5, the via hole area of the first gate layer GT1 and the source-drain metal layer SD is removed, so that the second gate layer GT2 has a larger layout space, thereby facilitating the layout of the top gate of the sub-driving transistor ST5. The difference between this example and the first example is that the driving transistor T5 includes three sub-driving transistors ST5 connected in series, that is, the channel region of the driving transistor T5 is composed of the channel regions ST5A of the three sub-driving transistors, and the length of each channel region ST5A of the sub-driving transistor is 4 μm. The top gate of each of the three sub-driving transistors ST5 is electrically connected to the first electrode plate EP1 at one end, and the first electrode plate EP1 serves as the connection structure CS. The other end of the top gate of each of the three sub-driving transistors ST5 is not connected to each other, that is, there is a gap between the other end of the top gate of each of the two adjacent sub-driving transistors ST5. The sixth lower via hole region HA6 is provided at one end of one of the sub-driving transistors ST5 away from the first electrode plate EP1. Therefore, the driving transistor T5 is divided into three sub-driving transistors ST5, so that the length of each channel region ST5A of the sub-driving transistor is 4 μm. Since the shorter the length of the channel region, the fewer the interface defects, the interface defects of the channel region of the driving transistor T5 composed of the channel regions ST5A of the three sub-driving transistors are further reduced, thereby more beneficial to improve the concentration of carriers, further reduce the stress and hysteresis effect of the driving transistor T5, and improve the display quality of the display panel PNL.

[0143] In a third example, referring to FIGS. 20-26, the difference between this example and the second example is that the driving transistor T5 includes four sub-driving transistors ST5 connected in series, that is, the channel region of the driving transistor T5 is composed of the channel regions ST5A of the four sub-driving transistors, and the length of each channel region ST5A of the sub-driving transistors is 3 μm. One end of the top gate of one of the sub-driving transistors ST5 is electrically connected to the first electrode plate EP1, and the first electrode plate EP1 serves as a connection structure CS; in other words, one end of the top gate of three of the sub-driving transistors ST5 is not directly electrically connected to the first electrode plate EP1, and a gap is left between the first electrode plate EP1 and the one end of the top gate of the three sub-driving transistors ST5. The other ends of the top gates of the four sub-driving transistors ST5, which are away from the first electrode plate EP1, are electrically connected to each other through another connection structure CS. The sixth lower via hole region HA6 is arranged on the connection structure CS at the one end of the sub-driving transistors ST5 away from the first electrode plate EP1. On the one hand, the driving transistor T5 is divided into four sub-driving transistors ST5, so that the length of each channel region ST5A of the sub-driving transistors is 3 μm. Since the shorter the length of the channel region, the fewer the interface defects, the interface defects of the channel region of the driving transistor T5 composed of the channel regions ST5A of the four sub-driving transistors are further reduced, thereby more favorably increasing the concentration of carriers, further reducing the stress and hysteresis effect of the driving transistor T5, and further improving the display quality of the display panel PNL. On the other hand, by arranging the sixth lower via hole region HA6 on the connection structure CS, the sixth lower via hole region HA6 is provided with a larger layout space, and when the length of the channel region ST5A of the sub-driving transistor is reduced, the problem that the length of the channel region ST5A of the sub-driving transistor cannot be reduced due to the area limitation of the sixth lower via hole region HA6 is avoided.

[0144] Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the features disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims

1. A display panel, comprising a sub-pixel and a pixel driving circuit for driving the sub-pixel; wherein, The pixel driving circuit comprises a driving transistor for generating a driving current; The driving transistor is a metal oxide transistor; The driving transistor comprises a plurality of sub-driving transistors connected in series; the top gates of each of the sub-driving transistors are electrically connected to each other.

2. The display panel of claim 1, wherein, The display panel further comprises a substrate, a transistor layer and a pixel layer which are sequentially stacked; The transistor layer comprises a semiconductor layer and a second gate layer which are sequentially stacked on one side of the substrate; The channel region of each sub-driving transistor is located in the semiconductor layer; The top gate of each sub-driving transistor is located in the second gate layer, and the extension direction of the top gate of each sub-driving transistor is perpendicular to the length direction of the channel region of the sub-driving transistor; At least one end of the top gate of each sub-driving transistor is electrically connected to each other through a connection structure located in the second gate layer.

3. The display panel of claim 2, wherein, The transistor layer further comprises a first gate layer; the first gate layer is located between the substrate and the semiconductor layer; The first gate layer has a plurality of conductive structures corresponding to the driving transistors; the conductive structures are electrically connected to the second poles of the corresponding driving transistors; and the orthographic projection of the conductive structures on the substrate covers at least the orthographic projection of the channel region of each sub-driving transistor of the corresponding driving transistor on the substrate.

4. The display panel of claim 3, wherein, The length of the channel region of each sub-driving transistor is the same.

5. The display panel of claim 2, wherein, In the same pixel driving circuit, the number of sub-driving transistors is two; The two ends of the top gates of the two sub-driving transistors are electrically connected to each other through a connection structure located in the second gate layer.

6. The display panel of claim 5, wherein, The transistor layer further comprises a first gate layer located between the semiconductor layer and the substrate; the second pole of the driving transistor is electrically connected to a conductive structure located in the first gate layer; and the orthographic projection of the conductive structure on the substrate covers at least the orthographic projection of the channel region of each sub-driving transistor on the substrate.

7. The display panel of claim 6, wherein, The display panel further comprises a source-drain metal layer located on the side of the second gate layer away from the substrate; the source-drain metal layer is provided with a connection part corresponding to each pixel driving circuit; the connection part is electrically connected to the conductive structure and the second pole of the driving transistor through a via; a part of the via exposes at least part of the second pole of the driving transistor, and a part of the via exposes at least part of the conductive structure.

8. The display panel of claim 2, wherein, In the same pixel driving circuit, the number of sub-driving transistors is three or more; The driving transistor does not have a conductive structure; Alternatively, the second pole of the driving transistor is not electrically connected to a conductive structure.

9. The display panel of claim 8, wherein, The pixel driving circuit further comprises a storage capacitor; the storage capacitor comprises a first electrode plate located in the second gate layer; the first electrode plate serves as a connection structure; In the same pixel driving circuit, one end of the top gate of each sub-driving transistor is electrically connected to each other through the first electrode plate.

10. The display panel of claim 8, wherein, The pixel driving circuit further comprises a storage capacitor, the storage capacitor comprises a first electrode plate arranged on the second gate layer; in the same pixel driving circuit, the second gate layer is provided with two connection structures; the first electrode plate serves as one of the connection structures; In the same pixel driving circuit, one end of the top gate of at least one of the sub-driving transistors is electrically connected through the first electrode plate, and the other end of the top gate of each of the sub-driving transistors is electrically connected to each other through the connection structures.

11. The display panel of claim 2, wherein, The display panel further comprises a source-drain metal layer arranged on the side of the second gate layer away from the substrate; the source-drain metal layer is provided with a connection part corresponding to each of the pixel driving circuits; The pixel driving circuit further comprises a storage capacitor and a gate reset transistor; in the same pixel driving circuit, the storage capacitor comprises a first electrode plate arranged on the second gate layer and a second electrode plate arranged on the source-drain metal layer; one end of the top gate of the gate reset transistor is electrically connected to one of the sub-driving transistors through the corresponding connection part; along the column direction, the orthogonal projection of the connection part on the substrate and the orthogonal projection of the second electrode plate on the substrate are located on both sides of the orthogonal projection of the channel region of each of the sub-driving transistors on the substrate.

12. The display panel of claim 2, wherein, The display panel further comprises a first gate layer and a source-drain metal layer; wherein the first gate layer is arranged on the side of the semiconductor layer away from the second gate layer, and the source-drain metal layer is arranged on the side of the second gate layer away from the substrate; The source-drain metal layer is provided with a driving power supply voltage trace for loading a driving power supply voltage, and the driving power supply voltage trace extends along the column direction; The first gate layer is provided with a driving power supply voltage auxiliary trace extending along the row direction, and the driving power supply voltage auxiliary trace is electrically connected to the driving power supply voltage trace.

13. The display panel of claim 2, wherein, The display panel further comprises a first gate layer and a source-drain metal layer; wherein the first gate layer is arranged on the side of the semiconductor layer away from the second gate layer, and the source-drain metal layer is arranged on the side of the second gate layer away from the substrate; The first gate layer is provided with an initialization voltage trace for loading an initialization voltage, and the initialization voltage trace extends along the row direction; the source-drain metal layer is provided with a connection part corresponding to each of the pixel driving circuits; the pixel driving circuit further comprises an electrode reset transistor; The connection part is electrically connected to the initialization voltage trace and the first electrode of the electrode reset transistor through a via; part of the via exposes at least part of the area of the initialization voltage trace, and part of the via exposes at least part of the area of the first electrode of the electrode reset transistor.

14. The display panel according to any one of claims 1 to 13, wherein Each of the transistors in the pixel driving circuit is a metal-oxide transistor.

15. A display device comprising the display panel of any one of claims 1-14.

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