Display system

Abstract

The present technology relates to a display system configured such that the power consumption of a control system can be reduced when carrying out time-controlled light emission control. A PWM generation circuit generates a PWM control signal by extracting a prescribed pulse from a generation pulse train on the basis of a PWM control value of a prescribed number of bits. The generation pulse train is formed from a low-order pulse train composed of pulses having a pulse width corresponding to each bit of the low-order bits of the PWM control value, and a high-order pulse train composed of the maximum number of pulses of a prescribed pulse width as represented by the high-order bits of the PWM control value, which are different from the low-order bits. The present technology can be applied to, for example, an LED display in which pixels comprising LEDs are arranged in an array.

Description

Display system

[0001] This technology relates to a display system, and more particularly to a display system that can reduce the power consumption of the control system when performing time-controlled light emission control.

[0002] Traditionally, large-screen displays in home theaters and similar settings have been achieved using projection-type display devices such as projectors. However, in recent years, there has been a growing demand for large-screen displays on the displays of multi-functional television receivers that also have television broadcasting reception, internet connectivity, and gaming capabilities.

[0003] In large-screen displays used for such large-screen presentations, the market for LED displays, which are direct-view displays using small LEDs (Light Emitting Diodes) as pixels, is expanding. Furthermore, significant progress has been made in reducing the pixel pitch of LED displays, with some now having a pixel pitch of less than 1.0 mm.

[0004] One method for driving pixels in LED displays is the active drive method, which drives each pixel independently. This active drive method is also used in OLED (organic LED) displays that use TFT (Thin Film Transistor) (see, for example, Patent Document 1).

[0005] The active drive method has the characteristic of a long continuous illumination time of the LED within the display time. Therefore, with the miniaturization of LEDs (there are now many LEDs that are 100um x 100um or smaller), even when the LED emits light with a small current value, the brightness, which is determined by the current value and illumination time, does not decrease, making it possible to achieve high brightness.

[0006] However, in an active drive system using general-purpose silicon semiconductors, each pixel is driven individually, so the light emission control circuit that controls the light emission of the LED of each pixel needs to be mounted on the substrate as a very small IC (Integrated Circuit).

[0007] Here, there are two methods for controlling the light emission of an LED: current-controlled (analog drive) and time-controlled (digital drive). Current-controlled light emission changes the brightness by changing the amount of current flowing through the LED. Time-controlled light emission changes the brightness by flowing a fixed amount of current through the LED and changing the duration of that current flow. PWM (Pulse width modulation) control and PDM (Pulse density modulation) control are used as examples of time-controlled light emission control.

[0008] The PWM control signal is generated by counting the number of clock cycles of an externally input high-speed clock using a built-in high-speed multi-bit counter. Therefore, ICs that implement a light emission control circuit that controls light emission using PWM control consume a large amount of power.

[0009] Japanese Patent Publication No. 2018-25829

[0010] As described above, there is a demand for methods to reduce the power consumption of control systems when performing time-controlled light emission control in display systems such as LED displays, but such demands have not been adequately met.

[0011] This technology was developed in light of these circumstances and aims to reduce the power consumption of the control system when performing time-controlled light emission control.

[0012] One aspect of this technology is a display system that includes a light emission control signal generation unit that generates a light emission control signal by extracting a predetermined pulse from a generation pulse train, which is composed of a first pulse train consisting of pulses with pulse widths corresponding to each bit of a first bit group of the light emission control value, and a second pulse train consisting of the largest number of pulses with predetermined pulse widths represented by a second bit group of the light emission control value that is different from the first bit group, based on a light emission control value of a predetermined number of bits.

[0013] In one aspect of this technology, a light emission control signal is generated by extracting a predetermined pulse from a generation pulse train, which is composed of a first pulse train consisting of pulses with pulse widths corresponding to each bit of a first bit group of the light emission control value, and a second pulse train consisting of the maximum number of pulses with predetermined pulse widths represented by a second bit group of the light emission control value that is different from the first bit group, based on a light emission control value of a predetermined number of bits.

[0014] The display system may be a standalone device or a module integrated into another device.

[0015] This figure shows an example configuration of an active-drive LED display using matrix wiring. This figure shows an example configuration of the logic circuit of the IC in Figure 1. This is a timing chart explaining the signals in the IC in Figure 2. This figure shows an example configuration of an active-drive LED display using single wiring. This figure shows an example configuration of the logic circuit of the IC in Figure 4. This is a timing chart explaining the signals in the IC in Figure 5. This figure shows an example configuration of the first embodiment of a display system to which this technology is applied. This figure shows an example configuration of the video wall controller and display unit in Figure 7. This figure shows an example configuration of the LED array panel in Figure 8. This figure shows a first example configuration of the logic circuit of the IC in Figure 9. This figure shows an example configuration of the lower bit processing circuit in Figure 10. This is a timing chart explaining the signals in the IC in Figure 10. This figure shows a detailed explanation of the clock signal in Figure 12. This figure shows a process for generating a PWM control signal for the lower bits. This figure shows another example of a clock signal. This figure shows yet another example of a clock signal. This figure shows a second example configuration of the logic circuit of the IC in Figure 9. This is a timing chart explaining the signals in the IC in Figure 17. This figure shows a detailed explanation of the clock signal in Figure 18. This figure shows an example of the display unit's implementation. This figure shows an example of the structure of the pixel substrate in Figure 20. This figure shows an example configuration of an LED array panel in a second embodiment of a display system to which this technology is applied. This figure shows an example configuration of the logic circuit of the IC in Figure 22. This is a timing chart explaining the signals in the IC in Figure 23. This figure shows an example structure of a pixel substrate on which an LED array panel is mounted. This figure shows another example of the pulse width of each pulse in the lower pulse train. This figure explains the effect of the offset value in Figure 26.

[0016] The following describes the embodiments for implementing this technology. The description will be in the following order: 1. Active-driven LED display using matrix wiring 2. Active-driven LED display using single wiring 3. First embodiment (display system with video wall using matrix wiring) 4. Second embodiment (display system with video wall using single wiring) 5. Other examples of pulse width of lower pulse trains

[0017] <1. Active-Driven LED Display Using Matrix Wiring> <Example of LED Display Configuration> Figure 1 shows an example of an active-driven LED display configuration using matrix wiring.

[0018] The LED display 1 in Figure 1 comprises a plurality of pixel units 2, a column drive circuit 3, a column wiring 4, a row drive circuit 5, and a row wiring 6. The LED display 1 drives each pixel unit 2 using an active drive method.

[0019] Specifically, the pixel units 2 are arranged in a matrix in the LED display 1. Each pixel unit 2 comprises three LEDs (light-emitting parts) 11-1 to 11-3, each emitting red, green, and blue light for a single pixel, and an IC 12 having a light emission control circuit that PWM controls the light emission of the LEDs 11-1 to 11-3. Column wiring 4 corresponding to the column of the pixel unit 2 and row wiring 6 corresponding to the row are connected to the IC 12 of each pixel unit 2. The power supply voltage VDD and the ground voltage GND are also connected to the IC 12.

[0020] The column drive circuit 3 is connected to the column wiring 4, which is arranged for each column of the pixel unit 2. The column drive circuit 3 (light emission control data signal generation unit) generates the light emission control data signal DAin for each column of the pixel unit 2 on a frame-by-frame basis and supplies it to the pixel unit 2 via the column wiring 4 of that column.

[0021] The light emission control data signal DAin is a signal synchronized with a fundamental clock of a predetermined frequency. The light emission control data signal DAin is output from the column drive circuit 3 and includes, in time division, a data signal representing the PWM control data for each pixel unit 2 in the column corresponding to the light emission control data signal DAin, and a start code signal representing the start instruction for PWM control. The PWM control data is composed of, in order from the beginning, a 1-bit header, a 15-bit control value for IC 12, and a 16-bit PWM control value (light emission control value) representing the brightness gradation of each LED 11-1 to 11-3. The header of the PWM control data is set to 1 to indicate that PWM control data follows this header. The start instruction for PWM control is represented by setting 0 as the 1-bit header.

[0022] The row drive circuit 5 is connected to row wiring 6, which is arranged for each row of the pixel unit 2. The row drive circuit 5 generates a clock signal CKSin for each row of the pixel unit 2 on a frame-by-frame basis and supplies it to the pixel unit 2 via the row wiring 6 for that row.

[0023] The clock signal CKSin is a signal synchronized with the base clock. The clock signal CKSin includes, in time division, an acquisition instruction signal that instructs the acquisition of the light emission control data signal DAin, and a PWM generation signal used to generate the PWM control signal (light emission control signal). The acquisition instruction signal for the clock signal CKSin is a signal in which the base clock is activated only for the period during which the data signal of the row corresponding to that clock signal CKSin is included in the light emission control data signal DAin. The PWM generation signal is a signal in which the base clock is activated for a period corresponding to the number of bits of the PWM control value after the start code signal is included in the light emission control data signal DAin.

[0024] If IC12 of pixel unit 2 does not detect a start code signal at the rising edge of the clock signal CKSin, it acquires the PWM control data represented by the light emission control data signal DAin based on the acquisition instruction signal included in the clock signal CKSin. IC12 then stores this PWM control data. As a result, each IC12 stores the PWM control data sequentially, row by row.

[0025] When the IC 12 detects a start code signal at the rising edge of the clock signal CKSin, it generates PWM control signals for causing each of the LEDs 11-1 to 11-3 to emit light, using the PWM generation signal included in the clock signal CKSin and the stored PWM control data. Each of the LEDs 11-1 to 11-3 emits light based on this PWM control signal.

[0026] As described above, in the LED display 1, each pixel unit 2 is actively driven using the matrix wiring composed of the column wiring 4 and the row wiring 6 arranged in a matrix.

[0027] <Configuration Example of the Logic Circuit of the IC> FIG. 2 is a diagram showing a configuration example of the logic circuit of the IC 12 in FIG. 1.

[0028] The logic circuit of the IC 12 includes a shift register 31, a header detection circuit 32, a counter 33, a PWM control circuit 34, and a reset control circuit 35.

[0029] The shift register 31 receives the light emission control data signal DAin via the column wiring 4 from the column drive circuit 3 in FIG. 1, and also receives the clock signal CKSin via the row wiring 6 from the row drive circuit 5. The shift register 31 also receives the header represented by the light emission control data signal DAin from the header detection circuit 32.

[0030] When the header is 1, the shift register 31 acquires the PWM control data represented by the data signal of the light emission control data signal DAin based on the acquisition instruction signal included in the clock signal CKSin. The shift register 31 has 16-bit registers 41-1 to 41-4.

[0031] The shift register 31 stores the 16 bits from the 63rd to the 48th bit of the 64-bit PWM control data, i.e., the header and the control value of IC 12, in a 16-bit register 41-1. This control value of IC 12 is used to control IC 12. The shift register 31 also stores the 16 bits from the 47th to the 32nd bit of the 64-bit PWM control data, i.e., the PWM control value of the red LED 11-1, in a 16-bit register 41-2.

[0032] The shift register 31 stores the 16 bits from the 31st to the 16th bit of the 64-bit PWM control data, i.e., the PWM control value of the green LED 11-2, in the 16-bit register 41-3. The shift register 31 stores the 16 bits from the 15th to the 0th bit of the 64-bit PWM control data, i.e., the PWM control value of the blue LED 11-3, in the 16-bit register 41-4.

[0033] The header detection circuit 32 receives the light emission control data signal DAin from the column drive circuit 3 via the column wiring 4, and the clock signal CKSin from the row drive circuit 5 via the row wiring 6. The header detection circuit 32 uses the clock signal CKSin to detect the header represented by the light emission control data signal DAin at the rising edge of the clock signal CKSin. The header detection circuit 32 supplies this header to the shift register 31, counter 33, PWM control circuit 34, and reset control circuit 35.

[0034] The counter 33 receives the clock signal CKSin from the row drive circuit 5 via the row wiring 6. The counter 33 is a 16-bit counter. When the header supplied from the header detection circuit 32 is 0, i.e., when the start code signal is detected, the counter 33 starts counting the base number of clock cycles of the clock signal CKSin. The counter 33 then supplies the count value of the base number of clock cycles of the PWM generation signal, which has been counted in this way, to the PWM control circuit 34. The counter 33 is reset when a reset signal is supplied from the reset control circuit 35 to instruct a reset.

[0035] The PWM control circuit 34 includes PWM generation circuits 50-1 to 50-3. When the header supplied from the header detection circuit 32 is 0, that is, when a start code signal is detected, the PWM control circuit 34 causes each of the PWM generation circuits 50-1 to 50-3 to start generating a PWM control signal.

[0036] When the PWM generation circuit 50-1 starts generating a PWM control signal, it reads the PWM control value stored in the register 41-2. The PWM generation circuit 50-1 generates a PWM control signal whose pulse width is the period from when the count value supplied from the counter 33 goes from 0 to the PWM control value, and outputs it to a subsequent analog circuit (not shown). Based on the PWM control signal, this analog circuit supplies a predetermined current value to the LED 11-1 for the duration of the pulse width of the PWM control signal.

[0037] When the PWM generation circuit 50-2 starts generating a PWM control signal, it reads the PWM control value stored in the register 41-3. The PWM generation circuit 50-2 generates a PWM control signal whose pulse width is the period from when the count value supplied from the counter 33 is zero until it reaches the PWM control value, and outputs it to a subsequent analog circuit (not shown). Based on the PWM control signal, this analog circuit supplies a predetermined current value to the LED 11-2 for the duration of the pulse width of the PWM control signal.

[0038] When the PWM generation circuit 50-3 starts generating a PWM control signal, it reads the PWM control value stored in the register 41-4. The PWM generation circuit 50-3 generates a PWM control signal whose pulse width is the period from when the count value supplied from the counter 33 goes from 0 to the PWM control value, and outputs it to a subsequent analog circuit (not shown). Based on the PWM control signal, this analog circuit supplies a predetermined current value to the LED 11-3 for the duration of the pulse width of the PWM control signal.

[0039] In the following, unless there is a need to distinguish between LEDs 11-1 to 11-3, they will simply be referred to as LED 11.

[0040] The reset control circuit 35 is supplied with a Power On Reset (POR) signal from the POR generation circuit 36, which instructs the system to reset when the power is turned on. When the POR signal is supplied, or when the header supplied from the header detection circuit 32 is 0, the reset control circuit 35 supplies a reset signal to the counter 33.

[0041] The POR generation circuit 36 ​​detects the rising edge of the power supply voltage VDD of IC 12. When the POR generation circuit 36 ​​detects the rising edge of the power supply voltage VDD of IC 12, it generates a POR signal and supplies it to the reset control circuit 35.

[0042] <Explanation of each signal in the IC> Figure 3 is a timing chart explaining the light emission control data signal DAin and the clock signal CKSin, which are input to IC 12 in Figure 2, as well as the PWM control signal generated by IC 12.

[0043] In Figure 3, the clock signal CKSin input from row wiring 6 in the i-th row from the top (i=0,1,...,m) is labeled as clock signal CKSin[i].

[0044] As shown in Figure 3, the frame-by-frame light emission control data signal DAin, input from the column wiring 4 of a given column, first contains data signals representing the 64-bit PWM control data of each pixel unit 2 in that column, starting from row 0 from the top. Following the data signals, a start code signal is included.

[0045] The frame-by-frame clock signal CKSin[0] first contains an acquisition instruction signal consisting of 64 basic clocks for a period representing the 64-bit PWM control data of the pixel unit 2 in the 0th row from the top, which is the data signal of the light emission control data signal DAin. Next, after the light emission control data signal DAin contains a start code signal, it contains a PWM generation signal consisting of basic clocks for a period corresponding to the number of bits in the PWM control value. Here, since the number of bits in the PWM control value is 16 bits, the number of basic clocks in the PWM generation signal is 65536 (=2 16 )

[0046] The frame-by-frame clock signal CKSin[1] first includes an acquisition instruction signal consisting of 64 basic clocks for a period representing the 64-bit PWM control data of the pixel unit 2 in the first row from the top, which is the data signal of the light emission control data signal DAin. Next, similar to the clock signal CKSin[1], the light emission control data signal DAin includes a start code signal followed by a PWM generation signal consisting of 65536 basic clocks.

[0047] Although not shown in the diagram, the frame-level clock signal CKSin[i] for the third row and subsequent rows similarly includes an acquisition instruction signal consisting of 64 fundamental clocks from the pixel unit 2 of that row and a PWM generation signal consisting of 65536 fundamental clocks.

[0048] As described above, the frame-by-frame clock signal CKSin[i] includes the base clock except for the period between the end of the acquisition instruction signal and the start of the PWM generation signal. If the LED display 1 has several to several dozen pixel units 2, the period during which the base clock is not included is, for example, about 10% of the frame duration.

[0049] When the light emission control data signal DAin and the clock signal CKSin[i] are input as described above, the counter 33 starts counting based on the start code signal, and the PWM control circuit 34 starts generating a PWM control signal. As a result, a PWM control signal is generated in which the pulse width is the period from when the count value counted by the counter 33 reaches the PWM control value of the LED 11.

[0050] By the way, IC12's counter 33 needs to count 65,536 basic clocks within the time remaining after subtracting the time spent writing PWM control data from the duration of one frame. Here, the frame rate of typical video such as television broadcasts is 60Hz, and high-definition video can have frame rates of 120Hz or higher. Therefore, even if the time spent writing PWM control data is 0, if the frame rate is 60Hz, the operating frequency of counter 33 needs to be 3.93MHz (=60Hz × 65536) or higher. If the frame rate is 120Hz, the operating frequency of counter 33 needs to be 7.86MHz (=120Hz × 65536) or higher. If we assume that the time spent writing PWM control data is 10% of the duration of one frame, the operating frequency of counter 33 will be even higher. For example, if the frame rate is 120Hz, the operating frequency of counter 33 needs to be 8.74MHz (=120Hz / 0.9 × 65536) or higher.

[0051] On the other hand, the power consumption of the logic circuit of IC 12 is proportional to the on / off drive per unit time, i.e., the operating frequency, assuming the same IC process rule (e.g., 160nm), power supply voltage, and circuit configuration. Therefore, when the operating frequency of counter 33 is high, the power consumption of counter 33 increases.

[0052] Furthermore, the wiring that inputs the clock signal CKSin to the shift register 31, the header detection circuit 32, and the counter 33, and the wiring that inputs the count value to the PWM generation circuits 50-1 to 50-3, respectively, is called a clock tree. This clock tree is wiring that supplies the base clock or a signal synchronized with the base clock, and buffers and the like are arranged to control the amount of wiring delay, etc. Therefore, since these buffers and the like also operate with the base clock, if the operating frequency of the counter 33, i.e., the frequency of the base clock, is high, the power consumption of these buffers and the like will also be high.

[0053] As a result, the power consumption of the logic circuit of IC12 will be large. The LED display 1 has an IC12 for each pixel unit 2. Therefore, even if the power consumption of the logic circuit per IC12 is only 40uW, if the number of pixels of the LED display 1 is approximately 2 million pixels consisting of 1920 x 1080 pixels, i.e., Full HD, the power consumption of the logic circuit of the entire LED display 1 will be 80W (= 40μW x 200 x 10 4 This 80W will be generated continuously while the display is active. In reality, the power consumption of IC12 is greater than 80W because it is the sum of the power consumption of the logic circuit and the power consumption of the analog circuit that supplies current to each LED11.

[0054] <2. Active-Drive LED Display Using Single Wiring> <Example of LED Display Configuration> Figure 4 shows an example of an LED display configuration using active-drive technology with single wiring.

[0055] In Figure 4, the parts of the LED display 51 that correspond to the LED display 1 in Figure 1 are given the same reference numerals. Therefore, the explanation of those parts will be omitted as appropriate, and the explanation will focus on the parts that differ from the LED display 1.

[0056] The LED display 51 in Figure 4 comprises a plurality of pixel units 52, a column drive circuit 53, column wiring 54, power supply voltage wiring 55, and ground voltage wiring 56. The LED display 51 drives each pixel unit 52 using an active drive method.

[0057] Specifically, the pixel units 52 are arranged in a matrix in the LED display 51. Each pixel unit 52 includes LEDs 11-1 to 11-3 and an IC 62 having a light emission control circuit that controls the light emission of the LEDs 11-1 to 11-3. Column wiring 54 corresponding to the row of the pixel unit 52 is daisy-chained to the IC 62 of each pixel unit 52. Power supply voltage wiring 55 and ground voltage wiring 56, which are arranged parallel to the column wiring 54 and corresponding to the row of the pixel unit 52, are also connected to the IC 62 of each pixel unit 52.

[0058] The column drive circuit 53 is connected to the column wiring 54, power supply voltage wiring 55, and ground voltage wiring 56, which are arranged for each column of the pixel unit 52. The column drive circuit 53 generates a data clock signal DCKin for each column of the pixel unit 52 on a frame-by-frame basis and supplies it to the pixel unit 52 via the column wiring 54 of that column.

[0059] The data clock signal DCKin is a signal synchronized with the base clock. The data clock signal DCKin is input from an external source and includes a data pulse train in which PWM control data for each pixel unit 52 in the column corresponding to the data clock signal DCKin is superimposed on the base clock, and a PWM generation signal, all in a time-division multiplexed manner.

[0060] Furthermore, the data clock signal DCKin includes a start instruction value in the control value of IC 52 of the PWM control data for the pixel unit 52 furthest from the column drive circuit 53, which indicates the start of the PWM generation signal. The start instruction value is, for example, 1 when it indicates a start instruction, and 0 when it does not. Only the header of the PWM control data for the pixel unit 52 closest to the column drive circuit 53 is set to 1 to indicate that PWM control data follows this header, while the headers of the PWM control data for the pixel units 52 in other rows are set to 0 as a dummy value.

[0061] The column drive circuit 53 also supplies a power supply voltage VDD to the pixel unit 52 of each column via the power supply voltage wiring 55 for that column. The column drive circuit 53 also supplies a ground voltage GND to the pixel unit 52 of each column via the ground voltage wiring 56 for that column.

[0062] As described above, the IC 62 of the pixel unit 52 is daisy-chained with the column wiring 54. Therefore, the data clock signal DCKin is supplied to each IC 62 of the pixel units 52 arranged in the column direction, starting from the one closest to the column drive circuit 53, and is transmitted in the column direction like a bucket brigade.

[0063] Specifically, IC 62 acquires and stores PWM control data that includes a header set to 1, which is superimposed on the data clock signal DCKin input from the column drive circuit 53 or IC 62 connected to it, whichever is closer to the column drive circuit 53. Then, IC 62 changes the header of the next PWM control data of the PWM control data to 1, and inputs the modified data clock signal DCKin to the column drive circuit 53 or IC 62 connected to it, whichever is further away from the column drive circuit 53. In this way, each IC 62 of the pixel units 52 arranged in the column direction acquires and stores PWM control data in order from the one closest to the column drive circuit 53.

[0064] When IC62 detects 1 as the start instruction value superimposed on the data clock signal DCKin, it then uses the PWM generation signal included in the data clock signal DCKin and the stored PWM control data to generate PWM control signals for each LED 11.

[0065] As described above, in the LED display 51, each pixel unit 52 is actively driven using a single row wiring 54. Therefore, the LED display 51 can reduce the number of wirings compared to the LED display 1. Note that the pixel units can also be driven using three wirings instead of matrix wiring or single wiring.

[0066] <Example of IC logic circuit configuration> Figure 5 shows an example of the logic circuit configuration of IC 62 in Figure 4.

[0067] In the logic circuit of IC62 in Figure 5, the parts corresponding to the logic circuit of IC12 in Figure 2 are given the same reference numerals. Therefore, explanations of those parts will be omitted as appropriate, and the explanation will focus on the parts that differ from IC12.

[0068] The logic circuit of IC62 includes a PWM control circuit 34, a POR generation circuit 36, a signal detection circuit 81, a header control circuit 82, a serial / parallel conversion circuit 83, registers 84-1 to 84-4, a counter 85, and a reset control circuit 86.

[0069] The signal detection circuit 81 receives the data clock signal DCKin from the column drive circuit 53 in Figure 4 via the column wiring 54. The signal detection circuit 81 detects the header superimposed on the data clock signal DCKin and supplies it to the header control circuit 82. The signal detection circuit 81 detects the PWM control data superimposed on the data clock signal DCKin, which includes a header set to 1, and supplies it to the serial / parallel conversion circuit 83. The signal detection circuit 81 detects the start instruction value of the PWM control data for the last m-th row of pixel unit 52, which includes a header set to 0, superimposed on the data clock signal DCKin, and supplies it to the serial / parallel conversion circuit 83. The signal detection circuit 81 supplies the data clock signal DCKin to the counter 85.

[0070] The signal detection circuit 81, when a header is set to 1, changes the next header to 1 and outputs the data clock signal DCKin from the changed header onward as the data clock signal DCKout to the column wiring 54. This data clock signal DCKout is input as the data clock signal DCKin to the IC 62 that is furthest from the column drive circuit 53 connected to its own IC 62 via the column wiring 54.

[0071] The header control circuit 82, when the header supplied from the signal detection circuit 81 is 1, supplies a notification signal to the serial / parallel conversion circuit 83 to inform it that the header is 1.

[0072] When a notification signal is supplied from the header control circuit 82, the serial / parallel conversion circuit 83 converts the 64-bit serial PWM control data supplied from the signal detection circuit 81 into 16-bit parallel PWM control data.

[0073] The serial / parallel conversion circuit 83 stores 16 bits of data from the 63rd to the 48th bit of the 64-bit PWM control data, i.e., the header and the control value of IC 62, in a 16-bit register 84-1. This control value of IC 62 is used to control IC 62. The serial / parallel conversion circuit 83 also stores 16 bits of data from the 47th to the 32nd bit of the 64-bit PWM control data, i.e., the PWM control value of the red LED 11-1, in a 16-bit register 84-2. This PWM control value is read out by the PWM generation circuit 50-1.

[0074] The serial / parallel conversion circuit 83 stores the 16 bits from the 31st to the 16th bit of the 64-bit PWM control data, i.e., the PWM control value for the green LED 11-2, in a 16-bit register 84-3. This PWM control value is read out by the PWM generation circuit 50-2. The serial / parallel conversion circuit 83 also stores the 16 bits from the 15th to the 0th bit of the 64-bit PWM control data, i.e., the PWM control value for the blue LED 11-3, in a 16-bit register 84-4. This PWM control value is read out by the PWM generation circuit 50-3.

[0075] The serial / parallel conversion circuit 83 updates the start instruction value stored in register 84-1 by supplying the start instruction value supplied from the signal detection circuit 81 to register 84-1.

[0076] Counter 85 is a 16-bit counter. Counter 85 reads the start instruction value from the control value of IC 62 stored in register 84-1. If the start instruction value is 1, Counter 85 starts counting the number of basic clock cycles of the data clock signal DCKin supplied from the signal detection circuit 81. Counter 85 then supplies the counted number of basic clock cycles of the PWM generation signal to the PWM generation circuits 50-1 to 50-3. Counter 85 is reset when a reset signal is supplied from the reset control circuit 86.

[0077] The reset control circuit 86 is supplied with a POR signal from the POR generation circuit 36. The reset control circuit 35 reads the start instruction value stored in register 84-1. If a POR signal is supplied, or if the start instruction value is 1, the reset control circuit 35 supplies a reset signal to the counter 85.

[0078] <Explanation of each signal in the IC> Figure 6 is a timing chart that explains the data clock signal DCKin input to IC 62 in Figure 5 and the PWM control signal generated by IC 62.

[0079] In Figure 6, the data clock signal DCKin input via column wiring 54 to IC 62 of the i-th pixel unit 52 closest to the column drive circuit 53, i.e., the i-th row from the top, is labeled as data clock signal DCKin[i]. IC 62 of the i-th row from the top pixel unit 52 is labeled as IC[i].

[0080] As shown in Figure 6, the frame-unit data clock signal DCKin[0] input to IC[0] from the column wiring 54 of a certain column first contains a data pulse sequence in which the PWM control data of each pixel unit 52 in each row is superimposed on the basic clock, starting from row 0 of the column.

[0081] Furthermore, the header of the PWM control data for the pixel unit 52 in the 0th row of this data clock signal DCKin[0] is set to 1, while the headers of the PWM control data for the pixel unit 52 in the other rows are set to 0. The control value IC[m] of the PWM control data for the last row, the mth row, contains the start instruction value. The frame-by-frame data clock signal DCKin[0] includes a PWM generation signal consisting of 65536 basic clocks corresponding to the number of bits in the PWM control value, following the data pulse train.

[0082] In the frame-unit data clock signal DCKin[1], which is output from IC[0] and input to IC[1] via column wiring 54, the basic clock superimposed with the PWM control data of the pixel unit 52 in the 0th row from the top is removed. Also, in the frame-unit data clock signal DCKin[1], the header of the PWM control data of the pixel unit 52 in the 1st row from the top is 1. Otherwise, it is the same as the data clock signal DCKin[0].

[0083] Although not shown in the diagram, the frame-by-frame data clock signal DCKin[i] for subsequent rows also contains a data pulse sequence superimposed on the basic clock for the PWM control data of the pixel unit 52 for the row following that row, as well as a signal for PWM generation. The header for the PWM control data of that row is 1.

[0084] When a frame-based data clock signal DCKin[i] as described above is input, the counter 85 starts counting based on the start instruction value, and the PWM control circuit 34 starts generating a PWM control signal. This generates a PWM control signal whose pulse width is the period from when the count value counted by the counter 85 reaches the PWM control value of the LED 11.

[0085] In IC62's counter 85, similar to counter 33, it is necessary to count 65,536 basic clocks within the time remaining after deducting the time required to write PWM control data from the duration of one frame. Therefore, the operating frequency of counter 33 in LED display 51 is high, similar to that of LED display 1. Also, the operating frequency of the signal detection circuit 81, which operates at the frequency of the basic clock, i.e., the operating frequency of counter 33, is high. Consequently, the power consumption of counter 85 and signal detection circuit 81 is high.

[0086] Furthermore, the wiring that inputs the signal corresponding to the data clock signal DCKin[i] to the header control circuit 82, the serial / parallel conversion circuit 83, and the counter 85, as well as the wiring that inputs the count value to each of the PWM generation circuits 50-1 to 50-3, constitutes a clock tree. As mentioned above, when the operating frequency of the counter 85 is high, the power consumption due to buffers and other components placed in this clock tree is also high.

[0087] As a result, the power consumption of the logic circuit of IC 62 increases. In the LED display 51, as with the LED display 1, each pixel unit 52 has an IC 62, so the power consumption of IC 62 has a significant impact on the overall power consumption of the LED display 51.

[0088] <3. First Embodiment> <Example of Display System Configuration> Figure 7 shows an example of the configuration of the first embodiment of a display system to which this technology is applied.

[0089] The following explanation uses the example of a display system having a large LED display composed of multiple display units arranged in a tile-like pattern, but this technology can also be applied to LED displays composed of a single display unit. Furthermore, this technology can also be applied to OLED (Organic Light Emitting Diode) displays and liquid crystal displays that use LEDs as backlights.

[0090] The display system 110 in Figure 7 consists of a PC (personal computer) 111, a video server 112, a video wall controller 113, and a video wall 114.

[0091] PC 111 is a general-purpose computer that accepts user input and supplies commands to the video wall controller 113 according to the operation.

[0092] The video server 112 consists of, for example, a server computer or a Blu-ray disc player, and supplies the video signal of each pixel of the video content to the video wall controller 113.

[0093] The video wall controller 113 controls the individual displays of the display units 121-1 to 121-n (where n is an integer of 2 or more) that make up the video wall 114 in accordance with commands supplied from the PC 111, and controls the video wall 114 as a whole to display a single image. Specifically, the video wall controller 113 applies predetermined signal processing to the video signal supplied from the video server 112, and distributes and supplies the resulting video signal to each of the display units 121-1 to 121-n.

[0094] In the following, when it is not necessary to distinguish between display units 121-1 to 121-n individually, they will simply be referred to as display unit 121.

[0095] As shown in the upper right of Figure 7, the video wall 114 is a large LED display in which display units 121-1 to 121-n, each consisting of an array of LED pixels, are arranged in a tile-like pattern. In the video wall 114, the images displayed by each individual display unit 121 are combined in a tile-like pattern to display a single image as a whole on the video wall 114.

[0096] The video wall controller 113 and the video wall 114 may be integrated into a single unit.

[0097] <Example Configuration of Video Wall Controller and Display Unit> Figure 8 shows an example configuration of the video wall controller 113 and display unit 121 shown in Figure 7.

[0098] The video wall controller 113 includes a LAN (Local Area Network) terminal 141, an HDMI (High Definition Multimedia Interface) (registered trademark) terminal 142, a DP (Display Port) terminal 143, and a DVI (Digital Visual Interface) terminal 144. The video wall controller 113 also includes a network interface 145, an MPU (Micro Processor Unit) 146, a signal input interface 147, a signal processing unit 148, a DRAM (Dynamic Random Access Memory) 149, a signal distribution unit 150, and output interfaces 151-1 to 151-n.

[0099] A PC 111 is connected to the LAN port 141 via a LAN cable.

[0100] The HDMI terminal 142, DP terminal 143, and DVI terminal 144 are all video signal input terminals and can be connected to the video server 112. In the example in Figure 8, the video server 112 is connected to the HDMI terminal 142.

[0101] The network interface 145 communicates with the PC 111 via LAN port 141. The network interface 145 supplies commands obtained from the PC 111 through this communication to the MPU 146. Note that LAN communication may also be performed wirelessly.

[0102] The MPU 146 supplies control signals to the signal processing unit 148 in response to commands supplied from the network IF 145.

[0103] The signal input interface 147 acquires a video signal via the HDMI terminal 142, DP terminal 143, or DVI terminal 144 connected to the video server 112, and supplies it to the signal processing unit 148.

[0104] The signal processing unit 148 adjusts the color temperature, contrast, brightness, etc., of the video signal supplied from the signal input IF 147 based on the control signals supplied from the MPU 146, and supplies them to the signal distribution unit 150. At this time, the signal processing unit 148 stores and reads intermediate processing results and processing results from the DRAM 149 as needed.

[0105] The signal distribution unit 150 distributes and supplies the video signal supplied from the signal processing unit 148 to the output IFs 151-1 to 151-n, which correspond to the display units 121-1 to 121-n. In the following, unless there is a need to distinguish between the output IFs 151-1 to 151-n, they will simply be referred to as output IF 151.

[0106] Output IF 151 supplies the video signal supplied from the signal distribution unit 150 to the display unit 121 corresponding to it.

[0107] The display unit 121 includes a driver control unit 161 and LED array panels 162-1 to 162-N.

[0108] The driver control unit 161 includes a signal input IF 171, a signal processing unit 172, and output IFs 173-1 to 173-N (where N is an integer of 1 or more).

[0109] The signal input IF 171 acquires the video signal supplied from the output IF 151 and supplies it to the signal processing unit 172.

[0110] The signal processing unit 172 has a color lookup table for its own display unit 121. The signal processing unit 172 refers to its color lookup table and applies color and brightness corrections to the video signal of each pixel supplied from the signal input IF 171, and converts the corrected video signal into PWM control data. The signal processing unit 172 divides the PWM control data for each pixel into PWM control data for one of the LED array panels 162-1 to 162-N, which include the pixel unit corresponding to that pixel. The signal processing unit 172 supplies the PWM control data for each of the LED array panels 162-1 to 162-N to the respective output IFs 173-1 to 173-N corresponding to each of the LED array panels 162-1 to 162-N.

[0111] In the following, if there is no need to distinguish between output IFs 173-1 to 173-N, they will simply be referred to as output IF 173. Similarly, if there is no need to distinguish between LED array panels 162-1 to 162-N, they will simply be referred to as LED array panel 162.

[0112] The LED array panel 162 comprises a plurality of pixel units arranged in a matrix (array). Each pixel unit includes three LEDs that emit red, green, and blue light, respectively, and an IC that has a light emission control circuit for PWM control of the light emission of the LEDs. The LED array panel 162 PWM controls the light emission of the LEDs of each pixel unit based on the PWM control data for each pixel unit supplied from the output IF 173.

[0113] <Example of LED array panel configuration> Figure 9 shows an example of the configuration of the LED array panel 162 shown in Figure 8.

[0114] In the LED array panel 162 of Figure 9, the parts corresponding to the LED display 1 in Figure 1 are given the same reference numerals. Therefore, the explanation of those parts will be omitted as appropriate, and the explanation will focus on the parts that differ from the LED display 1.

[0115] The LED array panel 162 differs from the LED display 1 in that PWM control data is input to the column drive circuit 3 from the output IF 173, and the pixel unit 2 and row drive circuit 5 are replaced by the pixel unit 182 and row drive circuit 185. Otherwise, it is configured the same as the LED display 1.

[0116] In the LED array panel 162, each pixel unit 182 is actively driven using matrix wiring consisting of column wiring 4 and row wiring 6.

[0117] Pixel unit 182 differs from pixel unit 2 in that it includes IC 192 instead of IC 12, but otherwise it is configured the same as pixel unit 2. The configuration of IC 192 will be described later with reference to Figures 10 and 17. Similar to IC 12, column wiring 4 and row wiring 6, as well as the power supply voltage VDD and ground voltage GND, are connected to IC 192.

[0118] The row drive circuit 185 is connected to the row wiring 6 of each row of the pixel unit 182. The row drive circuit 185 (clock signal generation unit) generates the clock signal NCKSin for each row of the pixel unit 182 on a frame-by-frame basis and supplies it to the pixel unit 182 via the row wiring 6 of that row.

[0119] The clock signal NCKSin differs from the clock signal CKSin in that the PWM generation signal is replaced by a generation pulse train consisting of a start pulse and pulses for PWM generation; otherwise, it is configured similarly to the clock signal CKSin.

[0120] The start pulse (PWM Start Pulse) is a pulse that indicates the start of the generation pulse train and is included between the acquisition instruction signal and the generation pulse train. The timing of the start pulse generation can be any timing between the acquisition instruction signal and the generation pulse train. For example, by setting the timing of the start pulse so that the illumination time of the LED 11 is maximized, power efficiency can be improved.

[0121] The generation pulse train consists of multiple pulses synchronized with the base clock and corresponding to the number of bits in the PWM control value, and is used to generate the PWM control signal. Specifically, the generation pulse train consists of a lower pulse train (first pulse train) consisting of pulses with pulse widths corresponding to each bit of the lower bits (first bit group) of the PWM control value, and an upper pulse train (second pulse train) consisting of pulses with a predetermined pulse width representing the maximum number of pulses expressed by the upper bits (second bit group) of the PWM control value.

[0122] Here, the 16-bit PWM control value is divided into the lower 8 bits and the upper 8 bits. The pulse width of the pulse corresponding to the j-th bit (j=0,1,...7) from the least significant bit in the lower pulse train is 2 times the fundamental clock. j It is doubled, and the pulse width of each pulse in the upper pulse train is twice that of the base clock. 8 It is doubled. That is, the generation pulse train is twice the base clock. j A lower pulse train consisting of eight pulses, each with twice the pulse width, and 2 8255 pulses with double pulse width (= 2 8 -1) and the upper pulse train consisting of these pulses.

[0123] Thus, the total of the pulse width of each pulse in the lower pulse train and the pulse width of each pulse in the upper pulse train is 65535 (= 2 0 + 2 1 + 2 2 + 2 3 + 2 4 + 2 5 + 2 6 + 2 7 + 2 8 × (2 8 -1)) times the pulse width. The PWM control signal corresponding to the lower 8-bit value of the PWM control value can be generated by extracting a predetermined pulse from the lower pulse train. The PWM control signal corresponding to the upper 8-bit value of the PWM control value can be generated by extracting a predetermined number of pulses from the upper pulse train. The PWM control signal generated in this way can also be said to be a PDM control signal in which the pulse density changes.

[0124] When the IC 192 of the pixel unit 182 does not detect the start code signal at the rising edge of the clock signal NCKSin, the IC 192 uses the acquisition instruction signal included in the clock signal NCKSin to acquire the PWM control data represented by the data signal of the light emission control data signal DAin. Then, the IC 192 stores the PWM control data. As a result, the PWM control data is sequentially stored in each IC 192 in row units.

[0125] When the IC 192 detects the start code at the rising edge of the clock signal NCKSin, that is, when the start code is detected at the rising edge of the start pulse, the IC 192 starts generating the PWM control signal for each LED 11. Specifically, in this case, for each LED 11, the IC 192 starts generating the PWM control signal by extracting a predetermined pulse from the pulse train for generation included in the clock signal NCKSin after the start pulse based on the stored PWM control data. Each LED 11 emits light based on this PWM control signal.

[0126] <First example of IC logic circuit configuration> Figure 10 shows a first example of the logic circuit configuration of IC192 shown in Figure 9.

[0127] In the logic circuit of IC192 in Figure 10, the parts corresponding to the logic circuit of IC12 in Figure 2 are given the same reference numerals. Therefore, explanations of those parts will be omitted as appropriate, and the explanation will focus on the parts that differ from the logic circuit of IC12.

[0128] The logic circuit of IC192 differs from that of IC12 in that counter 33, PWM control circuit 34, and reset control circuit 35 are replaced by counter 211, PWM control circuit 212, and reset control circuit 213. The logic circuit of IC192 also differs from that of IC12 in that the clock signal CKSin is replaced by the clock signal NCKSin. Otherwise, it is configured the same as the logic circuit of IC12.

[0129] The counter 211 receives the clock signal NCKSin from the row drive circuit 185 via the row wiring 6. The counter 211 is an 8-bit counter. When the header supplied from the header detection circuit 32 is 0, the counter 211 (counting unit) starts counting the number of pulses in the upper pulse sequence included in the clock signal NCKSin. The counter 211 supplies the resulting count value to the PWM control circuit 212. The counter 211 is reset when a reset signal is supplied from the reset control circuit 213.

[0130] The PWM control circuit 212 includes PWM generation circuits 221-1 to 221-3. The PWM control circuit 212 is supplied with a header from the header detection circuit 32. If the header is 0, the PWM control circuit 212 causes each of the PWM generation circuits 221-1 to 221-3 to start generating a PWM control signal.

[0131] The PWM generation circuit 221-1 (light emission control signal generation unit) includes an upper bit processing circuit 231-1, a lower bit processing circuit 232-1, and an AND circuit 233-1.

[0132] When the upper bit processing circuit 231-1 starts generating a PWM control signal, it reads the upper 8 bits of the 16-bit PWM control value stored in register 41-2. The upper bit processing circuit 231-1 generates an upper bit extraction instruction signal that is turned on only for the period from when the count value supplied from counter 33 reaches the value represented by its upper 8 bits, and supplies it to the AND circuit 233-1.

[0133] The lower bit processing circuit 232-1 receives the clock signal NCKSin from the row drive circuit 185 via the row wiring 6. When the lower bit processing circuit 232-1 starts generating the PWM control signal, it reads the value of the lower 8 bits of the 16-bit PWM control value stored in register 41-2. Based on the value of each of the lower 8 bits and the clock signal NCKSin, the lower bit processing circuit 232-1 generates a lower bit extraction instruction signal. This lower bit extraction instruction signal is turned on when the clock signal NCKSin contains a pulse corresponding to a bit that is 1 among the lower 8 bits, and turned off when it contains a pulse corresponding to a bit that is 0. The lower bit processing circuit 232-1 supplies this lower bit extraction instruction signal to the AND circuit 233-1. The configuration of the lower bit processing circuit 232-1 will be described later with reference to Figure 11.

[0134] The AND circuit 233-1 receives the clock signal NCKSin from the row drive circuit 185 via the row wiring 6. Based on the upper bit extraction signal and the lower bit extraction signal, the AND circuit 233-1 generates a PWM control signal by extracting a predetermined pulse from the generation pulse train contained in the clock signal NCKSin.

[0135] Specifically, the AND gate 233-1 extracts pulses from the generation pulse train when the upper bit extraction signal or the lower bit extraction signal is turned on, and generates them as PWM control signals. For example, if the upper 8 bits of the PWM control value are all 1, then the pulses from 0 to 255, i.e., all pulses in the upper pulse train, are extracted as the upper bit PWM control signals. On the other hand, if the upper 8 bits of the PWM control value are 0, 0, 1, 1, 1, 1, 1, 1 in order from the most significant bit, then the pulses from 0 to 63, i.e., 64 pulses in the upper pulse train, are extracted as the upper bit PWM control signals.

[0136] The generated PWM control signal is output to a subsequent analog circuit (not shown). This analog circuit supplies a predetermined current to LED 11-1 for a duration equal to the pulse width of each pulse of the PWM control signal. As a result, LED 11-1 lights up for a duration corresponding to the sum of the pulse widths of each pulse of the PWM control signal.

[0137] The PWM generation circuit 221-2 includes a high-order bit processing circuit 231-2, a low-order bit processing circuit 232-2, and an AND gate 233-2. The processing of the PWM generation circuit 221-2 is the same as that of the PWM generation circuit 221-1, except that the PWM control value is read from register 41-3, so a detailed explanation is omitted. Based on the PWM control signal generated by the PWM generation circuit 221-2, a current of a predetermined value is supplied to the LED 11-2 for a period equal to the pulse width of each pulse of the PWM control signal. As a result, the LED 11-2 lights up for a time corresponding to the sum of the pulse widths of each pulse of the PWM control signal.

[0138] The PWM generation circuit 221-3 includes a high-order bit processing circuit 231-3, a low-order bit processing circuit 232-3, and an AND gate 233-3. The processing of the PWM generation circuit 221-3 is the same as that of the PWM generation circuit 221-1, except that the PWM control value is read from register 41-4, so a detailed explanation is omitted. Based on the PWM control signal extracted by the PWM generation circuit 221-3, a current of a predetermined value is supplied to the LED 11-3 for a period equal to the pulse width of each pulse of the PWM control signal. As a result, the LED 11-3 lights up for a time corresponding to the sum of the pulse widths of each pulse of the PWM control signal.

[0139] The reset control circuit 213 is supplied with a POR signal from the POR generation circuit 36. When the POR signal is supplied, the reset control circuit 213 supplies a reset signal to the counter 33. The reset control circuit 213 receives the light emission control data signal DAin from the column drive circuit 3 via the column wiring 4, and the clock signal NCKSin from the row drive circuit 185 via the row wiring 6. The reset control circuit 213 uses the clock signal NCKSin to obtain the header represented by the light emission control data signal DAin. If the header is 0, the reset control circuit 213 supplies a reset signal to the counter 33.

[0140] Alternatively, instead of the reset control circuit 213 acquiring the header, the header may be supplied to the reset control circuit 213 from the header detection circuit 32.

[0141] <Example of lower bit processing circuit configuration> Figure 11 shows an example of the configuration of the lower bit processing circuit 232-1 in Figure 10.

[0142] The lower bit processing circuit 232-1 in Figure 11 includes a selector 251 and a counter 252.

[0143] When the selector 251 starts generating a PWM control signal, it reads the lower 8 bits of the 16-bit PWM control value stored in register 41-2 in Figure 10. Each time the count value supplied by counter 252 increments by 1, the selector 251 targets each bit of the lower 8 bits in order from the least significant bit. The selector 251 generates a lower bit extraction instruction signal, which is turned off if the value of the target bit is 0 and on if it is 1, and supplies it to the AND circuit 233-1.

[0144] Counter 252 is a 4-bit counter. Counter 252 counts the number of pulses in the pulse train used to generate the clock signal NCKSin, which is input via the row wiring 6, from 0 to 7, starting from the beginning. Counter 252 supplies the resulting 3-bit count value to the selector 251. Although not shown in the diagram, a reset signal is also supplied to this counter 252 from the reset control circuit 213. When the reset signal is supplied, counter 252 resets itself.

[0145] The configurations of the lower bit processing circuits 232-2 and 232-3 are the same as those of the lower bit processing circuit 232 in Figure 11, so their explanation will be omitted. Hereafter, unless there is a need to distinguish between the lower bit processing circuits 232-1 to 232-3, they will simply be referred to as the lower bit processing circuit 232. Unless there is a need to distinguish between the registers 41-1 to 41-3, they will simply be referred to as the register 41.

[0146] <Explanation of the first example of each signal in the IC> Figure 12 is a timing chart illustrating the light emission control data signal DAin and the clock signal NCKSin, which are input to IC 192 in Figure 10, as well as the PWM control signal generated by IC 192.

[0147] In Figure 12, the clock signal NCKSin input from the i-th row (i=1, ..., m) row wiring 6 is labeled as clock signal NCKSin[i]. This is also the case in Figure 18, which will be discussed later.

[0148] The light emission control data signal DAin in Figure 12 is identical to the light emission control data signal DAin in Figure 3, so its explanation is omitted.

[0149] The frame-by-frame clock signal NCKSin[0] in Figure 12 differs from the frame-by-frame clock signal CKSin[0] in Figure 3 in that it includes a start pulse and a generation pulse train instead of a PWM generation signal. Otherwise, it is the same as the frame-by-frame clock signal CKSin[0].

[0150] Specifically, the frame-unit clock signal NCKSin[0] includes an acquisition instruction signal, similar to the frame-unit clock signal CKSin[0] in Figure 3. After the acquisition instruction signal, if the light emission control data signal DAin includes a start code signal, a start pulse is included. After this start pulse, the base clock is 2 j A lower pulse train consisting of eight pulses, each with twice the pulse width, and 2 8 The upper pulse train consists of 255 pulses, each with twice the pulse width, and is included in sequence. Here, the interval between each pulse in the generating pulse train is 1 times the base clock, but it may be an integer multiple of 2 or more.

[0151] Similarly, the frame-unit clock signal NCKSin[i] for the rows from the first row onwards also contains an acquisition instruction signal, followed by the start pulse, lower pulse sequence, and upper pulse sequence, just like the frame-unit clock signal CKSin[i] in Figure 3.

[0152] When the light emission control data signal DAin and the clock signal NCKSin[i] described above are input, if the start code is detected at the rising edge of the start pulse, the counter 211 starts counting and the PWM control circuit 212 starts generating the PWM control signal.

[0153] This first generates a lower 8-bit PWM control signal based on the lower 8-bit value of the PWM control value of LED 11. Specifically, this lower 8-bit PWM control signal is generated by extracting a pulse corresponding to a bit if the bit is 1, starting from the least significant bit of the lower 8 bits, and not extracting a pulse if the bit is 0.

[0154] In the example in Figure 12, the lower 8 bits of the PWM control value are 1, 0, 1, 1... from the least significant bit. Therefore, the PWM control signal for the 0th bit from the least significant bit, i.e., the least significant bit, is the fundamental clock of the lower pulse train, which is 1 (=2 0 A pulse with twice the pulse width is extracted. The PWM control signal for the first bit from the least significant bit is twice the fundamental clock (=2 1 Pulses with a pulse width ) times greater than the original pulse width are not being extracted. The second bit from the least significant bit is used as the PWM control signal, which is 4 (=2) times the original clock. 2 A pulse with a pulse width 8 times (=2) is extracted. The third bit from the least significant bit is used as the PWM control signal, which is 8 times (=2) of the base clock. 3 A pulse with a pulse width ) times greater is being extracted.

[0155] Next, the pulses from the period during which the count value of counter 211 reaches a value represented by the upper 8 bits of the PWM control value, i.e., the number of pulses from the upper pulse sequence represented by the upper 8 bits of the PWM control value, are extracted as the upper 8-bit PWM control signal.

[0156] Here, the clock signal NCKSin for each row must contain one frame's worth of clock signal NCKSin within one frame period (one vertical scan period). However, the counter 211 only needs to count 255 pulses included in the upper pulse train within the time obtained by subtracting the acquisition instruction signal period, i.e., the writing time of the PWM control data, from one frame period. Therefore, assuming, for example, that the writing time of the PWM control data is 0, even if the frame rate is 120 Hz, the operating frequency of the counter 211 only needs to be around 30 kHz (30600 Hz = 120 Hz × 255). Thus, the power consumption of the counter 211 is smaller than that of the counter 33 in Figure 2.

[0157] As a result, IC52 can reduce the power consumption of its logic circuits compared to IC12. For example, the power consumption of IC192's logic circuits is reduced to about 1 / 100 to 1 / 250 of that of IC12.

[0158] In addition, in IC52, the operating frequency of the shift register 31 is the frequency of the base clock, which is high, similar to IC12. However, the operating time of the shift register 31, i.e., the writing time of the PWM control data, is short.

[0159] For example, if the base clock frequency is 8.7MHz and the frame rate is 120Hz, the ratio of power consumption due to writing PWM control data to the total power consumption due to the entire light emission control for one frame is 0.09% (=7.4μs / 8.3ms). For example, if the base clock frequency is 10MHz and the frame rate is 120Hz, the ratio of power consumption due to writing PWM control data to the total power consumption due to the entire light emission control for one frame is 0.08% (=6.4μs / 8.3ms). Therefore, the power consumption of the shift register 31 is negligibly small in the total power consumption of IC 52.

[0160] <Detailed explanation of the first example of the clock signal NCKSin> Figure 13 is a diagram that provides a detailed explanation of the clock signal NCKSin[0] in Figure 12.

[0161] In the example shown in Figure 13, the frequency of the base clock is 10 MHz. Therefore, the instruction signal for acquiring the frame-unit clock signal NCKSin[0] consists of 64 10 MHz base clocks. Following this acquisition instruction signal, the frame-unit clock signal NCKSin[0] contains, in order, a start pulse, a lower pulse sequence, and a higher pulse sequence.

[0162] The frame-based clock signal NCKSin[0], constructed as described above, is generated within one frame period. The acquisition instruction signal is generated within the vertical blanking interval (V-BLK period).

[0163] <Explanation of the lower bit processing circuit> Figure 14 is a diagram illustrating the process by which the lower bit processing circuit 232 generates a PWM control signal for the lower bits.

[0164] If the lower 8 bits of the 16-bit PWM control value read from register 41 are all 1, then, as shown in Figure 14A, all pulses in the lower pulse train are extracted as the lower bit PWM control signal.

[0165] On the other hand, if the values ​​of each of the lower 8 bits are 1, 1, 1, 1, 0, 1, 0, 1 from the least significant bit, then, as shown in Figure 14B, the 1st to 4th, 6th, and 8th pulses from the beginning of the lower pulse sequence are extracted as the lower bit PWM control signals.

[0166] In the above explanation, the 16-bit PWM control value was divided into the upper 8 bits and the lower 8 bits, and an upper pulse train corresponding to the upper 8 bits and a lower pulse train corresponding to the lower 8 bits were generated. However, the method of dividing the bits of the PWM control value is not limited to this.

[0167] In other words, a 16-bit PWM control value can be divided into any upper L bits (where L is a positive integer) and lower M bits (M = 16 - L). In this case, the lower pulse train has a pulse width corresponding to each bit of the lower M bits that is a power of 2 of the base clock, with each of the M integers between 0 and M being exponents, i.e., 2 0 ,2 1 ,・・・,2 M-1 It consists of M pulses, which is double the original value. The higher bits are twice the value of the base clock. M (2) L -1) pulses. The larger the number of L, the larger the maximum count value of counter 211, and therefore the higher the power consumption of IC 52.

[0168] <Second example of the clock signal NCKSin signal> Figure 15 shows an example of the clock signal NCKSin[0] when L is 7 and M is 9.

[0169] As shown in Figure 15, the frame-by-frame clock signal NCKSin[0] in this case differs from the frame-by-frame clock signal NCKSin[0] in Figure 13 in that the upper and lower pulse trains are different. Otherwise, it is the same as the frame-by-frame clock signal NCKSin[0] in Figure 13.

[0170] Specifically, the lower pulse train in Figure 15 corresponds to each of the lower nine bits of the PWM control value, with each pulse having a width equal to 2 times the base clock. 0 ,2 1 ,・・・,2 8 It is twice that, eight pulses. The upper pulse train corresponds to the upper seven bits, twice the base clock. 9 127 (=2) pulse width double the pulse width 7 There are -1) pulses.

[0171] In the above explanation, the lower pulse sequence and upper pulse sequence included in the frame-unit clock signal NCKSin[0] were arranged in the order of lower pulse sequence followed by upper pulse sequence. However, they may also be arranged in the order of upper pulse sequence followed by lower pulse sequence. For example, as shown in Figure 16, the lower pulse sequence and upper pulse sequence included in the frame-unit clock signal NCKSin[0] in Figure 15 may be arranged in the order of upper pulse sequence followed by lower pulse sequence.

[0172] The order and division method of the lower pulse train and upper pulse train may be preset during the design of IC192, or an order setting value (order information) representing the order and a division setting value (division information) indicating the division method may be input to IC192 as control values ​​for IC192. When an order setting value or division setting value is input to IC192, the PWM control circuit 212 generates a PWM control signal by extracting predetermined pulses from the generated pulse train based on the order setting value and division setting value. In this case, the size of the PWM control circuit 212 will increase. The order and division method of the lower pulse train and upper pulse train may be changed, for example, to suppress the occurrence of black bars when reshooting with the video wall 114 as the background.

[0173] Note that the number of bits representing the brightness gradation of the LED 11 may be other than 16 bits; for example, it may be 17 bits. In this case as well, the 17-bit PWM control value can be divided into any number of upper and lower bits. For example, the 17-bit PWM control value can be divided into an upper 8 bits and a lower 9 bits.

[0174] <Second example of IC logic circuit configuration> Figure 17 shows a second example of the logic circuit configuration of IC192 in Figure 9.

[0175] Note that in IC192 in Figure 17, the same reference numerals are used for parts corresponding to IC192 in Figure 10. Therefore, explanations of those parts will be omitted as appropriate, and the explanation will focus on the parts that differ from IC192 in Figure 10. IC192 in Figure 17 differs from IC192 in Figure 10 in the configuration of the clock signal NCKSin and the addition of a DFF (Delay Flip Flop) 261; otherwise, it is configured the same as IC192 in Figure 10.

[0176] The clock signal NCKSin input to IC192 in Figure 17 differs from the clock signal NCKSin input to IC192 in Figure 10 in that each pulse in the generation pulse train is replaced by a trigger pulse that represents the beginning and end of the pulse width period of that pulse. Specifically, the clock signal NCKSin includes a period pulse train instead of a generation pulse train. The period pulse train consists of a lower period pulse train (first period pulse train) consisting of trigger pulses that represent the beginning and end of the pulse width period of each pulse in the lower pulse train, and an upper period pulse train (second period pulse train) consisting of trigger pulses that represent the beginning and end of the pulse width period of each pulse in the upper pulse train.

[0177] The pulse width of the trigger pulse is, for example, about 1 μS. In the following, the trigger pulse that marks the beginning of the pulse width will be referred to as the beginning trigger pulse, and the trigger pulse that marks the end will be referred to as the end trigger pulse.

[0178] The DFF 261 receives the clock signal NCKSin from the row drive circuit 185 via the row wiring 6. The DFF 261 is also supplied with a header from the header detection circuit 32. If the header supplied from the header detection circuit 32 is 0, the DFF 261 (generation pulse train generation unit) initializes and starts generating a generation pulse train from the period pulse train contained in the clock signal CKSin. The DFF 261 supplies the generated generation pulse train to the counter 211 and AND circuits 233-1 to 233-3.

[0179] Furthermore, a reset signal is supplied to the DFF 261 from the reset control circuit 213, and the DFF 261 is initialized in response to this reset signal. When the header is 0, or when a reset signal is supplied, the DFF 261 is initialized, enabling it to accurately generate the pulse train for generation.

[0180] <Explanation of a second example of each signal in the IC> Figure 18 is a timing chart that explains the light emission control data signal DAin and the clock signal NCKSin signal input to IC 192 in Figure 17, the generation pulse train output from DFF 261, and the PWM control signal generated by IC 192.

[0181] The frame-by-frame light emission control data signal DAin and PWM control signal in Figure 18 are identical to those in Figure 12, so no further explanation is provided.

[0182] The frame-by-frame clock signal NCKSin[0] in Figure 18 differs from the frame-by-frame clock signal NCKSin[0] in Figure 12 in that it includes a period pulse train instead of a generation pulse train. Otherwise, it is the same as the frame-by-frame clock signal NCKSin[0].

[0183] Specifically, the frame-unit clock signal NCKSin[0] includes an acquisition instruction signal and a start pulse, similar to the frame-unit clock signal NCKSin[0] in Figure 12. Following this start pulse, a lower-period pulse train and an upper-period pulse train are included in order. The lower-period pulse train consists of two fundamental clock pulses. j It consists of eight trigger pulse pairs, each consisting of a leading trigger pulse and a terminating trigger pulse of twice the pulse width. The upper pulse train has 255 pulses, 2 8 It consists of a trigger pulse pair with twice the pulse width.

[0184] Similarly, the frame-unit clock signal NCKSin[i] for the rows from the first row onwards also contains the acquisition instruction signal and the start pulse, followed by the lower period pulse sequence and then the upper period pulse sequence in that order.

[0185] When the frame-by-frame light emission control data signal DAin and the clock signal NCKSin[i] are input as described above, the DFF 261 starts generating a pulse train based on the start pulse, and the PWM control circuit 212 starts generating a PWM control signal.

[0186] The DFF 261 generates pulses based on each trigger pulse pair included in the lower-period pulse train and the upper-period pulse train, with the pulse width being the period from the leading trigger pulse to the ending trigger pulse of that trigger pulse pair. Specifically, the DFF 261 generates pulses by dividing (toggle) the frequency, using the leading trigger pulse of each trigger pulse pair as the rising edge and the ending trigger pulse as the falling edge. As a result, a pulse train for generation is generated (demodulated) as shown in Figure 18.

[0187] <Detailed explanation of the second example of the clock signal NCKSin> Figure 19 is a diagram that provides a detailed explanation of the clock signal NCKSin[0] shown in Figure 18.

[0188] In the example shown in Figure 19, the frequency of the base clock is 10 MHz. Therefore, the instruction signal for acquiring the frame-unit clock signal NCKSin[0] consists of 64 10 MHz base clocks. Following this acquisition instruction signal, the frame-unit clock signal NCKSin[0] includes, in order, a start pulse, a lower period pulse train, and an upper period pulse train.

[0189] The frame-based clock signal NCKSin[0], constructed as described above, is generated within one frame period. The acquisition instruction signal is generated within the vertical blanking interval (V-BLK period).

[0190] In IC192 of Figure 17, as in the case of IC192 of Figure 10, the 16-bit PWM control value can be divided into arbitrary upper L bits and lower M bits. The lower period pulse train and upper period pulse train included in the clock signal NCKSin[0] may be arranged in the order of upper period pulse train followed by lower pulse period train.

[0191] <Example of display unit implementation> Figure 20 shows an example of the display unit 121 implementation.

[0192] As shown in Figure 20, the driver control unit 161 of the display unit 121 is mounted on the hub board 271 as a receiving card, and the LED array panel 162 is mounted on the pixel board 272.

[0193] The hub board 271 is connected to an internal AC power supply 273 and a connector 274. The internal AC power supply 273 supplies power voltage to the hub board 271. This power voltage is also supplied to the pixel board 272, which is connected to the hub board 271. The power voltage supplied to the pixel board 272 is used, for example, as the power voltage VDD of IC 192. The output IF 151 of the video wall controller 113 is connected to the connector 274, and the video signal output from the output IF 151 is input to it. This video signal is converted into PWM control data by the driver control unit 161 and supplied to the LED array panel 162 of the pixel board 272.

[0194] <Example of Pixel Substrate Structure> Figure 21 shows an example of the structure of the pixel substrate 272 in Figure 20.

[0195] Figures 21A and 21B show the display surface and the back surface of the pixel substrate 272, respectively.

[0196] As shown in Figure 21A, pixel units 182 are formed on the display surface of the pixel substrate 272. As shown in Figure 21B, a drive IC 291, on which a column drive circuit 3 and a row drive circuit 185 are mounted, is formed on the back surface of the pixel substrate 272 for each LED array panel 162. A connector 292 for connecting to the hub substrate 271 is also formed on the back surface of the pixel substrate 272. PWM control data and power supply voltage are input to the connector 292 from the hub substrate 271.

[0197] As described above, the number of wires connected to the pixel unit 182 is two: four column wires and six row wires. Therefore, the pixel substrate 272 can be manufactured at a low cost. In contrast, in the passive drive method, the number of wires connected to the pixel unit is a total of four: three column wires connected to the anodes of the three red, green, and blue LEDs of the pixel unit, and one row wire connected to the cathodes of all three LEDs.

[0198] As described above, in IC 192, the PWM generation circuit 221 generates a PWM control signal by extracting a predetermined pulse from a generation pulse train composed of a lower pulse train and a higher pulse train, based on the PWM control value. Therefore, the power consumption of IC 192 can be reduced compared to IC 12. As a result, the power consumption of the control system of the video wall 114 can be reduced. Furthermore, since the frequencies of the generation pulse train and the period pulse train are low as signal frequencies, EMI (Electromagnetic Interference) countermeasures become easier.

[0199] IC192 may be configured as a combination of IC192 in Figure 10 and IC192 in Figure 17, and may be capable of supporting both generation pulse trains and period pulse trains. In this case, for example, a value indicating whether the clock signal NCKSin contains a generation pulse train or a period pulse train is included in the control value of IC192. Based on this value, IC192 selectively performs processing corresponding to either a generation pulse train or a period pulse train.

[0200] <4. Second Embodiment> <Example of LED Array Panel Configuration> The configuration of the second embodiment of the display system to which this technology is applied differs from that of the display system 110 in Figure 7 in the configuration of the LED array panel, but the rest of the configuration is the same as that of the display system 110. Therefore, the following description will focus on the LED array panel.

[0201] Figure 22 shows an example of the configuration of an LED array panel in a second embodiment of a display system to which this technology is applied.

[0202] In Figure 22, the parts of the LED array panel 451 that correspond to the LED display 51 in Figure 4 are given the same reference numerals. Therefore, the explanation of those parts will be omitted as appropriate, and the explanation will focus on the parts that differ from the LED display 51.

[0203] The LED array panel 451 differs from the LED display 51 in that PWM control data is input from the output IF 173, and the pixel unit 52 and column drive circuit 53 are replaced by the pixel unit 452 and column drive circuit 453. Otherwise, it is configured the same as the LED display 51.

[0204] In the LED array panel 451, each pixel unit 452 is actively driven using a single row wiring 54.

[0205] The pixel unit 452 differs from the pixel unit 52 in that it has IC 462 instead of IC 62, but otherwise it is configured the same as the pixel unit 52. The configuration of IC 462 will be described later with reference to Figure 23. Similar to IC 62, the column wiring 54 is daisy-chained to IC 462, and the power supply voltage wiring 55 and ground voltage wiring 56 are also connected to it.

[0206] The column drive circuit 453 is connected to the column wiring 54 of each column of the pixel unit 452. The column drive circuit 453 (data clock signal generation unit) generates a data clock signal NDCKin for each column of the pixel unit 452 on a frame-by-frame basis and supplies it to the pixel unit 452 via the column wiring 54 of that column. The data clock signal NDCKin differs from the data clock signal DCKin in that the signal for PWM generation is replaced by a period pulse train, but is otherwise the same as the data clock signal DCKin.

[0207] As described above, the column wiring 54 is daisy-chained to IC 462 of the pixel unit 452. Therefore, similar to IC 62, the data clock signal NDCKin is supplied to each IC 462 of the pixel units 452 arranged in the column direction, starting from the one closest to the column drive circuit 453, and is transmitted in the column direction like a bucket brigade. As a result, each IC 462 of the pixel units 452 arranged in the column direction acquires and stores PWM control data in order from the one closest to the column drive circuit 453.

[0208] IC 462 starts generating PWM control signals for each LED 11 when it detects a start instruction value of 1 superimposed on the data clock signal NDCKin. Specifically, in this case, IC 462 generates a generation pulse train from the period pulse train included in the data clock signal NDCKin after this start instruction value. Then, for each LED 11, IC 462 starts generating a PWM control signal by extracting a predetermined pulse from the generation pulse train based on the stored PWM control data. Each LED 11 lights up based on this PWM control signal.

[0209] As described above, in the LED array panel 451, the pixel units 452 are driven using a single row wiring 54. Therefore, the LED array panel 451 can reduce the number of wirings compared to the LED array panel 162.

[0210] <Example of IC logic circuit configuration> Figure 23 shows an example of the logic circuit configuration of IC 462 shown in Figure 22.

[0211] In the logic circuit of IC462 in Figure 23, the parts corresponding to the logic circuit of IC62 in Figure 5 and the logic circuit of IC192 in Figure 10 are given the same reference numerals. Therefore, explanations of those parts will be omitted as appropriate, and the explanation will focus on the parts that differ from IC62 and IC192.

[0212] The logic circuit of IC462 differs from that of IC62 in that the PWM control circuit 34 and counter 85 are replaced by the PWM control circuit 212 and counter 483, and the AND gate 481 and DFF 482 are newly added. Otherwise, it is configured the same as the logic circuit of IC62.

[0213] The AND gate 481 reads the start instruction value stored in register 84-1. The AND gate 481 is supplied with the data clock signal NDCKin from the signal detection circuit 81. If the start instruction value is 1, the AND gate 481 supplies the data clock signal NDCKin to the DFF 482. As a result, the period pulse train of the data clock signal NDCKin is supplied to the DFF 482.

[0214] The DFF482 (generation pulse train generation unit), like the DFF261, generates a generation pulse train from the period pulse train supplied by the AND circuit 481. The DFF482 supplies the generated period pulse train to the counter 483 and AND circuits 233-1 to 233-3. The DFF482 is initialized when a notification signal is supplied from the header control circuit 82 or when a reset signal is supplied from the reset control circuit 213. This initialization enables the DFF482 to accurately generate the generation pulse train.

[0215] Counter 483 is an 8-bit counter. Counter 483 reads the start instruction value stored in register 84-1. If the start instruction value is 1, Counter 483 (counting unit) starts counting the number of pulses in the upper pulse sequence of the generation pulse sequence supplied from DFF 284. Counter 483 supplies the resulting count value to the upper bit processing circuits 231-1 to 231-3. Note that Counter 483 is reset when a reset signal is supplied from the reset control circuit 86.

[0216] <Explanation of each signal in the IC> Figure 24 is a timing chart that explains the data clock signal NDCKin input to IC 462 in Figure 23, the generation pulse train generated by DFF 482, and the PWM control signal generated by IC 462.

[0217] In Figure 24, the data clock signal NDCKin, which is input via column wiring 54 to IC 462 of the i-th pixel unit 452 closest to the column drive circuit 453, i.e., the i-th row from the top, is labeled as data clock signal NDCKin[i].

[0218] The frame-by-frame data clock signal NDCKin[0] in Figure 24 differs from the frame-by-frame data clock signal DCKin[0] in Figure 6 in that it includes a period pulse train instead of a PWM generation signal. Otherwise, it is the same as the frame-by-frame data clock signal DCKin[0].

[0219] Specifically, the frame-level data clock signal NDCKin[0] contains a data pulse train, similar to the frame-level data clock signal DCKin[0] in Figure 6. Following this data pulse train, a lower-period pulse train and an upper-period pulse train are included in order.

[0220] Although not shown in the diagram, the frame-level data clock signal NDCKin[i] for the rows from the first row onwards also similarly contains a data pulse sequence followed by a lower-period pulse sequence and then an upper-period pulse sequence.

[0221] When a frame-unit data clock signal NDCKin[i] as described above is input, the AND circuit 481 supplies the period pulse train included in the data clock signal NDCKin[i] to the DFF 261 based on the start instruction value. As a result, the DFF 482 starts generating the generation pulse train shown in Figure 24, similar to the DFF 261.

[0222] The generation pulse train generated by the DFF 482 is input to the counter 483, and the counter 483 starts counting the number of pulses in the upper pulse train of the generation pulse train according to the start instruction value. The PWM control circuit 212 generates the upper bit PWM control signal based on the resulting count value. The method for generating the lower bit PWM control signal is the same as the method described in Figure 12, so the explanation is omitted.

[0223] Here, the data clock signal NDCKin for each column must contain one frame's worth of clock signal NCKSin within one frame period. However, the counter 483 only needs to count 255 pulses included in the upper pulse train within the time obtained by subtracting the data pulse train period, i.e., the writing time of the PWM control data, from one frame period. Therefore, assuming, for example, that the writing time of the PWM control data is 0, even if the frame rate is 120 Hz, the operating frequency of the counter 483 only needs to be around 30 kHz (30600 Hz = 120 Hz × 255). Thus, the power consumption of the counter 483 is smaller than that of the counter 85 in Figure 5. As a result, the power consumption of the logic circuit can be reduced with IC 462 compared to IC 62.

[0224] In IC462, the operating frequency of the signal detection circuit 81 is the same as the frequency of the base clock, and is high, similar to IC62. However, the operating time of the signal detection circuit 81, i.e., the time it takes to write PWM control data, is short. For example, if the operating frequency of the signal detection circuit 81, i.e., the frequency of the base clock, is 20MHz, and the number of pixel units 452 in one row (m+1) is 270, then the time it takes to write PWM control data is 864μs (=64×270×0.05). Therefore, if the frame rate is 120Hz, the ratio of the writing time to the frame duration of 8.3ms is approximately 10%. Thus, the power consumption of the signal detection circuit 81 is negligibly small in the overall power consumption of IC462.

[0225] <Example of Pixel Substrate Structure> In the second embodiment of the display system to which this technology is applied, the driver control unit of the display unit is mounted on a hub substrate, similar to the display unit 121 in Figure 20, and the LED array panel 451 is mounted on a pixel substrate.

[0226] Figure 25 shows an example of the structure of a pixel substrate on which an LED array panel 451 is mounted.

[0227] Figures 25A and 25B show the display surface and back surface structures of the pixel substrate 521 on which the LED array panel 451 is mounted, respectively.

[0228] As shown in Figure 25A, pixel units 452 are formed on the display surface of the pixel substrate 521. As shown in Figure 25B, on the back surface of the pixel substrate 521, drive ICs 531 are formed for each row of LED array panels 451, with drive circuits 453 for one or more LED array panels 451 arranged in the column direction mounted on each row. Therefore, the number of drive ICs 531 is less than the number of drive ICs 291 in Figure 21. A connector 532 for connecting to a hub substrate (not shown) is also formed on the back surface of the pixel substrate 521. PWM control data and power supply voltage are input to the connector 532 from the hub substrate.

[0229] As described above, the number of wires connected to the pixel unit 452 is one, which is a row wire 54. In contrast, in the passive drive method, as described above, the number of wires connected to the pixel unit is four. Since the wires connected to the pixel unit 452 do not cross on the pixel substrate 521, the number of wiring layers can be reduced compared to the pixel substrate 272. Therefore, the manufacturing cost of the pixel substrate 521 is lower than that of the pixel substrate 272.

[0230] As described above, in IC 462, the PWM generation circuit 221 generates a PWM control signal by extracting a predetermined pulse from a generation pulse train composed of a lower pulse train and a higher pulse train, based on the PWM control value. Therefore, the power consumption of IC 462 can be reduced compared to IC 62. As a result, the power consumption of the control system of a video wall having IC 462 can be reduced. Since the frequencies of the generation pulse train and the period pulse train are low as signal frequencies, EMI countermeasures become easier.

[0231] In addition, in the first and second embodiments, when the display system is in energy-saving mode, the power consumption of IC 192 (462) may be further reduced by reducing the number of bits in the brightness gradation of LED 11. For example, if the number of bits in the brightness gradation is reduced from 16 bits to 12 bits, the frequency of the basic clock decreases to 1 / 16th, and the power consumption of IC 192 (462) is significantly reduced.

[0232] In the first and second embodiments, the power consumption of IC 192 (462) may be further reduced by finening the IC process rule. For example, the power consumption of IC 192 (462) can be further reduced by finening the IC process rule from 160 μm to 90 nm.

[0233] In the first and second embodiments, IC192(462) may have multiple presets for the order and division method of the lower pulse train and the upper pulse train. In this case, which preset IC192(462) uses is specified, for example, by a 15-bit control value of IC192(462) following a 1-bit header of the PWM control data. Alternatively, the order and division method of the lower pulse train and the upper pulse train may be input to IC192(462) by specifying the order setting value (order information) and division setting value (division information), which are determined by user setting or automatic setting, using the 15-bit control value of IC192(462) in the PWM control data.

[0234] The pulse train for generation is 2 of the base clock. j The pulse train may consist only of pulses with twice the pulse width, and in this case as well, the power consumption of IC192 (462) is reduced. However, in this case, false contours may occur in the displayed image and the image quality may deteriorate, but as described in the first and second embodiments, the occurrence of false contours can be suppressed by combining a lower pulse train consisting of pulses with pulse widths corresponding to each lower bit of the PWM control value and an upper pulse train consisting of the maximum number of predetermined pulse widths represented by the upper bits of the PWM control value. Similarly, for the period pulse train, twice the basic clock j It may consist only of trigger pulse pairs with twice the pulse width.

[0235] The counter 211 (483) may be a counter having performance exceeding the bit precision used. In the first and second embodiments, the counter 211 (483) was described as an 8-bit precision counter, but a counter having performance exceeding 8 bits of bit precision, such as one corresponding to 16 bits of precision, can be used. In this case, for example, the number of pulses in the upper pulse train of the generation pulse train (period pulse train) input to IC 192 (462) is 255 (=2 8If the value is -1) or less, counter 211 (483) can be used as an 8-bit precision counter, and if the number of pulses in the upper pulse train (upper period pulse train) exceeds 255, counter 211 (483) can be used as a counter with a bit precision greater than 8 bits. This makes it possible to use IC 192 (462) with higher bit precision while reducing the power consumption of IC 192 (462) depending on the bit precision used.

[0236] Note that the lower and upper bits of the PWM control value, and the lower and upper pulse sequences of the generation pulse train, may be reversed. For example, the upper pulse sequence of the generation pulse train may consist of pulses with pulse widths corresponding to each of the upper bits of the PWM control value, and the lower pulse sequence may consist of the maximum number of pulses with predetermined pulse widths represented by the lower bits of the PWM control value. The same applies to the period pulse train.

[0237] <5. Other Examples of Pulse Widths in Lower Pulse Trains> Figure 26 shows another example of the pulse width of each pulse in a lower pulse train.

[0238] In the first and second embodiments, the pulse width of each pulse in the lower pulse train is 2 times the base clock. j Although it was doubled, as shown in Figure 26, an offset may be added to the pulse width of at least a portion of the lower pulse train.

[0239] In the example shown in Figure 26, an offset value is added to the pulse width for pulses with pulse widths of 1x, 2x, 4x, and 8x the base clock, i.e., pulses corresponding to each of the four bits from the least significant bit.

[0240] Note that pulses to which an offset value is added to the pulse width are not limited to the pulses in the example shown in Figure 26. The offset value may be different for each pulse or may be the same for each pulse.

[0241] <Effects of Offset Values> Figure 27 is a diagram illustrating the effects of the offset values ​​in Figure 26.

[0242] In Figure 27A, the horizontal axis represents time [t] and the vertical axis represents the PWM control signal. In Figure 27B, the horizontal axis represents time [t] and the vertical axis represents the luminous intensity of LED 11.

[0243] As shown in Figure 27, when the PWM control signal is turned on, current is supplied to the LED 11, but the luminescence of the LED 11 increases slowly. Therefore, for example, if the pulse width of the PWM control signal is small, the energizing time of the LED 11 is short, and the luminescence of the LED 11 does not rise sufficiently.

[0244] For example, if the frame rate is 120Hz, the frequency of the base clock needs to be around 8MHz, and in this case, the pulse width of one times the base clock is approximately 125ns. However, considering the response of the LED 11, a light emission time of 200ns or more is required to obtain the desired light emission brightness.

[0245] Therefore, in this case, an offset value equal to 1x the base clock is added to the pulse width of the pulse corresponding to the least significant bit, i.e., the pulse with a pulse width equal to 1x the base clock. As a result, the pulse width becomes twice that of the base clock, i.e., approximately 250ns (=125 × 2), and the desired luminescence brightness can be obtained.

[0246] As described above, the linearity of low-brightness gradations can be improved by adding an offset value to the pulse width of pulses with small pulse widths among the lower pulse trains, so that the LED 11 can obtain the desired luminescence brightness.

[0247] In recent years, LCD (Liquid Crystal Display) displays that employ local dimming (partial dimming) methods have been developed for use in television receivers and other devices. In the backlights of such LCD displays, as the number of local dimming divisions increases (higher resolution), some use an active drive method to drive the local dimming. This technology can also be applied to such backlights. For example, IC192 or IC462 can be installed in the backlight of an LCD display that uses an active drive method to drive local dimming. This reduces the power consumption of the backlight control system.

[0248] In this specification, a system refers to a collection of multiple components (devices, modules (parts), etc.), regardless of whether all components are located in the same enclosure. Therefore, multiple devices housed in separate enclosures and connected via a network, and a single device containing multiple modules within a single enclosure, are both considered systems.

[0249] The embodiments of this technology are not limited to those described above, and various modifications are possible without departing from the spirit of this technology.

[0250] The effects described herein are merely illustrative and not limited to those described herein; other effects may also occur.

[0251] The present technology can take the following configurations: (1) A display system comprising a light emission control signal generation unit that generates a light emission control signal by extracting a predetermined pulse from a generation pulse train, which is composed of a first pulse train consisting of pulses with pulse widths corresponding to each bit of a first bit group of the light emission control value, and a second pulse train consisting of the largest number of pulses with predetermined pulse widths represented by a second bit group of the light emission control value that is different from the first bit group, based on a light emission control value of a predetermined number of bits. (2) The display system according to (1), wherein the generation pulse train is synchronized with a clock of a predetermined frequency, and when the number of bits included in the first bit group is k (where k is an integer of 1 or more), the first pulse train includes pulses with pulse widths that are powers of 2 of the clock, each having k integers of 0 or more but less than k as exponents, and the predetermined pulse width is configured to be 2 to the power of k of the clock. (3) The display system according to (2), wherein the first bit group is a bit group including a predetermined number of bits from the least significant bit of the light emission control value, the second bit group is a bit group higher than the first bit group, and the pulse width of the pulse corresponding to the j-th bit from the least significant bit in the first pulse train is configured to be 2 to the power of j times the clock. (4) The display system according to (3), further comprising a counting unit for counting the number of pulses included in the second pulse train, wherein the light emission control signal generation unit is configured to generate the light emission control signal corresponding to the second bit group by extracting a predetermined pulse from the second pulse train based on the value of the second bit group of the light emission control value and the number of pulses counted by the counting unit. (5) The display system according to (3) or (4), wherein the light emission control signal generation unit is configured to generate the light emission control signal corresponding to the first bit group by extracting the pulse corresponding to that bit from the first pulse train based on the value of each bit in the first bit group of the light emission control value.(6) The display system according to any one of (2) to (5), wherein the clock signal synchronized with the clock includes an acquisition instruction signal that instructs the acquisition of the light emission control value and the generation pulse train, and between the acquisition instruction signal and the generation pulse train, there is a start pulse that indicates the start of the generation pulse train, and the light emission control signal generation unit is configured to start generating the light emission control signal based on the start pulse. (7) The display system according to (6), wherein the light emission control signal generation unit acquires the light emission control value from a light emission control data signal that indicates the light emission control value based on the acquisition instruction signal, and the light emission control data signal is configured to synchronize with the clock. (8) The display system according to (7), further comprising a clock signal generation unit that generates the clock signal and a light emission control data signal generation unit that generates the light emission control data signal. (9) The display system according to (8), wherein the light emission control signal generation unit is arranged in a matrix and provided for each light-emitting unit that emits light based on the light emission control signal, the clock signal generation unit generates the clock signal on a row-by-row basis for the light-emitting unit, and the light emission control data signal generation unit generates the light emission control data signal on a column-by-column basis for the light-emitting unit. (10) The display system according to any one of (2) to (5), further comprising a generation pulse train generation unit that generates the generation pulse train from a period pulse train composed of a first period pulse train consisting of a trigger pulse representing the period of the pulse width of each pulse in the first pulse train and a second period pulse train consisting of a trigger pulse representing the period of a predetermined pulse width for each pulse in the second pulse train, wherein the light emission control signal generation unit is configured to generate the light emission control signal by extracting the predetermined pulse from the generation pulse train generated by the generation pulse train generation unit. (11) The display system according to (10), wherein the data clock signal synchronized with the clock includes a data pulse train and a period pulse train in which the light emission control value is superimposed on the clock, the data pulse train also includes a start instruction value that indicates the start of the period pulse train, and the light emission control signal generation unit is configured to start generating the light emission control signal based on the start instruction value.(12) The display system according to (11), further comprising a data clock signal generation unit for generating the data clock signal. (13) The display system according to (12), wherein the light emission control signal generation unit is arranged in a matrix and provided for each light-emitting unit that emits light based on the light emission control signal, and the data clock signal generation unit is configured to generate the data clock signal in units of columns of the light-emitting units. (14) The display system according to any one of (2) to (13), wherein an offset value is added to the pulse width of at least some of the pulses in the first pulse train. (15) The display system according to any one of (1) to (14), wherein the light emission control signal generation unit is configured to extract predetermined pulses from the generation pulse train based on sequence information representing the order of the first pulse train and the second pulse train included in the generation pulse train. (16) The display system according to any one of (1) to (15), wherein the light emission control signal generation unit is configured to extract a predetermined pulse from the generation pulse train based on division information representing a method for dividing the first pulse train and the second pulse train included in the generation pulse train. (17) The display system according to any one of (1) to (6), wherein the light emission control signal generation unit is configured to acquire a plurality of light emission control values ​​from a plurality of light emission control data signals representing a plurality of light emission control values ​​corresponding to a plurality of light-emitting elements included in a single pixel, and to generate a light emission control signal for causing the light-emitting elements included in the pixel to emit light. (18) The display system according to any one of (1) to (8) and (10) to (12), further comprising a light-emitting unit that emits light based on the light emission control signal. (19) The display system according to (18), wherein the light-emitting units are arranged in a matrix, and the light emission control signal generation unit is provided for each light-emitting unit. (20) The display system according to (19), wherein the light emission control signal generation unit is composed of an IC.

[0252] 3-column drive circuit, 11-1 to 11-3 LEDs, 114 video wall, 162 ICs, 185-row drive circuit, 211 counter, 221-1 to 221-3 PWM generation circuit, 261 DFF, 451 IC, 453-column drive circuit, 482 DFF

Claims

A light emission control signal generation unit generates a light emission control signal by extracting a predetermined pulse from a generation pulse train, which is composed of a first pulse train consisting of pulses with pulse widths corresponding to each bit in the first bit group of the light emission control value, and a second pulse train consisting of the maximum number of pulses with predetermined pulse widths represented by a second bit group of the light emission control value that is different from the first bit group, based on a light emission control value of a predetermined number of bits. A display system equipped with the following features. 　 The aforementioned generation pulse train is synchronized with a clock of a predetermined frequency. When the number of bits included in the first bit group is k (where k is an integer greater than or equal to 1), The first pulse train includes the pulses of the clock, each having a pulse width that is a power of 2, with each of the k integers (0 or greater, less than k) as its exponent. The predetermined pulse width is 2 to the power of k times the clock. It is configured in such a way The display system according to claim 1. 　 The first bit group is a bit group that includes a predetermined number of bits starting from the least significant bit of the light emission control value, The second set of bits is a set of bits that are higher in rank than the first set of bits. The pulse width of the pulse corresponding to the j-th bit from the least significant bit in the first pulse train is 2 to the power of j times the clock. It is configured in such a way The display system according to claim 2. 　 A counting unit that counts the number of pulses included in the second pulse train. Furthermore, The light emission control signal generation unit generates the light emission control signal corresponding to the second bit group by extracting a predetermined pulse from the second pulse sequence based on the second bit group value of the light emission control value and the number of pulses counted by the counting unit. It is configured in such a way The display system according to claim 3. 　 The light emission control signal generation unit generates the light emission control signal corresponding to the first bit group by extracting the pulse corresponding to that bit from the first pulse train based on the value of each bit in the first bit group of the light emission control value. It is configured in such a way The display system according to claim 3. 　 The clock signal synchronized with the aforementioned clock includes an acquisition instruction signal that instructs the acquisition of the light emission control value and the generation pulse train, Between the acquisition instruction signal and the generation pulse train, a start pulse is included that indicates the start of the generation pulse train. The light emission control signal generation unit starts generating the light emission control signal based on the start pulse. It is configured in such a way The display system according to claim 2. 　 The light emission control signal generation unit acquires the light emission control value from the light emission control data signal representing the light emission control value based on the acquisition instruction signal. The light emission control data signal is synchronized with the clock. It is configured in such a way The display system according to claim 6. 　 A clock signal generation unit that generates the aforementioned clock signal, A light emission control data signal generation unit that generates the aforementioned light emission control data signal and Furthermore, it is equipped with The display system according to claim 7. 　 The light emission control signal generation unit is arranged in a matrix and is provided for each light emission unit that emits light based on the light emission control signal. The clock signal generation unit generates the clock signal on a row-by-row basis for the light-emitting unit. The light emission control data signal generation unit generates the light emission control data signals in a row-by-row unit. It is configured in such a way The display system according to claim 8. 　 A pulse train generation unit generates the generation pulse train from a period pulse train composed of a first period pulse train consisting of a first period pulse train consisting of a trigger pulse representing the duration of the pulse width of each pulse in the first pulse train, and a second period pulse train consisting of a trigger pulse representing the duration of the predetermined pulse width of each pulse in the second pulse train. Furthermore, The light emission control signal generation unit generates the light emission control signal by extracting predetermined pulses from the generation pulse train generated by the generation pulse train generation unit. It is configured in such a way The display system according to claim 2. 　 The data clock signal synchronized with the clock includes a data pulse train in which the light emission control value is superimposed on the clock and a period pulse train. In the data pulse train, a start instruction value representing the start of the period pulse train is also superimposed on the clock. The light emission control signal generation unit starts generating the light emission control signal based on the start instruction value. It is configured in such a way The display system according to claim 10. 　 Data clock signal generation unit that generates the aforementioned data clock signal Furthermore, it is equipped with The display system according to claim 11. 　 The light emission control signal generation unit is arranged in a matrix and is provided for each light emission unit that emits light based on the light emission control signal. The data clock signal generation unit generates the data clock signal in a row-by-row unit of the light-emitting unit. It is configured in such a way The display system according to claim 12. 　 An offset value is added to the pulse width of at least some of the pulses in the first pulse train. It is configured in such a way The display system according to claim 2. 　 The light emission control signal generation unit also extracts the predetermined pulses from the generation pulse train based on sequence information representing the order of the first pulse train and the second pulse train included in the generation pulse train. It is configured in such a way The display system according to claim 1. 　 The light emission control signal generation unit also extracts the predetermined pulses from the generation pulse train based on division information representing the method of dividing the first pulse train and the second pulse train included in the generation pulse train. It is configured in such a way The display system according to claim 1. 　 The light emission control signal generation unit is Multiple light emission control values ​​are obtained from light emission control data signals representing multiple light emission control values ​​corresponding to multiple light-emitting elements contained in a single pixel. The light-emitting control signal is generated to cause the light-emitting element contained in the pixel to emit light. It is configured in such a way The display system according to claim 1. 　 Light-emitting unit that emits light based on the light-emitting control signal. Furthermore, it is equipped with The display system according to claim 1. 　 The light-emitting units are arranged in a matrix, The light emission control signal generation unit is provided for each of the light emission units. It is configured in such a way The display system according to claim 18. 　 The light emission control signal generation unit is composed of an IC. The display system according to claim 19.

Images