Display substrate and preparation method therefor, and display apparatus

Abstract

A display substrate and a preparation method therefor, and a display apparatus. The display substrate comprises a driving structure layer. The driving structure layer comprises a plurality of repeating units (Q), wherein an insertion column is disposed between adjacent columns of repeating units; and at least one repeating unit (Q) comprises a plurality of circuit units, and at least one circuit unit comprises a pixel driving circuit and a data signal line (70). The driving structure layer further comprises first connecting lines (81), second connecting lines (82), first constant-voltage traces (91) and second constant-voltage traces (92), wherein first ends of the first connecting lines (81) are connected to the data signal lines (70), second ends of the first connecting lines (81) are connected to the second connecting lines (82), and at least one second constant-voltage trace (92) is connected to at least one first constant-voltage trace (91), so as to form a mesh-connected structure for transmitting a constant-voltage signal; and the second connecting lines (82) and the second constant-voltage traces (92) are disposed in the insertion columns.

Description

Display substrate and its preparation method, display device

[0001] This application claims priority to Chinese Patent Application No. 202411441730.5, filed on October 15, 2024, entitled "Display Substrate and Method for Preparing the Same, Display Device", the contents of which are to be understood as incorporated herein by reference. Technical Field

[0002] This article relates to, but is not limited to, the field of display technology, specifically to a display substrate and its preparation method, and a display device. Background Technology

[0003] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] On one hand, this disclosure provides a display substrate, including a driving structure layer disposed on a substrate; the driving structure layer includes a plurality of repeating units forming a plurality of repeating unit rows and a plurality of repeating unit columns, with an insertion column disposed between adjacent repeating unit columns; at least one repeating unit includes a plurality of circuit units arranged sequentially along a first direction, at least one circuit unit including a pixel driving circuit and a data signal line extending along a second direction, the data signal line being connected to the pixel driving circuit and configured to provide a data signal to the pixel driving circuit, the first direction and the second direction intersecting; the driving structure layer further includes at least one first connecting line and at least one first constant voltage trace extending along the first direction, and at least one second connecting line and at least one second constant voltage trace extending along the second direction, a first end of the first connecting line being connected to the data signal line, a second end of the first connecting line being connected to the second connecting line, and at least one second constant voltage trace being connected to at least one first constant voltage trace to form a mesh-like interconnected structure for transmitting constant voltage signals; the second connecting line and the second constant voltage trace are disposed in the insertion column.

[0006] In an exemplary embodiment, at least one repeating unit includes three circuit units.

[0007] In an exemplary embodiment, the pixel driving circuit includes at least a storage capacitor, a first transistor as a first initialization transistor, and a second transistor as a compensation transistor. The first transistor includes at least a first gate electrode and a first active layer, and the second transistor includes at least a second gate electrode and a second active layer. The storage capacitor includes a first electrode and a second electrode. The orthographic projection of the second electrode on the substrate at least partially overlaps with the orthographic projection of the first electrode on the substrate. The first electrode is connected to a second region of the first active layer and a first region of the second active layer. The second electrode is connected to a first power line. At least one circuit unit further includes a shielding electrode connected to the second electrode. The orthographic projection of the shielding electrode on the substrate at least partially overlaps with the orthographic projection of the first active layer between the two gate electrodes of the first transistor on the substrate. The orthographic projection of the shielding electrode on the substrate at least partially overlaps with the orthographic projection of the second active layer between the two gate electrodes of the second transistor on the substrate. The orthographic projection of at least one second connection line on the substrate at least partially overlaps with the orthographic projection of the shielding electrode on the substrate.

[0008] In an exemplary embodiment, the pixel driving circuit further includes a third transistor as a driving transistor and a fourth transistor as a data writing transistor. The third transistor includes at least a third active layer, and the fourth transistor includes at least a fourth active layer. A first region of the third active layer is connected to a second region of the fourth active layer. At least one circuit unit further includes a compensation electrode connected to the second electrode plate. The orthographic projection of the compensation electrode on the substrate at least partially overlaps with the orthographic projection of the connection region of the first region of the third active layer and the second region of the fourth active layer on the substrate.

[0009] In an exemplary embodiment, the pixel driving circuit further includes a fourth transistor as a data writing transistor, the second gate electrode is connected to a first scan signal line extending along the first direction, the gate electrode of the fourth transistor is connected to a second scan signal line extending along the first direction, the first electrode of the fourth transistor is connected to the data signal line, and the second scan signal line is disposed on the side of the first scan signal line away from the second electrode plate; in the second direction, the first connecting line and the first constant voltage trace are disposed between the first scan signal line and the second electrode plate, or the first connecting line and the first constant voltage trace are disposed between the first scan signal line and the second scan signal line.

[0010] In an exemplary embodiment, at least one circuit unit further includes a data connection electrode, the data signal line being connected to the data connection electrode via a via, and the data connection electrode being connected to the first electrode of the fourth transistor via a via; at least one repeating unit further includes a data connection block, the data connection block being connected to the first connection line and the data connection electrode in one circuit unit respectively, and the data connection block being disposed on the side of the first scan signal line near the second electrode plate.

[0011] In an exemplary embodiment, at least one repeating unit further includes a data connection block connected to the first connection line. The data connection block is connected to the first electrode of the fourth transistor in a circuit unit via a via. The data signal line is connected to the data connection block via a via. The data connection block is disposed on the side of the first scan signal line away from the second electrode plate.

[0012] In an exemplary embodiment, the pixel driving circuit further includes a fifth transistor as a first light-emitting control transistor, the gate electrode of the fifth transistor being connected to the light-emitting signal line, the first electrode of the fifth transistor being connected to the first power supply line, and the light-emitting signal line being disposed on one side of the second electrode plate in the second direction; in the second direction, the first connecting line and the first constant voltage trace are disposed on the side of the light-emitting signal line away from the second electrode plate.

[0013] In an exemplary embodiment, the display substrate further includes a light-emitting structure layer disposed on the side of the driving structure layer away from the substrate. The light-emitting structure layer includes at least a red light-emitting unit, a green light-emitting unit, and a blue light-emitting unit. The red light-emitting unit includes at least a first anode, the green light-emitting unit includes at least a second anode, and the blue light-emitting unit includes at least a third anode. The orthographic projections of at least one first anode and at least one second anode on the substrate at least partially overlap with the orthographic projections of the second connecting line or the second constant voltage trace on the substrate. The orthographic projection of at least one third anode on the substrate at least partially overlaps with the orthographic projection of the data signal line on the substrate.

[0014] In an exemplary embodiment, at least one third anode is provided with an anode groove, the anode groove being a strip-shaped portion extending along the second direction, and the orthographic projection of the anode groove on the substrate at least partially overlaps with the orthographic projection of the data signal line on the substrate.

[0015] In an exemplary embodiment, at least one constant voltage connection line extending along the second direction is further provided in at least one insertion column; in the first direction, the constant voltage connection line is disposed between the second connection line and the data signal line, or the constant voltage connection line is disposed between the second constant voltage trace and the data signal line.

[0016] In an exemplary embodiment, at least one circuit unit further includes a first initial signal line, a second initial signal line, and a third initial signal line extending along the first direction. The pixel driving circuit is connected to the first initial signal line, the second initial signal line, and the third initial signal line, respectively. The first initial signal line, the second initial signal line, and the third initial signal line are configured to provide a first initial signal, a second initial signal, and a third initial signal to the pixel driving circuit, respectively. At least one of the constant voltage connection lines is connected to the first initial signal line, the second initial signal line, or the third initial signal line.

[0017] In an exemplary embodiment, the display substrate further includes a light-emitting structure layer disposed on the side of the driving structure layer away from the substrate. The light-emitting structure layer includes a plurality of light-emitting units, at least one of which includes a light-emitting device. The light-emitting device is connected to a second power line, which is configured to provide a second power signal to the light-emitting device. At least one circuit unit further includes a first initial signal line, a second initial signal line, a third initial signal line extending along the first direction, and a first power line extending along the second direction. The pixel driving circuit is connected to the first initial signal line, the second initial signal line, the third initial signal line, and the first power line, respectively. The first initial signal line, the second initial signal line, and the third initial signal line are configured to provide a first initial signal, a second initial signal, and a third initial signal to the pixel driving circuit, respectively. The first power line is configured to provide a first power signal to the pixel driving circuit. The second constant voltage trace is connected to any one or more of the following: the first initial signal line, the second initial signal line, the third initial signal line, the first power line, or the second power line.

[0018] In an exemplary embodiment, the display substrate is divided into multiple sub-regions. The second constant voltage trace in one sub-region is connected to the first initial signal line, the second constant voltage trace in another sub-region is connected to the second initial signal line, and the second constant voltage trace in yet another sub-region is connected to the third initial signal line, thereby forming a mesh-connected structure for transmitting the first initial signal, a mesh-connected structure for transmitting the second initial signal, and a mesh-connected structure for transmitting the third initial signal.

[0019] In an exemplary embodiment, multiple second constant voltage traces are respectively connected to the first initial signal line, the second initial signal line, and the third initial signal line. In the first direction, the second constant voltage traces connected to the first initial signal line, the second constant voltage traces connected to the second initial signal line, and the second constant voltage traces connected to the third initial signal line are arranged periodically.

[0020] In an exemplary embodiment, multiple second constant voltage traces are respectively connected to the first initial signal line, the second initial signal line, the third initial signal line, and the second power line. In the first direction, the second constant voltage traces connected to the first initial signal line, the second constant voltage traces connected to the second power line, the second constant voltage traces connected to the second initial signal line, the second constant voltage traces connected to the second power line, the second constant voltage traces connected to the third initial signal line, and the second constant voltage traces connected to the second power line are periodically arranged.

[0021] In an exemplary embodiment, the second constant voltage trace located in the same insertion column as the second connection line is connected to the first power line or the second power line, and the second constant voltage trace separately disposed in the insertion column is connected to the first initial signal line, the second initial signal line or the third initial signal line.

[0022] In an exemplary embodiment, the display substrate includes multiple conductive layers in a direction perpendicular to the substrate. The second constant voltage trace, the first constant voltage trace, and at least one initial signal line are disposed in different conductive layers. A portion of the second constant voltage trace is connected to the first constant voltage trace, and another portion of the second constant voltage trace is connected to the initial signal line.

[0023] On the other hand, this disclosure also provides a display device including the aforementioned display substrate.

[0024] In another aspect, this disclosure also provides a method for fabricating a display substrate, including forming a driving structure layer on the substrate;

[0025] The driving structure layer includes multiple repeating units forming multiple repeating unit rows and multiple repeating unit columns, with insertion columns provided between adjacent repeating unit columns; at least one repeating unit includes multiple circuit units arranged sequentially along a first direction, at least one circuit unit including a pixel driving circuit and a data signal line extending along a second direction, the data signal line being connected to the pixel driving circuit and configured to provide data signals to the pixel driving circuit, the first direction and the second direction intersecting; the driving structure layer also includes at least one first connecting line and at least one first constant voltage trace extending along the first direction, and at least one second connecting line and at least one second constant voltage trace extending along the second direction, the first end of the first connecting line being connected to the data signal line, the second end of the first connecting line being connected to the second connecting line, and at least one second constant voltage trace being connected to at least one first constant voltage trace, forming a mesh-like interconnected structure for transmitting constant voltage signals; the second connecting line and the second constant voltage trace are disposed in the insertion columns.

[0026] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0027] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0028] Figure 1 is a schematic diagram of the structure of a display device;

[0029] Figure 2 is a schematic diagram of the structure of a display substrate;

[0030] Figures 3A and 3B are schematic diagrams of the planar structure of the display area in a display substrate;

[0031] Figure 4 is a schematic cross-sectional view of the display area in a display substrate;

[0032] Figures 5A and 5B are equivalent circuit diagrams of a pixel driving circuit.

[0033] Figure 6 is a schematic diagram of the planar structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0034] Figure 7 is a schematic diagram of the arrangement of a data connection line according to an exemplary embodiment of the present disclosure;

[0035] Figure 8 is a schematic diagram of the structure of a data connection line and a constant voltage trace according to an exemplary embodiment of the present disclosure;

[0036] Figures 9A to 9D are schematic diagrams of the structure of a display substrate according to an embodiment of the present disclosure;

[0037] Figure 10 is a schematic diagram of a display substrate after a semiconductor layer pattern has been formed in this disclosure;

[0038] Figures 11A and 11B are schematic diagrams of a display substrate after the formation of the first conductive layer pattern according to the present disclosure;

[0039] Figures 12A and 12B are schematic diagrams of a display substrate after a second conductive layer pattern has been formed in the present disclosure.

[0040] Figure 13 is a schematic diagram of a display substrate after a fourth insulating layer pattern has been formed in the present disclosure;

[0041] Figures 14A to 14D are schematic diagrams of a display substrate after the formation of a third conductive layer pattern according to the present disclosure;

[0042] Figures 15A and 15B are schematic diagrams of a display substrate after a first planarization layer pattern has been formed in the present disclosure.

[0043] Figures 16A to 16D are schematic diagrams of a display substrate after the formation of a fourth conductive layer pattern according to the present disclosure;

[0044] Figure 17 is a schematic diagram of a display substrate after the formation of a second planarization layer pattern according to the present disclosure;

[0045] Figures 18A and 18B are schematic diagrams of a display substrate after an anode conductive layer pattern has been formed in this disclosure.

[0046] Figure 19 is a schematic diagram of the structure of another display substrate according to an embodiment of the present disclosure;

[0047] Figure 20 is a schematic diagram of the structure of another display substrate according to an embodiment of the present disclosure;

[0048] Figure 21 is a schematic diagram of the structure of another display substrate according to an embodiment of the present disclosure;

[0049] Figure 22 is a schematic diagram of the structure of another display substrate according to an embodiment of the present disclosure;

[0050] Figure 23 is a schematic diagram of the structure of another display substrate according to an embodiment of the present disclosure;

[0051] Figure 24 is a schematic diagram of the structure of another display substrate according to an embodiment of the present disclosure;

[0052] Figure 25 is a schematic diagram of the structure of another display substrate according to an embodiment of the present disclosure;

[0053] Figure 26 is a schematic diagram of the structure of another display substrate according to an embodiment of the present disclosure;

[0054] Figure 27 is a schematic diagram of the structure of another display substrate according to an embodiment of the present disclosure;

[0055] Figure 28 is a schematic diagram of another data connection line and constant voltage wiring in an exemplary embodiment of the present disclosure;

[0056] Figure 29 is a schematic diagram of the structure of another data connection line and constant voltage wiring according to an exemplary embodiment of the present disclosure;

[0057] Figure 30 is a schematic diagram of another data connection line and constant voltage wiring according to an exemplary embodiment of the present disclosure.

[0058] Explanation of reference numerals in the attached figures: 10—First active connection line; 11—First active layer; 12—Second active layer; 13—Third active layer; 14—Fourth active layer; 15—Fifth active layer; 16—Sixth active layer; 17—Seventh active layer; 18—Eighth active layer; 19—Active connection strip; 21—First gate electrode; 22—Second gate electrode; 24—Fourth gate electrode; 25—First electrode plate; 26—Second electrode plate; 27—Compensation electrode; 28—Shielding electrode; 30—Third active connection line; 31—First scan signal line; 32—Second scan signal line; 33—Third scan signal line; 34—Fourth scan signal line; 35—Emitting light control line; 36—Scan connection line; 37—Repair line; 41—First initial signal line; 42—Second initial signal line; 43—Third initial signal line; 51—First connecting electrode; 52—Second connecting electrode; 53—Third connecting electrode; 54—Fourth connecting electrode; 55—Fifth connecting electrode; 56—Sixth connecting electrode; 57—Seventh connecting electrode; 58—Eighth connecting electrode; 61—First power line; 62—Power connection line; 63—Anode connecting electrode; 70—Data signal line; 80—Data connection line; 81—First connecting line; 82—Second connecting line; 83—Dummy connection block; 84—Data connection block; 90—Horizontal trace; 91—First constant voltage trace; 92—Second constant voltage trace; 93—Constant voltage connection line; 94—Fourth connection block; 95—Fifth connection block; 100—Display area; 101—Substrate; 102—Driver structure layer;103—Light-emitting structure layer; 104—Encapsulation structure layer; 110—First region; 120—Second region; 200—Binding region; 300—Border region. Detailed Implementation

[0059] To make the objectives, technical solutions, and advantages of this disclosure clearer, embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be varied in various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0060] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0061] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0062] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0063] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0064] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0065] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged, and the "source terminal" and "drain terminal" can be interchanged.

[0066] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0067] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0068] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0069] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfered corners, curved edges, and other variations.

[0070] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0071] Figure 1 is a schematic diagram of a display device. As shown in Figure 1, the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is connected to the data driver, the scan driver, and the light-emitting driver. The data driver is connected to multiple data signal lines (D1 to Dn), the scan driver is connected to multiple scan signal lines (S1 to Sm), and the light-emitting driver is connected to multiple light-emitting signal lines (E1 to Eo). The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, which is connected to the scan signal lines, the light-emitting signal lines, and the data signal lines. The light-emitting unit may include a light-emitting device, which is connected to the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller can provide grayscale values ​​and control signals of specifications suitable for the data driver to the data driver, provide clock signals, scan start signals, etc. of specifications suitable for the scan driver to the scan driver, and provide clock signals, transmit stop signals, etc. of specifications suitable for the light-emitting driver to the light-emitting driver. The data driver can use grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn in pixel rows, where n can be a natural number. The scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm by receiving clock signals, scan start signals, etc., from the timing controller. For example, the scan driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number. The light-emitting driver can generate transmit signals to be provided to light-emitting signal lines E1, E2, E3, ..., Eo by receiving clock signals, transmit stop signals, etc., from the timing controller. For example, the light-emitting driver can sequentially provide transmit signals with cutoff level pulses to the light-emitting signal lines E1 to Eo. For example, the light-emitting driver can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals in the form of cutoff level pulses to the next stage circuit under the control of a clock signal, where o can be a natural number. In an exemplary embodiment, a pixel array can be disposed on a display substrate.

[0072] Figure 2 is a schematic diagram of a display substrate. As shown in Figure 2, the display substrate may include a display area 100, a bonding area 200 located on one side of the display area 100, and a border area 300 located on other sides of the display area 100. In an exemplary embodiment, the display area 100 may be a flat area, including multiple sub-pixels Pxij that make up a pixel array. The multiple sub-pixels Pxij are configured to display dynamic or still images, and the display area 100 may be referred to as the active area (AA). In an exemplary embodiment, the display substrate may be a flexible substrate, and therefore the display substrate may be deformable, such as being rolled, bent, folded, or rolled up.

[0073] In an exemplary embodiment, the bonding region 200 may include a lead area, a bending area, a driver chip area, and a bonding pin area arranged sequentially along a direction away from the display area. The lead area is connected to the display area 100 and includes at least data leads. The bending area is connected to the lead area and may include at least a composite insulating layer with grooves configured to bend the bonding area to the back side of the display area. The driver chip area may include an integrated circuit (IC) configured to connect to multiple data leads. The bonding pin area may include bonding pads configured to bond to an external flexible printed circuit (FPC).

[0074] In an exemplary embodiment, the bezel region 300 may include a circuit region, a power line region, a crack dam region, and a cutting region sequentially arranged along a direction away from the display region 100. The circuit region is connected to the display region 100 and may include at least a gate driving circuit connected to scan signal lines and light emission signal lines in the display region 100. The power line region is connected to the circuit region and may include at least bezel power leads extending parallel to the edge of the display region and connected to a cathode in the display region 100. The crack dam region is connected to the power line region and may include at least a plurality of cracks formed on the composite insulating layer. The cutting region is connected to the crack dam region and may include at least a cutting groove formed on the composite insulating layer, configured such that after all film layers of the display substrate have been prepared, a cutting device cuts along the cutting grooves respectively.

[0075] In an exemplary embodiment, the lead-out area in the binding area 200 and the power line area in the border area 300 may be provided with isolation dams. The isolation dams may extend along a direction parallel to the edge of the display area to form a ring structure surrounding the display area 100. The edge of the display area is the edge of the binding area or the border area of ​​the display area.

[0076] Figure 3A is a schematic diagram of a planar structure of a display area in a display substrate. As shown in Figure 3A, the display area may include multiple pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1, a second sub-pixel P2, and a third sub-pixel P3. Each sub-pixel may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, which is connected to a scan signal line, a light-emitting signal line, and a data signal line, respectively. The pixel driving circuit is configured to receive the data voltage transmitted by the data signal line and output a corresponding current to the light-emitting unit under the control of the scan signal line and the light-emitting signal line. The light-emitting unit may include a light-emitting device, which is connected to the pixel driving circuit of the sub-pixel. The light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.

[0077] In an exemplary embodiment, the first sub-pixel P1 can be a red sub-pixel (R) that emits red light, the second sub-pixel P2 can be a green sub-pixel (G) that emits green light, and the third sub-pixel P3 can be a blue sub-pixel (B) that emits blue light. In an exemplary embodiment, the shape of the sub-pixels can be rectangular, rhomboid, pentagonal, or hexagonal, and the three sub-pixels can be arranged in Real RGB mode.

[0078] Figure 3B is a schematic diagram of the planar structure of the display area in another type of display substrate. As shown in Figure 3B, the pixel unit P can include four sub-pixels. The first sub-pixel P1 can be a red sub-pixel that emits red light, the second sub-pixel P2 and the fourth sub-pixel P4 can be green sub-pixels (G) that emit green light, and the third sub-pixel P3 can be a blue sub-pixel (B) that emits blue light. The four sub-pixels can be arranged in an RGBG pattern.

[0079] Figure 4 is a cross-sectional structural diagram of a display area in a display substrate, illustrating the structure of three sub-pixels in the display area. As shown in Figure 4, on a plane perpendicular to the display substrate, the display area may include a driving structure layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on the side of the driving structure layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on the side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementations, the display area may include other film layers, such as a touch structure layer, etc., which are not limited herein.

[0080] In an exemplary embodiment, the substrate 101 can be a flexible substrate or a rigid substrate. The driving structure layer 102 can include multiple circuit units, each of which can include at least a pixel driving circuit composed of multiple transistors and storage capacitors. The light-emitting structure layer 103 can include multiple light-emitting units, each of which can include a light-emitting device. The light-emitting device can include at least an anode, an organic light-emitting layer, and a cathode. The anode is connected to the pixel driving circuit, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of a corresponding color under the driving of the anode and cathode. The encapsulation structure layer 104 can include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers can be made of inorganic materials, and the second encapsulation layer can be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers, forming an inorganic / organic / inorganic material stacked structure, which can ensure that external moisture cannot enter the light-emitting structure layer 103.

[0081] Figure 5A is an equivalent circuit diagram of a pixel driving circuit. As shown in Figure 5A, the pixel driving circuit may include eight transistors (first transistor T1 to eighth transistor T8) and one storage capacitor C. The pixel driving circuit is connected to ten signal lines (first scan signal line S1, second scan signal line S2, third scan signal line S3, fourth scan signal line S4, light emission signal line EM, first initial signal line INIT1, second initial signal line INIT2, third initial signal line INIT3, data signal line DATA, and first power supply line VDD).

[0082] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the second terminal of a first transistor, the first terminal of a second transistor T2, the gate electrode of a third transistor T3, and the first terminal of a storage capacitor C. The second node N2 is connected to the first terminal of a third transistor T3, the second terminal of a fourth transistor T4, the second terminal of a fifth transistor T5, and the second terminal of an eighth transistor T8. The third node N3 is connected to the second terminals of a second transistor T2, a third transistor T3, and a sixth transistor T6. The fourth node N4 is connected to the second terminal of a sixth transistor T6 and a seventh transistor T7.

[0083] In an exemplary embodiment, the first end of the storage capacitor C is connected to the first node N1, and the second end of the storage capacitor C is connected to the first power line VDD.

[0084] In an exemplary embodiment, the gate electrode of the first transistor T1 is connected to the fourth scan signal line S4, the first electrode of the first transistor T1 is connected to the first initial signal line INIT1, and the second electrode of the first transistor is connected to the first node N1.

[0085] In an exemplary embodiment, the gate electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the first node N1, and the second electrode of the second transistor T2 is connected to the third node N3.

[0086] In an exemplary embodiment, the gate electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3.

[0087] In an exemplary embodiment, the gate electrode of the fourth transistor T4 is connected to the second scan signal line S2, the first electrode of the fourth transistor T4 is connected to the data signal line DATA, and the second electrode of the fourth transistor T4 is connected to the second node N2.

[0088] In an exemplary embodiment, the gate electrode of the fifth transistor T5 is connected to the light-emitting signal line EM, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the second node N2.

[0089] In an exemplary embodiment, the gate electrode of the sixth transistor T6 is connected to the light-emitting signal line EM, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the fourth node N4.

[0090] In an exemplary embodiment, the gate electrode of the seventh transistor T7 is connected to the third scan signal line S3, the first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is connected to the fourth node N4.

[0091] In an exemplary embodiment, the gate electrode of the eighth transistor T8 is connected to the third scan signal line S3, the first electrode of the eighth transistor T8 is connected to the third initial signal line INIT3, and the second electrode of the eighth transistor T8 is connected to the second node N2.

[0092] In an exemplary embodiment, the pixel driving circuit may further include a second node capacitor C. N2 The second node capacitor C N2 One end is connected to the second node N2, and the capacitor C of the second node is... N2 The other end is connected to the first power line VDD. In an exemplary embodiment, the second node capacitor C N2 It can stabilize the voltage of the second node N2.

[0093] In an exemplary embodiment, the pixel driving circuit can implement normal driving and low-frequency driving. In scenarios where the refresh rate requirement is not high, low-frequency refresh can be used to save power. During normal driving, the driving sequence of the pixel driving circuit can include four stages: initialization, compensation, data writing, and emission. During low-frequency driving, the driving sequence of the pixel driving circuit can include six stages: initialization, compensation, data writing, emission, adjustment, and re-emission. In the adjustment stage, the third initial signal (bias voltage) is written to the first electrode of the third transistor T3 using the eighth transistor T8. This ensures that the bias state of the third transistor T3 remains consistent with the bias state when the data signal was first written. This not only improves the stability of the driving transistor's operating state and reduces low-frequency flicker, but also effectively improves the hysteresis of the third transistor, which is beneficial for image retention and overall display performance.

[0094] In an exemplary embodiment, the first electrode of the light-emitting device EL is connected to the fourth node N4, and the second electrode of the light-emitting device EL is connected to the second power line VSS. The light-emitting device EL can be an OLED, including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or it can be a QLED, including a stacked first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode).

[0095] In an exemplary embodiment, the first power line VDD is configured to provide a constant first power signal to the pixel driving circuit, and the second power line VSS is configured to provide a constant second power signal to the light-emitting device. The voltage of the first power signal is higher than the voltage of the second power signal, the first power signal is a high-level signal, and the second power signal is a low-level signal. The first initial signal line INIT1, the second initial signal line INIT2, and the third initial signal line INIT3 are configured to provide constant first initial signal, second initial signal, and third initial signal to the pixel driving circuit, respectively; this disclosure is not limited thereto. In an exemplary embodiment, the third initial signal can be referred to as a reference signal, and the third initial signal line INIT3 can be referred to as a reference signal line.

[0096] In an exemplary embodiment, the first transistor T1 to the eighth transistor T8 in the pixel driving circuit can be either P-type transistors or N-type transistors. Using the same type of transistor in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 to the eighth transistor T8 may include both P-type and N-type transistors.

[0097] In an exemplary embodiment, the first transistor T1 to the eighth transistor T8 can be a low-temperature polycrystalline silicon (LTPS) transistor, or an oxide transistor, or a combination of both. The active layer of the LTPS transistor is made of low-temperature polycrystalline silicon (LTPS), while the active layer of the oxide transistor is made of oxide semiconductor. LTPS transistors have advantages such as high mobility and fast charging, while oxide transistors have advantages such as low leakage current. Integrating LTPS transistors and oxide transistors onto a single display substrate to form an LTPO (Low Temperature Polycrystalline + Oxide) display substrate leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0098] Figure 5B shows an equivalent circuit diagram of another pixel driving circuit. As shown in Figure 5B, the pixel driving circuit can be a 9T2C structure, which can include 9 transistors (11th transistor T11 to 19th transistor T19) and 2 storage capacitors (first capacitor C1 and second capacitor C2). The pixel driving circuit is connected to 12 signal lines (first scan signal line S1, second scan signal line S2, third scan signal line S3, fourth scan signal line S4, first light emission signal line EM1, second light emission signal line EM2, first initial signal line INIT1, second initial signal line INIT2, first reference signal line REF1, second reference signal line REF2, data signal line D, and first power supply line VDD).

[0099] In an exemplary embodiment, the pixel driving circuit may include an eleventh node N11, a twelfth node N12, a thirteenth node N13, a fourteenth node N14, and a fifteenth node N15. The eleventh node N11 is connected to the second terminal of the eleventh transistor T11, the first terminal of the twelfth transistor T12, the gate electrode of the thirteenth transistor T13, and the first terminal of the first capacitor C1. The twelfth node N12 is connected to the second terminal of the fourteenth transistor T14, the second terminal of the eighteenth transistor T18, the second terminal of the first capacitor C1, and the second terminal of the second capacitor C2. The thirteenth node N13 is connected to the first terminal of the thirteenth transistor T13, the second terminal of the fifteenth transistor T15, and the second terminal of the nineteenth transistor T19. The fourteenth node N14 is connected to the second terminal of the twelfth transistor T12, the second terminal of the thirteenth transistor T13, and the first terminal of the sixteenth transistor T16. The fifteenth node N15 is connected to the second terminal of the sixteenth transistor T16 and the second terminal of the seventeenth transistor T17.

[0100] In an exemplary embodiment, the first terminal of the first capacitor C1 is connected to the eleventh node N11, the second terminal of the first capacitor C1 is connected to the twelfth node N12, the first terminal of the second capacitor C2 is connected to the first power line VDD, and the second terminal of the second capacitor C2 is connected to the twelfth node N12.

[0101] In an exemplary embodiment, the gate electrode of the eleventh transistor T11 is connected to the fourth scan signal line S4, the first electrode of the eleventh transistor T11 is connected to the first initial signal line INIT1, and the second electrode of the eleventh transistor T11 is connected to the eleventh node N11.

[0102] In an exemplary embodiment, the gate electrode of the twelfth transistor T12 is connected to the second scan signal line S2, the first electrode of the twelfth transistor T12 is connected to the eleventh node N11, and the second electrode of the twelfth transistor T12 is connected to the fourteenth node N14.

[0103] In an exemplary embodiment, the gate electrode of the thirteenth transistor T13 is connected to the eleventh node N11, the first electrode of the thirteenth transistor T13 is connected to the thirteenth node N13, and the second electrode of the thirteenth transistor T13 is connected to the fourteenth node N14.

[0104] In an exemplary embodiment, the gate electrode of the fourteenth transistor T14 is connected to the third scan signal line S3, the first electrode of the fourteenth transistor T14 is connected to the data signal line DATA, and the second electrode of the fourteenth transistor T14 is connected to the twelfth node N12.

[0105] In an exemplary embodiment, the gate electrode of the fifteenth transistor T15 is connected to the first light-emitting signal line EM1, the first electrode of the fifteenth transistor T15 is connected to the first power supply line VDD, and the second electrode of the fifteenth transistor T15 is connected to the thirteenth node N13.

[0106] In an exemplary embodiment, the gate electrode of the sixteenth transistor T16 is connected to the second light-emitting signal line EM2, the first electrode of the sixteenth transistor T16 is connected to the fourteenth node N14, and the second electrode of the sixteenth transistor T16 is connected to the fifteenth node N15.

[0107] In an exemplary embodiment, the gate electrode of the seventeenth transistor T17 is connected to the first scan signal line S1, the first electrode of the seventeenth transistor T17 is connected to the second initial signal line INIT2, and the second electrode of the seventeenth transistor T17 is connected to the fifteenth node N15.

[0108] In an exemplary embodiment, the gate electrode of the eighteenth transistor T18 is connected to the second scan signal line S2, the first electrode of the eighteenth transistor T18 is connected to the first reference signal line REF1, and the second electrode of the eighteenth transistor T18 is connected to the twelfth node N12.

[0109] In an exemplary embodiment, the gate electrode of the nineteenth transistor T19 is connected to the first scan signal line S1, the first electrode of the nineteenth transistor T19 is connected to the second reference signal line REF2, and the second electrode of the nineteenth transistor T19 is connected to the thirteenth node N13.

[0110] In an exemplary embodiment, the first electrode of the light-emitting device EL is connected to the fifteenth node N15, and the second electrode of the light-emitting device EL is connected to the second power line VSS.

[0111] In an exemplary embodiment, the eleventh transistor T11 to the nineteenth transistor T19 can all be P-type transistors, or all be N-type transistors, or may include both P-type and N-type transistors. This pixel driving circuit can improve the hysteresis of the driving transistors, which is beneficial to improving the display effect.

[0112] With the development of OLED display technology, consumers have increasingly higher requirements for display effects and quality. Narrow bezels have become a new trend in display product development. Therefore, narrow bezels and even bezel-less designs are receiving more and more attention in OLED display product design. In one type of display substrate, because the data signals of the integrated circuits in the bonding area need to be introduced to the wider display area through data leads in a fan-out manner, the lead-out area occupies a large space, resulting in a relatively large bottom bezel, which has remained at around 2.0mm.

[0113] To reduce the width of the bottom bezel, an exemplary embodiment of this disclosure provides a display substrate employing a fanout-in-panel (FIP) structure. Multiple data connection lines are disposed in the display area, with one end of each line correspondingly connected to multiple data signal lines in the display area, and the other end extending to a bonding area, where it is connected to an integrated circuit via multiple data leads in a lead-out area. Since the lead-out area does not require fan-shaped diagonal lines, its width is reduced, thus decreasing the width of the bottom bezel.

[0114] An exemplary embodiment of this disclosure provides a display substrate, including a driving structure layer disposed on a substrate; the driving structure layer includes a plurality of repeating units forming a plurality of repeating unit rows and a plurality of repeating unit columns, with an insertion column disposed between adjacent repeating unit columns; at least one repeating unit includes a plurality of circuit units arranged sequentially along a first direction, the at least one circuit unit including a pixel driving circuit and a data signal line extending along a second direction, the data signal line being connected to the pixel driving circuit and configured to provide a data signal to the pixel driving circuit, the first direction and the second direction intersecting; the driving structure layer further includes at least one first connecting line and at least one first constant voltage trace extending along the first direction, and at least one second connecting line and at least one second constant voltage trace extending along the second direction, a first end of the first connecting line being connected to the data signal line, a second end of the first connecting line being connected to the second connecting line, and at least one second constant voltage trace being connected to at least one first constant voltage trace to form a mesh-like interconnected structure for transmitting constant voltage signals; the second connecting line and the second constant voltage trace are disposed in the insertion column.

[0115] In an exemplary embodiment, at least one repeating unit includes three circuit units.

[0116] In an exemplary embodiment, the display substrate further includes a light-emitting structure layer disposed on the side of the driving structure layer away from the substrate. The light-emitting structure layer includes a plurality of light-emitting units, at least one of which includes a light-emitting device. The light-emitting device is connected to a second power line, which is configured to provide a second power signal to the light-emitting device. At least one circuit unit further includes a first initial signal line, a second initial signal line, a third initial signal line extending along the first direction, and a first power line extending along the second direction. The pixel driving circuit is connected to the first initial signal line, the second initial signal line, the third initial signal line, and the first power line, respectively. The first initial signal line, the second initial signal line, and the third initial signal line are configured to provide a first initial signal, a second initial signal, and a third initial signal to the pixel driving circuit, respectively. The first power line is configured to provide a first power signal to the pixel driving circuit. The second constant voltage trace is connected to any one or more of the following: the first initial signal line, the second initial signal line, the third initial signal line, the first power line, or the second power line.

[0117] Figure 6 is a schematic planar structure diagram of a display substrate according to an exemplary embodiment of the present disclosure. As shown in Figure 6, in a plane parallel to the display substrate, the display substrate may include at least a display area 100, a bonding area 200 located on one side of the display area 100, and a border area 300 located on other sides of the display area 100. In a plane perpendicular to the display substrate, the display substrate may include a driving structure layer disposed on a substrate, a light-emitting structure layer disposed on the side of the driving structure layer away from the substrate, and an encapsulation structure layer disposed on the side of the light-emitting structure layer away from the substrate.

[0118] In an exemplary embodiment, the driving structure layer of the display area 100 may include multiple pixel driving circuits, multiple data signal lines 70, and multiple data connection lines 80. The pixel driving circuits are configured to output corresponding currents to the connected light-emitting devices. The light-emitting structure layer of the display area 100 may include multiple light-emitting devices, which are connected to corresponding pixel driving circuits and are configured to emit light of corresponding brightness in response to the current output by the connected pixel driving circuits.

[0119] In an exemplary embodiment, at least one data signal line 70 is connected to at least one pixel driving circuit. The data signal line 70 is configured to provide data signals to the connected pixel driving circuit. One end of at least one data connection line 80 is connected to the data signal line 70, and the other end is connected to the data lead-out line 80A in the bonding area 200, thereby realizing the connection between the data signal line 70 and the data lead-out line 80A.

[0120] In an exemplary embodiment, the bonding area 200 may include a lead area, a bending area, a driver chip area, and a bonding pin area arranged sequentially along a direction away from the display area. The lead area is connected to the display area 100, and the bending area is connected to the lead area. The lead area may have at least a plurality of data leads 80A, which extend along a direction away from the display area. The first end of a portion of the data leads 80A is connected to a data connection line 80 in the display area 100, and the first end of another portion of the data leads is connected to a data signal line 70 in the display area 100. The second end of all the data leads 80A extends along the second direction Y and crosses the bending area to connect to the integrated circuit in the driver chip area, so that the data signal of the integrated circuit is applied to the data signal line 70 through the data leads 80A and the data connection line 80. Since the data connection line 80 is located in the display area, the length of the lead area in the second direction Y can be effectively reduced, the bottom bezel width can be greatly reduced, the screen ratio can be improved, and it is beneficial to realize a full-screen display.

[0121] In an exemplary embodiment, the multiple data signal lines 70 in the display area can be divided into a first data signal line group and a second data signal line group according to whether they are connected to the data connection line 80. The data signal lines 70 in the first data signal line group are connected to the data connection line 80, while the data signal lines 70 in the second data signal line group are not connected to the data connection line 80. The multiple data lead-out lines 80A in the lead-out area can be divided into a first lead-out line group and a second lead-out line group according to whether they are connected to the data connection line 80. The data lead-out lines 80A in the first lead-out line group are connected to the data connection line 80, while the data lead-out lines 80A in the second lead-out line group are not connected to the data connection line 80. One end of each of the multiple data signal lines 70 in the first data signal line group is connected to one end of each of the multiple data connection lines 80, and the other end of each of the multiple data connection lines 80 is connected to one end of each of the multiple data lead-out lines 80A in the first lead-out line group. Similarly, the multiple data signal lines 70 in the second data signal line group are connected to one end of each of the multiple data lead-out lines 80A in the second lead-out line group.

[0122] In an exemplary embodiment, the display area 100 may have a center line O. The multiple data signal lines 70, multiple data connection lines 80 and multiple data lead-out lines 80A in the lead area 201 of the display area 100 may be symmetrically arranged with respect to the center line O. The center line O may be a straight line that bisects the display area 100 in the first direction X and extends along the second direction Y.

[0123] Figure 7 is a schematic diagram of the arrangement of a data connection line according to an exemplary embodiment of the present disclosure. As shown in Figure 7, the data connection line 80 may include at least a first connection line 81 and a second connection line 82. The shape of the first connection line 81 may be a straight line or a broken line extending along a first direction X. The shapes of the data signal line 70 and the second connection line 82 may be straight lines or broken lines extending along a second direction Y. The first direction X and the second direction Y intersect. The first end of the first connection line 81 can be connected to the data signal line 70 through a first connection hole. The second end of the first connection line 81 extends along the first direction X or the opposite direction of the first direction X and can be connected to the first end of the second connection line 82 through a second connection hole. The second end of the second connection line 82 extends along the second direction Y towards the lead area and is connected to the data lead line.

[0124] In an exemplary embodiment, the data lead-out line and the data signal line 70, and the data lead-out line and the data connection line 80 can be directly connected, or they can be connected through a connection hole. This disclosure does not limit the scope of the invention.

[0125] In an exemplary embodiment, since the data connection line includes a first connection line 81 extending along the first direction X and a second connection line 82 extending along the second direction Y, and is disposed in a portion of the display area, the display area can be divided into a first area 110 and a second area 120 based on the presence or absence of the data connection line. The first area 110 may be an area with either the first connection line 81 or the second connection line 82, and can be referred to as a FIP area. The second area 120 may be an area without either the first connection line 81 or the second connection line 82, and can be referred to as a non-FIP area.

[0126] This disclosure, by setting data connection lines within the display area, allows the data lead-out lines of the binding area to be connected to the data signal lines via the data connection lines. This eliminates the need for fan-shaped diagonal lines in the lead-out area, effectively reducing the length of the lead-out area, significantly reducing the bottom bezel width, increasing the screen-to-body ratio, and facilitating the realization of full-screen display.

[0127] Figure 8 is a schematic diagram of the structure of a data connection line and a constant voltage trace according to an exemplary embodiment of the present disclosure. As shown in Figure 8, in an exemplary embodiment, the driving structure layer of the display area 100 may include a plurality of repeating units Q forming a plurality of repeating unit rows and a plurality of repeating unit columns. The repeating unit Q is the basic unit constituting the driving structure layer, and the driving structure layer can be formed by repeating it and continuously arranging it along the first direction X and the second direction Y. At least one repeating unit Q may include a plurality of circuit units arranged sequentially along the first direction X, and at least one circuit unit may include a pixel driving circuit. The light-emitting structure layer of the display area 100 may include a plurality of light-emitting units, and at least one light-emitting unit may include a light-emitting device, which is connected to the pixel driving circuit of the corresponding circuit unit.

[0128] In exemplary embodiments, the circuit unit referred to in this disclosure refers to a region divided according to the pixel driving circuit, and the light-emitting unit referred to in this disclosure refers to a region divided according to the light-emitting device. In exemplary embodiments, the position of the orthographic projection of the light-emitting unit on the substrate may correspond to the position of the orthographic projection of the circuit unit on the substrate, or the position of the orthographic projection of the light-emitting unit on the substrate may not correspond to the position of the orthographic projection of the circuit unit on the substrate.

[0129] In an exemplary embodiment, a plurality of repeating units arranged sequentially along a first direction X can be referred to as a repeating unit row, and a plurality of repeating units arranged sequentially along a second direction Y can be referred to as a repeating unit column. A plurality of circuit units arranged sequentially along the first direction X can be referred to as a unit row, and a plurality of circuit units arranged sequentially along the second direction Y can be referred to as a unit column.

[0130] In an exemplary implementation, a repeating cell row may include one cell row, that is, a cell row and a repeating cell row are the same concept, and a repeating cell column may include three cell columns.

[0131] In an exemplary embodiment, the driving structure layer of the display area 100 may further include multiple insertion columns, which are respectively disposed between adjacent repeating unit columns. The insertion columns are configured to provide vertical traces, such as second connecting lines or second constant voltage traces. Specifically, the insertion column mentioned in this disclosure may be one where the distance between two circuit units with an insertion column is greater than the distance between two circuit units without an insertion column.

[0132] In an exemplary embodiment, the driving structure layer of the display area 100 may further include multiple data signal lines 70, multiple first connection lines 81, multiple second connection lines 82, multiple first constant voltage lines 91, and multiple second constant voltage lines 92. The shapes of the first connection lines 81 and the first constant voltage lines 91 may be straight lines or broken lines extending along the first direction X, and the shapes of the data signal lines 70, the second connection lines 82, and the second constant voltage lines 92 may be straight lines or broken lines extending along the second direction Y.

[0133] In an exemplary embodiment, multiple data signal lines 70 can be respectively disposed in each cell column and arranged sequentially along the first direction X. The data signal lines 70 are connected to the pixel driving circuits of multiple circuit units in the cell column. Multiple first connection lines 81 and multiple second connection lines 82 can be disposed in the first region 110. The multiple first connection lines 81 can be respectively disposed in the corresponding repeating cell rows and arranged sequentially along the second direction Y. The multiple second connection lines 82 can be respectively disposed in the corresponding insertion columns and arranged sequentially along the first direction X. Multiple first constant voltage lines 91 and multiple second constant voltage lines 92 can be disposed in the second region 120. The multiple first constant voltage lines 91 can be respectively disposed in the corresponding repeating cell rows and arranged sequentially along the second direction Y. The multiple second constant voltage lines 92 can be respectively disposed in the corresponding insertion columns and arranged sequentially along the first direction X. In an exemplary embodiment, some of the first constant voltage lines 91 and some of the second constant voltage lines 92 can extend into the first region 110.

[0134] In an exemplary embodiment, there may be a repeating unit (three circuit units) between two adjacent second connecting lines 82 in the first direction X, and there may be a repeating unit (three circuit units) between two adjacent second constant voltage lines 92 in the first direction X, that is, the second connecting lines 82 and the second constant voltage lines 92 are three-in-one structures.

[0135] In an exemplary embodiment, three data signal lines 70 may be provided between two adjacent second connecting lines 82 in the first direction X, and three data signal lines 70 may be provided between two adjacent second constant voltage lines 92 in the first direction X.

[0136] In an exemplary embodiment, the driving structure layer of the display substrate may include multiple conductive layers in a direction perpendicular to the display substrate. The first connecting line 81 and the second connecting line 82 may be disposed in different conductive layers, and the first connecting line 81 and the data signal line 70 may be disposed in different conductive layers. The first end of the first connecting line 81 may be connected to the data signal line 70 through a first connecting hole K1. The second end of the first connecting line 81 extends along a first direction X or the opposite direction of the first direction X and is connected to the first end of the second connecting line 82 through a second connecting hole K2. The second end of the second connecting line 82 extends along a second direction Y towards the lead area and is connected to the data lead.

[0137] In an exemplary embodiment, the first constant voltage trace 91 and the second constant voltage trace 92 can be disposed in different conductive layers. At least one second constant voltage trace 92 can be connected to at least one first constant voltage trace 91 through the third connection hole K3, forming a mesh-like interconnected structure for transmitting constant voltage signals in the display area.

[0138] In an exemplary embodiment, the first constant voltage trace 91 and the first connecting line 81 can be arranged on the same layer and formed synchronously through the same patterning process. The data signal line 70, the second connecting line 82 and the second constant voltage trace 92 can be arranged on the same layer and formed synchronously through the same patterning process.

[0139] In an exemplary embodiment, at least one repeating cell row may include at least one first connecting line 81 and at least one first constant voltage trace 91. A first break DF1 may be provided between the first connecting line 81 and the first constant voltage trace 91, and the first break DF1 is configured to achieve mutual insulation between the first connecting line 81 and the first constant voltage trace 91. In an exemplary embodiment, the cell row may be a cell row including a first region 110 and a second region 120.

[0140] In an exemplary embodiment, at least one repeating cell row may contain only one first constant voltage trace 91, and no first connecting trace 81 may be provided in that cell row. In an exemplary embodiment, that cell row may be a cell row of the second region 120.

[0141] In an exemplary embodiment, at least one insertion column may be provided with at least one second connecting line 82 and at least one second constant voltage trace 92. A second break DF2 may be provided between the second connecting line 82 and the second constant voltage trace 92, and the second break DF2 is configured to achieve mutual insulation between the second connecting line 82 and the second constant voltage trace 92. In an exemplary embodiment, the insertion column may be an insertion column including a first region 110 and a second region 120.

[0142] In an exemplary embodiment, at least one insertion column may contain only one second constant voltage trace 92, and no second connecting line 82 may be provided in the insertion column. In an exemplary embodiment, the insertion column may be an insertion column of the second region 120.

[0143] Figures 9A, 9B, 9C, and 9D are schematic diagrams of the structure of a display substrate according to an exemplary embodiment of the present disclosure. Figure 9A is a schematic diagram of the structure of region A in Figure 8, Figure 9B is a schematic diagram of the first connecting line and the second connecting line in Figure 9A, Figure 9C is a schematic diagram of the structure of region B in Figure 8, and Figure 9D is a schematic diagram of the first constant voltage trace and the second constant voltage trace in Figure 9C. Figures 9A and 9B illustrate the structure of six circuit units in the first region, consisting of one unit row (M-4th unit row) and six unit columns (N+9th to N+14th unit columns). Figures 9C and 9D illustrate the structure of six circuit units in the second region, consisting of one unit row (M-4th unit row) and six unit columns (N+9th to N+14th unit columns).

[0144] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate may include at least a driving structure layer disposed on the substrate and a light-emitting structure layer disposed on the side of the driving structure layer away from the substrate. In a plane parallel to the substrate, the driving structure layer may include a plurality of repeating units Q forming a plurality of repeating unit rows and a plurality of repeating unit columns, with an insertion column IN disposed between adjacent repeating unit columns. At least one repeating unit Q may include three circuit units arranged sequentially along a first direction X, and at least one circuit unit may include a pixel driving circuit, which may be connected to a first scan signal line 31, a second scan signal line 32, a third scan signal line 33, a fourth scan signal line 34, a light-emitting signal line 35, a first initial signal line 41, a second initial signal line 42, a third initial signal line 43, a first power supply line 61, and a data signal line 70, respectively.

[0145] In an exemplary embodiment, the first scan signal line 31, the second scan signal line 32, the third scan signal line 33, and the fourth scan signal line 34 are configured to provide a first scan signal, a second scan signal, a third scan signal, and a fourth scan signal to the pixel driving circuit, respectively. The light emission signal line 35 is configured to provide a light emission control signal to the pixel driving circuit. The first initial signal line 41, the second initial signal line 42, and the third initial signal line 43 are configured to provide a first initial signal, a second initial signal, and a third initial signal to the pixel driving circuit, respectively. The first power supply line 61 is configured to provide a first power supply signal to the pixel driving circuit. The data signal line 70 is configured to provide a data signal to the pixel driving circuit. The multiple signal lines connected to the pixel driving circuit can be located within a circuit unit.

[0146] In an exemplary embodiment, the shapes of the first scan signal line 31, the second scan signal line 32, the third scan signal line 33, the fourth scan signal line 34, the light emission signal line 35, the first initial signal line 41, the second initial signal line 42, and the third initial signal line 43 can be straight lines or broken lines extending along the first direction X of the main body, and the shapes of the first power line 61 and the data signal line 70 can be straight lines or broken lines extending along the second direction Y of the main body.

[0147] In this disclosure, "A extends along direction B" means that A may include a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped body. The main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In the following description, "A extends along direction B" refers to "the main body of A extends along direction B".

[0148] In an exemplary embodiment, the pixel driving circuit may include a storage capacitor and eight transistors. The storage capacitor may include a first electrode and a second electrode stacked together, wherein the orthographic projection of the second electrode onto the substrate at least partially overlaps with the orthographic projection of the first electrode onto the substrate. The eight transistors may include a first transistor T1 as a first initialization transistor, a second transistor T2 as a compensation transistor, a third transistor T3 as a driving transistor, a fourth transistor T4 as a data writing transistor, a fifth transistor T5 as a first light-emitting control transistor, a sixth transistor T6 as a second light-emitting control transistor, a seventh transistor T7 as a second initialization transistor, and an eighth transistor T8 as a third initialization transistor. In an exemplary embodiment, all eight transistors may be low-temperature polysilicon transistors (P-type transistors).

[0149] In an exemplary embodiment, the gate electrode of the first transistor T1 is connected to the fourth scan signal line 34, the first terminal of the first transistor T1 is connected to the first initial signal line 41, and the second terminal of the first transistor T1 is connected to the first terminal of the second transistor T2 and the first plate (which is also the gate electrode of the third transistor T3). The gate electrode of the second transistor T2 is connected to the first scan signal line 31, and the second terminal of the second transistor T2 is connected to the second terminal of the third transistor T3 and the first terminal of the sixth transistor T6. The gate electrode of the fourth transistor T4 is connected to the second scan signal line 32, the first terminal of the fourth transistor T4 is connected to the first data signal line 70, and the second terminal of the fourth transistor T4 is connected to the first terminal of the third transistor T3, the second terminal of the fifth transistor T5, and the second terminal of the eighth transistor T8. The gate electrode of the fifth transistor T5 is connected to the light emission signal line 35, and the first terminal of the fifth transistor T5 is connected to the first power supply line 61. The gate electrode of the sixth transistor T6 is connected to the light emission signal line 35, and the second terminal of the sixth transistor T6 is connected to the second terminal of the seventh transistor T7. The gate electrode of the seventh transistor T7 is connected to the third scan signal line 33, and the first electrode of the seventh transistor T7 is connected to the second initial signal line 42. The gate electrode of the eighth transistor T8 is connected to the third scan signal line 33, and the first electrode of the eighth transistor T8 is connected to the third initial signal line 43.

[0150] In an exemplary embodiment, in at least one circuit unit, a first scan signal line 31 may be disposed on the side opposite to the second direction Y of the storage capacitor; a second scan signal line 32 may be disposed on the side of the first scan signal line 31 away from the storage capacitor; a fourth scan signal line 34 may be disposed on the side of the second scan signal line 32 away from the storage capacitor; and a first initial signal line 41 may be disposed on the side of the fourth scan signal line 34 away from the storage capacitor. A light-emitting signal line 35 may be disposed on the side of the storage capacitor in the second direction Y; a third scan signal line 33 may be disposed on the side of the light-emitting signal line 35 away from the storage capacitor; a second initial signal line 42 may be disposed on the side of the third scan signal line 33 away from the storage capacitor; and a third initial signal line 43 may be disposed on the side of the second initial signal line 42 away from the storage capacitor.

[0151] In an exemplary embodiment, the driving structure layer may further include at least one power connection line 62. The power connection line 62 may be in the shape of a zigzag line extending along the first direction X, and may be disposed between the first scan signal line 31 and the light emission signal line 35. The power connection line 62 is connected to the second electrode plate through a via, and the first power line 61 is connected to the power connection line 62 through a via. The first power line 61 and the power connection line 62 form a mesh-like interconnected structure for transmitting the first power signal.

[0152] In an exemplary embodiment, the driving structure layer may further include at least one first connecting line 81, at least one second connecting line 82, at least one first constant voltage trace 91, and at least one second constant voltage trace 92. The first connecting line 81 and the first constant voltage trace 91 may be straight or broken lines extending along a first direction X, and the second connecting line 82 and the second constant voltage trace 92 may be straight or broken lines extending along a second direction Y. The first connecting line 81 is configured to connect to the data signal line 70 and the second connecting line 82 respectively, forming a structure where the data connection lines are located in the display area. The first constant voltage trace 91 and the second constant voltage trace 92 are configured to be interconnected, forming a mesh-like interconnected structure for transmitting constant voltage signals.

[0153] In an exemplary embodiment, the display substrate may include multiple conductive layers disposed on a substrate in a direction perpendicular to the display substrate. The first connecting line 81 and the second connecting line 82 may be disposed in different conductive layers, the first connecting line 81 and the first constant voltage trace 91 may be disposed in the same layer, and the second connecting line 82 and the second constant voltage trace 92 may be disposed in the same layer.

[0154] As shown in Figures 9A and 9B, in the first region, the first connecting line 81 can be disposed between the first scan signal line 31 and the second plate, and the second connecting line 82 can be disposed in the insert column IN. Three first power lines 61 and three data signal lines 70 can be disposed between two adjacent second connecting lines 82, that is, three circuit units (one repeating unit Q) can be spaced between two adjacent second connecting lines 82.

[0155] In an exemplary embodiment, at least one first power line 61 may be disposed between the data signal line 70 and the second connection line 82 in the first direction X.

[0156] In an exemplary embodiment, at least one repeating cell row may be provided with at least one first connecting line 81 and at least one first constant voltage trace 91. A first break DF1 may be provided between the first connecting line 81 and the first constant voltage trace 91, and the first break DF1 is configured to achieve mutual insulation between the first connecting line 81 and the first constant voltage trace 91. At least one insert column IN may be provided with at least one second connecting line 82 and at least one second constant voltage trace 92. A second break DF2 may be provided between the second connecting line 82 and the second constant voltage trace 92, and the second break DF2 is configured to achieve mutual insulation between the second connecting line 82 and the second constant voltage trace 92.

[0157] In an exemplary embodiment, each circuit unit in the first region may be provided with a third connection electrode 53, which serves as a data connection electrode of this disclosure. The data signal line 70 can be connected to the third connection electrode 53 via a via. At least one circuit unit in the first region may be provided with a data connection block 84. The data connection block 84 may be disposed between the first connection line 81 and the third connection electrode 53, and both ends of the data connection block 84 are respectively connected to the first connection line 81 and the third connection electrode 53, thereby realizing the connection between the first end of the first connection line 81 and the data signal line 70. For example, the data connection block 84 may be disposed in the circuit unit of the Mth unit row and the N+1th unit column, realizing the connection between the first connection line 81 in the Mth unit row and the data signal line 70 in the N+1th unit column.

[0158] In an exemplary embodiment, in at least one repeating unit row, a data connection block 84 may be disposed on the side of the first scan signal line 31 near the second electrode plate, and the third connection electrodes 53 of multiple circuit units may be disposed on the side of the first scan signal line 31 near the second electrode plate, and located on the same straight line extending along the first direction X.

[0159] In an exemplary embodiment, in at least one insertion column of the first region, the second connection line 82 can be connected to the first connection line 81 via a via, thus achieving a connection between the second end of the first connection line 81 and the second connection line 82. For example, in the insertion column between the N+3 and N+4 cell columns, the second connection line 82 is connected to the first connection line 81 in the M cell row via a via.

[0160] As shown in Figures 9C and 9D, in the second region, the first constant voltage trace 91 can be positioned between the first scan signal line 31 and the second electrode, and the second constant voltage trace 92 can be positioned in the insert column IN. Three first power supply lines 61 and three data signal lines 70 can be positioned between two adjacent second constant voltage traces 92, meaning that three circuit units (one repeating unit Q) can be spaced between two adjacent second constant voltage traces 92.

[0161] In an exemplary embodiment, at least one first power line 61 may be disposed between the data signal line 70 and the second constant voltage trace 92 in the first direction X.

[0162] In an exemplary embodiment, at least one repeating cell row may include only the first constant voltage trace 91 without providing a first connecting line. At least one insert column IN may include only the second constant voltage trace 92 without providing a second connecting line 82.

[0163] In an exemplary embodiment, in at least one insertion column of the second region, the second constant voltage trace 92 can be connected to the first constant voltage trace 91 via a via, thus realizing the connection between the first constant voltage trace 91 and the second constant voltage trace 92, forming a mesh-like interconnected structure for transmitting constant voltage signals. For example, in the insertion column between the N+9th and N+10th unit columns, the second constant voltage trace 92 is connected to the first constant voltage trace 91 in the M-4th unit row via a via. Similarly, in the insertion column between the N+12th and N+13th unit columns, the second constant voltage trace 92 is connected to the first constant voltage trace 91 in the M-4th unit row via a via.

[0164] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate may include a first conductive layer disposed on a substrate, a second conductive layer disposed on a side of the first conductive layer away from the substrate, a third conductive layer disposed on a side of the second conductive layer away from the substrate, and a fourth conductive layer disposed on a side of the third conductive layer away from the substrate. The first connecting line 81 and the first constant voltage trace 91 may be disposed in the third conductive layer, and the second connecting line 82 and the second constant voltage trace 92 may be disposed in the fourth conductive layer.

[0165] The following description uses the fabrication process of a display substrate as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as depositing a film, coating with photoresist, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as coating with organic materials, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0166] In an exemplary embodiment, taking six circuit units in a repeating unit row as an example, the fabrication process of the display substrate in this embodiment may include the following operations. A repeating unit Q includes three circuit units.

[0167] (11) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on a substrate, patterning the semiconductor film using a patterning process to form a first insulating layer covering the substrate, and a semiconductor layer disposed on the first insulating layer, as shown in FIG10. FIG10 is a schematic diagram of the structure of region A in FIG8, and the semiconductor layer pattern of region B in FIG8 is substantially the same as that of region A in FIG8.

[0168] In an exemplary embodiment, the semiconductor layer of each circuit unit in the display area may include at least the first active layer 11 of the first transistor T1 to the eighth active layer 18 of the eighth transistor T8, and the first active layer 11 to the seventh active layer 17 may be an integral structure interconnected, while the eighth active layer 18 may be set separately.

[0169] In an exemplary embodiment, the first active layer 11, the second active layer 12 and the fourth active layer 14 may be located on the side opposite to the second direction Y of the third active layer 13 of the circuit unit, and the fifth active layer 15, the sixth active layer 16, the seventh active layer 17 and the eighth active layer 18 may be located on the side of the second direction Y of the third active layer 13 of the circuit unit.

[0170] In an exemplary embodiment, the first active layer 11, the fourth active layer 14, the fifth active layer 15, the seventh active layer 17 and the eighth active layer 18 can be strip-shaped extending along the second direction Y, the second active layer 12 and the sixth active layer 16 can be L-shaped, and the third active layer 13 can be an inverted Ω-shaped.

[0171] In an exemplary embodiment, the active layer of each transistor may include a first region, a second region, and a channel region located between the first and second regions. In an exemplary embodiment, the second region 11-2 of the first active layer and the first region 12-1 of the second active layer may be interconnected, and the second region 11-2 of the first active layer may serve as the first region 12-1 of the second active layer. The first region 13-1 of the third active layer 13, the second region 14-2 of the fourth active layer, and the second region 15-2 of the fifth active layer may be interconnected, and the first region 13-1 of the third active layer may simultaneously serve as both the second region 14-2 of the fourth active layer and the second region 15-2 of the fifth active layer. The second region 12-2 of the second active layer, the second region 13-2 of the third active layer, and the first region 16-1 of the sixth active layer may be interconnected, and the second region 12-2 of the second active layer may simultaneously serve as both the second region 13-2 of the third active layer and the first region 16-1 of the sixth active layer. The second region 16-2 of the sixth active layer and the second region 17-2 of the seventh active layer can be interconnected, and the second region 16-2 of the sixth active layer can serve as the second region 17-2 of the seventh active layer. The first region 11-1 of the first active layer, the first region 14-1 of the fourth active layer, the first region 15-1 of the fifth active layer, the first region 17-1 of the seventh active layer, the first region 18-1 of the eighth active layer, and the second region 18-2 of the eighth active layer can be set independently.

[0172] In an exemplary embodiment, the eighth active layer 18 may be disposed separately on the side opposite to the first direction X of the seventh active layer 17, the first region 18-1 of the eighth active layer may be disposed on the side of the channel region of the eighth active layer away from the third active layer 13, and the second region 18-2 of the eighth active layer may be disposed on the side of the channel region of the eighth active layer close to the third active layer 13.

[0173] In an exemplary embodiment, a first active block 11A may be disposed on the first active layer 11. The shape of the first active block 11A may be a strip extending along the first direction X, and it may be disposed on one side of the first active layer 11 in the first direction X and connected to the first active layer 11.

[0174] In an exemplary embodiment, in at least one circuit unit, the first active layer 11 and the first active block 11A can be an integral structure that is interconnected.

[0175] In an exemplary embodiment, a second active block 12A may be disposed on the second active layer 12. The shape of the second active block 12A may be block-shaped (such as trapezoidal), and it may be disposed at the corner of the "L" shape and connected to the second active layer 12.

[0176] In an exemplary embodiment, in at least one circuit unit, the second active layer 12 and the second active block 12A can be an integral structure that is interconnected.

[0177] In an exemplary embodiment, the semiconductor layer may further include a first active interconnect line 10 and a third active interconnect line 30.

[0178] In an exemplary embodiment, the first active connection line 10 can be a straight line or a broken line extending along the first direction X. It can be disposed on the side of the first active layer 11 away from the third active layer 13 and connected to the first region 11-1 of the first active layer of each circuit unit. The first active connection line 10 can be multiplexed as a first initial trace extending along the first direction X, which can ensure that the first regions of multiple first active layers in a unit row have the same potential.

[0179] In an exemplary embodiment, in at least one repeating unit, a first active connection block 10A may be disposed on the first active connection line 10. The first active connection block 10A may be block-shaped (e.g., rectangular), and may be disposed on the side of the first active connection line 10 away from the third active layer 13, and connected to the first active connection line 10. The first active connection block 10A is configured to be connected to the first initial signal line through a subsequently formed sixth connection electrode, so that the first active connection line and the first initial signal line form a double-layer signal line structure.

[0180] In an exemplary embodiment, the first active connection block 10A may be disposed in the boundary region between the (N+1)th and (N+2)th unit columns, and may be disposed in the boundary region between the (N+4)th and (N+5)th unit columns. In at least one repeating unit, the first active connection line 10 and the first active connection block 10A may be an integral structure that is interconnected.

[0181] In an exemplary embodiment, the third active connection line 30 can be a straight line or a broken line extending along the first direction X. It can be disposed on the side of the seventh active layer 17 away from the third active layer 13 and connected to the first region 17-1 of the seventh active layer of each circuit unit. The third active connection line 30 can be reused as a third initial trace extending along the first direction X, which can ensure that the first regions of multiple seventh active layers in a unit row have the same potential.

[0182] In an exemplary embodiment, in at least one repeating unit, a third active connection block 30A may be disposed on the third active connection line 30. The third active connection block 30A may be block-shaped (e.g., rectangular), and may be disposed on the side of the third active connection line 30 near the third active layer 13 and connected to the third active connection block 30A. The third active connection block 30A is configured to be connected to the third initial signal line through a subsequently formed seventh connection electrode, so that the third active connection line and the third initial signal line form a double-layer signal line structure.

[0183] In an exemplary embodiment, the third active connection block 30A can be disposed in the circuit cells of the N+1th and N+4th cell columns, respectively. In at least one repeating cell, the third active connection line 30 and the third active connection block 30A can be an integral structure interconnected with each other.

[0184] In an exemplary embodiment, in at least one repeating unit, the eighth active layer 18 may be disposed on the side of the third active connection block 30A close to the third active layer 13 and connected to the third active connection block 30A.

[0185] In an exemplary embodiment, the second region 12-2 of the second active layer can serve as the second terminal of the second transistor T2, the second region 13-2 of the third active layer can serve as the second terminal of the third transistor (driving transistor) T3, and the first region 16-1 of the sixth active layer can serve as the first terminal of the sixth transistor T6. The interconnected region of the second region 12-2 of the second active layer, the second region 13-2 of the third active layer, and the first region 16-1 of the sixth active layer forms the third node N3 of the pixel driving circuit. The second region 16-2 of the sixth active layer can serve as the second terminal of the sixth transistor T6, and the second region 17-2 of the seventh active layer can serve as the second terminal of the seventh transistor T7. The interconnected region of the second region 16-2 of the sixth active layer and the second region 17-2 of the seventh active layer forms the fourth node N4 of the pixel driving circuit.

[0186] (12) Forming a first conductive layer pattern. In an exemplary embodiment, forming a first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on a substrate on which the aforementioned pattern is formed; patterning the first conductive film using a patterning process to form a second insulating layer covering the semiconductor layer pattern; and a first conductive layer pattern disposed on the second insulating layer, as shown in Figures 11A and 11B, where Figure 11B is a planar schematic diagram of the first conductive layer in Figure 11A. Figure 11A is a structural schematic diagram of region A in Figure 8, and the first conductive layer pattern of region B in Figure 8 is substantially the same as that of region A in Figure 8. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0187] In an exemplary embodiment, the first conductive layer pattern of each circuit unit in the display area includes at least: a first gate electrode 21, a second gate electrode 22, a fourth gate electrode 24, a first plate 25 of a storage capacitor, a light emission control line 35, and a scan connection line 36.

[0188] In an exemplary embodiment, the first electrode 25 of the storage capacitor can be rectangular in shape, and the corners of the rectangle can be chamfered or grooved. The orthographic projection of the first electrode 25 on the substrate and the orthographic projection of the third active layer 13 on the substrate at least partially overlap. The first electrode 25 can simultaneously serve as an electrode of the storage capacitor and the gate electrode of the third transistor T3.

[0189] In an exemplary embodiment, the first gate electrode 21 can be in the shape of a "C" and can be disposed on the side opposite to the second direction Y of the first electrode plate 25. The orthographic projection of the first gate electrode 21 on the substrate and the orthographic projection of the first active layer 11 on the substrate at least partially overlap. The two regions where the first gate electrode 21 and the first active layer 11 overlap can serve as the two gate electrodes of the first transistor T1 with a dual-gate structure.

[0190] In an exemplary embodiment, in the second direction Y, the first active block 11A may be located between the two gate electrodes of the first transistor T1.

[0191] In an exemplary embodiment, a first gate connection block 21-1 may be provided on the first gate electrode 21. The first gate connection block 21-1 may be block-shaped (such as rectangular), may be provided on the side of the first gate electrode 21 away from the third active layer 13, and may be connected to the first gate electrode 21. The first gate connection block 21-1 is configured to be connected to the subsequently formed fourth scan signal line.

[0192] In an exemplary embodiment, in at least one circuit unit, the first gate electrode 21 and the first gate connection block 21-1 can be an integral structure that is interconnected.

[0193] In an exemplary embodiment, the shape of the second gate electrode 22 can be "L" shaped, and it can be disposed on the side opposite to the second direction Y of the first electrode plate 25. The orthogonal projection of the second gate electrode 22 on the substrate and the orthogonal projection of the second active layer 12 on the substrate at least partially overlap. The two regions where the second gate electrode 22 and the second active layer 12 overlap can serve as the two gate electrodes of the second transistor T2 with a dual-gate structure.

[0194] In an exemplary embodiment, the second active block 12A may be located between the two gate electrodes of the second transistor T2.

[0195] In an exemplary embodiment, a second gate connection block 22-1 may be provided on the second gate electrode 22. The second gate connection block 22-1 may be block-shaped (e.g., rectangular), and may be disposed on the side of the second gate electrode 22 away from the third active layer 13 and connected to the second gate electrode 22. The second gate connection block 22-1 is configured to be connected to the subsequently formed first scan signal line.

[0196] In an exemplary embodiment, in at least one circuit unit, the second gate electrode 22 and the second gate connection block 22-1 can be an integral structure that is interconnected.

[0197] In an exemplary embodiment, the fourth gate electrode 24 can be L-shaped and can be disposed on the side opposite to the second direction Y of the first electrode plate 25. The orthogonal projection of the fourth gate electrode 24 on the substrate and the orthogonal projection of the fourth active layer 14 on the substrate at least partially overlap. The area where the fourth gate electrode 24 and the fourth active layer 14 overlap can serve as the gate electrode of the fourth transistor T4.

[0198] In an exemplary embodiment, a fourth gate connection block 24-1 may be disposed on the fourth gate electrode 24. The fourth gate connection block 24-1 may be block-shaped (e.g., rectangular), may be disposed on the side of the fourth gate electrode 24 away from the third active layer 13, and may be connected to the fourth gate electrode 24. The fourth gate connection block 24-1 is configured to be connected to the second scan signal line subsequently formed.

[0199] In an exemplary embodiment, in at least one circuit unit, the fourth gate electrode 24 and the fourth gate connection block 24-1 can be an integral structure that is interconnected.

[0200] In an exemplary embodiment, the shape of the light-emitting control line 35 can be a straight line or a broken line extending along the first direction X of the main body, and can be disposed on one side of the first electrode plate 25 in the second direction Y. The orthographic projection of the light-emitting control line 35 on the substrate at least partially overlaps with the orthographic projection of the fifth active layer 15 on the substrate, and the overlapping area can serve as the gate electrode of the fifth transistor T5. The orthographic projection of the light-emitting control line 35 on the substrate at least partially overlaps with the orthographic projection of the sixth active layer 16 on the substrate, and the overlapping area can serve as the gate electrode of the sixth transistor T6.

[0201] In an exemplary embodiment, the shape of the scanning connection line 36 can be a straight line or a broken line extending along the first direction X of the main body, and it can be disposed on the side of the light-emitting control line 35 away from the first electrode plate 25. The orthographic projection of the scanning connection line 36 on the substrate at least partially overlaps with the orthographic projection of the seventh active layer 17 on the substrate, and the overlapping area can serve as the gate electrode of the seventh transistor T7. The orthographic projection of the scanning connection line 36 on the substrate at least partially overlaps with the orthographic projection of the eighth active layer 18 on the substrate, and the overlapping area can serve as the gate electrode of the eighth transistor T8.

[0202] In an exemplary embodiment, in at least one repeating unit, a connection line break DF0 may be provided on the scanning connection line 36, which cuts off the scanning connection line 36 to reduce static electricity accumulation.

[0203] In an exemplary embodiment, the connection break DF0 can be provided in the circuit cells of the N+2 and N+5th cell columns.

[0204] In an exemplary embodiment, in at least one repeating unit, a scan connection block 36-1 may be provided on the scan connection line 36. The scan connection block 36-1 may be block-shaped (such as rectangular), may be located on the side of the scan connection line 36 away from the first electrode plate 25, and may be connected to the scan connection line 36. The scan connection block 36-1 is configured to be connected to the subsequently formed third scan signal line.

[0205] In an exemplary embodiment, the first scan connection block 36-1 may be disposed in the circuit cells of the N+1th and N+4th cell columns. In at least one repeating cell, the scan connection line 36 and the first scan connection block 36-1 may be an integral structure interconnected with each other.

[0206] In an exemplary embodiment, after the first conductive layer pattern is formed, the first conductive layer can be used as a shield to conduct the semiconductor layer. The semiconductor layer in the region shielded by the first conductive layer forms the channel region of the first transistor T1 to the eighth transistor T8. The semiconductor layer in the region not shielded by the first conductive layer is conducted, that is, the first and second regions of the first active layer to the eighth active layer, the first active connection line and the third active connection line are all conducted.

[0207] (13) Forming a second conductive layer pattern. In an exemplary embodiment, forming a second conductive layer pattern may include: depositing a third insulating film and a second conductive film sequentially on a substrate on which the aforementioned pattern is formed, patterning the second conductive film using a patterning process to form a third insulating layer covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer, as shown in Figures 12A and 12B, where Figure 12B is a planar schematic diagram of the second conductive layer in Figure 12A.

[0208] Figure 12A is a schematic diagram of the structure of region A in Figure 8. The pattern of the second conductive layer in region B of Figure 8 is basically the same as that in region A of Figure 8. In an exemplary embodiment, the second conductive layer may be referred to as the second gate metal (GATE2) layer.

[0209] In an exemplary embodiment, the second conductive layer pattern of each circuit unit in the display area includes at least: a second electrode 26 for a storage capacitor, a compensation electrode 27, a shielding electrode 28, a repair line 37, a first initial signal line 41, and a third initial signal line 43.

[0210] In an exemplary embodiment, the outline shape of the second electrode plate 26 of the storage capacitor can be rectangular, and the corners of the rectangle can be chamfered or grooved. The orthographic projection of the second electrode plate 26 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 25 on the substrate. The second electrode plate 26 can serve as another electrode plate of the storage capacitor, and the first electrode plate 25 and the second electrode plate 26 constitute the storage capacitor of the pixel driving circuit.

[0211] In an exemplary embodiment, the compensation electrode 27 can be block-shaped (e.g., rectangular), and can be disposed on the side opposite to the first direction X of the second electrode plate 26, and connected to the second electrode plate 26. The orthographic projection of the compensation electrode 27 on the substrate at least partially overlaps with the orthographic projection of the connection region of the first region of the third active layer and the second region of the fourth active layer (i.e., the second node N2 of the pixel driving circuit) on the substrate. In an exemplary embodiment, the connection region of the first region of the third active layer and the second region of the fourth active layer can serve as a capacitor electrode, and can have the potential of the second node N2. The compensation electrode 27 can serve as another capacitor electrode. Since the second electrode plate 26 is configured to be connected to the subsequently formed first power line, the compensation electrode 27 has the potential of the first power line. The compensation electrode 27 and the second node N2 of the pixel driving circuit form a second node capacitor C. N2 The second node capacitor C N2 It can stabilize the voltage of the second node N2.

[0212] In an exemplary embodiment, in at least one circuit unit, the second electrode 26 and the compensation electrode 27 can be an integral structure that is interconnected.

[0213] In an exemplary embodiment, a plate connecting line 26-1 may be provided on the second plate 26. The shape of the plate connecting line 26-1 may be a strip extending along the first direction X, and it may be disposed on one side of the second plate 26 in the first direction X. The first end of the plate connecting line 26-1 is connected to the second plate 26 of this circuit unit, and the second end of the plate connecting line 26-1 extends along the first direction X and is connected to the compensation electrode 27 of the adjacent circuit unit, so that the second plates 26 of adjacent circuit units in a unit row are interconnected through the compensation electrode 27 and the plate connecting line 26-1.

[0214] In an exemplary embodiment, in at least one unit row, the second electrode 26, compensation electrode 27, and electrode connection line 26-1 of multiple circuit units can be an integral structure that is interconnected. The second electrode 26, compensation electrode 27, and electrode connection line 26-1 of the integral structure can be reused as a power signal connection line, ensuring that multiple second electrodes in a unit row have the same potential, which is beneficial to improving the uniformity of the panel, avoiding display defects of the display substrate, and ensuring the display effect of the display substrate.

[0215] In an exemplary embodiment, the second electrode plate 26 may have an opening 26-2, which may be located in the middle of the second electrode plate 26. The shape of the opening 26-2 may be block-shaped (such as rectangular), so that the second electrode plate 26 forms an annular structure. The opening 26-2 exposes the third insulating layer covering the first electrode plate 25, and the orthographic projection of the first electrode plate 25 on the substrate includes the orthographic projection of the opening 26-2 on the substrate. In an exemplary embodiment, the opening 26-2 is configured to accommodate a subsequently formed eleventh via, which is located within the opening 26-2 and exposes the first electrode plate 25, so that the subsequently formed first connecting electrode is connected to the first electrode plate 25.

[0216] In an exemplary embodiment, the shielding electrode 28 can be L-shaped and located on the side opposite to the second direction Y of the second electrode plate 26. The orthographic projection of the shielding electrode 28 on the substrate at least partially overlaps with the orthographic projection of the first active block 11A on the substrate, and the orthographic projection of the shielding electrode 28 on the substrate at least partially overlaps with the orthographic projection of the second active block 12A on the substrate. The end closest to the second electrode plate 26 is connected to the second electrode plate 26. Since the first active block 11A is disposed between the two gate electrodes of the first transistor T1, the shielding electrode 28 can effectively prevent data voltage jumps from affecting the first active layer between the two gate electrodes of the first transistor T1, thus preventing data voltage jumps from affecting the normal operation of the pixel driving circuit and improving the display effect. Since the second active block 12A is disposed between the two gate electrodes of the second transistor T2, the shielding electrode 28 can effectively prevent data voltage jumps from affecting the second active layer between the two gate electrodes of the second transistor T2, thus preventing data voltage jumps from affecting the normal operation of the pixel driving circuit, reducing crosstalk, and improving the display effect.

[0217] In an exemplary embodiment, in at least one circuit unit, the second electrode 26 and the shielding electrode 28 can be an integral structure that is interconnected, that is, the shielding electrode 28 is a part of the second electrode 26 extending along the second direction Y.

[0218] In an exemplary embodiment, the length and width of the shielding electrode 28 can be adjusted according to the layout space, and the shielding electrode 28 can also be used to form a capacitor, etc., which are not limited here.

[0219] In an exemplary embodiment, the repair line 37 can be a straight line or a broken line extending along the first direction X of the main body. It can be disposed between the light emission control line 35 and the scanning connection line 36. The repair line 37 is configured as a repair line for a large-size display substrate. In the event of a defect in the pixel driving circuit, the repair line 37 can be connected to the light emission device that is separated from the pixel driving circuit to quickly repair the light emission device that cannot be lit, thereby effectively improving the yield.

[0220] In an exemplary embodiment, the shape of the first initial signal line 41 can be a straight line or a broken line extending along the first direction X of the main body, and can be disposed on the side of the first gate electrode 21 away from the first electrode plate 26. The orthographic projection of the first initial signal line 41 on the substrate at least partially overlaps with the orthographic projection of the first active connection line 10 on the substrate.

[0221] In an exemplary embodiment, in at least one repeating unit, the first initial signal line 41 may include a first initial connection portion 41-1 and a first initial bend portion 41-2. The first initial connection block 41-1 may be block-shaped (e.g., rectangular) and may be disposed on the side of the first initial signal line 41 away from the second electrode plate 26. The orthographic projection of the first initial connection block 41-1 on the substrate at least partially overlaps with the orthographic projection of the first active connection block 10A on the substrate. The first initial connection block 41-1 is configured to be connected to the first active connection block 10A via a subsequently formed sixth connection electrode. The first initial bend portion 41-2 may be arc-shaped, convex toward the direction of the second electrode plate 26, and forms a first groove 41-3 exposing the first active connection block 10A. The first groove 41-3 is configured to accommodate a subsequently formed thirteenth via.

[0222] In an exemplary embodiment, the shape of the third initial signal line 43 can be a straight line or a broken line extending along the first direction X of the main body, and can be set on the side of the first connecting line 81 away from the light emission control line 35. The orthographic projection of the third initial signal line 43 on the substrate and the orthographic projection of the third active connecting line 30 on the substrate at least partially overlap.

[0223] In an exemplary embodiment, in at least one repeating unit, the third initial signal line 43 may include a third initial connection portion 43-1 and a third initial bend portion 43-2. ​​The third initial connection portion 43-1 may be block-shaped (e.g., rectangular) and may be disposed on the side of the third initial signal line 43 away from the second electrode plate 26. The orthographic projection of the third initial connection portion 43-1 on the substrate at least partially overlaps with the orthographic projection of the third active connection block 30A on the substrate. The third initial connection portion 43-1 is configured to be connected to the third active connection block 30A via a subsequently formed seventh connection electrode. The third initial bend portion 43-2 may be arc-shaped, convex toward the direction of the second electrode plate 26, and forms a third groove 43-3 exposing the third active connection block 30A. The third groove 43-3 is configured to accommodate a subsequently formed fifteenth via.

[0224] (14) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming a fourth insulating layer pattern may include: depositing a fourth insulating film on a substrate on which the aforementioned pattern is formed, and patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the second conductive layer. Each circuit unit has multiple vias, as shown in FIG13. FIG13 is a schematic diagram of the structure of region A in FIG8. The via structure of region B in FIG8 is substantially the same as that of region A in FIG8.

[0225] In an exemplary embodiment, the plurality of vias of each circuit unit in the display area include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, and a twelfth via V12.

[0226] In an exemplary embodiment, the orthographic projection of the first via V1 onto the substrate is located within the range of the orthographic projection of the second region of the first active layer (which is also the first region of the second active layer) onto the substrate. The fourth insulating layer, the third insulating layer, and the second insulating layer within the first via V1 are etched away, exposing the surface of the second region of the first active layer (which is also the first region of the second active layer). The first via V1 is configured to allow a subsequently formed first connection electrode to be connected to the second region of the first active layer (which is also the first region of the second active layer) through the via.

[0227] In an exemplary embodiment, the orthographic projection of the second via V2 onto the substrate lies within the range of the orthographic projection of the first region of the third active layer (which is also the second region of the fourth active layer and the second region of the fifth active layer) onto the substrate. The fourth, third, and second insulating layers within the second via V2 are etched away, exposing the surface of the first region of the third active layer (which is also the second region of the fourth active layer and the second region of the fifth active layer). The second via V2 is configured to allow a subsequently formed second connection electrode to be connected to the first region of the third active layer (which is also the second region of the fourth active layer and the second region of the fifth active layer) through the via.

[0228] In an exemplary embodiment, the orthographic projection of the third via V3 onto the substrate is within the range of the orthographic projection of the first region of the fourth active layer onto the substrate. The fourth insulating layer, the third insulating layer, and the second insulating layer within the third via V3 are etched away, exposing the surface of the first region of the fourth active layer. The third via V3 is configured to allow a subsequently formed third connection electrode to be connected to the first region of the fourth active layer through the via.

[0229] In an exemplary embodiment, the first region of the fifth active layer is within the orthographic projection range of the fourth via V4 onto the substrate. The fourth insulating layer, the third insulating layer, and the second insulating layer within the fourth via V4 are etched away, exposing the surface of the first region of the fifth active layer. The fourth via V4 is configured to allow the subsequently formed fifth connection electrode to be connected to the first region of the fifth active layer through the via.

[0230] In an exemplary embodiment, the orthographic projection of the fifth via V5 onto the substrate lies within the orthographic projection of the second region of the sixth active layer (which is also the second region of the seventh active layer) onto the substrate. The fourth, third, and second insulating layers within the fifth via V5 are etched away, exposing the surface of the second region of the sixth active layer (which is also the second region of the seventh active layer). The fifth via V5 is configured to allow a subsequently formed fourth connection electrode to be connected to the second region of the sixth active layer (which is also the second region of the seventh active layer) through the via.

[0231] In an exemplary embodiment, the orthographic projection of the sixth via V6 onto the substrate is within the range of the orthographic projection of the first region of the seventh active layer onto the substrate. The fourth, third, and second insulating layers within the sixth via V6 are etched away, exposing the surface of the first region of the seventh active layer. The sixth via V6 is configured to allow a subsequently formed second initial signal line to be connected to the first region of the seventh active layer through the via.

[0232] In an exemplary embodiment, the orthographic projection of the seventh via V7 onto the substrate is within the range of the orthographic projection of the second region of the eighth active layer onto the substrate. The fourth, third, and second insulating layers within the seventh via V7 are etched away, exposing the surface of the second region of the eighth active layer. The seventh via V7 is configured to allow a subsequently formed second connection electrode to be connected to the second region of the eighth active layer through the via.

[0233] In an exemplary embodiment, the orthographic projection of the eighth via V8 on the substrate is within the range of the orthographic projection of the first gate connection block 21-1 of the first gate electrode 21 on the substrate. The fourth insulating layer and the third insulating layer in the eighth via V8 are etched away, exposing the surface of the first gate connection block 21-1. The eighth via V8 is configured to allow the subsequently formed fourth scan signal line to be connected to the first gate connection block 21-1 through the via.

[0234] In an exemplary embodiment, the orthogonal projection of the ninth via V9 on the substrate is within the range of the orthogonal projection of the second gate connection block 22-1 of the second gate electrode 22 on the substrate. The fourth and third insulating layers in the ninth via V9 are etched away, exposing the surface of the second gate connection block 22-1. The ninth via V9 is configured to allow the subsequently formed first scan signal line to be connected to the second gate connection block 22-1 through the via.

[0235] In an exemplary embodiment, the orthogonal projection of the tenth via V10 onto the substrate is within the range of the orthogonal projection of the fourth gate connection block 24-1 of the fourth gate electrode 24 onto the substrate. The fourth insulating layer and the third insulating layer within the tenth via V10 are etched away, exposing the surface of the fourth gate connection block 24-1. The tenth via V10 is configured to allow the subsequently formed second scan signal line to be connected to the fourth gate connection block 24-1 through the via.

[0236] In an exemplary embodiment, the orthographic projection of the eleventh via V11 onto the substrate is within the range of the orthographic projection of the opening 26-2 of the second electrode plate 26 onto the substrate. The fourth and third insulating layers within the eleventh via V11 are etched away, exposing the surface of the first electrode plate 25. The eleventh via V11 is configured to allow the subsequently formed first connection electrode to be connected to the first electrode plate 25 through the via.

[0237] In an exemplary embodiment, the orthographic projection of the twelfth via V12 on the substrate is within the range of the orthographic projection of the compensation electrode 27 on the substrate. The fourth insulating layer within the twelfth via V12 is etched away, exposing the surface of the compensation electrode 27. The twelfth via V12 is configured to allow subsequently formed power connection lines to be connected to the compensation electrode 27 through the via.

[0238] In an exemplary embodiment, at least one repeating unit may further include a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, a sixteenth via V16, and a seventeenth via V17.

[0239] In an exemplary embodiment, the orthographic projection of the thirteenth via V13 on the substrate is within the range of the orthographic projection of the first active connection block 10A of the first active connection line 10 on the substrate. The fourth insulating layer, the third insulating layer and the second insulating layer in the thirteenth via V13 are etched away, exposing the surface of the first active connection block 10A. The thirteenth via V13 is configured to allow the subsequently formed sixth connection electrode to be connected to the first active connection block 10A through the via.

[0240] In an exemplary embodiment, the orthographic projection of the fourteenth via V14 on the substrate is within the range of the orthographic projection of the first initial connection portion 41-1 of the first initial signal line 41 on the substrate. The fourth insulating layer in the fourteenth via V14 is etched away, exposing the surface of the first initial connection portion 41-1. The fourteenth via V14 is configured to allow the subsequently formed sixth connection electrode to be connected to the first initial connection portion 41-1 through the via.

[0241] In an exemplary embodiment, the orthographic projection of the fifteenth via V15 on the substrate is within the range of the orthographic projection of the third active connection block 30A of the third active connection line 30 on the substrate. The fourth insulating layer, the third insulating layer and the second insulating layer in the fifteenth via V15 are etched away, exposing the surface of the third active connection block 30A. The fifteenth via V15 is configured to allow the subsequently formed seventh connection electrode to be connected to the third active connection block 30A through the via.

[0242] In an exemplary embodiment, the orthographic projection of the sixteenth via V16 on the substrate is within the range of the orthographic projection of the third initial connection portion 43-1 of the third initial signal line 43 on the substrate. The fourth insulating layer in the sixteenth via V16 is etched away, exposing the surface of the third initial connection portion 43-1. The sixteenth via V16 is configured to allow the subsequently formed seventh connection electrode to be connected to the third initial connection portion 43-1 through the via.

[0243] In an exemplary embodiment, the orthographic projection of the seventeenth via V17 on the substrate is within the range of the orthographic projection of the first scan connection block 36-1 on the substrate of the scan connection line 36. The fourth and third insulating layers in the seventeenth via V17 are etched away, exposing the surface of the first scan connection block 36-1. The seventeenth via V17 is configured to allow the subsequently formed third scan signal line to be connected to the first scan connection block 36-1 through the via.

[0244] (15) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive film on a substrate on which the aforementioned pattern is formed, patterning the third conductive film using a patterning process, and forming a third conductive layer disposed on a fourth insulating layer, as shown in Figures 14A, 14B, 14C, and 14D. Figure 14A is a structural schematic diagram of region A in Figure 8, Figure 14B is a planar schematic diagram of the third conductive layer in Figure 14A, Figure 14C is a structural schematic diagram of region B in Figure 8, and Figure 14D is a planar schematic diagram of the third conductive layer in Figure 14C. In an exemplary embodiment, the third conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0245] In an exemplary embodiment, the third conductive layer pattern of each circuit unit in the display area includes: a first scan signal line 31, a second scan signal line 32, a third scan signal line 33, a fourth scan signal line 34, a second initial signal line 42, a first connecting electrode 51, a second connecting electrode 52, a third connecting electrode 53, a fourth connecting electrode 54, a fifth connecting electrode 55, and a power connection line 62.

[0246] In an exemplary embodiment, the shape of the first scan signal line 31 can be a straight line or a broken line extending along the first direction X of the main body, and it can be located on the side opposite to the second direction Y of the second electrode plate 26. The first scan signal line 31 is connected to the second gate connection block 22-1 in each circuit unit through the ninth via V9. Since the second gate connection block 22-1 is connected to the second gate electrode 22, the connection between the first scan signal line 31 and the gate electrode of the second transistor T2 in each circuit unit is realized. The second gate electrode 22 located in the first conductive layer and the first scan signal line 31 located in the third conductive layer form a double-layer parallel structure. The first scan signal line 31 can control the conduction or disconnection of the second transistor T2 in each circuit unit.

[0247] In an exemplary embodiment, the shape of the second scan signal line 32 can be a straight line or a broken line extending along the first direction X of the main body. It can be located on the side of the first scan signal line 31 away from the second electrode plate 26. The second scan signal line 32 is connected to the fourth gate connection block 24-1 through the tenth via V10. Since the fourth gate connection block 24-1 is connected to the fourth gate electrode 24, the fourth gate electrode 24 located in the first conductive layer and the second scan signal line 32 located in the third conductive layer form a double-layer parallel structure. Thus, the connection between the second scan signal line 32 and the gate electrode of the fourth transistor T4 in each circuit unit is realized. The second scan signal line 32 can control the conduction or disconnection of the fourth transistor T4 in each circuit unit.

[0248] In an exemplary embodiment, the shape of the third scanning signal line 33 can be a straight line or a broken line extending along the first direction X of the main body, and can be set on the side of the repair line 37 away from the second electrode plate 26, and the orthographic projection of the third scanning signal line 33 on the substrate at least partially overlaps with the orthographic projection of the scanning connection line 36 on the substrate.

[0249] In an exemplary embodiment, in at least one repeating unit, a second scan connection block 33-1 may be provided on the third scan signal line 33. The second scan connection block 33-1 may be block-shaped (e.g., rectangular), and may be located on the side of the third scan signal line 33 away from the second electrode plate 26, and connected to the third scan signal line 33. The orthographic projection of the second scan connection block 33-1 on the substrate at least partially overlaps with the orthographic projection of the scan connection block 36-1 on the substrate, and the second scan connection block 33-1 is connected to the scan connection block 36-1 through the seventeenth via V17. Since the scan connection block 36-1 is connected to the scan connection line 36, and the second scan connection block 33-1 is connected to the third scan signal line 33, the connection between the third scan signal line 33 and the gate electrode of the seventh transistor T7 and the gate electrode of the eighth transistor T8 in each circuit unit is realized, and the third scan signal line 33 can control the conduction or disconnection of the seventh transistor T7 and the eighth transistor T8 in each circuit unit.

[0250] In an exemplary embodiment, the scan connection line 36 and the third scan signal line 33 form a double-layered and parallel structure of scan signal lines, which can effectively reduce the resistance of the third scan signal line 33, reduce the voltage drop of the third scan signal, and improve the performance of the pixel driving circuit.

[0251] In an exemplary embodiment, the second scan connection block 33-1 may be disposed in the circuit cells of the N+1th and N+4th cell columns. In at least one repeating cell, the third scan signal line 33 and the second scan connection block 33-1 may be an integral structure interconnected with each other.

[0252] In an exemplary embodiment, the fourth scan signal line 34 can be a straight line or a broken line extending along the first direction X of the main body, and can be disposed on the side of the second scan signal line 32 away from the second electrode plate 26. The fourth scan signal line 34 is connected to the first gate connection block 21-1 through the eighth via V8. Since the first gate connection block 21-1 is connected to the first gate electrode 21, the first gate electrode 21 located in the first conductive layer and the fourth scan signal line 34 located in the third conductive layer form a double-layer parallel structure, thus realizing the connection between the fourth scan signal line 34 and the gate electrode of the first transistor T1 in each circuit unit. The fourth scan signal line 34 can control the conduction or disconnection of the first transistor T1 in each circuit unit.

[0253] By placing the first scan signal line 31, the second scan signal line 32, the third scan signal line 33, and the fourth scan signal line 34 in the third conductive layer, this disclosure can effectively reduce the resistance of the scan signal lines, reduce the voltage drop of the scan signal, and improve the performance of the pixel driving circuit.

[0254] In an exemplary embodiment, the shape of the second initial signal line 42 can be a straight line or a broken line extending along the first direction X of the main body. It can be set on the side of the third scan signal line 33 away from the second electrode plate 26. The second initial signal line 42 is connected to the first region of the seventh active layer in each circuit unit through the sixth via V6, thereby realizing that the second initial signal line 42 writes the second initial signal into the first electrode of the seventh transistor T7 in each circuit unit.

[0255] In an exemplary embodiment, the power connection line 62 may be in the shape of a broken line extending along the first direction X, and may be disposed between the first scan signal line 31 and the third scan signal line 33. The power connection line 62 is connected to the compensation electrode 27 in each circuit unit through the twelfth via V12, and the power connection line 62 is configured to connect the subsequently formed first power line.

[0256] In an exemplary embodiment, the first connecting electrode 51 can be a strip extending along the second direction Y. The first end of the first connecting electrode 51 is connected to the first electrode plate 25 through an eleventh via V11, and the second end of the first connecting electrode 51 is connected to the second region of the first active layer (which is also the first region of the second active layer) through a first via V1. In an exemplary embodiment, since the first electrode plate 25 can serve as the gate electrode of the third transistor T3, the first connecting electrode 51 realizes the interconnection between the second electrode of the first transistor T1, the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first electrode plate 25, forming the first node N1 of the pixel driving circuit.

[0257] In an exemplary embodiment, the second connection electrode 52 can be a strip shape extending along the second direction Y. The first end of the second connection electrode 52 is connected to the first region of the third active layer (which is also the second region of the fourth and fifth active layers) through the second via V2, and the second end of the second connection electrode 52 is connected to the second region of the eighth active layer through the seventh via V7. In an exemplary embodiment, the second connection electrode 52 realizes the interconnection between the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5, and the second electrode of the eighth transistor T8, forming the second node N2 of the pixel driving circuit.

[0258] In an exemplary embodiment, the third connection electrode 53 may be block-shaped (e.g., rectangular). The third connection electrode 53 is connected to the first region of the fourth active layer through a third via V3, and the third connection electrode 53 is configured to connect to a subsequently formed data signal line. In an exemplary embodiment, the third connection electrode 53 may serve as a data connection electrode of this disclosure.

[0259] In an exemplary embodiment, in at least one repeating unit, the third connection electrodes 53 of multiple circuit units may all be disposed on the side of the first scan signal line 31 near the second electrode plate 26, and the multiple third connection electrodes 53 may be located on the same straight line extending along the first direction X.

[0260] In an exemplary embodiment, the fourth connection electrode 54 may be block-shaped (e.g., rectangular), and the fourth connection electrode 54 is connected to the second region of the sixth active layer (which is also the second region of the seventh active layer) through the fifth via V5. The fourth connection electrode 54 is configured to be connected to the subsequently formed anode connection electrode.

[0261] In an exemplary embodiment, the fifth connection electrode 55 can be a strip extending along the second direction Y, and can be disposed on the side of the power connection line 62 away from the first scan signal line 31. The first end of the fifth connection electrode 55 is connected to the first region of the fifth active layer through the fourth via V4, and the second end of the fifth connection electrode 55 is connected to the power connection line 62. Since the power connection line 62 is connected to the subsequently formed first power line, the fifth connection electrode 55 enables the first power line to write the first power signal into the first electrode of the fifth transistor T5.

[0262] In an exemplary embodiment, in at least one circuit unit, the fifth connection electrode 55 and the power connection line 62 can be an integral structure that is interconnected.

[0263] In an exemplary embodiment, in at least one repeating unit, the third conductive layer may further include a sixth connecting electrode 56 and a seventh connecting electrode 57.

[0264] In an exemplary embodiment, the sixth connecting electrode 56 can be a strip extending along the first direction X, and can be disposed on the side of the fourth scan signal line 34 away from the second electrode plate 26. The first end of the sixth connecting electrode 56 is connected to the first active connecting block 10A through the thirteenth via V13, and the second end of the sixth connecting electrode 56 is connected to the first initial connecting portion 41-1 through the fourteenth via V14. Since the first active connecting block 10A is connected to the first active connecting line 10, and the first initial connecting portion 41-1 is connected to the first initial signal line 41, the sixth connecting electrode 56 realizes the connection between the first initial signal line 41 and the first active connecting line 10, forming a double-layered and parallel structure of the first initial signal line. This can effectively reduce the resistance of the first initial signal line, reduce the voltage drop of the first initial signal, effectively improve the uniformity of the first initial signal, effectively improve display uniformity, and improve display quality.

[0265] In an exemplary embodiment, since the first active connection line 10 is connected to the first region of the first active layer in each circuit unit, the first initial signal line 41 writes the first initial signal into the first pole of the first transistor T1 in each circuit unit.

[0266] In an exemplary embodiment, the seventh connecting electrode 57 can be a strip extending along the first direction X, and can be disposed on the side of the second initial signal line 42 away from the second electrode plate 26. The first end of the seventh connecting electrode 57 is connected to the third active connecting block 30A through the fifteenth via V15, and the second end of the seventh connecting electrode 57 is connected to the third initial connecting portion 43-1 through the sixteenth via V16. Since the third active connecting block 30A is connected to the third active connecting line 30, and the third initial connecting portion 43-1 is connected to the third initial signal line 43, the seventh connecting electrode 57 realizes the connection between the third initial signal line 43 and the third active connecting line 30, forming a double-layered and parallel structure of the third initial signal line. This can effectively reduce the resistance of the third initial signal line, reduce the voltage drop of the third initial signal, effectively improve the uniformity of the third initial signal, effectively improve display uniformity, and improve display quality.

[0267] In an exemplary embodiment, since the third active connection line 30 is connected to the first region of the eighth active layer in each circuit unit, the third initial signal line 43 writes the third initial signal into the first pole of the eighth transistor T8 in each circuit unit.

[0268] In an exemplary embodiment, the sixth connecting electrode 56 may be disposed in the boundary region between the N+1th and N+2th unit columns and the boundary region between the N+4th and N+5th unit columns, respectively, and the seventh connecting electrode 57 may be disposed in the circuit units of the N+1th and N+4th unit columns, respectively.

[0269] As shown in Figures 14A and 14B, the third conductive layer of the first region (FIP region) may also include a first connecting line 81 and a first constant voltage trace 91.

[0270] In an exemplary embodiment, the first connecting line 81 and the first constant voltage line 91 can be straight or broken lines extending along the first direction X, and can be disposed between the first scan signal line 31 and the second electrode plate 26 (also between the first scan signal line 31 and the power connection line 62).

[0271] In an exemplary embodiment, a first connecting block 81-1 may be provided on the first connecting line 81. The first connecting block 81-1 may be block-shaped (such as rectangular), may be provided on the side of the first connecting line 81 near the second electrode plate 26, and may be connected to the first connecting line 81. The first connecting block 81-1 is configured to be connected to the second connecting line formed subsequently.

[0272] In an exemplary embodiment, the first connecting block 81-1 may be disposed in the insertion column, and the first connecting line 81 and the first connecting block 81-1 may be an integral structure that is interconnected. For example, the first connecting block 81-1 may be disposed in the insertion column between the N+3rd and N+4th cell columns.

[0273] In an exemplary embodiment, at least one dummy connection block 83 may also be provided on the first connection line 81. The dummy connection block 83 may be block-shaped (such as rectangular), and may be provided on the side of the first connection line 81 near the second electrode plate 26 and connected to the first connection line 81.

[0274] In an exemplary embodiment, the dummy connection block 83 can be disposed in the insertion column, and the first connection line 81 and the dummy connection block 83 can be an integral structure that is interconnected. For example, the dummy connection block 83 can be disposed in the insertion column between the Nth cell column and the N+1th cell column.

[0275] In an exemplary embodiment, the position and shape of the dummy connection block 83 in one insertion column can be substantially the same as the position and shape of the first connection block 81-1 in another insertion column. The difference is that the first connection block 81-1 is configured to connect to the subsequently formed second connection line, while the dummy connection block 83 is neither connected to the second connection line nor to any other trace. This disclosure, through the identical design of the transition area, not only improves the uniformity of subsequent etching processes but also ensures that different locations achieve the same display effect under transmitted and reflected light, improving display uniformity, eliminating shadows, effectively avoiding appearance defects and mura on the display substrate, and improving display quality.

[0276] In an exemplary embodiment, at least one circuit unit may also include a data connection block 84. The data connection block 84 may be block-shaped (e.g., rectangular) and may be disposed between the first connection line 81 and the third connection electrode 53. The first end of the data connection block 84 is connected to the first connection line 81, and the second end of the data connection block 84 is connected to the third connection electrode 53.

[0277] In an exemplary embodiment, the data connection block 84 can be disposed in the circuit unit of the Mth unit row and the N+1th unit column, and the first connection line 81, the data connection block 84 and the third connection electrode 53 can be an integral structure that is interconnected.

[0278] In an exemplary embodiment, at least one repeating unit row may be provided with at least one first connecting line 81 and at least one first constant voltage trace 91. A first break DF1 may be provided between the first connecting line 81 and the first constant voltage trace 91 to achieve mutual insulation between the first connecting line 81 and the first constant voltage trace 91.

[0279] In one exemplary embodiment, the width of the first constant voltage trace 91 can be equal to the width of the first connecting trace 81. In another exemplary embodiment, the widths of the first connecting trace 81 and the first constant voltage trace 91 can be different. The widths of the first connecting trace 81 and the first constant voltage trace 91 are dimensions in the second direction Y.

[0280] As shown in Figures 14C and 14D, the third conductive layer in the second region (non-FIP region) may also include a first constant voltage trace 91.

[0281] In an exemplary embodiment, the shape of the first constant voltage line 91 can be a straight line or a broken line extending along the first direction X, and it can be disposed between the first scan signal line 31 and the second electrode plate 26 (also between the first scan signal line 31 and the power connection line 62).

[0282] In an exemplary embodiment, at least one repeating cell row may only have a first constant voltage trace 91, without a first connecting line.

[0283] In an exemplary embodiment, at least one first constant voltage connecting block 91-1 may be provided on the first constant voltage line 91. The first constant voltage connecting block 91-1 may be block-shaped (such as rectangular), may be provided on the side of the first constant voltage line 91 near the second electrode plate 26, and may be connected to the first constant voltage line 91. The first constant voltage connecting block 91-1 is configured to be connected to the second constant voltage line formed subsequently.

[0284] In an exemplary embodiment, the first constant voltage connector 91-1 can be disposed in the insertion column, and the first constant voltage trace 91 and the first constant voltage connector 91-1 can be an integral structure that is interconnected. For example, the first constant voltage connector 91-1 can be disposed in the insertion column between the N+9th and N+10th unit columns, and in the insertion column between the N+12th and N+13th unit columns, respectively.

[0285] In an exemplary embodiment, a constant voltage lead may be provided in the border area, which can transmit a first power signal or a second power signal. At least one first constant voltage trace 91 may extend to the border area and connect with the constant voltage lead, thus the first constant voltage trace 91 is a trace for transmitting the first power signal or the second power signal.

[0286] (16) Forming a first planarization layer pattern. In an exemplary embodiment, forming a first planarization layer pattern may include: coating a first planarization film on a substrate on which the aforementioned pattern is formed, and patterning the first planarization film using a patterning process to form a first planarization layer covering a third conductive layer. The first planarization layer is provided with a plurality of vias, as shown in Figures 15A and 15B. Figure 15A is a structural schematic diagram of region A in Figure 8, and Figure 15B is a structural schematic diagram of region B in Figure 8.

[0287] In an exemplary embodiment, each circuit unit in the display area includes multiple vias: a twenty-first via V21, a twenty-second via V22, and a twenty-third via V23.

[0288] In an exemplary embodiment, the orthographic projection of the 21st via V21 on the substrate is within the range of the orthographic projection of the power connection line 62 on the substrate. The first planarization layer within the 21st via V21 is removed, exposing the surface of the power connection line 62. The 21st via V21 is configured to allow a subsequently formed first power line to be connected to the power connection line 62 through the via.

[0289] In an exemplary embodiment, the orthographic projection of the 22nd via V22 onto the substrate is within the range of the orthographic projection of the fourth connecting electrode 54 onto the substrate. The first planarization layer within the 22nd via V22 is removed, exposing the surface of the fourth connecting electrode 54. The 22nd via V22 is configured to allow a subsequently formed anode connecting electrode to be connected to the fourth connecting electrode 54 through the via.

[0290] In an exemplary embodiment, the orthographic projection of the 23rd via V23 on the substrate is within the range of the orthographic projection of the third connection electrode 53 on the substrate. The first planarization layer within the 23rd via V23 is removed, exposing the surface of the third connection electrode 53. The 23rd via V23 is configured to allow subsequently formed data signal lines to be connected to the third connection electrode 53 through the via.

[0291] In an exemplary embodiment, since the third connection electrode 53 in the circuit unit of the Mth unit row and the N+1th unit column is connected to the first connection line 81 through the data connection block 84, the twenty-third via V23 in the circuit unit of the Mth unit row and the N+1th unit column can be used as the first connection hole of this disclosure.

[0292] As shown in Figure 15A, the first planarization layer of the first region may further include a twenty-fourth via V24. In an exemplary embodiment, the orthographic projection of the twenty-fourth via V24 onto the substrate lies within the range of the orthographic projection of the first connecting block 81-1 of the first connecting line 81 onto the substrate. The first planarization layer within the twenty-fourth via V24 is removed, exposing the surface of the first connecting block 81-1. The twenty-fourth via V24 is configured to allow a subsequently formed second connecting line to connect to the first connecting block 81-1 through this via. In an exemplary embodiment, the twenty-fourth via V24 can serve as the second connecting hole of this disclosure.

[0293] As shown in Figure 15B, the first planarization layer of the second region may further include a twenty-fifth via V25. In an exemplary embodiment, the orthographic projection of the twenty-fifth via V25 onto the substrate lies within the orthographic projection of the first constant-voltage connector 91-1 onto the substrate of the first constant-voltage trace 91. The first planarization layer within the twenty-fifth via V25 is removed, exposing the surface of the first constant-voltage connector 91-1. The twenty-fifth via V25 is configured to allow a subsequently formed second constant-voltage trace to connect to the first constant-voltage connector 91-1 through this via. In an exemplary embodiment, the twenty-fifth via V25 can serve as a third connection hole of this disclosure.

[0294] (17) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming a fourth conductive layer pattern may include: depositing a fourth conductive film on a substrate on which the aforementioned pattern is formed, and patterning the fourth conductive film using a patterning process to form a fourth conductive layer disposed on a first planarization layer, as shown in Figures 16A, 16B, 16C, and 16D. Figure 16A is a structural schematic diagram of region A in Figure 8, Figure 16B is a planar schematic diagram of the fourth conductive layer in Figure 16A, Figure 16C is a structural schematic diagram of region B in Figure 8, and Figure 16D is a planar schematic diagram of the fourth conductive layer in Figure 16C. In an exemplary embodiment, the fourth conductive layer may be referred to as a second source / drain metal (SD2) layer.

[0295] In an exemplary embodiment, the fourth conductive layer pattern of each circuit unit in the display area includes at least a first power line 61, an anode connection electrode 63, and a data signal line 70.

[0296] In an exemplary embodiment, the shape of the first power line 61 can be a straight line or a broken line extending along the second direction Y of the main body. The first power line 61 is connected to the power connection line 62 through the twenty-first via V21, thus realizing the interconnection between the power connection line 62 extending along the first direction X and the first power line 61 extending along the second direction Y. The power connection line 62 and the first power line 61 form a mesh-like interconnected structure for transmitting the first power signal, which can effectively reduce the resistance of the first power line, effectively reduce the voltage drop of the first power signal, effectively improve the uniformity of the first power signal, effectively improve the display uniformity, and improve the display quality.

[0297] In an exemplary embodiment, the orthographic projection of the first power line 61 on the substrate at least partially overlaps with the orthographic projection of the first connecting electrode 51 on the substrate. Since the first connecting electrode 51 serves as the first node N1 in the pixel driving circuit, the first power line 61, which has a constant voltage, can effectively shield the first node N1 from the influence of other signals in the pixel driving circuit, preventing other signals (such as data voltage jumps) from affecting the potential of the first node N1 in the pixel driving circuit, reducing crosstalk, and improving the display effect.

[0298] In an exemplary embodiment, the orthographic projection of the first power line 61 onto the substrate may include the orthographic projection of the first connecting electrode 51 onto the substrate.

[0299] In an exemplary embodiment, the first power line 61 can be designed with non-uniform width. The non-uniform width design of the first power line 61 not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between the first power line and the data signal line.

[0300] In an exemplary embodiment, the orthographic projection of the first power line 61 on the substrate may include the orthographic projection of the first break DF1 on the first connecting line 81 on the substrate, so that the first power line 61 can block the first break DF1 from above, which can effectively eliminate the film layer difference in different areas, which is beneficial for shadow removal and avoids poor appearance of the display substrate.

[0301] In an exemplary embodiment, the anode connection electrode 63 can be a strip shape extending along the first direction X. The anode connection electrode 63 is connected to the fourth connection electrode 54 through the twenty-second via V22, and the anode connection electrode 63 is configured to be connected to the subsequently formed anode. Since the fourth connection electrode 54 is connected to the second region of the sixth active layer (which is also the second region of the seventh active layer) through the via, the pixel driving circuit drives the light-emitting device to emit light.

[0302] In an exemplary embodiment, the data signal line 70 can be a straight line or a broken line extending along the second direction Y in its main body. The data signal line 70 is connected to the third connection electrode 53 through the twenty-third via V23. Since the third connection electrode 53 is connected to the first region of the fourth active layer through the via, the data signal line 70 writes the data signal to the first electrode of the fourth transistor T4.

[0303] In an exemplary embodiment, since the third connection electrode 53 in the circuit unit of the Mth unit row and the N+1th unit column is connected to the first connection line 81 through the data connection block 84, the connection between the first connection line 81 in the Mth unit row and the data signal line 70 in the N+1th unit column is realized.

[0304] As shown in Figures 16A and 16B, the fourth conductive layer in the first region may further include a second connecting line 82 and a second constant voltage trace 92. The shapes of the second connecting line 82 and the second constant voltage trace 92 may be straight lines or broken lines extending along the second direction Y of the main body, and they may be respectively set in the insertion column.

[0305] In an exemplary embodiment, a second connecting block 82-1 may be provided on the second connecting line 82. The second connecting block 82-1 may be block-shaped (e.g., rectangular), and may be located on the side opposite to the first direction X of the second connecting line 82, and connected to the second connecting line 82. The second connecting block 82-1 is connected to the first connecting block 81-1 through the twenty-fourth via V24. Since the first connecting block 81-1 is connected to the first connecting line 81, and the second connecting block 82-1 is connected to the second connecting line 82, the connection between the first connecting line 81 in the Mth unit row and the second connecting line 82 located in the column inserted between the N+3rd and N+4th unit columns is realized. Because of the connection between the first connection line 81 in the Mth unit row and the data signal line 70 in the N+1th unit column, the sequential connection between the second connection line 82 in the insertion column, the first connection line 81 in the Mth unit row, and the data signal line 70 in the N+1th unit column is realized. The data signal of the binding area can be transmitted to the data signal line 70 through the first connection line 81 and the second connection line 82.

[0306] In an exemplary embodiment, at least one second connecting line 82 and at least one second constant voltage line 92 may be provided in at least one insertion column. A second break DF2 may be provided between the second connecting line 82 and the second constant voltage line 92, so that the second connecting line 82 and the second constant voltage line 92 located on both sides of the second break DF2 are mutually insulated.

[0307] In an exemplary embodiment, the orthographic projection of the second break DF2 on the substrate can be located within the range of the orthographic projection of the first initial signal line 41 on the substrate, so that the first initial signal line 41 can support the second break DF2 from below, which can effectively eliminate the film layer difference in different areas, which is beneficial for shadow removal and avoids poor appearance of the display substrate.

[0308] In some possible implementations, the orthographic projection of the second break DF2 on the substrate may be within the range of the orthographic projection of the second initial signal line 42 on the substrate, or the orthographic projection of the second break DF2 on the substrate may be within the range of the orthographic projection of the third initial signal line 43 on the substrate, or the orthographic projection of the second break DF2 on the substrate may be within the range of the orthographic projection of the power connection line 62 on the substrate.

[0309] In some other possible implementations, the orthographic projection of the second break DF2 on the substrate may be within the range of the orthographic projection of the first connecting line 81 on the substrate, which is not limited herein.

[0310] In an exemplary embodiment, in at least one repeating unit, the orthographic projection of the second connecting block 82-1 on the substrate at least partially overlaps with the orthographic projection of the dummy connecting block 83 on the substrate.

[0311] In one exemplary embodiment, the width of the second constant voltage trace 92 can be equal to the width of the second connecting trace 82. In another exemplary embodiment, the widths of the second connecting trace 82 and the second constant voltage trace 92 can be different. The widths of the second connecting trace 82 and the second constant voltage trace 92 are dimensions in the first direction X.

[0312] As shown in Figures 16C and 16D, the fourth conductive layer of the second region may also include a second constant voltage trace 92. The shape of the second constant voltage trace 92 may be a straight line or a broken line extending along the second direction Y of the main body, and may be set in the corresponding insertion column.

[0313] In an exemplary embodiment, at least one second constant voltage connecting block 92-1 may be provided on the second constant voltage trace 92. The shape of the second constant voltage connecting block 92-1 may be block-shaped (such as rectangular), and it may be located on the side opposite to the first direction X of the second constant voltage trace 92 and connected to the second constant voltage trace 92. The second constant voltage connecting block 92-1 is connected to the first constant voltage connecting block 91-1 through the twenty-fifth via V25. Since the first constant voltage connecting block 91-1 is connected to the first constant voltage trace 91, and the second constant voltage connecting block 92-1 is connected to the second constant voltage trace 92, the interconnection of the first constant voltage trace 91 extending along the first direction X and the second constant voltage trace 92 extending along the second direction Y is realized. The first constant voltage trace 91 and the second constant voltage trace 92 form a mesh-like interconnected structure for transmitting constant voltage signals, which can effectively reduce the resistance of the constant voltage signal line, effectively reduce the voltage drop of the constant voltage signal, effectively improve the uniformity of the constant voltage signal, effectively improve the display uniformity, and improve the display quality.

[0314] In an exemplary embodiment, at least one insertion column may only have a second constant voltage trace 92, without a second connecting line.

[0315] In an exemplary embodiment, in at least one repeating unit, the orthographic projection of the second constant pressure connecting block 92-1 on the substrate at least partially overlaps with the orthographic projection of the dummy connecting block 83 on the substrate.

[0316] In an exemplary embodiment, at least one first power line 61 may be disposed between the data signal line 70 and the second connection line 82, or at least one first power line 61 may be disposed between the data signal line 70 and the second constant voltage line 92.

[0317] In an exemplary embodiment, the orthographic projection of at least one second connection line 82 on the substrate at least partially overlaps with the orthographic projection of the shielding electrode 28 on the substrate, or the orthographic projection of at least one second constant voltage line 92 on the substrate at least partially overlaps with the orthographic projection of the shielding electrode 28 on the substrate.

[0318] In an exemplary embodiment, the bonding area may be provided with a bonding constant voltage lead, which can transmit a first power signal or a second power signal. At least one second constant voltage trace 92 can extend to the bonding area and connect with the bonding constant voltage lead, thus the second constant voltage trace 92 is a trace for transmitting the first power signal or the second power signal.

[0319] In an exemplary embodiment, both the first constant voltage trace 91 and the second constant voltage trace 92 are traces for transmitting the first power signal, forming a mesh-like interconnected structure for transmitting the first power signal.

[0320] In an exemplary embodiment, both the first constant voltage trace 91 and the second constant voltage trace 92 are traces for transmitting the second power signal, forming a mesh-like interconnected structure for transmitting the second power signal.

[0321] In some possible implementations, the second constant voltage line 92 can be directly connected to the first power line 61 via a connecting strip, which is not limited in this disclosure.

[0322] (18) Forming a second planarization layer pattern. In an exemplary embodiment, forming a second planarization layer pattern may include: coating a second planarization film on a substrate on which the aforementioned pattern is formed, and patterning the second planarization film using a patterning process to form a second planarization layer covering a fourth conductive layer. A plurality of vias are provided on the second planarization layer, as shown in FIG17. FIG17 is a schematic structural diagram of region A in FIG8. The via structure of region B in FIG8 is substantially the same as that of region A in FIG8.

[0323] In an exemplary embodiment, the plurality of vias for each circuit unit in the display area may include an anode via V30.

[0324] In an exemplary embodiment, the orthographic projection of the anode via V30 on the substrate is within the range of the orthographic projection of the anode connection electrode 63 on the substrate. The second planarization layer within the anode via V30 is removed, exposing the surface of the anode connection electrode 63. The anode via V30 is configured to allow a subsequently formed anode to be connected to the anode connection electrode 63 through the via.

[0325] At this point, the driving structure layer is fabricated on the substrate. In a plane parallel to the display substrate, the driving structure layer may include multiple circuit units. Each circuit unit may include a pixel driving circuit, and a first scan signal line, a second scan signal line, a third scan signal line, a fourth scan signal line, a light emission control line, a first initial signal line, a second initial signal line, a third initial signal line, a first power supply line, and a data signal line connected to the pixel driving circuit. In a plane perpendicular to the display substrate, the driving structure layer may include at least a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a first planarization layer, a fourth conductive layer, and a second planarization layer sequentially stacked on the substrate.

[0326] In an exemplary embodiment, the substrate can be a flexible substrate or a rigid substrate. The rigid substrate can be, but is not limited to, one or more of glass and quartz, while the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an exemplary embodiment, the flexible substrate can include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer films, etc. The materials of the first and second inorganic material layers can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The material of the semiconductor layer can be amorphous silicon (a-Si).

[0327] In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They can be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo. The first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON). They can be single-layer, multi-layer, or composite layers. The first planarization layer and the second planarization layer can be made of organic materials, such as resin. The active layer can be made of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, or polythiophene, etc. That is, this disclosure applies to transistors manufactured based on oxide technology, silicon technology, or organic technology.

[0328] In an exemplary embodiment, after the driving structure layer is prepared, a light-emitting structure layer is prepared on the driving structure layer. The preparation process of the light-emitting structure layer may include the following operations.

[0329] (19) Forming an anode conductive layer pattern. In an exemplary embodiment, forming an anode conductive layer pattern may include: depositing an anode conductive film on a substrate on which the aforementioned pattern is formed, and patterning the anode conductive film using a patterning process to form an anode conductive layer disposed on a second planarization layer, as shown in Figures 18A and 18B, where Figure 18B is a planar schematic diagram of the anode conductive layer in Figure 18A. Figure 18A is a structural schematic diagram of region A in Figure 8, and the anode conductive layer pattern in region B of Figure 8 is substantially the same as that in region A of Figure 8.

[0330] In an exemplary embodiment, the anode conductive layer may include at least a plurality of anode patterns. These anode patterns may include a first anode 130A for red light-emitting units, a second anode 130B for green light-emitting units, and a third anode 130C for blue light-emitting units. The first anode 130A and the second anode 130B may be alternately arranged along a second direction Y, and the third anode 130C may be disposed on one side of the second anode 130B along a first direction X. The first anode 130A, the second anode 130B, and the third anode 130C may be connected to the anode connection electrode 63 of the corresponding circuit unit through anode vias V30, respectively.

[0331] In an exemplary embodiment, at least one of the first anode 130A, the second anode 130B, and the third anode 130C may include an anode body portion and an anode connecting portion that are connected to each other. The anode body portion may be rectangular in shape, and the corners of the rectangular shape may be chamfered. The anode connecting portion may be block-shaped (such as rectangular). The anode connecting portion is connected to the anode connecting electrode 63 through the anode through-hole V30.

[0332] In an exemplary embodiment, the orthographic projection of the anode body portion of at least one first anode 130A and at least one second anode 130B on the substrate at least partially overlaps with the orthographic projection of the first power line 61 and the second connecting line 82 on the substrate; or, the orthographic projection of the anode body portion of at least one first anode 130A and at least one second anode 130B on the substrate at least partially overlaps with the orthographic projection of the first power line 61 and the second constant voltage line 92 on the substrate.

[0333] In an exemplary embodiment, the orthographic projection of the anode body portion of at least one third anode 130C onto the substrate at least partially overlaps with the orthographic projections of a data signal line 70 and two first power lines 61 onto the substrate, and in the first direction X, the data signal line 70 is disposed between the two first power lines 61.

[0334] In an exemplary embodiment, an anode groove 131 may be provided on the anode body portion of at least one third anode 130C. The shape of the anode groove 131 may be a strip extending along the second direction Y, and it may be disposed in the middle region of the anode body portion of the third anode 130C in the first direction X. The orthographic projection of the anode groove 131 on the substrate at least partially overlaps with the orthographic projection of the data signal line 70 on the substrate. That is, the anode body portion of the third anode 130C has a forked structure, and the forked position avoids the data signal line 70, which can effectively reduce the impact of data voltage jumps on the data signal line on the anode potential and improve the display effect.

[0335] In an exemplary embodiment, the anode body portion of the third anode 130C may have a first length L1, and the anode groove 131 may have a second length L2, wherein the ratio of the second length L2 to the first length L1 may be 0.3 to 0.7. The first length L1 is the average dimension of the anode body portion of the third anode 130C in the second direction Y, and the second length L2 is the average dimension of the anode groove 131 in the second direction Y.

[0336] In an exemplary embodiment, the anode conductive layer adopts a single-layer structure, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or it can adopt a multi-layer composite structure, such as ITO / Ag / ITO.

[0337] In an exemplary embodiment, the subsequent fabrication process may include: first forming a pixel definition layer pattern, then forming an organic light-emitting layer using vapor deposition or inkjet printing, then forming a cathode on the organic light-emitting layer, and then forming an encapsulation structure layer. The encapsulation structure layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers to ensure that external moisture cannot enter the light-emitting structure layer.

[0338] This exemplary embodiment provides a display substrate that achieves a FIP (Film In-Place) structure by setting data connection lines within the display area and connecting data lead-out lines in the bonding area to data signal lines via these data connection lines. This eliminates the need for fan-shaped diagonal lines in the lead-out line area, effectively reducing the length of the lead-out line area, significantly shortening the bottom bezel width, increasing the screen-to-body ratio, and facilitating full-screen display. This disclosure also utilizes a multi-insertion (e.g., 3-insertion) design for the FIP routing, with the second connection line positioned in the insertion column between repeating units. This reduces the bottom bezel width while simultaneously lowering the density of vertical routing, reducing defects, and improving yield.

[0339] This disclosure, by setting a first constant voltage trace and a second constant voltage trace in the display area to transmit a first power signal or a second power signal, and forming a mesh-like interconnected structure for transmitting the first power signal or the second power signal, can not only effectively reduce the resistance of the first power signal or the second power line and effectively reduce the voltage drop of the first power signal or the second power signal to achieve low power consumption, but also effectively improve the uniformity of the first power signal or the second power signal in the display substrate, effectively improving display uniformity, display quality, and display performance.

[0340] This disclosure achieves a VSS in pixel structure by forming a mesh-like interconnected structure for transmitting a second power signal within the display area. This significantly reduces the width of the constant voltage lead in the bezel, greatly reduces the width of the left and right bezels, increases the screen-to-body ratio, and facilitates the realization of full-screen display.

[0341] This disclosure arranges the data connection line in the first region and the constant voltage trace in the second region, so that the first region and the second region have substantially the same trace structure. The different regions can achieve substantially the same display effect under transmitted light and reflected light, effectively avoiding poor appearance of the display substrate and improving display quality.

[0342] This disclosure, by setting a first initial signal line and a third initial signal line with a double-layer structure, can effectively reduce the resistance of the first initial signal line and the third initial signal line, reduce the voltage drop of the first initial signal and the third initial signal, effectively improve the uniformity of the first initial signal and the third initial signal, effectively improve display uniformity, and improve display quality and display performance.

[0343] This disclosure effectively reduces the resistance of the scan signal lines, lowers the voltage drop of the scan signal, and improves the performance of the pixel driving circuit by setting multiple scan signal lines in the third conductive layer and making the third scan signal line a double-layer structure.

[0344] This disclosure provides a repair line in the display area. In the event of a defect in the pixel driving circuit, the repair line can be connected to a light-emitting device that is separate from the pixel driving circuit, so as to quickly repair the light-emitting device that cannot be lit, and can effectively improve the yield.

[0345] This disclosure improves the display effect by setting the third anode as a bifurcated structure, with the bifurcation position avoiding the data signal line, which can effectively reduce the impact of data voltage jumps on the anode potential on the data signal line.

[0346] The preparation process disclosed herein is well compatible with existing preparation processes, is simple to implement, easy to carry out, has high production efficiency, low production cost, and high yield.

[0347] Figure 19 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure, and is a schematic diagram of the structure of region A in Figure 8. In the exemplary embodiment, the main structure of the display substrate of this embodiment is basically the same as that of the embodiments shown in Figures 9A to 9D, except that the first connecting line 81 can be disposed between the first scan signal line 31 and the second scan signal line 32.

[0348] In an exemplary embodiment, in at least one repeating cell row of the first region, the shapes of the fourth active layers 14 of the plurality of circuit cells are differentiated. The first region of the fourth active layer of at least one circuit cell is disposed between the first scan signal line 31 and the second scan signal line 32, while the first region of the fourth active layer of other circuit cells is disposed between the first scan signal line 31 and the second electrode plate, and is located on the same straight line extending along the first direction X.

[0349] In an exemplary embodiment, in at least one repeating cell row of the first region, a first connection line 81 may be disposed between the first scan signal line 31 and the second scan signal line 32. A circuit cell may also be provided with a data connection block 84, which may be block-shaped (e.g., rectangular), disposed on the side of the first connection line 81 near the first scan signal line 31, and connected to the first connection line 81. The data connection block 84 may be connected to the first region of the fourth active layer in the circuit cell through a via, while other circuit cells still adopt a structure in which the third connection electrode is connected to the first region of the fourth active layer through a via.

[0350] In an exemplary embodiment, in at least one repeating cell row, a data connection block 84 may be disposed on the side of the first scan signal line 31 away from the second electrode plate, and the first connection line 81 and the data connection block 84 may be an integral structure that is interconnected.

[0351] In an exemplary embodiment, the data connection block 84 can be disposed in the circuit unit of the Mth unit row and the N+1th unit column. The data signal line in the N+1th unit column can be connected to the data connection block 84 through a via, thereby realizing the connection between the first connection line 81 in the Mth unit row and the data signal line 70 in the N+1th unit column.

[0352] In some possible embodiments, the first region of the fourth active layer of multiple circuit units in a repeating cell row may be disposed between the first scan signal line 31 and the second scan signal line 32, which is not limited herein.

[0353] Figure 20 is a structural schematic diagram of another display substrate according to an exemplary embodiment of the present disclosure, and is a structural schematic diagram of region A in Figure 8. In the exemplary embodiment, the main structure of the display substrate of this embodiment is basically the same as that of the embodiments shown in Figures 9A to 9D, except that the first connecting line 81 and the first power supply line 91 can be disposed on the side of the light-emitting signal line 25 away from the power connecting line 62, that is, the light-emitting signal line 25 can be located between the power connecting line 62 and the first connecting line 81.

[0354] In an exemplary embodiment, in at least one repeating cell row of the first region, the first connection line 81 and the first power supply line 91 may be disposed on the side of the second initial signal line 42 away from the power connection line 62, and in at least one repeating cell row of the second region, the first power supply line 91 may be disposed on the side of the second initial signal line 42 away from the power connection line 62.

[0355] In an exemplary embodiment, the orthographic projection of the first connection line 81 or the first power supply line 91 on the substrate at least partially overlaps with the orthographic projection of the third initial signal line 43 on the substrate. The third initial signal line 43, which has a constant voltage, can effectively shield the influence of data voltage jumps in the first connection line 81 on the pixel driving circuit and reduce crosstalk.

[0356] In an exemplary embodiment, at least one repeating cell row in the first region may also be provided with a data connection block 84. The data connection block 84 may be block-shaped (such as rectangular), and may be located on the side of the first connection line 81 away from the second initial signal line 42 and connected to the first connection line 81. The data signal line 70 may be connected to the data connection block 84 through a via, thereby realizing the connection between the first connection line 81 in the Mth cell row and the data signal line 70 in the N+1th cell column.

[0357] Figure 21 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure, and is a schematic diagram of the structure of region A in Figure 8. In the exemplary embodiment, the main structure of the display substrate of this embodiment is basically the same as that of the embodiments shown in Figures 9A to 9D, except that the first connecting line 81 and the first power supply line 91 can be disposed on the side of the light-emitting signal line 25 away from the power supply connecting line 62, and the second initial signal line 42 can be disposed in the second conductive layer.

[0358] In an exemplary embodiment, in at least one repeating cell row of the first region, the first connecting line 81 and the first power supply line 91 may be disposed between the light-emitting signal line 25 and the third initial signal line 43, and in at least one repeating cell row of the second region, the first power supply line 91 may be disposed between the light-emitting signal line 25 and the third initial signal line 43.

[0359] In an exemplary embodiment, the orthographic projection of the first connection line 81 or the first power supply line 91 on the substrate at least partially overlaps with the orthographic projection of the second initial signal line 42 on the substrate. This not only allows the second initial signal line 42, which has a constant voltage, to effectively shield the data voltage jumps in the first connection line 81 from the influence on the pixel driving circuit and reduce crosstalk, but also saves wiring space as much as possible, which is beneficial for achieving higher resolution (PPI).

[0360] In an exemplary embodiment, a data connection block 84 may be provided in at least one repeating cell row of the first region. The data connection block 84 may be block-shaped (such as rectangular), and may be located on the side of the first connection line 81 away from and close to the third initial signal line 43, and connected to the first connection line 81. The data signal line 70 may be connected to the data connection block 84 through a via, thereby realizing the connection between the first connection line 81 in the Mth cell row and the data signal line 70 in the N+1th cell column.

[0361] In an exemplary embodiment, the fabrication process of the display substrate is basically the same as that shown in Figures 9A to 9D. The difference is that the formed second conductive layer also includes a second initial signal line, and the second initial signal line 42 can be disposed between the third scan signal line 33 and the third initial signal line 43.

[0362] In an exemplary embodiment, the positions of the third scan signal line 33 and the scan connection line 36 can be appropriately moved upwards depending on the layout space. For example, space can be made for setting the second initial signal line 42 by canceling the repair line.

[0363] Figure 22 is a structural schematic diagram of another display substrate according to an exemplary embodiment of the present disclosure, and is a structural schematic diagram of region A in Figure 8. In the exemplary embodiment, the main structure of the display substrate of this embodiment is basically the same as that of the embodiments shown in Figures 9A to 9D, except that a constant voltage connection line 93 is also provided in the insertion column.

[0364] In an exemplary embodiment, at least one insertion column may be provided with two vertical lines, which may be a second connecting line 82 and a constant voltage connecting line 93, or a second power supply line 92 and a constant voltage connecting line 93.

[0365] In an exemplary embodiment, the constant voltage connection line 93 can be a straight line or a broken line with its main body extending along the second direction Y. The constant voltage connection line 93 can be disposed between the second connection line 82 and the adjacent data signal line 70, or it can be disposed between the second power supply line 92 and the adjacent data signal line 70. By disposing the constant voltage connection line 93 between the second connection line 82 and the data signal line 70, this disclosure effectively avoids crosstalk in the data signals.

[0366] In an exemplary embodiment, the second connecting line 82, the second power supply line 92, and the constant voltage connecting line 93 can be disposed in the same conductive layer and formed synchronously through the same patterning process.

[0367] In an exemplary embodiment, at least one fourth connecting block 94 may be provided on the constant voltage connecting line 93. The fourth connecting block 94 may be block-shaped (e.g., rectangular) and may be located on one side of the constant voltage connecting line 93 in the first direction X or on the opposite side of the first direction X, and connected to the constant voltage connecting line 93. The fourth connecting block 94 may be connected to the second initial signal line 42 through a via, thereby realizing the interconnection between the second initial signal line 42 extending along the first direction X and the constant voltage connecting line 93 extending along the second direction Y. The second initial signal line 42 and the constant voltage connecting line 93 form a mesh-like interconnected structure for transmitting the second initial signal, which can effectively reduce the resistance of the second initial signal line, effectively reduce the voltage drop of the second initial signal, effectively improve the uniformity of the second initial signal, effectively improve the display uniformity, and improve the display quality.

[0368] In some possible implementations, the constant voltage connection line 93 can be connected to the first initial signal line 41, thus realizing the interconnection between the first initial signal line 41 extending along the first direction X and the constant voltage connection line 93 extending along the second direction Y. The first initial signal line 41 and the constant voltage connection line 93 form a mesh-like interconnected structure for transmitting the first initial signal, which can effectively reduce the resistance of the first initial signal line, effectively reduce the voltage drop of the first initial signal, effectively improve the uniformity of the first initial signal, effectively improve the display uniformity, and improve the display quality and display performance.

[0369] In some other possible implementations, a constant voltage connection line 93 in an insert column can be connected to a third initial signal line 43, thus realizing the interconnection between the third initial signal line 43 extending along the first direction X and the constant voltage connection line 93 extending along the second direction Y. The third initial signal line 43 and the constant voltage connection line 93 form a mesh-like interconnection structure for transmitting the third initial signal, which can effectively reduce the resistance of the third initial signal line, effectively reduce the voltage drop of the third initial signal, effectively improve the uniformity of the third initial signal, effectively improve the display uniformity, and improve the display quality.

[0370] In some other possible implementations, a constant voltage connection line 93 in one insertion column can be connected to a first initial signal line 41, a constant voltage connection line 93 in another insertion column can be connected to a second initial signal line 42, and a constant voltage connection line 93 in yet another insertion column can be connected to a third initial signal line 43, thus simultaneously forming a mesh-like interconnection structure for transmitting the first initial signal, a mesh-like interconnection structure for transmitting the second initial signal, and a mesh-like interconnection structure for transmitting the third initial signal on the display substrate. For example, in the first direction X, the constant voltage connection lines 93 connected to the first initial signal line 41, the constant voltage connection lines 93 connected to the second initial signal line 42, and the constant voltage connection lines 93 connected to the third initial signal line 43 can be arranged periodically.

[0371] Figure 23 is a structural schematic diagram of another display substrate according to an exemplary embodiment of the present disclosure, and is a structural schematic diagram of region A in Figure 8. In the exemplary embodiment, the main structure of the display substrate of this embodiment is basically the same as that of the embodiments shown in Figures 9A to 9D, except that a constant voltage connection line 93 is also provided in the unit column.

[0372] In an exemplary embodiment, at least one unit column may be provided with three vertical lines, which may be a first power line 61, a data signal line 70, and a constant voltage connection line 93.

[0373] In an exemplary embodiment, the second connecting line 82, the second power supply line 92, and the constant voltage connecting line 93 can be disposed in the same conductive layer and formed synchronously through the same patterning process.

[0374] In an exemplary embodiment, at least one connecting block may be connected to the constant voltage connecting line 93. The connecting block is configured to be connected to the first initial signal line 41, the second initial signal line 42, or the third initial signal line 43 through a via, forming a mesh-like interconnected structure for transmitting the first initial signal, the second initial signal, or the third initial signal.

[0375] In some possible implementations, the constant voltage connection line 93 in one unit column can be connected to the first initial signal line 41, the constant voltage connection line 93 in another unit column can be connected to the second initial signal line 42, and the constant voltage connection line 93 in yet another unit column can be connected to the third initial signal line 43, thus simultaneously forming a mesh-like interconnection structure for transmitting the first initial signal, a mesh-like interconnection structure for transmitting the second initial signal, and a mesh-like interconnection structure for transmitting the third initial signal on the display substrate. For example, in the first direction X, the constant voltage connection lines 93 connected to the first initial signal line 41, the constant voltage connection lines 93 connected to the second initial signal line 42, and the constant voltage connection lines 93 connected to the third initial signal line 43 can be arranged periodically.

[0376] In some other possible implementations, the embodiments shown in FIG22 and FIG23 can be combined into new schemes, with two vertical lines (second connecting line 82 and constant voltage connecting line 93) in the insertion column and three vertical lines (first power line 61, data signal line 70 and constant voltage connecting line 93) in the cell column. That is, the second connecting line 82 is a 3-in-1 structure and the constant voltage connecting line is a 1-in-1 structure, which can further stabilize the constant voltage signal and further reduce power consumption.

[0377] Figure 24 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure, and is a schematic diagram of the structure of region A in Figure 8. In the exemplary embodiment, the main structure of the display substrate of this embodiment is basically the same as that of the embodiments shown in Figures 9A to 9D, except that the second constant voltage trace 92 is connected to the first initial signal line 41.

[0378] In an exemplary embodiment, at least one circuit unit may further include an active connecting strip 19 and an eighth connecting electrode 58. The active connecting strip 19 may be a strip extending along the second direction Y, and may be disposed on the side of the first active connecting line 10 near the power connecting line 62. A first end of the active connecting strip 19 is connected to the first active connecting line 10, and a second end of the active connecting strip 19 extends towards the power connecting line 62. The eighth connecting electrode 58 may be block-shaped (e.g., rectangular), and may be disposed on the side of the first active connecting line 10 near the power connecting line 62. The eighth connecting electrode 58 may be connected to the second end of the active connecting strip 19 via a via.

[0379] In an exemplary embodiment, in at least one circuit unit, the first active connection line 10 and the active connection strip 19 can be arranged on the same layer and are an integral structure that is interconnected with each other.

[0380] In an exemplary embodiment, the eighth connection electrode 58 may be disposed in the third conductive layer.

[0381] In an exemplary embodiment, at least one fifth connecting block 95 may also be provided on at least one second constant voltage trace 92. The fifth connecting block 95 may be block-shaped (e.g., rectangular), may be located on one side of the second constant voltage trace 92 in the first direction X, and may be connected to the second constant voltage trace 92. The fifth connecting block 95 may be connected to the sixth connecting electrode 56 through a via. Since the first active connecting line 10 is connected to the first initial signal line 41, the interconnection of the first initial signal line 41 extending along the first direction X and the second constant voltage trace 92 extending along the second direction Y is realized, and the first initial signal line 41 and the second constant voltage trace 92 form a mesh-like interconnected structure for transmitting the first initial signal.

[0382] In some possible implementations, the first constant voltage trace 91 or the second constant voltage trace 92 may extend to the border area and connect with the lead transmitting the first initial signal, which is not limited herein.

[0383] Figure 25 is a structural schematic diagram of another display substrate according to an exemplary embodiment of the present disclosure, and is a structural schematic diagram of region A in Figure 8. In the exemplary embodiment, the main structure of the display substrate of this embodiment is basically the same as that of the embodiments shown in Figures 9A to 9D, except that the second constant voltage trace 92 is connected to the second initial signal line 42.

[0384] In an exemplary embodiment, at least one fifth connecting block 95 may also be provided on at least one second constant voltage trace 92. The fifth connecting block 95 may be block-shaped (e.g., rectangular), and may be located on the opposite side of the first direction X of the second constant voltage trace 92 and connected to the second constant voltage trace 92. The fifth connecting block 95 may be connected to the second initial signal line 42 through a via, thereby realizing the interconnection between the second initial signal line 42 extending along the first direction X and the second constant voltage trace 92 extending along the second direction Y. The second initial signal line 42 and the second constant voltage trace 92 form a mesh-like interconnected structure for transmitting the second initial signal.

[0385] In some possible implementations, the first constant voltage trace 91 or the second constant voltage trace 92 may extend to the border area and connect with the lead transmitting the second initial signal, which is not limited herein.

[0386] Figure 26 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure, and is a schematic diagram of the structure of region A in Figure 8. In the exemplary embodiment, the main structure of the display substrate of this embodiment is basically the same as that of the embodiments shown in Figures 9A to 9D, except that the second constant voltage trace 92 is connected to the third initial signal line 43.

[0387] In an exemplary embodiment, at least one fifth connecting block 95 may also be provided on at least one second constant voltage trace 92. The fifth connecting block 95 may be block-shaped (e.g., rectangular), and may be located on the opposite side of the first direction X of the second constant voltage trace 92 and connected to the second constant voltage trace 92. The fifth connecting block 95 may be connected to the third initial signal line 43 through a via, thereby realizing the interconnection between the third initial signal line 43 extending along the first direction X and the second constant voltage trace 92 extending along the second direction Y. The third initial signal line 43 and the second constant voltage trace 92 form a mesh-like interconnected structure for transmitting the third initial signal.

[0388] In some possible implementations, the first constant voltage trace 91 or the second constant voltage trace 92 may extend to the border area and connect with the lead transmitting the third initial signal, which is not limited herein.

[0389] In some possible implementations, the second constant voltage trace 92 can be connected to the first constant voltage trace 91 via a via in the embodiments shown in Figures 24 to 26. The initial signal line (first initial signal line 41, second initial signal line 42 or third initial signal line 43) extending along the first direction X and the first constant voltage trace 91 and the second constant voltage trace 92 extending along the second direction Y form a mesh-like interconnected structure for transmitting the initial signal.

[0390] In some other possible implementations, the first constant voltage trace 91 and the second constant voltage trace 92 may not be connected in the embodiments shown in Figures 24 to 26, and the first constant voltage trace 91 and the second constant voltage trace 92 may transmit different constant voltage signals. For example, the first constant voltage trace 91 may transmit a first power signal or a second power signal, and the second constant voltage trace 92, which is connected to the initial signal line (first initial signal line 41, second initial signal line 42, or third initial signal line 43), may transmit the initial signal.

[0391] In some other possible implementations, in the embodiments shown in Figures 24 to 26, a portion of the second constant voltage traces 92 may be connected to a portion of the first constant voltage traces 91 via vias, while the other portion of the first constant voltage traces 91 and the other portion of the second constant voltage traces 92 may not be connected, and the two portions of the second constant voltage traces 92 may transmit different constant voltage signals respectively.

[0392] For example, the second constant voltage trace 92, located in the same insertion column as the second connection line 82, can be connected to the first power line or the second power line, and connected via a via to the first constant voltage trace 91, which is separately located in the repeating cell row, forming a mesh-like interconnected structure for transmitting the first power signal or the second power signal. The second constant voltage trace 92, separately located in the insertion column, can be connected to the initial signal line (first initial signal line 41, second initial signal line 42, or third initial signal line 43), forming a mesh-like interconnected structure for transmitting the initial signal. This connection method enables different constant voltage traces to be meshed, fully utilizing wiring space and significantly reducing power consumption.

[0393] For example, the first constant voltage trace 91, which is disposed on the same layer as the first connecting line 81, can transmit a first power signal or a second power signal. A portion of the second constant voltage trace 92, disposed on the same layer as the second connecting line 82, can be connected to the first constant voltage trace 91, while another portion of the second constant voltage trace 92 can be connected to the first initial signal line 41 or the third initial signal line 43 located in the second conductive layer. The two portions of the second constant voltage trace 92 can be alternately arranged in the first direction X. This connection method enables traces in different film layers, provides more usable space, allows for more potential meshes, and reduces power consumption.

[0394] Figure 27 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure, and is a schematic diagram of the structure of region B in Figure 8. In the exemplary embodiment, the main structure of the display substrate of this embodiment is basically the same as that of the embodiments shown in Figures 9A to 9D, except that the second constant voltage trace 92 is connected to the first initial signal line 41 and the second initial signal line 42 respectively.

[0395] In an exemplary embodiment, one second constant voltage trace 92 can be connected to the first initial signal line 41 to form a mesh-like interconnected structure for transmitting the first initial signal, and another second constant voltage trace 92 can be connected to the second initial signal line 42 to form a mesh-like interconnected structure for transmitting the second initial signal. The connection structure between the second constant voltage trace 92 and the first initial signal line 41 can be substantially the same as that shown in Figure 24, and the connection structure between the second constant voltage trace 92 and the second initial signal line 42 can be substantially the same as that shown in Figure 25; these details will not be repeated here.

[0396] In an exemplary embodiment, at least one first constant voltage line 91 may be provided with a third break DF3. The first constant voltage lines 91 located on both sides of the third break DF3 are mutually insulated, thereby severing the connection between the mesh connection structure transmitting the first initial signal and the mesh connection structure transmitting the second initial signal.

[0397] In some possible implementations, the display substrate can be divided into multiple sub-regions. Multiple second constant voltage traces 92 in one sub-region can be connected to the first initial signal line 41, multiple second constant voltage traces 92 in another sub-region can be connected to the second initial signal line 42, and multiple second constant voltage traces 92 in yet another sub-region can be connected to the third initial signal line 43. A mesh-like interconnection structure for transmitting the first initial signal, a mesh-like interconnection structure for transmitting the second initial signal, and a mesh-like interconnection structure for transmitting the third initial signal are simultaneously formed on the display substrate. For example, in the first direction X or the second direction Y, the mesh-like interconnection structure for transmitting the first initial signal, the mesh-like interconnection structure for transmitting the second initial signal, and the mesh-like interconnection structure for transmitting the third initial signal can be arranged periodically.

[0398] In other possible implementations, multiple second constant voltage traces 92 in the second region can be connected to the first initial signal line 41, the second initial signal line 42, the third initial signal line 43, and the second power line, respectively. For example, the second constant voltage traces 92 connected to the first initial signal line 41, the second constant voltage traces 92 connected to the second power line, the second constant voltage traces 92 connected to the second initial signal line 42, the second constant voltage traces 92 connected to the second power line, the second constant voltage traces 92 connected to the third initial signal line 43, and the second constant voltage traces 92 connected to the second power line can be arranged periodically.

[0399] In some other possible implementations, the multiple second constant voltage traces 92 in the first region can be connected to the first power line or the second power line to form a mesh-like interconnected structure for transmitting the first power signal or the second power signal. The multiple second constant voltage traces 92 in the second region can be connected to the first initial signal line 41, the second initial signal line 42, or the third initial signal line 43 to form a mesh-like interconnected structure for transmitting the first initial signal, the second initial signal, or the third initial signal.

[0400] In some other possible implementations, the second constant voltage trace 92 located in the same insertion column as the second connection line 82 can be connected to the first initial signal line 41, the second initial signal line 42, or the third initial signal line 43. The second constant voltage trace 92, which is set separately in the insertion column, can be connected to the first power line or the second power line. This disclosure does not limit the scope of the implementation.

[0401] Figure 28 is a schematic diagram of another data connection line and constant voltage trace in an exemplary embodiment of this disclosure. As shown in Figure 28, the main structure of the data connection line and constant voltage trace in this embodiment is basically the same as that in the embodiment shown in Figure 8. The difference is that the line width of the constant voltage trace is different in the first region (FIP region) and the second region (non-FIP region).

[0402] In an exemplary embodiment, the width of the first constant voltage trace 91 in the first region may be greater than the width of the first constant voltage trace 91 in the second region; or, the width of the second constant voltage trace 92 in the first region may be greater than the width of the second constant voltage trace 92 in the second region; or, the width of the first constant voltage trace 91 in the first region may be greater than the width of the first constant voltage trace 91 in the second region; and the width of the second constant voltage trace 92 in the first region may be greater than the width of the second constant voltage trace 92 in the second region. The width of the first constant voltage trace 91 may be a dimension in the second direction Y, and the width of the second constant voltage trace 92 may be a dimension in the first direction X.

[0403] In an exemplary embodiment, the first constant voltage trace 91 and the second constant voltage trace 92 can be respectively disposed in the first region and the second region. Specifically, the first constant voltage trace 91 and the first connecting line 81 in the first region are disposed in the same repeating cell row, and the second constant voltage trace 92 and the second connecting line 82 in the first region are disposed in the same insertion column. The second region only contains the first constant voltage trace 91 and the second constant voltage trace 92, without the first connecting line 81 and the second connecting line 82. Thus, the grid density formed by the first constant voltage trace 91 and the second constant voltage trace 92 in the first region is lower than the grid density formed by the first constant voltage trace 91 and the second constant voltage trace 92 in the second region. By setting the line width of the constant voltage trace in the first region to be greater than that in the second region, this disclosure not only improves the display uniformity of the two regions but also reduces the resistance of the constant voltage trace in the first region.

[0404] Figure 29 is a schematic diagram of another data connection line and constant voltage trace according to an exemplary embodiment of the present disclosure. As shown in Figure 29, the main structure of the data connection line and constant voltage trace in this embodiment is basically the same as that in the embodiment shown in Figure 8. The difference is that the second constant voltage trace 92 can transmit different constant voltage signals.

[0405] In an exemplary embodiment, the multiple second constant voltage traces 92 can be divided into two groups. The second constant voltage traces 92 in the first group can be connected to the first constant voltage trace 91 through vias, and the second constant voltage traces 92 in the second group can be connected to the lateral trace 90 through vias. In the first direction X, the second constant voltage traces 92 in the first group and the second constant voltage traces 92 in the second group can be alternately arranged to form a structure in which the second constant voltage traces 92 alternately transmit different constant voltage signals.

[0406] In an exemplary embodiment, the lateral trace 90 may be a first initial signal line 41, a second initial signal line 42, a third initial signal line 43, or a power connection line 62, and this disclosure does not limit it.

[0407] In an exemplary embodiment, the horizontal trace 90 and the second constant voltage trace 92 can be arranged on the same layer, or the horizontal trace 90 and the second constant voltage trace 92 can be arranged on different layers.

[0408] In an exemplary embodiment, since the lateral trace 90 and the second constant voltage trace 92 are disposed on different conductive layers, the orthographic projection of the lateral trace 90 on the substrate and the orthographic projection of the second constant voltage trace 92 on the substrate can be configured to at least partially overlap.

[0409] Figure 30 is a schematic diagram of another data connection line and constant voltage wiring according to an exemplary embodiment of the present disclosure. As shown in Figure 30, the main structure of the data connection line and constant voltage wiring in this embodiment is basically the same as that in the embodiment shown in Figure 8. The difference is that a second connection line 82 and a constant voltage connection line 93 are respectively provided in the insertion column, and a constant voltage connection line 93 is provided in the cell column.

[0410] In an exemplary embodiment, at least one unit column may be provided with a constant voltage connection line 93, and at least one insertion column may be provided with two vertical lines. The two vertical lines may be a second connection line 82 and a constant voltage connection line 93, or they may be a second power supply line 92 and a constant voltage connection line 93. That is, the second connection line 82 (second power supply line 92) is a 3-in-1 structure, and the constant voltage connection line is a 1-in-1 structure, which can further stabilize the constant voltage signal and further reduce power consumption.

[0411] In an exemplary embodiment, the constant voltage connection line 93 can be connected to the first initial signal line, the second initial signal line, or the third initial signal line to form a mesh-like interconnected structure for transmitting the initial signal, which is not limited herein.

[0412] In an exemplary embodiment, the constant voltage connection line 93 can be disposed between the second connection line 82 and the data signal line 70, which can effectively avoid crosstalk of the data signal.

[0413] In an exemplary embodiment, if the constant voltage connection line 93 is not disposed between the second connection line 82 and the data signal line 70, the spacing between the constant voltage connection line 93 and the data signal line 70 can be set to be smaller than the spacing between the constant voltage connection line 93 and the second connection line 82. The spacing can be the dimension of the first direction X.

[0414] The structure and preparation process described above in this disclosure are merely illustrative examples. In the exemplary embodiments, the corresponding structure and the patterning process can be changed or added or reduced according to actual needs. This disclosure does not limit these aspects.

[0415] In exemplary embodiments, the display substrate of this disclosure can be applied to display devices with pixel driving circuits, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., and this disclosure does not limit it.

[0416] This disclosure also provides a method for fabricating a display substrate to prepare the aforementioned display substrate. In an exemplary embodiment, the method for fabricating the display substrate may include: forming a driving structure layer on a substrate;

[0417] The driving structure layer includes multiple repeating units forming multiple repeating unit rows and multiple repeating unit columns, with insertion columns provided between adjacent repeating unit columns; at least one repeating unit includes multiple circuit units arranged sequentially along a first direction, at least one circuit unit including a pixel driving circuit and a data signal line extending along a second direction, the data signal line being connected to the pixel driving circuit and configured to provide data signals to the pixel driving circuit, the first direction and the second direction intersecting; the driving structure layer also includes at least one first connecting line and at least one first constant voltage trace extending along the first direction, and at least one second connecting line and at least one second constant voltage trace extending along the second direction, the first end of the first connecting line being connected to the data signal line, the second end of the first connecting line being connected to the second connecting line, and at least one second constant voltage trace being connected to at least one first constant voltage trace, forming a mesh-like interconnected structure for transmitting constant voltage signals; the second connecting line and the second constant voltage trace are disposed in the insertion columns.

[0418] This disclosure also provides a display device, which includes the aforementioned display substrate. The display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator, and the embodiments of the present invention are not limited thereto.

[0419] While the embodiments disclosed herein are as described above, it should be noted that these embodiments are merely exemplary and not restrictive. Therefore, this disclosure is not limited to the specific content shown and described herein. Various modifications, substitutions, or omissions can be made to the form and details of the embodiments without departing from the scope of this disclosure.

Claims

1. A display substrate, characterized by, The system includes a driving structure layer disposed on a substrate; the driving structure layer includes multiple repeating units forming multiple repeating unit rows and multiple repeating unit columns, with insertion columns disposed between adjacent repeating unit columns; at least one repeating unit includes multiple circuit units arranged sequentially along a first direction, at least one circuit unit including a pixel driving circuit and a data signal line extending along a second direction, the data signal line being connected to the pixel driving circuit and configured to provide data signals to the pixel driving circuit, the first direction and the second direction intersecting; the driving structure layer further includes at least one first connecting line and at least one first constant voltage trace extending along the first direction, and at least one second connecting line and at least one second constant voltage trace extending along the second direction, a first end of the first connecting line being connected to the data signal line, a second end of the first connecting line being connected to the second connecting line, and at least one second constant voltage trace being connected to at least one first constant voltage trace, forming a mesh-like interconnected structure for transmitting constant voltage signals; the second connecting line and the second constant voltage trace are disposed in the insertion columns.

2. The display substrate of claim 1, wherein, At least one repeating unit comprises three circuit units. 3.The display substrate of claim 1, wherein, The pixel driving circuit includes at least a storage capacitor, a first transistor as a first initialization transistor, and a second transistor as a compensation transistor. The first transistor includes at least a first gate electrode and a first active layer. The second transistor includes at least a second gate electrode and a second active layer. The storage capacitor includes a first electrode plate and a second electrode plate. The orthographic projection of the second electrode plate on the substrate at least partially overlaps with the orthographic projection of the first electrode plate on the substrate. The first electrode plate is connected to a second region of the first active layer and a first region of the second active layer. The second electrode plate is connected to a first power line. At least one circuit unit further includes a shielding electrode connected to the second electrode plate, wherein the orthographic projection of the shielding electrode on the substrate at least partially overlaps with the orthographic projection of the first active layer between the two gate electrodes of the first transistor on the substrate, and the orthographic projection of the shielding electrode on the substrate at least partially overlaps with the orthographic projection of the second active layer between the two gate electrodes of the second transistor on the substrate. The orthographic projection of at least one of the second connecting lines on the substrate at least partially overlaps with the orthographic projection of the shielding electrode on the substrate.

4. The display substrate of claim 3, wherein, The pixel driving circuit further includes a third transistor as a driving transistor and a fourth transistor as a data writing transistor. The third transistor includes at least a third active layer, and the fourth transistor includes at least a fourth active layer. A first region of the third active layer is connected to a second region of the fourth active layer. At least one circuit unit further includes a compensation electrode connected to the second electrode plate. The orthographic projection of the compensation electrode on the substrate at least partially overlaps with the orthographic projection of the connection region of the first region of the third active layer and the second region of the fourth active layer on the substrate. 5.The display substrate of claim 3, wherein, The pixel driving circuit further includes a fourth transistor as a data writing transistor. The second gate electrode is connected to a first scan signal line extending along the first direction. The gate electrode of the fourth transistor is connected to a second scan signal line extending along the first direction. The first electrode of the fourth transistor is connected to the data signal line. The second scan signal line is disposed on the side of the first scan signal line away from the second electrode. In the second direction, the first connecting line and the first constant voltage trace are disposed between the first scan signal line and the second electrode, or the first connecting line and the first constant voltage trace are disposed between the first scan signal line and the second scan signal line. 6.The display substrate of claim 5, wherein, At least one circuit unit further includes a data connection electrode, the data signal line being connected to the data connection electrode via a via, and the data connection electrode being connected to the first electrode of the fourth transistor via a via; at least one repeating unit further includes a data connection block, the data connection block being connected to the first connection line and the data connection electrode in one circuit unit respectively, and the data connection block being disposed on the side of the first scan signal line near the second electrode plate. 7.The display substrate of claim 5, wherein, At least one repeating unit further includes a data connection block connected to the first connection line, the data connection block being connected to the first electrode of the fourth transistor in a circuit unit via a via, the data signal line being connected to the data connection block via a via, and the data connection block being disposed on the side of the first scan signal line away from the second electrode plate. 8.The display substrate of claim 3, wherein, The pixel driving circuit further includes a fifth transistor as a first light-emitting control transistor. The gate electrode of the fifth transistor is connected to the light-emitting signal line, and the first electrode of the fifth transistor is connected to the first power supply line. The light-emitting signal line is disposed on one side of the second electrode plate in the second direction. In the second direction, the first connecting line and the first constant voltage trace are disposed on the side of the light-emitting signal line away from the second electrode plate. 9.The display substrate of claim 1, wherein, The display substrate further includes a light-emitting structure layer disposed on the side of the driving structure layer away from the substrate. The light-emitting structure layer includes at least a red light-emitting unit, a green light-emitting unit, and a blue light-emitting unit. The red light-emitting unit includes at least a first anode, the green light-emitting unit includes at least a second anode, and the blue light-emitting unit includes at least a third anode. The orthographic projections of at least one first anode and at least one second anode on the substrate at least partially overlap with the orthographic projections of the second connecting line or the second constant voltage trace on the substrate, and the orthographic projections of at least one third anode on the substrate at least partially overlap with the orthographic projections of the data signal line on the substrate. 10.The display substrate of claim 9, wherein, At least one third anode is provided with an anode groove, the anode groove being a strip-shaped portion extending along the second direction, and the orthographic projection of the anode groove on the substrate at least partially overlaps with the orthographic projection of the data signal line on the substrate. 11.The display substrate of claim 1, wherein, At least one insertion column is further provided with at least one constant voltage connection line extending along the second direction; in the first direction, the constant voltage connection line is disposed between the second connection line and the data signal line, or the constant voltage connection line is disposed between the second constant voltage trace and the data signal line. 12.The display substrate of claim 11, wherein, At least one circuit unit further includes a first initial signal line, a second initial signal line, and a third initial signal line extending along the first direction. The pixel driving circuit is connected to the first initial signal line, the second initial signal line, and the third initial signal line, respectively. The first initial signal line, the second initial signal line, and the third initial signal line are configured to provide a first initial signal, a second initial signal, and a third initial signal to the pixel driving circuit, respectively. At least one of the constant voltage connection lines is connected to the first initial signal line, the second initial signal line, or the third initial signal line. 13.The display substrate according to any one of claims 1 to 12, characterized in that, The display substrate further includes a light-emitting structure layer disposed on the side of the driving structure layer away from the substrate. The light-emitting structure layer includes a plurality of light-emitting units, at least one light-emitting unit includes a light-emitting device, the light-emitting device is connected to a second power line, and the second power line is configured to provide a second power signal to the light-emitting device. At least one circuit unit further includes a first initial signal line, a second initial signal line, a third initial signal line extending along the first direction, and a first power line extending along the second direction. The pixel driving circuit is connected to the first initial signal line, the second initial signal line, the third initial signal line, and the first power line, respectively. The first initial signal line, the second initial signal line, and the third initial signal line are configured to provide a first initial signal, a second initial signal, and a third initial signal to the pixel driving circuit, respectively. The first power line is configured to provide a first power signal to the pixel driving circuit. The second constant voltage trace is connected to any one or more of the following: the first initial signal line, the second initial signal line, the third initial signal line, the first power line, or the second power line. 14.The display substrate of claim 13, wherein, The display substrate is divided into multiple sub-regions. The second constant voltage trace in one sub-region is connected to the first initial signal line, the second constant voltage trace in another sub-region is connected to the second initial signal line, and the second constant voltage trace in yet another sub-region is connected to the third initial signal line, thus forming a mesh-connected structure for transmitting the first initial signal, a mesh-connected structure for transmitting the second initial signal, and a mesh-connected structure for transmitting the third initial signal. 15.The display substrate of claim 13, wherein, Multiple second constant voltage traces are respectively connected to the first initial signal line, the second initial signal line and the third initial signal line. In the first direction, the second constant voltage traces connected to the first initial signal line, the second constant voltage traces connected to the second initial signal line and the second constant voltage traces connected to the third initial signal line are arranged periodically. 16.The display substrate of claim 13, wherein, Multiple second constant voltage traces are respectively connected to the first initial signal line, the second initial signal line, the third initial signal line, and the second power line. In the first direction, the second constant voltage traces connected to the first initial signal line, the second constant voltage traces connected to the second power line, the second constant voltage traces connected to the second initial signal line, the second constant voltage traces connected to the second power line, the second constant voltage traces connected to the third initial signal line, and the second constant voltage traces connected to the second power line are arranged periodically. 17.The display substrate of claim 13, wherein, The second constant voltage trace located in the same insertion column as the second connection line is connected to the first power line or the second power line. The second constant voltage trace separately located in the insertion column is connected to the first initial signal line, the second initial signal line, or the third initial signal line. 18.The display substrate of claim 13, wherein, In a direction perpendicular to the substrate, the display substrate includes multiple conductive layers. The second constant voltage trace, the first constant voltage trace, and at least one initial signal line are disposed in different conductive layers. A portion of the second constant voltage trace is connected to the first constant voltage trace, and another portion of the second constant voltage trace is connected to the initial signal line.

19. A display device comprising: Includes the display substrate as described in any one of claims 1 to 18.

20. A method for preparing a display substrate, characterized in that, This includes forming a driving structure layer on the substrate; The driving structure layer includes multiple repeating units forming multiple repeating unit rows and multiple repeating unit columns, with insertion columns provided between adjacent repeating unit columns; at least one repeating unit includes multiple circuit units arranged sequentially along a first direction, at least one circuit unit including a pixel driving circuit and a data signal line extending along a second direction, the data signal line being connected to the pixel driving circuit and configured to provide data signals to the pixel driving circuit, the first direction and the second direction intersecting; the driving structure layer also includes at least one first connecting line and at least one first constant voltage trace extending along the first direction, and at least one second connecting line and at least one second constant voltage trace extending along the second direction, the first end of the first connecting line being connected to the data signal line, the second end of the first connecting line being connected to the second connecting line, and at least one second constant voltage trace being connected to at least one first constant voltage trace, forming a mesh-like interconnected structure for transmitting constant voltage signals; the second connecting line and the second constant voltage trace are disposed in the insertion columns.

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