Semiconductor device

Abstract

Provided in the present application is a semiconductor device. A semiconductor epitaxial wafer comprises an active region and an edge terminal region surrounding the active region; several source regions are disposed in the active region; a gate electrode layer of a first conductive layer is disposed in the active region, and a gate bus layer connected to the gate electrode layer is disposed in the edge terminal region; an inter-layer dielectric layer covers the first conductive layer; a second conductive layer is disposed on the side of the inter-layer dielectric layer away from the semiconductor epitaxial wafer, and comprises a source pad and a gate pad, the source pad being at least disposed in the active region and being electrically connected to the active region, and the gate pad being at least disposed in the edge terminal region and being electrically connected to the gate bus layer; the first conductive layer further comprises a capacitor plate layer, and both the gate electrode layer and the gate bus layer are insulated from the capacitor plate layer; the source pad is electrically connected to the capacitor plate layer; and a portion of the gate pad and a portion of the capacitor plate layer are stacked and isolated by means of a dielectric layer, and the thickness of the dielectric layer is less than the thickness of the inter-layer dielectric layer.

Description

semiconductor devices Cross-reference to related applications

[0001] This application claims priority to Chinese Patent Application No. 202411451140.0, filed on October 17, 2024, entitled "Semiconductor Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to a semiconductor device. Background Technology

[0003] Power semiconductor devices, as core components of power electronic systems, have always been indispensable electronic components in modern life. They are widely used in consumer electronics, automotive electronic systems, smart grids, and various industrial equipment, locomotives, aerospace, and marine systems. SiC MOSFETs (silicon carbide-based metal oxide semiconductor field-effect transistors) have become the mainstream devices in the high voltage and high frequency fields due to their advantages such as high input impedance, good temperature stability, excellent high-frequency and high-voltage performance, and large safe operating area.

[0004] However, existing semiconductor devices are prone to crosstalk. Technical solutions

[0005] A semiconductor device according to some embodiments includes a semiconductor epitaxial wafer, the semiconductor epitaxial wafer including an active region and an edge termination region surrounding the active region;

[0006] Several source regions are disposed in the active region;

[0007] The first conductive layer includes a gate electrode layer and a gate bus layer that are electrically connected to each other; the gate electrode layer is disposed in the active region, and the gate bus layer is disposed in the edge terminal region;

[0008] An interlayer dielectric layer covers the first conductive layer;

[0009] A second conductive layer is disposed on the side of the interlayer dielectric layer away from the semiconductor epitaxial wafer; the second conductive layer includes a source pad and a gate pad; the source pad is at least disposed in the active region and electrically connected to the source region; the gate pad is at least disposed in the edge termination region and electrically connected to the gate bus layer;

[0010] The first conductive layer further includes a capacitor plate layer, and the gate electrode layer and the gate bus layer are both insulated from the capacitor plate layer; the source pad is electrically connected to the capacitor plate layer; a portion of the gate pad is stacked with a portion of the capacitor plate layer and isolated by a dielectric layer, the thickness of which is less than the thickness of the interlayer dielectric layer.

[0011] The semiconductor device according to some embodiments includes:

[0012] A semiconductor epitaxial wafer includes an active region and an edge termination region surrounding the active region;

[0013] Several source regions are disposed in the active region;

[0014] The first conductive layer includes a gate electrode layer and a gate bus layer that are electrically connected to each other; the gate electrode layer is disposed in the active region, and the gate bus layer is disposed in the edge terminal region;

[0015] An interlayer dielectric layer covers the first conductive layer;

[0016] A second conductive layer is disposed on the side of the interlayer dielectric layer away from the semiconductor epitaxial wafer; the second conductive layer includes a source pad and a gate pad; the source pad is at least disposed in the active region and electrically connected to the source region; the gate pad is at least disposed in the edge termination region and electrically connected to the gate bus layer;

[0017] Wherein, a portion of the gate electrode layer or a portion of the gate bus layer is stacked with a portion of the source pad and isolated by a dielectric layer, and the thickness of the dielectric layer is less than the thickness of the interlayer dielectric layer;

[0018] The interlayer dielectric layer has a first opening, such that a portion of the gate electrode layer or a portion of the gate bus layer is exposed to form a first exposed portion; the dielectric layer is disposed within the first opening and covers the first exposed portion; a portion of the source pad extends into the first opening and is located on the surface of the dielectric layer away from the first exposed portion.

[0019] The semiconductor device according to some embodiments includes:

[0020] A semiconductor epitaxial wafer includes an active region and an edge termination region surrounding the active region;

[0021] Several source regions are disposed in the active region;

[0022] The first conductive layer includes a gate electrode layer and a gate bus layer that are electrically connected to each other; the gate electrode layer is disposed in the active region, and the gate bus layer is disposed in the edge terminal region;

[0023] An interlayer dielectric layer covers the first conductive layer;

[0024] A second conductive layer is disposed on the side of the interlayer dielectric layer away from the semiconductor epitaxial wafer; the second conductive layer includes a source pad and a gate pad; the source pad is at least disposed in the active region and electrically connected to the source region; the gate pad is at least disposed in the edge termination region and electrically connected to the gate bus layer;

[0025] The source pad is stacked with a portion of the gate pad and isolated by a dielectric layer to form a gate-source capacitor. The thickness of the dielectric layer is less than the thickness of the interlayer dielectric layer. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein:

[0027] Figure 1 is an equivalent circuit diagram of a semiconductor device;

[0028] Figure 2 is a top view of some embodiments of the semiconductor device provided in this application;

[0029] Figure 3 is a cross-sectional view of a portion of the structure of the semiconductor device shown in Figure 2 along line A-A'.

[0030] Figure 4a is a schematic diagram of the region division of a semiconductor device;

[0031] Figure 4b is a top view of the semiconductor device shown in Figure 2 excluding the second conductive layer;

[0032] Figure 4c is an enlarged view of the pad area in Figure 4b;

[0033] Figure 5 is a partial cross-sectional view of the structure shown in Figure 4b along line A-A'.

[0034] Figure 6a is another cross-sectional view of a portion of the structure of the semiconductor device shown in Figure 2 along line A-A';

[0035] Figure 6b is an enlarged view of point M in Figure 6a;

[0036] Figure 7 is a schematic diagram of the structure for forming the second conductive layer on the semiconductor device shown in Figure 6a;

[0037] Figure 8 is another top view of the semiconductor device shown in Figure 2, excluding the interlayer dielectric layer and the second conductive layer.

[0038] Figure 9 is a partial sectional view of the structure shown in Figure 8 along line B-B'.

[0039] Figure 10 is a schematic diagram of the structure on which a passivation layer is formed in the structure shown in Figure 3;

[0040] Figure 11 is a top view of some other embodiments of the semiconductor device provided in this application;

[0041] Figure 12 is a partial structural cross-sectional view of the semiconductor device shown in Figure 11 along line C-C' provided in an embodiment of this application;

[0042] Figure 13 is a partial structural cross-sectional view of a semiconductor device provided in another embodiment of this application along line C-C'.

[0043] Figures 14 and 15 are partial structural cross-sectional views of semiconductor devices provided in different embodiments of this application along line C-C'.

[0044] Figure 16 is a flowchart of a method for fabricating a semiconductor device according to an embodiment of this application;

[0045] Figure 17 is a schematic diagram of the structure of a partial intermediate product after the semiconductor epitaxial wafer is processed by step S2 in Figure 16;

[0046] Figure 18 is a schematic diagram of the structure of a partial intermediate product after the semiconductor epitaxial wafer is processed by step S3 in Figure 16.

[0047] Figure 19 is a partial cross-sectional view of the semiconductor device shown in Figure 18 along line C-C'.

[0048] Figure 20 is a top view of a portion of the intermediate product structure of a semiconductor epitaxial wafer after step S5;

[0049] Figure 21 is a partial cross-sectional view of the structure shown in Figure 20 along line C-C'.

[0050] Figure 22 is a top view of a portion of the intermediate product structure of the semiconductor epitaxial wafer after processing in step S6 of Figure 16;

[0051] Figure 23 is a partial sectional view of the structure shown in Figure 22 along line C-C'.

[0052] Explanation of reference numerals in the attached figures

[0053] 1-Semiconductor epitaxial wafer; A1-Active region; A2-Edge termination region; A3-Ring trace region; A4-Pad region; 11-Termination structure; 12-Well region; 2-Well region contact region; 18-Drain electrode; 13-Source region; 3-First conductive layer; 31-Gate electrode layer; 31a-Gate structure; 32-Gate bus layer; 33-Capacitor plate layer; 4-Interlayer dielectric layer; 41-First opening; 42-Second opening; 43-Third opening; 44-Fourth opening; 5-Second conductive layer; 51-Source pad; 52-Gate pad; 6-Dielectric layer; 61-Aperture; 7a-Gate insulating layer; 7b-Traffic insulating layer; 7c-Passivation layer; 71-Fifth opening; 72-Sixth opening; b1-First sidewall; b2-Second sidewall; b3-Third sidewall; b4-Fourth sidewall. Embodiments of the present invention

[0054] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0055] The terms "first," "second," and "third" in this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationships and movements between components in a specific orientation (as shown in the figures). If the specific orientation changes, the directional indications also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0056] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0057] In practical applications, there are a large number of converters, many of which have a dual-transistor structure, such as half-bridge, three-phase full-bridge, and three-level converters. When the active transistor switches, its own drive voltage does not oscillate or glitches, while the drive voltage of the synchronous rectifier transistor will exhibit glitches. That is to say, in a bridge circuit, the active switching action of a device will affect the Vgs (maximum gate-source voltage) of its counterpart transistor; this phenomenon is called crosstalk.

[0058] Referring to Figure 1, Cds (source-drain parasitic capacitance), Cgd (gate-drain parasitic capacitance), and Cgs (gate-source parasitic capacitance) are the junction capacitances of the interfered transistor. Rg(int) is the internal resistance of the device's gate bus layer, and Rg(ext) is the external drive resistance. The turn-off drive voltage is V. DRV（off） .

[0059] Due to the switching action of the transistor, the voltage Vds at the terminal of the affected transistor changes by dV when the transistor is turned on. DS(on) The speed of / dt increases, and when the actuator is turned off, it is at dV. DS(off) / dt speed decreases. The positive spike V of the gate bus layer voltage in crosstalk is enabled. CK-on(max) and the negative voltage spike V in the turn-off crosstalk gate bus layer CK-off(min) They are respectively:

[0060]

[0061]

[0062] As can be seen from the above formula, the larger Cgd is, the larger the displacement current, leading to severe crosstalk; the larger Cgs is, the slower the displacement current charges it, thus mitigating crosstalk. Therefore, module users generally require the ratio of Ciss to Crss to be greater than 200, or even greater than 400; however, most existing semiconductor devices cannot meet the requirement that the ratio of Ciss to Crss (i.e., Ciss / Crss) is greater than 400, making semiconductor devices prone to crosstalk problems. Here, Ciss is the input capacitance; Crss is the reverse capacitance.

[0063] Please refer to Figures 2 to 5. This application provides a semiconductor device, which may be a SiC MOSFET (silicon carbide-based metal-oxide-semiconductor field-effect transistor). The semiconductor device includes a semiconductor epitaxial wafer 1, a plurality of source regions 13, a first conductive layer 3, an interlayer dielectric layer 4, and a second conductive layer 5.

[0064] As shown in Figures 2 and 3, the semiconductor epitaxial wafer 1 includes an active region A1 and an edge termination region A2 surrounding the active region A1. A plurality of source regions 13 are disposed within the semiconductor epitaxial wafer 1 and located within the active region A1, with each source region 13 extending from one side of the active region A1 to the opposite side. As shown in Figure 3, the edge termination region A2 is provided with a termination structure 11 to protect the device from damage caused by overvoltage or overcurrent. The termination structure 11 can be a field-limiting ring structure or a junction termination extension region (JTE region). The functions and structures of the field-limiting ring structure and the junction termination extension region are existing technologies and will not be described in detail here.

[0065] As shown in Figure 3, the first conductive layer 3 includes a gate electrode layer 31 and a gate bus layer 32 that are electrically connected to each other. The gate electrode layer 31 is disposed on the semiconductor epitaxial wafer 1 and located in the active region A1. The gate electrode layer 31 includes a plurality of gate structures 31a spaced apart along the first direction Y. The orthogonal projection of each gate structure 31a on the semiconductor epitaxial wafer 1 is located between two source regions 13. In some embodiments, the first conductive layer 3 is a doped polysilicon layer or a conductive metal, which is not limited here, as long as it has a conductive function.

[0066] In some embodiments, the semiconductor device further includes a plurality of well regions 12 and a plurality of well region contact regions 2. The plurality of well regions 12 and the plurality of well region contact regions 2 are disposed within the semiconductor epitaxial wafer 1. The plurality of well regions 12, the plurality of well region contact regions 2 and the plurality of source regions 13 are correspondingly disposed. The well regions 12, the well region contact regions 2 and the source regions 13 all extend along the surface of the semiconductor epitaxial wafer 1 from one side of the active region A1 to the opposite side of the active region A1 within the semiconductor epitaxial wafer 1.

[0067] The semiconductor epitaxial wafer 1 and the source region 13 have a first conductivity type, and the ion doping concentration of the source region 13 is greater than the ion doping concentration of the semiconductor epitaxial wafer 1; the well region 12 and the well region contact region 2 have a second conductivity type, and the ion doping concentration of the well region contact region 2 is greater than the ion doping concentration of the well region 12.

[0068] The first conductivity type can be either N-type or P-type, and the second conductivity type can be either N-type or P-type. This application takes N-type as the first conductivity type and P-type as the second conductivity type as an example.

[0069] Referring to Figures 2 and 3, the gate bus layer 32 is disposed in the edge terminal region A2; and the gate bus layer 32 surrounds the active region A1 and is connected to the end of each gate structure 31a. Referring to Figure 4b, the gate bus layer 32 is connected to the end of each gate structure 31a along the second direction X, and multiple gate structures 31a are spaced apart in the first direction Y, with the gate bus layer 32 surrounding the periphery of all gate structures 31a.

[0070] In this embodiment, by placing the gate bus layer 32 on the edge termination region A2, compared to placing the gate bus layer 32 on the active region A1 in other methods, the area of ​​the active region A1 can be saved. This makes the semiconductor device basically active region A1 except for the edge termination region A2, thereby improving the device's outflow capability and reducing on-resistance. Furthermore, the gate bus layer 32 is connected to the end of each gate structure 31a extending to the edge of the active region A1, and the gate bus layer 32 can drive each gate structure 31a, thus not affecting the reliability of the device.

[0071] Referring to Figure 3, the interlayer dielectric layer 4 covers the first conductive layer 3. The second conductive layer 5 is disposed on the side of the interlayer dielectric layer 4 away from the semiconductor epitaxial wafer 1. The second conductive layer 5 includes a source pad 51 and a gate pad 52; the source pad 51 and the gate pad 52 are used for electrical connection between the device and external equipment. Specifically, the source pad 51 is at least disposed in the active region A1 and electrically connected to the source region 13. The gate pad 52 is at least disposed in the edge termination region A2 and electrically connected to the gate bus layer 32.

[0072] The gate pad 52 may be entirely disposed in the edge termination region A2 and surrounding the active region A1. Alternatively, at least a portion of the gate pad 52 may extend into the active region A1 and be insulated from the source pad 51, as may be designed as needed. The materials of the source pad 51 and the gate pad 52 include, but are not limited to, any one or a combination of aluminum, copper, tungsten, silver, or nickel.

[0073] Interlayer dielectric layer 4 covers each gate structure 31a and is used to isolate each gate structure 31a; referring to FIG5, in the active region A1, the area of ​​interlayer dielectric layer 4 corresponding to each source region 13 has a third opening 43, so that at least a portion of each source region 13 is exposed through its corresponding third opening 43, and a portion of the source pad 51 extends into the third opening 43 and contacts and is electrically connected to the source region 13.

[0074] In some embodiments, the semiconductor device further includes a plurality of ohmic contact metals (not shown), each disposed within a third opening 43 and electrically connected to the corresponding source region 13; the source pad 51 forms ohmic contact metal contact with each source region 13 to electrically connect to the source region 13 via the ohmic contact metal. The material of the ohmic contact metal includes, but is not limited to, any one or a combination of Ti, Ni, Al, Au, Ta, or W.

[0075] Referring to Figures 3 and 5, the interlayer dielectric layer 4 also covers the gate bus layer 32 for isolating the gate bus layer 32. In the edge termination region A2, the interlayer dielectric layer 4 has a fourth opening 44 corresponding to the area of ​​the gate bus layer 32, so that at least a portion of the gate bus layer 32 is exposed through the fourth opening 44. A portion of the gate pad 52 extends into the fourth opening 44 and is electrically connected to the gate bus layer 32.

[0076] In some embodiments, the material of the interlayer dielectric layer 4 can be silicon oxide or silicon nitride, and the thickness of the interlayer dielectric layer 4 is 800nm-1000nm. For example, the thickness of the interlayer dielectric layer 4 can be 800nm, 850nm, 900nm, 950nm, or 1000nm, etc., and is not limited here. The specific design is based on the actual device size.

[0077] In one embodiment, referring to FIG3, the first conductive layer 3 further includes a capacitor plate layer 33, and the gate electrode layer 31 and the gate bus layer 32 are both insulated from the capacitor plate layer 33; the source pad 51 is electrically connected to the capacitor plate layer 33; a portion of the gate pad 52 is stacked with a portion of the capacitor plate layer 33 and isolated by the dielectric layer 6; wherein, the thickness of the dielectric layer 6 is less than the thickness of the interlayer dielectric layer 4. The gate bus layer 32 may be arranged around the periphery of the capacitor plate layer 33 and spaced apart from the capacitor plate layer 33. In this way, during the formation of the semiconductor device, a portion of the original gate bus layer 32 can be partitioned off to serve as the capacitor plate layer 33; thus, the capacitor plate layer 33 can be formed without increasing the area of ​​the semiconductor device.

[0078] In some embodiments, the thickness of dielectric layer 6 can be 50-200 nanometers; for example, the thickness of dielectric layer 6 can be 50 nm, 80 nm, 110 nm, 140 nm, 170 nm, or 200 nm, etc., and is not limited thereto. Dielectric layer 6 is a thermally oxidized silicon oxide layer. The gate-source capacitance value (C) can be adjusted by regulating the thickness of dielectric layer 6. gs The size of ) is adjusted to maximize Cgs, thereby making the Ciss / Crss range adjustable.

[0079] The above scheme, by making the first conductive layer 3 include a capacitor plate layer 33, and making the gate electrode layer 31 and the gate bus layer 32 insulated from the capacitor plate layer 33; the source pad 51 is electrically connected to the capacitor plate layer 33; a portion of the gate pad 52 is stacked with a portion of the capacitor plate layer 33 and isolated by the dielectric layer 6, so that an additional gate-source capacitance is formed by the gate pad 52 covering a portion of the capacitor plate layer 33, the dielectric layer 6, and the portion of the capacitor plate layer 33 and the gate pad 52 stacked together, thereby increasing the Ciss / Crss ratio and reducing the risk of crosstalk in semiconductor devices.

[0080] The above scheme involves partitioning a portion of the original first conductive layer 3 to serve as a capacitor plate layer 33. For example, if the capacitor plate layer 33 is located in the edge terminal region A2, it is equivalent to partitioning a portion of the original gate bus layer 32 to serve as a capacitor plate layer 33, thereby forming an additional gate-source capacitance and increasing Ciss / Crss. This design only involves a change in the position of the gate pad 52, and since the capacitor plate layer 33 does not affect the connection between the gate pad 52 and the source pad 51 and other structures in the active region A1, the modification is minor and will not affect the reliability of the original semiconductor device, greatly improving the crosstalk immunity of the semiconductor device. At the same time, it does not increase the area of ​​the semiconductor device.

[0081] In some embodiments, the capacitor plate layer 33 is disposed on the same layer as the gate electrode layer 31 and the gate bus layer 32, and they are made of the same material. In this way, during the fabrication of the semiconductor device, the capacitor plate layer 33 can be formed synchronously with the gate electrode layer 31 and the gate bus layer 32 using the same process steps, thus avoiding additional process steps and saving costs.

[0082] In some embodiments, referring to FIG5, the capacitor plate layer 33 is located in the edge terminal region A2; the interlayer dielectric layer 4 has a first opening 41, such that the capacitor plate layer 33 is partially exposed to form a first exposed portion; the dielectric layer 6 is disposed within the first opening 41 and covers the first exposed portion. A portion of the gate pad 52 extends into the first opening 41 and is located on the surface of the dielectric layer 6 away from the first exposed portion.

[0083] By placing the capacitor plate layer 33 in the edge terminal region A2, an additional gate-source capacitor structure can be formed; and compared with placing the capacitor plate layer 33 in the active region A1, the area of ​​the active region A1 can be saved, so that the semiconductor device is basically active region A1 except for the edge terminal region A2, thereby improving the outflow capability of the device; there is no need to consider the limitation of occupied area too much.

[0084] The following are two ways to achieve electrical connection between the source pad 51 and the capacitor plate layer 33.

[0085] In one embodiment, referring to Figures 3 to 5, the dielectric layer 6 has an opening 61; a portion of the source pad 51 sequentially contacts the first exposed portion through the first opening 41 and the opening 61 to electrically connect with the capacitor plate layer 33. A portion of the source pad 51 extends into the first opening 41 and further extends into the opening 61 to contact the first exposed portion. The portion of the source pad 51 extending into the first opening 61 and the portion of the gate pad 52 extending into the first opening 41 can be spaced apart to achieve insulation between them. The opening 61 can be spaced apart from the sidewall of the first opening 41 of the interlayer dielectric layer 4 along the first direction Y, thus reducing processing difficulty.

[0086] To ensure that the area of ​​the portion of the gate pad 52 extending into the first opening 41 is large enough to meet the requirements of subsequent packaging wire bonding, the opening 61 needs to be located close to the edge of the dielectric layer 6, and its width cannot be too large. In some embodiments, referring to FIG4c, the opening 61 is disposed at the edge of the dielectric layer 6 near the active region A1. The first opening 41 has opposing first sidewalls b1 and b2 along the first direction Y; along the first direction Y, the first distance L1 between the opening 61 and the first sidewall b1 is less than the second distance L2 between the opening 61 and the second sidewall b2.

[0087] To ensure effective contact between the source pad 51 and the capacitor plate layer 33, and to facilitate the opening 61, in some embodiments, the first opening 41 has opposing third sidewalls b3 and fourth sidewalls b4 along the second direction X; along the second direction X, the opening 61 is spaced apart from the third sidewall b3, and the opening 61 is spaced apart from the fourth sidewall b4. The length L3 of the opening 61 along the second direction X is greater than the length L4 of the opening 61 along the first direction Y.

[0088] In another embodiment, referring to Figures 6a and 7, the interlayer dielectric layer 4 has a second opening 42 spaced from the first opening 41, such that a portion of the capacitor electrode layer 33 is exposed to form a second exposed portion; that is, the portion of the capacitor electrode layer 33 exposed through the second opening 42 forms the second exposed portion. A portion of the source pad 51 extends into the second opening 42 and contacts the second exposed portion to achieve electrical connection between the source pad 51 and the capacitor electrode layer 33. In this way, a larger area of ​​the gate pad 52 can extend into the first opening 41 to be stacked with the capacitor electrode layer 33; thereby effectively increasing the relative area between the gate pad 52 and the capacitor electrode layer 33, increasing the Cgs value, and further reducing the risk of crosstalk in the semiconductor device. In addition, the second opening 42 can be formed in the same patterning process step as the third opening 43 and the fourth opening 44, which can optimize the process flow and effectively reduce the process complexity.

[0089] The following is a description of the specific location of the capacitor plate layer 33 in the edge terminal area A2 provided in different embodiments of this application.

[0090] In one embodiment, referring to Figures 4a and 4b, the edge termination region A2 includes a ring-shaped trace region A3 and a pad region A4. The ring-shaped trace region A3 surrounds the periphery of the active region A1. The pad region A4 is connected to the ring-shaped trace region A3 and is located on one side of the active region A1. The cross-sectional area of ​​the pad region A4 is larger than the cross-sectional area of ​​the ring-shaped trace region A3 located on each side of the active region A1; the capacitor electrode layer 33 is located in the pad region A4. Thus, a larger area capacitor electrode layer 33 can be provided in the edge termination region A2, allowing a larger area gate pad 52 to be positioned opposite the capacitor electrode layer 33, thereby further increasing the gate-source capacitance value.

[0091] In some embodiments, the pad area A4 is located inside the annular trace area A3; that is, it is located on the side of the annular trace area A3 near the active area A1.

[0092] In one specific embodiment, the edge terminal area A2 includes a ring-shaped trace area A3 surrounding the active area A1 and a pad area A4 connected to the ring-shaped trace area A3. The ring-shaped trace area A3 includes a first edge area and a second edge area disposed opposite each other along a first direction Y, and a third edge area and a fourth edge area disposed opposite each other along a second direction X. The first edge area to the fourth edge area form a closed loop structure, and the active area A1 is located within this closed loop structure. The aforementioned pad area A4 is specifically connected to the first edge area and is located on the side of the first edge area facing the second edge area, and is located between the active area A1 and the first edge area. A portion of the source area 13 extends from the third edge area to the fourth edge area.

[0093] In one embodiment, the pad area A4 extends along the first direction Y, and the active area A1 extends to the opposite sides of the pad area A4 along the second direction X; that is, a portion of the active area A1 is located on both sides of the pad area A4 along the second direction X, thus maximizing the area of ​​the active area A1 within a limited area. The first direction Y is perpendicular to the second direction X.

[0094] In another embodiment, referring to Figures 8 and 9, the difference from the embodiment corresponding to Figure 4b is that the gate bus layer 32 includes a ring-shaped trace layer located in the ring-shaped trace region A3 and a pad layer located in the pad region A4; the capacitor plate layer 33 is located in the second edge region and inside the ring-shaped trace layer. This facilitates making the capacitor plate layer 33 longer along the second direction X. Specifically, the portion of the ring-shaped trace layer located in the second edge region surrounds the entire capacitor plate layer 33 and is spaced apart from it.

[0095] Of course, in other embodiments, the capacitor plate layer 33 can also be disposed in the third edge region and the fourth edge region, as long as it is insulated from the various layer structures and the annular trace layer disposed in the active region A1.

[0096] In some embodiments, referring to FIG10, the semiconductor device further includes a plurality of well regions 12, a plurality of well region contact regions 2, a gate insulating layer 7a, a wiring insulating layer 7b, a passivation layer 7c, and a drain electrode 18.

[0097] A plurality of well regions 12 and a plurality of well region contact regions 2 are disposed within the semiconductor epitaxial wafer 1. The plurality of well regions 12, the plurality of well region contact regions 2 and the plurality of source regions 13 are correspondingly disposed. The well regions 12, the well region contact regions 2 and the source regions 13 all extend along the surface of the semiconductor epitaxial wafer 1 within the semiconductor epitaxial wafer 1.

[0098] A gate insulating layer 7a is disposed at least in the active region A1; a gate electrode layer 31 is disposed on the side of the gate insulating layer 7a away from the semiconductor epitaxial wafer 1, so as to isolate the gate electrode layer 31 from the semiconductor epitaxial wafer 1, the well region 12, the well region contact region 2 and / or the source region 13 through the gate insulating layer 7a. In one embodiment, a portion of the gate insulating layer 7a further extends to the edge termination region A2 to connect with the wiring insulating layer 7b.

[0099] A wiring insulating layer 7b is disposed on the semiconductor epitaxial wafer 1 and located in the edge termination region A2; a gate bus layer 32 is disposed on the side surface of the wiring insulating layer 7b away from the semiconductor epitaxial wafer 1. The wiring insulating layer 7b isolates the gate bus layer 32 from the semiconductor epitaxial wafer 1 and the termination structure 11.

[0100] The materials of the gate insulating layer 7a and the wiring insulating layer 7b can be silicon oxide or silicon nitride, etc., which are not limited here, as long as they can achieve dielectric isolation between the first conductive layer 3 and the semiconductor epitaxial wafer 1.

[0101] In some embodiments, the thickness of the wiring insulating layer 7b is greater than the thickness of the gate insulating layer 7a. Here, thickness refers to the dimension along the direction from the semiconductor epitaxial wafer 1 toward the gate insulating layer 7a.

[0102] The semiconductor device can be a planar gate semiconductor device or a trench gate semiconductor device. When the semiconductor device is a planar gate semiconductor device, referring to Figure 10, a gate insulating layer 7a is disposed on the surface of the semiconductor epitaxial wafer 1, and a gate electrode layer 31 is disposed on the surface of the gate insulating layer 7a away from the semiconductor epitaxial wafer 1. The gate insulating layer 7a is used to isolate the gate electrode layer 31 from the semiconductor epitaxial wafer 1. When the gate insulating layer 7a and the gate electrode layer 31 also extend onto the well region 12 and at least part of the source region 13, the gate insulating layer 7a is also used to isolate the gate electrode layer 31 from the semiconductor epitaxial wafer 1, the well region 12, and the source region 13. When the semiconductor device is a trench gate semiconductor device (not shown in the figure), the gate structure 31a extends along the surface of the semiconductor epitaxial wafer 1 and into the semiconductor epitaxial wafer 1, and the gate insulating layer 7a wraps around the gate electrode layer 31 to isolate the gate electrode layer 31 from the semiconductor epitaxial wafer 1, the well region 12, the well region contact region 2, and the source region 13.

[0103] The passivation layer 7c covers the second conductive layer 5. Specifically, the passivation layer 7c covers the source pad 51 to isolate the source pad 51, and the area of ​​the passivation layer 7c corresponding to the source pad 51 has a fifth opening 71 so that a portion of the source pad 51 is exposed through the fifth opening 71. The passivation layer 7c also covers the gate pad 52 to isolate the gate pad 52, and the area of ​​the passivation layer 7c corresponding to the gate pad 52 has a sixth opening 72 so that a portion of the gate pad 52 is exposed through the sixth opening 72.

[0104] The drain electrode 18 is disposed on the surface of the semiconductor epitaxial wafer 1 away from the source region 13. The material of the drain electrode 18 may be the same as or similar to the material of the gate pad 52 and / or the source pad 51.

[0105] The semiconductor device provided in this embodiment includes a capacitor plate layer 33 in the first conductive layer 3, and the gate electrode layer 31 and the gate bus layer 32 are both insulated from the capacitor plate layer 33. The source pad 51 is electrically connected to the capacitor plate layer 33. A portion of the gate pad 52 is stacked with a portion of the capacitor plate layer 33 and isolated by the dielectric layer 6. This forms an additional gate-source capacitance by the gate pad 52 covering a portion of the capacitor plate layer 33, the dielectric layer 6, and the portion of the capacitor plate layer 33 and the gate pad 52 stacked together. This increases the Ciss / Crss ratio, provides a wider adjustment range, and improves the semiconductor device's crosstalk immunity. Simultaneously, it does not affect the active region A1 or the reliability of the semiconductor device.

[0106] Referring to Figures 11 and 12, in a semiconductor device according to some embodiments, the first conductive layer 3 does not include the capacitor plate layer 33; a portion of the gate bus layer 32 is stacked with a portion of the source pad 51 and isolated by the dielectric layer 6.

[0107] In this embodiment, a portion of the gate bus layer 32 is exposed through the first opening 41. A dielectric layer 6 is disposed within the first opening 41 and covers the portion of the gate bus layer 32 exposed through the first opening 41. A portion of the source pad 51 extends into the first opening 41 and is located on the surface of the dielectric layer 6 away from the first exposed portion. The portion of the gate bus layer 32 covered by the dielectric layer 6, the dielectric layer 6 itself, and the portion of the source pad 51 covered by the dielectric layer 6 together form an additional gate-source capacitance (Cgs), thereby increasing Ciss / Crss and reducing the risk of crosstalk in the semiconductor device.

[0108] In the above scheme, the first conductive layer 3 does not need to separate the capacitor plate layer 33, and a portion of the area of ​​the gate bus layer 32 can be sacrificed to prepare Cgs.

[0109] Referring to Figure 13, in a semiconductor device according to some embodiments, the first conductive layer 3 does not include the capacitor plate layer 33; a portion of the gate electrode layer 31 is stacked with a portion of the source pad 51 and isolated by the dielectric layer 6.

[0110] Specifically, a seventh opening is formed on the interlayer dielectric layer 4, exposing the portion of the gate electrode layer 31 away from the semiconductor epitaxial wafer 1 to form a third exposed portion; the dielectric layer 6 is disposed within the seventh opening and covers the third exposed portion. A portion of the source pad 51 extends into the seventh opening and is located on the surface of the dielectric layer 6 away from the first exposed portion; so that the third exposed portion, the dielectric layer 6, and the portion of the source pad 51 covering the dielectric layer 6 together form an additional gate-source capacitance (C). gs This increases Ciss / Crss, thereby reducing the risk of crosstalk in semiconductor devices.

[0111] The dielectric layer 6 can be obtained by oxidizing the surface of the gate electrode layer 31.

[0112] In this scheme, the first conductive layer 3 also does not need to separate the capacitor plate layer 33, and a portion of the area of ​​the gate electrode layer 31 can be sacrificed to prepare Cgs.

[0113] Referring to Figures 14 and 15, in a semiconductor device according to some embodiments: the first conductive layer 3 does not include the capacitor electrode layer 33; a portion of the source pad 51 is stacked with a portion of the gate pad 52 and isolated by the dielectric layer 6, thereby forming a capacitor Cgs. That is, the portion of the source pad 51 and the gate pad 52 stacked together cooperates with the dielectric layer 6 to form the capacitor Cgs.

[0114] In one embodiment, as shown in FIG14, the dielectric layer 6 is located in the edge terminal region A2 and on the portion of the gate pad 52 away from the semiconductor epitaxial wafer 1; a portion of the source pad 51 extends to the surface of the dielectric layer 6 away from the semiconductor epitaxial wafer 1 to be stacked with a portion of the gate pad 52.

[0115] In another embodiment, as shown in FIG15, the dielectric layer 6 is located in the active region A1 and on the surface of the source pad 51 away from the semiconductor epitaxial wafer 1; a portion of the gate pad 52 extends to the surface of the dielectric layer 6 away from the semiconductor epitaxial wafer 1 to be stacked with a portion of the gate pad 52.

[0116] Referring to Figure 16, a method for fabricating a semiconductor device according to some embodiments is described. This method can be used to fabricate a first type of semiconductor device, and the fabrication methods for other semiconductor devices are similar. The method includes:

[0117] Step S1: Provide a semiconductor epitaxial wafer 1, wherein the semiconductor epitaxial wafer 1 includes an active region A1 and an edge termination region A2.

[0118] In some embodiments, the semiconductor epitaxial wafer 1 includes a substrate (not shown) and a semiconductor epitaxial layer (not shown) stacked together. In some embodiments, the substrate is a SiC substrate with a crystal form of 4H SiC, and the SiC epitaxial layer is grown on the SiC substrate using a vapor deposition process.

[0119] Step S2: Form several well regions 12, several well region contact regions 2 and several source regions 13 in the active region A1.

[0120] Referring to Figure 17, ion implantation can be performed on the active region A1 of the semiconductor epitaxial wafer 1 to form a plurality of well regions 12, a plurality of well contact regions 2, and a plurality of source regions 13. The plurality of well regions 12, well contact regions 2, and source regions 13 all extend along the surface of the semiconductor epitaxial wafer 1 and within the semiconductor epitaxial wafer 1; and the plurality of well regions 12, well contact regions 2, and source regions 13 extend from the active region A1 to the edge of the active region A1. The plurality of well regions 12 are spaced apart, and each well region 12 contains an adjacent well contact region 2 and a source region 13.

[0121] Please refer to Figure 17. In step S2, a terminal structure 11 is also formed simultaneously in the edge terminal area A2 to protect the device from damage such as overvoltage or overcurrent.

[0122] Step S3: High-temperature activation of semiconductor epitaxial wafer 1, and formation of wiring insulation layer 7b in the region of edge termination area A2 on the first surface of semiconductor epitaxial wafer 1.

[0123] Specifically, a dielectric material layer can be grown by thermo-oxidative growth, followed by oxidation and annealing at temperatures ranging from 1200℃ to 1450℃, with oxidation times of 10 min to 30 min and annealing times of 30 min to 300 min. Finally, the layer is patterned to form a trace insulation layer 7b located in the edge terminal region A2.

[0124] Referring to Figures 18 and 19, the wiring insulation layer 7b surrounds the active area A1.

[0125] Step S4: A first conductive layer 3 is formed on the first surface of the semiconductor epitaxial wafer 1; the first conductive layer 3 includes a capacitor plate layer 33, and a gate electrode layer 31 and a gate bus layer 32 that are electrically connected to each other; the gate electrode layer 31 is disposed in the active region A1, and the gate bus layer 32 is disposed in the edge terminal region A2; the gate electrode layer 31 and the gate bus layer 32 are both insulated from the capacitor plate layer 33.

[0126] Referring to Figure 9, in the specific implementation process, before step S4, a gate insulating layer 7a is formed on the surface of the semiconductor device. The gate insulating layer 7a can be formed using the same process as the wiring insulating layer 7b; however, because their thicknesses are different, the wiring insulating layer 7b and the gate insulating layer 7a are not formed in the same step, and there is no specific order between them.

[0127] The gate electrode layer 31 is formed on the side surface of the gate insulating layer 7a away from the semiconductor epitaxial wafer 1; the gate bus layer 32 and the capacitor plate layer 33 are formed on the side surface of the wiring insulating layer 7b away from the semiconductor epitaxial wafer 1.

[0128] In the specific implementation process, the gate electrode layer 31, the gate bus layer 32, and the capacitor plate layer 33 can be formed in the same step by magnetron sputtering or vapor deposition. Specifically, a gate material can be formed on the entire surface of the semiconductor epitaxial wafer 1 on which the wiring insulating layer 7b and the gate insulating layer 7a are formed. The gate material can be polysilicon or a conductive metal material. Then, the gate material is patterned to form several layers disposed on the gate electrode layer 31, the gate bus layer 32, and the capacitor plate layer 33.

[0129] Step S5: Form an interlayer dielectric layer 4 on the first conductive layer 3, and expose at least a portion of the interlayer dielectric layer 4 to the capacitor electrode layer 33.

[0130] Referring to Figures 20 and 21, in some embodiments, the interlayer dielectric layer 4 is formed by magnetron sputtering or vapor deposition, and the material of the interlayer dielectric layer 4 can be silicon oxide or silicon nitride, etc.

[0131] The interlayer dielectric layer 4 has a first opening 41, which exposes part of the capacitor plate layer 33 and forms a conversion part.

[0132] Step S6: Oxidize the portion of the capacitor plate layer 33 that exposes the interlayer dielectric layer 4 to form the dielectric layer 6.

[0133] Referring to Figures 22 and 23, a high-quality thermally oxidized silicon dielectric layer 6 can be obtained using a mature silicon oxidation process. In a specific implementation, the part to be converted is oxidized so that the portion of the part to be converted that is away from the semiconductor epitaxial wafer 1 is oxidized to form the dielectric layer 6, while the unoxidized portion of the part to be converted is retained as the capacitor electrode layer 33 or still exists as the capacitor electrode layer 33.

[0134] Step S7: The interlayer dielectric layer 4 is patterned to expose at least a portion of the source region 13 and at least a portion of the gate bus layer 32. Referring to FIG5, the interlayer dielectric layer 4 has a third opening 43 and a fourth opening 44; the third opening 43 is located in the active region A1, exposing at least a portion of the source region 13; the fourth opening 44 is located in the edge termination region A2, exposing at least a portion of the gate bus layer 32; and the dielectric layer 6 or the interlayer dielectric layer 4 is patterned to expose a portion of the first exposed portion. In some implementations, as shown in FIG5, an opening 61 can be formed on the dielectric layer 6 to expose a portion of the first exposed portion, and the subsequently formed source pad 51 can be electrically connected to the electrode plate layer through the opening 61. Of course, as shown in FIG6a, a second opening 42 can also be formed on the interlayer dielectric layer 4 to expose a second exposed portion, so that the source pad 51 contacts the second exposed portion through the second opening 42.

[0135] In some specific implementations, ohmic contact metal can be formed within each third opening 43. This ohmic contact metal can be formed within the third opening 43 by vapor deposition, magnetron sputtering, or patterning, with an annealing process temperature ranging from 800℃ to 1100℃ and a time range from 60s to 300s.

[0136] Step S8: A second conductive layer 5 is formed on the interlayer dielectric layer 4; the second conductive layer 5 includes a source pad 51 and a gate pad 52; the source pad 51 is at least disposed in the active region A1 and electrically connected to the source region 13; the gate pad 52 is at least disposed in the edge terminal region A2 and electrically connected to the gate bus layer 32.

[0137] Referring to Figures 2 and 3, in some embodiments, a metal layer is formed on the entire surface of the interlayer dielectric layer 4 by vapor deposition or magnetron sputtering, and then the source pad 51 and the gate pad 52, which are at least partially located in the edge terminal region A2, are patterned.

[0138] The source pad 51 is disposed on the interlayer dielectric layer 4 and extends into each third opening 43 and is connected to the ohmic contact metal in each third opening 43, thereby connecting to each source region 13. The gate pad 52 is disposed on the interlayer dielectric layer 4 and extends into the fourth opening 44 and is connected to the gate bus layer 32.

[0139] Step S9: Form a passivation layer 7c covering the source pad 51 and the gate pad 52; wherein the passivation layer 7c has a fifth opening 71 in the region corresponding to the source pad 51 and a sixth opening 72 in the region corresponding to the gate pad 52.

[0140] The passivation layer 7c can be formed using the same process as the interlayer dielectric layer 4, which will not be elaborated here.

[0141] Referring to Figure 10, specifically, the passivation layer 7c is used to isolate the source pad 51 and the gate pad 52.

[0142] Step S10: A drain pad is formed on the side of the semiconductor epitaxial wafer 1 away from the source pad 51 and the gate pad 52.

[0143] In some embodiments, the surface of the substrate facing away from the source pad 51 and the gate pad 52 can be thinned first; then the drain pad can be formed. Specifically, an ohmic contact can be formed on the back side of the semiconductor epitaxial wafer 1 first, and then a full-surface metal layer can be formed on the back side of the semiconductor epitaxial wafer 1 as a drain pad by vapor deposition or magnetron sputtering.

[0144] The semiconductor device fabrication method provided in this application involves forming a capacitor plate layer 33 disposed on the same layer as the gate electrode layer 31 and the gate bus layer 32, with both the gate electrode layer 31 and the gate bus layer 32 being insulated from each other by the capacitor plate layer 33; the source pad 51 is electrically connected to the capacitor plate layer 33; a portion of the gate pad 52 is stacked with a portion of the capacitor plate layer 33 and isolated by the dielectric layer 6, so that an additional gate-source capacitance is formed by the gate pad 52 covering the portion of the capacitor plate layer 33, the dielectric layer 6, and the portion of the capacitor plate layer 33 and the gate pad 52 stacked together, thereby increasing the Ciss to Crss ratio and reducing the risk of crosstalk in the semiconductor device. Furthermore, this design only involves a change in the position of the gate pad 52 and does not affect the reliability of the active region A1 or the semiconductor device. Furthermore, by placing the gate bus layer 32 on the edge termination region A2, compared to placing the gate bus layer 32 on the active region A1 in other methods, the area of ​​the active region A1 can be saved, so that the semiconductor device is basically active region A1 except for the edge termination region A2. This can improve the device's outflow capability and reduce on-resistance. Moreover, the gate bus layer 32 is connected to the end of each gate structure 31a extending to the edge of the active region A1, and the gate bus layer 32 can drive each gate structure 31a, so as not to affect the reliability of the device.

[0145] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A semiconductor device, comprising: A semiconductor epitaxial wafer includes an active region and an edge termination region surrounding the active region; Several source regions are disposed in the active region; The first conductive layer includes a gate electrode layer and a gate bus layer that are electrically connected to each other; the gate electrode layer is disposed in the active region, and the gate bus layer is disposed in the edge terminal region; An interlayer dielectric layer covers the first conductive layer; A second conductive layer is disposed on the side of the interlayer dielectric layer away from the semiconductor epitaxial wafer; the second conductive layer includes a source pad and a gate pad; the source pad is at least disposed in the active region and electrically connected to the source region; the gate pad is at least disposed in the edge termination region and electrically connected to the gate bus layer; The first conductive layer further includes a capacitor plate layer, and the gate electrode layer and the gate bus layer are both insulated from the capacitor plate layer; the source pad is electrically connected to the capacitor plate layer; a portion of the gate pad is stacked with a portion of the capacitor plate layer and isolated by a dielectric layer, the thickness of which is less than the thickness of the interlayer dielectric layer.

2. The semiconductor device according to claim 1, wherein, The capacitor plate layer is located in the edge terminal area; The interlayer dielectric layer has a first opening, which exposes a portion of the capacitor electrode layer to form a first exposed portion; the dielectric layer is disposed within the first opening and covers the first exposed portion; a portion of the gate pad extends into the first opening and is located on the surface of the dielectric layer away from the first exposed portion.

3. The semiconductor device according to claim 2, wherein, The dielectric layer has an opening; the source pad contacts the first exposed portion in sequence through the first opening and the opening.

4. The semiconductor device of claim 3, wherein, The opening is spaced apart from the sidewall of the first opening of the interlayer dielectric layer along the first direction.

5. The semiconductor device of claim 3, wherein, The opening is located at the edge of the dielectric layer near the active region; The first opening has opposing first and second sidewalls along a first direction; along the first direction, the first distance between the opening and the first sidewall is less than the second distance between the opening and the second sidewall.

6. The semiconductor device according to claim 3, wherein, The first opening has opposing third and fourth sidewalls along the second direction; along the second direction, the opening is spaced apart from the third sidewall and the opening is spaced apart from the fourth sidewall.

7. The semiconductor device according to claim 3, wherein, The length of the opening along the second direction is greater than the length of the opening along the first direction.

8. The semiconductor device according to claim 2, wherein, The interlayer dielectric layer has a second opening spaced apart from the first opening, thereby exposing a portion of the capacitor electrode layer to form a second exposed portion; the source pad contacts the second exposed portion through the second opening.

9. The semiconductor device according to claim 2, wherein, The edge terminal area includes a ring-shaped trace area surrounding the active area and a pad area connected to the ring-shaped trace area; the capacitor electrode layer is located in the pad area.

10. The semiconductor device according to claim 9, wherein, The pad area is located inside the annular trace area, and the active area extends to the opposite sides of the pad area.

11. The semiconductor device according to claim 2, wherein, The edge terminal region includes a ring-shaped trace area surrounding the active region and a pad area connected to the ring-shaped trace area; the ring-shaped trace area includes a first edge area and a second edge area disposed opposite to each other along a first direction, and a third edge area and a fourth edge area disposed opposite to each other along a second direction; a portion of the source region extends from the third edge area to the fourth edge area; the pad area is connected to the first edge area, and the gate bus layer includes a ring-shaped trace layer located in the ring-shaped trace area and a pad layer located in the pad area; the capacitor plate layer is located in the second edge area and inside the ring-shaped trace layer.

12. The semiconductor device according to any one of claims 1-11, wherein, The first conductive layer is a doped polycrystalline silicon layer; the dielectric layer is a thermally oxidized silicon oxide layer.

13. The semiconductor device according to any one of claims 1-11, wherein, The thickness of the interlayer dielectric layer is 800-1000 nanometers; the thickness of the dielectric layer is 50-200 nanometers.

14. The semiconductor device according to any one of Claims 1-11, wherein, The semiconductor device is a SiC MOSFET, and also includes: A plurality of well regions and a plurality of well region contact regions; the plurality of well regions, the plurality of well region contact regions and the plurality of source regions are correspondingly arranged; A gate insulating layer is disposed at least in the active region; the gate electrode layer is disposed on the side of the gate insulating layer away from the semiconductor epitaxial wafer; A wiring insulating layer is disposed in the edge terminal region; the gate bus layer is disposed on the side of the wiring insulating layer away from the semiconductor epitaxial wafer; A passivation layer covers the second conductive layer; The drain electrode is disposed on the surface of the semiconductor epitaxial wafer opposite to the source region; In the active region, the interlayer dielectric layer has a third opening, exposing at least a portion of the source region and contacting the source pad; in the edge termination region, the interlayer dielectric layer has a fourth opening, exposing at least a portion of the gate bus layer and contacting the gate pad; the passivation layer has a fifth opening and a sixth opening, the fifth opening exposing a portion of the source pad and the sixth opening exposing a portion of the gate pad.

15. A semiconductor device, comprising: A semiconductor epitaxial wafer includes an active region and an edge termination region surrounding the active region; Several source regions are disposed in the active region; The first conductive layer includes a gate electrode layer and a gate bus layer that are electrically connected to each other; the gate electrode layer is disposed in the active region, and the gate bus layer is disposed in the edge terminal region; An interlayer dielectric layer covers the first conductive layer; A second conductive layer is disposed on the side of the interlayer dielectric layer away from the semiconductor epitaxial wafer; the second conductive layer includes a source pad and a gate pad; the source pad is at least disposed in the active region and electrically connected to the source region; the gate pad is at least disposed in the edge termination region and electrically connected to the gate bus layer; Wherein, a portion of the gate electrode layer or a portion of the gate bus layer is stacked with a portion of the source pad and isolated by a dielectric layer, and the thickness of the dielectric layer is less than the thickness of the interlayer dielectric layer; The interlayer dielectric layer has a first opening, such that a portion of the gate electrode layer or a portion of the gate bus layer is exposed to form a first exposed portion; the dielectric layer is disposed within the first opening and covers the first exposed portion; a portion of the source pad extends into the first opening and is located on the surface of the dielectric layer away from the first exposed portion.

16. The semiconductor device according to claim 15, wherein, The first conductive layer is a doped polycrystalline silicon layer; the dielectric layer is a thermally oxidized silicon oxide layer.

17. The semiconductor device according to claim 15, wherein, The thickness of the interlayer dielectric layer is 800-1000 nanometers; the thickness of the dielectric layer is 50-200 nanometers.

18. The semiconductor device of claim 15, wherein, The semiconductor device is a SiC MOSFET, and also includes: A plurality of well regions and a plurality of well region contact regions; the plurality of well regions, the plurality of well region contact regions and the plurality of source regions are correspondingly arranged; A gate insulating layer is disposed in the active region; the gate electrode layer is disposed on the side of the gate insulating layer away from the semiconductor epitaxial wafer; A wiring insulating layer is disposed in the edge terminal region; the gate bus layer is disposed on the side of the wiring insulating layer away from the semiconductor epitaxial wafer; A passivation layer covers the second conductive layer; The drain electrode is disposed on the surface of the semiconductor epitaxial wafer opposite to the source region; In the active region, the interlayer dielectric layer, the gate electrode layer, and the gate insulating layer have a third opening, exposing the source region and contacting the source pad; in the edge termination region, the interlayer dielectric layer has a fourth opening, exposing the gate bus layer and contacting the gate pad; the passivation layer has a fifth opening and a sixth opening, the fifth opening exposing a portion of the source pad and the sixth opening exposing a portion of the gate pad.

19. A semiconductor device, comprising: A semiconductor epitaxial wafer includes an active region and an edge termination region surrounding the active region; Several source regions are disposed in the active region; The first conductive layer includes a gate electrode layer and a gate bus layer that are electrically connected to each other; the gate electrode layer is disposed in the active region, and the gate bus layer is disposed in the edge terminal region; An interlayer dielectric layer covers the first conductive layer; A second conductive layer is disposed on the side of the interlayer dielectric layer away from the semiconductor epitaxial wafer; the second conductive layer includes a source pad and a gate pad; the source pad is at least disposed in the active region and electrically connected to the source region; the gate pad is at least disposed in the edge termination region and electrically connected to the gate bus layer; The source pad is stacked with a portion of the gate pad and isolated by a dielectric layer to form a gate-source capacitor. The thickness of the dielectric layer is less than the thickness of the interlayer dielectric layer.

20. The semiconductor device according to claim 19, wherein, The dielectric layer is located in the edge termination region and on a portion of the surface of the gate pad away from the semiconductor epitaxial wafer; a portion of the source pad extends to the surface of the dielectric layer away from the semiconductor epitaxial wafer; or The dielectric layer is located in the active region and on a portion of the surface of the source pad away from the semiconductor epitaxial wafer; a portion of the gate pad extends to the surface of the dielectric layer away from the semiconductor epitaxial wafer.

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