Communication delay measurement device and communication delay measurement method

Abstract

This communication delay measurement device comprises: a first clock that generates a first clock signal with a first period; a second clock that generates a second clock signal with a second period different from the first period; and a communication delay measurement unit that measures a communication delay with a time resolution shorter than the first period on the basis of the first clock signal generated by the first clock and the second clock signal generated by the second clock.

Description

Communication delay measurement device and communication delay measurement method

[0001] The present invention relates to a communication delay measurement device and a communication delay measurement method.

[0002] Regarding the ITU-T (International Telecommunication Union) recommendation G. 709, the technology described in Non-Patent Document 1 is known. In the OTN (Optical Transport Network) described in G. 709, a method is used to measure communication delay using DMOH (Delay Measurement Overhead).

[0003] Recommendation ITU-T G.709 / Y.1331 (2020) Amd.3 (03 / 2024)

[0004] However, in the method described in G. 709, the measurement resolution of the communication delay depends on the frame period. In the method described in G. 709, processing is performed using an asynchronous clock within each communication device, making it difficult to measure the communication delay with a resolution finer than one clock cycle.

[0005] The present invention aims to provide a technology that can measure communication delay with a resolution finer than one clock cycle.

[0006] One aspect of the present invention is a communication delay measuring device comprising: a first clock that generates a first clock signal in a first cycle; a second clock that generates a second clock signal in a second cycle different from the first cycle; and a communication delay measuring unit that measures the communication delay with a time resolution shorter than the first cycle based on the first clock signal generated by the first clock and the second clock signal generated by the second clock.

[0007] Another aspect of the present invention is a communication delay measurement method in which a first clock generates a first clock signal in a first period using a first clock, and a second clock generates a second clock signal in a second period different from the first period using a second clock, and the communication delay is measured with a time resolution shorter than the first period based on the first clock signal generated by the first clock and the second clock signal generated by the second clock.

[0008] According to the present invention, communication delay can be measured with a resolution finer than one clock cycle.

[0009] This figure shows the principle of measuring communication delay according to the first embodiment of the present invention. This is a schematic block diagram showing the configuration of a communication delay measuring device according to the first embodiment of the present invention. This figure shows an example of a signal processed by a communication delay measuring device according to the first embodiment of the present invention. This is a schematic block diagram showing the configuration of a communication delay measuring device according to a modification of the first embodiment of the present invention. This figure shows an example of a signal processed by a communication delay measuring device according to a modification of the first embodiment of the present invention. This is a schematic diagram showing the configuration of a communication delay measuring system according to the second embodiment of the present invention. This is a schematic block diagram showing the configuration of the delay measurement unit of the first communication device according to the second embodiment of the present invention. This figure illustrates the correction processing by the correction value estimation processing unit of the first communication device according to the second embodiment of the present invention. This figure illustrates the synthesis processing by the correction value synthesis unit of the first communication device according to the second embodiment of the present invention. This is a schematic block diagram showing the configuration of the delay measurement unit according to a modification of the second embodiment of the present invention. This figure illustrates the synthesis processing by the correction value synthesis unit according to a modification of the second embodiment of the present invention. This is a schematic diagram showing the configuration of a communication delay measuring system according to the third embodiment of the present invention.

[0010] Hereinafter, several embodiments of the present invention will be described with reference to the drawings. First, a first embodiment of the present invention will be described.

[0011] [First Embodiment] First, the first embodiment of the present invention will be described. FIG. 1 is a diagram showing the measurement principle of communication delay according to the first embodiment of the present invention. In the first embodiment of the present invention, as shown in FIG. 1, signals of a measurement trigger, a secondary scale CLK (clock), and a primary scale CLK are used. The time of the measurement trigger is measured by the primary scale CLK, which is a clock asynchronous with the measurement trigger. A reception CLK synchronized with the measurement trigger is used as the secondary scale CLK.

[0012] In FIG. 1, let the period of the primary scale CLK be T Ｍ And in FIG. 1, let the period of the secondary scale CLK be T Ｖ Hereinafter, although it will be described assuming T Ｍ > T Ｖ the same applies when T Ｍ < T Ｖ Let the quantization error of the primary scale CLK be Δt Ｅ In FIG. 1, let the rising time of the primary scale CLK be t Ｍｎ (n is an integer of 0 or more). In FIG. 1, let the rising time of the secondary scale CLK be t Ｖｎ (n is an integer of 0 or more).

[0013] In this case, the rising time t Ｍｎ of the primary scale CLK is represented by the following formula (1). However, n = 0 means immediately before the rising of the measurement trigger.

[0014] t Ｍｎ = n × T Ｍ ... (1)

[0015] Also, the rising time t Ｖｎ of the secondary scale CLK is represented by the following formula (2). However, n = 0 means the rising point of the measurement trigger.

[0016] t Ｖｎ = ΔT Ｅ + n × T Ｖ ... (2)

[0017] The time difference Δt ｎ between the edges of the primary scale CLK and the secondary scale CLK is represented by the following formula (3).

[0018] Δt ｎ = Δt Ｅ+n×T Ｖ -n×T Ｍ =Δt Ｅ -n×(T Ｍ -T Ｖ ) ··· (3)

[0019] However, in the above formula (3), when Δt ｎ >0, it indicates that the phase of the main scale CLK is advancing. Also, in the above formula (3), when Δt ｎ <0, it indicates that the phase of the sub-scale CLK is advancing.

[0020] Here, when n = i, considering i for which Δt ｉ－１ ≧0 and Δt ｉ <0, the following formula (4) holds.

[0021] (i - 1)×(T Ｍ -T Ｖ )≦Δt Ｅ <i×(T Ｍ -T Ｖ ) ··· (4)

[0022] Therefore, Δt Ｅ can be measured as the resolution (T Ｍ -T Ｖ ). That is, for delay measurement, at the main scale clock and the sub-scale clock, the point where the progress of the phase of the clock edge reverses can be detected and regarded as the matching point. Note that it is not limited to the case where the point where the progress of the phase of the clock edge reverses at the main scale clock and the sub-scale clock is regarded as the matching point, and the matching point may be obtained by other methods.

[0023] Figure 2 is a schematic block diagram showing the configuration of the communication delay measurement device 100a according to the first embodiment of the present invention. Figure 2 is a diagram showing the signals processed by the communication delay measurement device 100a. Although not shown in Figure 1, the communication delay measurement device 100a includes a CPU (Central Processing Unit) that controls each part of the communication delay measurement device 100a and a memory that stores the data processed by the communication delay measurement device 100a.

[0024] The communication delay measuring device 100a comprises a main scale CLK 10a, a main scale counter 11a (also referred to as the first counter), a sub-scale CLK 12a, a sub-scale counter 13a (also referred to as the second counter), a comparator 14a, and an error estimation processing unit 15a. The main scale CLK 10a is connected to the main scale counter 11a. The main scale CLK 10a has a predetermined period (for example, period T shown in Figure 1). Ｍ The clock signal of ) is output to the main scale counter 11a.

[0025] The main scale counter 11a is connected to the main scale CLK 10a and the comparator 14a. When a measurement trigger signal is input to the communication delay measuring device 100a (see Figure 3(A)), the main scale counter 11a starts counting the number of times the rising edge of the main scale CLK 10a occurs (see Figure 3(C)).

[0026] The vernier scale CLK12a is connected to the vernier counter 13a. The vernier scale CLK13a has a predetermined period (for example, period T shown in Figure 1). Ｖ The clock signal of the ) is output to the vernier counter 12a. The vernier counter 13a is connected to the vernier scale CLK 12a and the comparator 14a. When a measurement trigger signal is input to the communication delay measuring device 100a (see Figure 3(A)), the vernier counter 13a starts counting the number of times the rising edge of the vernier scale CLK 12a occurs (see Figure 3(B)).

[0027] The comparator 14a is connected to the main scale counter 11a, the vernier scale counter 13a, and the error estimation processing unit 15a. The comparator 14a compares the magnitude of the count output by the main scale counter 11a and the count output by the vernier scale counter 13a, and outputs the information from the vernier scale counter 13a when the count output by the vernier scale counter 13a is greater than the count output by the main scale counter 11a, as matching point information to the error estimation processing unit 15a. Ｍ <T Ｖ In this case, the information from the vernier counter 13a when the count output by the vernier counter 13a becomes smaller than the count output by the main scale counter 11a is used as the matching point information. For example, in Figure 3, the information for matching point i = 3 is used as the matching point information.

[0028] The error estimation processing unit 15a is connected to the comparator 14a. Based on the matching point information output from the comparator 14a, the error estimation processing unit 15a estimates the error using the following equation (5).

[0029] (i-1) × (T) Ｍ -T Ｖ ) ≤ Δt Ｅ <i x (T Ｍ -T Ｖ ) ... (5)

[0030] In the first embodiment, the main scale CLK10a (also referred to as the first clock) has a first period (period T Ｍ The first clock signal is generated at ). Then, the vernier scale CLK12a (also called the second clock) is set to a second period (period T) which is different from the first period. Ｖ A second clock signal is generated at ) . Then, the error estimation processing unit 15a (also called the communication delay measurement unit) calculates a resolution (Δt) shorter than the first period based on the first clock signal generated by the main scale CLK 10a and the second clock signal generated by the subscale CLK 12a. Ｅ ) The communication delay is measured. In this way, in the first embodiment, the communication delay measuring device 100a measures the error Δt with a resolution finer than one clock cycle of the main scale CLK 10a. Ｅ It is possible to estimate this.

[0031] [Modifications of the First Embodiment] Next, modifications of the first embodiment of the present invention will be described. Figure 4 is a schematic block diagram showing the configuration of a communication delay measuring device 100b according to a modification of the first embodiment of the present invention. Figure 5 is a diagram showing an example of a signal processed by the communication delay measuring device 100b. Although not shown in Figure 4, the communication delay measuring device 100b includes a CPU that controls each part of the communication delay measuring device 100b and a memory that stores the data processed by the communication delay measuring device 100b.

[0032] The communication delay measuring device 100b comprises a main scale CLK 10b, a sub-scale CLK 12b, a sub-scale counter 13b, an error estimation processing unit 15b, and a matching point search counter 16b. The main scale CLK 10b is connected to the matching point search counter 16b. The main scale CLK 10b has a predetermined period (for example, period T shown in Figure 1). ＭThe clock signal of ) is output to the main scale counter 11b (see Figure 5(E)).

[0033] The vernier scale CLK12b is connected to the vernier counter 13b and the matching point search counter 16b. The vernier scale CLK13b has a predetermined period (for example, period T shown in Figure 1). Ｖ The clock signal from the above is output to the vernier counter 13b and the matching point search counter 16b.

[0034] The matching point search counter 16b is connected to the main scale CLK 10b, the vernier scale CLK 12b, and the vernier scale counter 13b. The matching point search counter 16b resets on the rising edge of the clock signal output from the main scale CLK 10b and increments on the rising edge of the clock signal output from the vernier scale CLK 12b (see Figure 5(D)). When the count value of the matching point search counter 16b becomes 2, it generates a matching point detection signal (see Figure 5(C)) and outputs it to the vernier scale counter 13b.

[0035] The vernier counter 13b is connected to the vernier scale CLK 12b and the match point search counter 16b. When a measurement trigger signal is input to the communication delay measuring device 100b (see Figure 5(A)), the vernier counter 13b starts counting the number of times the rising edge of the vernier scale CLK 12b occurs (see Figure 5(B)). Also, when a match point detection signal is output from the match point search counter 16b, the vernier counter 13b takes the count value of the vernier counter 13b as the match point and outputs it as match point information to the error estimation processing unit 15b. For example, in Figure 5, the information for the match point i=3 becomes the match point information.

[0036] The error estimation processing unit 15b is connected to the vernier counter 13b. Based on the matching point information output from the vernier counter 13b, the error estimation processing unit 15b estimates the error using the above-described equation (5).

[0037] In the modified version of the first embodiment, as in the first embodiment described above, the communication delay measuring device 100b can estimate the error ΔtE with a resolution finer than one clock cycle of the main scale CLK 10b.

[0038] [Second Embodiment] Next, a second embodiment of the present invention will be described. Figure 6 is a schematic diagram showing the configuration of a communication delay measurement system 1000c according to the second embodiment of the present invention. The communication delay measurement system 1000c comprises a first communication device 100c (also referred to as a communication delay measurement device) and a second communication device 200c.

[0039] The second embodiment is applicable when measuring communication delay between two devices whose clocks are in a dependent synchronization relationship, such as when using SyncE (Synchronous Ethernet), a standard for adding synchronization functionality to asynchronous Ethernet.

[0040] The first communication device 100c includes a main scale CLK 10c, a signal generation unit 17c, a DM (Delay Measurement) information insertion unit 18c, a transmission unit 19c, a transmission CLK 20c, a received signal processing unit 21c, a DM information detection unit 22c, a receiving unit 23c, a received CLK 24c, and a delay measurement unit 25c (also referred to as a communication delay measurement unit). Although not shown in Figure 6, the first communication device 100c includes a CPU that controls each part of the first communication device 100c and a memory that stores the data processed by the first communication device 100c.

[0041] The signal generation unit 17c is connected to the DM information measurement unit 25c. The signal generation unit 17c generates a data signal to be transmitted from the first communication device 100c to the second communication device 200c and outputs it to the DM information insertion unit 18c.

[0042] The DM information insertion unit 18c is connected to the signal generation unit 17c, the transmission unit 19c, and the delay measurement unit 25c. The DM information insertion unit 18c inserts DM (Delay Measurement) information into the data signal output from the signal generation unit 17c and outputs it to the transmission unit 19c. Subsequently, the DM information insertion unit 18c outputs a notification of DM transmission completion to the delay measurement unit 25c.

[0043] The transmitting CLK 20c is connected to the transmitting unit 19c. The transmitting CLK 20c outputs a clock signal of a predetermined period to the transmitting unit 19c. The transmitting unit 19c is connected to the DM information insertion unit 18c. The transmitting unit 19c transmits the signal output from the DM information insertion unit 18c to the second communication device 200c based on the clock signal output from the transmitting CLK 20c.

[0044] The receiving unit 23c is connected to the DM information detection unit 22c and the receiving CLK 24c. The receiving unit 23c receives a signal from the second communication device 200c and outputs it to the DM information detection unit 22c. The receiving unit 23c also causes the receiving CLK 24c to regenerate a clock based on the signal received from the second communication device 200c.

[0045] The receiving CLK 24c is connected to the receiving unit 23c. The receiving CLK 24c regenerates the clock based on the signal output from the receiving unit 23c. The DM information detection unit 22c is connected to the received signal processing unit 21c, the receiving unit 23c, and the delay measurement unit 25c. The DM information detection unit 22c detects DM from the received signal output from the received signal processing unit 21c and outputs a DM detection notification to the delay measurement unit 25c. The DM information detection unit 22c also detects frame phase information and received clock information from the received signal output from the received signal processing unit 21c and outputs them to the delay measurement unit 25c.

[0046] The received signal processing unit 21c is connected to the DM information detection unit 22c. The received signal processing unit 21c performs reception processing on the signal output from the DM information detection unit 22c. The main scale CLK 10c is connected to the delay measurement unit 25c. The main scale CLK 10c has a predetermined period (for example, the period T shown in Figure 1). Ｍ The clock signal of the ) is output to the delay measurement unit 25c. The delay measurement unit 25c is connected to the main scale CLK 10c, the DM information insertion unit 18c, and the DM information detection unit 22c. Details of the delay measurement unit 25c will be described later in the explanation of Figure 7.

[0047] The second communication device 200c includes a receiving unit 50c, a DM information detection unit 51c, a received signal processing unit 52c, a transmitting unit 54c, a DM information insertion unit 55c, and a signal generation unit 56c. Although not shown in Figure 6, the second communication device 200c includes a CPU that controls each part of the second communication device 200c and a memory that stores the data processed by the second communication device 200c.

[0048] The receiving unit 50c is connected to the DM information detection unit 51c and the receiving CLK 53c. The receiving unit 50c receives a signal from the first communication device 100c and outputs it to the DM information detection unit 51c. The receiving unit 50c also causes the receiving CLK 53c to regenerate a clock based on the received signal received from the first communication device 100c.

[0049] The DM information detection unit 51c is connected to the receiving unit 50c, the received signal processing unit 52c, and the DM information insertion unit 55c. The DM information detection unit 51c detects DM information from the signal output from the receiving unit 50c and outputs it to the DM information insertion unit 55c as DM control information. The DM information detection unit 51c outputs the signal after detecting the DM information to the received signal processing unit 52c.

[0050] The received signal processing unit 52c is connected to the DM information detection unit 51c. The received signal processing unit 52c performs reception processing on the signal output from the DM information detection unit 51c. The signal generation unit 56c is connected to the DM information insertion unit 55c. The signal generation unit 56c generates a data signal to be transmitted from the second communication device 200c to the first communication device 100c and outputs it to the DM information insertion unit 55c.

[0051] The DM information insertion unit 55c is connected to the DM information detection unit 51c, the transmission unit 54c, and the signal generation unit 56c. The DM information insertion unit 55c inserts DM (Delay Measurement) information into the data signal output from the signal generation unit 56c and outputs it to the transmission unit 54c. The receiving CLK 53c is connected to the receiving unit 50c and the transmission unit 54c. Based on the clock regeneration instruction output from the receiving unit 50c, the receiving CLK 53c regenerates the clock and outputs it to the transmission unit 54c.

[0052] The transmitting unit 54c is connected to the receiving CLK 53c and the DM information insertion unit 55c. Based on the clock signal output from the receiving CLK 53c, the transmitting unit 54c transmits the signal output from the DM information insertion unit 55c to the first communication device 100c.

[0053] In the second communication device 200c, the receiving CLK 53c is used to generate the transmission signal. Therefore, in the second communication device 200c, there is no uncertainty of less than one clock cycle. In the first communication device 100c, the transmitting CLK 20c and the receiving CLK 24c are frequency synchronized, but their phases are not synchronized. Therefore, a main scale CLK 10c is provided independently of each, and the errors in DM information insertion during transmission processing and DM detection during reception processing are measured, respectively.

[0054] Figure 7 is a schematic block diagram showing the configuration of the delay measurement unit 25c of the first communication device 100c according to a second embodiment of the present invention. The delay measurement unit 25c comprises a matching point detection unit 251c1, a correction value estimation processing unit 252c1, a matching point detection unit 253c1, a correction value estimation processing unit 254c1, a correction value synthesis unit 255c1, and a raw counter unit 256c1.

[0055] The matching point detection unit 251c1 is connected to the correction value estimation processing unit 252c1. The matching point detection unit 251c1 receives a clock signal from the main scale CLK 10c, a clock signal from the transmission CLK 20c, and a DM transmission completion notification from the DM information insertion unit 18c. Based on this information, the matching point detection unit 251c1 generates matching point information and outputs it to the correction value estimation processing unit 252c1.

[0056] The correction value estimation processing unit 252c1 is connected to the matching point detection unit 251c1 and the correction value synthesis unit 255c1. Based on the matching point information output from the matching point detection unit 251c1, the correction value estimation processing unit 252c1 estimates a first correction value and outputs it to the correction value synthesis unit 255c1.

[0057] The matching point detection unit 253c1 is connected to the correction value estimation processing unit 254c1. The matching point detection unit 253c1 receives a clock signal from the main scale CLK 10c, a clock signal from the transmission CLK 20c, and a DM detection notification from the DM information detection unit 22c. Based on this information, the matching point detection unit 253c1 generates matching point information and outputs it to the correction value estimation processing unit 254c1.

[0058] The correction value estimation processing unit 254c1 is connected to the matching point detection unit 253c1 and the correction value synthesis unit 255c1. Based on the matching point information output from the matching point detection unit 253c1, the correction value estimation processing unit 254c1 estimates a second correction value and outputs it to the correction value synthesis unit 255c1.

[0059] The correction value synthesis unit 255c1 is connected to the correction value estimation processing unit 252c1 and the correction value estimation processing unit 254c1. The correction value synthesis unit 255c1 synthesizes the first correction value output from the correction value estimation processing unit 252c1 and the second correction value output from the correction value estimation processing unit 254c1, and detects the delay with a resolution of 1 clock or less.

[0060] The sub-counter unit 256c1 measures the delay in units of one clock cycle using the main scale CLK 10c based on the clock signal from the main scale CLK 10c, the DM transmission completion notification from the DM information insertion unit 18c, and the DM detection notification from the DM information detection unit 22c.

[0061] Figure 8 illustrates the correction process performed by the correction value estimation processing units 252c1 and 254c1 of the first communication device 100c according to a second embodiment of the present invention. Figures 8(A) and 8(B) show the correction process performed by the correction value estimation processing unit 252c1. Figure 8(A) shows the DM transmission completion notification from the DM information insertion unit 18c and the clock signal output from the transmission CLK 20c. Figure 8(B) shows the clock signal output from the main scale CLK 10c.

[0062] The correction value estimation processing unit 252c1 uses the time difference between the rising edge of the transmission CLK 20c when the DM transmission completion notification shown in Figure 8(A) is received and the rising edge of the main scale CLK 10c when the DM transmission completion notification shown in Figure 8(A) is received as the first correction value. The correction value estimation processing unit 252c1 also uses the time when the rising edge of the transmission CLK 20c and the rising edge of the main scale CLK 10c in Figure 8(A) coincide as the first coincidence point.

[0063] Figures 8(A) and 8(B) show the correction process performed by the correction value estimation processing unit 252c1. Figure 8(A) shows the DM transmission completion notification from the DM information insertion unit 18c and the clock signal output from the transmission CLK 20c. Figure 8(B) shows the clock signal output from the main scale CLK 10c.

[0064] On the other hand, Figures 8(B) and 8(C) show the correction processing by the correction value estimation processing unit 254c1. Figure 8(C) shows the DM detection notification from the DM information detection unit 22c and the clock signal output from the receiving CLK 24c. Figure 8(B) shows the clock signal output from the main scale CLK 10c.

[0065] The correction value estimation processing unit 254c1 uses the difference between the rising edge of the received CLK 24c when the DM detection notification shown in Figure 8(C) is received and the rising edge of the main scale CLK 10c when the DM detection notification shown in Figure 8(C) is received as the second correction value. The correction value estimation processing unit 254c1 also uses the time at which the rising edge of the received CLK 24c and the rising edge of the main scale CLK 10c in Figure 8(C) coincide as the second coincidence point.

[0066] Figure 9 is a diagram illustrating the synthesis process by the correction value synthesis unit 255c1 of the first communication device 100c according to a second embodiment of the present invention. The correction value synthesis unit 255c1 measures the delay time with respect to the main scale CLK 10c. Specifically, as shown in Figure 9, the correction value synthesis unit 255c1 determines the delay time based on the following formula (6).

[0067] Delay time = raw counter value × T Ｍ -First correction value + Second correction value ... (6)

[0068] [Modification of the Second Embodiment] Next, a modification of the second embodiment of the present invention will be described. In the second embodiment, a delay measurement unit 25c shown in Figure 7 was provided, whereas in the modification of the second embodiment, a delay measurement unit 25c2 shown in Figure 10 is provided.

[0069] Figure 10 is a schematic block diagram showing the configuration of a delay measurement unit 25c2 according to a modified example of the second embodiment of the present invention. The delay measurement unit 25c2 comprises a matching point detection unit 251c1, a correction value estimation processing unit 252c2, a matching point detection unit 253c2, a correction value estimation processing unit 254c2, a correction value synthesis unit 255c2, and a raw counter unit 256c2. The processing of the matching point detection unit 251c1, the correction value estimation processing unit 252c2, the matching point detection unit 253c2, the correction value estimation processing unit 254c2, and the raw counter unit 256c2 in Figure 10 is the same as the processing of the matching point detection unit 251c1, the correction value estimation processing unit 252c1, the matching point detection unit 253c1, the correction value estimation processing unit 254c1, and the raw counter unit 256c1 in Figure 7, so their explanations are omitted.

[0070] In the delay measurement unit 25c (Figure 7) according to the second embodiment, the clock signal of the main scale CLK 10c was output to the matching point detection units 251c1, 253c1 and the sub-counter unit 256c1, the clock signal of the transmitting CLK 20c was output to the matching point detection unit 251c1, and the clock signal of the receiving CLK 24c was output to the matching point detection unit 253c2. In contrast, the delay measurement unit 25c2 (Figure 10) according to a modification of the second embodiment differs in that the clock signal of the transmitting CLK 20c is output to the matching point detection unit 251c2 and the sub-counter unit 256c2, the clock signal of the main scale CLK 10c is output to the matching point detection units 251c2 and 253c2, and the clock signal of the receiving CLK 24c is output to the matching point detection unit 253c2.

[0071] Figure 11 is a diagram illustrating the synthesis process by the correction value synthesis unit 255c2 according to a modified example of the second embodiment of the present invention. The correction value synthesis unit 255c2 measures the delay time with reference to the transmitted CLK 20c. Specifically, as shown in Figure 11, the correction value synthesis unit 255c2 determines the delay time based on the following formula (7).

[0072] Delay time = raw counter value × TＶ -First correction value + Second correction value ... (7)

[0073] In Figure 11, the case in which the correction value synthesis unit 255c2 measures the delay time based on the transmitted CLK 20c is described, but the correction value synthesis unit 255c2 may also measure the delay time based on the received CLK 24c.

[0074] [Third Embodiment] Next, a third embodiment of the present invention will be described. Figure 12 is a schematic diagram showing the configuration of a communication delay measurement system 1000d according to the third embodiment of the present invention. The communication delay measurement system 1000d comprises a first communication device 100d (also referred to as a communication delay measurement device) and a second communication device 200d.

[0075] The first communication device 100d includes a main scale CLK 10d, a signal generation unit 17d, a DM information insertion unit 18d, a transmission unit 19d, a transmission CLK 20d, a received signal processing unit 21d, a DM information detection unit 22d, a receiving unit 23d, and a delay measurement unit 25d.

[0076] The main scale CLK10d, signal generation unit 17d, DM information insertion unit 18d, transmission unit 19d, transmission CLK20d, received signal processing unit 21d, DM information detection unit 22d, reception unit 23d, and delay measurement unit 25d in Figure 11 perform the same processing as the main scale CLK10c, signal generation unit 17c, DM information insertion unit 18c, transmission unit 19c, transmission CLK20c, received signal processing unit 21c, DM information detection unit 22c, reception unit 23c, and delay measurement unit 25c in Figure 6, so their explanations are omitted.

[0077] In the third embodiment, the delay measurement unit 25d of the first communication device 100d measures the time from the transmission of DM information from the first communication device 100d to the second communication device 200d to the reception of DM information from the second communication device 200d to the first communication device 100d.

[0078] The second communication device 200d in Figure 11 includes a receiving unit 50d, a DM information detection unit 51d, a received signal processing unit 52d, a transmitting unit 54d, a DM information insertion unit 55d, a signal generation unit 56d, a loopback delay measurement unit 57d, a main scale CLK 58d, and a transmitting CLK 59d. Although not shown in Figure 11, the second communication device 200d includes a CPU that controls each part of the second communication device 200d and a memory that stores the data processed by the second communication device 200d.

[0079] The receiving unit 50d is connected to the DM information detection unit 51d and the receiving CLK 53d. The receiving unit 50d receives a signal from the first communication device 100d and outputs it to the DM information detection unit 51d. The receiving unit 50d also causes the receiving CLK 53d to regenerate a clock based on the received signal received from the first communication device 100d.

[0080] The DM information detection unit 51d is connected to the receiving unit 50d, the received signal processing unit 52d, and the loopback delay measurement unit 57d. The DM information detection unit 51d detects DM information from the signal output from the receiving unit 50d and outputs it to the loopback delay measurement unit 57d as a DM detection notification. The DM information detection unit 51d outputs the signal after detecting the DM information to the received signal processing unit 52d.

[0081] The received signal processing unit 52d is connected to the DM information detection unit 51d. The received signal processing unit 52d performs reception processing on the signal output from the DM information detection unit 51d. The signal generation unit 56d is connected to the DM information insertion unit 55d. The signal generation unit 56d generates a data signal to be transmitted from the second communication device 200d to the first communication device 100d and outputs it to the DM information insertion unit 55d.

[0082] The main scale CLK58d is connected to the folding delay measurement unit 57d. The main scale CLK58d has a predetermined period (for example, period T shown in Figure 1). Ｍ The clock signal of ) is output to the aliasing delay measurement unit 57d.

[0083] The DM information insertion unit 55d is connected to the signal generation unit 56d, the transmission unit 54c, and the loopback delay measurement unit 57d. The DM information insertion unit 55d inserts DM (Delay Measurement) information into the data signal output from the signal generation unit 56d and outputs it to the transmission unit 54d. Subsequently, the DM information insertion unit 55d outputs a notification of DM transmission completion to the loopback delay measurement unit 57d.

[0084] The transmitting CLK 59d is connected to the transmitting unit 54d. The transmitting CLK 59d outputs a clock signal with a predetermined period to the transmitting unit 54d. The receiving CLK 53d is connected to the receiving unit 50d. The receiving CLK 53d regenerates the clock based on the clock regeneration instruction output from the receiving unit 50d.

[0085] The transmitting unit 54d is connected to the transmitting CLK 54d and the DM information insertion unit 55d. Based on the clock signal output from the transmitting CLK 54d, the transmitting unit 54d transmits the signal output from the DM information insertion unit 55d to the first communication device 100d.

[0086] The loopback delay measurement unit 57d is connected to the DM information detection unit 51d, the DM information insertion unit 55d, and the main scale CLK 58d. Based on the DM detection notification output from the DM information detection unit 51d, the DM transmission completion notification output from the DM information insertion unit 55d, and the clock signal output from the main scale CLK 58d, the loopback delay measurement unit 57d measures the time required for the loopback of DM information in the second communication device 200d.

[0087] In the third embodiment, the second communication device 200d also measures and corrects the time required from receiving the DM to completing the transmission with a resolution of one clock cycle or less. Therefore, according to the third embodiment, both the first communication device 100d and the second communication device 200d can measure the communication delay with a resolution finer than one clock cycle.

[0088] In the above-described embodiment, the period T of the main scale CLK is Ｍ However, the period T of the vernier scale CLK Ｖ We have explained the case where it is greater than this, but it is not limited to this, the period T of the vernier scale CLK Ｖ However, the period T of the main scale CLK ＭIt may be made to be larger than that.

[0089] Furthermore, in the first embodiment and its modified form, the processing and configuration related to the measurement of quantization error were described with reference to Figures 2 to 5. However, in conjunction with the quantization error measurement function, a function to measure time by counting up in units of one clock cycle based on the main scale CLK or the vernier scale CLK may also be used.

[0090] Furthermore, the principle and apparatus configuration of the delay measurement described in the first embodiment are not limited to specific applications, and can be applied, for example, to LiDAR (Light Detection and Ranging), a technology that measures the distance to an object and the shape of the object based on the information of the reflected light after irradiating it with laser light.

[0091] Furthermore, the functions of at least some of the parts of the apparatus in the first to third embodiments described above, and in the modifications of the first and second embodiments, may be implemented by a computer. In this case, the functions may be implemented by recording a program for implementing these functions on a computer-readable recording medium, loading the program recorded on this recording medium into a computer system, and executing it. Here, "computer system" includes hardware such as an OS (Operating System) and peripheral devices. Furthermore, "computer-readable recording medium" refers to portable media such as flexible disks, magneto-optical disks, ROMs (Read Only Memory), CD-ROMs, and storage devices such as hard disks built into a computer system. Moreover, "computer-readable recording medium" may also include those that dynamically hold programs for a short period of time, such as communication lines used when transmitting programs via networks such as the Internet or communication lines such as telephone lines, and those that hold programs for a certain period of time, such as volatile memory inside a computer system that acts as a server or client in such cases. Furthermore, the above program may be for implementing some of the functions described above, or it may be a program that can implement the above functions in combination with a program already recorded in the computer system, or it may be implemented using a programmable logic device such as an FPGA.

[0092] Although several embodiments of this invention have been described in detail above with reference to the drawings, the specific configuration is not limited to these embodiments and includes designs and the like that do not depart from the spirit of this invention.

[0093] This invention can be applied to communication delay measurement devices and communication delay measurement methods that require measuring communication delay with a resolution finer than one clock cycle.

[0094] 10a, 10b, 10c, 10d... Main scale CLK, 11a... Main scale counter, 12a, 12b... Vernier scale CLK, 13a, 13b... Vernier scale counter, 14a... Comparator, 15a, 15b... Error estimation processing unit, 16b... Match point search counter, 17c, 17d... Signal generation unit, 18c, 18d... DM information insertion unit, 19c, 19d... Transmitting unit, 20c, 20d... Transmitting CLK, 21c, 21d... Received signal processing unit, 22c, 22d... DM information detection unit, 23c, 23d... Receiving unit, 25c, 25c2, 25d... Delay measurement unit, 50c, 50d... Receiving unit, 51c, 51d... DM information detection unit, 52c, 52d... Received signal processing unit, 54c, 54d...Transmission unit, 55c, 55d...DM information insertion unit, 56c, 56d...Signal generation unit, 57d...Loopback delay measurement unit, 58d...Main scale CLK, 59d...Transmission CLK, 100a, 100b...Communication delay measurement device, 100c, 100d...First communication device, 200c, 200d...Second communication device, 251c1, 251c...Two-match point detection unit, 252c1, 252c2...Correction value estimation processing unit, 253c1, 253c2...Match point detection unit, 254c1, 254c2...Correction value estimation processing unit, 255c1, 255c2...Correction value synthesis unit, 256c1, 256c2...Elemental counter unit

Claims

1. A communication delay measuring device comprising: a first clock that generates a first clock signal in a first cycle; a second clock that generates a second clock signal in a second cycle different from the first cycle; and a communication delay measuring unit that measures the communication delay with a time resolution shorter than the first cycle based on the first clock signal generated by the first clock and the second clock signal generated by the second clock.

2. The communication delay measuring device according to claim 1, further comprising a first counter for counting the edges of the first clock signal generated by the first clock, and a second counter for counting the edges of the second clock signal generated by the second clock, wherein the communication delay measuring unit measures the communication delay based on the number counted by the first counter and the number counted by the second counter.

3. A communication delay measuring device according to claim 1 or 2, further comprising a third clock that generates a third clock signal in a third cycle, and a communication delay measuring unit that measures the communication delay based on the first clock signal generated by the first clock, the second clock signal generated by the second clock signal, and the third clock signal generated by the third clock signal.

4. A communication delay measurement method comprising: generating a first clock signal in a first cycle using a first clock; generating a second clock signal in a second cycle different from the first cycle using a second clock; and measuring the communication delay with a time resolution shorter than the first cycle based on the first clock signal generated by the first clock and the second clock signal generated by the second clock.

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