Integrated circuit using standard cell layout structure for eliminating design rule violation and design method thereof

Abstract

The present invention relates to an integrated circuit using a standard cell layout, the integrated circuit being characterized by comprising: a first power region and a second power region which supply positive power; a common power region which supplies negative power; a first PMOS region disposed between the first power region and the common power region and adjacent to the first power region; a first NMOS region disposed between the first PMOS region and the common power region; a second PMOS region disposed between the common power region and the second power region and adjacent to the second power region; and a second NMOS region disposed between the second PMOS region and the common power region, wherein the first PMOS region and the second PMOS region are symmetrically disposed with respect to the common power region, and the first NMOS region and the second NMOS region are symmetrically disposed with respect to the common power region.

Description

Integrated circuit using a standard cell layout structure that eliminates design rule violations and a method for designing the same

[0001] The present invention relates to an integrated circuit using a standard cell layout structure and a method for designing the same, and specifically, to an integrated circuit using a standard cell layout structure capable of eliminating design rule violations and a method for designing the same.

[0002] Semiconductor integrated circuit (IC) design is a core technology for modern electronic devices that require both high performance and low power consumption; among these, the Standard Cell Layout is widely utilized as the fundamental unit of semiconductor chip design. Standard cells play a crucial role in optimizing power consumption and performance while reducing design time through reusable and efficient transistor and circuit placement. Traditionally, a Standard Cell Layout consists of Regular Vt (RVT) PMOS and NMOS regions, providing basic switching speeds while maintaining a balanced power consumption. However, in modern semiconductor designs requiring high-speed operation, it is difficult to achieve sufficient performance with basic RVT implants alone; therefore, efforts are being made to improve transistor switching speeds by adding Low Vt (LVT) implants to standard cells. While LVT implants enable fast switching by providing a low threshold voltage, they come with the disadvantage of increased power consumption and leakage current. Conversely, in mobile devices or battery-based equipment where low-power design is critical, efforts are underway to reduce leakage current and lower power consumption by adding High Vt (HVT) implants to standard cells. HVT implants effectively suppress leakage current by providing a high threshold voltage, but this comes with the disadvantage of degrading the transistor's switching speed. While standard cell layouts attempt to balance performance and power consumption through combinations of these various implants, actual design processes frequently involve mirroring along the X-axis to maintain layout symmetry and reduce area. However, if RVT, LVT, and HVT implants are placed adjacently during this mirroring process, interference between layers can lead to violations of design rules.Violations of design rules can cause critical defects in the semiconductor manufacturing process, leading to increased manufacturing costs and higher defect rates, which in turn reduce overall production efficiency. Furthermore, artificially increasing the spacing between implants to eliminate such violations increases the total layout area, resulting in lower semiconductor chip integration density. This, in turn, increases manufacturing costs and has an adverse effect on product miniaturization. Conventional semiconductor design methods have not been able to completely resolve these issues, leaving design rule violations caused by interference between implants and the inefficient increase in layout area as persistent problems. Therefore, to improve the reliability and efficiency of semiconductor design, a new technical approach is required that can effectively resolve interference between RVT, LVT, and HVT implants in standard cell layouts and minimize layout area while adhering to design rules.

[0003] The present invention aims to reduce the layout area by eliminating design rule violations caused by implants in a standard cell layout.

[0004] However, the technical problem that this embodiment aims to solve is not limited to the technical problem described above, and other technical problems may exist.

[0005] An integrated circuit using a standard cell layout according to the present invention may include a first power region and a second power region that supply positive power, a common power region that supplies negative power, a first PMOS region disposed between the first power region and the common power region and adjacent to the first power region, a first NMOS region disposed between the first PMOS region and the common power region, a second PMOS region disposed between the common power region and the second power region and adjacent to the second power region, and a second NMOS region disposed between the second PMOS region and the common power region. The first PMOS region and the second PMOS region may be symmetrically disposed around the common power region, and the first NMOS region and the second NMOS region may be symmetrically disposed around the common power region.

[0006] According to one embodiment, the first PMOS region and the second PMOS region can be implanted to have a normal threshold voltage (RVT).

[0007] According to one embodiment, the first NMOS region and the second NMOS region may be implanted to have a low threshold voltage (LVT).

[0008] According to one embodiment, the first NMOS region and the second NMOS region may be implanted to have a high threshold voltage (HVT).

[0009] According to one embodiment, it may include a first power region and a second power region that supply negative power, a common power region that supplies positive power, a first NMOS region disposed between the first power region and the common power region and adjacent to the first power region, a first PMOS region disposed between the first NMOS region and the common power region, a second NMOS region disposed between the common power region and the second power region and adjacent to the second power region, and a second PMOS region disposed between the second NMOS region and the common power region. The first NMOS region and the second NMOS region may be disposed symmetrically with respect to the common power region, and the first PMOS region and the second PMOS region may be disposed symmetrically with respect to the common power region.

[0010] According to one embodiment, the first NMOS region and the second NMOS region can be implanted to have a normal threshold voltage (RVT).

[0011] According to one embodiment, the first PMOS region and the second PMOS region can be implanted to have a low threshold voltage (LVT).

[0012] According to one embodiment, the first PMOS region and the second PMOS region can be implanted to have a high threshold voltage (HVT).

[0013] A standard cell layout design method according to another embodiment of the present invention may include the steps of: performing a composite layout for a portion of a standard cell layout; mirroring and arranging the composite layout based on a common voltage area; detecting a design rule violation for the standard cell layout; replacing the composite layout with a single layout when a design rule violation is detected; and verifying the design rule violation for the standard cell layout including the replaced single layout.

[0014] According to one embodiment, the composite layout may include at least normal threshold voltage (RVT) transistors and low threshold voltage (LVT) transistors.

[0015] According to one embodiment, a single layout may include transistors having a low threshold voltage (LVT).

[0016] According to one embodiment, the composite layout may include at least normal threshold voltage (RVT) transistors and high threshold voltage (HVT) transistors.

[0017] According to one embodiment, a single layout may include transistors having a high threshold voltage (HVT).

[0018] A computer-readable storage medium according to another embodiment of the present invention may store instructions for performing a standard cell layout design method described in claims 9 through 13, which is performed by a computing device that designs a standard cell layout.

[0019] According to the present invention, the layout area can be reduced by eliminating design rule violations caused by implants in a standard cell layout.

[0020] Figures 1(a) and 1(b) are diagrams showing a standard cell layout structure using LVT_N implants in the transistors of a portion of the RVT_NMOS region.

[0021] Figures 2(a) and 2(b) are diagrams showing a standard cell layout structure using LVT_P implants in transistors in a portion of the RVT_PMOS region.

[0022] Figures 3(a) and 3(b) are diagrams showing a standard cell layout structure using HVT_N implants in the transistors of a portion of the RVT_NMOS region.

[0023] Figures 4(a) and 4(b) are diagrams showing a standard cell layout structure using HVT_N implants in the transistors of a portion of the RVT_PMOS region.

[0024] FIG. 5 is a diagram showing a standard cell layout structure laid out with LVT_N implants throughout the entire RVT_NMOS region according to one embodiment of the present invention.

[0025] FIG. 6 is a diagram showing a standard cell layout structure laid out with LVT_P implants throughout the entire RVT_PMOS region according to another embodiment of the present invention.

[0026] FIG. 7 is a diagram showing a standard cell layout structure laid out with HVT_N implants throughout the entire RVT_NMOS region according to another embodiment of the present invention.

[0027] FIG. 8 is a diagram showing a standard cell layout structure laid out with HVT_P implants throughout the entire RVT_PMOS region according to another embodiment of the present invention.

[0028] FIG. 9 is a flowchart illustrating a method for designing a standard cell layout structure according to another embodiment of the present invention.

[0029] FIG. 10 is a block diagram showing a computing device that performs a method for designing a standard cell layout structure according to another embodiment of the present invention.

[0030] Embodiments of the present invention are described in detail below with reference to the attached drawings so that those skilled in the art can easily implement the invention. Since the present invention is susceptible to various modifications and may have various embodiments, specific embodiments are illustrated in the drawings and described in detail in the description. However, this is not intended to limit the present invention to specific embodiments, and it should be understood that it includes all modifications, equivalents, and substitutions that fall within the spirit and scope of the invention.

[0031] To clearly explain the present invention, parts unrelated to the description in the drawings have been omitted, and similar parts throughout the specification have been given similar reference numerals. Furthermore, while describing with reference to the drawings, even if components are shown with the same name, the drawing numbers may vary depending on the drawing, and the drawing numbers are merely for the convenience of explanation and the concept, feature, function, or effect of each component is not to be interpreted restrictively by the corresponding drawing number.

[0032] Similar reference numerals are used for similar components when describing each figure. Terms such as "first," "second," etc., may be used to describe various components, but said components should not be limited by said terms. These terms are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be named the second component, and similarly, the second component may be named the first component. The term "and / or" includes a combination of a plurality of related described items or any of a plurality of related described items.

[0033] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as generally understood by those skilled in the art to which this invention pertains.

[0034] Terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the context of the relevant technology, and should not be interpreted in an ideal or overly formal sense unless explicitly defined in this application.

[0035] Throughout the specification, when a part is described as being "connected" to another part, this includes not only cases where they are "directly connected" but also cases where they are "electrically connected" with other elements interposed between them. Furthermore, when a part is described as "comprising" a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but rather allows for the inclusion of additional components; it should be understood that this does not preclude the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0036] In this specification, the term 'part' or 'module' includes a unit realized by hardware or software, or a unit realized using both; a single unit may be realized using two or more pieces of hardware, or two or more units may be realized by a single piece of hardware.

[0037] First, I would like to explain a typical standard cell layout structure from FIGS. 1 to 4.

[0038] Figures 1(a) and 1(b) are diagrams showing a standard cell layout structure using LVT_N implants in the transistors of a portion of the RVT_NMOS region.

[0039] In the standard cell layout structure illustrated in FIG. 1(a), an RVT_PMOS region (120) and an RVT_NMOS region (130) may be arranged between a VDD power region (110) and a VSS power region (140). The VDD power region (110) serves to supply power to semiconductor devices, and the RVT_PMOS region (120) and the RVT_NMOS region (130) may each be composed of PMOS and NMOS transistors (TR). Here, RVT (Regular Threshold Voltage) represents the threshold voltage (Vt) of the transistor, which signifies the reference point of the voltage at which the transistor begins to flow current. The RVT_PMOS (120) may include a PMOS transistor with a standard threshold voltage (RVT), and the RVT_NMOS (130) may include an NMOS transistor with the same threshold voltage. The VSS power region (140) is located in the center of the cell and can be a ground or reference power shared by the RVT_PMOS (120) and RVT_NMOS (130) transistors.

[0040] However, in circuit designs requiring high-speed operation, it is necessary to add LVT_N implants (Low Threshold Voltage NMOS Implants) to some NMOS transistors to lower the threshold voltage of the transistors and improve the switching speed. For example, as shown in FIG. 1(a), there are cases where standard cells must be designed with LVT_N implants applied to some transistors (TR) in the RVT_NMOS region (130).

[0041] In a standard cell layout, if transistors with these LVT_N implants are mirrored along the X-axis, a structure is formed in which the VSS power supply (140) is shared. In this case, because only some transistors use LVT_N implants, the LVT_N implants arranged symmetrically with respect to the shared VSS power supply are not laid out inconsistently. This inconsistency causes an imbalance in the threshold voltage characteristics of the transistors, which causes a Design Rule Violation (DRV).

[0042] In Fig. 1(b), a method of isolating the shared VSS power supply is presented to solve the problem of violating these design rules. When the VSS power supply is isolated, the layout area of ​​the standard cell increases, which leads to increased manufacturing costs and a decrease in integration density.

[0043] Figures 2(a) and 2(b) are diagrams showing a standard cell layout structure using LVT_P implants in transistors in a portion of the RVT_PMOS region.

[0044] Similarly, in the standard cell layout structure illustrated in FIG. 2(a), an RVT_NMOS region (220) and an RVT_PMOS region (230) may be disposed between a VSS power region (210) and a VDD power region (240). The VSS power region (210) supplies ground or reference power to the semiconductor device, and the RVT_PMOS region (230) and the RVT_NMOS region (220) may each be composed of PMOS and NMOS transistors (TR). Here, the RVT_PMOS may include a PMOS transistor with a general threshold voltage (RVT), and the RVT_NMOS may include an NMOS transistor with the same threshold voltage.

[0045] As illustrated in FIG. 2(a), there are cases where standard cells must be designed with LVT_P implants applied to some transistors (TR) in the RVT_PMOS region (230). These LVT_P implants lower the threshold voltage of the PMOS transistors, enabling faster switching, but increase power consumption and leakage current. If the transistors with LVT_P implants are mirrored along the X-axis in the standard cell layout, a structure is formed where the VDD power supply (240) is shared. In this case, because only some transistors use LVT_P implants, the LVT_P implants symmetrically arranged with respect to the shared VDD power supply are laid out inconsistently. This causes an imbalance in the threshold voltage characteristics of the PMOS transistors, which leads to a violation of design rules. When such a violation of design rules occurs, the shared VDD power supply must be separated as shown in FIG. 2(b), but separating the shared VDD power supply increases the standard cell region.

[0046] Figures 3(a) and 3(b) are diagrams showing a standard cell layout structure using HVT_N implants in the transistors of a portion of the RVT_NMOS region.

[0047] In the standard cell layout structure illustrated in FIG. 3(a), an RVT_PMOS region (320) and an RVT_NMOS region (330) may be arranged between the VDD power region (310) and the VSS power region (340). The VDD power region (310) serves to supply power to semiconductor devices, and the RVT_PMOS region (320) and the RVT_NMOS region (330) may each be composed of PMOS and NMOS transistors (TR). In some cases, HVT_N implants are applied to some transistors (TR) in the RVT_NMOS region (330) to increase the threshold voltage of the transistors and decrease the switching speed. In the standard cell layout, if transistors with these HVT_N implants are arranged by mirroring them with respect to the X-axis, a structure is formed in which the VSS power (340) is shared. In this case, since only some transistors use HVT_N implants, the HVT_N implants arranged symmetrically with respect to the shared VSS power source (340) are laid out inconsistently. This causes an imbalance in the threshold voltage characteristics of the NMOS transistors, which leads to a violation of design rules. When such a violation of design rules occurs, the shared VSS power source must be separated as shown in FIG. 3(b), but separating the shared VSS power source increases the standard cell area.

[0048] Figures 4(a) and 4(b) are diagrams showing a standard cell layout structure using HVT_N implants in the transistors of a portion of the RVT_PMOS region.

[0049] In the standard cell layout structure illustrated in FIG. 4(a), an RVT_NMOS region (420) and an HVT_PMOS region (430) may be placed between the VSS power region (410) and the VDD power region. The VSS power region (410) serves to supply ground or reference power to the semiconductor device, and the RVT_PMOS region (430) and the RVT_NMOS region (420) may each be composed of PMOS and NMOS transistors (TR). Here, the RVT_PMOS is a PMOS transistor with a standard threshold voltage (RVT), while the PMOS transistor with an HVT_P implant (High Threshold Voltage PMOS Implant) has a high threshold voltage, which reduces power consumption and ensures stable operation. In the standard cell layout, if these transistors with HVT_P implants are mirrored along the X-axis, a structure is formed in which the VDD power (440) is shared. In this case, since only some transistors use HVT_P implants, the HVT_P implants arranged symmetrically with respect to the shared VSS power supply are laid out inconsistently. This causes an imbalance in the threshold voltage characteristics of the PMOS transistors, which leads to a violation of design rules. In Figure 4(b), a method of isolating the shared VSS power supply is proposed to solve this design rule violation problem, but this results in an increase in the placement area of ​​the standard cell.

[0050] As mentioned above, using a combination of RVT, LVT, and HVT implants in a standard cell layout is a design method intended to strike a balance between high-speed operation and power efficiency. However, design rule violations arising from the application of these complex implants and the mirroring process can cause critical defects in the semiconductor manufacturing process; furthermore, choosing power isolation to resolve this issue entails an increase in layout area.

[0051] Hereinafter, a standard cell layout structure according to various embodiments of the present invention will be described with reference to FIGS. 5 to 12.

[0052] FIG. 5 is a diagram showing a standard cell layout structure laid out with LVT_N implants throughout the entire RVT_NMOS region according to one embodiment of the present invention.

[0053] Referring to FIG. 5, a standard cell layout structure laid out with LVT_N implants throughout the entire RVT_NMOS region according to one embodiment of the present invention includes a first power supply region (510), a first RVT_PMOS (520), a first LVT_NMOS (530), a common power supply region (540), a second LVT_NMOS (531), a second RVT_PMOS (521), and a second power supply region (511). By symmetrically arranging the components around the VSS power region (540), a structure can be implemented that effectively eliminates violations of design rules and minimizes the layout area.

[0054] The first power supply area (510) and the second power supply area (511) are located at one end and the other end of the standard cell and can supply VDD power (positive power).

[0055]

[0056] The first RVT_PMOS (520) and the second RVT_PMOS (521) may each be composed of PMOS transistors having RVT characteristics. The first and second RVT_PMOS transistors may have a general threshold voltage. In the present invention, these PMOS transistors are arranged symmetrically around a common power supply region (540), for example, a VSS power region.

[0057] The first LVT_NMOS (530) and the second LVT_NMOS (531) may be composed of NMOS transistors with LVT_N implants. Since the first and second LVT_NMOS transistors have a low threshold voltage, they provide faster switching speeds and are suitable for circuit designs requiring high-speed operation. These NMOS transistors are symmetrically arranged around the VSS power supply region (540) so that all NMOS transistors maintain the same threshold voltage characteristics, thereby eliminating violations of design rules.

[0058] The common power supply area (540) is located in the center of the standard cell and can supply VSS power (ground or negative power).

[0059] The first RVT_PMOS (520) and second RVT_PMOS (521), and the first LVT_NMOS (530) and second LVT_NMOS (531) transistors can be symmetrically arranged around the VSS power supply area (540). This symmetrical arrangement ensures that all transistors maintain the same implant characteristics with respect to the X-axis, thereby effectively eliminating design rule violations caused by mismatches between implants. Additionally, by symmetrically arranging the first RVT_PMOS (520) and second RVT_PMOS (521) with respect to the VSS power supply area (540), all PMOS transistors maintain the same threshold voltage characteristics.

[0060] Likewise, the first LVT_NMOS (530) and the second LVT_NMOS (531) are symmetrically arranged so that the NMOS transistors receive the same LVT_N implants, ensuring consistent electrical characteristics. As shown in FIG. 5, by placing only standard cells unified with LVT_N implants throughout the entire RVT NMOS region, the NMOS transistors maintain the same threshold voltage characteristics, thereby fundamentally resolving the problem of violating design rules.

[0061] FIG. 6 is a diagram showing a standard cell layout structure laid out with LVT_P implants throughout the entire RVT_PMOS region according to another embodiment of the present invention.

[0062] Referring to FIG. 6, a standard cell layout structure laid out with LVT_P implants throughout the entire RVT_PMOS region according to another embodiment of the present invention may include a first power supply region (610), a first RVT_NMOS (620), a first LVT_PMOS (630), a common power supply region (640), a second LVT_PMOS (631), a second RVT_NMOS (621), and a second power supply region (611).

[0063] The first power supply area (610) and the second power supply area (611) are located at one end and the other end of the standard cell, respectively, and perform the function of supplying VSS power. VSS generally refers to ground or negative power. The first power supply area (610) is positioned at one end of the cell to allow the transistors at one end to receive ground power stably, and the second power supply area (611) is positioned at the other end of the cell to supply ground power to the transistors at the other end.

[0064] The first RVT_NMOS (620) and the second RVT_NMOS (621) can each be composed of NMOS transistors having RVT characteristics. The first RVT_NMOS (620) can be located at one end of a standard cell and the second RVT_NMOS (621) at the other end, and can be positioned between the first power supply area (610) and the second power supply area (611), respectively. Here, the first power supply area (610) and the second power supply area (611) may be supplied with VSS power.

[0065] The first LVT_PMOS (630) and the second LVT_PMOS (631) may each be composed of PMOS transistors with LVT_P implants applied. The LVT_P implants lower the threshold voltage of the PMOS transistors, allowing the transistors to switch quickly even at lower voltages. The first LVT_PMOS (630) is positioned between the first power supply area (610) and the RVT_NMOS (620) and may be located adjacent to the common power supply area (640). The second LVT_PMOS (631) is positioned between the VDD power supply area (640) and the second RVT_NMOS (621) and may be located adjacent to the second power supply area (611).

[0066] A common power supply area (640) is located in the center to provide a positive power supply (VDD) shared by the first RVT_NMOS (620) and second RVT_NMOS (621) and the first LVT_PMOS (630) and second LVT_PMOS (631) transistors. At this time, the first RVT_NMOS (620) and the second RVT_NMOS (621) are symmetrically arranged between the VSS power supply areas (610, 611), and the first LVT_PMOS (630) and the second LVT_PMOS (631) are also symmetrically arranged around the VDD power supply area (640). By being symmetrically arranged around the VDD power supply area (640), design rule violation issues can be effectively eliminated and the layout area minimized.

[0067] FIG. 7 is a diagram showing a standard cell layout structure laid out with HVT_N implants throughout the entire RVT_NMOS region according to another embodiment of the present invention.

[0068] Referring to FIG. 7, a standard cell layout structure laid out with HVT_N implants throughout the entire RVT_NMOS region according to another embodiment of the present invention may include a first power supply region (710), a first RVT_PMOS (720), a first HVT_NMOS (730), a common power supply region (740), a second RVT_PMOS (731), a second HVT_NMOS (721), and a second power supply region (711).

[0069] The first power supply area (710) and the second power supply area (711) are located at one end and the other end of the standard cell, respectively, and can supply VDD power (positive power). The first power supply area (710) is positioned at one end of the cell so that the transistors at one end can stably receive VDD power, and the second power supply area (711) is positioned at the other end of the cell so that VDD power can be supplied equally to the transistors at the other end.

[0070] The first RVT_PMOS (720) and the second RVT_PMOS (721) may each be composed of PMOS transistors having RVT characteristics. The first RVT_PMOS (720) is positioned between the first power supply area (710) and the common power supply area (740), and the second RVT_PMOS (721) is positioned between the common power supply area (740) and the second power supply area (711).

[0071] The first HVT_NMOS (730) and the second HVT_NMOS (731) can each be composed of NMOS transistors with HVT_N implants applied. The HVT_N implant increases the threshold voltage of the NMOS transistor, causing the transistor to flow current only at higher voltages, thereby reducing power consumption and ensuring stable operation. The first HVT_NMOS (730) is positioned between the first RVT_PMOS (720) and the common power supply area (740), and the second HVT_NMOS (731) is positioned between the common power supply area (740) and the second RVT_PMOS (721).

[0072] The common power supply area (740) is located in the center of the standard cell and serves to supply VSS power (ground or negative power).

[0073] In the standard cell layout structure illustrated in FIG. 7, the first RVT_PMOS (720) and the first RVT_PMOS (721), and the first HVT_NMOS (730) and the first HVT_NMOS (731) are symmetrically arranged around the common power supply area (740). By symmetrically arranging the first RVT_PMOS (720) and the second RVT_PMOS (721) with respect to the common power supply area (740), the PMOS transistors maintain the same threshold voltage characteristics. Similarly, the first HVT_NMOS (730) and the second HVT_NMOS (731) are symmetrically arranged so that the NMOS transistors receive the same HVT_N implant, ensuring consistent electrical characteristics. This effectively eliminates violations of design rules and minimizes critical defects in the semiconductor manufacturing process.

[0074] FIG. 8 is a diagram showing a standard cell layout structure laid out with HVT_P implants throughout the entire RVT_PMOS region according to another embodiment of the present invention.

[0075] Referring to FIG. 8, a standard cell layout structure laid out with HVT_P implants throughout the entire RVT_PMOS region according to another embodiment of the present invention may include a first power supply region (810), a first RVT_NMOS (820), a first HVT_PMOS (830), a common power supply region (840), a second RVT_NMOS (831), a second HVT_PMOS (821), and a second power supply region (811).

[0076] The first power supply area (810) and the second power supply area (811) are located at one end and the other end of the standard cell, respectively, and can supply VSS power (ground or negative power). The first power supply area (810) is positioned at one end of the cell so that the transistors at one end can stably receive VSS power, and the second power supply area (811) is positioned at the other end of the cell so that VSS power can be supplied equally to the transistors at the other end.

[0077] The first RVT_NMOS (820) and the second RVT_NMOS (821) may each be composed of NMOS transistors having RVT characteristics. The first RVT_NMOS (820) may be placed between the first power supply area (810) and the common power supply area (840), and the second RVT_NMOS (821) may be placed between the common power supply area (840) and the second power supply area (811).

[0078] The first HVT_PMOS (830) and the second HVT_PMOS (831) can each be composed of PMOS transistors with HVT_P implants applied. The HVT_P implant increases the threshold voltage of the PMOS transistor, causing the transistor to flow current only at higher voltages, thereby reducing power consumption and ensuring stable operation. The first HVT_PMOS (830) is positioned between the first RVT_NMOS (820) and the common power supply area (840), and the second HVT_PMOS (831) is positioned between the common power supply area (840) and the second RVT_NMOS (831).

[0079] The common power supply area (840) is located in the center of the standard cell and can supply VDD power (positive power).

[0080]

[0081] In the standard cell layout structure according to FIG. 8, the first RVT_NMOS (820) and the second RVT_NMOS (821), and the first HVT_PMOS (830) and the second HVT_PMOS (831) can be symmetrically arranged around the common power supply area (840). For example, the first HVT_PMOS (830) and the second HVT_PMOS (821) are symmetrically arranged with respect to the common power supply area (840), and likewise, the first RVT_NMOS (820) and the second RVT_NMOS (831) are symmetrically arranged, so that violations of design rules can be effectively eliminated.

[0082] FIG. 9 is a flowchart illustrating a method for designing a standard cell layout structure according to another embodiment of the present invention.

[0083] Referring to FIG. 9, a method for designing a standard cell layout structure according to another embodiment of the present invention consists of a series of steps to effectively detect and resolve design rule violations that may occur during the semiconductor standard cell layout design process. In particular, the goal is to minimize DRV by converting a complex layout method into a single layout method and to realize a stable and highly reliable semiconductor device.

[0084] First, the process begins with the step (S910) of performing a complex layout. In step S910, a standard cell layout is designed by applying various implants as described in FIGS. 1 to 4. For example, in FIG. 1, LVT_N implants are applied to some transistors (TR) in the RVT_NMOS region to lower the threshold voltage of the transistors and improve the switching speed. In FIG. 2, LVT_P implants are applied to some transistors in the RVT_PMOS region to increase the switching speed of the PMOS transistors. In FIG. 3, HVT_N implants are applied to some transistors in the RVT_NMOS region to increase the threshold voltage of the transistors, thereby reducing leakage current and power consumption. In FIG. 4, HVT_P implants are applied to some transistors in the RVT_PMOS region to achieve a similar effect. This complex layout design is intended to optimize circuit performance by mixing various transistor characteristics. However, because the types of implants applied to each transistor differ during this process, violations of design rules may occur during the subsequent mirroring and placement processes.

[0085] Next, the complex layout is mirrored and arranged based on the common voltage region (S920). In step S920, the previously designed complex layout is mirrored based on the X-axis, that is, based on the common voltage region (VSS or VDD). This allows for the symmetrical arrangement of standard cells to increase integration density and achieve the effect of balancing the power supply.

[0086] Next, a design tool is used to verify design rule violations (S930). In step S930, the designed layout is verified using the design tool for design rule violations. The design tool can detect threshold voltage mismatches between transistors, power supply imbalances, insufficient spacing between wires, and various other design rule violations. For example, if NMOS transistors with LVT_N implants and NMOS transistors without them are symmetrically placed in a mirrored layout, the design tool can detect these mismatches and report them to the DRV.

[0087] If the design tool detects a design rule violation, the process proceeds to a step of replacing the complex layout method with a single layout method (S940). In step S940, the layout is reconfigured to resolve the previously occurred DRV. Specifically, the area where implants were mixed in the complex layout is unified into a single implant. For example, to resolve the DRV related to the LVT_N implant, the entire RVT_NMOS area is replaced with a standard cell laid out with LVT_N implants. This is similar to the method presented in FIG. 5, and consistency of threshold voltage characteristics is ensured by applying the same LVT_N implant to all NMOS transistors.

[0088] Similarly, to resolve DRVs related to LVT_P implants, the entire RVT_PMOS region can be replaced with standard cells laid out with LVT_P implants. This is done in the manner presented in FIG. 6, where all PMOS transistors receive the same LVT_P implants, thereby unifying their electrical characteristics. The same principle is applied to DRVs related to HVT_N implants or HVT_P implants, replacing their layouts in the manner presented in FIGs. 7 and 8, respectively. This single layout method can fundamentally resolve design rule violations caused by mismatches in implant types.

[0089] Finally, a design tool is used to verify design rule violations in the replaced layout (S950). After replacing with a single layout method, the design tool is used to check for design rule violations again. During this process, it is verified whether the layout complies with all design rules, and additional layout adjustments may be performed if necessary. Ultimately, a stable layout can be secured in which all transistors receive the same implant, maintaining consistent threshold voltage characteristics and complying with design rules.

[0090] The design tool used in the present invention is specialized software for the design and verification of semiconductor standard cell layouts, and can effectively detect and resolve design rule violations that may occur during the design process. This design tool can support complex semiconductor designs by providing various functions such as layout editing, design rule checking (DRC), circuit verification (LVS), and parasitic device extraction. Examples of design tools that may be used include Cadence’s Virtuoso platform, Synopsys’ tool set, Mentor Graphics’ Calibre, Silvaco’s Expert Layout Editor and Guardian DRC / LVS, and ANSYS’s RedHawk and Totem; however, these are merely examples of design tools, and various design tools may be selected and used as needed.

[0091] FIG. 10 is a conceptual diagram illustrating a computing device for executing a method according to an embodiment of the present invention. An exemplary computing device (1000) for executing the above-described method and / or embodiment is described. According to one embodiment, the computing device (1000) may be implemented using hardware and / or software configured to interact with a user. Here, the computing device (1000) may include, but is not limited to, a laptop, a desktop, a workstation, a personal digital assistant, a server, a blade server, a main frame, etc. The components of the above-described computing device, their connection relationships, and their functions are intended to be exemplary and are not intended to limit the embodiments of the present invention described and / or claimed herein.

[0092] The computing device (1000) includes a processor (1010), memory (1020), storage device (1030), communication device (1040), a high-speed interface (1050) connected to the memory (1020) and a high-speed expansion port, and a low-speed interface (1060) connected to a low-speed bus and storage device. Each of the components (1010, 1020, 1030, 1040, 1050, and 1060) may be interconnected using various buses and may be mounted on the same main board or connected in other suitable ways. The processor (1010) may be configured to process instructions of a computer program by performing basic arithmetic, logic, and input / output operations. For example, the processor (1010) can process instructions stored in memory (1020), storage device (1030), etc., and / or instructions executed within a computing device (1000) to display graphic information on an external input / output device (1070), such as a display device coupled to a high-speed interface (1050).

[0093] The communication device (1040) may provide a configuration or function for the input / output device (1070) and the computing device (1000) to communicate with each other via a network, and may provide a configuration or function to support the input / output device (1070) and / or the computing device (1000) communicating with other external devices, etc. For example, a request or data generated by the processor of an external device according to arbitrary program code may be transmitted to the computing device (1000) via a network under the control of the communication device (1040). Conversely, a control signal or command provided under the control of the processor (1010) of the computing device (1000) may be transmitted to another external device via the communication device (1040) and the network.

[0094] In FIG. 10, a computing device (1000) is depicted as including one processor (1010), one memory (1020), etc., but is not limited thereto, and the computing device (1000) may be implemented using multiple memories, multiple processors and / or multiple buses, etc. Additionally, in FIG. 10, it is described as having one computing device (1000), but is not limited thereto, and multiple computing devices may interact and perform operations necessary to execute the method described above.

[0095] Memory (1020) can store information within a computing device (1000). According to one embodiment, memory (1020) may be composed of a volatile memory unit or a plurality of memory units. Additionally or alternatively, memory (1020) may be composed of a non-volatile memory unit or a plurality of memory units. Furthermore, memory (1020) may be composed of other forms of computer-readable media, such as a magnetic disk or an optical disk. Additionally, memory (1020) may store an operating system and at least one program code and / or instruction.

[0096] The storage device (1030) may be one or more mass storage devices for storing data for a computing device (1000). For example, the storage device (1030) may be a computer-readable medium including a magnetic disc such as a hard disk or removable disk, an optical disc, a semiconductor memory device such as an EPROM (Erasable Programmable Read-Only Memory), an EEPROM (Electrically Erasable PROM), or a flash memory device, or may be configured to include such a computer-readable medium. Additionally, a computer program may be tangibly implemented on such a computer-readable medium.

[0097] The high-speed interface (1050) and the low-speed interface (1060) may be means for interaction with an input / output device (1070). For example, the input device may include a device such as a camera including an audio sensor and / or an image sensor, a keyboard, a microphone, a mouse, etc., and the output device may include a device such as a display, a speaker, a haptic feedback device, etc. In another example, the high-speed interface (1050) and the low-speed interface (1060) may be means for interfacing with a device in which the configuration or function for performing input and output is integrated into one, such as a touchscreen, etc.

[0098] According to one embodiment, the high-speed interface (1050) manages bandwidth-intensive operations for the computing device (1000), while the low-speed interface (1060) may manage less bandwidth-intensive operations than the high-speed interface (1050), but such function assignments are merely exemplary. According to one embodiment, the high-speed interface (1050) may be coupled to high-speed expansion ports capable of accommodating memory (1020), an input / output device (1070), and various expansion cards (not shown). Additionally, the low-speed interface (1060) may be coupled to a storage device (1030) and a low-speed expansion port. Furthermore, the low-speed expansion port, which may include various communication ports (e.g., USB, Bluetooth, Ethernet, wireless Ethernet), may be coupled to one or more input / output devices (1070), such as a keyboard, a pointing device, or a scanner, or to a networking device such as a router or a switch via a network adapter.

[0099] In FIG. 10, the input / output device (1070) is depicted as not being included in the computing device (1000), but is not limited thereto and may be configured as a single device with the computing device (1000). Additionally, the high-speed interface (1050) and / or low-speed interface (1060) are depicted as elements configured separately from the processor (1010), but are not limited thereto and the high-speed interface (1050) and / or low-speed interface (1060) may be configured to be included in the processor (1010).

[0100] In the present invention, various embodiments may be implemented in a computing device comprising back-end components (e.g., data servers), middleware components (e.g., application servers), and / or front-end components. In this case, the components may be interconnected by any form or medium of digital data communication, such as a communication network. According to one embodiment, the communication network may be composed of a wired network such as Ethernet, Power Line Communication, telephone line communication devices, and RS-serial communication, a mobile communication network, a Wireless LAN (WLAN), a wireless network such as Wi-Fi, Bluetooth, and ZigBee, or a combination thereof. For example, the communication network may include a Local Area Network (LAN), a Wide Area Network (WAN), etc.

[0101] Various embodiments of the present invention, including specific structural and functional details, are exemplary. Accordingly, the embodiments of the present invention are not limited to those described above and may be implemented in various other forms. Furthermore, the terms used in the present invention are intended to describe some embodiments and are not to be interpreted as limiting the embodiments. For example, singular words and the above may be interpreted to include plural forms unless the context clearly indicates otherwise.

[0102] In this invention, unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as generally understood by those skilled in the art to which such concepts belong. Furthermore, commonly used terms, such as those defined in advance, should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology.

[0103] Although the present invention has been described in relation to some embodiments, various modifications and changes may be made without departing from the scope of the invention as understood by a person skilled in the art to which the invention pertains. Furthermore, such modifications and changes should be considered to fall within the scope of the claims appended to this specification.

[0104] [Personal Statement]

[0105] (Korean) This result is the outcome of the Local Government-University Cooperation-based Regional Innovation Project, conducted in 2024 with funding from the Ministry of Education and support from the National Research Foundation of Korea. (2023RIS-009)

[0106] (English)This research was supported by "Regional Innovation Strategy (RIS)" through the National Research Foundation of Korea(NRF) funded by the Ministry of Education(MOE). (2023RIS-009)

[0107] [National R&D projects that supported this invention]

[0108] [Project ID] 1345370817

[0109] [Project No.] 2023RIS-009

[0110] [Ministry Name] Ministry of Education

[0111] [Project Management (Specialized) Agency Name] Jeju Regional Innovation Platform Green Energy Future Mobility Business Group

[0112] [Research Project Name] Green Energy & Future Mobility Core Enterprise Growth Bridge Project

[0113] [Research Project Title] Technology Development for the Regional Advanced Semiconductor Ecosystem

[0114] [Name of Project Performing Organization] Meta C&I Co., Ltd.

[0115] [Research Period] March 1, 2024 – February 28, 2025

Claims

1. A first power area and a second power area supplying positive power; Common power area supplying ground or negative power; A first PMOS region disposed between the first power region and the common power region, and disposed adjacent to the first power region; A first NMOS region disposed between the first PMOS region and the common power region; A second PMOS region disposed between the second power region and the common power region, and disposed adjacent to the second power region; and A second NMOS region disposed between the second PMOS region and the common power region; comprising, An integrated circuit using a standard cell layout, characterized in that the first PMOS region and the second PMOS region are symmetrically arranged around the common power region, and the first NMOS region and the second NMOS region are symmetrically arranged around the common power region.

2. In Paragraph 1, An integrated circuit using a standard cell layout, characterized in that the first PMOS region and the second PMOS region are implanted to have a normal threshold voltage (RVT).

3. In Paragraph 2, An integrated circuit using a standard cell layout, characterized in that the first NMOS region and the second NMOS region are implanted to have a low threshold voltage (LVT).

4. In Paragraph 2, An integrated circuit using a standard cell layout, characterized in that the first NMOS region and the second NMOS region are implanted to have a high threshold voltage (HVT).

5. A first power area and a second power area supplying ground or negative power; Common power area supplying positive power; A first NMOS region disposed between the first power region and the common power region, and disposed adjacent to the first power region; A first PMOS region disposed between the first NMOS region and the common power region; A second NMOS region disposed between the second power region and the common power region, and disposed adjacent to the second power region; and A second PMOS region disposed between the second NMOS region and the common power region; comprising, An integrated circuit using a standard cell layout, characterized in that the first NMOS region and the second NMOS region are symmetrically arranged around the common power region, and the first PMOS region and the second PMOS region are symmetrically arranged around the common power region.

6. In Paragraph 5, An integrated circuit using a standard cell layout, characterized in that the first NMOS region and the second NMOS region are implanted to have a normal threshold voltage (RVT).

7. In Paragraph 6, An integrated circuit using a standard cell layout, characterized in that the first PMOS region and the second NPOS region are implanted to have a low threshold voltage (LVT).

8. In Paragraph 6, An integrated circuit using a standard cell layout, characterized in that the first PMOS region and the second PMOS region are implanted to have a high threshold voltage (HVT).

9. A standard cell layout design method performed by a computing device that designs a standard cell layout, wherein the method comprises: A step of performing a complex layout for a portion of the above standard cell layout; A step of mirroring and arranging the above complex layout based on a common voltage region; A step of detecting design rule violations for the above standard cell layout; If a violation of the above design rule is detected, a step of replacing the complex layout with a single layout; and A step of verifying design rule violations for a standard cell layout including the replaced single layout; A standard cell layout design method including 10. In Paragraph 9, A standard cell layout design method characterized in that the above-described complex layout includes at least normal threshold voltage (RVT) transistors and low threshold voltage (LVT) transistors.

11. In Paragraph 10, A standard cell layout design method characterized in that the above single layout includes transistors having a low threshold voltage (LVT).

12. In Paragraph 9, A standard cell layout design method characterized in that the above-described complex layout includes at least normal threshold voltage (RVT) transistors and high threshold voltage (HVT) transistors.

13. In Paragraph 12, A standard cell layout design method characterized in that the above single layout includes transistors having a high threshold voltage (HVT).

14. A computer-readable storage medium storing instructions for performing a standard cell layout design method described in any one of claims 9 through 13, which is performed by a computing device for designing a standard cell layout.

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