Communication method and apparatus, and vehicle

Abstract

A communication method and apparatus, and a vehicle. The method comprises: a first slave node receiving a downlink frame, which comprises first indication information, second indication information and third indication information, the first indication information being used for indicating whether to execute a write operation on an operation object, the second indication information being used for indicating whether to execute a read operation on the operation object, and the third indication information being used for indicating that the mode of the write operation or read operation is a first mode or a second mode, or the third indication information being invalid, wherein the downlink frame comprises a first field for carrying data associated with the operation object, in the first mode, the number of bytes of the first field is 1, and in the second mode, the number of bytes of the first field is 2; and the first slave node sending an uplink frame, which indicates whether a second slave node has successfully received the downlink frame, wherein the second slave node is a slave node associated with the operation object. The present solution can be applied to the field of audio and video transmission, and can improve the initialization speed of an audio and video system and reduce the overall power consumption of the audio and video system.

Description

Communication methods, devices and vehicles Technical Field

[0001] This application relates to the field of audio and video transmission, and more specifically, to a communication method, apparatus, and vehicle. Background Technology

[0002] In a vehicle's wired audio-visual system, there is usually an audio-visual control device and multiple audio-visual devices. The audio-visual control device and the multiple audio-visual devices are usually connected in a daisy-chain network. The audio-visual control device sends the audio-visual data to be played to one or more audio-visual devices for playback through the audio-visual bus. The audio-visual devices transmit the audio-visual data they have collected to the audio-visual control device through the audio-visual bus.

[0003] When audio / video control devices communicate with multiple audio / video devices in a daisy-chain network, each audio / video device (including slave nodes and their connected external devices, hereinafter referred to as peripherals) needs to be initialized and configured before data transmission occurs in the audio / video system. In scenarios with multiple slave nodes, rapid initialization and configuration of slave nodes can reduce the latency and power consumption of the entire audio / video system.

[0004] Therefore, a communication scheme that can improve the initialization speed of audio and video systems urgently needs to be developed.

[0005] Summary of the Invention

[0006] This application provides a communication method, apparatus, and vehicle that helps improve the initialization speed of audio and video systems, thereby reducing the overall power consumption of audio and video systems.

[0007] In a first aspect, a communication method is provided, which is applied to a slave node in an audio-visual system. For example, it can be executed by a chip or circuit of the slave node. The following description takes the execution of this method by a first slave node or a chip or circuit of the first slave node as an example.

[0008] The method includes: receiving a first downlink frame, the first downlink frame including first indication information, second indication information, and third indication information; the first indication information is used to indicate whether a write operation is performed on the operation object, the second indication information is used to indicate whether a read operation is performed on the operation object; the third indication information is used to indicate whether the write operation mode is the first mode or the second mode, or the third indication information is used to indicate whether the read operation is the first mode or the second mode, or the third indication information is invalid; wherein, the first downlink frame includes a first field, the first field is used to carry data associated with the operation object; in the first mode, the number of bytes in the first field is n; in the second mode, the number of bytes in the first field is m, n and m are both positive integers, and n is not equal to m; sending a first uplink frame, the first uplink frame indicating whether a second slave node has successfully received the first downlink frame, the second slave node being the slave node associated with the operation object.

[0009] In some implementations, the first slave node and the second slave node can be the same slave node, or they can be different slave nodes. When the first slave node and the second slave node are different slave nodes, the second slave node is the downlink slave node of the first slave node.

[0010] In some implementations, the first indication information and the second indication information are carried by a single field in the first downlink frame; or, the first indication information and the second indication information are each carried by two separate fields in the first downlink frame. n can be 1, m can be 2, or n and m can be other positive integers.

[0011] In some implementations, the third indication information may be invalid when the first downlink frame indicates that a read operation is to be performed on the object being operated on.

[0012] In practical implementation, both the first downlink frame and the first uplink frame carry the identifier of the second slave node. This allows each slave node to identify the target slave node of the control information carried in the first downlink frame as the second slave node, or allows each slave node and the master node to identify the initiating slave node of the first uplink frame as the second slave node. The initiating slave node refers to the source of the uplink frame; that is, the slave node that initiates the composition and transmission of the uplink frame. During the transmission of this uplink frame, the data and / or control information within it may change, but the frame number and frame type of the uplink frame remain unchanged.

[0013] It should be noted that the data associated with the operation object can include: data that needs to be written to the operation object when performing a write operation; and data that needs to be read from the operation object when performing a read operation. The slave node associated with the operation object can be: the node through which read and / or write operations on the operation object are performed.

[0014] In the above technical solution, multiple bytes (such as two bytes) of data can be written or read within the first downlink frame transmission cycle, which helps improve data read and write efficiency, thereby improving the initialization speed of the slave node and reducing the overall power consumption of the audio and video system. Furthermore, the first downlink frame is compatible with multiple modes, eliminating the need to design different frame structures for different byte data types. The master and slave nodes also do not need to adopt different processing methods for different frame structures, which helps reduce the complexity of processing transmission frames by the master and slave nodes in the audio and video system.

[0015] In some implementations, m is greater than n. In the first mode, the remaining (mn) bytes are used to carry a state transition timer, which indicates whether the slave node is transitioning from the initialization state to the data transmission state. In other words, when the first downlink frame is compatible with multiple modes, the second mode can be used to accelerate the initialization process in the early stages. When the initialization is complete and the slave node needs to enter the data transmission state, the first mode can be used to control the state transition of the slave node.

[0016] In conjunction with the first aspect, in some implementations of the first aspect, when the second slave node and the first slave node are the same slave node, the method further includes: initiating the first uplink frame.

[0017] Secondly, a communication method is provided, which is applied to a master node in an audio / video system, for example, and can be executed by a chip or circuit of the master node. In some implementations, the method can also be applied to a slave node in the audio / video system, which can be a slave node of the uplink of a second slave node.

[0018] The method includes: sending a first downlink frame, the first downlink frame including first indication information, second indication information, and third indication information; the first indication information is used to indicate whether a write operation is performed on the operation object, the second indication information is used to indicate whether a read operation is performed on the operation object; the third indication information is used to indicate whether the write operation mode is the first mode or the second mode, or the third indication information is used to indicate whether the read operation is the first mode or the second mode, or the third indication information is invalid; wherein, the first downlink frame includes a first field, the first field is used to carry data associated with the operation object; in the first mode, the number of bytes in the first field is n; in the second mode, the number of bytes in the first field is m, n and m are both positive integers, and n is not equal to m; receiving a first uplink frame, the first uplink frame indicating whether a second slave node has successfully received the first downlink frame, the second slave node being the slave node associated with the operation object.

[0019] In conjunction with the second aspect, in some implementations of the second aspect, the method further includes: generating a first downlink frame.

[0020] In conjunction with the first aspect or the second aspect, in some implementations of the first aspect or the second aspect, the first downlink frame further includes fourth indication information, which indicates that the operation object is a register of the second slave node, or the operation object is a first peripheral connected to the second slave node.

[0021] More specifically, the first peripheral connected to the second slave node refers to the register of the first peripheral connected to the second slave node.

[0022] In the above technical solution, the first downlink frame can be used to perform read or write operations on the registers of the slave node, or read or write operations on the registers of the slave node's peripherals, without the need to introduce other frame structures, which helps to reduce the complexity of master and slave nodes in the audio and video system when processing transmission frames.

[0023] In conjunction with the first or second aspect, in some implementations of the first or second aspect, when the fourth indication information indicates that the operation object is the first peripheral device, the first downlink frame also includes a fifth indication information, which indicates that the state of the inter-integrated circuit (I2C) communication between the second slave node and the first peripheral device is at least one of the following: start state, wait state, or end state.

[0024] More specifically, the fifth instruction information indicates the target state of the I2C communication between the second slave node and the first peripheral device, so that the second slave node switches the state of its I2C communication with the first peripheral device to the target state according to the fifth instruction information.

[0025] In the above technical solution, when the operation target is the register of the peripheral device connected to the slave node, the target status of I2C communication is simultaneously indicated to the second slave node through the first downlink frame, without the need to transmit other downlink frames, which helps to save communication overhead. Furthermore, since at least one set of downlink and uplink frames is saved between the master node and the slave node in this process, the communication latency can be further shortened, thereby improving the data reading efficiency or writing efficiency.

[0026] In conjunction with the first aspect or the second aspect, in some implementations of the first aspect or the second aspect, the first uplink frame further includes first information indicating whether the second slave node has received I2C acknowledgment information from the first peripheral.

[0027] The I2C acknowledgment message indicates that the first peripheral device has received I2C-related information sent by the second slave node. This I2C-related information may include, but is not limited to, a start signal, an I2C address, a register address, or data to be written (when the third message indicates that a write operation is being performed on the target). If the second slave node does not receive the I2C acknowledgment message, it means that the first peripheral device has not received the I2C-related information, or that the first peripheral device has not had time to send back I2C acknowledgment or I2C denial information.

[0028] In the above technical solution, the first uplink frame helps the master node to know the transmission status of I2C related information on the second slave node side, so that the master node can adjust or maintain the I2C communication status on the master node side in a timely manner, which helps to ensure the smoothness of read or write operations, thereby improving the data reading efficiency or writing efficiency.

[0029] In conjunction with the first or second aspect, in some implementations of the first or second aspect, when the second indication information indicates that a read operation is performed on the operation object, and the first information indicates that the second slave node has received I2C confirmation information, the first uplink frame also includes a second field, which is used to carry data associated with the operation object.

[0030] In some implementations, when the second indication indicates that a read operation should be performed on the object being operated on, the first indication indicates that a write operation should not be performed on the object being operated on.

[0031] In the above technical solution, when the second slave node receives the I2C confirmation information and the data associated with the operation object, it carries the data associated with the operation object through the first uplink frame, which helps to save communication overhead and communication latency, thereby improving the data reading efficiency.

[0032] In conjunction with the first or second aspect, in some implementations of the first or second aspect, when the first information indicates that the second slave node has not received I2C acknowledgment information, the first uplink frame also includes second information, which indicates that the second slave node has received I2C denial information from the first peripheral device, or that the second information indicates that the second slave node is in a waiting state.

[0033] The second slave node being in a waiting state can be understood as the second slave node waiting to receive I2C acknowledgment information and I2C denial information.

[0034] In the above technical solution, the first uplink frame helps the master node to know that the second slave node has received the I2C denial information from the first peripheral, or that the first peripheral has not had time to send back the I2C denial information and the I2C acknowledgment information.

[0035] In conjunction with the first aspect, in some implementations of the first aspect, the second slave node and the first slave node are the same slave node. The method further includes: when the fifth indication information indicates that the state of I2C communication is a start state and a waiting state, controlling the I2C communication to be in a waiting state; or, when the fifth indication information indicates that the state of I2C communication is a start state, a waiting state, and an end state, controlling the I2C communication to be in an end state.

[0036] In conjunction with the first or second aspect, in some implementations of the first or second aspect, when the second indication information indicates that a read operation is to be performed on the operation object, the first uplink frame also includes data associated with the operation object.

[0037] In conjunction with the first or second aspect, in some implementations of the first or second aspect, when the third indication information indicates the first mode or the third indication information is invalid, the number of bytes of data associated with the operation object carried by the first uplink frame is n; when the third indication information indicates the second mode, the number of bytes of data associated with the operation object carried by the first uplink frame is m.

[0038] In some implementations, m is greater than n. In the first mode, the remaining (mn) bytes are used to carry interrupt-related information, which is used to indicate that a slave node has experienced a first interrupt.

[0039] In the above technical solution, carrying n bytes of data or m bytes of data in the first uplink frame helps to flexibly adjust the data and / or other control information reported in each frame.

[0040] In conjunction with the first or second aspect, in some implementations of the first or second aspect, the first uplink frame indicates that the second slave node has successfully received the first downlink frame.

[0041] In conjunction with the first or second aspect, in some implementations of the first or second aspect, the first downlink frame further includes sixth indication information, which indicates the address of the object to be operated on.

[0042] Specifically, when the operation target is a register of a slave node, the address of the operation target is the address of the register; when the operation target is a peripheral connected to the slave node, the address of the operation target is the I2C address of the peripheral.

[0043] In some implementations, when the fourth indication information indicates that the operation target is the register of the second slave node, the first uplink frame also includes a sixth indication information.

[0044] In some other implementations, when the fourth indication information indicates that the operation object is the register of the peripheral connected to the second slave node, and the fifth indication information indicates that the I2C communication state between the second slave node and the first peripheral device is in the initial state, the first uplink frame also includes a sixth indication information.

[0045] In the above technical solution, when a write operation needs to be performed on the object, the address information of the object and the data to be written to the object are transmitted simultaneously through the first downlink frame, which helps to save communication overhead and reduce communication latency, thereby improving the efficiency of data writing.

[0046] In conjunction with the first or second aspect, in some implementations of the first or second aspect, when the third indication information indicates the second mode, the sixth indication information is the address of the operation object corresponding to a byte of data in the data associated with the operation object.

[0047] In practice, the object of this operation can be a register.

[0048] In the above technical solution, when a register can store one byte of data, the address of the register corresponding to one byte of data can indicate the m registers associated with m bytes of data, which helps to save the communication overhead required to indicate the register address.

[0049] In conjunction with the first aspect, in some implementations of the first aspect, when the first slave node and the second slave node are the same slave node, the method further includes: determining the I2C address of the first peripheral based on the value corresponding to the peripheral I2C address register associated with the first slave node.

[0050] In conjunction with the second aspect, in some implementations of the second aspect, the method further includes: determining the second slave node based on the value of the slave node number field in the node or peripheral selection register associated with the master node.

[0051] In conjunction with the second aspect, in some implementations of the second aspect, the method further includes: determining the register of the slave node or the peripheral connected to the slave node based on the value of the select slave node or peripheral field in the select register of the node or peripheral associated with the master node.

[0052] In conjunction with the first or second aspect, in some implementations of the first or second aspect, after transmitting the first uplink frame, the method further includes: transmitting a fourth downlink frame, the fourth downlink frame indicating the end of a read or write operation.

[0053] Thirdly, a data transmission structure is provided for information transmission between a master node and a second slave node in an audio-visual system. The second slave node is associated with an operation object. The data transmission structure carries first indication information, second indication information, and third indication information. The first indication information indicates whether a write operation is performed on the operation object, and the second indication information indicates whether a read operation is performed on the operation object. The third indication information indicates whether the write operation mode is the first mode or the second mode, or whether the read operation is the first mode or the second mode, or whether the third indication information is invalid. The data transmission structure includes a first field, which carries data associated with the operation object. In the first mode, the number of bytes in the first field is n; in the second mode, the number of bytes in the first field is m, where n and m are both positive integers, and n is not equal to m.

[0054] The data transmission structure provided by this technical solution enables the writing or reading of multiple bytes (such as two bytes) of data within a single frame transmission cycle, which helps improve data read / write efficiency, thereby increasing the initialization speed of slave nodes and reducing the overall power consumption of the audio / video system. Furthermore, this data transmission structure is compatible with multiple modes, eliminating the need to design different data transmission structures for different byte types of data. The master and slave nodes also do not need to adopt different processing methods for different data transmission structures, which helps reduce the processing complexity of master and slave nodes in the audio / video system.

[0055] In conjunction with the third aspect, in some implementations of the third aspect, the data transmission structure also includes a third field, which is used to carry third indication information.

[0056] In conjunction with the third aspect, in some implementations of the third aspect, the data transmission structure also includes a fourth field, which is used to carry the first indication information and / or the second indication information.

[0057] In conjunction with the third aspect, in some implementations of the third aspect, the data transmission structure also includes a fifth field, which is used to carry fourth indication information. The fourth indication information indicates that the operation object is the register of the second slave node, or the operation object is the first peripheral connected to the second slave node.

[0058] The data transmission structure provided by this technical solution enables read or write operations on the registers of slave nodes, or read or write operations on the registers of peripheral devices of slave nodes, without the need to introduce other data transmission structures. This helps to reduce the complexity of data transmission structure processing between master and slave nodes in audio and video systems.

[0059] In conjunction with the third aspect, in some implementations of the third aspect, the data transmission structure further includes a sixth field, which carries fifth indication information. The fifth indication information indicates that the state of the I2C communication between the second slave node and the first peripheral is at least one of the following: start state, wait state, or end state.

[0060] The data transmission structure provided by this technical solution can simultaneously indicate the target status of I2C communication to the second slave node without transmitting other transmission frames, which helps to save communication overhead.

[0061] In conjunction with the third aspect, in some implementations of the third aspect, the data transmission structure also includes a seventh field, which is used to carry the sixth indication information, which indicates the address of the operation object.

[0062] When a write operation needs to be performed on an object, the data transmission structure provided in this application can simultaneously transmit the address information of the object and the data to be written to the object, which helps to save communication overhead and reduce communication latency, thereby improving the efficiency of data writing.

[0063] In conjunction with the third aspect, in some implementations of the third aspect, the data transmission structure also includes an eighth field, which is used to carry the identifier of the second slave node.

[0064] Fourthly, a data transmission structure is provided for information transmission between a master node and a second slave node in an audio-visual system. The second slave node is associated with an operation object, which is the object on which the master node performs read or write operations. The data transmission structure is used to carry feedback information, which indicates whether the second slave node has successfully received the first downlink frame. The first downlink frame indicates that a read or write operation is performed on the operation object.

[0065] In conjunction with the fourth aspect, in some implementations of the fourth aspect, the data transmission structure also includes a ninth field, which is used to carry third information. The third information indicates that the operation object is the register of the second slave node, or the operation object is the first peripheral connected to the second slave node.

[0066] In conjunction with the fourth aspect, in some implementations of the fourth aspect, the data transmission structure includes a second field; when the operation object is the register of the second slave node, the second field is used to carry the data associated with the operation object; when the operation object is the first peripheral connected to the second slave node, and the second slave node receives the I2C acknowledgment information from the first peripheral, the second field is used to carry the data associated with the operation object; or, when the operation object is the first peripheral connected to the second slave node, and the second slave node has not received the I2C acknowledgment information from the first peripheral, the second field is used to carry second information, the second information indicating that the second slave node has received the I2C denial information from the first peripheral; or the second information indicating that the second slave node is in a waiting state.

[0067] The data transmission structure provided by this technical solution helps the master node to know the transmission status of I2C related information on the second slave node side, thereby enabling the master node to adjust or maintain the I2C communication status on the master node side in a timely manner, which helps to ensure the smoothness of read or write operations, thereby improving the data reading efficiency or writing efficiency.

[0068] In conjunction with the fourth aspect, in some implementations of the fourth aspect, the data transmission structure also includes a tenth field, which is used to carry the first information, indicating whether the second slave node has received the I2C acknowledgment information.

[0069] The data transmission structure provided by this technical solution allows the second slave node to carry the data associated with the operation object through the first uplink frame when it receives the I2C confirmation information and the data associated with the operation object. This helps to save communication overhead and communication latency, thereby improving the data reading efficiency.

[0070] In conjunction with the fourth aspect, in some implementations of the fourth aspect, the data transmission structure also includes an eleventh field, which is used to carry feedback information.

[0071] In conjunction with the fourth aspect, in some implementations of the fourth aspect, the data transmission structure also includes a twelfth field, which is used to carry the identifier of the second slave node.

[0072] Fifthly, a communication device is provided, comprising a transceiver unit configured to receive a first downlink frame, the first downlink frame including first indication information, second indication information, and third indication information; the first indication information is used to indicate whether a write operation is performed on an operation object, the second indication information is used to indicate whether a read operation is performed on the operation object; the third indication information is used to indicate whether the write operation mode is a first mode or a second mode, or the third indication information is used to indicate whether the read operation is a first mode or a second mode, or the third indication information is invalid; wherein, the first downlink frame includes a first field, the first field being used to carry data associated with the operation object; in the first mode, the number of bytes in the first field is n; in the second mode, the number of bytes in the first field is m, where n and m are both positive integers, and n is not equal to m; the transceiver unit is further configured to: send a first uplink frame, the first uplink frame indicating whether a second slave node has successfully received the first downlink frame, the second slave node being a slave node associated with the operation object.

[0073] In conjunction with the fifth aspect, in some implementations of the fifth aspect, the apparatus further includes a processing unit, which, when the second slave node and the first slave node are the same slave node, is used to: initiate a first uplink frame.

[0074] In a sixth aspect, a communication apparatus is provided, comprising a transceiver unit for transmitting a first downlink frame, the first downlink frame including first indication information, second indication information, and third indication information; the first indication information is used to indicate whether a write operation is performed on an operation object, the second indication information is used to indicate whether a read operation is performed on the operation object; the third indication information is used to indicate whether the write operation mode is a first mode or a second mode, or the third indication information is used to indicate whether the read operation is a first mode or a second mode, or the third indication information is invalid; wherein the first downlink frame includes a first field, the first field being used to carry data associated with the operation object; in the first mode, the number of bytes in the first field is n; in the second mode, the number of bytes in the first field is m, where n and m are both positive integers, and n is not equal to m; and receiving a first uplink frame, the first uplink frame indicating whether a second slave node has successfully received the first downlink frame, the second slave node being a slave node associated with the operation object.

[0075] In conjunction with the sixth aspect, in some implementations of the sixth aspect, the apparatus further includes a processing unit for: generating a first downlink frame.

[0076] In conjunction with the fifth or sixth aspect, in some implementations of the fifth or sixth aspect, the first downlink frame further includes fourth indication information, which indicates that the operation object is a register of the second slave node, or the operation object is a first peripheral connected to the second slave node.

[0077] In conjunction with the fifth or sixth aspect, in some implementations of the fifth or sixth aspect, when the fourth indication information indicates that the operation object is the first peripheral device, the first downlink frame also includes the fifth indication information, which indicates that the state of the I2C communication between the second slave node and the first peripheral device is at least one of the following: start state, wait state, or end state.

[0078] In conjunction with the fifth aspect, in some implementations of the fifth aspect, the second slave node and the first slave node are the same slave node, and the processing unit of the device is further configured to: control the I2C communication to a waiting state when the fifth indication information indicates that the I2C communication state is a start state and a waiting state; or, control the I2C communication to a stop state when the fifth indication information indicates that the I2C communication state is a start state, a waiting state, and a stop state.

[0079] In conjunction with the fifth or sixth aspect, in some implementations of the fifth or sixth aspect, the first uplink frame further includes first information indicating whether the second slave node has received I2C acknowledgment information from the first peripheral.

[0080] In conjunction with the fifth or sixth aspect, in some implementations of the fifth or sixth aspect, when the second indication information indicates that a read operation is performed on the operation object, and the first information indicates that the second slave node has received I2C confirmation information, the first uplink frame also includes a second field, which is used to carry data associated with the operation object.

[0081] In conjunction with the fifth or sixth aspect, in some implementations of the fifth or sixth aspect, when the first information indicates that the second slave node has not received I2C acknowledgment information, the first uplink frame also includes second information, which indicates that the second slave node has received I2C denial information from the first peripheral; or the second information indicates that the second slave node is in a waiting state.

[0082] In conjunction with the fifth or sixth aspect, in some implementations of the fifth or sixth aspect, when the second indication information indicates that a read operation is to be performed on the operation object, the first uplink frame also includes data associated with the operation object.

[0083] In conjunction with the fifth or sixth aspect, in some implementations of the fifth or sixth aspect, when the third indication information indicates the first mode or the third indication information is invalid, the number of bytes of data associated with the operation object carried by the first uplink frame is n; when the third indication information indicates the second mode, the number of bytes of data associated with the operation object carried by the first uplink frame is m.

[0084] In conjunction with the fifth or sixth aspect, in some implementations of the fifth or sixth aspect, the first uplink frame indicates that the second slave node has successfully received the first downlink frame.

[0085] In conjunction with the fifth or sixth aspect, in some implementations of the fifth or sixth aspect, the first downlink frame also includes sixth indication information, which indicates the address of the object to be operated on.

[0086] In conjunction with the fifth or sixth aspect, in some implementations of the fifth or sixth aspect, when the third indication information indicates the second mode, the sixth indication information is the address of the register corresponding to a byte of data in the data associated with the operation object.

[0087] A seventh aspect provides a communication device comprising: a memory for storing a computer program; and a processor for executing the computer program stored in the memory, such that the device performs a method as described in any possible implementation of the first aspect.

[0088] Eighthly, a communication device is provided, the device comprising: a memory for storing a computer program; and a processor for executing the computer program stored in the memory, such that the device performs a method as described in any possible implementation of the second aspect.

[0089] In conjunction with aspects five through eight, in certain implementations of any of aspects five through eight, the communication device communicates with other communication devices based on the data transmission structure in any possible implementation of aspect three or four.

[0090] Ninth aspect, an audio-visual system is provided, the system including means as in any possible implementation of the fifth aspect and means as in any possible implementation of the sixth aspect; or, the system including means as in any possible implementation of the seventh aspect and means as in any possible implementation of the eighth aspect.

[0091] In a tenth aspect, a vehicle is provided that includes a system as described in any possible implementation of the ninth aspect.

[0092] Eleventhly, a computer program product is provided, the computer program product comprising: computer program code, which, when the computer program code is run on a computer, causes the computer to perform the method in any possible implementation of the first or second aspect.

[0093] It should be noted that the above-mentioned computer program code can be stored in whole or in part on the first storage medium, wherein the first storage medium can be packaged together with the processor or packaged separately from the processor.

[0094] In a twelfth aspect, a computer-readable medium is provided that stores instructions which, when executed by a processor, cause the processor to implement the method in any possible implementation of either the first or second aspect.

[0095] In a thirteenth aspect, a chip is provided, the chip including circuitry for performing the methods in any possible implementation of the first or second aspect described above.

[0096] For the beneficial effects not described in detail in aspects three through thirteen, please refer to the descriptions in aspects one and two, which will not be repeated here. Attached Figure Description

[0097] Figure 1 is a schematic block diagram of an audio-visual system provided in an embodiment of this application;

[0098] Figure 2 is another schematic block diagram of the audio and video system provided in the embodiments of this application;

[0099] Figure 3 is a schematic block diagram of the vehicle provided in an embodiment of this application;

[0100] Figure 4 is a schematic diagram of the communication process involved when performing a write operation on the register of a slave node according to an embodiment of this application;

[0101] Figure 5 is a schematic diagram of the frame structure of the downlink frame provided in an embodiment of this application;

[0102] Figure 6 is another schematic diagram of the communication process involved when performing a write operation on the register of a slave node according to an embodiment of this application;

[0103] Figure 7 is another schematic diagram of the frame structure of the downlink frame provided in the embodiments of this application;

[0104] Figure 8 is another schematic diagram of the communication process involved when performing a write operation on the register of a slave node according to an embodiment of this application;

[0105] Figure 9 is a schematic diagram of the communication process involved when performing a read operation on the register of a slave node according to an embodiment of this application;

[0106] Figure 10 is a schematic diagram of the frame structure of the uplink frame provided in an embodiment of this application;

[0107] Figure 11 is another schematic diagram of the communication process involved when performing a read operation on the register of a slave node according to an embodiment of this application;

[0108] Figure 12 is another schematic diagram of the frame structure of the uplink frame provided in the embodiment of this application;

[0109] Figure 13 is another schematic diagram of the communication process involved when performing a read operation on the register of a slave node according to an embodiment of this application;

[0110] Figure 14 is another schematic diagram of the communication process involved when performing a read operation on the register of a slave node according to an embodiment of this application;

[0111] Figure 15 is a schematic diagram of the communication process involved when performing a read operation on the register of a peripheral device of a slave node according to an embodiment of this application;

[0112] Figure 16 is another schematic diagram of the frame structure of the downlink frame provided in the embodiment of this application;

[0113] Figure 17 is another schematic diagram of the frame structure of the uplink frame provided in the embodiment of this application;

[0114] Figure 18 is another schematic diagram of the communication process involved when performing a read operation on the register of a peripheral device of a slave node according to an embodiment of this application;

[0115] Figure 19 is another schematic diagram of the frame structure of the downlink frame provided in the embodiment of this application;

[0116] Figure 20 is another schematic diagram of the frame structure of the uplink frame provided in the embodiment of this application;

[0117] Figure 21 is a schematic diagram of the communication process involved when performing a write operation on the register of a peripheral device of a slave node according to an embodiment of this application;

[0118] Figure 22 is another schematic diagram of the communication process involved when performing a write operation on the register of a peripheral device of a slave node according to an embodiment of this application;

[0119] Figure 23 is another schematic diagram of the communication process involved when performing a write operation on the register of a peripheral device of a slave node according to an embodiment of this application;

[0120] Figure 24 is another schematic diagram of the communication process involved when performing a write operation on the register of a peripheral device of a slave node according to an embodiment of this application;

[0121] Figure 25 is a schematic flowchart of the communication method provided in an embodiment of this application;

[0122] Figure 26 is a schematic block diagram of a communication device provided in an embodiment of this application;

[0123] Figure 27 is another schematic block diagram of the communication device provided in the embodiments of this application. Detailed Implementation

[0124] The technical solutions in this application will now be described with reference to the accompanying drawings.

[0125] Figure 1 shows a schematic diagram of the audio-visual system provided in an embodiment of this application. As shown in Figure 1, the audio-visual system 100 includes an audio-visual control device 110, an audio-visual device 120, an audio-visual device 130, and an audio-visual device 140. The audio-visual control device 110 includes a main controller 111 and a master node 112; the audio-visual device 120 includes a peripheral device 121 and a slave node 122; the audio-visual device 130 includes a peripheral device 131 and a slave node 132; and the audio-visual device 140 includes a peripheral device 141 and a slave node 142. The master node 112 is connected to the slave nodes 122, 132, and 142 via cables using a daisy-chain networking method. The slave nodes 122, 132, and 142 can be processors, transmission chips, or other devices in each audio-visual device, respectively. The peripheral devices 121, 131, and 141 can each include hardware functional modules such as audio-visual decoders, digital-to-analog converters, and analog-to-digital converters in each audio-visual device. The master node 112 is used for communication between the audio / video control device 110 and the audio / video devices 120 to 140. In one example, the master controller 111 sends the audio / video data that needs to be played by the audio / video device 140 to the peripheral device 141 of the audio / video device 140 in sequence through the master node 112, slave node 122, slave node 132, and slave node 142, and the audio / video data is played through the peripheral device 141. In another example, the audio / video device 130 transmits the audio / video data collected by the peripheral device 131 to the master controller 111 in sequence through the slave node 132, slave node 122, and master node 112. In this embodiment, the master node can be a logical unit that performs resource management and control on the slave nodes in the link. The slave node can be a logical unit that receives resource management and control from the master node in the link.

[0126] As can be seen from the above description, the system shown in Figure 1 mainly involves two parts of information transmission. One part is the information transmission within the audio / video control equipment or within the audio / video equipment itself, such as the information transmission between the main controller and the master node, or the information transmission between slave nodes and, and between slave nodes and, to, peripherals. The aforementioned transmitted information includes control information and / or audio / video data. The control information generally includes the master node's I2C communication protocol, used to configure the registers of the master node, slave nodes, and peripherals connected to the slave nodes. The control information may also include control information related to general purpose input / output (GPIO) interfaces or communication protocols, used for slave nodes to report interrupt requests and the master node to issue control information. The audio / video data may include time division multiplexing (TDM) / inter-IC sound (I2S) audio / video data, pulse density modulation (PDM) audio / video data, etc., transmitted between slave nodes and peripherals connected to them. The other part is the information transmission on the cable shown in the figure, i.e., the information transmission between the master node and slave nodes, or the information transmission between two slave nodes. Information transmission over cables involves encapsulating data or control information generated by peripherals and the main controller in a specific format and transmitting it between multiple nodes.

[0127] In a link consisting of a master node and multiple slave nodes, a link where a slave node transmits information to or towards the master node can be considered an uplink, and a link where the slave node transmits information to a slave node farther from the master node can be considered a downlink. Furthermore, a link where the master node transmits information to a slave node is also a downlink. In other words, a data transmission link from the master node to a slave node is a downlink, and a data transmission link from a slave node to the master node is an uplink. For example, slave node 132 can transmit data to slave node 142 via a downlink, and correspondingly, slave node 132 can also receive data from slave node 142 via an uplink. The master node can transmit data to slave nodes 122, 132, and 142 via downlinks, and slave nodes 122, 132, and 142 can transmit data to master node 112 via uplinks. The slave node in the downlink of slave node m is the slave node farther from the master node relative to slave node m in the daisy chain. If, during the discovery process, the identifiers assigned to slave nodes are sequentially increased, then the downlink slave nodes of slave node m are: slave nodes whose identifiers are greater than those of slave node m. Correspondingly, the uplink slave nodes of slave node m are: slave nodes in the daisy chain that are closer to the master node relative to slave node m; or, slave nodes whose identifiers are smaller than those of slave node m. Frames sent by the master or slave node through the downlink are downlink frames, and frames sent by the slave node through the uplink are uplink frames. Functionally, downlink frames can include downlink discovery frames, downlink configuration frames, downlink data frames, and downlink heartbeat frames; uplink frames can include uplink discovery response frames, uplink configuration response frames, and uplink data frames.

[0128] Figure 2 shows a schematic diagram of the distribution of the audio-visual system provided in this application embodiment in a vehicle. As shown in Figure 2, the audio-visual control device is connected to audio-visual devices 1 to 8 via a daisy-chain network. Audio-visual devices 1 and 3, 3 and 4, 4 and 7, 7 and 8, 8 and 6, 6 and 5, and 5 and 2 can be connected via an in-vehicle audio-visual bus. The audio and video control device may include the audio and video control device 110 shown in FIG1. ​​The audio and video devices 1 to 8 may include one or more of the audio and video devices 120, 130 and 140 shown in FIG1. ​​For example, audio and video device 1 may be the audio and video device 120 shown in FIG1, one or more of audio and video devices 3, 4, 7 and 8 may be the audio and video device 130 shown in FIG1, and one or more of audio and video devices 6, 5 and 2 may be the audio and video device 140 shown in FIG1.

[0129] For example, audio and video devices 1 to 8 may include, but are not limited to: a multimedia head unit, a speaker, a microphone (MIC), and an audio power amplifier (APM).

[0130] Figure 3 shows a functional schematic diagram of a vehicle provided in an embodiment of this application. As shown in Figure 3, the vehicle includes the audio-visual system 100 shown in Figure 1. When the audio-visual system 100 is installed in the vehicle, the audio-visual control device 110 can be installed in at least one of the following: cockpit domain controller (CDC); vehicle domain controller (VDC); and advanced driving domain controller (ADC), or mobile data center (MDC). The cockpit is comprised of several components: CDC (Cockpit Control Unit) and ICAS (Intelligent Cockpit Server). CDC is used to implement intelligent cockpit functions such as human-machine interaction. In practice, CDC may also be called other names, such as Media Graphics Unit (MGU), Intelligent Cockpit Server (ICAS3), or Cockpit Super Core (CSC). VDC (Vehicle Control Unit) is used to implement vehicle control functions. VDC can be seen as an integration of the powertrain domain, chassis domain, and body domain. In practice, VDC may also be called other names, such as Body Domain Controller (BDC), Vehicle Control Server (ICAS1), or Body Super Core (BSC). ADC (Action Control Unit) or MDC (Mechanical Control Unit) is used to implement perception, decision-making, and control functions related to intelligent driving. In practice, ADC or MDC may also be called other names, such as Special Equipment System (SAS), Intelligent Driving Server (ICAS2), or ADAS Super Core. ICAS stands for In-Car Application Server. Alternatively, the audio and video control device 110 can also be located in a central computing platform, for example, the central computing platform may include a vehicle central computer (VCC).

[0131] The main controller 111 and the main node 112 may each include one or more processors in the audio and video control device 110 shown in FIG3, such as processors 201 to 20n (n is a positive integer).

[0132] In other examples, the aforementioned main controller can be a vehicle infotainment system, and the peripheral device can be an audio system or microphone. Accordingly, the node connected to the main controller is the master node, and the node connected to the audio system or microphone is the slave node. The vehicle infotainment system establishes a communication connection with the audio system or microphone to achieve data interaction. Alternatively, the aforementioned main controller can also be a mobile phone, and the peripheral device can be a headset. Accordingly, the node connected to the control components within the mobile phone is the master node, and the node connected to the control components within the peripheral device is the slave node. The mobile phone and the headset establish a communication connection to achieve data interaction.

[0133] It should be understood that Figures 1 to 3 are merely illustrative examples. In actual implementation, the audio-visual system 100 may include more or fewer slave nodes, that is, the audio-visual system may include more or fewer audio-visual devices.

[0134] Generally, when initializing audio / video equipment, the main controller 111 initiates I2C communication as an I2C master, and the master node 112 receives the I2C information sent by the main controller 111 as an I2C slave. This I2C information includes initialization configuration information, such as register addresses and written data values. Further, the master node 112 sends the relevant initialization configuration information to the corresponding slave node via an in-vehicle media transmission protocol to perform read or write operations on the slave node's registers or the registers of peripherals connected to the slave node. Here, I2C communication refers to data transmission between the microcontroller and various integrated circuits via the I2C bus. The aforementioned in-vehicle media transmission information can be a high-speed media transmission (HSMT) protocol or an in-vehicle high-speed media transmission protocol, etc.

[0135] To facilitate understanding of the communication method provided in this application's embodiments, the following detailed description, in conjunction with Figures 4 to 25, illustrates the communication process involved in performing read or write operations on the operation object (i.e., the register of the slave node or the register of the peripheral connected to the slave node). It should be noted that in the I2C operation formats shown in Figures 4 to 25, the signals corresponding to the gray-filled boxes are signals sent from the I2C master to the I2C slave, and the signals corresponding to the white boxes are signals sent from the I2C slave to the I2C master. Furthermore, in the I2C operation format, "AS" represents the acknowledgement (ACK) signal sent by the I2C slave, i.e., AS is an abbreviation for ACK from slave; "NAS" represents the not acknowledgement (NACK) signal sent by the I2C slave, i.e., NAS is an abbreviation for NACK from slaver; "AM" represents the ACK signal sent by the I2C master, i.e., AM is an abbreviation for ACK from master; and "NAM" represents the NACK signal sent by the I2C master, i.e., NAM is an abbreviation for NACK from master.

[0136] It should also be noted that the transmission frames (including downlink frames and uplink frames) involved in this application may include a synchronization field, a control field, and a data field. The synchronization field carries information for clock synchronization, the control field carries the transmission frame number, type, and related control information, and the data field carries relevant data to be sent to the slave or master node. In the following embodiments, unless otherwise specified, a downlink frame refers to the control field of the downlink frame, and an uplink frame refers to the control field of the uplink frame.

[0137] Figure 4 illustrates the communication process involved in performing a write operation on the register of a slave node according to an embodiment of this application. As shown in Figure 4(a), each time a byte of data is written via I2C communication (i.e., single-byte data write mode), the master controller indicates the target slave node to the master node (e.g., sends the slave node number corresponding to slave node n to the master node), and the operation object is the register of the slave node (e.g., indicates the operation to be performed on the register of the target slave node through 1 bit). Then, the master controller sequentially sends a start signal, an I2C address, and a write instruction (R / W = 0) signal. The aforementioned I2C address can be BUS_ADDR, which indicates: based on the I2C protocol, remote access to the register of the slave node and / or the peripheral connected to the slave node via HSMT. After the master controller receives the AS acknowledgment signal 1, the master controller continues to send a register address signal, which indicates the address of the target register to be written. After the master controller receives the AS acknowledgment signal 2 from the master node, the master controller continues to send a signal of the data to be written, which includes the value of the one byte of data to be written to the register. After receiving the AS response signal 3 from the master node (the response signal corresponding to the completion of data writing), the master controller sends an end signal to terminate the write operation on the target object.

[0138] For example, the master controller can indicate the target slave node and the operation object to the master node by writing corresponding information to the node or peripheral selection register (such as 0x18). For example, the functions of the 8 bits of the node or peripheral selection register are shown in Table 1. The information written to the first 6 bits of the node or peripheral selection register is the slave node number, indicating the slave node associated with the operation object; the information written to the 7th bit of the node or peripheral selection register indicates that the operation object is a register of a slave node or a register of a peripheral.

[0139] Table 1

[0140] More specifically, when the master controller needs to write one byte of data to register a of slave node n, the communication flow between the master controller, the master node, and slave node n is shown in Figures 4(b) and (c). The communication flows in parts A and B of Figure 4(b) correspond to those in parts A and B of Figure 4(c), respectively, and register address 1 is the address of register a of slave node n. It should be noted that before part A, the master controller also indicates the target slave node and the register of the slave node to the master node. After the master node receives the I2C signal for one byte of data to be written (a), the following steps are performed between the master node and slave node n:

[0141] S1, the master node sends downlink frame 1 to the slave node n.

[0142] In this downlink frame 1, the mode is indicated as value 1, the operation object is indicated as value 1, and a write operation is performed on the operation object. Furthermore, this downlink frame 1 carries 1 byte of data to be written, 'a', and register address 1.

[0143] For example, mode 1 indicates that the number of bytes of data carried in the transmission frame is 1, mode 2 indicates that the number of bytes of data carried in the transmission frame is 2; operation object 1 indicates that the operation object is the register of the slave node, operation object 2 indicates that the operation object is the peripheral of the slave node.

[0144] S2, the data to be written from node n is written to the register corresponding to register address 1.

[0145] S3, send uplink frame 1 from node n to the master node.

[0146] The uplink frame 1 is used to confirm that the slave node n has correctly received the downlink frame 1. Specifically, the uplink frame 1 is used to confirm that the slave node n has correctly received the control field of the downlink frame 1. For example, when the slave node determines that the verification has passed based on the verification information corresponding to the information in the control field, the slave node can determine that it has correctly obtained the information in the control field.

[0147] Furthermore, after the master node receives uplink frame 1, it sends an AS response signal 3 to the master controller.

[0148] In some implementations, the frame structure of downlink frame 1 in this embodiment is shown in Figure 5, and the downlink frame includes 8 bytes. Specifically:

[0149] The first byte carries the frame number (4 bits), frame type (3 bits), and operation object (1 bit). The frame number field indicates the order of the transmitted frames; for example, the frame number of a downlink frame indicates the order or sequence of the downlink frames among all transmitted frames. The frame number can start from 0 and increment by 1 for each frame in a cyclic count. The frame type field indicates that the downlink frame is a configuration frame. The operation object field indicates whether data is written to the register of the slave node or to the register of the peripheral device connected to the slave node. For example, when the operation object field is 0 (i.e., an example of the first value mentioned above), it indicates that data is written to the register of the slave node; when the operation object field is 1 (i.e., an example of the second value mentioned above), it indicates that data is written to the register of the peripheral device connected to the slave node.

[0150] The second byte is used to carry the slave node identifier (6 bits), which can be determined based on the slave node number sent by the master controller to the master node earlier in Part A.

[0151] The third byte includes a mode field (1 bit), a read field (1 bit), and a write field (1 bit). The mode field indicates the number of bytes of data carried in the transmission frame. For example, when the mode field is 0 (an example of the first value mentioned above), it means that the transmission frame carries one byte of data. When the mode field is 1 (an example of the second value mentioned above), it means that the transmission frame carries two bytes of data. When the read field is 0, it means that the read operation is invalid. When the read field is 1, it means that the read operation is valid. When the write field is 0, it means that the write operation is invalid. When the write field is 1, it means that the write operation is valid.

[0152] The fourth byte is used to carry the register address, which can be determined based on the register address in the I2C information.

[0153] The fifth byte is used to carry the data to be written to the operation object (such as the data to be written, 'a').

[0154] The sixth byte is used to carry the state transition timer. The information in the state transition timer field is used to notify the slave node of a state change, such as notifying the slave node to transition from the initialization state to the data transmission state, or notifying the slave node to transition from the data transmission state to the sleep state.

[0155] The seventh and eighth bytes are used to carry verification information, which is used to verify the information in the first six bytes. For example, the aforementioned verification information can be cyclic redundancy check (CRC) information, etc.

[0156] For example, in this embodiment, the operation object field of downlink frame 1 is 0; the slave node identifier field of downlink frame 1 is set to the identifier of slave node n; the read field of downlink frame 1 is 0, the write field is 1, and the mode field is 0; the register address field of downlink frame 1 carries register address 1.

[0157] Figure 6 illustrates another schematic diagram of the communication process involved in performing a write operation on the register of a slave node according to an embodiment of this application. The difference from the embodiment shown in Figure 4 is that each I2C communication writes n bytes of data (i.e., multi-byte data write mode). As shown in Figure 6(a), during one I2C communication, between the start signal and the end signal sent by the master controller, the master controller can send n bytes of data to the master node. In this case, the downlink frame sent by the master node to the slave node n can carry two bytes of data.

[0158] More specifically, taking the example of the master controller needing to write two bytes of data into the register of slave node n, the communication flow between the master controller, the master node, and the slave node n is shown in Figures 6(b) and (c). The communication flows in parts A and B of Figure 6(b) correspond to the communication flows in parts A and B of Figure 6(c), respectively. Furthermore, since a register can store one byte of data, the aforementioned two bytes of data can be data written to two registers with adjacent addresses. Therefore, register address 2 in Figure 6 can be the address of either of the two registers. For example, if the addresses of the two registers are 0x10 and 0x11, then register address 2 can be 0x10. The difference from the embodiment shown in Figure 4 is that after the master node receives one byte of data to be written (e.g., data a), the master node first buffers the data and sends an AS acknowledgment signal 3 to the master controller. After the master controller receives the acknowledgment signal 3, it then sends another byte of data to be written (e.g., data b) to the master node. After the master node receives 2 bytes of data to be written, the master node and slave node n perform the following steps:

[0159] S1, the master node sends downlink frame 1 to the slave node n.

[0160] In this downlink frame 1, the mode is indicated by value 2, the operation object by value 1, and a write operation is performed on the operation object. Furthermore, this downlink frame 1 carries 1 byte each of data to be written (a) and data to be written (b), as well as register address 2.

[0161] S2, from node n, write the data to be written a and the data to be written b into the register corresponding to register address 2 in sequence.

[0162] In some implementations, when a register can store one byte of data, the register corresponding to register address 2 includes register address 2 and two registers indicated by its adjacent addresses. Then, the data to be written, 'a', and the data to be written, 'b', are sequentially written from node n into the aforementioned two registers.

[0163] In some implementations, when a register can store two bytes of data, the register corresponding to register address 2 is a register, and the slave node n will write the data to be written, a and b, into this register in sequence.

[0164] S3, send uplink frame 1 from node n to the master node.

[0165] The uplink frame 1 is used to confirm that the slave node n has correctly received the downlink frame 1.

[0166] Furthermore, after the master node receives uplink frame 1, it sends an AS acknowledgment signal 4 to the master controller. After receiving the master node's AS acknowledgment signal 4, the master controller sends a termination signal.

[0167] In some implementations, the frame structure of downlink frame 1 in this embodiment is shown in Figure 7, and the downlink frame includes 8 bytes. The frame structure of this downlink frame differs from that shown in Figure 5 in that the fifth and sixth bytes in this downlink frame are used to carry data written to the operation object (such as data to be written a and data to be written b). Furthermore, in this embodiment, the operation object field of downlink frame 1 has a value of 0, the read field has a value of 0, the write field has a value of 1, the mode field has a value of 1, the slave node identifier field sets the identifier of slave node n, and the register address field carries register address 2.

[0168] In some implementations, when two or more bytes of data need to be written to the target object in each I2C communication, each downlink frame transmitted between the master node and the slave node can also carry 1 byte of data, i.e., the downlink frame adopts the frame structure shown in Figure 5. For the aforementioned situation, the communication process between the master controller, the master node, and the slave node n can be as shown in Figure 8. Among them, the communication process of parts A to C in Figure 8(a) corresponds to the communication process of parts A to C in Figure 8(b). As shown in Figure 8, when the master node receives 1 byte of data to be written (such as data a or b), it sends 1 byte of data to be written to the slave node n through a downlink frame (such as downlink frame 1 or 2). Downlink frame 1 in Figure 8 also carries register address 2, and downlink frame 2 can carry register address 2. Furthermore, after the master node receives an uplink frame indicating that the data writing is complete, it sends an AS acknowledgment signal to the master controller until all the data that the master controller needs to write has been written. Then, the master controller sends an end signal to the master node to end the data writing process. It should be understood that Figure 8 illustrates the example of writing two bytes of data to the operation object in each I2C communication. When more than two bytes of data need to be written to the operation object, the following steps ① to ③ are repeated until more than two bytes of data are written: ① The master controller sends the data to be written to the master node, ② S1 to S3 (or S4 to S6), and ③ The master node sends the AS response signal to the master controller.

[0169] In some implementations, when each I2C communication requires writing more than two bytes of data to the target object, the downlink frame transmitted between the master node and the slave node may include a downlink frame carrying 1 byte of data, i.e., the downlink frame adopts the frame structure shown in Figure 5; or, it may include a downlink frame carrying 2 bytes of data, i.e., the downlink frame adopts the frame structure shown in Figure 7. In the aforementioned cases, after the master node transmits a downlink frame carrying 1 byte of data to the slave node n, it can then transmit a downlink frame carrying 2 bytes of data, until all two or more bytes of data have been written. For more specific implementation details, please refer to the descriptions in Figures 6 and 8, which will not be repeated here.

[0170] Figure 9 illustrates the communication process involved in performing a read operation on the register of a slave node according to an embodiment of this application. As shown in Figure 9(a), each time a byte of data is read via I2C communication (i.e., single-byte data read mode), after the master controller indicates the target slave node and the register of the slave node to the master node, the master controller first sends a virtual write signal. This virtual write signal is used to indicate to the master node the register corresponding to the address of the operation object (i.e., the register address). After the master controller receives the AS response signal for the register address signal, the master controller continues to send the I2C address and read instruction (R / W=1) signal. The master node controls the slave node to read data from the operation object according to the I2C address and read instruction signal. When the master node receives the data from the operation object, it sends the AS response signal 3 to the master controller. After receiving the response signal 3, the master controller obtains the data to be read from the master node, and then sends the NAM response signal and the end signal to the master node to end the read operation on the operation object.

[0171] More specifically, when the master controller needs to read one byte of data (e.g., data A) from register b of slave node n, the communication flow between the master controller, master node, and slave node n is shown in Figures 9(b) and (c). It should be understood that the communication flows of the virtual write section, section A, and section B in Figure 9(b) correspond to the communication flows of the virtual write section, section A, and section B in Figure 9(c), respectively, and register address 3 is the address of register b of slave node n. It should be noted that before section A, the master controller also indicates the target slave node and the register whose operation object is the slave node to the master node. After the master node receives the I2C signal indicating the configuration of the node or peripheral selection register (e.g., 0x18), it can determine the master controller's I2C bus address (e.g., BUS_ADDR) based on the configuration of this register, access the corresponding slave node (e.g., slave node number), and the node or peripheral selection status (e.g., selecting a slave node or selecting a peripheral), and then perform the following steps between the master node and slave node n:

[0172] S1, the master node sends downlink frame a to the slave node n.

[0173] In this downlink frame a, the mode is indicated as value 1, the operand is indicated as value 1, and a read operation is performed on the operand. Furthermore, this downlink frame a also carries register address 3.

[0174] S2, read data A from the register corresponding to register address 3 from node n.

[0175] S3, the slave node n sends an uplink frame a to the master node. The uplink frame a indicates that the slave node n has correctly received the downlink frame a, and the uplink frame a carries data A.

[0176] Furthermore, after the master node receives uplink frame a, it sends an AS response signal 3 to the master controller.

[0177] In some implementations, the frame structure of the aforementioned downlink frame a can be as shown in Figure 5. More specifically, in this embodiment, the operation object field of downlink frame a is 0, the read field is 1, the write field is 0, the mode field is 0, the slave node identifier field sets the identifier of slave node n, the register address field carries register address 3, and the fifth byte is the default value.

[0178] In some implementations, the frame structure of the aforementioned uplink frame is as shown in Figure 10, and this uplink frame includes 8 bytes. Specifically:

[0179] The first byte carries the frame number (4 bits), frame type (3 bits), and operation object (1 bit). The specific meaning of each of the aforementioned pieces of information can be found in the description of the corresponding part in Figure 4, and will not be repeated here.

[0180] The second byte carries the slave node identifier (6 bits) and frame acknowledgment information (1 bit). It should be noted that the frame number, frame type, operation target, and slave node identifier of the uplink frame must be consistent with its corresponding downlink frame. The correspondence between uplink and downlink frames can be understood as: the uplink frame is a response frame to the downlink frame. The aforementioned frame acknowledgment information is used to indicate whether the slave node n has successfully received the control information in the downlink frame (as shown in the control field of the downlink frame). For example, a frame acknowledgment field value of 0 indicates that the slave node n has not successfully received the control information in the downlink frame; a frame acknowledgment field value of 1 indicates that the slave node n has successfully received the control information in the downlink frame.

[0181] The third byte is used to carry the data of the one byte read.

[0182] The fourth and fifth bytes are used to carry verification information, which is used to verify the information in the first three bytes.

[0183] The sixth and seventh bytes are used to carry interrupt-related information. Specifically, the sixth byte carries the identifier (6 bits) of the slave node that initiated the interrupt and the interrupt request information (1 bit), and the seventh byte carries the interrupt type information. When a slave node experiences an interrupt, it can initiate an interrupt to indicate the location and type of the interrupt to the master node. "Slave node interrupt" can be understood as: the slave node itself has experienced an interrupt; or, an interrupt related to the slave node has occurred, for example, if the slave node is not a terminal slave node, and an interrupt occurs between the slave node and the downlink slave node, this interrupt can be considered a slave node-related interrupt; or, an interrupt affecting the slave node has occurred, for example, an interrupt in the communication bus of an audio / video system, which may affect the stability of the audio / video system, in which case the interrupt is considered to affect the current slave node. In addition, the interrupt type includes any of the following: cable failure, bus error, master node-related interrupt, general purpose input / output (GPIO) interrupt, or mailbox interrupt.

[0184] The eighth byte is used to carry verification information, which is used to verify the information carried by the sixth and seventh bytes.

[0185] In this embodiment, the operation object field of uplink frame a is set to 0, the slave node identifier field sets the identifier of slave node n, the frame acknowledgment field is set to 1, and the (read) data field carries data A. When a slave node initiates an interrupt, the sixth and seventh bytes can also carry interrupt-related information. Furthermore, the frame number and frame type of uplink frame a are the same as those of downlink frame a.

[0186] It should be understood that the frame structure of the uplink frame involved in the embodiments corresponding to Figures 4, 6 and 8 can also be as shown in Figure 10, and the content of the uplink frame is similar to the aforementioned uplink frame a. The difference is that in the uplink frames of Figures 4, 6 and 8, the (read) data field is a default value.

[0187] Figure 11 illustrates another schematic diagram of the communication process involved in performing a write operation on the register of a slave node according to an embodiment of this application. The difference from the embodiment shown in Figure 9 is that each I2C communication reads n bytes of data (i.e., multi-byte data read mode). As shown in Figure 11(a), during one I2C communication, between the start signal and the end signal sent by the master controller, the master controller can read n bytes of data from the master node. In this case, the uplink frame sent by slave node n to the master node can carry two bytes of data.

[0188] More specifically, taking the example of the master controller needing to read two bytes of data from the register of slave node n, the communication flow between the master controller, master node, and slave node n is shown in Figures 11(b) and (c). The virtual write, part A, and part B communication flows in Figure 11(b) correspond to the virtual write, part A, and part B communication flows in Figure 11(c), respectively. Furthermore, since a register can store one byte of data, the aforementioned two bytes of data can be data read from two registers with adjacent addresses. Therefore, register address 4 in Figure 11 can be the address of either of the two registers, for example, the address of the register with the smaller value. The difference from the embodiment shown in Figure 9 is that after slave node n reads two bytes of data (such as data A and data B), it sends the two bytes of data to the master node via uplink frame a, and the master node then sends the two bytes of data to the master controller in sequence.

[0189] In some implementations, the frame structure of downlink frame a in this embodiment is shown in Figure 7. More specifically, in this embodiment, the operation object field of downlink frame a is 0, the read field is 1, the write field is 0, the mode field is 1, the slave node identifier field sets the identifier of slave node n, the register address field carries the register address 4, and the fifth and sixth bytes are default values.

[0190] In some implementations, the frame structure of uplink frame a in this embodiment is shown in Figure 12(a), which includes 8 bytes. The frame structure of this uplink frame differs from that shown in Figure 10 in that the sixth byte in this uplink frame is used to carry data read from the operation object; the seventh byte is used to carry verification information, which is used to verify the data carried in the sixth byte; and the eighth byte is a reserved byte.

[0191] In some other implementations, the frame structure of uplink frame a in this embodiment is shown in Figure 12(b), which includes 8 bytes. The frame structure of this uplink frame differs from that shown in Figure 12(b) in that the third and fourth bytes of this uplink frame are used to carry data read from the operation object; the fifth to seventh bytes are used to carry verification information, wherein the verification information carried by the fifth and sixth bytes is used to verify the information carried in the first three bytes, and the verification information carried by the seventh byte is used to verify the data carried in the fourth byte.

[0192] In this embodiment, the operation object field of uplink frame a is set to 0, the slave node identifier field sets the identifier of slave node n, the frame acknowledgment field is set to 1, and the (read) data field carries data A and data B. The specific content carried by the other fields in uplink frame a can be found in the description of uplink frames in Figure 9, and will not be repeated here.

[0193] In some implementations, when each I2C communication requires reading two or more bytes of data from the operating object, each uplink frame transmitted between the master node and the slave node can also carry one byte of data, i.e., the uplink frame adopts the frame structure shown in Figure 10. For the aforementioned situation, the communication process between the master controller, the master node, and the slave node n can be as shown in Figure 13. Among them, the virtual write in Figure 13(a) and the communication process from A to C correspond to the virtual write in Figure 13(b) and the communication process from A to C, respectively. As shown in Figure 13, each time the master node receives one byte of data (such as data A or B) from the uplink frame, it sends an AS acknowledgment signal to the master controller, so that the master controller reads one byte of data. This continues until the master controller has read all the data that needs to be read. Then, the master controller sends a NAM acknowledgment signal and a stop signal to the master node, ending the data reading process. It should be understood that Figure 13 illustrates the example of writing two bytes of data to the operation object in each I2C communication. When more than two bytes of data need to be written to the operation object, the following steps ① to ④ are repeated until more than two bytes of data are read: ① S1 to S3 (or S4 to S6), ② the master node sends an AS response signal to the slave node, ③ the master controller reads data from the master node, and ④ the master controller sends an AM response signal to the master node.

[0194] In some implementations, when each I2C communication requires reading more than two bytes of data from the operation object, the uplink frame transmitted between the master and slave nodes may include an uplink frame carrying 1 byte of data, i.e., the uplink frame adopts the frame structure shown in Figure 10; or, it may include an uplink frame carrying 2 bytes of data, i.e., the uplink frame adopts the frame structure shown in Figure 12. Figure 14 shows a schematic diagram of the communication flow with an uplink frame carrying 2 bytes of data. For a more specific implementation of this flow, please refer to the descriptions in Figures 11 and 13, which will not be repeated here.

[0195] It should be understood that the frame structure of the uplink frame involved in the embodiments corresponding to Figures 6 and 8 can also be as shown in Figure 12, and the content of the uplink frame is similar to the uplink frame a involved in Figure 11 above. The difference is that in the uplink frames of Figures 6 and 8, the (read) data field is a default value.

[0196] Figure 15 illustrates the communication flow involved in performing a write operation on the register of a peripheral connected to a slave node according to an embodiment of this application. In a single I2C communication, if the master controller needs to write one byte of data to the register of the peripheral m connected to the slave node n, the communication flow between the master controller, the master node, the slave node n, and the peripheral m is shown in Figure 15. The slave node n and the peripheral m can belong to an audio / video device n, which can be any of the audio / video devices shown in Figures 1 to 3. The communication flow in parts A to D of Figure 15(a) corresponds to the communication flow in parts A to D of Figure 15(b). Generally, one peripheral is connected to one register; therefore, register address 5 is the I2C address of peripheral m. In some implementations, one peripheral is connected to multiple registers; in this case, register address 5 is still the I2C address of peripheral m. The slave node n can repeatedly execute part B and S1' to S6' based on register address 5 to write data to the target register of peripheral m.

[0197] It should be noted that the communication process shown in Figure 15 differs from that in Figure 4 in that, before the master controller sends a signal indicating the I2C address of peripheral m and the data to be written to the master node, the master controller needs to write the I2C address of peripheral m into the register of slave node n so that slave node n can determine the target of the operation. Specifically, before executing part A of the communication, the master controller indicates the target slave node to the master node (e.g., sends the slave node number corresponding to slave node n to the master node), and the register of the target slave node (e.g., indicates the operation to be performed on the target slave node through 1 bit). After the master node confirms receipt of the signal indicating the target slave node and the target slave node, it executes part A of the communication process, which specifically includes:

[0198] The master controller sequentially sends a start signal, an I2C address, and a write instruction (R / W = 0) signal. After receiving the AS acknowledge signal 1 from the master node, the master controller continues to send a register address signal, which indicates that an operation needs to be performed on the register of the slave node's peripheral. After receiving the master node's AS acknowledge signal 2, the master controller continues to send a data signal, which indicates which specific peripheral of the slave node should be operated on. For example, 0x17 represents the address of the peripheral I2C address register. The specific value of 0x17 represents the I2C address of a peripheral of the slave node. For example, 0x10 represents the I2C address of peripheral 1 of the slave node, and 0x11 represents the I2C address of peripheral 2 of the slave node. The aforementioned register address signal can carry 0x17, and the data signal can carry the specific value of 0x17, such as 0x10 or 0x11. In this embodiment, the data signal carries register address 5, that is, the I2C address of peripheral m.

[0199] For example, the master controller can indicate the address of the object to be operated on to the slave node by writing the I2C address of the peripheral m into the peripheral I2C address register (e.g., 0x17) of the slave node n. For example, the functions of the 8 bits of the peripheral I2C address register are shown in Table 2, where the information written into the first 7 bits of the peripheral I2C address register is the I2C address of the peripheral m, indicating the address of the object to be operated on.

[0200] Table 2

[0201] After the master node receives the data signal from part A, it performs the following steps:

[0202] S1, the master node sends downlink frame 1.

[0203] In this downlink frame 1, the mode is indicated by value 1, the operation object is indicated by value 1, and a write operation is performed on the operation object. Furthermore, downlink frame 1 carries the peripheral I2C address (“REG”) and the I2C address (“data”) of peripheral m. Specifically, in this embodiment, the frame structure of downlink frame 1 can be as shown in Figure 5, where the operation object field of downlink frame 1 has a value of 0, the read field has a value of 0, the write field has a value of 1, the mode field has a value of 1, the slave node identifier field sets the identifier of slave node n, the register address field carries the peripheral I2C address (e.g., 0x17), and the data field carries the I2C address of peripheral m. It should be understood that the identifier of slave node n is determined based on the slave node number sent by the master controller.

[0204] After receiving downlink frame 1 from node n, the I2C address of peripheral m is written into the register corresponding to the peripheral I2C address, and S2 is executed.

[0205] S2, send uplink frame 1 from node n.

[0206] Uplink frame 1 is used to confirm that the slave node n has correctly received downlink frame 1. Specifically, in this embodiment, the frame structure of uplink frame 1 can be as shown in Figure 10, and the operation object field of uplink frame 1 is set to 0, the slave node identifier field is set to the identifier of slave node n, the frame acknowledgment field is set to 1, and the (read) data field is the default value. In addition, the frame number and frame type of uplink frame 1 are the same as those of downlink frame 1.

[0207] After the master node receives uplink frame 1, it sends an AS acknowledgment signal 3 to the master controller. After receiving acknowledgment signal 3, the master controller sends an end signal to the master node to indicate the end of this I2C communication. Further, in part B, the master controller sends a start signal to the master node to initiate the process of writing data to the register of peripheral m of slave node n. It should be noted that before the master controller sends the start signal of part B, the master controller indicates the target slave node to the master node (e.g., sending the slave node number corresponding to slave node n to the master node), and the peripheral to be operated on (e.g., indicating the operation on the target slave node's peripheral via 1 bit). After the master node confirms receipt of the signal indicating the target slave node and the peripheral to be operated on, it executes the subsequent process of part B, specifically including:

[0208] The master controller sequentially sends a start signal, an I2C address, and a write instruction (R / W = 0) signal. After receiving the AS acknowledge signal 1, the master controller continues to send a register address signal, which carries the I2C address of peripheral m. After receiving the master node's AS acknowledge signal 4, the master controller continues to send a data signal, which carries the data to be written to the register of peripheral m (such as data to be written 1'). After the master node receives the signal indicating the data to be written 1', the following steps are performed between the master node and slave node n, between slave node n and peripheral m, and between the master node and the master controller:

[0209] S1', the master node sends downlink frame 1' to the slave node n.

[0210] In this downlink frame 1', the mode is indicated as value 1, the target object as value 2, and a write operation is performed on the target object. Furthermore, downlink frame 1' indicates that the I2C communication state between node n and peripheral m is in the initial state ("start"), and downlink frame 1' also carries data 1' to be written.

[0211] After receiving downlink frame 1' from node n, the I2C address of peripheral m is determined based on the values ​​of the first 7 bits in the peripheral I2C address register. A start signal is then sent to peripheral m, and S2' is executed. S2' can be executed before, after, or simultaneously with the start signal.

[0212] S2', send uplink frame 1' from node n to the master node.

[0213] The uplink frame 1' indicates that the slave node n acknowledges receipt of the control information in the downlink frame 1' ("acknowledgment"). The uplink frame 1' also indicates that the slave node n is waiting for the peripheral m to send back I2C acknowledgment information (such as the AS's acknowledgment signal) and / or I2C denial information (such as the NAS's acknowledgment signal) ("waiting").

[0214] S3', the master node sends downlink frame 2' to the slave node n.

[0215] The downlink frame 2' indicates that the I2C communication status between node n and peripheral m is in a waiting state ("waiting").

[0216] It should be understood that the "waiting" indicated by the downlink frame is different from the "waiting" indicated by the uplink frame. The "waiting" indicated by the downlink frame indicates the communication status between the slave node n and the peripheral m, while the "waiting" indicated by the uplink frame indicates whether the slave node n has received an acknowledgment signal (such as AS and / or NAS) from the peripheral m.

[0217] S4', send uplink frame 2' from node n to the master node.

[0218] The frame structure and content of uplink frame 2' can be the same as those of uplink frame 1'.

[0219] S5', the master node sends downlink frame n' to slave node n.

[0220] The frame structure and content of downlink frame n' and downlink frame 2' can be the same.

[0221] In some implementations, multiple sets of downlink and uplink frames can be transmitted between S4' and S5'. The frame structure and content of the downlink frames in each set can be the same as those of downlink frame 2', and the frame structure and content of the uplink frames in each set can be the same as those of uplink frame 1'.

[0222] It should be noted that while executing S2 to S5, the following communication process is performed between slave node n and peripheral device m: slave node n sends the I2C address and write instruction (R / W=0) signal to peripheral device m; peripheral device m sends the AS acknowledge signal a to slave node n; slave node n sends the signal indicating register address 5 to peripheral device m; peripheral device m sends the AS acknowledge signal b to slave node n; slave node n sends the data to be written 1' to peripheral device m; peripheral device m sends the AS acknowledge signal c to slave node n.

[0223] If node n receives an acknowledgment signal c from peripheral m at or after receiving downlink frame n', then S7' is executed.

[0224] S6', send uplink frame n' from node n to the master node.

[0225] The uplink frame n' indicates that the slave node n has acknowledged receiving the control information in the downlink frame n', and that the slave node n has received the I2C acknowledgment information from the peripheral m, which indicates that the peripheral m has received the data to be written 1'.

[0226] After receiving uplink frame n' from node n, the slave node sends an acknowledgment signal 2 (AS) to the master node, indicating that the master node has received register address 4. Upon receiving acknowledgment signal 2, the master controller sends the data to be written, 1', to the master node. After receiving the data to be written, 1', the master node executes step S7.

[0227] After receiving uplink frame n', the master node sends an acknowledgment signal 3 to the master controller, indicating that the master node has received the data to be written, 1'. Upon receiving acknowledgment signal 3, the master controller sends a stop signal to the master node to terminate the data writing process. Further, upon receiving the stop signal from the master controller, the master node executes S7'.

[0228] S7', the master node sends downlink frame m to slave node n.

[0229] The downlink frame m is used to indicate that the I2C communication between node n and peripheral m has entered the end state.

[0230] After receiving downlink frame m from node n, a stop signal is sent to peripheral m to terminate the data writing process. S8' is executed before, after, or during the execution of the stop signal from node n.

[0231] S8', the node n sends the uplink frame m to the master node.

[0232] The uplink frame m indicates that node n has acknowledged receiving the downlink frame m.

[0233] In actual implementation, multiple sets of downlink and uplink frames can be transmitted between S6' and S7'. The frame structure and content of the downlink frames in each set can be the same as those of downlink frame 2', and the frame structure and content of the uplink frames in each set can be the same as those of uplink frame n'.

[0234] In some implementations, the frame structure of the downlink frame involved in S1' to S8' of this embodiment can be as shown in Figure 16. This downlink frame includes 8 bytes. The frame structure of this downlink frame differs from that shown in Figure 5 in that the first three bits of the fourth byte of this downlink frame are used to carry I2C communication status indication information, which indicates the target status of I2C communication between the slave node n and the peripheral m. More specifically, the first bit (hereinafter referred to as the start field) is used to indicate whether the I2C communication is in the initial state, and the value of the start field can be 0 or 1; the second bit (hereinafter referred to as the end field) is used to indicate whether the I2C communication is in the final state, and the value of the end field can be 0 or 1; the third bit (hereinafter referred to as the wait field) is used to indicate whether the I2C communication is in the wait field, and the value of the wait field can be 0 or 1. In actual implementation, if the values ​​of the start field, end field, and wait field are 1, 0, and 0 respectively, it indicates that the target state of the I2C communication between slave node n and peripheral m is the start state; if the values ​​of the start field, end field, and wait field are 0, 0, and 1 or 1, 0, and 1 respectively, it indicates that the target state of the I2C communication between slave node n and peripheral m is the wait state; if the values ​​of the start field, end field, and wait field are 0, 1, and 0, or 0, 1, and 1, 1, and 0, or 1, 1, and 1 respectively, it indicates that the target state of the I2C communication between slave node n and peripheral m is the end state; if the values ​​of the start field, end field, and wait field are 0, 0, and 0 respectively, it is considered that this downlink frame does not indicate the target state of I2C communication. Furthermore, the fifth byte of this downlink frame can be used to carry the data to be written.

[0235] In this embodiment, the operation object field in the downlink frames S1' to S8' is set to 1, the read field to 0, the write field to 1, the mode field to 0, and the slave node identifier field to set the identifier of slave node n. Furthermore, the fifth byte of downlink frame 1' carries the data to be written, 1', and the values ​​of the start field, end field, and wait field in downlink frame 1' are 1, 0, and 0, respectively. The fifth byte of downlink frames 2' and n' has a default value, and the values ​​of the start field, end field, and wait field in downlink frames 2' and n' can be 0, 0, 1 or 1, 0, 1, respectively. The fifth byte of downlink frame m has a default value, and the values ​​of the start field, end field, and wait field in downlink frame m can be 0, 1, 0, or 0, 1, 1, or 1, 1, 0, or 1, 1, 1, respectively.

[0236] In some implementations, when the downlink frame indicates that the I2C communication status between slave node n and peripheral m is in a waiting state or an end state, the values ​​of the operation object field, read field, write field, and mode field in the downlink frame can also be default values.

[0237] The frame structure of the uplink frame involved in S1' to S8' of this embodiment can be as shown in Figure 17. This uplink frame includes 8 bytes. The frame structure of this uplink frame differs from that shown in Figure 10 in that the last bit of the second byte of this uplink frame is used to carry I2C indication information (i.e., I2C ACK). This I2C indication information is used to indicate whether the slave node n has received the I2C acknowledgment information from the peripheral m. The I2C acknowledgment information indicates that the peripheral m has successfully received the I2C signal from the slave node n. When the I2C acknowledgment information field is 1, it indicates that the slave node n has received the I2C acknowledgment information from the peripheral m; when the I2C acknowledgment information field is 0, it indicates that the slave node n has not received the I2C acknowledgment information from the peripheral m. When node n does not receive an I2C acknowledgment from peripheral m, two scenarios are possible: ① Node n receives an I2C denial message from peripheral m, indicating that peripheral m has not successfully received the I2C signal from node n; ② Node n does not receive an I2C denial message from peripheral m, meaning that node n has not received any feedback from peripheral m regarding the I2C signal reception result. Furthermore, the third byte of the uplink frame shown in Figure 17 differs from that in Figure 10. When the I2C indication field is 1, the third byte carries the read data; when the I2C indication field is 0, the first bit (NACK field) and the second bit (wait field) of the third field carry information indicating whether node n has received the I2C denial message from peripheral m. A NACK field value of 0 indicates that node n has not received the I2C denial message from peripheral m; a NACK field value of 1 indicates that node n has received the I2C denial message from peripheral m. When the wait field is 0, it indicates that the slave node n has received an I2C denial message from the peripheral m; when the wait field is 1, it indicates that the slave node n has not received an I2C denial message from the peripheral m.

[0238] In this embodiment, the frame number and frame type of the uplink frames in S1' to S8' are the same as the frame number and frame type of their corresponding downlink frames. The operation object field of the uplink frame is set to 1, and the slave node identifier field carries the identifier of the slave node n. The frame acknowledgment field of uplink frame 1' and uplink frame 2' is set to 1, the I2C indication information field is set to 0, and the NACK field is set to 0 and the wait field is set to 1. In one example, the frame acknowledgment field of uplink frame n' and uplink frame m is set to 1, the I2C indication information field is set to 1, and the third byte is set to the default value. In another example, the frame acknowledgment field of uplink frame n' and uplink frame m is set to 1, the I2C indication information field is set to 0, and the NACK field and the wait field are both set to 0. In addition, when a slave node initiates an interrupt, the sixth and seventh bytes of the aforementioned one or more uplink frames can also carry interrupt-related information.

[0239] In some implementations, before instructing the master node to perform a read or write operation, the master controller can configure I2C communication-related information for the slave node, such as configuring the I2C communication speed, whether I2C transmission is enabled, and the read / write mode. For example, the master controller can configure the I2C communication between the slave node n and the peripheral by writing relevant information to the slave node n's I2C configuration register (e.g., 0x16). For instance, the functions of the 8 bits in the I2C configuration register are shown in Table 3. The information written to the first two bits of the I2C configuration register indicates the I2C communication rate, the information written to the third bit indicates the read / write mode, and the information written to the first three bits indicates whether the retransmission mode is enabled.

[0240] Table 3

[0241] Figure 18 illustrates another schematic diagram of the communication process involved in performing a write operation on the register of a peripheral connected to a slave node according to an embodiment of this application. In an I2C communication, if the master controller needs to write two bytes of data to the register of the peripheral m connected to the slave node n, the downlink frame sent by the master node to the slave node n can carry two bytes of data. The communication process between the master controller, the master node, the slave node n, and the peripheral m is shown in Figure 18. The communication process in parts A to D of Figure 18(a) corresponds to the communication process in parts A to D of Figure 18(b). Furthermore, if a register can store one byte of data, the aforementioned two bytes of data can be data written to two registers with adjacent addresses. As mentioned earlier, generally, one peripheral is connected to one register. In this case, the aforementioned two registers can be the registers connected to two peripherals with adjacent addresses. Then, register address 6 in Figure 18 can be the I2C address of either of the aforementioned two peripherals. For example, it can be the peripheral I2C address with the smaller value among the two peripheral I2C addresses. Furthermore, when a peripheral is connected to a register, writing two bytes of data to the register of peripheral m connected to slave node n can be understood as writing one byte of data to both the register of peripheral m and the register of peripheral m+1. In some implementations, when a peripheral is connected to multiple registers, writing two bytes of data to the register of peripheral m connected to slave node n can be understood as writing one byte of data to each of the two registers of peripheral m.

[0242] The difference from the embodiment shown in Figure 15 is that after the master node receives 1 byte of data to be written (e.g., data to be written 1'), the master node first buffers the data to be written 1' and sends an AS acknowledgment signal 3 to the master controller. After the master controller receives the acknowledgment signal 3, it sends another 1 byte of data to be written (e.g., data to be written 2') to the master node. After the master node receives 2 bytes of data to be written, it sends a downlink frame 1' carrying two bytes of data (i.e., data to be written 1' and data to be written 2') to the slave node. When peripheral m is connected to two or more registers, after the slave node n receives the downlink frame 1', it sends the data to be written 1' and data to be written 2' to peripheral m in sequence. After receiving the AS acknowledgment signal d from peripheral m, the slave node n sends an uplink frame n to the master node to indicate that the data has been received by peripheral m. With each peripheral m connected to a register, the communication flow in part D differs from that shown in Figures 17 and 18 as follows: After receiving downlink frame 1', node n first sends a start signal, I2C address, and write instruction (R / W = 0) signal to peripheral m in sequence. After receiving the AS acknowledgment signal a, the master controller continues to send the register address signal. After receiving the AS acknowledgment signal b, node n sends the data to be written 1' to peripheral m. After receiving the acknowledgment signal c from peripheral m, it first sends the register address signal to peripheral m+1 in sequence. The system sends a start signal, I2C address, and write instruction (R / W=0) signal. After receiving an acknowledgment signal from the AS of peripheral m+1, slave node n continues to send a register address signal (which can carry the I2C address of peripheral m+1) to peripheral m+1. After receiving the acknowledgment signal from the AS of peripheral m+1, slave node n sends the data to be written, 2', to peripheral m+1. After receiving the acknowledgment signal from the AS of peripheral m+1, slave node n sends an uplink frame n' to the master node to indicate that the data has been received by the peripheral. After receiving the uplink frame n, the master node sends an acknowledgment signal 4 to the master controller, indicating that the master node has received the data to be written, 1' and 2'. After receiving the acknowledgment signal 4, the master controller sends an end signal to the master node to end the data writing process. The master node controls slave node n to end the data writing process according to the end signal sent by the master controller. Other contents not described in detail in this embodiment can be referred to the description in Figure 15, and will not be repeated here.

[0243] In some implementations, the frame structure and content of downlink frame 1 in this embodiment can be the same as those of downlink frame 1 in the embodiment shown in FIG15; the frame structure and content of uplink frame 1 in this embodiment can be the same as those of uplink frame 1 in the embodiment shown in FIG15.

[0244] The frame structure of the downlink frames involved in S1' to S7' in this embodiment is shown in Figure 19. This downlink frame includes 8 bytes. The difference from the frame structure shown in Figure 16 is that the sixth byte in this downlink frame is used to carry the data to be written.

[0245] In this embodiment, the operation object field in the downlink frames involved in S1' to S7' has a value of 1, the read field has a value of 0, the write field has a value of 1, the mode field has a value of 1, and the slave node identifier field sets the identifier of slave node n. Furthermore, the fifth and sixth bytes of downlink frame 1' carry the data to be written 1' and the data to be written 2', and the values ​​of the start field, end field, and wait field in downlink frame 1' are 1, 0, and 0, respectively. The fifth and sixth bytes of downlink frames 2' and n' are default values, and the values ​​of the start field, end field, and wait field in downlink frames 2' and n' can be 0, 0, 1 or 1, 0, 1, respectively. The fifth and sixth bytes of downlink frame m are default values, and the values ​​of the start field, end field, and wait field in downlink frame m can be 0, 1, 0, or 0, 1, 1, or 1, 1, 0, or 1, 1, 1, respectively.

[0246] In some implementations, when the downlink frame indicates that the I2C communication status between slave node n and peripheral m is in a waiting state or an end state, the values ​​of the operation object field, read field, write field, and mode field in the downlink frame can also be default values.

[0247] The frame structure of the uplink frame involved in S1' to S7' of this embodiment can be shown in Figure 20(a), which includes 8 bytes. The frame structure of this uplink frame differs from that shown in Figure 17 in that the sixth byte in this uplink frame is used to carry data read from the operation object; the seventh byte is used to carry verification information, which is used to verify the data carried in the sixth byte; and the eighth byte is a reserved byte. In this embodiment, the specific content carried by the other fields in the uplink frame can be referred to the description of the uplink frame in Figure 9, and will not be repeated here.

[0248] In some other implementations, the frame structure of the uplink frames in S1' to S7' of this embodiment is shown in Figure 20(b), and the uplink frame includes 8 bytes. The frame structure of this uplink frame differs from that shown in Figure 20(b) in that the third and fourth bytes in this uplink frame are used to carry data read from the operation object; the fifth to seventh bytes are used to carry verification information, wherein the verification information carried by the fifth and sixth bytes is used to verify the information carried in the first three bytes, and the verification information carried by the seventh byte is used to verify the data carried in the fourth byte.

[0249] In this embodiment, the frame number and frame type of the uplink frame are the same as those of its corresponding downlink frame. The operation object field of the uplink frame is set to 1, and the slave node identifier field carries the identifier of the slave node n. The frame acknowledgment field of uplink frame 1' and uplink frame 2' is set to 1, the I2C indication information field is set to 0, the NACK field is set to 0, and the wait field is set to 1. The frame acknowledgment field of uplink frame n', uplink frame n, and uplink frame m is set to 1, the I2C indication information field is set to 1, and the third and sixth bytes are set to default values.

[0250] When each I2C communication requires writing more than two bytes of data to the target object, the downlink frame transmitted between the master and slave nodes can include a downlink frame carrying 1 byte of data, i.e., the downlink frame adopts the frame structure shown in Figure 16; or it can include a downlink frame carrying 2 bytes of data, i.e., the downlink frame adopts the frame structure shown in Figure 19. A more specific implementation of the communication between the master and slave nodes can be found in the descriptions in Figures 15 and 18, which will not be repeated here.

[0251] Figures 21 and 22 illustrate the communication flow involved when performing a read operation on the register of a peripheral connected to a slave node according to an embodiment of this application. In an I2C communication, if the master controller needs to read one byte of data (such as data 1) from the register of the peripheral m connected to the slave node n, the communication flow between the master controller, the master node, the slave node n, and the peripheral m is shown in Figures 21 and 22. The address write and communication flows A to E in Figure 21 correspond to the address write and communication flows A to F in Figure 22, respectively. Furthermore, register address 7 is the I2C address of the peripheral m connected to the slave node n.

[0252] It should be noted that the communication flow shown in Figures 21 and 22 differs from that in Figure 9 in that, before the master controller sends the signal indicating the I2C address of peripheral m and the read instruction to the master node, it needs to write the I2C address of peripheral m into the register of slave node n. This allows slave node n to confirm the peripheral m that needs to be operated on. The communication flow between the master controller and the master node writes the I2C address of peripheral m into the register of slave node n through the address writing part. The specific implementation of this part can be referred to the communication flow in part A of Figure 15 and the relevant descriptions of S1 to S2, which will not be repeated here. The frame structure and content of downlink frame 1 and uplink frame 1 involved in this part are the same as those of downlink frame 1 and uplink frame 1 in Figure 15, respectively.

[0253] After the master node receives uplink frame 1, it sends AS acknowledgment signal 3 to the master controller. After the master controller receives acknowledgment signal 3, it sends an end signal to the master node to indicate the end of this I2C communication. Further, the remaining communication process of part A is executed, specifically: the master controller sends a start signal to the master node to initiate the process of reading data from the registers of peripheral m of slave node n. It should be noted that before the master controller sends the start signal of part A, the master controller indicates the target slave node to the master node (e.g., sends the slave node number corresponding to slave node n to the master node), and the peripheral to be operated on is the slave node (e.g., indicates the operation to be performed on the peripheral of the target slave node through 1 bit). After the master node confirms receipt of the signal indicating the target slave node and the peripheral to be operated on, the subsequent process of part A is executed, specifically including:

[0254] The master controller sequentially sends a start signal, an I2C address, and a write instruction (R / W=0) signal. After receiving the AS's acknowledge signal 1, the master controller continues to send a register address signal, which carries the peripheral's I2C address. After receiving the master node's AS's acknowledge signal 4, the master controller continues to send a data signal, which carries register address 7 (i.e., the peripheral m's I2C address).

[0255] After the master node receives the signal indicating bearer register address 7, the following steps are performed between the master node and slave node n, between slave node n and peripheral device m, and between the master node and the master controller:

[0256] S3, the master node sends downlink frame 1' to the slave node n.

[0257] In this downlink frame 1', the mode is indicated as value 1, the operand as value 2, and a write operation is performed on the operand. Furthermore, downlink frame 1' indicates that the I2C communication between node n and peripheral m is in the initial state ("start"). Downlink frame 1' also carries data, specifically register address 7.

[0258] After receiving downlink frame 1', the slave node n sends a start signal to peripheral m and sends a response frame to downlink frame 1', similar to uplink frame 1. Uplink frame 1' indicates that the slave node n acknowledges receipt of the control information in downlink frame 1' ("acknowledgment"). Uplink frame 1' also indicates that the slave node n is waiting for peripheral m to return I2C acknowledgment information (such as an AS acknowledgment signal) and / or I2C denial information (such as a NAS acknowledgment signal) ("waiting").

[0259] It should be noted that after the slave node receives downlink frame 1', the following communication process is executed between the slave node n and the peripheral m: the slave node n sends the I2C address and write instruction (R / W=0) signal to the peripheral m; the peripheral m sends the AS acknowledge signal a to the slave node n; the slave node n sends the signal indicating register address 7 to the peripheral m; the peripheral m sends the AS acknowledge signal b to the slave node n; the slave node n sends the data to be written 1' to the peripheral m; and the peripheral m sends the AS acknowledge signal c to the slave node n.

[0260] S4, the master node sends downlink frame 2' to the slave node n, which indicates that the I2C communication status between the slave node n and the peripheral m is a waiting state ("waiting").

[0261] S5, send uplink frame 2' from node n to the master node.

[0262] The frame structure and content of uplink frame 2' can be the same as those of uplink frame 1'.

[0263] Furthermore, the master node sends downlink frame n' to the slave node n. The frame structure and content of downlink frame n' can be the same as those of downlink frame 2'.

[0264] S4 is executed when or after receiving the acknowledgment signal c from peripheral m from node n.

[0265] S6, send uplink frame n' from node n to the master node.

[0266] In some implementations, prior to S4, the interaction process between the master node and slave node n includes the following:

[0267] For example, uplink frame n' indicates that node n has acknowledged receiving control information in downlink frame n', and that node n has received I2C acknowledgment information from peripheral m, which indicates that peripheral m has received register address 7.

[0268] For example, the frame structure of the downlink frames involved in S3 to S4 can be as shown in Figure 16. Specifically, in S3 to S4, the operation object field of the downlink frame has a value of 1, the read field has a value of 0, the write field has a value of 1, the mode field has a value of 0, and the slave node identifier field sets the identifier of the slave node n. In addition, the fifth byte of downlink frame 1' carries register address 7, and the values ​​of the start field, end field, and wait field in downlink frame 1' are 1, 0, and 0, respectively. It should be understood that register address 7 is the data to be written to the peripheral device of the slave node. The values ​​of the start field, end field, and wait field in downlink frame 2' and downlink frame n' can be 0, 0, 1 or 1, 0, 1, respectively, and the fifth byte in downlink frame 2' and downlink frame n' has a default value.

[0269] After receiving uplink frame n', the master node sends an AS acknowledgment signal 6 to the master controller, indicating that the master node has received register address 7. Upon receiving acknowledgment signal 6, the master controller sends a start signal, along with the I2C address and read instruction signals, to the master node to initiate the process of reading data from the peripheral's register. Further, the following steps are performed between the master node and slave node n, between slave node n and peripheral m, and between the master node and the master controller:

[0270] S1', the master node sends downlink frame a to the slave node n.

[0271] The downlink frame 'a' indicates that the mode is value 1, the target is value 2, and a read operation is performed on the target.

[0272] In some implementations, downlink frame a can indicate that the I2C communication between slave node n and peripheral m is in a start state (“start”).

[0273] S2', the node n sends uplink frame a to the master node.

[0274] The uplink frame a indicates that the slave node n acknowledges receipt of the control information in the downlink frame a (“acknowledgment”). The uplink frame a also indicates that the slave node n is in a state of waiting for the peripheral m to send back I2C acknowledgment information and / or I2C denial information (“waiting”).

[0275] S3', the master node sends downlink frame b to the slave node n.

[0276] The downlink frame b indicates that the I2C communication between node n and peripheral m is in a waiting state (“waiting”).

[0277] S4', the node n sends uplink frame b to the master node.

[0278] The frame structure and content of uplink frame b can be the same as those of uplink frame a. After transmitting uplink frame b, multiple sets of downlink and uplink frames can be transmitted between the master node and the slave node. The frame structure and content of the downlink frames in each set can be the same as those of downlink frame b, and the frame structure and content of the uplink frames in each set can be the same as those of uplink frame b.

[0279] It should be noted that while executing S1' to S4', the following communication process occurs between slave node n and peripheral device m: slave node n sends a start signal, I2C address, and read instruction (R / W=1) signal to peripheral device m; peripheral device m sends an AS acknowledge signal c to slave node n; peripheral device m sends the read data 1 to slave node n. After slave node n receives data 1, it executes S5'.

[0280] S5', send uplink frame N from node n to the master node.

[0281] The uplink frame N carries data 1. In addition, the uplink frame can also indicate to the slave node n that it has received control information in the downlink frame N, and to the slave node n that it has received I2C acknowledgment information from the peripheral m. The I2C acknowledgment information indicates that the peripheral m has received the I2C address and read instruction signal.

[0282] In this context, downlink frame N is the downlink frame corresponding to uplink frame N, meaning that the frame number and frame type of uplink frame N are the same as those of downlink frame N. Furthermore, the frame structure and content of downlink frame N are the same as or similar to those of downlink frame b.

[0283] After receiving uplink frame N, the master node sends an acknowledgment signal 3 to the master controller. This acknowledgment signal 3 indicates that the master node has received the I2C address and read command signal from the master controller. Upon receiving acknowledgment signal 3, the master controller reads data 1 from the master node. After reading data 1, the master controller sends an acknowledgment signal 4 to the master node. This acknowledgment signal 4 can be NAM, indicating that data reading is complete. After sending acknowledgment signal 3, the master controller continues to send a stop signal to terminate the data reading process. Further, when the master node receives the stop signal from the master controller, it executes step S11.

[0284] S6', the master node sends downlink frame M to slave node n.

[0285] The downlink frame M is used to indicate that the I2C communication between node n and peripheral m has entered the end state.

[0286] After receiving downlink frame M from node n, the slave node sends an acknowledgment signal e and a stop signal to peripheral m to terminate the data writing process. The acknowledgment signal e can be a NAM acknowledgment signal to indicate to peripheral m that data reading is complete. S12 is executed before, after, or during the execution of the stop signal from node n.

[0287] S7', the node n sends an uplink frame M to the master node.

[0288] The uplink frame M indicates that node n has acknowledged receiving the downlink frame M.

[0289] The frame structure of the downlink frames involved in S1' to S7' of this embodiment can be as shown in Figure 16. Specifically, the operation object field in the downlink frame is set to 1, the read field is set to 1, the write field is set to 0, the mode field is set to 0, the slave node identifier field is set to the identifier of the slave node n, and the fifth byte is the default value. In addition, the values ​​of the start field, end field, and wait field in downlink frame a are 0, 0, 0 or 0, 0, 1 or 1, 0, 1 respectively; the values ​​of the start field, end field, and wait field in downlink frame b can be 0, 0, 1 or 1, 0, 1 respectively; the values ​​of the start field, end field, and wait field in downlink frame M can be 0, 1, 0, or 0, 1, 1, or 1, 1, 0, or 1, 1, 1 respectively.

[0290] In some implementations, when the downlink frame indicates that the I2C communication status between slave node n and peripheral m is in a waiting state or an end state, the values ​​of the operation object field, read field, write field, and mode field in the downlink frame can also be default values.

[0291] The frame structure of the uplink frames involved in S1' to S7' of this embodiment can be shown in Figure 17. Specifically, the frame number and frame type of the uplink frame are the same as the frame number and frame type of its corresponding downlink frame. The operation object field of the uplink frame is 1, and the slave node identifier field carries the identifier of the slave node n. The frame acknowledgment field of uplink frame a' and uplink frame b' is 1, the I2C indication information field is 0, the NACK field is 0, and the wait field is 1. In one example, the frame acknowledgment field of uplink frame N' and uplink frame M is 1, the I2C indication information field is 1, and the third byte is the default value. In another example, the frame acknowledgment field of uplink frame N' and uplink frame M is 1, the I2C indication information field is 0, and the NACK field and the wait field are both 0. The frame acknowledgment field of uplink frame N is 1, the I2C indication information field is 1, and the third byte carries the data 1. In addition, when an interrupt is initiated by a slave node, the sixth and seventh bytes of one or more of the aforementioned uplink frames can also carry interrupt-related information.

[0292] Figures 23 and 24 illustrate another schematic diagram of the communication process involved in performing a read operation on the register of a peripheral connected to a slave node according to the embodiments of this application. In an I2C communication, if the master controller needs to read two bytes of data from the register of the peripheral m connected to the slave node n, the uplink frame sent by the slave node n to the master node can carry two bytes of data. The communication process between the master controller, the master node, the slave node n, and the peripheral m is shown in Figures 23 and 24. The address writing and communication processes A to F in Figure 23 correspond to the address writing and communication processes A to F in Figure 24, respectively. Furthermore, if a register can store one byte of data, the aforementioned two bytes of data can be data read from two registers with adjacent addresses. As mentioned earlier, generally, one peripheral is connected to one register. In this case, the aforementioned two registers can be the registers connected to two peripherals with adjacent addresses. Therefore, register address 8 in Figure 23 can be the I2C address of either of the two peripherals, for example, it can be the I2C address with the smaller value among the two I2C addresses. Furthermore, when a peripheral is connected to a register, reading two bytes of data from the register of peripheral m connected to slave node n can be understood as reading one byte of data from both the register of peripheral m and the register of peripheral m+1. In some implementations, when a peripheral is connected to multiple registers, reading two bytes of data from the register of peripheral m connected to slave node n can be understood as reading one byte of data from each of the two registers of peripheral m.

[0293] The difference from the embodiments shown in Figures 21 and 22 is that, when peripheral m is connected to two or more registers, after slave node n reads 1 byte of data (e.g., data 1) from peripheral m, slave node n first buffers data 1 and sends an AS acknowledgment signal d to peripheral m; after sending the acknowledgment signal d, slave node n reads another 1 byte of data (e.g., data 2) from peripheral m. After receiving the two bytes of data, slave node n sends the two bytes of data to the master node through uplink frame N. When peripheral m is connected to a register, the communication process for part D differs from that shown in Figures 23 and 24 in that: after receiving the acknowledgment signal b from the slave node n, the slave node n first sends the start signal, I2C address, and write instruction (R / W=0) signal to the peripheral m+1 in sequence. After receiving the acknowledgment signal AS from the peripheral m+1, the slave node n continues to send the register address signal (which can carry the I2C address of the peripheral m+1) to the peripheral m+1. After receiving the acknowledgment signal AS from the peripheral m+1, the slave node n sends the uplink frame n' to the master node. Furthermore, in the communication process of part E, the difference from that shown in Figures 23 and 24 is that after the slave node n receives data 1 from peripheral m and sends an acknowledgment signal d to peripheral m, the slave node n sends a start signal, an I2C address, and a read instruction (R / W = 1) signal to peripheral m+1 in sequence. After the slave node n receives the acknowledgment signal AS from peripheral m+1, the slave node n reads data 2 from peripheral m+1 and sends an uplink frame N to the master node.

[0294] After receiving uplink frame N, the master node sends an acknowledgment signal 7 to the master controller, indicating that it has received the I2C address and read command signal. Upon receiving acknowledgment signal 3, the master controller reads data 1 and data 2 sequentially from the master node. After reading data 2, the master controller sends a NAM acknowledgment signal 9 and a stop signal to the master node to terminate the data writing process. Based on the stop signal sent by the master controller, the master node controls the slave node n to terminate the data writing process. Other details not described in detail in this embodiment can be found in Figures 21 and 22, and will not be repeated here.

[0295] In some implementations, the frame structure and content of downlink frame 1 in this embodiment can be the same as those of downlink frame 1 in the embodiment shown in FIG22; the frame structure and content of uplink frame 1 in this embodiment can be the same as those of uplink frame 1 in the embodiment shown in FIG22; the frame structure and content of downlink frame 1' in this embodiment can be the same as those of downlink frame 1' in the embodiment shown in FIG22; and the frame structure and content of uplink frame 1' in this embodiment can be the same as those of uplink frame 1' in the embodiment shown in FIG22.

[0296] The frame structure of the downlink frames involved in S1' to S7' of this embodiment can be as shown in Figure 19. Specifically, the operation object field in the downlink frame is set to 1, the read field is set to 1, the write field is set to 0, the mode field is set to 1, the slave node identifier field is set to the identifier of the slave node n, and the fifth and sixth bytes are default values. In addition, the values ​​of the start field, end field, and wait field in downlink frame a are 0, 0, 0 or 0, 0, 1 or 1, 0, 1 respectively; the values ​​of the start field, end field, and wait field in downlink frame b can be 0, 0, 1 or 1, 0, 1 respectively; the values ​​of the start field, end field, and wait field in downlink frame M can be 0, 1, 0, or 0, 1, 1, or 1, 1, 0, or 1, 1, 1 respectively.

[0297] In some implementations, when the downlink frame indicates that the I2C communication status between slave node n and peripheral m is in a waiting state or an end state, the values ​​of the operation object field, read field, write field, and mode field in the downlink frame can also be default values.

[0298] The frame structure of the uplink frames involved in S1' to S7' of this embodiment can be as shown in Figure 20. Specifically, the frame number and frame type of the uplink frame are the same as the frame number and frame type of its corresponding downlink frame. The operation object field of the uplink frame is 1, and the slave node identifier field carries the identifier of the slave node n. The frame acknowledgment field of uplink frame a' and uplink frame b' is 1, the I2C indication information field is 0, the NACK field is 0, and the wait field is 1. In one example, the frame acknowledgment field of uplink frame N' and uplink frame M is 1, the I2C indication information field is 1, and the third byte is the default value. In another example, the frame acknowledgment field of uplink frame N' and uplink frame M is 1, the I2C indication information field is 0, and the NACK field and wait field are both 0. The frame acknowledgment field of uplink frame N is 1, the I2C indication information field is 1, and the third and sixth bytes carry data 1 and data 2, respectively.

[0299] When each I2C communication requires reading more than two bytes of data from the target object, the uplink frame transmitted between the master and slave nodes can include an uplink frame carrying 1 byte of data, i.e., the uplink frame adopts the frame structure shown in Figure 17; alternatively, it can also include an uplink frame carrying 2 bytes of data, i.e., the uplink frame adopts the frame structure shown in Figure 20. A more specific implementation of the communication between the master and slave nodes can be found in the descriptions in Figures 21 to 24, and will not be repeated here.

[0300] It should be noted that in the aforementioned embodiments, there may be no other slave nodes between the master node and slave node n, meaning that downlink and uplink frames are directly transmitted between the master node and slave node n; alternatively, there may be one or more other slave nodes between the master node and slave node n, with downlink frames sent by the master node being forwarded to slave node n via one or more slave nodes, and uplink frames sent by slave node n being forwarded to the master node via one or more slave nodes. When forwarding downlink frames, slave nodes do not change the existing control information in the downlink frames. If a synchronization field exists in the downlink frame, the slave node can use the information in the synchronization field for clock synchronization during forwarding. When forwarding uplink frames, slave nodes do not change the existing control information in the uplink frames, but they can add information they want to report to the master node, such as interrupt-related information, to the uplink frames.

[0301] It should also be noted that the structures of the aforementioned downlink and uplink frames are merely illustrative examples. In actual implementation, downlink frames may also include fields for carrying more bytes of data, and uplink frames may also include fields for carrying more bytes of data. Correspondingly, the mode field may also include more bits to indicate multiple modes used by the downlink or uplink frame to carry different bytes of data.

[0302] Figure 25 shows a schematic flowchart of the communication method provided in an embodiment of this application. This method 1000 can be executed by the audio / video system 100 shown in Figure 1, or it can also be applied to the audio / video system shown in Figure 2. Exemplarily, the master node can be the master node 112 in the aforementioned embodiments, and the first slave node can be the slave node n in the aforementioned embodiments. The first slave node can be a slave node connected to the master node, or one or more slave nodes can be connected between the first slave node and the master node. The method 1000 includes:

[0303] S1010, the master node generates a first downlink frame, which includes first indication information, second indication information, and third indication information. The first indication information indicates whether a write operation is performed on the operation object, the second indication information indicates whether a read operation is performed on the operation object, and the third indication information indicates whether the write operation is in the first mode or the second mode, or whether the read operation is in the first mode or the second mode, or the third indication information is invalid. The first downlink frame includes a first field, which carries the data associated with the operation object. In the first mode, the number of bytes in the first field is n; in the second mode, the number of bytes in the first field is m, where n and m are both positive integers, and n is not equal to m. A first uplink frame is sent, which indicates whether the second slave node has successfully received the first downlink frame. The second slave node is the slave node associated with the operation object.

[0304] In some implementations, n is 1 and m is 2; or n and m can be other positive integers.

[0305] In one example, the first indication information may be the information carried by the write field in the aforementioned embodiments, the second indication information may be the information carried by the read field in the aforementioned embodiments, and the third indication information may be the information carried by the pattern field in the aforementioned embodiments.

[0306] In another example, the first indication information and the second indication information can be carried by the same field. That is, the read field and the write field in the aforementioned embodiments can be merged into the same field, for example, into a 1-bit field, through which the read operation or write operation is indicated to be performed on the operation object.

[0307] In some implementations, the first downlink frame also includes fourth indication information, which indicates that the operation target is the register of the second slave node, or the operation target is the first peripheral connected to the second slave node.

[0308] For example, the fourth instruction information may be the information carried by the operation object field in the foregoing embodiments.

[0309] In some implementations, when the fourth indication information indicates that the operation object is the first peripheral device, the first downlink frame also includes a fifth indication information, which indicates that the state of the I2C communication between the second slave node and the first peripheral device is at least one of the following: start state, wait state, or end state.

[0310] For example, the fifth indication information may be information carried by at least one of the start field, end field, and wait field in the foregoing embodiments.

[0311] In some implementations, the first downlink frame also includes sixth indication information, which indicates the address of the operation object. When the third indication information indicates the second mode, the sixth indication information is the address of the operation object corresponding to a byte of data in the data associated with the operation object.

[0312] For example, when the operation target is the register of the slave node, the sixth indication information can be the information carried by the register address field in the aforementioned embodiment. In this case, the first downlink frame can be downlink frame 1 in Figures 4 and 6, or it can be downlink frame a in Figures 9 and 11. When the operation target is the register connected to the peripheral of the slave node, the sixth indication information can be the information carried by the data field (fifth byte) in the aforementioned embodiment. In this case, the first downlink frame can be downlink frame 1 in Figures 15 and 18, or it can be downlink frame 1' in Figures 22 and 24.

[0313] S1020, the master node sends the first downlink frame.

[0314] After the first slave node receives the first downlink frame, S1030 is executed.

[0315] S1030, the first slave node sends a first uplink frame, which indicates whether the second slave node has successfully received the first downlink frame. The second slave node is the slave node associated with the operation object.

[0316] For example, the first uplink frame indicates to the second slave node whether it has successfully received the first downlink frame via feedback information. For example, this feedback information may be the information carried in the frame acknowledgment field of the foregoing embodiments.

[0317] In some implementations, when the target of the operation is a first peripheral device, the first uplink frame also includes first information, which indicates whether the second slave node has received I2C acknowledgment information from the first peripheral device. When the second indication information indicates that a read operation is performed on the target of the operation, and the first information indicates that the second slave node has received I2C acknowledgment information, the first uplink frame also includes a second field, which carries data associated with the target of the operation. When the first information indicates that the second slave node has not received I2C acknowledgment information, the first uplink frame also includes second information, which indicates that the second slave node has received I2C denial information from the first peripheral device, or that the second information indicates that the second slave node is in a waiting state.

[0318] For example, the first information may be the information carried in the I2C confirmation information field in the foregoing embodiments, and the second information may be the information carried in the NACK field and / or the wait field in the foregoing embodiments.

[0319] In some implementations, the second slave node and the first slave node are the same slave node. The method further includes: when the fifth indication information indicates that the I2C communication state is a start state and a waiting state, the first slave node controls the I2C communication to a waiting state; or, when the fifth indication information indicates that the I2C communication state is a start state, a waiting state, and an end state, the first slave node controls the I2C communication to an end state.

[0320] For example, when both the start and wait fields are 1, and the end field is 0, the second slave node determines that the target state for I2C communication indicated by the master node is the wait state; when all three fields (start, wait, and end) are 1, the second slave node determines that the target state for I2C communication indicated by the master node is the end state. In other words, if the end field is 1, the second slave node determines that the target state for I2C communication indicated by the master node is the end state, regardless of the values ​​of the start and wait fields; if the end field is 0 and the wait field is 1, the second slave node determines that the target state for I2C communication indicated by the master node is the wait state, regardless of the value of the start field.

[0321] In some implementations, when the second indication information indicates a read operation on the operation object, the first uplink frame also includes data associated with the operation object. Specifically, when the third indication information indicates a first mode or the third indication information is invalid, the number of bytes of data associated with the operation object carried by the first uplink frame is n; when the third indication information indicates a second mode, the number of bytes of data associated with the operation object carried by the first uplink frame is m.

[0322] The invalid third indication information means that when the first downlink frame indicates that a read operation is to be performed on the operation object, regardless of the value of the third indication information, the field used to carry the data in the first uplink frame is n bytes.

[0323] In implementation method one, when the first downlink frame indicates a write operation on the target object, and the target object is the register of the second slave node, if the third indication information indicates that the write operation mode is the first mode, then the first downlink frame also carries n bytes of data. For example, taking n as 1, the first downlink frame can be downlink frame 1 in Figure 4, or downlink frame 1 or downlink frame 2 in Figure 8. If the third indication information indicates that the write operation mode is the second mode, then the first downlink frame also carries m bytes of data. For example, taking m as 2, the first downlink frame can be downlink frame 1 in Figure 6.

[0324] In implementation method two, when the first downlink frame indicates a read operation on the target object, and the target object is the register of the second slave node, if the third indication information indicates that the read operation mode is the first mode, then the first uplink frame also carries n bytes of data. For example, taking n as 1, the first uplink frame can be uplink frame a in Figure 9, or uplink frame a or uplink frame b in Figure 13. If the third indication information indicates that the write operation mode is the second mode, then the first downlink frame also carries m bytes of data. For example, taking m as 2, the first uplink frame can be uplink frame a in Figure 11.

[0325] In implementation method three, when the first downlink frame indicates that a write operation is to be performed on the operation object, and the operation object is the register of the peripheral connected to the second slave node, before the master node sends the data to be written to the first slave node through the first downlink frame, the method includes: the master node sending a second downlink frame to the first slave node, the second downlink frame being used to write the I2C address of the first peripheral into the register of the second slave node.

[0326] For example, the first downlink frame can be downlink frame 1' in Figure 15 or Figure 18, and the second downlink frame can be downlink frame 1 in Figure 15 or Figure 18. In this case, the first uplink frame can be uplink frame 1' in Figure 15 or Figure 18.

[0327] In some implementations, specifically implementation three, the method further includes: the first slave node sending a third uplink frame to the master node, the third uplink frame being used to confirm that the second slave node has received the second downlink frame. Further, the master node sending the first downlink frame to the first slave node includes: sending the first downlink frame after the master node receives the third uplink frame. Exemplarily, the third uplink frame can be uplink frame 1 in Figure 15 or Figure 18.

[0328] In some implementations, specifically implementation three, the first downlink frame also indicates that the I2C communication between the second slave node and the first peripheral is in the initial state.

[0329] In some implementations, specifically for implementation three, after receiving the first uplink frame, the method further includes: the master node sending a third downlink frame, which indicates that the I2C communication between the second slave node and the first peripheral is in a waiting state. For example, the third downlink frame can be downlink frame 2' or downlink frame n' as shown in Figure 15 or Figure 18.

[0330] In some implementations, specifically implementation three, the method further includes: the master node sending a fourth downlink frame to the first slave node, the fourth downlink frame indicating the end of the write operation. For example, the fourth downlink frame can be downlink frame m as shown in Figure 15 or Figure 18.

[0331] In conjunction with implementation method three, if the third indication information indicates that the write operation mode is the first mode, then the first downlink frame also carries n bytes of data. For example, if n is 1, the first downlink frame can be downlink frame 1 in Figure 15. If the third indication information indicates that the write operation mode is the second mode, then the first downlink frame also carries m bytes of data. For example, if m is 2, the first downlink frame can be downlink frame 1 in Figure 18. It should be understood that in this implementation method, the first downlink frame does not carry information indicating the address of the operation object; that is, the first downlink frame does not carry the register address.

[0332] In implementation method four, when the first downlink frame indicates that a read operation is to be performed on the operation object, and the operation object is the register of the peripheral connected to the second slave node, before the master node sends the first downlink frame indicating the read operation to the first slave node, the method includes: the master node sending a second downlink frame to the first slave node, the second downlink frame being used to write the I2C address of the first peripheral into the register of the second slave node.

[0333] For example, the first downlink frame can be downlink frame a in Figure 22 or Figure 24, and the second downlink frame can be downlink frame 1 in Figure 15 or Figure 18. In this case, the first uplink frame can be uplink frame a in Figure 15 or Figure 18.

[0334] In some implementations, specifically for implementation method four, the method further includes: the first slave node sending a third uplink frame to the master node, the third uplink frame being used to confirm that the second slave node has received the second downlink frame.

[0335] In some implementations, specifically for implementation four, after the master node receives the third uplink frame, the method further includes: the master node sending a fifth downlink frame to the first slave node. The fifth downlink frame indicates that the I2C communication between the second slave node and the first peripheral is in a state of initiation, and indicates the I2C address of the first peripheral. For example, the fifth downlink frame can be downlink frame 1' as shown in Figure 22 or Figure 24.

[0336] In some implementations, specifically implementation four, the method further includes: the first slave node sending a fourth uplink frame to the master node. This fourth uplink frame confirms that the second slave node has received the fifth downlink frame, and indicates that the first peripheral device has not received I2C-related information. For example, the I2C-related information may be a signal indicating a register address, and the fourth uplink frame may be uplink frame 1' as shown in Figure 22 or Figure 24.

[0337] In some implementations, specifically for implementation four, before the master node sends the first downlink frame instructing the first slave node to perform a read operation, the method further includes: the master node sending a sixth downlink frame to the first slave node. This sixth downlink frame indicates that the I2C communication between the second slave node and the first peripheral device is in a waiting state. For example, after receiving the fourth uplink frame, the master node sends the sixth downlink frame to the first slave node. This sixth downlink frame can be downlink frame 2' or n' as shown in Figure 22 or Figure 24.

[0338] In some implementations, for implementation method four, the master node sends a first downlink frame to the first slave node, including: after the master node receives the second uplink frame, it sends the first downlink frame, wherein the second uplink frame indicates that the first peripheral has received I2C related information, and the I2C related information can be a signal indicating the register address, and the second uplink frame can be the uplink frame n' in Figure 22 or Figure 24.

[0339] In some implementations, specifically for implementation four, after receiving the first uplink frame, the method further includes: the master node sending a seventh downlink frame, which indicates that the I2C communication between the second slave node and the first peripheral is in a waiting state. For example, the seventh downlink frame can be downlink frame b in Figure 22 or Figure 24.

[0340] In some implementations, specifically implementation four, the method further includes: the first slave node sending a fifth uplink frame to the master node, the fifth uplink frame including the read data. For example, the fifth uplink frame can be uplink frame N as shown in Figure 22 or Figure 24.

[0341] In some implementations, specifically implementation four, the method further includes: the master node sending a fourth downlink frame to the first slave node, the fourth downlink frame indicating the end of the read operation. For example, the fourth downlink frame can be downlink frame M as shown in Figure 22 or Figure 24.

[0342] The communication method provided in this application embodiment can complete the writing or reading of multiple bytes of data in the first downlink frame transmission cycle, which helps to improve data reading and writing efficiency, thereby helping to improve the initialization speed of the slave node and reduce the overall power consumption of the audio and video system. In addition, the first downlink frame can be compatible with multiple modes, without the need to design different frame structures for different bytes of data, and the master node and slave node do not need to adopt different processing methods for different frame structures, which helps to reduce the complexity of master nodes and slave nodes in the audio and video system when processing transmission frames.

[0343] This application provides a data transmission structure for information transmission between a master node and a second slave node in an audio / video system. The second slave node is associated with an operation object. The data transmission structure carries first indication information, second indication information, and third indication information. The first indication information indicates whether a write operation is performed on the operation object; the second indication information indicates whether a read operation is performed on the operation object; and the third indication information indicates whether the write operation is in the first or second mode, or whether the read operation is in the first or second mode, or whether the third indication information is invalid. The data transmission structure includes a first field, which carries data associated with the operation object. In the first mode, the number of bytes in the first field is n; in the second mode, the number of bytes in the first field is m, where n and m are both positive integers, and n is not equal to m.

[0344] Specifically, the data transmission structure can be the downlink frame in the aforementioned embodiments.

[0345] For example, the first field can be a field used to carry data in the foregoing embodiments, such as the field corresponding to the fifth byte in Figure 5 or Figure 16, or the field corresponding to the fifth and sixth bytes in Figure 7 or Figure 19.

[0346] In some implementations, the data transmission structure also includes a third field, which is used to carry third indication information.

[0347] For example, the third field can be the pattern field in the foregoing embodiments, such as the field corresponding to the first bit of the third byte in Figures 5, 7, 16 or 19.

[0348] In some implementations, the data transmission structure also includes a fourth field, which is used to carry the first indication information and / or the second indication information.

[0349] For example, the fourth field may include the read field and / or write field in the foregoing embodiments, wherein the read field is the field corresponding to the second bit of the third byte in Figures 5, 7, 16 or 19; and the write field is the field corresponding to the third bit of the third byte in Figures 5, 7, 16 or 19.

[0350] In some implementations, the data transmission structure also includes a fifth field, which carries fourth indication information. The fourth indication information indicates that the operation object is the register of the second slave node, or the operation object is the first peripheral connected to the second slave node.

[0351] For example, the fifth field can be the operation object field in the foregoing embodiments, such as the field corresponding to the 8th bit of the first byte in Figures 5, 7, 16 or 19.

[0352] In some implementations, the data transmission structure also includes a sixth field, which carries fifth indication information. The fifth indication information indicates that the state of the I2C communication between the second slave node and the first peripheral is at least one of the following: start state, wait state, or end state.

[0353] For example, the sixth field may include at least one of the start field, end field, or wait field in the foregoing embodiments, wherein the start field is the field corresponding to the first bit of the fourth byte in Figure 16 or Figure 19; the end field is the field corresponding to the second bit of the fourth byte in Figure 16 or Figure 19; and the wait field is the field corresponding to the third bit of the fourth byte in Figure 16 or Figure 19.

[0354] In some implementations, the data transmission structure also includes a seventh field, which carries a sixth indication information, indicating the address of the object being operated on.

[0355] In one example, when the operation target is a slave node's register, the seventh field can be a register address field, such as the field corresponding to the fourth byte shown in Figure 5 or Figure 7.

[0356] In another example, when the operation target is the register of a peripheral connected to the slave node, the seventh field can be a field used to carry data, such as the field corresponding to the fifth byte in Figure 16 or Figure 19.

[0357] In some implementations, the data transmission structure also includes an eighth field, which is used to carry the identifier of the second slave node.

[0358] For example, the eighth field can be a slave node identification field, such as the field corresponding to the first 6 bits of the second byte in Figures 5, 7, 16, or 19.

[0359] In some implementations, the data transmission structure also includes a check field, which carries check information used to verify the information carried by the first seven bytes.

[0360] This application embodiment also provides a data transmission structure for information transmission between a master node and a second slave node in an audio-visual system. The second slave node is associated with an operation object, which is the object on which the master node performs read or write operations. The data transmission structure is used to carry feedback information, which indicates whether the second slave node has successfully received a first downlink frame. The first downlink frame indicates that a read or write operation is performed on the operation object.

[0361] Specifically, the data transmission structure can be the uplink frame in the aforementioned embodiments.

[0362] In some implementations, the data transmission structure also includes a ninth field, which carries third information indicating that the operation target is the register of the second slave node, or the operation target is the first peripheral connected to the second slave node.

[0363] For example, the ninth field can be the operation object field in the foregoing embodiments, such as the field corresponding to the last bit of the first byte in Figures 10, 12, 17 or 20.

[0364] In some implementations, the data transmission structure includes a second field; when the operation object is the register of the second slave node, the second field is used to carry the data associated with the operation object; when the operation object is the first peripheral connected to the second slave node, and the second slave node receives I2C acknowledgment information from the first peripheral, the second field is used to carry the data associated with the operation object; or, when the operation object is the first peripheral connected to the second slave node, and the second slave node has not received I2C acknowledgment information from the first peripheral, the second field is used to carry second information, the second information indicating that the second slave node has received I2C denial information from the first peripheral; or the second information indicating that the second slave node is in a waiting state.

[0365] For example, the second field can be the (read) data field in the foregoing embodiments, such as the field corresponding to the third byte in Figures 10, 12, 17 or 20.

[0366] In some implementations, the data transmission structure also includes a thirteenth field, which carries data associated with the operation object, or, alternatively, carries interrupt-related information.

[0367] For example, the thirteenth field can be the field corresponding to the sixth byte in Figure 10, Figure 12, Figure 17 or Figure 20; or, the thirteenth field can also be the field corresponding to the sixth and seventh bytes in Figure 10, Figure 12, Figure 17 or Figure 20.

[0368] In some implementations, the data transmission structure also includes a tenth field, which carries first information indicating whether the second slave node has received I2C acknowledgment information.

[0369] For example, the tenth field can be the I2C confirmation information field in the aforementioned embodiments, such as the field corresponding to the 8th bit of the second byte in Figures 10, 12, 17 or 20.

[0370] In some implementations, the data transmission structure also includes an eleventh field, which is used to carry feedback information.

[0371] For example, the eleventh field can be the frame confirmation field in the foregoing embodiments, such as the field corresponding to the 7th bit of the second byte in Figures 10, 12, 17 or 20.

[0372] In some implementations, the data transmission structure also includes a twelfth field, which carries the identifier of the second slave node.

[0373] For example, the twelfth field can be the node identification field in the foregoing embodiments, such as the field corresponding to the first 6 bits of the second byte in Figures 10, 12, 17 or 20.

[0374] In some implementations, the data transmission structure also includes a first check field and a second check field. The first check field carries check information used to check the information carried by the first three bytes, and the second check field is used to check the information carried by the sixth byte. Alternatively, the second check field is used to check the information carried by the sixth and seventh bytes.

[0375] The communication method and the frame structure of the transmission frames involved in the communication process have been described in detail above. In the various embodiments of this application, unless otherwise specified or logically conflicting, the terminology and / or descriptions between the embodiments are consistent and can be referenced mutually. Technical features in different embodiments can be combined to form new embodiments based on their inherent logical relationships.

[0376] The methods provided by the embodiments of this application have been described in detail above with reference to Figures 1 to 25. The apparatus provided by the embodiments of this application will now be described in detail with reference to Figures 26 and 27. It should be understood that the descriptions of the apparatus embodiments correspond to the descriptions of the method embodiments; therefore, any content not described in detail can be referred to the method embodiments above, and for the sake of brevity, will not be repeated here.

[0377] Figure 26 shows a schematic block diagram of a communication device 2000 provided in an embodiment of this application. The device 2000 may include units for executing the methods described in the foregoing embodiments. Furthermore, each unit in the device 2000 implements a corresponding process of the above method embodiments. The device 2000 includes a transceiver unit 2010, which can be used to implement corresponding data acquisition or transmission / reception functions. The device 2000 also includes a processing unit 2020, which can be used to implement corresponding processing functions.

[0378] Optionally, the device 2000 further includes a storage unit, which can be used to store instructions and / or data. The processing unit 2020 can read the instructions and / or data in the storage unit so that the device can perform the relevant actions in the aforementioned method embodiments.

[0379] It should be understood that the specific process of each unit performing the above-mentioned corresponding steps has been described in detail in the above method embodiments, and will not be repeated here for the sake of brevity.

[0380] It should also be understood that the device 2000 described herein is embodied in the form of a functional unit. The terms “module” or “unit” may refer to application-specific ASICs, electronic circuits, processors (e.g., shared processors, proprietary processors, or group processors) and memory for executing one or more software or firmware programs, integrated logic circuits, and / or other suitable components that support the described functions.

[0381] The apparatus in this embodiment has the function of implementing the corresponding steps in the aforementioned method. The function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above functions; for example, the transceiver unit 2010 can be replaced by a transceiver, and other units, such as the processing unit, can be replaced by a processor, used to execute the relevant processing operations in each method embodiment.

[0382] For example, when the device 2000 is used to perform the steps performed by the slave node, the transceiver unit 2010 and the processing unit 2020 can be chips or circuits in the slave node; when the device 2000 is used to perform the steps performed by the master node, the transceiver unit 2010 and the processing unit 2020 can be chips or circuits in the master node.

[0383] In the specific implementation process, the units in the above devices can be fully or partially integrated together, or they can be implemented independently. In one implementation, these units are integrated together and implemented in the form of a system-on-a-chip (SoC).

[0384] Figure 27 is another schematic block diagram of the communication device provided in an embodiment of this application. The device 2100 shown in Figure 27 may include a processor 2110, a transceiver 2120, and a memory 2130. The processor 2110, transceiver 2120, and memory 2130 are connected via internal connection paths. The memory 2130 is used to store instructions, and the processor 2110 is used to execute the instructions stored in the memory 2130 to implement the methods in the above embodiments. Optionally, the memory 2130 may be coupled to the processor 2110 via an interface or integrated with the processor 2110.

[0385] It should be noted that the transceiver 2120 mentioned above may include, but is not limited to, transceiver devices such as input / output interfaces, to realize communication between device 2100 and other devices or communication networks.

[0386] Memory 2130 can be volatile memory and / or non-volatile memory. Non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory can be random access memory (RAM). For example, RAM can be used as an external cache. By way of example and not limitation, RAM includes various forms such as: static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM).

[0387] Transceiver 2120 uses transceiver devices, such as but not limited to transceivers, to enable communication between device 2100 and other devices or communication networks to receive / send data / information for implementing the methods in the above embodiments.

[0388] This application also provides an audio-visual system, which includes the device 2000 or device 2100 in the above embodiments.

[0389] This application also provides a vehicle that includes the audio-visual system described in the foregoing embodiments.

[0390] This application also provides a computer program product, which includes computer program code. When the computer program code is run on a computer, it causes the computer to implement the methods described in the above embodiments of this application.

[0391] This application also provides a computer-readable storage medium storing computer instructions that, when executed on a computer, cause the computer to implement the methods described in the above embodiments of this application.

[0392] This application also provides a chip, including circuitry, for performing the methods described in the above embodiments of this application.

[0393] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0394] In the description of the embodiments of this application, unless otherwise stated, " / " means "or", for example, A / B can mean A or B; "and / or" in this document describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. In this application, "at least one" means one or more, and "more" means two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or multiple items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0395] The use of prefixes such as "first" and "second" in this application embodiment is solely for distinguishing different descriptive objects and does not limit the position, order, priority, quantity, or content of the described objects. The use of ordinal numbers and other prefixes to distinguish descriptive objects in this application embodiment does not constitute a limitation on the described objects. The description of the described objects is found in the claims or the context of the embodiments, and the use of such prefixes should not constitute unnecessary restrictions.

[0396] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0397] In the various embodiments of this application, unless otherwise specified or in case of logical conflict, the terminology and / or descriptions between the various embodiments are consistent and can be referenced by each other. Technical features in different embodiments can be combined to form new embodiments according to their inherent logical relationships.

[0398] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0399] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0400] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A communication method, characterized in that, Applied to the first slave node, the method includes: Receive a first downlink frame, the first downlink frame including first indication information, second indication information and third indication information; The first indication information is used to indicate whether a write operation is to be performed on the operation object, and the second indication information is used to indicate whether a read operation is to be performed on the operation object; The third indication information is used to indicate that the write operation is in the first mode or the second mode, or the third indication information is used to indicate that the read operation is in the first mode or the second mode, or the third indication information is invalid; The first downlink frame includes a first field, which is used to carry data associated with the operation object; in the first mode, the number of bytes in the first field is n; in the second mode, the number of bytes in the first field is m, where n and m are both positive integers, and n is not equal to m; Send a first uplink frame, which indicates whether the second slave node has successfully received the first downlink frame. The second slave node is the slave node associated with the operation object.

2. The method according to claim 1, characterized in that, The first downlink frame also includes fourth indication information, which indicates that the operation object is the register of the second slave node, or the operation object is the first peripheral device connected to the second slave node.

3. The method according to claim 2, characterized in that, When the fourth indication information indicates that the operation object is the first peripheral device, the first downlink frame further includes a fifth indication information, which indicates that the state of the internal integrated circuit I2C communication between the second slave node and the first peripheral device is at least one of the following: Initial state, waiting state, or ending state.

4. The method according to claim 3, characterized in that, The first uplink frame also includes first information, which indicates whether the second slave node has received I2C acknowledgment information from the first peripheral.

5. The method according to claim 4, characterized in that, When the second indication information indicates that the read operation is performed on the operation object, and the first information indicates that the second slave node has received the I2C confirmation information, the first uplink frame further includes a second field, which is used to carry the data associated with the operation object.

6. The method according to claim 4 or 5, characterized in that, When the first information indicates that the second slave node has not received the I2C acknowledgment information, the first uplink frame also includes second information, which indicates that the second slave node has received the I2C denial information from the first peripheral device, or the second information indicates that the second slave node is in a waiting state.

7. The method according to any one of claims 3 to 6, characterized in that, The second slave node and the first slave node are the same slave node, and the method further includes: When the fifth indication information indicates that the I2C communication is in a start state or a waiting state, the I2C communication is controlled to be in a waiting state; or... When the fifth indication information indicates that the I2C communication is in the start state, waiting state, or end state, the I2C communication is controlled to be in the end state.

8. The method according to any one of claims 1 to 4, characterized in that, When the second indication information indicates that the read operation is performed on the operation object, the first uplink frame also includes data associated with the operation object.

9. The method according to claim 8, characterized in that, When the third indication information indicates the first mode or the third indication information is invalid, the number of bytes of data associated with the operation object carried in the first uplink frame is n; When the third indication information indicates the second mode, the number of data bytes associated with the operation object carried in the first uplink frame is m.

10. The method according to any one of claims 3 to 9, characterized in that, The first uplink frame indicates that the second slave node has successfully received the first downlink frame.

11. The method according to claim 1 or 2, characterized in that, The first downlink frame also includes a sixth indication information, which indicates the address of the object being operated on.

12. The method according to claim 11, characterized in that, When the third indication information indicates the second mode, the sixth indication information is the address of the register corresponding to a byte of data in the data associated with the operation object.

13. The method according to any one of claims 3 to 7, characterized in that, When the first slave node and the second slave node are the same slave node, the method further includes: The I2C address of the first peripheral is determined based on the value of the peripheral I2C address register associated with the first slave node.

14. A communication method, characterized in that, Applied to the master node, the method includes: A first downlink frame is sent, the first downlink frame including first indication information, second indication information and third indication information; The first indication information is used to indicate whether a write operation is to be performed on the operation object, and the second indication information is used to indicate whether a read operation is to be performed on the operation object; The third indication information is used to indicate that the write operation is in the first mode or the second mode, or the third indication information is used to indicate that the read operation is in the first mode or the second mode, or the third indication information is invalid; The first downlink frame includes a first field, which is used to carry data associated with the operation object; in the first mode, the number of bytes in the first field is n; in the second mode, the number of bytes in the first field is m, where n and m are both positive integers, and n is not equal to m; A first uplink frame is received, which indicates whether the second slave node has successfully received the first downlink frame. The second slave node is the slave node associated with the operation object.

15. The method according to claim 14, characterized in that, The method further includes: The second slave node is determined based on the value of the slave node number field in the node or peripheral selection register associated with the master node.

16. The method according to claim 14 or 15, characterized in that, The method further includes: Based on the value of the select slave node or peripheral field in the node or peripheral selection register associated with the master node, the operation object is determined to be the register of the slave node or the peripheral connected to the slave node.

17. A data transmission structure, characterized in that, The data transmission structure is used for information transmission between the master node and the second slave node in the audio and video system. The second slave node is associated with the operation object. The data transmission structure is used to carry first instruction information, second instruction information and third instruction information. The first indication information is used to indicate whether a write operation is to be performed on the operation object, and the second indication information is used to indicate whether a read operation is to be performed on the operation object; The third indication information is used to indicate that the write operation is in the first mode or the second mode, or the third indication information is used to indicate that the read operation is in the first mode or the second mode, or the third indication information is invalid; The data transmission structure includes a first field, which is used to carry the data associated with the operation object; in the first mode, the number of bytes in the first field is n; In the second mode, the number of bytes in the first field is m, where n and m are both positive integers, and n is not equal to m.

18. The data transmission structure according to claim 17, characterized in that, The data transmission structure also includes a third field, which is used to carry the third indication information.

19. The data transmission structure according to claim 17 or 18, characterized in that, The data transmission structure further includes a fourth field, which is used to carry the first indication information and / or the second indication information.

20. The data transmission structure according to any one of claims 17 to 19, characterized in that, The data transmission structure further includes a fifth field, which carries fourth indication information. The fourth indication information indicates that the operation object is the register of the second slave node, or the operation object is the first peripheral connected to the second slave node.

21. The data transmission structure according to any one of claims 17 to 20, characterized in that, The data transmission structure further includes a sixth field, which carries fifth indication information. The fifth indication information indicates that the state of the internal integrated circuit I2C communication between the second slave node and the first peripheral is at least one of the following: start state, wait state, or end state.

22. The data transmission structure according to any one of claims 17 to 20, characterized in that, The data transmission structure also includes a seventh field, which carries a sixth indication information, indicating the address of the operation object.

23. The data transmission structure according to any one of claims 17 to 22, characterized in that, The data transmission structure also includes an eighth field, which is used to carry the identifier of the second slave node.

24. A data transmission structure, characterized in that, The data transmission structure is used for information transmission between the master node and the second slave node in the audio and video system. The second slave node is associated with an operation object, which is the object on which the master node performs a read operation or a write operation. The data transmission structure is used to carry feedback information, which indicates whether the second slave node has successfully received the first downlink frame. The first downlink frame indicates that the read operation or the write operation is performed on the operation object.

25. The data transmission structure according to claim 24, characterized in that, The data transmission structure further includes a ninth field, which carries third information indicating that the operation object is the register of the second slave node, or the operation object is the first peripheral connected to the second slave node.

26. The data transmission structure according to claim 24 or 25, characterized in that, The data transmission structure includes a second field; When the operation object is the register of the second slave node, the second field is used to carry the data associated with the operation object; When the operation object is the first peripheral connected to the second slave node, and the second slave node receives the I2C confirmation information from the first peripheral, the second field is used to carry the data associated with the operation object; or, When the operation target is the first peripheral connected to the second slave node, and the second slave node has not received the I2C acknowledgment information from the first peripheral node, the second field is used to carry second information. The second information indicates that the second slave node has received the I2C denial information from the first peripheral node, or the second information indicates that the second slave node is in a waiting state.

27. The data transmission structure according to claim 26, characterized in that, The data transmission structure also includes a tenth field, which carries first information indicating whether the second slave node has received the I2C acknowledgment information.

28. The data transmission structure according to any one of claims 24 to 27, characterized in that, The data transmission structure also includes an eleventh field, which is used to carry the feedback information.

29. The data transmission structure according to any one of claims 24 to 28, characterized in that, The data transmission structure also includes a twelfth field, which is used to carry the identifier of the second slave node.

30. A communication device, characterized in that, The device is located at a first slave node, and the device includes a transceiver unit and a processing unit, the transceiver unit and the processing unit being used to perform the method as described in any one of claims 1 to 16.

31. A communication device, characterized in that, include: Memory, used to store computer programs; A processor for executing a computer program stored in the memory to cause the apparatus to perform the method as described in any one of claims 1 to 16.

32. A vehicle, characterized in that, Includes the apparatus as described in claim 30 or 31.

33. A computer-readable storage medium, characterized in that, It stores instructions that, when executed by a processor, cause the processor to implement the method as described in any one of claims 1 to 16.

34. A chip, characterized in that, The chip includes circuitry for performing the method as described in any one of claims 1 to 16.

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