R-turing complete, universal quantum computing system with auto- parallelized quantum processing units operatable on minimal quantum information depth, and method thereof

Abstract

Proposed is a r-Turing complete, universal quantum computing system and corresponding method for programmable, universal quantum computing. A quantum computing circuit is composed of a plurality of auto-parallelized quantum network devices, wherein each quantum network device comprises one or more quantum logic gates whose computational steps are synchronized in time, wherein a quantum logic gate is a device performing a fixed unitary operation on selected qubits in a fixed period of time, wherein for each quantum logic gate one or more qubits form an input quantum register to the respective quantum logic gate and one or more qubits form an output quantum register to the respective quantum logic gate, the outputs of the quantum logic gates being at least partially connected by wires to the inputs of other quantum logic gates, and quantum network devices performing the computational steps by its quantum logic gates within one clock cycle.

Description

[0001] r-Turing Complete, Universal Quantum Computing System With Auto- Parallelized Quantum Processing Units Operatable On Minimal Quantum Information Depth, and Method Thereof

[0002] Field of the Invention

[0003] This invention relates generally to the design and manufacture of quantum computing circuitry (QCC) and more particularly to a system and a method of maximizing quantum processor performance, processing speed and definiteness (error rate) by using QCC layout optimization driven by quantum computing circuit fabrication process simulation. Furthermore, the current invention generally relates to the programmable quantum computing circuitry and quantum processors based on generic parallelized quantum processing units (QPU) referred herein as quantum network devices. In the inventive quantum computing circuitry comprising parallelized, quantum multi-network devices, each quantum network device comprising one or more quantum logic gates whose computational steps is synchronized in time. Further, it relates to a system and a method of scalable manufacturing yield providing universal, programmable quantum systems, processors and quantum computers, optimized QCC processing performance, processing speed and definiteness (error-rate) independent to a specific code to be processed and executed. This is achieved by the described, specifically architectured and optimized and granular quantum multi-network device architecture. More particular, it further relates to mutual optimization of the parallelization of code and optimization of a respective QCC design. In the technical field of quantum computing circuitry, important characteristics and classifications arise inter alia, from the challenges to building quantum circuits, which are (i) for all computations reversible, typically resulting in a potential massive space overhead for ancilla registers and which are not easy to define generically; (ii) there is no-cloning-theorem, (iii) presently no-saving / memory structures, and (iv) measuring collapses the superposition on qubits to the components of states. This invention relates generally to quantum systems enabled to overcome the mentioned challenges and limitations by providing a r-Turing complete, universal quantum computing system with autoparallelized quantum processing units operatable on minimal quantum information depth. Background of the Invention

[0004] The fundamental technical and physical limits on classical computation and the possibilities of exponential speedups from quantum effects have brought quantum circuits to the attention of the field of electronic design and automation. The realization of efficient quantum logic circuits relies on two tasks: (i) implementing generic quantum computations with an acceptable computational error-rate and (ii) initializing quantum registers. In contrast to conventional computing, both tasks are nontrivial and technically challenging, the latter because the state-space of an n-qubit register is not finite and contains exponential superpositions of classical bit strings. There is a large demand for quantum circuits and quantum circuits implementation which are optimal, or at least asymptotically optimal, for respective tasks and improve the deficiencies of the prior art systems in the design, transpilation and synthesis of quantum circuits, in particular in automation of design and synthesis of quantum circuits for generic (generically programmable) quantum computation, and more particularly for generic, scalable quantum computing applicable to any problem to be solved or processed.

[0005] In the prior art, the minimization efforts of the classical transistors approach atomic proportions, and Moore's law, i.e. the postulate that there is a log-linear relationship between device complexity (higher circuit density at reduced cost and time) becomes limited to the small-scale granularity of the world: it is not possible to build wires thinner than atoms. Worse still, at atomic dimensions, the technology is confronted to contend with the laws of quantum mechanics. For example, supposing one bit is encoded as the presence or the absence of an electron in a small region. Since it is known precisely where the electron is located, it follows from the Heisenberg uncertainty principle that its momentum cannot be known with high accuracy at the same time. Without a reasonable upper bound on the electron's momentum, there is no alternative but to use a large potential to keep it in place, and expend significant energy during logic switching. A quantitative analysis of these phenomena leads to fundamental limitations on the scalability of any computing device which moves electrons. Further, in the transistor approach, there are fundamental technical challenges of engineering nanoscale transistors in the design of gates. As device dimensions shrink, controlling the current flow in the thin channel becomes more difficult. Modern nanoscale transistors typically take the form of multi-gate MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistor), with the FinFET (Fin Field-Effect Transistor) being the most common nanoscale MOSFET transistor. The FinFET has gate dielectric on three sides of the channel. In comparison, the Gate-AII-Around FET (GAAFET) structure has even better gate control. FinFET and GAAFET are both non-planar transistors, i.e. 3D transistors, where GAAFETs are the successor to FinFETs, as they can work at sizes below 7nm. However, the influence of connection structures on circuit behavior becomes increasingly serious at a nano scale. The higher the switching speed of the transistors and the thinner the connection lines become, the more limiting technical and physical properties become predominant as factors for further increases in the speed of transistor-based circuits. With clock frequencies in the GHz range, integrated circuits behave more and more like microwave circuits. Mainly their electrical resistance and capacitances cause disruptive properties such as signal distortion, attenuation, crosstalk, and heating. More particularly, with a physical gate length in today's MOSFETs below 7 nm, various physical effects needs to be taken into account providing limits of miniaturization of integrated circuits: (i) spread of doping atoms in a semiconductor material; each dopant induces a relatively high potential bump; (ii) quantization of both electrical and thermal conductance in narrow and thin transistors' channels and in conducting paths; (iii) propagation time of electromagnetic wave along and across a chip (IC); (iv) electrostatics; a loss of electrostatic control of the drain current versus the gate voltage; and (v) electron tunneling between a source and a drain inside a MOSFET through a insulation (oxide). In summary, the classical transistor approach approaches its miniaturization and speed limits due to physical limits given by the manufacturing process (e.g. given by the Abbe diffraction limit and the optical masks needed for manufacturing), the individual interconnects (semiconductor integrated circuits depend on fast and dense interconnects), the conventional transistor itself (conventional transistors are limited by their width of the gate dielectric, which nowadays reached the size of several atoms, and the design requirements (integrated circuit design using grid-based automated layout through algorithms are limited in redesign by serious optimization problems).

[0006] The potential of quantum computing indicates a way out of these limitations. For example, to suppress quantum effects, integrated chip manufacturers tend to go to great lengths. In quantum computing, instead of suppressing quantum effects, the quantum effects are harnessed for the benefit of computing. Though quantum computers work by executing the same quantum algorithm several times over again, where the most likely result after these runs is the solution, the time it takes it run the quantum computer several times typically is still exponentially faster to arrive at the result, than a conventional computer would need in a single run working on the same problem. This is particularly true for hard computation problems. Such hard problems are characterized by exponential growth in complexity, as it can be found, for example, in optimization problems, machine learning, sampling of large data sets, forecasting simulations and the like.

[0007] In general, quantum computing refers to the technical field of computation systems and quantum computing circuitry (QCC) that use quantum mechanical phenomena to manipulate data. These quantum mechanical phenomena, such as superposition (in which a quantum variable can simultaneously exist in multiple different states) and entanglement (in which multiple quantum variables have related states irrespective of the distance between them in space or time), do not have analogs in the world of classical digital computing, and thus cannot be implemented with classical computing devices. However, quantum computing, emerging as a transformative field from quantum mechanics and computer science, has gained immense attention for its potential to revolutionize computation. The promises are high, as for example, it allows to provide massively fast / large computational sizes, because with an n-qubit system 2n information can be computed in parallel, or by the fact that quantum computing promises the realization of single Instruction - multiple data (SIM D) with new scales. On the other side, the challenges to building quantum circuits are also high since (i) all computations must be reversible, which may result in potential massive space overhead for ancilla registers and which are not easy to define generically; (ii) there is no-cloning-theorem, (iii) no-saving / memory - at least not in foreseeable future, and (iv) measuring collapses the superposition on qubits to the components of states.

[0008] Nevertheless, quantum computing technology uses different approaches to solve certain computational problems, demonstrating greater efficiency compared to classical computing systems. The outcome of the present inventive quantum computing circuitries is remarkable, inter alia, providing the possibility of quantum computers becoming commercially available in the near future. A prominent example of quantum computing's ability lies in Shor's algorithm, renowned for its capability to factor large numbers efficiently. This algorithm marked a pivotal step in the advancement of quantum computing by enabling the determination of prime factors of large numbers by quantum computers, and has also caused consternation in cryptography field as many public key cryptography algorithms rely on the difficulty of factoring large numbers by classical computers. A distinct difference in computational power of classical versus quantum computers can be illustrated with the evaluation of the time required to crack encryption schemes like Rivest-Shamir-Adleman (RSA) that rely on the difficulty of finding prime factors of large numbers. While traditional computers would require billions of years for such a task, quantum computers could potentially solve it in a short time.

[0009] Quantum computers share some components with classical computers, such as registers, gates, and memory elements. However, their underlying physical structures are fundamentally distinct and technically unique. Quantum computations unfold within quantum registers, where qubits can exist in the state of superposition and entanglement. These unique characteristics make quantum computers fundamentally different from traditional classical computers. Another distinct difference of quantum computing versus classical computing is computational units such as bits. Bits in classical computing are restricted to zero or one whereas quantum computing employ units, so called qubits, that may have a value that is either 0, 1 or a quantum superposition of 0 and 1. A two dimensional column vector of real or complex numbers represents a possible quantum state held by a qubit, represented as that is a qubit state with the

[0010]

[0011] complex numbers a and satisfying \a |2+ | / ?|2= 1. This unique attribute grants quantum computers the remarkable ability to simultaneously follow multiple computational paths within a single calculation, which is not possible by classical computers without repeated iterations. Examples of valid quantum state vectors representing qubits are:

[0012]

[0013] With other words, any quantum information is reducible to qubits, to one-and two-qubit gate operations. As mentioned, qubits are the counterparts of binary bits. Their physical counterparts are polarized photons. The decoherence of quantum superposition through the interaction of the computer with the environment, and the precise application of quantum state transformations in order to obtain accurate results after many computation steps, are considered as some of the main difficulties of quantum computing. Some fundamental problems brought from the beginning of quantum computing doubts whether a quantum computer could surpass the capabilities of a classical computer. Many of these fundamental problems originate from concerns about the complexity of quantum computer design and difficulty of controlling quantum computation devices. These concerns are primarily related to the concept of decoherence, where quantum systems interact with their environment and lose their quantum properties (superposition, entanglement, and interference) over time affecting the outcome of quantum circuits. The technical problems of providing a controlled quantum environment have led to debates about achieving reliable quantum computers. However, if certain conditions are met, quantum computers promised to outperform classical computers.

[0014] While early noisy quantum computers have been used to implement algorithms such as Shor's, Grover's, and Deutsch-Jozsa's, the prevailing high error rates and noise prevent the scaling of these algorithms. In order to achieve fault-tolerant quantum computation, substantial improvements are required in quantum computers to control and protect the qubits sufficiently for reliable algorithms. In the prior art, to achieve more fault-tolerant quantum computation, hardware modifications or the use of error-correcting codes was proposed. For example, Quantum Error Correction (QEC) was introduced, which allows to encode information from one logical qubit onto multiple physical qubits, protecting it from errors. At least, this demonstrated the technical possibility of executing quantum computations reliably with noisy quantum hardware.

[0015] In quantum computing, noise and quantum scaling technically relate to each other. If errors and noise are below a certain threshold, it's theoretically possible to scale up quantum computers to larger sizes. Many types of error-correcting techniques have been developed in the prior art, but research indicates that millions of physical qubits are needed to achieve useful quantum computers. Despite this, various algorithms have claimed quantum supremacy, showcasing computations on quantum devices and circuits likely surpass classical computers' capabilities in a reasonable time frame. Prominent prior art quantum computing is provided, e.g., by IBM, Xanadu, and Google's Quantum Al team. Though these prior art systems are significant steps to quantum computing, they have limitations in scaling up quantum computations due to noise and errors. The present inventive system providing a programmable, r-Turing complete, universal quantum computing circuit and system has, inter alia, the advantage that allows to provide quantum computing systems, which overcome at least some of the deficiencies of the prior art quantum computing systems. The inventive system allows

[0016] (i) to extract ideal parallelism from a given code in a (high) language or in assembler

[0017] (ii) to extract the instructions and parallel needed data, especially for loop-sections

[0018] (iii) to exploit what Single Instruction – Multiple Data (SIMD) platforms are able to exploit

[0019] (iv) to compile a given code directly into quantum circuits

[0020] (v) to provide efficient quantum circuits, consisting of universal, reversible quantum gates by using known / state-of-the-art methods, such as the Quantum Fourier Transformation, which enables arithmetic operations with phase rotations

[0021] (vi) to provide a reliable system capable of writing custom quantum circuits in "quantum blocks" consisting of the set of state-of-the-art universal quantum gates to solve arithmetic / logical operations within a computation block (CB)

[0022] (vii) to be based on Computation Blocks (CB), which, as in quantum computing, do not allow two inputs are to map to the same output (reversibility). The inventive Computation Block therefore differentiate it exactly that manner from Basic Blocks, as used in classical parallel processing systems.

[0023] (viii) (vii) and the inventive system's capabilities of coupling of runtimevariable with ideal parallelism segments enables a direct compiling approach to quantum computing circuits. (ix) to provide by the correct sequence of operations given in an inventive code also the relevant order in quantum computing (e.g.

[0024] 2d heat equation the spatial evolution must be solved before the temporal computation step).

[0025] (x) to represent, by the inventive system, code-steps with distinct parallel data size. From this minimal parallel data dimension efficient quantum blocks are formed based on universal quantum gates.

[0026] (i) Basics and notation of Quantum Computing

[0027] In place of bits in classical computing, quantum computing uses qubits, which can exist in multiple states at the same time, a phenomenon known as superposition. Quantum entanglement signifies a unique connection between qubits and quantum interference can alter the outcome of the qubits. Quantum computers also face a challenge called quantum noise, which can lead to loss of quantum properties, such as superposition, entanglement, and interference, and can affect the outcome of a quantum system. Below, a simple yet comprehensive understanding of quantum computing fundamentals is provided.

[0028] In a classical digital circuit, flip-flops and latches (hereafter wires) are circuits that have two stable states that can store state information, a so called bistable multivibrator. The flip-flops and latches circuit can be made to change state by signals applied to one or more control inputs and will output its state (often along with its logical complement too). It is the basic storage element in sequential logic. Flip-flops and latches are fundamental building blocks of digital electronics systems used in computers.

[0029] For a classical digital circuit, a wire can be in state ‘O' or ‘ 1 ', mean the value of the bit on the wire is 0 or 1. Considering one bit, it can be in state 1 with probability pi, or in state 0 with probability po, what can be described by a two-dimensional vector:^0. In a classical deterministic circuit a wire can be seen in state 0 with probability: J). If a gate is applied to a wire, this influences the state of the bit on the wire. E.g., the NOT gate would flip the state: NOT J) and same for the

[0030]

[0031] opposite. The NOT gate / vector could be expressed as a matrix:

[0032]

[0033] Applying of the gate to the wire results in:

[0034]

[0035] If a second wire is added with probabilities q0 and ql, four potential probabilities can arise:{00,01,10,l 1}, what results in the probabilities:

[0036]

[0037] For quantum computing, reversible computations are mandatory. It is known, any irreversible computation can be transformed into a reversible computation. But this needs additional information. In case of a AND gate, beneath the two input wires, a third wire is needed to save the additional information necessary to reverse the operation. But this would lead to transform a reversible circuit by adding additional states / wires, what transforms an irreversible circuit with depth T and space S to a total of S+ST space and depth T. This additional information generated to make every circuit reversible can be lost at the end of the computation by copying out the needed information, see figure 1.

[0038] A reversible circuit computes, where the input states xtare computed with the gates q:

[0039] (x1,x2,x3), (c1,c2,c3) -> (x1,x2,x3),(c1©y1,c2©y2, C3©y3) Where / '(x1,x2,x3) = (yi,y2,y3).

[0040] To describe a quantum mechanical platform, it can be started by a quantum mechanical (two-level) system, where a simple experiment with photons can be used. If looked with a setup with one beam splitter at each detector 50% of the photons are measured, as shown in fig. 2. Changing this setup by adding a mirror and point the photons to a second beam splitter (see fig. 3), the results change.

[0041] Following classical physic, the photons would arrive 50% percent on the ‘O'

[0042] and 50% on the ‘1 ' path. But experimental results show that they arrive 100% only on

[0043] one detector. Figure 4a shows a block diagram schematically illustrating a measurement statistics with two beam splitters. Figure 4b shows a block diagram schematically illustrating the ‘O' path. Figure 4c shows a block diagram schematically illustrating the ‘ 1 ' path.

[0044] The photon in the setup can be seen as a two-state system, whether the photon is on path ‘O' or ‘ 1 '. The path (first path ‘O' or second path ‘ 1 ') of a photon can be captured by:

[0045]

[0046] The effect origins in the superposition of the photon to go in both ‘O' and

[0047] ‘ 1 ', what can be seen as a linear combination the photon must be on

[0048]

[0049] one path the probability the photon is: |a012+ l«i I2= 1-

[0050] The state vector would be and leads to - without any

[0051]

[0052] measurement:

[0053]

[0054] Therefore, if behind the second beam splitter the photon is measured, this results in, that the photon is in ‘ 1 ' path with the probability of |i|2= 1.

[0055] Qubit is a quantum computing particle that has a wave-like nature with wavefunction ip(x) that satisfies the Schrodinger equation. Theoretically, this wavefunction exists in an infinite dimensional Hilbert dual space. Therefore, the state vector representing this wavefunction in Hilbert space requires an infinite dimensional vector notation. This infinite dimensional vector state of the qubit in Hilbert dual space is expressed using Dirac's braket notation. It is to be noted, that it can also be a finitedimensional vector having two states, e.g. on / off or spin-up / spin-down, which can be shown in two-dimensional Hilbert space. In this notation, two-dimensional state vectors | 1 ) (i.e. ket one) and | 0) (i.e. ket zero) are used for qubit.

[0056] In summary, qubits represent the classical bits in quantum states, and they describe the state in a system. In the binary world 0 and 1 is distinguished by two voltage stages. In the quantum world a qubit (two state-quantum system) describes a quantum mechanical system which can be differentiated by measurements to be in two different states. An n-qubit basis state is described by an 2”-dimensional vector. In the above-mentioned Dirac notation, this vector is described by a binary string of length n, identified with the notation |a). The vector describing the finite-dimensional quantum states are then described by a complex vector space, which is the mentioned Hilbert space J£. The computational basis is then described by this basis, meaning with 2”-dimensional vector describing in Dirac notation:

[0057] what leads to the notation:

[0058]

[0059]

[0060] Therefore, the state vector |a) can be seen as a n-sized binary string.

[0061] Looking on how quantum computers technically must be programmed, the used mathematical notation of quantum computing has to be introduced. There are two approaches to quantum computing: a. Theoretical perspective with focus on linear algebra representation: This is suitable for closed quantum systems. This perspective makes it easier to think about them in theory. They are about pure states and unitary operations on them. This can be described by linear algebra methods.

[0062] b. Practical perspective with focus on real systems: They are not directly closed (key word: measurements) and we get mixed states. This makes it necessary and a bit more complicated to formulate applicable operations on quantum computers with so called superoperators.

[0063] The dot-product of two vectors v and w (v,w) may be defined as:

[0064]

[0065] In case of vectors with complex numbers (with c* = a - bi as complex conjugate for c = a + bi), their vector spawns up a Hilbert space J£. For vectors of the complex numbers an inner product must be a function which takes two vectors from the same space and resolves to a single complex number. If their inner product is zero, they are orthogonal. A vector describing the states

[0066]

[0067] has norm:

[0068] ||| r)|| = y >

[0069] (ii) Orthonormal basis

[0070] And is called unit vector if the norm is 1. Two vectors with inner product equal 0, means they are orthogonal. This is important when it comes to specify a basis for a space where points can be located. The Kronecker delta function 5i;- is defined to be on all indexes equal 1 where i = j and everywhere else equal 0.

[0071]

[0072] Thus, the state vector can be written in the following form in case when the basis B = is described by orthonormal basis (bn\bm) = 6^

[0073]

[0074] Whenne< C are the coefficients of \i ).

[0075] (Hi) Quantum operators and unitary operators

[0076] To transform with a linear transformation T:

[0077]

[0078] a vector it is the multiplication. The means to apply an operator it is a multiplication, respectively an outer product of an operator

[0079]

[0080] to the vector |y):

[0081] Cl 'X^^lr) = C<<£»ly»ly>

[0082] The outer product of a vector

[0083]

[0084] with itself

[0085]

[0086] defines an operator and this operator projects a vector \<p)eK to a subspace of

[0087]

[0088] spanned by

[0089]

[0090] If then B = {|bn)} is an orthonormal basis for a vector in space J£, every linear operator T on Jf ca be written as:

[0091]

[0092] where Tnm= (bn\T\bm). Therefore, applying T on

[0093]

[0094] is a summation (matrix elements) of Tnm

[0095] T^m{bmWbn)

[0096]

[0097] bn,bmeB

[0098] At this step a unitary operator U can be defined by:

[0099]

[0100] And I is the complex conjugated transpose of the matrix U (called Hermitean conjugate). This is important as U is a class of operators which can describe the time-evolution of quantum states. Furthermore, the unitary operators preserve inner products between vectors and norm of vectors. In case an operator follows:

[0101] 7’1' = T

[0102] This operator is called Hermitian. In this case T is equal the own Hermitian conjugate. The next relation known from linear algebra is:

[0103] T\p) = c\ip)

[0104] In this case, the vector

[0105]

[0106] is called the eigenvector of an operator T for some constant c. Therefore, in case 7’t= T and T|I 4 =

[0107]

[0108] leads that the constants A R. This is an important fact, when measuring quantum states. A further important fact is that taking the trace of an operator A

[0109]

[0110] is NOT dependent on the choice of orthonormal basis. This leads to the interesting fact, that: For every normal operator T acting on a finite-dimensional Hilbert space there is an orthonormal basis of this space consisting of the eigenvectors of \Tt) of T. And T is diagonal in its own eigenbasis:

[0111]

[0112] This theorem shows that a linear Operator T can be diagonalized (only represented by a diagonal matrix) in some basis. This allows, that any normal operator T can be diagonalized, what can be reached by changing the basis to the basis consisting of eigenvalues. This is accomplished by conjugating the operator T with a unitary operator P.

[0113] Therefore, for every normal matrix T a unitary matrix P exists with T = P / \P where A is a diagonal matrix. This allows to define function of operators, for example to compute the power of T is computing the power of all diagonal elements. This allows to show to apply a function f to the matrix T, it is applying the function to the diagonal elements:

[0114]

[0115] (iv) Tensor products

[0116] With the tensor product different spaces can be combined, also e.g. two Hilbert spaces

[0117]

[0118] ®?f2. When building a tensor product of two vectors in space tAand J£Bthen there exist orthonormal basis \cp } and | cp? > so the new states can be described by:

[0119]

[0120]

[0121] are called the Schmidt coefficients. This leads to known notations of a general state vector

[0122]

[0123] formed by a tensor product in KA® J£Bcan simplify to:

[0124]

[0125] And the coefficient can be assumed to be real.

[0126] (v) Qubits (Quantum Bits)

[0127] In quantum computing, a quantum bit (Qbit) is a basic unit of quantum information, the quantum version of the classic binary bit physically realized with a two-state device. A qubit is a two-state (or two-level) quantum-mechanical system. In a classical system, a bit would have to be in one state or the other. However, quantum mechanics allows the qubit to be in a coherent superposition of multiple states simultaneously, a property that is fundamental to quantum mechanics and quantum computing. In particular, as a two-state quantum system, the qubit is the simplest nontrivial quantum system of all. The term "two-state system" does not refer to the number of states that the system can assume. Every non-trivial quantum mechanical system can in principle assume an infinite number of different states. However, in general, the state of a quantum system cannot always be determined with certainty by measurement, since the measurement randomly selects one of the possible measured values of the measured observables, whereby the probability of each measured value is determined by the state present before the measurement. Moreover, since the measurement usually changes the state, this problem cannot be circumvented by repeated measurements on the same system. However, it is fundamental to understand, that a Qbit has only two states, at the moment, they are reliably distinguished by “measurement".

[0128] Two quantum states, like a photon on a path ‘ 1 ' or ‘O', can be expressed by a basis:

[0129] (X )

[0130] And the state of the photon by a complex vector:

[0131] )withl“ol2+ l«i I2= 1

[0132] Physical states are represented in quantum mechanics by a unit vector in a Hilbert space J£. This indicates a very important causa: Looking e.g. at a particle which can be anywhere in space. This would lead to an infinite Hilbert space, which is continuous. In practice with finite resources, we CANNOT distinguish a continuous state space from one with a discrete state space, having a sufficiently small minimum spacing between adjacent locations. In practice we look therefor only at two-level systems. For such a two-level system, we use qubit, which is the basis for the 2-dimensional space, with basis vector |0) and |1). This is analogous to classical computation, where a voltage level above a certain positive value (e.g. 5mV) is encoded as 1 and otherwise the binary value 0. In such a two-level a general state of the system would be: ao|0) + a l)

[0133] Where a0and a1are called amplitude of the corresponding states |0) and |1). A complex amplitude can be decomposed unique as a product:

[0134] e‘e\a |

[0135] With \a |eIR depending on the magnitude of a. The general state of the system is a superposition of a photon being present, and a photon not being present.

[0136] The quantum states are technically described by classes of unit vectors and can express the most general state

[0137]

[0138] of a single qubit:

[0139]

[0140] If the classical bit is getting a probabilistic classical bit, this leads to two probabilities p0and p1and these probabilities can be represented in a 2-dimensional unit vector:

[0141]

[0142] The distinction between classical and quantic bits can e.g. be represented, as illustrated by figure 5.

[0143] Looking the state on a sphere (the Bloch sphere) and a system will be a function of time I '(t)), then the evolution of the state vector of a closed quantum system is linear (It is to be noted that the Bloch sphere is a mathematical representation of a given quantum state of a qubit, with which a technical skilled person can pinpoint and manipulate various such states within the sphere to their advantage. Three qubits | 1 >, | -) and, | y ) are shown in Bloch sphere representation in Figure 6.). Therefore, a fixed transformation U, maps | i i > to

[0144]

[0145]

[0146] Under time variance the state vector satisfies:

[0147]

[0148] The time-evolution of the states of a closed quantum system can be described by a “ unitary operator”. There is an operator U that transforms the initial state 1 of the system

[0149]

[0150] after the evolution to state 2 of the system:

[0151]

[0152] Therefore, the state of n distinct subsystems is the tensor product space of the state spaces of the n subsystems. Here is the first link to the Computation Blocks (as introduced below): Information, represented by the input data of parallel Computation Blocks (bits in classical computing / code) can be seen as information needed to be represented by any computing system and will be then computed in parallel by the operations in the parallel Computation blocks.

[0153] It is important to know, that the state of 2-qubit composite system cannot always be written in the product form

[0154]

[0155] ® I,2>- If theyareprepared separately and kept separated, they form each a closed system and the state can be written as a product form, but if they interact this is not given any more. If they interact, this is called they are entangled. Along an example with a 2-qubit composite system applying the NOT-gate X on the first qubit, the identity operator I is applied to the second qubit. This means:

[0156] X ® I

[0157]

[0158] Important to notice is that this is a 1 -qubit gate, but acts on the composite 2-qubit system. So applying a gate X on the first qubits, leads to interacting with all n-qubits in the n-qubit system. There are 2-qubits gates, which act on both qubits and cannot be written as a tensor-product of two 1 -qubit gates. (vi) Measuring; Reading out a qubit

[0159] When measuring a quantum mechanical system, the closed assumption in the evolution postulate will be violated. Therefore, the evolution of the state of a system is NOT unitary anymore during measurement. Thus, measuring is the point that any basis can be chosen to see in which one of the basis the system is in. If applied the system is found to be in one of these basis, even it may have been in any state before the measurement (by measurement the system changes to one possible outcome!). Which of the basis states is random. Looking at a system, which is initially in the state:

[0160]

[0161] With complex coefficients cnwhere J)n|cn|2= 1 and { l is a set of vectors with n = 0,...,, N - 1 build an orthonormal basis for this space. If the system is initially in the state

[0162]

[0163] then the probability that the state |n) is found, is given by |cn|2.

[0164] Measurement, for which the result is one of the basis states, is called a Von Neumann measurement.

[0165] Quantum states contain always some probabilities within them. Once a quantum state is expressed in some basis, the coefficients for that basis determine the probabilities for finding the system in those basis states. The knowledge of a quantum system can be described by probability density over all possible states

[0166]

[0167] It must be distinguished between a superposition and a mixture of states. A mixture is when a system is merely in one state, but it is not known in which one - in contrast to superposition: in this case the system is definitely not in one of the states.

[0168] It is again to be noted, that in classical computing, a bit possesses a binary nature, exclusively adopting either a state of 1 or 0. Correspondingly, in a 2-bit classical system, only one state can exist at a given time among four distinct states that is 00, 01, 10, and 11. This conceptual framework can be extended to n-bit classical systems with 2n states but only one state exists at a given time representing the state of the classical system. Conversely, in quantum computing, a single quantum bit (qubit) can exist in the state of 0, 1, or any linear combination of these states as shown in Figure 2. This phenomenon is called superposition which enables qubits to exist in a combination of the states. Upon measurement, the superposition collapses, and the final outcome is determined depending on the probability distribution of the qubit states. Quantum superposition denotes the ability of a qubit to be in multiple states simultaneously until it is measured.

[0169] As can be illustrated by the famous double-slit experiment, light has a wave-particle duality. Figure 7 shows the difference between lightwaves and particle through two slits in a wall and the different pattern on a detector location behind the source. Figures 8 and 9 illustrate the duality of photons by the famous double-slit experiment. In figure 8, above, only one slit is used for the photons and the photons appear in particles-like accumulation pattern, while below, two slits are used for the photons and the photons appear in a wave-interference-like pattern. The same picture can be seen in figure 9 by detecting or not detecting (i.e. measuring) the photons at the slits. In figure 9, above, each photon is measured at the slit (forcing the photon in a defined state) and the photons appear in particles-like accumulation pattern, while below, the photons are not measured at the slits (detector off) and the photons appear in a wave-interference-like pattern. Looking at the probabilities, if one slit is closed (fig. 8 above), then the state on screen for slit is:

[0170] I ’i>

[0171] The probability density at position x is defined as:

[0172]

[0173] Where |x) state on screen at position x. The same for slit 2. So the position if both slits are open (fig. 8) are:

[0174] 1 1

[0175] Pmix = 2P1 to + 2P2 to

[0176] This probability distribution is assumed when it is a mixture of state I 'i) and To find out why this is, then you can detect the number of photons passing through every slit: But when they passed through the slit (so the state is defined) the state is in superposition:

[0177]

[0178] The same is true, if the photons are measured at the slits: If they are entangled, they are in neither state, but if the photons are measured, they go into one state (fig. 9). This can be used to compute in superposition, but any measurement destroys the quantum system. And it is important that measuring e.g. 1 qubit of a system with two qubits in the computational basis, influences the measurements, respectively the rest of the system. The key therefore is to know which state has to be measured. The advantage of the present system according to the invention is that it is based on detecting any change of a particular information over the run of a code.

[0179] In respect to quantum entanglement, it is to be noted that in classical computers, the state of a bit can vary independently, that is, the state of a bit is not influenced by the state of another bit. However, in quantum computing, the probability of a qubit state can be affected by the change of another qubit state probability. This phenomenon is what is called quantum entanglement. In quantum circuits, entanglement is created through quantum gates by performing specific operations on the qubits that result in inseparable states of qubits. Regardless of the physical distance between the entangled qubits, a change in one qubit state probability can change the probability distribution of all qubits in the entangled quantum system. For example, quantum entanglement occurs when two or more particles become correlated in such a way that the state of one qubit is dependent on the state of the other qubit, regardless of the distance between them. If the state of one qubit changes in the entangled system, then the states of all other qubits will be affected. There are specific states in 2-qubit systems, which are called Bell's states or EPR (Einstein-Podolsky-Rosen) pairs, which exhibit entangled properties and cannot be written in separable states. In the 2-qubit system, each of the qubits is in a superposition state but qubits are not entangled. Therefore, the probabilities of all superposed qubit states are independent of each other. When these qubits are entangled, then the change in the probability of one qubit affects the probabilities of the entangled qubits. If the two qubits are not independent particles, they are entangled and their states are dependent on each other. This entanglement results in the change of probability distribution of the state of the entangled quantum system, even if the entangled qubits are far away from each other.

[0180] It is to be noted that quantum interference is not the same as quantum entanglement. Though, qubits are represented with bra-ket notation or Bloch sphere, this is just a mathematical representation of the qubit state. In reality, the qubit has a wave-like nature that is described by a quantum wavefunction satisfying the Schrodinger equation. A wavefunction is a mathematical description of the quantum state that consists of complex probability amplitudes, and the corresponding probabilities of quantum system states. When there are multiple qubits, their wavefunctions are added together to give an overall wavefunction describing the resultant states of a quantum system. This adding process of wavefunctions is called interference. It is a fundamental phenomenon that arises from the wave-like nature of quantum particles, such as electrons or photons and it distinguishes quantum systems from classical systems. In quantum computing, when two quantum wavefunctions overlap, they can interfere with each other constructively or destructively. This results in a change in the resultant wave-function of the quantum system that affects the probability distribution of its quantum states. Interference can also be a challenge in quantum computing due to the phenomenon of decoherence. Decoherence is the loss of quantum coherence, which is the property of a quantum state to maintain its superposition and entanglement, due to the interactions with environment and thermalization. This loss of coherence leads to a breakdown of interference effects and making quantum computation error-prone. Quantum error correction techniques are used to mitigate the impact of the external environment and preserve the delicate quantum interference necessary for quantum computation. Overall, interference is a foundational concept in quantum computing, allowing quantum systems to perform computations by updating the probability distributions of the quantum states. This concept solves certain problems in ways that are not achievable using classical computing methods.

[0181] Further, also quantum decoherence and quantum noise have to be distinguished. Quantum noise refers to the uncertainty and fluctuations that arise in quantum systems due to the probabilistic nature of quantum mechanics. It is a challenge in quantum systems even at low temperatures. In classical systems, noise is often associated with random variations in signals or disturbances caused by external factors. When a quantum system is in a superposition state, its outcome upon measurement is not deterministic but is determined by the probability distribution of the quantum states. Noise and error can affect the outcome due to the quantum system's interaction with the external environment. It can lead to loss of quantum properties (superposition, entanglement, and interference (see above)) over time affecting the outcome of quantum circuits. Quantum noise has several manifestations in quantum systems, and it can impact various aspects of quantum computing. Some common examples of quantum noise include:

[0182] • Measurement Noise: When measuring a quantum system, the act of measurement can cause a quantum system to lose the quantum superposition and collapse the quantum state into one of its states, introducing uncertainty in the outcome due to the probabilistic nature of the measurement process.

[0183] • Decoherence: Interactions with the environment can cause quantum systems to lose quantum superposition, entanglement, and interference, affecting the performance of quantum algorithms.

[0184] Quantum noise poses a significant challenge for quantum computing. To address this challenge, technical skilled persons have been working on quantum error correction techniques, which are essential for preserving the quantum states against the detrimental effects of measurement noise and decoherence.

[0185] A Von Neumann measurement on a system ℋAwith a basis B = {|φi⟩} given a state:

[0186]

[0187] Outputs a label i with the probability la2and leaves the system in state |< Pj). For a bipartite state space ‘fA0

[0188]

[0189] the same effect is happening: a Von Neumann measurement yield to label i with the probability |αi|2and lefts the system in a bipartite state |φi⟩|γi⟩. Measuring of two qubits only the first qubits, lets left the second qubit in superposition.

[0190] Therefore, measuring a subsystem influences the rest of the system, what is a problem. A Von Neumann measurement projects the input state |ψ⟩ into one of the orthogonal subspaces corresponding to the projection operators Piwith probability equal to the square of the size of the amplitudes of the component of |ψ⟩ (Eigenvalues spawn basis for diagonal operator). To measure a pure state, one should use ancillary register (or named ancilla). Ancilla registers are extra bits (or qubits) to implement irreversible logical operations. As mentioned above, a real system is not in a pure state, it is more in a mixed state. This occurs by:

[0191] 1. Preparation of the systems lead to numerous pure states and the probabilities of the preparation must be considered.

[0192] 2. When the system is entangled and therefor describes a combined state. Then the density matrix of an entangled system differs from the one of the ensemble of pure states.

[0193] Therefore, a qubit can be described by a specific set of state vectors, with corresponding probabilities. This mixture of probabilities of states is called mixture or ensemble of states. A pure state is a special state of mixed states, then when only one of the states occur with probability greater than zero. A quantum state in the d-dimensional system is a superposition of d basis states:

[0194]

[0195] |α1|2+ |α2|2+ ··· + |αd|2= 1

[0196] As mentioned, in reality there is "noise" in the states, so each quantum states |ψi⟩ has a probability pito occur.

[0197]

[0198] This is important for measurements. When measuring the physical system of such a device to the basis

[0199]

[0200] |v2⟩, ···, |vd⟩ we compute:

[0201]

[0202] The outcome of the measurements (Pr[observe |vi⟩]) in the basis

[0203]

[0204] can be expressed in the terms of the density matrix p

[0205] Pr[observe |vi⟩] = ⟨vi|ρ|vi⟩

[0206] A hypothetical measurement given for a pure state |ψ⟩

[0207]

[0208] would be:

[0209] 1. Pick an orthogonal basis |v1⟩, |v2⟩, ···, |vd⟩

[0210] 2. Receive the outcome for “i" with probability

[0211]

[0212]

[0213] The first step is to measure as it is not a pure system, it is a mixed system. This is solved by density matrix, respectively it can be concluded, that when applying a unitary operator U to a state

[0214]

[0215] a state U|ψ⟩ is received with a density operator (density operator for a pure state is: ρ = |ψ⟩⟨ψ|) leads to

[0216]

[0217] • It can be derived that when measuring any observable property of a system, the density operator itself matters, not the precise decomposition. This is like constructing mathematically a bigger Hilbert space and find a pure state

[0218]

[0219] such that p = 7’r|i'X 'ol-

[0220] The second big step is to measure only a partial part, what changes the entangled qubits - so the measurement of one qubit changes the states of the entangled. So it is an important point to measure a subsystem of a composite system. For example, if there are two qubits in entangle pure state |ψ⟩AB∈ℋA⊗ ℋB, to get the state vector |ψ⟩A∈ℋAas a result, then the state of the first qubit can be described by a density operator pA. Extracting this is called a partial trace:

[0221] ρA≡ TrB(ρAB)

[0222] This enables to formulate so called superoperators. The partial trace can be retrieved, if the system is expressed in Schmidt form. Recall the Schmidt form for the state vector is:

[0223]

[0224] The density matrix I 'X 'I is then:

[0225]

[0226] And the trace reduces to:

[0227]

[0228] A closed system has pure states and unitary evolution. Real system interacts with other systems (e.g. to measure) and mixed states are got. Operators for mixed states are called superoperators / general quantum operations. They can take as input a system described by density operator pin, add ancilla-registers of arbitrary size, perform a unitary operator U on the joint system and discard some subsystems. This is the basics of quantum computing.

[0229] ρin→ ρout= TrB(U(ρin⊗ |00···0⟩⟨00···0|)U†) (Equation 1)

[0230] It is an advantage of the present inventio, that it allows to support to build minimal ancilla registers for the generic operations with available reversible unitary quantum gates by using the computation blocks as subsystems.

[0231] (vii) Gates for applications

[0232] Looking at 1 -qubit: Every state is on the Bloch sphere or is equivalent with a unit vector with origin in the middle of the sphere. An action U can be seen as a rotation on the Bloch sphere for

[0233]

[0234] to the Bloch vector for U\i ). E.g. Pauli gates can move a point around the axes! It can be derived, that when U is a 1 -qubit unitary gate then there exist real numbers a,p,y and 6 to compose:

[0235] U = eiαRl(β)Rm(γ)Rn(δ) The CNOT gate (controlled-NOT) gate can control a second qubit, depending on the state of the first qubit. This means if the first controlled qubit is in state 11>, it can control on the second, what is controlling the qubits in superposition.

[0236] Controlled-CNOT gates are called Toffoli gates. They have nice effects: As shown in figures 10a and 10b, if somewhere in the computations, gates are only used to control subsequent qubits, but then are discarded, i.e. o not used for the final result, then applying the Toffoli gate is the same, as when measuring the state in the computational basis and then classically control the transformation

[0237] It is a technical advantage of the present inventive system, that for code segmented by the present inventive system, it is known for all segments which information can be controlled in parallel. Therefore this effect can be exploited to support auto-parallelization on a code and then express the parallel code as quantum circuits. It is known which states (and therefore qubits) are only be used by subsequent operations to control before being discarded. The present inventive system extracts the minimal needed "overhead" = ancilla-registers for each step in a code to keep all operations reversible and the needed data in the corresponding (entangled) states. This is very important in quantum computing as measuring changes the entangled states.

[0238] (viii) Accuracy

[0239] An important property of gates is the accuracy. A gate implements a desired unitary operation - in practice this is only possible with a specific level of accuracy. The error is then defined as the difference of the desired unitary operation and the other - real - unitary transformation V on the state vector

[0240]

[0241]

[0242] This introduces to the expression ‘approximated to arbitrary accuracy': E(U, 7) < E. Universal sets have to have this accuracy. An entangled 2-qubit gate and all 1 -qubit gates can implement any n-qubit unitary exactly. (ix) Efficiency of gates

[0243] The efficiency is a number how it is possible to express a desired unitary transformation U with a polynomial number of gates from the universal set, where polynomial means here polynomial in

[0244]

[0245] and in the number of qubits n. It can be showed, that for example the Hadamard and T-gates { / Q phase gates = rotates the state around axis) are able to approximate a circuit of m 1 -qubits requiring at most The goal is to choose some finite set of gates so that, by constructing a

[0246]

[0247] circuit using only gates from that set, non-trivial quantum computations can be implemented.

[0248] It is a further advantage of the present invention, that it can support building a given code and building the corresponding gates using state-of-the-art methods suitable for the segments of the inventive system in a generic way. Therefore, the present invention enables to retrieve a possible quantum gate circuit from the set of universal gates.

[0249] (x) Gates and measurements

[0250] In general, the principle of superposition that occurs in quantum mechanics is intimately interconnected with a physical interpretation that presupposes indeterminacy in the results of observations. A superposition of inputs gives a superposition of outputs, which equals to an entangled state, based on the exact sameness of polarization. A photon passing through an interferometer is considered, as being in a translational state, resulting by the superposition of two probable states, until with a quantum jump interferes with itself.

[0251] The concept of a quantum state assigns a probability distribution to the outcomes of each possible measurement on a system. The behavior of a quantum system is determined by the quantum state together with the rules for the system's evolution. A pure quantum state corresponds to a ray in a Hilbert space over the complex numbers, while mixed states are represented by density matrices. Individual qubits making up a multi-qubit system, cannot always be characterized as having 19

[0252] individual states of their own. More precisely, they do not always have what are called pure states of their own. Hence, a statistical description of an individual qubit, or a group of qubits is given, in terms of a density matrix or mixed state.

[0253] Given an orthonormal basis \<pi) the states \ip) can be described by:

[0254]

[0255] A Von Neumann measurement of the states

[0256]

[0257] with respect to the basis can be described by the orthogonal projectors {|< Pi>(< Pi 1} and will output the result with probability:

[0258] Tr(|ψ⟩⟨ψ||φi⟩⟨φi|) = |αj|2

[0259] First, a quantum circuit, denoted herein as quantum network device, is constructed that implements a unitary transformation U on the basis \<pj

[0260] U\(Pt) = |i)

[0261] Where i is the index in a n-bit binary and |i) is the corresponding n-qubit computational basis state. As illustrated by figure 11, this is, in the present inventive system one computation block (CB) with a distinct data size Scompute i.

[0262] Then the operator U performs a basis change from the {|

[0263]

[0264] basis to the computational basis. On the general state

[0265]

[0266] the change U is applied and then measurements of the registers in the computational basis are done, as illustrated by figure 12. Then the inverse computations I / -1have to be applied to result in the orthonormal basis

[0267]

[0268] An alternative approach is not to measure the state with respect to the computational basis after the base change, instead to "copy" (which is more making a reversible transformation which extracts the computational basis states and not the superposition) the values to ancillary registers, which then measure the computational basis, as illustrated by figure 13. (xi) Applying gates

[0269] When building quantum circuits with arithmetic operations, using ancillary registers is often mandatory. Because by operate on entangled qubits (qubits in superposition), applying operation on one qubit only is not possible without influencing entangled qubits. Furthermore, reversibility makes it necessary to save some states over the time of the computation to reverse to the input state. By copying their states to an ancillary register, the original state is preserved, implement U, which calculates the parity of three qubits with CNOT gates, is illustrated in figure 14.

[0270] This results in the state:

[0271]

[0272] When the ancilla qubit is measured, it leaves the first register (qubit) in state I 'o) with probability | a012,

[0273]

[0274] \a1\2and li^) with |a212• A full measurement on each of the states would have getting more information and leaving the states in a random basis state |x). The measurement on the ancilla register measures only the parity and no other information.

[0275] (xii) Reversibility – Ancilla Qubits – Quantum Circuit Complexity

[0276] Reversibility plays an important role in quantum computing. Reversible computing is feasible by running back to the input the intermediate calculations of the computational output and reversing the computer to its initial state. However, quantum mechanics differ from classical, as their dynamical variables do not obey the commutative law of multiplication, since position and momentum are conjugate variables. These dynamic variables are not ordinary "c -numbers" but so-called “q-numbers", representable by matrices whose elements are c-numbers (functions of a time parameter). In quantum computation, the state of the computer is described by a state vector ψ. Quantum logic gates are represented by unitary matrices. Qubits obey a nocloning rule, which also precludes sending a qubit state to two different gates at the same time. A quantum gate on one qubit is described by a 2×2 matrix, and a quantum gate on two qubits by a 4×4 matrix. A gate which acts on n qubits is represented by a 2nx2nunitary matrix. The quantum states that the gates act upon are vectors in 2ncomplex dimensions. The state's evolution in the course of time t is described by a unitary operator U on this vector space, thus, a linear transformation which is bijective and length-preserving.

[0277] The reversible operations that a quantum computer can perform upon a single qubit are represented by the action on the state of the qubit of any linear transformation that takes unit vectors into unit vectors. These transformations are called unitary and satisfy the condition UU† = U†U = 1. Since any unitary transformation has a unitary inverse, such actions of a quantum computer on a qubit are reversible. The only nontrivial reversible operation a classical computer can perform on a single qubit is the NOT operation X. The operations AND, NAND, OR and XOR are irreversible. Hence, from the output of the gate, the input cannot be reconstructed: information is irreversibly lost.

[0278] In contrast, the functionality of the quantum logic gates, is necessarily reversible, since the input should always be inferred from the output. The CONTROLLED NOT (CN) gate allows for reversible computing using a control line for information conservation and input inversion for the NOT line (only if the input in the control line is 1). The CONTROLLED CONTROLLED NOT (CCN) gate obtains two control lines for the conservation of passing signals. The NOT line is activated only if the input in both control lines is 1. In this case the CCN gate is a NOT. If only A=l, then the gate is just a CN gate. It is to be noted that the logic circuit CCN gate or CCNOT gate is also known as Toffoli gate, which is a CN gate with two control qubits and one target qubit. That is, the target qubit (third qubit) will be inverted if the first and second qubits are both 1. CNN gates are universal reversible logic gate, which means that any classical reversible circuit can be constructed from CCN gates, i.e. Toffoli gates. Thus, they are essential components in quantum computation technology.

[0279] Thus, though quantum gates are irreversible where the loss of information is dissipated by heat, this can be overcome by information conservation using control lines with so-called ancilla bits. In reversible computing, ancilla bits are extra bits used to implement irreversible logical operations. In contrast to classical deterministic computing, there is no way to deterministically put bits in a specific prescribed state in quantum computing unless one is given access to bits whose original state is known in advance. Such bits, whose values are known a priori, are said ancilla bits in a quantum or reversible computing task. A trivial use for ancilla bits is downgrading complicated quantum gates into simple gates. For example, by placing controls on ancilla bits, a Toffoli gate can be used as a controlled NOT gate or a NOT gate.

[0280] For classical reversible computation, a constant number of ancilla bits is necessary and sufficient for universal computation. Additional ancilla bits are not necessary, though extra workspace can allow for simpler circuit constructions that use fewer gates. In quantum computing, the concept of ancilla bit is extended in terms of ancilla qubits, These ancilla qubits are the basis for information conservation in quantum computing, i.e. in quantum error correction. In general, quantum error correction are techniques allowing to protect quantum information from errors due to decoherence and other quantum noise. Quantum error correction is essential to achieve fault tolerant quantum computing that can reduce the effects of noise on stored quantum information, faulty quantum gates, faulty quantum state preparation, and faulty measurements. Effective quantum error correction allows quantum computers with low qubit fidelity to execute algorithms of higher complexity or greater circuit depth. Generally, in classical computation, complexity quantifies the resources required to implement a computation. For example, the complexity of a Boolean function can be defined as the minimal number of gates, chosen from a given gate set, necessary to evaluate the function. Thus, for this application, circuit complexity is a measure to classify basic operations or functions, e.g. Boolean functions, according to the size or depth of a quantum circuit that compute them. The size of a circuit is the number of gates it contains and its depth is the maximal length of a path from an input gate to the output gate. Thus, a Boolean circuit with input bits is a directed acyclic graph in which every gate (i.e. node) is either an input node labelled by one of the input bits, an AND gate, an OR gate, or a NOT gate. The circuit-size complexity of a Boolean function f is then the minimal size of any circuit computing f, and the circuitdepth complexity of a Boolean function f is the minimal depth of any circuit computing f. Thus, the circuit structure provides a natural measure of complexity for pure states and unitaries: a unitary transformation's quantum circuit complexity is the size, measured with the number of gates of the smallest circuit that effects the unitary. With other words, a pure state's quantum circuit complexity definable is the size of the smallest circuit that produces the state from a product state.

[0281] The balance when forming reversible quantum gates, is between space (number of ancilla qubits) and time (size, which is equal the number of gates).

[0282] However, for a reversible quantum circuit computing a Boolean function, there are at least 1 ancilla bit needed. Therefore, the key for a compiler compiling higher programming languages to a quantum platform is to find from the set of universal quantum gates a reversible circuit with necessary, minimal ancilla-registers. The number of available qubits on the target platform makes is essential which segments of the code can run in quantum states and how many qubits are needed to perform the operations. The present inventive system allows to extract the minimal parallel information size of a given code.

[0283] In the present inventive system, as each computation block maps an input to one output and no other operation is influencing this series of operations, a Computational Block (CB) defines the minimal partition of the code to build reversible circuits (reversibility prevents to map more than one input to the output). Therefore, the present inventive system allows to provide the minimal ancilla-registers and possible reversible quantum gates circuits using one of the prior art ways to port arithmetic and logical operation on quantum computers.

[0284] (xiii) Circuit Complexity and Quantum-Gate-Synthesis

[0285] In the computer technology, a problem is regarded as inherently difficult if its solution requires significant resources, whatever algorithm is used. The prior art formalizes this intuition, by introducing mathematical modeling of computation to study the associated technical problems and quantifying their computational complexity, i.e., the amount of resources needed to solve them, such as computational time and storage. Other measures of complexity are also used, such as the amount of communication (i.e. communication complexity), the number of gates in a circuit (i.e. circuit complexity) and the number of processors (i.e. parallel computing complexity). One of the roles of computational complexity theory is to determine the practical limits on what computers can and cannot do. The P versus NP problem is part of the field of computational complexity.

[0286] Quantum circuit complexity quantifying the minimal size of a circuit that implements a given unitary operation, is closely related to the quantum computational notion complexity, i.e. the difficulty of solving a given computational task with a quantum computer. Thus, the quantum circuit complexity differs from quantum computational notion complexity, where the latter depending on the difficulty of finding the quantum circuit. It can be shown that the vast majority of unitary operators have near-maximal complexities. However, lower-bounding the quantum circuit complexity is a long-standing, technical problem in quantum information theory and quantum circuit design. The core difficulty is that the gates performed early in a quantum circuit may partially cancel with gates performed later. One can rarely rule out the existence of a shortcut, a seemingly unrelated but smaller circuit that generates the same unitary. Consequently, quantum-gate-synthesis algorithms, which decompose a given unitary into gates, run for times exponential in the system size. Approaches to lower-bounding unitaries' quantum complexities include Nielsen's geometric picture

[0287] A technical key question in the quantum circuit complexity is associated with constructing deeper and deeper quantum circuits by providing an n-qubit system. The central question is at what rate does the circuit complexity increase. Typically, it is assumed that by adding qubits, the complexity of quantum circuits generically grows linearly for an exponentially long time. Further, it may be assumed that most quantum circuits are fundamentally incompressible, i.e. no substantially shorter quantum circuit effects the same unitary. Thus, quantum complexity, if it grows linearly with a generic quantum circuit's depth, strongly supports the complexity equals volume assumption similar to the wormhole-growth paradox. This assumption therefore implies that complexity growth is as generic as thermalization and operator growth. However, in contrast to easily measurable physical quantities, quantum complexity grows for an exponentially long time.

[0288] Summary of the Invention It is one object of the present invention to provide a new system and method for generic quantum computing circuit design. The system and method should be able to provide automated segmented code suitable to automatically provide corresponding quantum gates architecture suitable for processing the segments in a generic way. Therefore, the present invention should be able to provide a possible quantum gate circuit from a set of universal gates. Further, one of the keys for a compiler auto-compiling higher programming languages to a quantum platform is to find from the set of universal quantum gates a reversible circuit with necessary, minimal ancilla-registers. The number of available qubits on the target platform makes is essential which segments of the code can run in quantum states and how many qubits are needed to perform the operations. The present inventive system should allow to automatically extract the minimal parallel information size of a given code. In particular, the present inventive system should allow for providing the minimal ancilla-registers and possible reversible quantum gates circuits using one of the prior art ways to port arithmetic and logical operation on quantum computers. Finally, it is an object of the present invention to provide a new system and method for generic quantum computing circuit design by automatically building a fault-tolerant quantum computer that is capable of conducting specific and hard tasks in non-exponential time.

[0289] According to the present invention, these objects are achieved, particularly, with the features of the independent claims. In addition, further advantageous embodiments can be derived from the dependent claims and the related descriptions.

[0290] According to the present invention, the above-mentioned objects for a r-Turing complete, universal quantum computing system and corresponding method are achieved, particularly, in that the quantum computing system comprising a quantum circuit being composed of a plurality of auto-parallelized quantum network devices, wherein each quantum network device comprises one or more quantum logic gates providing computations steps by one or more unitary operations, each quantum network device being synchronized in time, wherein a quantum logic gate is a device performing a fixed unitary operation on an ensemble of logic qubits correlated by quantum entanglements, wherein for each quantum network device one or more logic qubits form an input quantum register to the respective quantum network device and one or more logic qubits form an output quantum register to the respective quantum network device, an output quantum information signal of an output quantum register being at least partially transferable to an input quantum register of another quantum network device as input quantum information signal by a control unit, and the quantum network devices performing the one or more unitary operations as computational steps processed by its quantum logic gates synchronously and in parallel within one clock cycle, in that the universal quantum computing system comprises a synthesis system for synthesizing and auto-parallelization of a source program code in a source programming language for execution by the quantum network devices by translating the source programming language of the source program code into a quantum processing code as target code by generating the quantum processing code as parallelized quantum processing code comprising a number of sets of unitary operations, each set executable by one of the plurality of quantum network devices of the parallel processing system, and / or comprising control code for controlling the operation of the plurality of quantum network devices and the quantum circuit, respectively; in that the synthesis system comprises a parser module for translating the source programming language into a elementary instruction code with a flow of elementary instructions to be processed by the quantum network devices, the elementary instructions selectable by the synthesis system out of a set of elementary instructions comprising elementary arithmetic operations and / or logic operations and / or variable and array declarations operations and / or compare operation instructions and / or control and / or memory operations for the number of the quantum circuit; in that the parser module comprises means for partitioning the source program code of elementary instructions into computation block nodes, each computation block node consisting of a smallest possible segmentation of a non-further decomposable sequence of elementary instructions of the code processable by a single quantum network devices, the smallest possible segmentation of the elementary instructions being characterized by a sequence of elementary instructions framed by consecutive read and write instructions, said sequence being not further decomposable by smaller sequences of elementary instructions between consecutive read and write instructions having a minimal quantum information depth required to process the source program code, and the read and write instructions needed to receive data required for processing said sequence of elementary instructions by the quantum network device and transmit back data after processing by the sequence; in that the synthesis system comprises a matrix builder for generating numerical matrices out of computation chains portioned from the code by the computation block nodes, the numerical matrices comprising computation and transfer matrices, wherein a computation chain is formed by one or more computation block nodes creating an ordered flow of computation block nodes within a row of a numerical matrix, wherein input quantum information of the computation block nodes of a subsequent column of a numerical matrix at least partially depend on output quantum information of the computation block nodes of the antecedent column, and wherein each computation chain is executed by one quantum network device while the computation block nodes of a column are executed in parallel by the plurality of auto-parallelized quantum network devices; in that the computation matrix contains in each row the computation chain of a quantum network device with each column having the sequence of elementary instructions of a computation block node within the computation chain of the row and the transfer matrix contains transfer properties associated with a quantum information transfer from one to a consecutive computation block node; in that by means of a quantum code generator of the synthesis system a sequence of unitary operation is generated from the elementary instructions of each computation block node and decomposed into a sequence of logic quantum gates, the sequence of quantum logic gates processing an input quantum state as input quantum information of a computation block node to a target quantum state as output quantum information; in that the quantum circuit with the auto-parallelized quantum network devices is provided by a transpiler system of the quantum computing system, mapping the decomposed sequence of logic quantum gates with logic qubits to an ensemble of physical quantum gates with physical qubits; and in that the r-Turing complete, universal, parallel processing quantum computing system processes the source program code by said control unit based on the sequence of elementary instructions of the computation block nodes of a computation chain and the generated transfer matrices.

[0291] The present inventive system providing a programmable, r-Turing complete, universal quantum computing circuit and system has, inter alia, the advantage that allows to provide quantum computing systems, which overcome at least some of the deficiencies of the prior art quantum computing systems. The inventive system allows

[0292] (i) to extract ideal parallelism from a given code in a (high) language or in assembler

[0293] (ii) to extract the instructions and parallel needed data, especially for loop-sections (iii) to exploit what Single Instruction – Multiple Data (SIMD) platforms are able to exploit

[0294] (iv) to compile a given code directly into quantum circuits

[0295] (v) to provide efficient quantum circuits, consisting of universal, reversible quantum gates by using known / state-of-the-art methods, such as the Quantum Fourier Transformation, which enables arithmetic operations with phase rotations

[0296] (vi) to provide a reliable system capable of writing custom quantum circuits in "quantum blocks" consisting of the set of state-of-the-art universal quantum gates to solve arithmetic / logical operations within a computation block (CB)

[0297] (vii) to be based on Computation Blocks (CB), which, as in quantum computing, do not allow two inputs are to map to the same output (reversibility). The inventive Computation Block therefore differentiate it exactly that manner from Basic Blocks, as used in classical parallel processing systems.

[0298] (viii) (vii) and the inventive system's capabilities of coupling of runtimevariable with ideal parallelism segments enables a direct compiling approach to quantum computing circuits.

[0299] (ix) to provide by the correct sequence of operations given in an inventive code also the relevant order in quantum computing (e.g.

[0300] 2d heat equation the spatial evolution must be solved before the temporal computation step).

[0301] (x) to represent, by the inventive system, code-steps with distinct parallel data size. From this minimal parallel data dimension efficient quantum blocks are formed based on universal quantum gates. It is to be noted that in classical binary computing systems, the optimization step involves the minimization of transfers for a given hardware between all parallel computation blocks of one computation step to the following. In contrast to quantum computing platforms, where the problem of handling transfer latencies does not exist, at least not in this context. One of the goals of the inventive system is to provide an optimization step which is more about to minimize the number of needed ancilla bits holding additional information to keep each computation step reversible. This means 3-4 parallel instructions in a classical basic block of a digital general purpose application, are replaced by the inventive system 1 by parallel computation block nodes holding serial instruction chains also over the boundaries of basic blocks and resulting in 3-4 number of parallel groups of instruction. By the used resolution provided by the computational block nodes, the needed computational, independent information size per group can be derived. This enables to group the available number of logical qubits on the platform optimal to independent groups of entangled qubits. Depending on the instructions, the number of needed ancilla bits for each computational step can be derived automatically. Additionally, the size of all transfers between the parallel computation block nodes defines the needed swap registers (or measurements) for each computational step. Furthermore, the chain of instructions defines the order of applying unitary operations in each group.

[0302] Finally, it has to be noted that the present inventive quantum system 1 allows a complete automation of processing a programmable source code with the inventive quantum processing circuit, the automation comprising the synthesis, transpilation, up to the quantum program scheduling and grouping of the qubits by appropriate activation of entanglements in the non-local closed zones of the parallel processing quantum network devices. Thus, the quantum computing system 1 provides a programmable, r-Turing complete, universal quantum computer and system allowing to process any source code inputted in a high level language, automatically by the quantum information processing parallel quantum network devices.

[0303] Brief Description of the Drawing

[0304] The present invention will be explained in more detail, by way of example, with reference to the drawings in which: Figure 1 shows a block diagram schematically illustrating of making an irreversible circuit reversible and copy out the target information.

[0305] Figure 2 shows a block diagram schematically illustrating measurement statistics with one beam splitter.

[0306] Figure 3 shows a block diagram schematically illustrating a setup with two beam splitters.

[0307] Figure 4a shows a block diagram schematically illustrating a measurement statistics with two beam splitters.

[0308] Figure 4b shows a block diagram schematically illustrating the ‘O' path.

[0309] Figure 4c shows a block diagram schematically illustrating the ‘1 ' path.

[0310] Figure 5 shows a block diagram schematically illustrating the distinction between classical and quantic bits.

[0311] Figure 6 shows a block diagram schematically illustrating the Bloch sphere representation of three different qubits. The Bloch sphere gives a mathematical representation of a given quantum state of a qubit, with which a technical skilled person can pinpoint and manipulate various such states within the sphere to their advantage. Three qubits | 1>, | -) and, | y ) are shown in Bloch sphere representation in Figure 6.

[0312] Figure 7 shows a block diagram schematically illustrating the difference between lightwaves and particle through two slits in a wall and the different pattern on a detector location behind the source.

[0313] Figures 8 and 9 show block diagrams schematically illustrating the duality of photons by the famous double-slit experiment. In figure 8, above, only one slit is used for the photons and the photons appear in particles-like accumulation pattern, while below, two slits are used for the photons and the photons appear in a wave-interference-like pattern. The same picture can be seen in figure 9 by detecting or not detecting (i.e. measuring) the photons at the slits. In figure 9, above, each photon is measured at the slit (forcing the photon in a defined state) and the photons appear in particles-like accumulation pattern, while below, the photons are not measured at the slits (detector off) and the photons appear in a wave-interference-like pattern.

[0314] Figures 10a and 10b show block diagrams schematically illustrating that, if somewhere in the computations, gates are only used to control subsequent qubits, but then are discarded, i.e. o not used for the final result, then applying the Toffoli gate is the same, as when measuring the state in the computational basis and then classically control the transformation.

[0315] Figure 11 shows a block diagram schematically illustrating the construction of a quantum circuit, denoted herein as quantum network device, that implements a unitary transformation U on the basis

[0316]

[0317] with U\<pi) = |i>, where i is the index in a n-bit binary and |i) is the corresponding n-qubit computational basis state. As illustrated by figure 10, this is, in the present inventive system one computation block (CB) with a distinct data size Scompute,i.

[0318] Figure 12 shows a block diagram schematically illustrating for the quantum network device, according to figure 11, the operator U performing a basis change from the basis to the computational basis. On the general state

[0319]

[0320] the change U is applied and then measurements of the registers in the computational basis are done.

[0321] Figure 13 shows a block diagram schematically illustrating an alternative approach to figure 12, which does not measure the state with respect to the computational basis after the base change, instead to "copy" (which is more making a reversible transformation which extracts the computational basis states and not the superposition) the values to ancillary registers, which then measure the computational basis.

[0322] Figure 14 shows a block diagram schematically illustrating implementing U which calculates the parity of three qubits with CNOT gates.

[0323] Figure 15 shows a diagram schematically illustrating examples of common quantum logic gates, circuit form(s) and the corresponding unitary matrices Figure 16 shows a block diagram schematically illustrating a systems view of a quantum information processor. It consists of a physical and logical layer. The physical layer provides the error correction and consists of a physical quantum processor that has both input and output lines that are controlled by the QEC processor. This processor is in turn controlled by the logical layer, where the encoded qubits are defined and the logical operations are performed for the desired quantum algorithm.

[0324] Figure 17 shows a block diagram schematically illustrating an example of a physical qubit processor being realized by using superconducting qubits. The processor is located at the bottom (15mK) plate of a dilution refrigerator. Microwave pulses are generated at room temperature using synthesizers, arbitrary waveform generators, and mixers. These pulses are filtered and attenuated to assure negligible noise at the qubit. In this example, high-fidelity readout of the qubit state requires quantum-limited and other cryogenic amplification to overcome thermal noise for digitization and weighted homodyne measurement. The QEC processor sits above and governs the physical control and readout functions, to perform the error correction protocol.

[0325] Figure 18 shows a block diagram schematically illustrating the relation of quantum computing components to the components of the inventive quantum system, in particular the inventive Computation Blocks (CB) and potential transfers.

[0326] Figure 19 shows a block diagram schematically illustrating the present inventive system allowing technically to create quantum computing circuits and corresponding quantum code for running the quantum circuits from a processing code written in a generic, high programing language without any annotation or other hints by programmers. The inventive system transforms code from intermediate representation or opcode from an interpreted language into Computation Blocks instead of Basic Blocks in a Control Flow Graph (CFG).

[0327] Figure 20 shows a block diagram schematically illustrating a number n,, of parallel Computations in loops with the same computations / instructions' series spawning a bit-size Scompute,CB∥. Figure 21 shows an exemplary block diagram illustrating how to come from loop-sections in (a) CFG with Basic Blocks to (b) a gamma-graph with different transfers for the different phases of a loop-section.

[0328] Figure 22 shows an exemplary block diagram illustrating QFT represented as a unitary matrix acting on a quantum state vector. This can be implemented with the Hadamard gate and the phase gate Rkwhat results in a quantum circuit, which is illustrated by figure 22.

[0329] Figure 23 shows an exemplary block diagram illustrating, that when applying QFT to the state vector for n-qubit to represent the number m, then the y-th qubit will have a phase.

[0330] Figure 24 shows an exemplary block diagram illustrating a computation block defining by its in-transfers and the out-transfers the corresponding states needed to represent the defined variables (and instructions).

[0331] Figure 25 shows an exemplary block diagram illustrating, that by using QFT or AQFT, it is possible to derive generically arithmetic and logic operations into the Fourier-space and the phases become additive. For example, for an addition of two variables in a Computation Block, the quantum circuit, illustrated in figure 25, can be derived.

[0332] Figure 26 shows an exemplary block diagram illustrating an exemplary use of the input-registers for the computation by applying the QFT directly to their input states and used to produce the target states.

[0333] Figure 27 shows an exemplary block diagram illustrating an exemplary multiplier (MULC) with constant b (MULCb) and the respective symbol. A multiplier (modulo d°i) with q constant b implements the function f : 0…dq − 1 → 0…dq − 1 with y = f(x) = bx (mod qq). When constant b is relative prime to d^ then there exists the inverse b-1(mod d^) and consequently there exists the inverse function f_,(y) = b_,y (mod d^) = b_,bx (mod d^) = x. This is always the case when d is a prime number. Figure 27 shows how to construct a multiplier with constant b using two MACb blocks and the necessary direct and inverse QFT blocks. It requires a q qudit register initially holding the integer x and another q qubits ancilla register initially in zero state. At the end, one register is set to the state | bx (mod dc')> while the other register is set to state zero, so effectively the ancilla register is reset back and can be reused. In the diagram of figure 27, the boxes with the black strip at their right side are the "direct" blocks while these with the black strip at their left side are the respective inverses. The operation of the inverse MAC with parameter b-1is to perform subtraction instead of accumulation, that is referring to figure 27, there the operation MACj~-i\bx > |<p(x) > = \bx > |<p(x - b-1(bx)) > = \bx > |0 >. By inspecting the labels at the qudit buses of figure 27 describing the respective states, it can be concluded that the circuit implements the multiplication MULCb ( | x> | 0>) = | bx> | 0>. Excluding the ancilla register, which is in the zero state before and after the operation and thus it remains unentangled, it can be conclude that this circuit performs the desired multiplication operation. In present context, it is to be noted that in digital signal processing, the multiply-accumulate (MAC) or multiply-add (MAD) operation is a step that computes the product of two numbers and adds that product to an accumulator. The hardware unit that performs the operation is known as a multiplieraccumulator (MAC unit); the operation itself is called a MAC or a MAD operation. In summary, the present inventive system, in general, is able to generate quantum circuits for multilevel qudits, where the later are basic integer arithmetic operations circuits (like addition, multiplication / accumulation and multiplication) as well as more complex circuits such as squarers and the like (e.g. QFT (Quantum Fourier Transform) circuit, MMAC (Multiplier of two integers and Accumulator) circuit, and SMAC (Squarer / Multiplier with constant / Accumulator) circuit). Additional extensions can be applied. E.g., the ADD, ADDC, MAC and MULC circuits can be converted to single qudit controlled versions. Such controlled versions are e.g. useful for multilevel qudits quantum phase estimations and quantum simulations.

[0334] Figure 28 shows an exemplary block diagram illustrating an exemplary form to build quantum blocks from Computation Blocks according to the form illustrated in figure 27, where figure 27 illustrates that for a generic form of building quantum blocks from Computation Blocks, the ancilla-registers can be inverted with their input and the output of the quantum block can then again be used for a following quantum block / Computation Block.

[0335] Figure 29 shows an exemplary block diagram illustrating exemplarily the graph given by the inventive system for a simple, only exemplary code. It is interesting in the graph of the present inventive system that the minimal ancilla-register can be specified and re-used after inverting the applied gates. This enables over a code to specify the minimal number of needed ancilla-registers.

[0336] Figure 30 shows an exemplary block diagram illustrating an exemplary the forming for each of the computation blocks, where it is generically possible to generate quantum blocks with corresponding ancilla-registers and reflecting by phase-shifts the arithmetic and logical operations defined in the CBs. In the last quantum block the inverse operations can be neglected resulting in the target value, which then can be measured (see |x5».

[0337] Figures 31 and 32 show exemplary block diagrams illustrating the two cases to be distinguished, both needing a different number of ancilla-registers: (a) When the input registers are still need in later computation blocks / quantum blocks, then the ancilla-register can be "reversed" after the computed states are used. This indicate that over two side by side inventive system's-columns / graph-levels enough ancilla-register must be available: nancilla= nII A+ nII B; (b) One of the input states is no longer needed and can be used to reverse the ancilla-registers and we result in: nancilla= max(nw,n|bB).

[0338] Figure 33 shows an exemplary block diagram illustrating exemplary that the inventive system enables to retrieve the number of parallel computation blocks n,| from the statement in a serial programmed code.

[0339] Figure 34 shows an exemplary block diagram illustrating exemplary quantum block. As exemplarily illustrated in figure 33, the inventive system enables to retrieve the number of parallel computation blocks n,, from the statement in a serial programmed code. The size Swrite= tfdefines the number of needed ancilla-registers, meaning qubits m. The operation in the computation block defines the unitary transformation. By first transfer the ancilla-register in the Fourier states, it is possible to generically transpile the operation into the correlated phase shifts. This results in a corresponding quantum block exemplary illustrated in figure 34.

[0340] Figure 35 shows an exemplary block diagram illustrating exemplary that the inventive system enables to generate a basic quantum block for the parallel computation blocks in a loop. Each CB has the same statement (see figure 35). This enables for a given resolution of the mesh nxand nyto create an efficient quantum circuit. Each parallel CB gets the same quantum block, as illustrated in the above figure 35.

[0341] Figure 36 shows an exemplary block diagram illustrating exemplary that after the first iteration (see figure 35) in the second loop-internal, transfers dominate.

[0342] Figure 37 shows an exemplary block diagram illustrating exemplary quantum blocks (as illustrated in figures 35 and 36) with ancilla-registers, reversed after the computation for a mesh with nx= 5 and ny= 4. The transfers, illustrated in figure 36, define the controlled link between the states as a function of the runtime-variables nxand ny. The benefit of the above defined quantum blocks with ancilla-registers, reversed after the computation, is that they are available in the following iteration over the special extend of the problem. How this looks for a mesh with nx= 5 and ny= 4 is illustrated in figure 37. For visibility only for the first CB the link to the initial states is shown in figure 37. The yellow marks a potential measurement point to get the value of a target point at coordinates x and y after time t + 2 ■ tk.

[0343] Figure 38 shows an exemplary block diagram illustrating exemplary an executing of a parallelized quantum processing code 301. The system 1 starts at time i =0, loading the programs specified by S(i), i.e. the i-th set of the parallel sets S(i) of unitary operations 3011 to the respective quantum network device 21 (QPU) until all r rounds are ran. The quantum outputs of the parallelized, distributed program sets S(i) unitary operations 3011 are accumulated in an output vector y during execution. Finally M maps the collection of n quantum outputs y to a single output.

[0344] Figure 39 shows an exemplary block diagram illustrating exemplary an r-Turing complete, universal quantum computing system 1. The quantum computing system 1 comprise a quantum circuit 2 being composed of a plurality of autoparallelized quantum network devices 21. Each quantum network device 21 comprises one or more quantum logic gates 211 providing computations steps by one or more unitary operations 216. Each quantum network device 21 is synchronized in time, wherein a quantum logic gate 211 is a device performing a fixed unitary operation 30 on an ensemble of logic qubits 2111 correlated by quantum entanglements (213), wherein for each quantum network device 21 one or more logic qubits 2111 form an input quantum register 214 to the respective quantum network device 21 and one or more logic qubits 2111 form an output quantum register 215 to the respective quantum network device 21. An output quantum information signal 2151 of an output quantum register 215 is at least partially transferable to an input quantum register 214 of another quantum network device 21 as input quantum information signal 2141 by a control unit 20. The quantum network devices 21 perform the one or more unitary operations 216 as computational steps processed by its quantum logic gates 2111 synchronously and in parallel within one clock cycle 201.

[0345] Figures 40a and 40b show two exemplary diagrams illustrating exemplary the realization of quantum circuits to build the computational block nodes 333. The quantum circuit shown in fig. 40a is composed of two qubits and two gates. First, a Hadamard operation is applied to qubit q0, setting qo into a superposition. Afterwards, a controlled NOT (CNOT) operation is conducted, where qo serves as control qubit and qi is the target qubit. Here, the value of qi is inverted if qo is in the basis state | 1>. Figure 40b illustrates the mapping of the logic quantum circuit of figure 40a to a reversible quantum circuit. The reversible quantum circuit shown in fig. 40b is composed of three qubits and four gates. The target qubit of a Toffoli gate is again denoted by ®, whereas control qubits are denoted by •. Additionally, the intermediate values of the qubits are labeled throughout the circuit when applying | qoq,q2> = | 000> as input. Since a reversible circuit can be modeled in the classical domain (no quantum effects are exploited), 0 and 1 are used here to indicate the basis states (rather than | 0> and | 1>). The first gate has not control qubits and, thus, inverts the value of qo from 0 to 1. The second gate is controlled by qo. Since the value of qo is 1, the value of qi is inverted from 0 to 1. The second gate does not affect the state of the qubits, since the control qubit q2 is set to 0. Eventually, the last gate inverts the state of q2 from 0 to 1.

[0346] Figure 41 shows a block diagram schematically illustrating the different scopes of the units "basic blocks" (or "block units" respectively) and "computation block nodes" as schematic examples. "Computation block nodes" as used in the present application differ essentially from those block units, used in SOTA (State-Of-The-Art) compilers.

[0347] Figures 42, 43 and 44 show a block diagram schematically illustrating the step of numbering the computation block nodes depending on their call-position in the code, resulting in a pseudo graph like schematically represented in figure 42, which in return results in the computation and transfer matrix for each path number as shown in figures 43 and 44. In the perspective to see a matrix as a m x n object, then there will be created one set of a computation and a transfer matrix per path number, resulting in 2 computation and 2 transfer matrices. The switch of the paths (or conditions) can be seen in figure 45, where the 'True' / 'False' signaling is indicated.

[0348] Figure 45 shows a block diagram schematically illustrating how each row of the computational and transfer matrix together, represents a combination of a chain of instructions and communication entries for one unit. Units are depending on the level of implementation (e.g. bare assembly, threads, processes, compute-nodes, etc.).

[0349] Obviously empty computation cells or not used communication entries (empty cells in the computation and / or transfer matrices) vanish, as well as start- and endcommunication link together as can be seen in figure 45. This provides the result of combining start- and end-communication cells in the transfer matrix and eliminating empty cells in the computation matrix (for each path) and bring them back to different code segments. Based on this code segments of elementary instructions 35 a quantum processing code 30 / 301 of unitary operations 3012 can be generated by the synthesis system 11. Depending on the synthesis method to implement the communication, nonblocking or blocking mechanisms can be used, as it is guaranteed, that during a computation block node no information will be transferred used in the instructions at the same time, respectively another cbn with same number.

[0350] Figure 46 shows a block diagram schematically illustrating an exemplary embodiment variant according to the present invention with the source code 31 as input code to the programmable, r-Turing complete, universal quantum system 1 comprising the parser 111, the computational block chains module 114, the matrix builder 115, the optimizer 116, the quantum program scheduler 113, the code generator 117, the quantum system 1 generating the parallelized and optimized quantum target code 30 as parallel sets 301 / 3011 of unitary quantum operations 3012 for execution by the quantum circuit 2 having a plurality of quantum network devices 21.

[0351] Used definitions, terms, and possible realizations

[0352] The following terms and definitions are used herein: Quantum computers, i.e. quantum circuits, as understood herein, are constructed from two elementary quantum building blocks, which are logic quantum bits (logic qubits) and quantum logic gates. The quantum logic gates form the fundamental building blocks of quantum circuits, acting as the essential logic elements that allows running of quantum algorithms, analogously to digital logic gates which are devices that acts as a building block for digital circuits. Quantum logic gates consist of an ensemble of qubits and entanglements between the qubits. The entanglements creating a unique connection in which altering one qubit instantaneously affects another. As digital logic gates perform basic logical functions that are fundamental to digital circuits, the quantum logic gates perform basic unitary operations by manipulating the state of qubits (A unitary operator is a surjective bounded operator on a Hilbert space, whereas a Hilbert space, which arises frequently in physics, is a vector space equipped with an inner product that induces a distance function for which the space is a complete metric space, i.e. that preserves the inner product). Figure 15 is illustrating exemplarily some known quantum logic gates.

[0353] In a digital circuit, logic gates work based on a combination of digital signals coming from its inputs. Most digital logic gates have two inputs and one output, and they are based on Boolean algebra. Depending on the type of digital logic gate being used and the combination of inputs, the binary output will differ. There are seven basic digital logic gates, namely: AND, OR, XOR, NOT, NAND, NOR and XNOR.

[0354] Analogously to digital logic gates, in quantum computing, quantum algorithms use quantum logic gates to execute computations. A digital logic gate is denoted as universal, if this gate can implement any Boolean function without need to use any other gate type. The digital logical gates NAND and NOR are universal gates. In practice, this is advantageous since NAND and NOR gates are economical and easier to fabricate and are the basic gates used in all IC (Integrated Circuit) digital logic families.

[0355] Regarding universality of quantum gates, it has to be considered that in contrast to many classical digital logic gates, quantum logic gates are reversible. However, it is possible to perform classical computing using only reversible gates. For example, the reversible Toffoli gate can implement all Boolean functions, often at the cost of having to use ancilla bits. The Toffoli gate has a direct quantum equivalent, showing that quantum circuits can perform all operations performed by classical circuits. Thus, the Toffoli quantum gate is a universal logic gate. In the present patent application, a set of universal quantum gates is any set of gates to which any operation possible on a quantum computer can be reduced, that is, any other unitary operation can be expressed as a finite sequence of gates from the set. For the present application, the used quantum gates can be drawn from a universal set of quantum gates. Testing if a set of quantum gates is universal can be done using group theory methods and / or relation to (approximate) unitary t-designs. Some universal quantum gate sets include: (i) The rotation operators Rx(θ), Ry(θ), Rz(θ) (usually denoted as Pauli gates (X, Y, Z)), the phase shift gate P(<p) and CNOT are commonly used to form a universal quantum gate set, (ii) The Clifford set {CNOT, H, 3} + T gate. The Clifford set alone is not a universal quantum gate set, as it can be efficiently simulated classically according to the Gottesman–Knill theorem, (iii) The Toffoli gate + Hadamard gate. The Toffoli gate alone forms a set of universal gates for reversible Boolean algebraic logic circuits, which encompasses all classical computation. Regarding reversibility, it has to be noted that most computation systems that form the basis of programming languages are usually deterministic in one direction (i.e. forward), but non-deterministic in the opposite (backward) direction. Most other known programming systems exhibit non-determinism in both directions. Common to both of these classes is that they lose information, because generally a previous computation state cannot be recovered from the current state. This has technical implications on the information processing and application of these systems. Reversible computing are computing systems wherein all computations are two-way deterministically, without logical information loss. This also applies to quantum computing, where each computation step must be reversible.

[0356] A Turing machine consists of (double-infinite) tape of cells along which a tape head moves in discrete steps, reading and writing on the tape according to an internal state and a fixed transition relation. It can be shown that Turing machine is capable of implementing any computer algorithm. A Turing machine is reversible, if it is locally forward and backward deterministic. Within this application, for simplicity, all classical Turning machines are assumed to be forward deterministic. In this context, a quantum Turing machine or universal quantum computer allows to capture and process any quantum algorithm, i.e. is capable of expressing any quantum algorithm as a particular quantum Turing machine, and, as such, is a computational equivalent to quantum circuits. Quantum Turing machines can be related to classical and probabilistic Turing machines based on transition matrices, i.e. there is always a transition matrix where its product with a matrix, representing a classical or probabilistic machine provides the quantum probabilistic matrix representing the quantum machine. Within this application, a system is r-Turing complete if it is able to capture any reversible Turing machine without garbage date. As discussed, any computation can be reversibilized, and thus, a r-Turing machine should be able to exactly compute what Turing machines in general can compute.

[0357] A logic qubit denotes herein a system with two basis states | 0) and | 1) (2-level quantum system), independently of its physical realization. The general quantum state of a logic qubit is a superposition (linear combination) co | 0) + ci | 1 ) with complex coefficients co, ci. A system of n logic qubits has 2nbasis states. The general state is a vector in a 2n-dimensional complex space. The transformation (evolution) of a state in a given time interval can be described by a unitary matrix of dimension 2nx 2n. As mentioned, quantum logic gates are unitary operators, and are be described by a unitary matrices relative to some orthonormal basis. Usually this computational basis is used, which means that for a d-level quantum system (e.g. qubit, quantum register, or qutrits and qudits) the orthonormal basis vectors are labeled | 0>, | 1> | d-l>, or use binary notation. In this application, the term qudit denotes a unit of quantum information that can be realized in suitable d-level quantum systems. A qubit register that can be measured to d states is identical to a d-level qudit (d-level quantum system). For quantum circuit design, qutrits (3-level quantum system, i.e. qubits that have one added dimension) often play a particular role, since quantum logic gates can also be realized using qutrit, i.e. quantum gates that operate using an ensemble of qutrits. Similar to how digital logic gates are the building blocks of digital circuits, qutrit quantum gates are in this case the building blocks of quantum circuits. As mentioned a qutrit can exist in a superposition of three possible quantum states, represented as | 0), | 1), and | 2), which functions as a generalization of the qubit. One of the advantages of qutrits is that they allow an improved decomposition of the Toffoli gate. For example, using only qubits, it would take at least 6 CNOTs to decompose the gate, whereas with qutrits it would be enough to use 3. Thus, besides the advantage associated with the enlarged computational space, the third qutrit level can be exploited to implement efficient compilation of multi-qubit gates. Within this patent application, it is generally referred to qubits, however, this also includes a possible realization with higher level quantum bits as qutrits or in general qudits.

[0358] In summary, for the present application, on the side of the logic realization, a quantum computation, performed by a quantum circuit, is a sequence of elementary unitary transformations (operations), each affecting an ensemble of entangled qubits denoted as quantum logic gates. The input to the quantum circuit can be encoded as a basis vector, e.g. having binary values, and the result (output) of the computation is defined probabilistically with the aid of projection operators (on the physical side realized by measurement of the output qubits), providing e.g. binary values.

[0359] Further, the term polynomial used herein in the context of computation and algorithms, is defined as follows: A computational problem is regarded as difficult, if it has no polynomial algorithm, where an algorithm is called polynomial, if the number of computational steps increases no faster than some power of the length of the input of the problem. It is to be noted that the notion of difficulty is defined related to the term computational complexity, which describes the scalability of algorithms that solve computational problems. Specifically, as the size of the input to an algorithm increases, at what rates do the computing resources (run time and memory requirements) grow. It is clear that this definition depends on the model of computations used. The majority of abstract computational models (the Turing machine, a machine with random access memory (RAM), and so on) are polynomially equivalent to one another. In other words, if an algorithm is processed by a Turing machine, which is able to produce the correct answer for any input string of length L in at most c Lksteps, where k and c are some constants independent of the input string, then the problem is referred to be solvable in polynomial time and is in the class called deterministic polynomial time (P). An algorithm with non-deterministic polynomial time (NP) consists of those decision problems whose solutions can be verified in polynomial time, however, there is no efficient way to determine a solution to such problems. NP-complete (NPC) problems are defined to include the most difficult problems in NP. NPC is the smallest subclass of NP that could remain outside P. A problem is in NPC if (a) it is in NP and (b) it is NP-hard, i.e., every other problem in NP is reducible to it (reduction is a transformation of one problem into another problem). Then it is said to be complete for NP.

[0360] Finally, many quantum algorithms contain larger Boolean parts. Such parts are sometimes referred to as oracles. Boolean parts can e.g. be queried with a highly superposed input to gain quantum speed-up. Examples are the modular exponentiation in Shor's algorithm for integer factorization or a Boolean description of the database that is queried in Grover's Algorithm. In order to use these Boolean components on a quantum computer, they have to be described as quantum circuits (i.e., a sequence of quantum operations represented by logic quantum gates), which are inherently reversible. The term synthesis denotes herein the process to determine a sequence of quantum operations (i.e. quantum gates) that realize a desired functionality. To synthesize a Boolean function, the Boolean function can be decomposed into several (not necessarily reversible) sub-functions. Hence, even though the overall functionality of any Boolean part needs to be inherently reversible, its sub-components may not be. In other words, quantum compilers for quantum circuit technology, like their classical counterparts, require that the compiler can translate from a human-readable input or programming language into operations that can be executed directly on quantum hardware. Circuit synthesis is an integral part of this compilation process. Given an arbitrary quantum circuit C and a universal gate set $, the synthesis process generates a decomposition,

[0361] UfcUfc-1... U2U1= C, with Uj e $

[0362] where k represents the depth of the circuit.

[0363] In the prior art, various synthesis methods currently exist to generate such a decomposition. They are generally divided into two classes: those that synthesize approximately (i.e. II

[0364]

[0365] - C IK E and those that synthesize exactly. Some procedures work for a single qubit, whereas others have been generalized to multiple qubits. Most of these synthesis methods are designed to work over the Clifford+T universal gate set, though other gate sets such as the V-basis also exist. However, many of the synthesis methods that perform exact synthesis fall victim to the fact that the time and space used depend exponentially on both the number of qubits and the depth of the circuit in question. Even on a reasonably fast machine, the synthesis of circuits with more than a handful of qubits and layers of depth becomes intractable. The inventive system does not have those disadvantages of the prior art since it, inter alia, allow providing computational blocks with the most minimal quantum information depth, possible.

[0366] Quantum error correction (QEC) is to encode information in subsystems of a larger physical space that are immune to noise. QEC can be used to define fault-tolerant logical qubits, through employing a subtle redundancy in superpositions of entangled states and non-local measurements to extract entropy from the system without learning the state of the individual physical qubits. Thus, QEC allows to perform fault-tolerant quantum computing, and thus technically allows to realize non-reversible functions in quantum logic by further adding qubits (herein referred to as ancillary or ancillae qubits) in order to make the output patterns distinguishable and, thus, obtain a reversible function. This process is called herein embedding, i.e. combining multiple physical qubits into a iogicai qubit or a logic quantum gate as an ensemble of qubits, where the logical error rate is suppressed exponentially as more qubits are added. Such additional qubits are often used to store intermediate results and have to be restored to their initial state by decomputing intermediate results) before leaving a quantum processing code (herein reference number 30). The correction can be autonomously achieved by an ensemble of physical qubits representing a logical qubit. This can also be used to realize quantum memory, which is defined herein as logical qubits that are sufficiently stable against local errors and allows essentially error-free storage. In any case, QEC is needed to realize practical, fault-tolerant quantum computation which always increases the number of physical qubits needed to realize a quantum processing code, i.e. the logic qubits representing the required logic quantum gates for the. In fact, even if the embedding process guarantees a minimum of ancillary or ancillae qubits, in the technical realization, their number can be substantial while physical qubits are a highly limited resource. Thus, there is a need to be able to decompose a quantum processing code, in particular its Boolean parts, to smallest parts as possible (herein referred to as computational block nodes 333) without affecting the overall quantum computation.

[0367] To synthesis such smaller parts, coded embeddings can then be used where each occurring output pattern is encoded with another unique pattern. This way, embedding and synthesis schemes can be used such as one-pass synthesis of reversible logic or any other synthesis exploiting coding techniques for the realization of quantum circuits. In the case, where QEC is realized by representing a logical qubit by an ensemble of physical qubits, the logical error per cycle can be reduced by more than half, each time the code distance increases by two, culminating in a distance-n logical lifetime more than double its best constituent physical qubit lifetime. This provides an exponential logical error suppression where code distance forms the basis of running large scale quantum algorithms with error correction. This method can also be used to realize quantum memory, where the logical error rate of even larger quantum memory can be suppressed by significant factors. The term franspilafion, as used in the present patent application for quantum computing, is not the same as synthesis and embedding. Transpilation, as used herein, is the process of rewriting a given input circuit to match the topology of a specific quantum device, and / or to optimize the circuit for execution on a specific noise level of a specific quantum system. With other words, quantum circuit transpilation and optimization are used in the patent application as terms denoting components of the quantum computing workflow, i.e. the algorithm generation, quantum circuit generation and quantum processor design. For the present application, similar to compilers in classical computing, transpiiers map iogicai quantum circuits to the instructions present physical quantum devices, and allow quantum circuit developers to focus on the quantum algorithms rather than specific details of the hardware. Optimized transpilation of quantum circuits (minimizing the overhead introduced in this mapping) is an important technical object for the field of quantum computing in general, but particularly relevant for near-term quantum computing hardware, where even small improvements on the transpiled circuit sizes can lead to important reductions in the noise present in the results. In contrast to transpilation, circuit synthesis denotes within the present patent application a task within the transpiling workflow and consists of generating a quantum circuit, within a given set of quantum gates, that implements a high-level description of a quantum operator. A typical workflow with circuit synthesis is to re-synthesize parts of a circuit to see if a more optimal circuit can be found and replace the original circuit parts if successful. With other words, circuit synthesis is defined in the present application as a sequential decision process where one decides at each step, for an operator Ot, which of the possible operations of the gate set to apply. Once a specific gate has been chosen (gt), the operator is derived based on the gate to obtain the next operator Ot+i. Starting from the input operator Oo (the operator to be implemented as a circuit) the decision process is repeated for a given number of steps T until the identity operator OT = I is reached. The circuit that implements Oo can be then recovered by inverting the circuit given by the sequence of gates go.j. Finally, it is to be noted, that quantum circuit synthesis can typically performed in different ways, e.g. (i) heuristic methods working with a specific gate set such that changing a gate set requires modifying the algorithm or incurs a further translation cost, (ii) databases of optimal circuits used to provide and assemble optimal circuits, however typically take longer times to generate, require large data storage, and are also fixed to specific gate sets, and (iii) generic optimization which typically allows to produce circuits tailored to a specific gate set, however at the cost of high running times.

[0368] Finally, another technical object for transpiling lies in scaling up quantum computers, which is referred to in the present applications as the technical problem of the connectivity of qubits. Unlike bits in classical computers, not every gate between every qubit is physically possible. This technical limitation is referred herein as the connectivity of the quantum chip. For example, considering a chain of qubits, where each qubit is connected to its left and right neighbor, or a 2d quantum chip, where each qubit is connected to its next neighbors, only gates between connected qubits can be realized. To still allow for all gates, typically quantum information is moved to neighboring position via SWAP or shuttling operations. For SWAP operations, SWAP gates are used. The primary function of a SWAP gate is to swap the states of two qubits. To perform such a swapping operation, the SWAP gate requires two qubits as inputs. After applying the SWAP gate, the state of the first qubit becomes the state of the second qubit, and vice versa. The SWAP gate is reversible, i.e. it can be applied again to restore the original states of the qubits. SWAP operations and gates play an essential role in quantum transpiling if the order of qubits in a quantum circuit needs to be rearranged or if information needs to be moved from one qubit to another (It is to be noted that there are also prior art systems which do not need or minimize SWAP operations for the realization of quantum computers, as e.g. systems using the ParityQC architecture. However, they come along with other technical problems). Within the present application, the term circuit routing refers to the important technical object of transpiling workflows by inserting SWAP operations on a quantum circuit to make two-qubit operations compatible with a given coupling map that restricts the pairs of qubits on which operations can be applied. Circuit routing faces similar challenges as circuit synthesis: there are heuristic algorithms but the resulting circuits are often far from optimal routing, especially in terms of circuit depth, and optimization methods have prohibitively high computational cost. Thus, quantum circuits with a smaller circuit depth can minimizing the problem of non-optimal circuit routing. Further, it is to be noted that optimal circuit routing is of particular significance for the execution time of quantum circuits in linear Quantum Charge-Coupled Devices (QCCDs), where SWAP gates are implemented by physically changing the position of the ions. Because SWAP gates are one of the most time-consuming operations in QCCDs, there is a technical need for an optimized transpiler workflow able to considerably reduce the runtime compared to circuits generated with standard compilers, like the TKET and Qiskit compiler. While increasing the problem size and therefore the number of qubits typically demands longer runtimes, which are constrained by coherence time, there is further a need for runtime reduction or at least limitation to only linear increase by simultaneously increasing the number of qubits at a given coherence time.

[0369] One of the technical problems further arises by the fact that many synthesis method only work for specific types of restricted connectivity graphs, so, in many cases, further routing is needed to run on real devices with architectures such as heavy-hex, resulting in a significant SWAP overhead. There are also full optimization methods based on SAT solvers (SAT solvers are computer programs directed to solve a Boolean satisfiability problem, i.e. a propositional satisfiability problem (also SAT or B-SAT), by determining if there exists an interpretation that satisfies a given Boolean formula, as e.g. an oracle. In other words, it asks whether the variables of a given Boolean formula can be consistently replaced by the values TRUE or FALSE in such a way that the formula evaluates to TRUE. If this is the case, the formula is called satisfiable. For example, on input a formula over Boolean variables, such as (x or y) and (x or not y), a SAT solver outputs whether the formula is satisfiable, meaning that there are possible values of x and y which make the formula true, or unsatisfiable, meaning that there are no such values of x and y. In this case, the formula is satisfiable when x is true, so the solver should return "satisfiable". For computational complexity, the Cook-Levin theorem states that a Boolean satisfiability problem is NP-complete. That is, it is in NP where any problem in NP can be reduced in polynomial time by a deterministic Turing machine to the Boolean satisfiability problem.) that offer complete flexibility in terms of connectivity but scale exponentially with the number of qubits and circuit sizes and are not practical for larger circuits. In the context of qubit routing, computationally efficient algorithms and methods exist in the prior art that can be used for larger systems (127+ qubits). However, they typically produce transpiled circuits that are far from optimal in terms of circuit depth, and they cannot directly leverage local circuit optimizations (e.g., cancellation of two consecutive CNOT gates). Full optimization methods based on SAT solvers can produce optimal or near-optimal circuits and can leverage gate optimizations, but they scale exponentially and are not feasible in a practical environment beyond 8-10 qubits.

[0370] In terms of the physical quantum layer (see below) of quantum circuits, the prior art offers several examples in the areas of synthesis, optimization, mapping and / or compilation. The present patent application is focused on the logical quantum layer, and, therefore, where it is not explicitly noted, for the physical layer, the inventive system builds upon existing state-of-the-art procedures and systems. The inventive system focuses on applying the inventive generic quantum computing circuit and processor design and inventive generic auto-transpiler to quantum circuit transpilation and optimization on the logical layer side. The particular architecture for implementing a fault-tolerant operating scheme depends on the requirements necessary for the underlying physical qubits. One possibility to achieving quantum fault-tolerance is by realizing a two-dimensional surface code. This code typically has a high tolerance to errors, or threshold (approximately 6.7 * 10-3), requires only nearest-neighbor qubit interactions, has simple error syndrome extraction circuits, and a suite of fault-tolerant logic based on transversal gates, code deformation, or lattice surgery. Thus, a quantum circuit, as used herein, can e.g. be assembled by using (i) physical qubits that are well isolated from the environment and are capable of being addressed and coupled to more than one extra qubit in a controllable manner, (ii) a fault-tolerant architecture supporting reliable logical qubits, and (iii) universal gates, initialization, and measurement of logical qubits.

[0371] Figure 16 shows an example of a fault-tolerant quantum computing circuit design (or quantum computing system comprising a plurality of circuits) illustrated by a layered structure. The system is comprised of two primary layers: a physical qubit layer and a logical qubit layer. The lower physical layer contains physical qubits controlled via a QEC processor, which can e.g. be realized as a classical processor that uses measurement outcomes of the physical qubits to realize a QEC code. This processor keeps track of the physical errors that arise, and implements the appropriate feedback on the controls of the physical qubits. The upper layer of figure 16 is referred herein as logical layer and functions through control of the physical layer. In the present inventive system, logical qubits are encoded within a fully error-corrected system of physical qubits, and logical controls and readouts are controlled and steered through a processor determining a specific implementation for a quantum algorithm, which is a synthesis of a computation to be performed as e.g. oracles, Shor's, Grover's, and any other quantum simulation. In figure 16, residing at the very bottom of the physical qubit layer, there are the physical qubits, which can be explored in a variety of different systems, as for example, superconducting qubits, trapped-ion, solid-state spin, nuclear spin, non-linear photonic, and neutral atom qubits. It is to be noted, that these are just a few examples of possible qubit systems allowing to realize multi-qubit operations. The present invention is not limited to any concrete realization of the physical qubits, as long as the particular architecture for implementing the fault-tolerant operating scheme has bearing on the requirements necessary for the underlying physical qubits, as provided by the present, inventive system for generic quantum computing circuit design. Coherence times in such systems may vary. However, for the purposes of the present invention, it may be important to normalize coherence to the gate (control) lengths possible for the system. Especially if superconducting qubits are used for the realization of the quantum circuit(s), with e.g. coherence times in the -100 s range and gate lengths -10-100 ns, the number of operations per coherence time currently approaching 104 operations, and may increase in future.

[0372] Inputs and outputs to the layer of physical qubits are controls and readouts, respectively. In the example of superconducting qubits, controls can comprise various microwave electronics and pulse-shaping, to realize specific qubit rotations and two-qubit controlled operations. The noise on these controls can e.g. be filtered and attenuated so that the noise at the qubit is negligible. In the case of superconducting qubits, it can also be important for readout to be boosted through stages of amplification, the first of which is quantum-limited. Analog readout signals can then be digitally processed either on classical computers or in customized field-programmable gate arrays (FPGAs) for fast processing. Figure 16 illustrates schematically an example of a physical layer for superconducting qubits. The quantum error correcting process can e.g. be performed at room temperature, however, it is also possible that at least some of this operation may be performed at lower temperatures stages e.g. within a dilution refrigerator.

[0373] The particular arrangement of physical qubits is governed by a specific selection of a fault-tolerant error correction architecture. With high error thresholds and simple physical lattice arrangement, the rotated surface code (RSC) can e.g. be used as schemes for QEC. The RSC code has the advantage that it typically requires less qubits than other standard surface code. The QEC processor (see figure 16) sits above the physical controls and readouts and functions to keep the lattice in a simultaneous eigenstate of Z-parity and X-parity stabilizers which can be implemented by the circuits. The order of the controlled-NOT (cNOT) gates is important for fault-tolerant operation to ensure that all error syndrome bits correctly identify single error faults anywhere in the extraction process. In each cycle, d2-l syndrome bits are extracted, and, in the absence of errors, the syndrome bit will have the same value every cycle. Each time the syndrome bit changes value, an endpoint of a chain of errors can be identified. From these chains, Edmonds' minimum weight perfect matching algorithm can e.g. be used to find the set of corrective operations. Corrections can e.g. be applied to the classical data associated with the measurement results rather than to the actual physical qubits. This ensures that no corrective operations need to be applied to the qubits (no additional errors) and no complicated feedback is necessary. In the example of the superconducting qubits, a code can be realized using coupling between the data qubits and the syndromes by using a quantum bus. Each bus e.g. couples to different (e.g. four) data qubits and each qubit couples to two buses allowing a tiling that achieves the connectivity required for the RSC. Using this tiling and provided the gate is directional and a minimum of five frequencies is required to allow selective two-qubit gates. In the example of the superconducting qubits, for example, coplanar waveguide microwave resonators can be used for the bus. With an error-corrected sea of physical qubits, it becomes then possible to enter the logical layer of figure 16. In the RSC only the logical Hadamard can be implemented transversally (i.e. the logical gate is represented by the product of operations on the single qubits) up to a rotation of the code. The cNOT gate, which has a lower overhead, is provided by lattice surgery. It is known that RSC or any 2D stabilizer code cannot implement all universal gates transversally. Thus, methods such as distillation and injection may be needed. It is to be mentioned, that the distillation process for the T gate usually needs the largest number of physical qubits. With these logical operations all quantum gates can be implemented efficiently, for example, using the Solovay-Kitaev algorithm or other optimizations.

[0374] Finally, at the top of the logic layer sits the application of the quantum computing providing the possibility to perform any synthesized quantum algorithms. Known examples of such synthesized quantum algorithms may be Shor's factoring, Grover's search, or digital quantum simulations of real world chemical molecules and dynamics.

[0375] The inventive system of this patent application focuses primarily on the upper section of the diagram of figure 16. Specific challenges depending on the choice of physical qubits towards implementing a fully-error corrected surface of physical qubits, i.e. in respect to a specific physical realization of the quantum processor by a specifically selected realization of physical qubits are not part of the present inventive quantum system. Thus, the inventive system of the present patent application mainly focuses on the technical challenges associated with the realization of the logic layer. Nevertheless, solving the technical challenges associated with the logic layer strongly influences the feasibility and implementability of the quantum circuit and quantum information processor, as such, in particular as a scalable, generic usable, and fault-tolerant quantum computing circuit and / or system.

[0376] The present inventive r-Turing complete, universal quantum computing system and quantum processor design allows to provide programmable reversible quantum computing based on quantum information processing. Typically, for programmable generic computing devices, two main combinatorial units are technically distinguished: the control unit and the arithmetic logic unit (ALU). The former derives from instructions the control signals that determine the operation of the arithmetic logic unit, which then combines the operands of the instruction to produce a result. Which instruction is selected next by the control unit may depend on the result calculated by the arithmetic logic unit. This feedback to the control unit is essential for the computations that can be programmed. The arithmetic logic unit is central for the design of the instruction set of a programmable computing device. The functionality provided by the arithmetic logic unit determines the possible set of data instructions (control instructions, the other part of an instruction set, are determined by the operation of the control unit). The basic structure of a stored-program computer, also known as von Neumann architecture, has remained almost the same despite changing technologies, such as relays, vacuum tubes and transistors. In the present invention, the non-localized quantum network devices 21 interacting with the control unit 20 allow to realize the task of the classical arithmetic logic units. It is to be noted that the inventive quantum network devices 21, thus, may be used as a fundamental building block of many types of computing circuits and quantum computing circuits, including corresponding central processing unit (CPU) of quantum computers, quantum floatingpoint units (FPU), and / or quantum graphics processing units (GPU).

[0377] The present invention allows to apply this fundamental scheme in the context of reversible computing and reversible logic as realized by quantum gates. Reversible logic is a core part of the quantum circuit where each reversible logic gate has a corresponding quantum version. It is to be noted, that the inventive synthesis can e.g. also be based efficiently on databases with optimized quantum circuits used to provide and assemble the quantum network devices with a minimal circuit depth. Thus, the inventive system does not need to rely on generic approaches as the Bennett approach implementing quantum (reversible) embeddings of processing codes. The inventive system 1 provides reversible quantum network devices 21 as quantum processing units or reversible arithmetic logic units that are then an essential part of the programmable reversible quantum computer system 1. The addition of control to a reversible circuit is essential and necessary for higher level of control in a reversible computing system, as quantum processors, integrating elementary controlled gates into a more complex controlled system. Typically, the integration of multiple functions into a single quantum circuit comes at the expense of logical depth and the number of quantum gates. The inventive system 1 has inter alia the advantage that it allows for the design of a reversible quantum network devices to maximize performance and to minimize resource costs, and on the other hand to identify a set of reversible data instructions that is expressive for programming while making it easy to build the device. As such, the inventive quantum system does not have said technical problem of the prior art systems. It is a technical effect of the inventive system, firstly, to provide a simple generic design of required quantum circuits and, secondly, to reduce the logic width, the logic depth and the number of gates of the quantum circuits used to process a quantum processing code (e.g. involving reversible arithmetic logic units), rather than to provide a large set of data instructions. Thus, the achieved quantum processor using the inventive reversible quantum network device (herein ref. number 21), disclosed by the present invention, combined with a suitable control unit (herein ref. number 20), permits the design of a r-Turing-complete and fully programmable reversible quantum computing device.

[0378] Detailed Description of the Preferred Embodiments

[0379] The subject matter of the patent applications PCT / EP2021 / 079873, PCT / EP2024 / 061258, PCT / EP2023 / 060677, and PCT / EP2024 / 061271, are explicitly incorporated herewith, by reference.

[0380] In the drawings, like reference numerals designate identical or corresponding parts throughout the several views. Further, as used herein, the words "a," "an" and the like generally carry a meaning of "one or more," unless stated otherwise. Furthermore, the terms "approximately," "approximate," "about," and similar terms generally refer to ranges that include the identified value within a margin of 20%, 10%, or preferably 5%, and any values therebetween.

[0381] (i) The controlled quantum circuit 2

[0382] This patent application discloses a novel universal, r-Turing complete quantum computing system 1, quantum circuit 2 with parallel quantum network devices 21, each representing its own closed quantum circuit and / or quantum processing unit (QPU), in particular a universal quantum computing system 1 for a fully programmable, reversible Turing complete quantum computing device and quantum computer 1, e.g. comprising reversibly operatable quantum network devices 21 (e.g. able to work as arithmetic logic units processing Boolean parts of a source code 3, as described above). The quantum computing system can further comprise mixed components, i.e. quantum circuits and classical computer components, where, for example analog readout signals of the quantum circuits or quantum processor can then be further digitally processed either on classical computers or in customized field-programmable gate arrays (FPGAs) for fast processing, or inputs can be controlled by a classical control unit.

[0383] Figure 39 schematically illustrates a block diagram of a r-Turing complete, universal quantum computing system 1. The quantum computing system 1 comprising a quantum circuit 2 composed of a plurality of parallel operatable quantum network devices 21. Each quantum network device 21 represents its own quantum circuit not interacting with other quantum network devices 21 during one cycle of operation, i.e. each quantum network device 21 represent closed quantum wave function not overlapping in time. As its own quantum circuit, each quantum network device 21 comprises one or more quantum logic gates 211 providing computations steps by one or more unitary operations 30, the quantum network devices 21 being synchronized in time. More generally, a quantum network device 21 as Quantum Processing Unit (QPU) denotes the logical and physical processing unit that uses qubits to process one or more unitary quantum operations. Herein, a quantum logic gate 211 is a device performing a fixed unitary operation 30 on an ensemble of logic qubits 2111 correlated by quantum entanglements 213. For each quantum network device 21 one or more logic qubits 2111 form an input quantum register 214 to the respective quantum network device 21 and one or more logic qubits 2111 form an output quantum register 215 to the respective quantum network device 21. An output quantum information signal 2151 of an output quantum register 215 is at least partially transferable to an input quantum register 214 of another quantum network device 21 as input quantum information signal 2141 by a control unit 20. The quantum network devices 21 perform the one or more unitary operations 30 as computational steps processed by its quantum logic gates 2111 synchronously and in parallel within one clock cycle 201. As discussed in more details below, auto-parallelizing a higher level monolithic program code 3 to parallel operatable quantum operation blocks with a definable quantum information depth is central to the inventive quantum computing system 1. For that, the present invention uses a generalized novel concept of mapping monolithic code 3 to unitary operation blocks processable by the one of the parallel network devices 21 and scheduling them for execution based on a limited set of elementary instructions. Such an operation block is herein referred as computational block node 333. Executing a source code 3 on a parallelized quantum computation system has a general preparation and execution stages: 1) Allocate logical qubits within each quantum network devices 21 of the quantum circuit 2 used; 2) Remap quantum network devices 21 for the possibly parallel qubit assignment; 3) Generate a schedule for the control operations; 4) Distribute and execute the schedule; and 5) Assess the quantum information outputs of the quantum network devices 21.

[0384] Some source codes 3 have a particular structure that allows them to gain horizontal speedups when parallelized. However, the possible speedups are only one of the advantages. The main advantage of the inventive quantum computing system 1 lies in the minimal information depth 3331 of the computational block nodes 333 decomposed from the source code 3, which are achieved by the inventive autoparallelization and mapping of the source code 3 to the computations block nodes 333 by the synthesis system 11. This minimal information depth 3331 of the computational block nodes 333 leads to a minimal circuit depth 217 of the quantum network devices 21 as quantum processing units (QPU) on the quantum information level of the quantum circuit 2. This technically allows the first time to provide a programmable, reversible Turing complete, universal quantum computing system 1, having the advantage of being simply programmable in a high level source code language 31, as e.g. C / C++ 311, phyton 312, Java 313, Fortran 314, or OpenCL (Open Computing Language) 315, among others. Id est, the inventive quantum system 1 proposes a reversible quantum logic and quantum cellular automata overcoming the technical disadvantages of the prior art quantum systems.

[0385] For the inventive staged process of preparation and execution, a quantum network device 21 (also QPU: Quantum Processing Unit) structure can be described as collection of integers Q =[qi qk] representing a network of k QPUs where each QPU i has qi e N logical qubits. For the inventive system 1, it can e.g. be implied that the quantum network topology is completely connected, where entanglement units are created during runtime. However, the quantum network devices 21 can e.g. also be realized as universal arithmetic logic quantum circuits, where such an arithmetic and logical quantum circuit is restricted to processing the small set of basic arithmetic and logic functions given by the basic set of elementary instructions 322. The limited basic set of elementary instructions 322 allows to have quantum network devices 21 with a small and controllable circuit depth. The logical basic operations may comprise AND, OR, EXOR, NOT, NAND, Copy, Equal, Constant. The arithmetic operations may comprise operations like add, add with carry, subtract, subtract with borrow, two's complement, increment, decrement and transfer operation.

[0386] With the above described the system 1 derives a quantum parallel code as sequences 35 of unitary operation 216 representing the elementary instructions 32 of a computational block node 33, which are then decomposed in a corresponding sequence of logic quantum gates 211. Thus, the inventive quantum parallel code P is the instruction-set needed to perform the execution of the monolithic source code 3 by the parallelized quantum network devices 21 of the quantum circuit 2 including the logical circuit and the number of times to repeat the execution. A schedule S(i) is a mapping from an execution-round number i to sets of integers, where | S(i) | is always the number of quantum network devices 21 (QPUs) in the parallelized QPU network. Thus, the k-th set of S(i) represents the quantum parallel codes Ptc where there

[0387]

[0388] are n quantum parallel codes total to run, executing at time i on the quantum network device k where two distinct sets in S(i) are not necessarily disjoint. Thus, a parallel quantum code P = {{Pi Pn}, S(i), M}, generated by the inventive system 1, is formed at least by (i) a collection of quantum parallel codes Pi⊂ given the unitary

[0389]

[0390] operations of the computational block nodes 33 in the computational block chains 34, (ii) a function M: On→ O for O as the output of a code which acts as a central merging function, and (iii) a schedule.

[0391] Figure 38 illustrates an exemplary execution of a parallelized quantum processing code 301. The system 1 starts at time i =0, loading the programs specified by S(i), i.e. the i-th set of the parallel sets S(i) of unitary operations 3011 to the respective quantum network device 21 (QPU) until all r rounds are ran. The quantum outputs of the parallelized, distributed program sets S(i) unitary operations 3011 are accumulated in an output vector y during execution. Finally M maps the collection of n quantum outputs y to a single output. In the control unit 20 of the present inventive quantum computing system 1 and the auto-parallelized quantum circuit 2, respectively, can e.g. comprise a parallel quantum program scheduler 113. A program code 3, for example having iterative parts, mapped to the computation block nodes 333 and scheduled using the quantum program scheduler 113 shows in the iterative part a horizontal speedup, which is a run-time speedup achieved by allocating maximal quantum processing units, i.e. quantum network devices 21, to run in parallel. The parallel allocation is maximal, since the quantum information depth 3331 of the inventive computation block nodes 333 can be proven to be minimal. Thus, to generate P, i.e. the collection of computation block nodes 333 and schedule, parallel quantum program scheduler 113 can be used. Input to parallel quantum program scheduler 113 is (i) the specifications of the quantum network devices 21 referred to as Q =[qi qn], (ii) the quantum network devices 21 input to P with width w, that is, the number of qubits simultaneously needed to run a computation block node 333 by a quantum network device 21, (iii) a scheduling processing structure 203, referred here as A, which takes Q as input and determines an allocation for w logical qubits or determines no allocation exists, and (iv) the collection of no further decomposable, monolithic computation block nodes 333 with {Pj}"=1. The output of the parallel quantum program scheduler 113 is a schedule for executing the computation block nodes 333, which can be executed in parallel, in parallel as

[0392]

[0393] see figure 38.

[0394] For example: {Pi Pt} is a collection of f computation block nodes 333 decomposed by the synthesis system 11, that are to be processed by the quantum network devices 21 having a logical qubit width of w, and a quantum network device structure of n quantum network devices qi to qn. The parallel quantum program scheduler 113 then allocates the w qubits of each of the quantum network devices 21 and further allocates the computation block nodes 333, which are to be run in parallel. The output of the parallel quantum program scheduler 113 comprises the sets S(0), S(l) S(k), wherein the computation block nodes 333 of a set S(i) are processed in parallel in step or cycle i, and wherein a set S(i) is given by the i-th column of the computation matrix 1151 decomposed from the program code 3 by the synthesis system 11 and the matrix builder 115, respectively. Thus, the computation block nodes 333 of a set S(i) are distributed between the quantum network devices 21, so that they run in parallel. If there are not enough parallel quantum network devices 21 as QPUs, the processing of the computation block nodes 333 within one column of a computation matrix 1151 is distributed on two or more processing cycles, for example S(i) and S(i+1), depending on the number of computation block nodes 333 in the respective column and the number of available QPUs 21. In the iterative example of program code 3, discussed above, the iterative parts mapped to the computation block nodes 333 and scheduled using the quantum program scheduler 113, thus, shows in particular in the iterative part a horizontal speedup, which is a run-time speedup achieved by allocating maximal quantum processing units, i.e. quantum network devices 21, to run in parallel. It is clear that influencing this speedup is, inter alia, the scheduling processing structure 203 used to allocate qubits for distributed processing. In the prior art, there are various scheduling processing structure 203 known, For example, an allocation by the scheduling processing structure 203 may simply choose qubit allocations randomly will likely introduce more non-local gates, potentially diminishing potential speedups due to the needed additional logic, whereas if the topology and connectivity of the quantum processing units, i.e. the quantum network devices 21, is considered, the number of non-local gates can be minimized. Another possibility addresses qubit allocation as to reduce the quantum network device width in a quantum network device 21 using e.g. circuit cutting to run parts of the quantum network device 21 independently and then uses classical post-processing to combine outputs. A scheduling processing structure 203 should further aim to minimize the classical post-processing overhead. The inventive quantum system 1 defines parallel program, i.e. parallel computation block nodes 333, to then execute the overall quantum circuit over the cluster of parallel QPUs given by the structure of the computation matrix 1151 decomposed from the program code 3 by the synthesis system 11 and the matrix builder 115, respectively.

[0395] It is to be noted, that correct parallel-scheduling the quantum network devices 21 by the quantum program scheduler 113 is important. This is because, the multi-programmed quantum network devices 21 can have an adverse impact on the reliability of the individual workloads. To enable parallel-scheduling of the quantum network devices 21 in a robust manner, there are various possibilities. For example, the qubits can be portioned into multiple reliable regions using error information from machine calibration so that each quantum processing code 30 can have a proper allocation of reliable qubits. Further, in some cases, it may be observed that when two parallelized quantum processing codes 301 are of unequal lengths, measurement operations 203 / 2031 can impact the reliability of the co-running quantum processing codes 301. To reduce this interference, a delayed instruction scheduling policy can be used and / or implemented in the quantum program scheduler 113 delaying the start of the shorter quantum processing code 301 so that all the measurement operations 203 / 2031 can be performed at the end. Finally, an adaptive multi-scheduling structure can be used that monitors the reliability at runtime and adapts the quantum scheduling if the reliability impact of the parallel-scheduling is greater than a predefined threshold.

[0396] As illustrated in figure 39, the program code 3 is firstly decomposed to the computational block nodes 333 of elementary instructions 32 resulting in corresponding matrices generated by the matrix builder 115. The matrices comprise computational matrices 1151, transfer matrices 1152 and / or task matrices 1153, where the last two are also used by the control unit 20 to steer the cycle process 202 processing of sets of parallelized quantum processing code 30 / 301 by processing cycles 2011. The matrix elements of the computation matrix 1151 are the computational block nodes 333, where the program code 3 is decomposed by the synthesis system 111 the minimal parallel codes of elementary instruction 32 / 321 / 322 / 323 / 324 / 325 processable by the quantum network devices 21 in parallel. Computational block nodes 333 of one column of the computation matrix 1151 are processed in parallel by the quantum network devices 21 within one cycle 2011. Only, if the number of parallel quantum network devices 21 is not enough to process all of the computational block nodes 333 of one column of the computation matrix 1151, more than one cycle is used to process one column. The computational block nodes 333 of elementary instructions 33 are then mapped to corresponding computational block nodes 333 of a sequence 35 of unitary operation 216 representing the elementary instructions 32 of a computation block node 333 (see figure 39). The sequence 35 of unitary operation 216 of a computation block node 333 is then mapped to the corresponding quantum logic gates 211 having the entanglements 213 by the synthesis system 11.

[0397] The computation block nodes 333 are composed of the elementary instructions 32 / 321 325. Further, as mentioned above, many computational block nodes 333 can e.g. contain Boolean parts (also referred to as oracles) that can e.g. be queried with a highly superposed input to gain additional quantum speed-up. In order to use these elementary instructions 32 / 321 325 on the quantum network devices 21 as quantum processing units, they have to be described as quantum circuits (i.e., a sequence 301 / 3011 of quantum operations 3012n that are applied to the qubits 211), which are inherently reversible description means. To determine the sequence of quantum operations (also denoted quantum gates) for the parallel quantum network devices 21 realizing the desired functionality a process synthesis is performed by the synthesis system 11, the elementary instructions 32, in particular the Boolean functions, to be realized can also be decomposed into several (not necessarily reversible) subfunctions. Hence, even though the overall functionality of the computational block node 333 is inherently reversible, its sub-components may not be. In order to realize non-reversible functions in quantum logic, further qubits (also referred to as ancillary, ancillae, or working qubits) can be added in order to make the output patterns distinguishable and, hence, obtain a reversible function. This process is herein referred to as embedding.

[0398] As an optional embodiment variant (see figure 39), at least some of the quantum network devices 21 are used as SWAP registers 218 holding intermediate results during a processing cycle and have to be restored to their initial state by decomputing intermediate results before the quantum information 2151 measured at the output register 215 leaves the quantum network device 21. As mentioned, such quantum network devices 21 used as intermediate holding computational block nodes 333 are herein referred to as SWAP registers (not to be confused with SWAP qubits for providing connectivity between the quantum gates). Since the input to computational block nodes 333, i.e. the corresponding quantum network devices 21 processing said computational block nodes 333, of a subsequent column of computational block nodes 333 depend on the output result of one or more computational block nodes 333 of the preceding column, the wave function of a quantum network devices 21 has to be closed for each quantum network devices 21 (i.e. should not overlap), since otherwise e.g. for multi dependencies between the subsequent and consecutive computational block nodes 333, the proper information transfer is destructed. It is worth noting that information transfer typically assumes that the qubits are individually addressable, meaning that the qubits are distinguishable and physically labeled. As discussed, there can be situations where two identical qubits are indistinguishable due to the spatial overlap of their wave functions (which is typically given within a quantum network device 21). Under this condition, the qubits cannot be individually controlled or measured. Nevertheless, the quantum information can still be assessed, e.g. by a teleportation protocol, which can still be (conditionally) implemented by exploiting two independently prepared qubits, with no need of an initial Bell state. This can be made by addressing the internal degrees of freedom of the qubits (e.g., spins or polarizations) by spatially localized measurements performed in separated regions where the two spatially overlapping, indistinguishable qubits can be found. As an embodiment variant, this can e.g. be verified via polarized photons in a quantum optical setup. Thus, in the standard embodiment variant of the quantum computing system 1, the processing of a computational block node 333 by the quantum network device 21 consists of (a) an initialization stage in which the quantum network device 21 is prepared in the n-qubit computational basis state, (b)a processing stage in which the sequence 35 of unitary gates 216 of the quantum network device 21 is applied, and (c) a read-out stage in which the result of the quantum information processing is read out by measuring the quantum output register 215 of the quantum network device 2 as sub-set of the qubits of the quantum network device 21. Id est, the optional step, illustrated in figure 39 by dotted lines, is not conducted and no additional SWAP register are included in on processing cycle. For each column of computational block nodes 333 of the computation matrix 1151, the measuring 203 / 2031 is performed before initializing the quantum network devices 21 to perform the next quantum processing step given by the computational block nodes 333 of the subsequent column. This standard embodiment variant has the advantage, that it allows to realize a r-Turing complete, universal quantum computing system 1 programmable in a high level language. However, the processing time gained by the high parallelism of the inventive system 1 and its minimal computational block nodes 333 may be annulled or even overcompensated by the time needed by the measuring 203 / 2031. The measurement 203 / 2031 can e.g. be realized by a Bell measurement and then teleport the quantum gate from the preceding quantum network device 21, i.e. the corresponding computational block node 333, to the subsequent computational block node 21. The standard embodiment variant allows to implement the computational block chain 34 as fault-tolerant construction of quantum gates 211. It is to be noted, that because of the entanglement, the measurement 203 / 2031 of a qubit will collapse the other qubit to a state whose measurement will yield one of two possible values, where the value depends on which Bell's state the two qubits are in initially. As such, Bell measurement a joint measurement of two qubits that determines in which of the four Bell states the two qubits are in, where the Bell states are the four states that can be created when two qubits are maximally entangled.

[0399] In the optional embodiment variant by using parts of the computational block nodes 21 as SWAP registers, as discussed above, the results from the output register 214 have to be compressed for the quantum information 2151 / 2141 transfer to the input register 214 subsequent quantum network device 21, so that the wave function of the preceding computational block node 333 is decupled from the wave function of the subsequent computational block node 333 to be processed by the quantum network devices 21 as quantum processing units. In this optional measurement approach for the quantum information processing, for example, only two operations can be used, namely, the storage of qubits as quantum memory, and nondestructive, projective measurements on the qubits of the output register 215 of a quantum network device 21 at a time. It is to be noted that no coherent dynamical operations are involved in this approach, contrary to most of the prior art quantum systems where such operations are crucial to for the quantum information processing. Further, it has to be noted that, e.g. controlled-NOT and single-qubit unitary operations can be sufficient for the realization of the inventive universal quantum system 1. Finally, quantum measurement 203 / 2031, as used herein, is a powerful element that can be performed during the quantum computation. By combining the quantum measurements 203 / 2031 with the preparation of the cluster of quantum input states for the quantum input registers 2141 of the quantum network devices 21 of the next processing cycle 2011.

[0400] As an even further embodiment variant, the number of required measurements 203 / 2031 can be minimized, while holding the error-proneness of the quantum system 1 below a definable threshold. Prior art quantum systems, relaying on many-qubit processing, have only are known to achieve a 99.99% - 99.9% fidelity entangling gates, which is far short of the ε < 10-10error rates needed for many applications (classical instruction on today computer achieve an error rate around 10-23). The quantum error correction, as applied herein and described above to realize high-fidelity logical qubits by distributing quantum information over many entangled physical qubits (auxiliary qubits), allows to protect against errors. One possibility is to is the so called surface code, which has error thresholds of up to 1%. If the physical operations are below a critical noise threshold, the logical error rate can be suppressed exponentially as the number of physical qubits per logical qubit increases. This behavior can be captured by the approximate relation εdfor error-corrected

[0401]

[0402] surface code logical qubits, while d is the code distance indicating 2d2- 1 physical qubits used per logical qubit, p and εdare the physical and logical error rates respectively, and pthr is the threshold error rate of the code. In any case, for a logarithmic circuit depth 217, the error rate increases linear, i.e. the error rate increases exponentially with the circuit depth 217. As discussed in detail below, the circuit depth 217 of the network quantum devices 21 representing a computational block node 333 can be proven to be minimal and no further decomposable. Experimentally, it can be shown, the averaged number of elementary instructions 32 in a computational block node 333 is between 3 and 5 elementary instructions 32 having typically a maximum at 7 to 9 elementary instructions 32. For this, it is clear that also the number of required logic qubits to process a computational block node 333 is also small. Thus, the error rate for processing a computational block nod 333 is due to its minimal circuit depth also within a range, which is lower than the currently achieved 99.9% fidelity of prior art quantum systems. In this embodiment variant, the computational block nodes 333 of 2 or more columns in the computation matrix 1151 are linked, thus having a coherent connected wave function. For such linked computational block nodes 333 having a multi-dependency on more than one preceding computational block nodes 333, the preceding computational block nodes 333 have to be multiplied by the number of dependencies. Id est, if two subsequent computational block nodes 333 depend on the same preceding computational block nodes 333, the preceding computational block node 333 will be processed by two quantum network devices 21, each of which separately linked to one of the subsequent quantum network devices 21, processing the subsequent computational block nodes 333 depending on the same preceding computational block node 333. Thus, each of the line has a connected wave function over the entire dependencies, separately. Each column linked to a preceding column reduces the required measurements in minimum in the range of the number of computational block nodes 333 of a column of the computation matrix 1151.

[0403] In this embodiment variant, the control unit 20 can e.g. further comprise an error measuring device 204, determining an error rate ε 2041. In the present inventive programmable quantum system 1, to process the program code 3 as quantum processing code 30 in the scale of 3 to 9 elementary instructions 32 of the computational block nodes 333, quantum network devices 21 are required that contains an appropriate number of qubits with the noise suppressed to the subthreshold regime. These qubits must be coupled by controllable interactions to form a network. Generally, at the present levels of connectivity between qubits, the quantum network devices 21 can be found to moderately tolerate errors, i.e. the noise threshold is controllable. If the quantum network devices are realized in a manner where qubits lie in a one-dimensional (I D) array with nearest-neighboring (NN) interactions, an estimated error-rate threshold ranging from 10-7to 10-5per gate, and may reach 10-4. However when qubits form a two-dimensional (2D) array with NN interactions, the threshold may be about 1% per gate. In particular, the quantum network devices can be realized fault-tolerant in a 1 D array of qubits interacting locally but with a range beyond NN distance. Specifically in the inventive quantum system 1 considering the inventive segmented computational block chain 34, where each segment is a small region within which all qubits can couple directly, the error threshold may exceed 0.1% per gate with the present segment sizes, therefore fault tolerance in a 1 D qubit array is feasible in the sense that the error rate is realistic for fault tolerant quantum processing. In the discussed embodiment variant, where a column of the computation matrix 1151 may be linked to a preceding column to reduce the required measurements the error rate ε 2041 may be determined by the error measuring device 204 in dependence of the number of computational block nodes 333, which are linked and thus having a coherent wave function, i.e. in dependence of the circuit depth 217 (now involving more than one computational block node) and the range where decomposition of the entanglements in the circuit occur. The control unit 20 may, in this embodiment variant, comprise a threshold value for the maximal allowed error rate ε 2041. Is the threshold value reached by the measured error rate ε 2041, the measurement 2031 by the measuring device 203 is triggered to collapse the wave function, and the error rate propagation becomes linear, again. The measurements 2031 and 2041 are controlled by the control unit 20 and can be conducted via the quantum network controller 41 accessing the quantum network devices 21.

[0404] It is to be noted here, that most of the prior art system having a current noise level, which does not allow for deeper quantum circuits for more than 50 qubits. Uses of a relatively large number of qubits are therefore limited to shallow (constantdepth) quantum circuits. The present invention does exactly solve this technical object by generating computational block nodes at a circuit depth of 3 to 9 elementary instructions 32. The elementary instructions 32 are e.g. Boolean basic instructions 321 or other elementary instructions, as logical operation instructions 322, variable and array declarations operations 323, compare operation instructions 324, and / or code flow instructions / Memory operation / l / O operation 325. Boolean operations are of particular interest, since they allow a significant speed up by parallelization. The number of logic quantum gates 211 required to implement a Boolean operation as elementary instruction 32 depends on the specific Boolean function and the available quantum gate set. For example, for a single-bit Boolean function (e.g., NOT, identity), the required quantum gates are for a NOT operation (X gate in quantum computing) 1 quantum gate (X gate), or for an identity operation (I gate) 1 quantum gate (I gate). For Boolean operations 321 with two bits (such as AND, OR, XOR), quantum computation operates differently since quantum circuits must be reversible (classical AND, OR, and XOR are not inherently reversible), and additional qubits (ancilla qubits) may be required to ensure reversibility. A possible implementation of a XOR operation (which is reversible) is using 1 logic CNOT gate. A AND operation (irreversible, requires extra qubit) can e.g. be realized by a Toffoli gate (CCNOT), which consists of at least 5 single- and two-qubit gates in terms of basic quantum decomposition. An OR operation can e.g. be implemented using De Morgan's theorem with a combination of Toffoli, CNOT, and NOT gates. For functions with more than two bits, the Toffoli gate (controlled-controlled NOT) can e.g. be used as building block for reversible classical logic in quantum computing. However, more complex Boolean functions (like full adders, multiplexers) can require dozens to hundreds of quantum gates when mapped onto basic quantum gates (e.g., CNOT, Hadamard, T, and S gates). Thus, the circuit depth is decisive. The approximate quantum logic gate 211 costs are:

[0405]

[0406] Thus, the number of quantum gates required depends on: the Boolean function's complexity, the need for reversibility, and the availability of quantum primitives (e.g., Toffoli, CNOT, Hadamard). For basic Boolean logic like XOR, a single CNOT suffices, while for more complex operations like AND, Toffoli gates (which require multiple quantum gates) are necessary. If the computational block node 21 is realized using a full adder, bit-scaling for full adder in quantum computing have to be considered. A classical full adder is a combinational circuit that takes three input bits (A, B, Cin) and produces two output bits, namely Sum (S) and Carry-out (Cout). In quantum computing, logic must be reversible, which means additional ancilla qubits and quantum gates have to be used to construct a quantum full adder. Quantum logic gates 211 can be used for a 1 -Bit Full Adder. A full adder can be implemented using Toffoli (CCNOT) and CNOT gates. The number of gates required depends on the quantum circuit design. In general, a standard quantum full adder (-20-30 gates) requires at least 2 ancilla qubits for reversibility, further uses a combination of CNOT (XOR logic) and Toffoli gates (AND logic), where a decomposed Toffoli gate requires at least 5-6 basic quantum gates (CNOT, Hadamard, and T gates). Thus, a single-bit full adder typically requires 2-3 ancilla qubits (to store intermediate values), -5 Toffoli gates, and -20-30 total basic quantum gates when decomposed into universal gates. For an n-bit full adder (ripple-carry adder), the sum of each bit requires its own quantum full adder circuit, and the carry propagation across bits requires additional logic.

[0407]

[0408] Thus, a full adder scales linearly (O(n) ) in the number of quantum gates required. It is to be noted, that there are optimizations known in the prior art, which allow to reduce the scaling. Examples are (i) Carry-Lookahead Adder (CLA): Can reduce the number of gate delays by computing carries in parallel, reducing depth complexity, or (ii) QFT-based Adder: Uses Quantum Fourier Transform (QFT) to perform addition more efficiently with O(nlogn)complexity.

[0409] In summary, many facts may increase the number of qubits needed to realize a computational block node 333. Even if the embedding process guarantees a minimum of ancillary qubits, their number may be quite substantial and has to be regarded carefully, since qubits are a highly limited resource. One technical advantage of the present quantum system 1 is, that the computational block nodes 333 have the minimal quantum information depth possible allowing to minimize the problem required ancillary qubits to realize the reversibility of the computational block nodes 333. Additionally, coded embeddings can e.g. be used where each occurring output pattern is encoded with another (smaller) unique pattern. This way, embedding and synthesis schemes can be used such as one-pass synthesis of reversible logic as well as synthesis exploiting coding techniques for the realization of the computational block nodes 333. Encoding outputs may further allow to significantly reduce the number of qubits to be minimal. For the inventive block nodes 333, it can be shown that this allows for the realization of computational block node 333 non-reversible subcomponents with at most one additional qubit only. It has to be reiterated that quantum computations are conducted by applying operations to qubits, which are entities that cannot only be in one of its two basis states (denoted | 0> and | 1 >), but also in any superposition of both. Typical operations acting on a single qubits are negating the state of a qubit (NOT operation, denoted by X or ®), setting a qubit into superposition (Hadamard operation, denoted by H), or conducting a phase shift by i (denoted by S). Moreover, these operations may be controlled by other qubits. Then, the operation is only conducted if all controlling qubits are in basis state | 1>. All these computations may be represented by means of circuit diagrams, where each qubit is represented by a horizontal line and quantum gates (i.e., operations that are applied to the qubits) on these lines determine (from left to right) in which order the respective operations are applied to the qubits (cf. figures 40a / b). Reversible circuits are a subset of quantum circuits. Hence, these circuits are e.g. used when designing Boolean components of the elementary instructions 32 for the computation block nodes 333 and can e.g. be composed of multiple-controlled Toffoli gates. These gates are composed of a (possibly empty) set of control qubits and a so-called target qubit. The value of the target qubit is inverted if, and only if, all control qubits are in basis state | 1>. Hence, the CNOT gate discussed in figures 40a / b are a multiple-controlled Toffoli gate with a single control.

[0410] Figures 40a and 40b show two diagrams illustrating the realization of quantum circuits to build the computational block nodes 333 (fig. 40a: quantum circuit; fig. 40b: reversible quantum circuit). The quantum circuit shown in fig. 40a is composed of two qubits and two gates. First, a Hadamard operation is applied to qubit qo, setting qo into a superposition. Afterwards, a controlled NOT (CNOT) operation is conducted, where qo serves as control qubit and qi is the target qubit. Here, the value of qi is inverted if qo is in the basis state | 1>. Figure 40b illustrates the mapping of the logic quantum circuit of figure 40a to a reversible quantum circuit. The reversible quantum circuit shown in fig. 40b is composed of three qubits and four gates. The target qubit of a Toffoli gate is again denoted by ®, whereas control qubits are denoted by •.

[0411] Additionally, the intermediate values of the qubits are labeled throughout the circuit when applying | qoqiq2> = | 000> as input. Since a reversible circuit can be modeled in the classical domain (no quantum effects are exploited), 0 and 1 are used here to indicate the basis states (rather than | 0> and | 1 >). The first gate has not control qubits and, thus, inverts the value of qo from 0 to 1. The second gate is controlled by qo. Since the value of qo is 1, the value of qi is inverted from 0 to 1. The second gate does not affect the state of the qubits, since the control qubit q2 is set to 0. Eventually, the last gate inverts the state of q2 from 0 to 1. As mentioned, ff the components occurring in computational block node 333 are complex, they e.g. can also be split into non-reversible parts by automated synthesis by the synthesis system 11 using prior art methods. But since quantum computations are inherently reversible, it has to be ensured that these sub-components are realized in a reversible fashion, i.e., as a function realizing a unique mapping from the inputs to the outputs and vice versa of the computational block nodes 333. To ensure a unique input-output mapping of a computational block node 333, the non-reversible function to be realized is embedded into a reversible one may have more variables. This embedding process can either be conducted by the synthesis system 11 explicitly or implicitly by using a synthesis scheme following a one-pass synthesis. The inventive embedding process provided by the synthesis system 11 can e.g. also comprise embedding physically swap qubits, if required, for the processing of the computational block nodes 333 by the quantum network devices 21. However, since physical SWAPs are mainly required challenge in scaling up quantum circuit due to the connectivity of qubits, the required physical SWAPs are, if necessary at all, very limited for the inventive system, since the circuit depth of the quantum network devices 21 is minimal. The term connectivity of qubits, as used herein, denotes a limitation of quantum circuits, coming from the fact, that unlike bits in classical computers, not every quantum gate between every qubit is physically possible. For example, having a chain of qubits, where each qubit is connected to its left and right neighbor, or a 2d quantum chip, where each qubit is connected to its next neighbors, only gates between connected qubits are realizable. To still allow for all gates, quantum information is moved to neighboring position via SWAP, i.e. shuttling operations. If required, such SWAP qubits are embedded by the synthesis system 11 during the synthesis process. It is to be noted, that the above mentioned advantage of minimal SWAP operation, is of particular significance for the execution time of the present quantum system 1 realized by linear Quantum Charge-Coupled Devices (QCCDs), where SWAP gates are implemented by physically changing the position of the ions. Because such SWAP gates are one of the most time-consuming operations in QCCDs, the present inventive quantum system 1 allows to considerably reduce the runtime of the quantum Fourier transform and the quantum approximate optimization structures on all-to-all spin approaches, compared to quantum circuits generated with standard compilers, like the TKET and Qiskit compiler. While increasing the problem size and therefore the number of qubits typically demands longer runtimes, which are constrained by coherence time, the runtime reduction with the present inventive system enables a significant increase in the number of qubits at a given coherence time due to the parallelism of the quantum network devices 21 without having this technical problem. However, when using QCCD, shuttling operations may still be required by default, as laser light may not be accessible in every part of the quantum chip. In summary, the synthesis system 11 also provides, if necessary, the required circuit routing consisting on inserting SWAP operations on a quantum network device 21 to make two-qubit operations compatible with a given coupling map that restricts the pairs of qubits on which operations can be applied. In the prior art, fast heuristic algorithms are known for circuit routing, however the resulting circuits are often far from optimal routing, especially in terms of circuit depth, and optimization methods have prohibitively high computational cost. The present invention has the technical advantage, to require only minimal circuit depth due to its high parallelism minimizing this technical problem of prior art system. Thus, the synthesis system 11 provides the inventive circuit synthesis by generating a quantum network device 21 as reversible quantum circuit within a given set of gates by implementing the higher-level description of the quantum operator mapped form the computational block nodes 333 provided in elementary instructions 32. A part of the circuit synthesis process can e.g. also comprise to re-synthesize parts of a quantum network device 21 by optimizing the generated quantum circuit, i.e. quantum network device 21, and replace the generated circuit parts if successful.

[0412] In an embodiment variant, the logical quantum network device 21 architecture, can e.g. be split into three zones. A storage zone can e.g. be used for dense qubit storage, free from entangling-gate errors and featuring long coherence times. Further an entangling zone can e.g. be used for parallel logical qubit encoding, stabilizer measurements and logical gate operations. Finally, a readout zone can e.g. enable mid-circuit readout of desired logical or physical qubits, without disturbing the coherence of the computation qubits still in operation. This architecture can e.g. be implemented using arrays of individual87Rb atoms trapped in optical tweezers, which can be dynamically reconfigured in the middle of the computation while preserving qubit coherence. In this embodiment variant, a quantum circuit 2 can e.g. be used with key upgrades enabling universal digital operation. Physical qubits are encoded in clock states within the ground-state hyperfine manifold (T2> 1 s) and stored in optical tweezer arrays created by a spatial light modulator (SLM). Presently, such systems allow to use up to 280 atomic qubits, combining high-fidelity two-qubit gates, enabled by fast excitation into atomic Rydberg states interacting through robust Rydberg blockade, with arbitrary connectivity enabled by atom transport by means of 2D acousto-optic deflectors (AODs). Central for this embodiment variant is a scalable control, where the AODs use frequency multiplexing to take in just two voltage waveforms (one for each axis) to create large, dynamically programmable grids of light. Fully programmable local single-qubit rotations can be realized through qubit-specific, parallel Raman excitation through an additional 2D AOD. Mid-circuit readout can be enabled by moving selected qubits about 100 μm away to a readout zone and illuminating with a focused imaging beam, resulting in high-fidelity imaging, as well as negligible decoherence on stored qubits. The mid-circuit image can be collected with a CMOS camera and sent to a field-programmable gate array (FPGA) for real-time decoding and feedforward. This embodiment variant allows to provide quantum network devices 21 by entangled systems of 3, 6, 12, 24 or 48 logic qubits 2111 or any number in between. With this embodiment variant, an error rate of approximately 0.1 for 48 logical qubits and non-local logical entangling gates, up to roughly an order of magnitude higher than prior art physical qubit implementations of digital circuits of similar complexity, which shows the benefits of a logical encoding for this embodiment variant. It is to be noted, that in this embodiment variant, one aspect of the logical quantum network device 21 is that individual logical qubits are controlled as the fundamental units, instead of individual physical qubits.

[0413] In the next step, as illustrated in figure 39, the transpilation system 12 provides a quantum circuit transpilation and optimization process. Similar to compilers in classical computing, the transpiler system 12 maps logical quantum circuits, i.e. the computational block nodes 333 mapped by the synthesis system 11 to their corresponding quantum logic gates 211 and entanglements 213, to the instructions present physical quantum devices, i.e. the quantum network devices 21. Since the present inventive system 1 provides a r-Turing complete, universal quantum computing system 1 programmable by a program code 3 in a high-level language 31, this has the technical advantage that it allows developers to focus on the programming algorithms rather than specific details of the hardware. The inventive quantum system 1 allows minimizing the overhead introduced in the transpilation mapping, which is an important technical advantage for the field of quantum computing in general, but especially relevant for near-term quantum computing hardware, where even small improvements on the transpiled circuit sizes can lead to important reductions in the noise present in the results.

[0414] (ii) The quantum synthesis system 11 and the transpiler system 12

[0415] As described above and in figure 39, the universal quantum computing system 1 comprises a synthesis system 11 for synthesizing and auto-parallelization of a source program code 3 in a source programming language 31 for execution by the quantum network devices 21 by translating the source programming language 31 (for example a high level language as C / C++ 311, phyton 312, Java 313, Fortran 314, or using framework as OpenCL (Open Computing Language) 315) of the source program code 3 into a quantum processing code 30 as target code by generating the quantum processing code 30 as parallelized quantum processing code 301 comprising a number of sets 3011 of unitary operations 3012. Each set 3011 is executable by one of the plurality of quantum network devices 21 of the parallel processing system 2. The parallelized quantum processing code 301 further comprises control code 302 for controlling the operation of the plurality of quantum network devices 21 and the quantum circuit 2, respectively.

[0416] The synthesis system 11 comprises a parser module 111 for translating the source programming language 31 into an elementary instruction code 32 with a flow of elementary instructions to be processed by the quantum network devices 21. The elementary instructions 32 are selectable by the synthesis system 11 out of a set of elementary instructions 32 comprising elementary arithmetic operations 321 and / or logic operations 322 and / or variable and array declarations operations 323 and / or compare operation instructions 324 and / or control and / or memory operations 325 for the number of the quantum circuit 2.

[0417] The parser module 111 comprises means for partitioning the source program code 32 of elementary instructions 32 into computation block nodes 333, each computation block node 333 consisting of a smallest possible segmentation of a non-further decomposable sequence of elementary instructions of the code 32 processable by a single quantum network devices 21, the smallest possible segmentation of the elementary instructions 32 being characterized by a sequence of elementary instructions framed by consecutive read and write instructions, said sequence being not further decomposable by smaller sequences of elementary instructions between consecutive read and write instructions having a minimal quantum information depth required to process the source program code 32, and the read and write instructions needed to receive data required for processing said sequence of elementary instructions by the quantum network device 21 and transmit back data after processing by the sequence.

[0418] The synthesis system 11 comprises a matrix builder 115 for generating numerical matrices 1151,...,115i out of computation chains 34 portioned from the code 32 by the computation block nodes 333. The numerical matrices 1151,...,115i comprise computation 1151 and transfer matrices 1152. A computation chain 34 is formed by one or more computation block nodes 333 creating an ordered flow of computation block nodes 333 within a row of a numerical matrix 1151,...,115i. Input quantum information 2141 of the computation block nodes 333 of a subsequent column of a numerical matrix 1151,...,115i at least partially depend on output quantum information 2151 of the computation block nodes 333 of the antecedent column. Each computation chain 34 is executed by one quantum network device 21 while the computation block nodes 333 of a column are executed in parallel by the plurality of auto-parallelized quantum network devices 21.

[0419] The computation matrix 1151 contains in each row the computation chain 34 of computational block nodes 333 processed sequentially by a quantum network device 21 with each column having the sequence of elementary instructions of a computation block node 333 within the computation chain 34 of the row and the transfer matrix contains transfer properties associated with a quantum information transfer from one to a consecutive computation block node 333.

[0420] By means of a quantum code generator 17 of the synthesis system 11 a sequence 35 of unitary operation 216 is generated from the elementary instructions 32 of each computation block node 333 and decomposed into a sequence 36 of logic quantum gates 211. The sequence 36 of quantum logic gates 211 process an input quantum state as input quantum information 2141 of a computation block node 333 to a target quantum state as output quantum information 2151. The quantum circuit 2 with the auto-parallelized quantum network devices 21 is provided by a transpiler system 12 of the quantum computing system 1, mapping the decomposed sequence 36 of logic quantum gates 211 with logic qubits 2111to an ensemble of physical quantum gates 212 with physical qubits 2121 / 2122 / 2123.

[0421] Additional physical ancillae qubits 2122 and / or SWAP gates 2123 can e.g. be embedded by the transpiler system 12 until fault-tolerant quantum computing and unitary operation reversibility is achieved. SWAP operations can e.g. be inserted by the transpiler system 12 to provide an appropriate coupling of the physical gates 212 given by the sequence 36 of logic quantum gates 211. The quantum network devices 21 can e.g. be realized by using universal, reversible quantum gates to execute operations within a computation block node 333, the universal quantum gates representing entangled qubits in Fourier-space, the quantum Fourier transform defined by frequencies and amplitudes.

[0422] The r-Turing complete, universal, parallel processing quantum computing system 1 processes the source program code 3 by said control unit 20 based on the sequence of elementary instructions 32 of the computation block nodes 333 of a computation chain 34 and the generated transfer matrices 1152 and / or task matrices 1153.

[0423] As an embodiment variant, the number computational chains 341 consisting of sequential computational block nodes 333 and forming a plurality of parallel quantum processing pipelines corresponds to the maximum number of quantum network devices 21 allocatable on the quantum circuit 2, wherein the quantum circuit 2 comprises the plurality of quantum network devices 21 generated and allocated to a plurality of computational chains 34, wherein position variables represent the location and connectivity of the plurality of physical qubits 212, and wherein a quantum network device 21 is generated for each cycle by a quantum circuit generator from the position variable values of a generated layout of each quantum network device 21.

[0424] (iii) Decomposition in computational block nodes 333 The term "computation block nodes", which group the instructions and entail the communication / transfer data to other computation block nodes, is crucial for the present application. The term "computation block node", as used herein, differ from similar terms, used in the state of the art, though there is no generally recognized meaning.

[0425] The well-known basic blocks (e.g. see Proceedings of a symposium on Compiler optimization; July 1970 Pages 1–19 https: / / doi.org / 10.1145 / 800028.808479) are a central definition in classical Control Flow Graphs (CFG). Simplified, they group statements, which have no jump or jump targets inside. Therefore, with a given input they can perform operations without interruption to the end, respectively to the output. This is a basic concept in compilers today. The definition for basic blocks is also historically targeted for single computation units and very well established. There exist optimization methods for a wide range of problems and it has been shown how they solve different technical problems. But seeing a code with the goal to split the statements to different dependent units (connected e.g. by a shared cache, via bus or network, etc.), this definition lacks in granularity and the classical scope prevent a broader perspective. Scoping the blocks on the bases of any unique information given in a code (see information as a bit-pattern) and combine this scope with the relevant times to compute and transfer of an information in a system, creates a different, but well physical based perspective on a given code. The alternative scope enables new option as well as solves some well-known technical problems of today's SOTA compilers (see following example for a PDE, Fibonacci or pointer disambiguations).

[0426] The term "computation block nodes", used in the present application, bases on a different and not in this way applied important unit in SOTA compilers: the interrelation of transfer and compute time for a given set of statements. These new defined "computation block nodes" group instructions together which use the same information, which is not changed by any other instructions (statements) in any other computation block node during a particular time in the complete code. In this way, they group instruction which can be processed or computed independently of any other statements with the scope on the information (information as a distinct bitpattern), what is called in the present application "not-further splitable instructions chains". These chains of instructions in every computation block node have each a physical based "time" associated how long it takes a unit to process or compute them on a given hardware. As the hardware properties have a fundamental influence (as well as software components, such as OS, drivers, etc.) on the time needed to process or compute the instructions, the "computation block nodes" correlate them also to the time needed to possible transfers of any other information during a particular time - if needed during a particular program step - to another "computation block node" in the complete code. Each "computation block node" knows which and when the information for the own instructions has to be exchanged (communicated / transferred, respectively "received " or "send") to other "computation block nodes". Therefore, a "computation block node", as used in this application, brings a new scope and a decision criterion, meaning one of the central aspects of parallelism of a code, in relation: compute an information (bit-pattern) on a unit or transfer this information to another unit and compute it parallel. This decision can only be done, when it is guaranteed, that the used information is not changed during a particular program step (or time) in any other part of the program. Furthermore, building block nodes with this scope do not only bring advantages to parallelize a given code, this scope also shows some advantages for problems not well handled with SOTA compiler optimization techniques. Such problems and different solutions are well documented, for example, in the publication Modem compiler design by D. Grune. To show the technical benefits, some advantages resulting from using the new scope to some of these known technical problems, is shown below, such as pointer disambiguation and different performances for Fibonacci series codes, but also how the method solves up till now not solvable problems, like PDE parallelization.

[0427] First, the different scope is illustrated with a schematic example in figure 41. The illustration makes some adaption to show easier, what the inventive system and method does, such as the statement 'y > a' would not occur twice in the same computation chain, the resulting "compute" -> "communicate" model would lead to a corresponding placing of a loop, jump or flow-control instruction. Nevertheless the example illustrates, what the different scope of the computation block nodes give compared to basic blocks: the fact that 'a' and 'b' do not change in block 1 and the information of the condition of 'y > a' is already known after the evaluation of the statement 'y:= a*b', the alternative scope of the computation block nodes takes these properties into account. The proposed perspective of computation block nodes groups the statements in a new way together. This change in perspective results from the approach to group operations together, which rest on information, which is not changed at the same time-step in the code. In the example this is shown that two independent computation-chains evolve, which both are independent concerning the information of 'y'.

[0428] The disclosed synthesis process forms out of the flow-graph of computation block nodes, as illustrated in figure 41, two technically defined matrices called "computation matrix" and "transfer matrix". Both are numerical matrices. The "computation matrix" contains the instruction chains and the "transfer matrix" the possible transfer properties (from and to other computation block nodes). Therefore, the code extracted from the matrices always forms a pattern "compute -> communicate", as it is described in more detail in the following passages. If code is mapped to one unit, the communicate part would vanish and the synthesis method would be reduced to the approach with basic blocks, as it is known by SOTA compilers.

[0429] The name "matrices" is used to name a structure of the from (m x n x p), where m, n, p e N0. As m, n and p depend on the code, this can include different forms of a mathematical object, especially concerning dimensions like as a point, vector, a matrix, a tensor, etc., m is the number of the maximal number of computation blocks, respectively block numbers like in Figure 43 the segment-numbers, n is the number of independent, but with the same segment number computation block nodes, like in Figure 43 indicated as chain numbers. Depending on the maximal level of conditions in a code (or series of branch nodes like in Figure 26), p is defined, indicated in Figure 43 as path number. Therefore it could be said, that whenever the term 'matrix' / 'matrices' is used, it can be a vector, a matrix or a tensor or any other object of the form (m x n x p) or with representation in from of a graph or tree. Therefore, optimization can also be done e.g. with one tensor by combining the computation and transfer matrices into one structure, or that a transfer and computation matrix each can be a tensor, or they both can be a vector, in a code with only one block / segment number. The dimension of these "matrices" depend on the form of the code and the way of handling / representing the information in the way the method is applied. The term "numerical matrices", as used herein, can also include forms of text, like for a transfer '1 ->2'.

[0430] Depending on the used optimizing / mapping techniques, the text in the matrices will be or can be reduced to a numerical value (depending on the used character encoding) so they can be e.g. searched or compared. Or the textual transfer '1 ->2' can be represented / encoded by a numerical value from the beginning and directly be compared with other transfers and therefore omitting character encoding. Figures 42, 43 and 44 show a diagram schematically the step of numbering the computation block nodes depending on their call-position in the code, resulting in a pseudo graph like schematically represented in figure 42, which in return results in the computation and transfer matrix for each path number as shown in figures 43 and 44. In the perspective to see a matrix as a m x n object, then there will be created one set of a computation and a transfer matrix per path number, resulting in 2 computation and 2 transfer matrices. The switch of the paths (or conditions) can be seen in figure 45, where the 'True' / 'False' signaling is indicated. Figure 45 shows a diagram illustrating how each row of the computational and transfer matrix together, represents a combination of a chain of instructions and communication entries for one unit. Units are depending on the level of implementation (e.g. bare assembly, threads, processes, compute-nodes, etc.). Obviously empty computation cells or not used communication entries (empty cells in the computation and / or transfer matrices) vanish, as well as start- and endcommunication link together as can be seen in figure 45. This provides the result of combining start- and end-communication cells in the transfer matrix and eliminating empty cells in the computation matrix (for each path) and bring them back to different code segments. Based on this code segments of elementary instructions 35 a quantum processing code 30 / 301 of unitary operations 3012 can be generated by the synthesis system 11. Depending on the synthesis method to implement the communication, nonblocking or blocking mechanisms can be used, as it is guaranteed, that during a computation block node no information will be transferred used in the instructions at the same time, respectively another cbn with same number.

[0431] After parsing the code and adding all instructions to computation block nodes (cbns), each computation block node can be enumerated depending on its position in the flow graph. This leads to a similar form of a Control Flow Graph, given by the edges between the cbns as well as the connection of the defined branch nodes. Using these positioning numbers, the unique positions in the flow of the code is used to place the information of what to compute and what to transfer in the two matrices "computational matrix" and "transfer matrix", the "computational matrix" for the computation and the "transfer matrix" for the transfers. It is obvious that meta data, such as size of the data needed for each cbn, the size of the transfer between the cbn, etc. can easily be derived. Matrices represent a much more scalable form of accessing information than graphs, respective show the well-formed nature of the control flow graph. They are not absolutely essential for the method and this step could also be performed directly on the graph / tree structure. But the definition of the block nodes also indicates the generic nature of the inventive matrices: Each row has an independent flow (dependency by transfers) of instructions (= computations) and needed transfers (= communications) to other cbns. It is guaranteed that a) no further information is needed to compute all instructions in a computation block node (this is similar to a basic block, but the scope of the independencies is quite different), b) the used information is nowhere else changed during the same computation step in the whole code and c) that only information is transferred not affected of computations during this time-step are possible. With this fact, each cell in the computation matrix has all instructions, which can be independently computed concurrent with all instructions in the other cells in the same column. In the transfer matrix in each cell, the needed transfers at the beginning and at the end of each computation step (corresponding cell in the computation matrix) is now known. Getting back code to run on the different units results in a representation in the form "communicate -> compute -> communicate -> compute" and so on. Each row represents a chain of computation and communication properties forming a series of computations coupled by communication with the other rows = chains of computations. The needed information to communicate with the other rows = chains is in the transfer matrix. Each row in the computation matrices (and the same combination in the transfer matrix) can also be combined (compute all instructions of both, combined cells and make the necessary transfers of both cells based on the transfer matrix) with any other row in the matrices to create a new combination of computation <-> transfer behavior of a given code. In this step the computations sum up and transfers on the same unit (by combination) vanish. This will lead later to a simple form of optimization, as well as the fact, that the optimization / mapping step results definitely in a runnable code, as no iterative or similar solution methods are needed. This is also a technical well known-problem parallelizing code, as debugging of parallel code is very complex (for example, see "ParaVis: A Library for Visualizing and Debugging Parallel Applications", A. Danner et al.).

[0432] Each row of the computation matrices, as defined herein, represents a chain of instruction blocks for one quantum network device 21. Obviously empty blocks (empty cells in the computation matrix) or not used communication entries (empty cells or transfer on same units in the transfer matrices) vanish, as well as start- and endcommunication link together as can be seen in figure 45. This results in case there is no transfer if the code is run on a single quantum network device 21 and all transfers will vanish by reassigning / renaming of variables, respectively applying well known optimizing synthesis methods to get on optimized code for a given quantum network device 21.

[0433] The generic, well defined nature of the matrices is the unique base for a wide range of possibilities to map / optimize a source code 3 to a specific quantum computing hardware or evaluate an optimal hardware configuration for a given source code 3. The structure guarantees as a result an executable quantum processing code 301. Each quantum hardware infrastructure has its own performance properties and in combination with the 2 layer approach (logic and physical layer), a modern quantum processing infrastructure can be very complex. The inventive method allows to optimize the source code 3 to a specific quantum processing hardware or allows to give out an ideal hardware design. The most obvious is by building different combination of rows from the computation and the transfer matrix 1151 / 1 152, whereby it is important that in both matrices the same combinations are built. Each combination (e.g. combine row 1 and 2 in computation AND transfer matrix) is then a new version of a parallelized quantum processing code 301 of unitary operations 3012 for the given source code 3 and then its properties on the target quantum infrastructure can be assessed.

[0434] By different combinations of the rows in the matrices (e.g. combine row 1 and 2 in computation and transfer matrix or row 2 and 5) different combinations of computation <-> communication ratios are retrieved. Each of the combinations then can be examined including other known meta-data for a given quantum hardware infrastructure. For example data types of the data nodes can be used to evaluate for hardware properties, such as circuit depth, decomposition properties, or other properties of a target platform. This form of combining and searching for an optimal parallelized quantum processing code 301 of unitary operations 3012 and a given hardware results always in an executable code, because no iterative solution method or similar approach is needed to find a solution in the optimizing step, nor solution with e.g. race-condition, dead-lock, etc. can occur, respectively dead-locks can be detected.

[0435] The grouping of the elementary instruction 35 is based on the inherent physical constraint associated with quantum signal transfer, as e.g.. the collapse of the wave function due the Bell measurement 203 / 2031, the inventive system and method spawns a form of optimal solution space for the most splitable form of a source code 3 and results in a well-defined way and search space for a unique way to find an optimal map for a given quantum processing hardware, or the ideal quantum processing hardware for a given source code 3. This makes this method quite generic and solves the technical problem to adapt a given code to a target quantum platform automatically. Other systems and methods do not exploit the inherent quantum information transfer properties and dependencies given by a source code 3 and do not produce this form of unique solution space to optimize, in the form the method's definition of the computation block nodes (by grouping by the scope of no changing information) - this solves technical problems directly in many ways. The examples in the detailed description will show this in more detail.

[0436] (iv) Relation to the components of the inventive system: Computation Blocks and potential transfers

[0437] For the present invention, the components referred to as Computation Blocks (CB / 333), are again described for the applied quantum computing below (see figure 18). Computation blocks map information 1:1 in a parallelized data space. Each computation block builds exactly one subset of a code to map the input to the output not interrupted by any other operation / instruct. Furthermore, each CB has a distinct data size. This size is defined by the declaration of the variables in the code, respectively by the size of the instructions. Parallel CBs n‖ together define the data size needed to compute the instructions in parallel. This corresponds in the classical perspective to number of bits (e.g. an unsigned integer 16 bit has a resolution of 16bit = uintl 6_t C-type). This parallel information is mapped to state vectors describing states in a quantum computer with qubits. The capacity of a quantum computer is defined by its size of qubits and how well a number of gates can be differentiated (c.f efficiency of gates above). As the inventive system relates the number of parallel Computation Blocks n‖ in the Control Flow Graph (CFG), the number of parallel CBs are getting a function of runtime-variables. This enables to detect boundaries during compile time, when a quantum platform is getting beneficial to compute a number of parallel CBs in contrast to classical platforms.

[0438] The number of parallel Computation Blocks ny together with the resolution of the corresponding data, respectively instructions, defines needed bit-sizes, respectively number of states and therefore number of qubits. Number of parallel bit information = 2nstates by n-qubits. The parallel information depths further define also the needed number of ancilla registers per computation block.

[0439] A computation block (CB) contains instructions for arithmetic or logical operations. Parallel CBs in a loop contain the same instructions. Some classical gates are universal gates, e.g. the NAND gate. But a quantum circuit must be additionally reversible, what makes it more complicated to directly transpile from classical circuits to quantum circuits. As described above, it is possible to create from a classical circuit a reversible unitary operator, which can be applied to quantum states. However, this can include many additional registers / qubits to preserve the results of the circuit to be able to reverse the states. Manipulating single entangled qubits is complex, as they influence the other qubits which are in superposition. There are known universal Quantum gates, as described above. One option is to use Quantum Fourier Transformation (QFT), and to represent the entangled qubits in form of frequency and amplitude. This enables to represent arithmetic operations in a more generic form. On the other hand, similar solution in the form of an Instruction Set Architecture can also be applied.

[0440] Below, an approach is introduced how the inventive system can form from the set of universal quantum logical gates for an input code using Quantum Fourier Transformation (QFT) / Approximate Quantum Fourier Transform (AQFT) an efficient quantum circuit automatically and without interaction with developers. This is like creating a code custom quantum circuit containing quantum blocks (1 quantum block is 1 computation block with granularity G0).

[0441] Each CB has a series of arithmetic operations using the transfer-in data points to compute a transfer-out data information. This is critical to form reversible and efficient quantum circuits.

[0442] In quantum computing the information is parallel available, what in classical computing platforms has to be transferred. In case of a quantum computing platform, the transfers indicate the dependencies between different quantum states and not a transfer of information. These transfers have now to be interpreted along the instructions in the Computation Blocks, meaning the transfer-in data is used in an instruction within the Computation Block, which can be interpreted as a controlled-linked between the source qubit and the target qubit. In this form a 1-qubic-quantum gate can be combined by a controlled-gate (such as the controlled-CNOT, or a Controlled-Z) and combined e.g. with a Pauli or a Phase gateway. Thus, transfers of the inventive system must be interpreted as controlled links to states of qubits in superposition of other CBs. In this form, the transfer acts on the source (controlled-2-qubit-gate) with the arithmetic computation (instruction in the Computation Block) forcing on the target, entangled qubit 1 -qubit gate.

[0443] ( ) Practical applications

[0444] Based on the above discussed information, the inventive system extracts for compiled and interpreted languages the needed information to form an efficient quantum circuit, e.g. for loop-sections:

[0445] 1. Number of parallel states for sections with high parallelism in code. This n,| parallel Computation Blocks with defined data / instruction sizes define the number of n- qubits (where n-qubits build 2nstates, which can be interpreted as classical bits). Depending on the approach to build the quantum circuits the needed qubits can be derived to spawn the states needed to compute the ny parallel Computation Blocks. Furthermore, they can be used to define the number of needed ancilla- registers.

[0446] 2. Measuring: Measuring quantum states lets collapse the superposition. The inventive system allows to know the state to measure and how these can be reached by the code with minimal parallel computation blocks (minimal information mapping only once an input data set to an output data set, which is the key to reversibility).

[0447] 3. Compiling operations from high programming languages reversible with state-of- the-art methods to efficient quantum circuits. This is possible by deriving from the defined sequential instructions series in each CB to quantum circuits composed of universal unitary quantum gates. One approach is to transform the states into Fourier states (e.g. using QFT / AQFT). Then the classical operations are mapped into combinations of controlled-gates (e.g. Controlled not) and rotations on the Block sphere, such as Pauli-X / -Y or -Z gates. This enables to formulate any classical arithmetic operations generically to quantum circuits, as the arithmetic logic operations getting rotations about the axis on the Bloch sphere in superposition.

[0448] 4. Define the number of ancilla registers, which are transformed into QFT, enabling to apply the CBs-arithmetic and logic computations. The reversable, conjugate operator Matrix for the QFT is known and can be applied to the corresponding ancilla registers.

[0449] 5. Define ancilla registers to measure, meaning extract target values, e.g. point for a 2d heat equation after time t. This ancilla register can be measured and "linked" to the target quantum state known from the QFT.

[0450] The present inventive system, thus, allows technically to create quantum computing circuits and corresponding quantum code for running the quantum circuits from a processing code written in a generic, high programing language without any annotation or other hints by programmers. The inventive system transforms code from intermediate representation or opcode from an interpreted language into Computation Blocks instead of Basic Blocks in a Control Flow Graph (CFG), (see figure 19).

[0451] In each node of the control flow graph, parallel and sequential Computation Blocks (CB) are known using the inventive system. The parallel CBs spawn a defined representation of the data as bits or states for each node in the Control Flow Graph and - depending on code - as a function of runtime-variables.

[0452] Loop sections can contain high parallelism. The inventive system extracts the number of parallel CBs with a novel extend, using the Read-after-Read data dependencies by building e.g. the index distance vector of statements. Figure 20 shows a number n,, of parallel Computations in loops with the same computations / instructions' series spawning a bit-size Scompute CBII.

[0453] This size Scompute CB|| defines the needed number of states. In contrast to classical computing, there exist no quantum memory (at least not for the foreseeable future), therefore all information used in the computing must be represented in the states. In classical computing the needed memory size is often realized by dynamic memory, which defines the memory spaces based on runtime-variables. This information can be used to define the needed quantum states to represent the problem computed in a target loop section. The information is illustrated in the following figure 21. Id est, from a code in Control Flow Graph (CFG) with Basic Blocks (BB), the inventive system can generate a gamma-graph with 4 phases, describing the parallel / distributed computation of the loop sections including needed data transfers (see figure 21): (1) Initialization: data from CBs before the loop have to be distributed to all parallel CBs

[0454]

[0455] (2) Computing: each unit computes one (or more) of the ny CBs iteration-by-iteration for nIoopiteration to complete the loop section; (3) Inter-loop transfer & gap / boundary transfers: Needed transfer between the units must be communicated / synchronized for each iteration between the n,, CBs and data, e.g. from gap in nested loop-definitions, have to be loaded to the units; and (4) Result: After computing nioopiterations, the results have to be transferred (not in any case!) to the main process, respectively to CBs after the loop. Each node in the gamma-graph represents a Computation Block (CB) and the edges represent potential transfers.

[0456] In classical computing, data must be available in memory to be addressed by a processor. This must be defined before the loop in one of the Basic Blocks and is available during runtime, respectively the corresponding runtime-variables defining the dynamic memory. The size dependencies from the run-time variables can be extracted during compile-time. The inventive system then extracts: (a) The complete data space covering a parallel problem computed within loop-sections. This corresponds with the memory size allocated in classical computing. This influences the ancilla register sizes in quantum computing; and (b) Extracting the information depth spawn in the loop by the H|| Computation Blocks. This is the region needed to cover with ancilla registers. One approach is to use these registers to reflect these states in Fourier space and this enables to implement generic arithmetic and logical operations from high programming languages in a generic way.

[0457] (vi) Quantum Fourier Transformation (QFT)

[0458] The classical Fourier Transformation (DFT) transfers an input-vector (x0, •••. Xjv- JeC1' by a transform function:

[0459]

[0460] A corresponding back-transformation is defined accordingly. Applying this concept to the quantum states, the so-called Quantum Fourier Transform can be formulated. This transforms the quantum states |ψ⟩ = Σᵢ αᵢ|i⟩ in the form that the output is another quantum state |y⟩ = Σᵢ yᵢ|i⟩ with:

[0461]

[0462] with N = 2n.

[0463] By discussing QFT, for clarity, also its classical counterpart is discussed: the discrete Fourier transform (DFT), which is the inverse operation of the QFT, i.e.. QFT with negative exponent:

[0464]

[0465] In other words, Quantum Fourier Transform (QFT) circuits are defined within this patent application to operate a linear transformation on quantum bits, and are the quantum analogue of the Discrete Fourier Transform (DFT), mentioned above. It is worth to mention, that Quantum Fourier Transform operation is a part of many quantum algorithms, as e.g. Shor's algorithm, for factoring and computing a discrete logarithm, a quantum phase estimation algorithm for estimating the eigenvalues of a unitary operator, and algorithms for the hidden subgroup problem. With small modifications to the QFT circuit, it can also be used for performing fast integer arithmetic operations such as addition and multiplication

[0466] In this context, QFT can also be seen as a unitary matrix acting on a quantum state vector. This can be implemented with the Hadamard gate and the phase gate Rkwhat results in a quantum circuit, as illustrated by figure 22. Hadamard gates transform state |0) and |1) in super positioned states. This gates maps the computational basis states:

[0467]

[0468]

[0469] And it is self-inverse:

[0470]

[0471] In compact form the QFT of a quantum state vector |x1x2···xn⟩:

[0472]

[0473] This needsn·(n+1) / 2gates / elementary operations and shows that the QFT can be performed efficiently. To represent a number in binary form with n-qubit - the numbers can go from 0 to 2n- 1 what can be expressed as a multi-qubit state:

[0474] l"i> = l<7o<7i •" <7n-i>

[0475] Then the decimal number is defined as:

[0476]

[0477] And as an example:

[0478] 6 = |110⟩ = 1 · 22+ 1 · 21+ 1 · 20

[0479] From this follows, that when applying QFT to the state vector for n-qubit to represent the number m, then the y-th qubit will have a phase (see figure 23):

[0480] θj=

[0481]

[0482] It is to be noted that using Approximate Quantum Fourier Transform (AQFT), the demand of gates to build the QFT can be lowered. In this case periodical phase shifts can be exploited to reduce the number of needed operations L on m qubit register by

[0483]

[0484] which is a reduction to the QFT. Critical for a compiler approach to make it possible to compile especially loop-sections from higher programming languages directly to quantum gates, is to have efficient implementation of arithmetic and logic operations. For building quantum circuits, different approaches can be used:

[0485] • Using direct transfer from classical gates, which can lead to a massive overhead for the needed ancilla-registers.

[0486] • Introducing an Instruction Set Architecture (ISA).

[0487] • Using QFT or AQFT.

[0488] The inventive system 1 can be used to build a compiler system, i.e. a synthesis and transpiler system, transforming high programming languages to practical and efficient quantum circuits automatically forming an appropriate set of universal quantum gates to process a desired source code 3 on quantum level. A source code 3 is segmented by the inventive system to n,, computation block 333 per code step. The operations in these segments must be reversible what requires corresponding ancilla-registers. One possible transfer from the operations in the computation blocks to quantum circuits is to use prior art systems allowing to express code from arithmetic / logic operations from unsigned and signed inter to floating-point arithmetic on quantum circuits. The same approach can e.g. be used with the inventive system and demonstrated along the two heat equation implementation to build an efficient quantum circuit 2 for the parallel execution of the computations in the loop (see below "application example: 2-dimensional heat equation).

[0489] (vii) Comments to physical and logical qubits

[0490] As discussed above, one logical qubit can consist of several physical qubits for error prevention and enables a fault-tolerant quantum computing. To be able to use directly physical qubits the error rates must decay drastically. Therefore, today logical qubits rely on the use of up to several hundreds of physical qubits to get a useable qubit for quantum computing. Most prior art systems, at the time of applying for the present patent application, have increased to 10 to 20 logic qubits in quantum volume, which is a measure of the computational capability of quantum circuits and implicitly includes the number of qubits, their connectivity and gate fidelity. This still small numbers are due to the known noisy intermediate-scale quantum devices are not robust against noise and error, which makes the outcome form a quantum processing being in general unreliable for larger numbers of qubits. As described, the quantum network devices 21 of the present quantum computing system 1 which have a minimal circuit depth however building highly parallelized network of non-local quantum processing units, can even be realized as shallow quantum network devices 21 (i.e. by a constant minimal circuit depth), not being restricted by its application through the limitation given by the maximum numbers of logic qubits, as other prior art systems do. Thus, the present invention provides a r-Turing complete, programmable quantum system 1 and processor based on synthesis and transpiler hardware-efficient control over logic qubits 211. The central aspect of the logic core of the present inventive system 1 is the minimization and control of individual logic qubits 211 in connection with the highest possible parallelization, instead of focusing on the control of physical qubits 2121. In the context of the present inventive system 1 for quantum computing, this makes a difference, since as starting point for the invention, qubits are used as a fundamental unit of information independently if a qubit is a logical qubit consisting of a cluster of physical qubits.

[0491] To realize the quantum network devices 21 by physical qubits 2121, there exist different technical approaches at the moment, resulting in different development and manufacturing of quantum circuits 2 and qubits 211. Exemplarily, just 5 of the most common approaches shall be mentioned here: (i) A common type of quantum circuit is a superconducting qubit quantum computer. Usually made from superconducting materials, these quantum computers utilize tiny electrical circuits to produce and manipulate the physical qubits 2121. When using superconducting qubits, gate operations can be performed quickly. Companies manufacturing superconducting quantum computers include Google, IBM, IQM and Rigetti Computing; (ii) Photonic quantum circuits use photons (particles of light) to carry and process quantum information, and there are some variations and complexity to how this works. For large-scale quantum computers, photonic qubits are an alternative to trapped ions and neutral atoms that require cryogenic or laser cooling. There are various companies working with photonic quantum computing technology including Xanadu, ORCA Computing, Quantum Computing Inc and PsiQuantum; (iii) Neutral atoms quantum processing circuits are based on neutral atoms involving atoms suspended in an ultrahigh vacuum by arrays of tightly focused laser beams called optical tweezers, though not all neutral atom approaches use optical tweezers. Neutral atom quantum circuits are less sensitive to stray electric fields, which makes them a good option for quantum processors. A number of companies work with neutral (cold) atom quantum computing technology include Pasqal (merged with Qu& Co), Atom Computing, ColdQuanta, and QuEra; (iv) Trapped ions quantum circuits involve using atoms or molecules with a net electrical charge (ions) that are trapped and manipulated using electric and magnetic fields to store and process quantum information. As trapped ions can be isolated from their environment, they are useful for precision measurements and other applications requiring high levels of stability and control. Also, the qubits can remain in a superposition state for a long time before becoming decoherent.

[0492] Companies manufacturing trapped ions quantum circuits are e.g. Quantinuum, lonQ, Quantum Factory, Alpine Quantum Technologies, eleQtron amongst others; (v) Quantum dots quantum circuits use silicon qubits made up of pairs of quantum dots. In this approach, such coupled quantum dots are used as robust quantum bits, or qubits. Companies in this area include Diraq, Siquance and Quantum Motion.

[0493] It is to be noted that there exist also other technical approaches for quantum computing hardware including electrons on helium, NV diamond and the topological approach. However, it is fundamental to understand that the present inventive system 1 provides a quantum computing circuit structure, which is independent from the physical realization of the physical qubits and the corresponding approach, as exemplarily described above. The quantum network device 21 can be realized with all of the available technical approaches and physical quantum computing hardware.

[0494] Further it is to be noted that critical for quantum circuits 2 is the number of needed qubits 211 / 212. The most efficient quantum circuit 2 does not minimize the error in the output, rather it minimizes the resources required for obtaining the same output. However, the present inventive system 1 allows to go beyond that, since the real technical challenge is: given a definable net error tolerance (suitable for a problem to be solved), what is the minimum number of gates needed to build the quantum circuit 2, it est the quantum network device 21. By providing minimal-possible circuit depth 217 by the inventive, no further decomposable, computational block nodes 211, the inventive quantum system 1 with it quantum processing units at a minimum circuit depth allows to provide a quantum circuit 2, which is able to process quantum information, thereby keeping the net error tolerance under a definable threshold value. A further technical challenge is that, on one side, quantum operations must be reversible, and, on the other side, measurements are not reversible. With other words, the problem is to form reversible circuits for a given problem by only measuring these results, which are needed, since otherwise the wave function of the circuit collapses and information is lost making the circuit irreversible. Thus, measuring a value collapses the superposition of the system and erases therefore the beneficial of entangled qubits. When building reversible circuits, there was a long time the prejudice, that all interims results have to be kept, i.e. it was believed that the only way to simulate an irreversible computation on a reversible Turing machine was to keep all the intermediate calculations. Consequently, the size of the memory (i.e., the space) needed to perform the computation reversibly was proportional to the time (i.e., number of steps) of the corresponding irreversible computation. However, Bennett, proved that the history of a reversible computation can be cleared in a reversible manner, leaving only the input and the output in memory, and recording the configuration of certain check-points of the irreversible computations. The inventive system parallel segments, i.e. computational block nodes 333, can be seen as such check-points, overcoming this technical problem.

[0495] A further critical point is that any n-bit reversible gate must specify how to map each distinct bit string input into a distinct bit string output of the same length. Thus no two inputs are allowed to be mapped to the same output and vice versa. This ensures the mapping is reversible. This is exactly what the inventive system's graph / matrix in granularity Goprovides with its consequently read and write analysis. Each Computation Block writes 1 output state and therefor maps the input-information to the output-information. The potential transfers define the dependencies between the states between two columns of parallel computation blocks n,,.

[0496] (viii) Building custom quantum circuits from Computation Blocks

[0497] The present inventive system provides fully automatically building of quantum blocks, which consist of efficient quantum circuits with minimal ancilla-registers for the needed instructions in the computation blocks. Below, it is disclosed, how the inventive system's segments can be used for the fully automatically building of the quantum blocks: • The segments are specifying the needed ancilla registers to make the circuits reversible

[0498] • The segments are needed for the quantum circuits for a series of instructions from a given code

[0499] • The segments are used by implementing arithmetic / logical operations efficiently from the state-of-the-art set of universal gates by transform in the amplitude and frequency space of Fourier space • The segments are only specifying / measuring the target states, respectively use ancilla register to not collapsing the superposition of the (sub-)systems.

[0500] For this, the following paragraphs disclose how a custom quantum block can be specified with needed ancilla registers from a Computation Block:

[0501] (a) Defining states from Computation Blocks

[0502] Programming languages define data sizes for variables and instructions. The binary representation of a variable can be expressed in its value as a Semi-Boolean-polynomial:

[0503]

[0504] For an example a 4-bit unsigned integer (C-type uint4_t) can be represented with resolution m as:

[0505] ma= a1· 20+ a2· 21+ ··· + am· 2m

[0506] A computation block defines by the in-transfers and the out-transfers the corresponding states needed to represent the defined variables (and instructions), as illustrated by figure 24.

[0507] (b) Defining arithmetic / logical operations Using the QFT or the AQFT it is possible to derive generically arithmetic and logic operations into the Fourier-space and the phases become additive. For example, for an addition of two variables in a Computation Block the quantum circuit can be derived, as illustrated by figure 25.

[0508] This can then be extended to generate quantum blocks with a given input, defined by the transfers into the Computation Blocks with the size Sread(representable as a binary string) and resulting with the transfer out, defining the resolution Swrite. Depending on whether an input-register are needed later in the code, their superposition can be preserved as in the above example using ancilla-registers.

[0509] Alternatively, the input-registers can be used for the computation by applying the QFT directly to their input states and used to produce the target states, as illustrated by figure 26.

[0510] For a generic form of building quantum blocks from Computation Blocks, the ancilla-registers can be inverted with their input and the output of the quantum block can then again be used for a following quantum block / Computation Block (see example in figure 27). In this form it is possible to build quantum blocks from Computation Blocks in the form illustrated in figure 28. This enables to reuse the ancilla-registers in following Computation Blocks, respectively quantum blocks. In this form the present inventive system enables to generate the minimal form of ancilla-registers over the complete code.

[0511] (c) Defining ancilla states

[0512] It is interesting in the graph of the present inventive system that the minimal ancilla-register can be specified and re-used after inverting the applied gates. This enables over a code to specify the minimal number of needed ancilla-registers. Figure 29 illustrates exemplarily the graph given by the inventive system for a simple, only exemplary code. Forming for each of the computation blocks, it is generically possible to generate quantum blocks with corresponding ancilla-registers and reflecting by phase-shifts the arithmetic and logical operations defined in the CBs. In the last quantum block the inverse operations can be neglected resulting in the target value, which then can be measured (see |x5) in figure 30). To compute this function the ancilla register from the first CB can be reused in the last CB. Two cases have to be distinguished, both need a different number of ancilla-registers:

[0513] a) When the input registers are still need in later computation blocks / quantum blocks, then the ancilla-register can be "reversed" after the computed states are used. This indicate that over two side by side inventive system's-columns / graph-levels enough ancilla-register must be available:

[0514] ^ancilla ^||, A "I" ^||, B

[0515] b) One of the input states is no longer needed and can be used to reverse the ancilla-registers and we result in:

[0516]

[0517] The case b) can be especially interesting for loop-sections, where massive parallel opportunities can arise, respectively the inter-loop communication is often the limiting case.

[0518] (ix) Application example: 2-dimensional heat equation

[0519] The inventive system enables to retrieve the number of parallel computation blocks n,| from the statement in a serial programmed code as illustrated in figure 33.

[0520] The size Swrite= tfdefines the number of needed ancilla-registers, meaning qubits m. The operation in the computation block defines the unitary transformation. By first transfer the ancilla-register in the Fourier states, it is possible to generically transpile the operation into the correlated phase shifts. This results in a corresponding quantum block, as exemplarily illustrated by figure 34. In other words, the inventive system enables to generate a basic quantum block for the parallel computation blocks in a loop. Each CB has the same statement, as illustrated in figure 35. This enables for a given resolution of the mesh nxand nyto create an efficient quantum circuit. Each parallel CB gets the same quantum block, as illustrated in the above figure 35. After the first iteration (see initialization phase above) in the second loop-internal, transfers dominate which can be illustrated by figure 36. These transfers define the controlled link between the states as a function of the runtime-variables nxand ny. The benefit of the above defined quantum blocks with ancilla-registers, reversed after the computation, is that they are available in the following iteration over the special extend of the problem. How this looks for a mesh with nx= 5 and ny= 4 is visible in figure 37. For visibility only for the first CB the link to the initial states is shown in figure 37. The yellow marks a potential measurement point to get the value of a target point at coordinates x and y after time t + 2 ■ tk.

[0521] It can be assumed, that there will come up further solution to form efficient quantum circuits from universal quantum gates, not only the used approach in this patent application with QFT. Analogously to possible methods for reducing time latencies in classical circuits, this means solutions using less gates. In this case the QFT can be produced once and then mirrored on different other groups, which would be very suitable for parallel computation blocks.

[0522] However, inventive system's technical "read" and "wrife'-approach enables to form parallel code's having minimal size to compute a given code in parallel. These segments (herein referred to as Computational Blocks (CB)) show the smallest segment, which describe an input to output map without any duplication. This is the key requirement for reversibility what enables the inventive system to fully-automatable compilating an input code to a quantum platform. This provides a unique solution to the challenges mentioned above (see critical issues and challenges to build efficient quantum circuits).

[0523] Thus, the patent application discloses a novel generic, r-Turing complete, universal quantum computing system 1, quantum circuit 2 and / or processor design system, i.e. a complete generic quantum computer. As an embodiment variant, the disclosed quantum circuit 2 and / or reversible quantum network devices 21 can be realized garbage free and can be enabled to use reversible updates to combine the standard reversible arithmetic and logical operations in one unit. Combined with a suitable control unit 20, the disclosed quantum circuit 2 permits the construction of a r-Turing complete quantum computing device programmable in a high-level programming language 31, as e.g. C / C++ 311, phyton 312, Java 313, Fortran 314, and / or OpenCL (Open Computing Language) 315. The different quantum network devices 21 and computational block nodes 333, respectively, disclosed can rely for their Boolean parts only on elementary reversible gates for five basic arithmetic-logical operations 32 on two n-bit operands. The single quantum circuits or quantum arithmetic logic units rely only on a minimal number of ancillae (if at all), allowing a unique low resource consumption. The inventive r-Turin complete quantum circuit design has, inter alia, the advantage that it, as described above, allows to formulate codes to any problem occurring using a high level language and synthesis and transpile it to corresponding quantum processing code 30 and quantum network devices 21 as quantum processing units, where the quantum processing code 30 is processable by the inventive generic r-Turing complete, universal quantum computing system 1 and quantum network devices 21. List of reference signs

[0524] 1 r-Turing complete, universal quantum computing system

[0525] 11 Synthesis system

[0526] 111 Lexer / Parser

[0527] 112 Analyzer

[0528] 113 Quantum program scheduler

[0529] 114 Computational block chains module

[0530] 115 Matrix builder

[0531] 1151 Computation matrices

[0532] 1152 Transfer matrices

[0533] 1153 Task matrices

[0534] 116 Optimizer module

[0535] 117 Code generator

[0536] 12 Transpiler system

[0537] 2 Auto-parallelized quantum circuit

[0538] 20 Control unit

[0539] 201 Clock

[0540] 2011 Clock cycle

[0541] 202 Processing of sets of parallelized quantum processing code 30 / 301 by processing cycles

[0542] 203 Measuring device

[0543] 2031 Measured collapsed wave function of the corresponding quantum network device 21

[0544] 204 Error measuring device

[0545] 2041 Error rate e

[0546] 21 Quantum network devices (Quantum Processing Units (QPU))

[0547] 211 Quantum logic gates

[0548] 2111 Logic qubits

[0549] 212 Quantum physical gates

[0550] 2121 Physical qubits

[0551] 2122 Ancillary qubits

[0552] 2123 SWAP gates

[0553] 213 Quantum entanglements

[0554] 214 Input quantum register

[0555] 2141 Input quantum information signal 215 Output quantum register

[0556] 2151 Output quantum information signal

[0557] 216 Unitary operations

[0558] 217 Quantum circuit depth of a quantum network device 21

[0559] 218 SWAP registers

[0560] Program code

[0561] 0 Quantum processing code

[0562] 301 Parallelized quantum processing code of unitary operations 3011 Parallel sets of unitary operations

[0563] 3012 Unitary operations

[0564] 302 Control code

[0565] 1 High level language

[0566] 311 C / C++

[0567] 312 phyton

[0568] 313 Java

[0569] 314 Fortran

[0570] 315 OpenCL (Open Computing Language) framework

[0571] 2 Elementary instructions

[0572] 321 Arithmetic operation instructions

[0573] 322 Logical operation instructions

[0574] 323 Variable and array declarations operations

[0575] 324 Compare operation instructions

[0576] 325 Code flow instructions / Memory operation / l / O operation

[0577] 3 Nodes

[0578] 331 Data nodes (holding certain data values)

[0579] 3311 Input data node for READ (Datanodein (read access)) 3312 Output data node for WRITE (Datanodeout, write access)) 332 Operation nodes (performing an operation)

[0580] 333 Computation block nodes (CB1, CB2 CBx)

[0581] 3331 Quantum information depth of a computation block node 334 Control flow nodes

[0582] 3341 Branch nodes

[0583] 3342 Hidden branch nodes

[0584] 3343 Loop branch nodes

[0585] 335 Condition nodes

[0586] 4 Chains 341 Computational chains (chains of computation block nodes) 342 Operational chains (chains of operation nodes)

[0587] 35 Sequence of unitary operation 216 representing the elementary instructions 32 of a computation block node 333

[0588] 36 Sequence of logic quantum gates 211

[0589] Network

[0590] 41 Network controller

Claims

1. Claims1. A r-Turing complete, universal quantum computing system (1), the quantum computing system (1) comprising a quantum circuit (2) being composed of a plurality of auto-parallelized quantum network devices (21), wherein each quantum network device (21) comprises one or more quantum logic gates (211) providing computations steps by one or more unitary operations (30), each quantum network device (21) being synchronized in time, wherein a quantum logic gate (211) is a device performing a fixed unitary operation (30) on an ensemble of logic qubits (2111) correlated by quantum entanglements (213), wherein for each quantum network device (21) one or more logic qubits (2111) form an input quantum register (214) to the respective quantum network device (21) and one or more logic qubits (2111) form an output quantum register (215) to the respective quantum network device (21), an output quantum information signal (2151) of an output quantum register (215) being at least partially transferable to an input quantum register (214) of another quantum network device (21) as input quantum information signal (2141) by a control unit (20), and the quantum network devices (21) performing the one or more unitary operations (30) as computational steps processed by its quantum logic gates (2111) synchronously and in parallel within one clock cycle (201), characterized3.in that the universal quantum computing system (1) comprises a synthesis system (11) for synthesizing and auto-parallelization of a source program code (3) in a source programming language (31) for execution by the quantum network devices (21) by translating the source programming language (31) of the source program code (3) into a quantum processing code (30) as target code by generating the quantum processing code (30) as parallelized quantum processing code (301) comprising a number of sets (3011) of unitary operations (3012), each set (3011) executable by one of the plurality of quantum network devices (21) of the parallel processing system (2), and / or comprising control code (302) for controlling the operation of the plurality of quantum network devices (21) and the quantum circuit (2), respectively;4.in that the synthesis system (11) comprises a parser module (111) for translating the source programming language (31) into a elementary instruction code (32) with a flow of elementary instructions (32) to be processed by the quantum network devices (21), the elementary instructions (32) selectable by the synthesis system (11) out of a set of elementary instructions comprising elementary arithmetic operations (321) and / or logic operations (322) and / or variable and array declarations operations (323) and / or compare operation instructions (324) and / or control and / or memory operations (325) for the number of the quantum circuit (2);5.in that the parser module (111) comprises means for partitioning the source program code (32) of elementary instructions into computation block nodes (333), each computation block node (333) consisting of a smallest possible segmentation of a non-further decomposable sequence of elementary instructions of the code (32) processable by a single quantum network devices (21), the smallest possible segmentation of the elementary instructions being characterized by a sequence of elementary instructions framed by consecutive read and write instructions, said sequence being not further decomposable by smaller sequences of elementary instructions between consecutive read and write instructions having a minimal quantum information depth required to process the source program code (32), and the read and write instructions needed to receive data required for processing said sequence of elementary instructions by the quantum network device (21) and transmit back data after processing by the sequence;6.in that the synthesis system (11) comprises a matrix builder (115) for generating numerical matrices (1151 115i) out of computation chains (34) portioned from the code (32) by the computation block nodes (333), the numerical matrices (1151 115i) comprising computation and transfer matrices, wherein a computation chain (34) is formed by one or more computation block nodes (333) creating an ordered flow of computation block nodes (333) within a row of a numerical matrix (1151 115i), wherein input quantum information (2141) of the computation block nodes (333) of a subsequent column of a numerical matrix (1151 115i) at least partially depend on output quantum information (2151) of the computation block nodes (333) of the antecedent column, and wherein each computation chain (34) is executed by one quantum network device (21) while the computation block nodes (333) of a column are executed in parallel by the plurality of auto-parallelized quantum network devices (21),7.in that the computation matrix (1151) contains in each row the computation chain (34) of a quantum network device (21) with each column having the sequence of elementary instructions (32) of a computation block node (333) within the computation chain (34) of the row and the transfer matrix contains transfer no8.properties associated with a quantum information transfer from one to a consecutive computation block node (333),9.in that by means of a quantum code generator (17) of the synthesis system (11) a sequence (35) of unitary operation (216) is generated from the elementary instructions (32) of each computation block node (333) and decomposed into a sequence (36) of logic quantum gates (211), the sequence (36) of quantum logic gates (211) processing an input quantum state as input quantum information (2141) of a computation block node (333) to a target quantum state as output quantum information (2151),10.in that the quantum circuit (2) with the auto-parallelized quantum network devices (21) is provided by a transpiler system (12) of the quantum computing system (1), mapping the decomposed sequence (36) of logic quantum gates (211) with logic qubits (2111) to an ensemble of physical quantum gates (212) with physical qubits (2121 / 2122 / 2123), and11.in that the r-Turing complete, universal, parallel processing quantum computing system (1) processes the source program code (3) by said control unit (20) based on the sequence of elementary instructions of the computation block nodes (333) of a computation chain (34) and the generated transfer matrices.

2. A r-Turing complete, universal, parallel processing quantum computing system (1) according to claim 1, characterized in that additional physical ancillae qubits (2122) and / or SWAP gates (2123) are embedded by the transpiler system (12) until fault-tolerant quantum computing and unitary operation reversibility is achieved.

3. A r-Turing complete, universal, parallel processing quantum computing system ( 1 ) according to one of the claims 1 or 2, characterized in that swap operations are inserted by the transpiler system (12) to provide an appropriate coupling of the physical gates (212) given by the sequence (36) of logic quantum gates (211).

4. A r-Turing complete, universal, parallel processing quantum computing system (1) according to one of the claims 1 to 3, characterized in that the quantum network devices (21) consist of universal, reversible quantum gates to execute operations within a computation block node (333), the universal quantum gatesI l l15.representing entangled qubits in Fourier-space, the quantum Fourier transform defined by frequencies and amplitudes.

5. A r-Turing complete, universal, parallel processing quantum computing system (1) according to one of the claims 1 to 4, characterized in that, the number computational chains (341) consisting of sequential computational block nodes (333) and forming a plurality of parallel quantum processing pipelines corresponds to the maximum number of quantum network devices (21) allocatable on the quantum circuit (2), wherein the quantum circuit (2) comprises the plurality of quantum network devices (21) generated and allocated to a plurality of computational chains (34), wherein position variables represent the location and connectivity of the plurality of physical qubits (212), and wherein a quantum network device (21) is generated for each cycle by a quantum circuit generator from the position variable values of a generated layout of each quantum network device (21).

6. A r-Turing complete, universal, parallel processing quantum computing system (1) according to one of the claims 1 to 5, characterized in that the averaged number of elementary instructions 32 in a computational block node 333 is between 3 and 5 elementary instructions 32 having a maximum at 7 to 11 elementary instructions 32.

7. A r-Turing complete, universal, parallel processing quantum computing system (1) according to one of the claims 1 to 6, characterized in that the processing of a computational block node (333) by the quantum network device (21) consists of (a) an initialization stage in which the quantum network device (21) is prepared in the n-qubit computational basis state, (b)a processing stage in which the sequence (35) of unitary gates (216) of the quantum network device (21 ) is applied, and (c) a read-out stage in which the result of the quantum information processing is read out by measuring (203 / 2031) the quantum output register (215) of the quantum network device (2) as sub-set of the qubits of the quantum network device (21).

8. A r-Turing complete, universal, parallel processing quantum computing system (1) according to claim 7, characterized in that a Bell measuring (203 / 2031) is performed before initializing the quantum network devices 21 to perform the next quantum processing step given by the subsequent computational block nodes (333) of the corresponding column of the computation matrix (1151).

9. A r-Turing complete, universal, parallel processing quantum computing system (1) according to one of the claims 1 to 8, characterized in that at least some of the quantum network devices 21 are used as SWAP registers (218) holding intermediate results during a processing cycle and have to be restored to their initial state by decomputing intermediate results before the quantum information (2151) measured at the output register (215) leaves the quantum network device (21).

10. A r-Turing complete, universal, parallel processing quantum computing system (1) according to claim 9, characterized in that the SWAP registers (218) are realized by processing the input quantum information signal (2141) of the input quantum register (214) within the quantum network device (21) at least by two times applying Hadamard gates by performing a 2π rotation about the (x̂ + ẑ) / √2 at the Bloch sphere.

11. A r-Turing complete, universal, parallel processing quantum computing system (1) according to one of the claims 1 to 10, characterized in that the computational block nodes (333) of 2 or more columns in the computation matrix (1151) are linked having a coherent, connected wave function, wherein for linked computational block nodes 333 having a multi-dependency on more than one preceding computational block nodes 333, the preceding computational block nodes 333 are multiplied by its number of dependencies providing for each dependency a separate quantum network device 12.

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